CY91F463NCPMC-GS-P02UJE1

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY91F463NA/F463NC/V460A FR60, CY91460N Series, 32-bit Microcontroller Datasheet CY91F463NA is a line of the general-purpose 32-bit RISC microcontrollers designed for embedded control applications which require high-speed real-time processing, such as consumer devices and on-board vehicle systems. CY91F463NA uses the FR60 CPU which is compatible with the FR CPUs. CY91F463NA contains the LIN-USART and CAN controllers. Note: CY91F463NC improved the features of CY91F463NA and updated the sector map for the flash memory. Please select CY91F463NC for the future development. Features FR60 CPU ■ 32-bit RISC, load/store architecture, five-stage pipeline ■ Maximum operating frequency: 80 MHz (oscillator frequency: 4 MHz; oscillator frequency multiplier: 20 (PLL clock  multiplication method)) Addressing mode specifies full 32-bit addresses (increment/decrement/fixed) Transfer mode (burst transfer/step transfer/block transfer) Transfer data size selectable from 8/16/32-bit ■ 16-bit fixed-length instructions (basic instructions) Multi-byte transfer capable (by programs) ■ Instruction execution speed: 1 instruction per cycle DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H) ■ Instructions including memory-to-memory transfer, bit  manipulation instructions, and barrel shift instructions:  Instructions suitable for embedded applications ■ Function entry/exit instructions and register data multi load store instructions: Instructions supporting C language ■ Register interlock function: Facilitating assembly-language coding ■ Built-in multiplier with instruction-level support Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles ■ 10-bit resolution: 8 channels Conversion time: 1 s (using at 5 V) , 3 s (using at 3.3 V) ■ External interrupt inputs: 10 channels ■ Bit search module (for REALOS) Function to search from the MSB (most significant bit) for the position of the first "0", "1" or changed bit in a word ■ ■ Interrupt (PC/PS saving): 6 cycles (16 priority levels) ■ Harvard architecture allowing program access and data access to be executed simultaneously ■ Instructions compatible with the FR family A/D converter (sequential comparison) LIN-USART (full duplex double buffer): 4 channels Clock synchronous/asynchronous selectable Sync-break detection Internal dedicated baud rate generator ■ I2C bus interface (Supports 400 kbps): 2 channels Master/slave transmission and reception Internal Peripheral Resources Arbitration function, clock synchronization function ■ Flash memory capacity : 288 Kbytes ■ Internal RAM capacity: 8 Kbytes (Data RAM)  2 Kbytes (Instruction/data RAM) ■ ■ General-purpose port: Maximum 48 ports 32 transmission/reception message buffers ■ DMAC (DMA Controller) ■ 16-bit PPG timer: 8 channels ■ 16-bit reload timer: 4 channels  1 channel (exclusive A/D converter) ■ 16-bit free-run timer: 4 channels ■ Input capture: 4 channels Maximum of 5 channels for able to operate simultaneously 2 transfer sources (internal peripheral/software) Activation source can be selected by programs Cypress Semiconductor Corporation Document Number: 002-04604 Rev. *C • CAN controller (C-CAN): 2 channels Maximum transfer speed: 1 Mbps 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 19, 2019 CY91460N Series ■ Output compare: 4 channels Package: LQFP-64 (LQG064) ■ 8/16-bit up/down counter: 2 channels (8-bit)/1channel (16-bit) CMOS 0.18 m technology ■ Watchdog timer 3.3 V only power supplies or 5 V only power supplies ■ Real-time clock ■ Low-power consumption mode: Sleep/stop mode function Document Number: 002-04604 Rev. *C Operating temperature range:  40°C to  85°C (using at 5 V)  40°C to  105°C (using at 3.3 V) Page 2 of 81 CY91460N Series Contents Product Lineup ...................................................................... 4 Pin Assignment ..................................................................... 6 Pin Description ...................................................................... 7 Power Supply/GND Pins ......................................................... 9 I/O Circuit Type .................................................................... 10 Precautions for Handling The Devices.............................. 14 Precautions for Product Design............................................. 14 Precautions for Package Mounting........................................ 16 Precautions for Use Environment.......................................... 17 Handling Devices................................................................. 18 Notes on Debugger ............................................................. 20 Execution of the RETI Command .......................................... 20 Break Function ...................................................................... 20 Operand Break ...................................................................... 20 Notes on PS Register ............................................................ 20 Block Diagram ..................................................................... 21 CPU and Control Unit.......................................................... 22 Features ................................................................................ 22 Internal Architecture .............................................................. 23 Programming Model .............................................................. 24 Registers ............................................................................... 25 Mode Setting ........................................................................ 28 Mode Pins.............................................................................. 28 Mode Register (MODR)......................................................... 28 Document Number: 002-04604 Rev. *C Recommended Setting.........................................................29 Setting of PLL and Clock Gear ...............................................29 Setting of Flash Memory Controller ........................................29 Setting of Clock Modulator .....................................................30 Memory Space ......................................................................34 Memory space ........................................................................34 Memory Map...........................................................................35 Flash Memory Sector Configuration .......................................36 I/O Map...................................................................................37 Interrupt Source Table .........................................................56 Electrical Characteristics.....................................................60 Absolute Maximum Rating......................................................60 Recommended Operating Conditions ....................................62 DC Characteristics..................................................................63 AC Characteristics..................................................................66 Electrical Characteristics for A/D Converter ...........................72 Notes on the A/D Converter ...................................................73 Definition of A/D Converter Terms..........................................74 Flash Memory Program/Erase Characteristics.......................76 Ordering Information............................................................77 Package Dimension..............................................................78 Main Changes in This Edition .............................................79 Document History.................................................................80 Sales, Solutions, and Legal Information ............................81 Page 3 of 81 CY91460N Series 1. Product Lineup Part Number CY91F463NA CY91F463NC CY91V460A Parameter Max core frequency (CLKB) 80 MHz Max resource frequency (CLKP) 40 MHz Max external bus frequency (CLKT) 40 MHz Max CAN frequency  (CLKCAN) 20 MHz 0.35 m 0.18 m Watchdog Timer Yes No Watchdog Timer (CR oscillator) Yes (disengageable) Yes Technology Bit search Yes Reset input (INITX) Yes Hardware standby input (HSTX) Yes No Clock modulator Yes Low-power mode Yes DMAC 5 channels MAC (DSP) No MMU/MPU Flash memory MPU (16 channels)[1] MPU (4 channels)[1] Emulation SRAM 32-bit read data Flash protection 288 Kbytes - Yes Data RAM 64 Kbytes 8 Kbytes Instruction/data RAM 64 Kbytes 2 Kbytes Flash-cache (instruction cache) 16 Kbytes 4 Kbytes Boot-ROM/BI-ROM 4 Kbytes fixed 4 Kbytes (BI-ROM) Real-time clock 1 channels Free-run timer 8 channels 4 channels ICU 8 channels 4 channels OCU 8 channels 4 channels 16-bit reload timer 8 channels 4 channels  1 channel 16-bit PPG 16 channels 8 channels Document Number: 002-04604 Rev. *C Page 4 of 81 CY91460N Series Part Number CY91V460A CY91F463NA CY91F463NC 16-bit PFM 1 channel No Sound Generator 1 channel No 4 channels (8-bit) / 2 channels (16-bit) 2 channels (8-bit) /1 channel (16-bit) 6 channels (128 message buffers) 2 channels (32 message buffers) 4 channels  4 channels (FIFO)  8 channels 4 channels 4 channels 2 channels FR external bus Yes (32-bit address, 32-bit data) No External interrupt 16 channels 10 channels Yes No 6 channels No Parameter 8/16-bit up/down counter C_CAN LIN-USART I2C (400 kbps) NMI interrupts Stepping motor controller (SMC) LCD controller (40  4) 1 channel No 10-bit A/D converter 32 channels 8 channels Alarm comparator 2 channels No Clock supervisor Yes No Main clock oscillator 4 MHz Sub clock oscillator 32 kHz - CR oscillator 100 kHz 100 kHz / 2 MHz 20 PLL DSU4 Yes No EDSU Yes (32 BP) [1] Yes (8 BP)[1] Power supply voltage 3V/5V Regulator Power consumption Temperature range (TA) Package Yes n.a. < 700 mW 0 C to +70°C  40 C to  105°C BGA-660 LQFP-64 1. MPU channels use EDSU breakpoint registers (shared operation between MPU and EDSU). Document Number: 002-04604 Rev. *C Page 5 of 81 Document Number: 002-04604 Rev. *C 21 P22_0/RX4/INT12 24 25 26 27 28 29 30 31 32 P22_3/TX5 P20_0/SIN2/AIN0 P20_1/SOT2/BIN0 P20_2/SCK2/CK2/ZIN0 P20_4/SIN3/AIN1 P20_5/SOT3/BIN1 P20_6/SCK3/CK3/ZIN1 P15_0/OCU0/TOT0 P15_1/OCU1/TOT1 23 20 P24_7/INT7/SCL3 P22_2/RX5/INT13 19 P24_6/INT6/SDA3 22 18 C P22_1/TX4 17 VSS AVSS AVRH P14_0/ICU0/TIN0/TTG0 P14_1/ICU1/TIN1/TTG1 P14_2/ICU2/TIN2/TTG2 P14_3/ICU3/TIN3/TTG3 P21_0/SIN0 P21_1/SOT0 P21_2/SCK0/CK0 P21_4/SIN1 P21_5/SOT1 P21_6/SCK1/CK1 P17_0/PPG0 P17_1/PPG1 P17_2/PPG2 VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CY91460N Series 2. Pin Assignment (TOP VIEW) AVCC 1 48 VCC P29_0/AN0 2 47 P17_3/PPG3 P29_1/AN1 3 46 P17_4/PPG4 P29_2/AN2 4 45 P17_5/PPG5 P29_3/AN3 5 44 P17_6/PPG6 P29_4/AN4 6 43 P17_7/PPG7 P29_5/AN5 7 42 P15_3/OCU3/TOT3 P29_6/AN6 8 41 P15_2/OCU2/TOT2 P29_7/AN7 9 40 INITX P24_0/INT0 10 39 MD0 P24_1/INT1 11 38 MD1 LQFP-64 P24_2/INT2 12 37 MD2 P24_3/INT3/MONCLK 13 36 MD3 P24_4/INT4/SDA2 14 35 X1 P24_5/INT5/SCL2 15 34 X0 VCC 16 33 VSS (LQG064) Page 6 of 81 CY91460N Series 3. Pin Description Pin No. 2 to 9 10 to 12 Pin Name P29_0 to P29_7 AN0 to AN7 P24_0 to P24_2 INT0 to INT2 I/O I/O Circuit Type[1] I/O B I/O A I/O A P24_3 13 INT3 I/O C 19 C I2C bus clock input/output pin P24_6 General-purpose input/output port INT6 I/O C INT7 General-purpose input/output port I/O C 24 I2C bus clock input/output pin P22_0 General-purpose input/output port RX4 I/O A P22_1 TX4 RX5 I/O A I/O A RX input pin of CAN5 INT13 External interrupt input pin General-purpose input/output port TX5 I/O A SIN2 SOT2 I/O A CK2 General-purpose input/output port I/O A General-purpose input/output port I/O A ZIN0 AIN1 Document Number: 002-04604 Rev. *C Data output pin of LIN-USART2 Up/down counter input pin Clock input/output pin of LIN-USART2 Free-run timer input pin Up/down counter input pin P20_4 SIN3 Data input pin of LIN-USART2 Up/down counter input pin BIN0 SCK2 TX output pin of CAN5 General-purpose input/output port P20_2 28 TX output pin of CAN4 P22_3 P20_1 27 General-purpose input/output port General-purpose input/output port AIN0 26 RX input pin of CAN4 External interrupt input pin P20_0 25 External interrupt input pin SCL3 P22_2 23 External interrupt input pin I2C bus data input/output pin INT12 22 External interrupt input pin SCL2 P24_7 21 External interrupt input pin General-purpose input/output port I/O SDA3 20 External interrupt input pins I2C bus data input/output pin P24_5 INT5 External interrupt input pins General-purpose input/output port SDA2 15 General-purpose input/output ports Clock monitor output pin P24_4 INT4 General-purpose input/output ports Analog input pins for A/D converter General-purpose input/output port MONCLK 14 Function General-purpose input/output port I/O A Data input pin of LIN-USART3 Up/down counter input pin Page 7 of 81 CY91460N Series Pin No. Pin Name I/O I/O Circuit Type[1] I/O A P20_5 29 SOT3 General-purpose input/output port BIN1 SCK3 CK3 General-purpose input/output port I/O A ZIN1 OCU0 General-purpose input/output port I/O A TOT0 OCU1 Output compare output pin Reload timer output pin P15_1 32 Clock input/output pin of LIN-USART3 Free-run timer input pin Up/down counter input pin P15_0 31 Data output pin of LIN-USART3 Up/down counter input pin P20_6 30 Function General-purpose input/output port I/O A X0  J 35 X1  J Clock (oscillation) output 36 MD3 I I Mode setting pin 37 MD2 I G Mode setting pin 38 MD1 I G Mode setting pin 39 MD0 I G Mode setting pin 40 INITX I H External reset input I/O A TOT1 34 Reload timer output pin P15_2 41 42 OCU2 TOT2 Reload timer output pin General-purpose input/output port OCU3 I/O A P17_7 to P17_0 PPG7 to PPG0 SCK1 55 P21_5 SOT1 P21_4 SIN1 I/O A I/O A SCK0 58 P21_1 SOT0 P21_0 SIN0 Document Number: 002-04604 Rev. *C Clock input/output pin of LIN-USART1 Free-run timer input pin I/O I/O A A General-purpose input/output port Data output pin of LIN-USART1 General-purpose input/output port Data input pin of LIN-USART1 General-purpose input/output port I/O A CK0 57 General-purpose input/output ports PPG timer output pins General-purpose input/output port P21_2 56 Output compare output pin Reload timer output pin CK1 54 Output compare output pin P15_3 P21_6 53 Clock (oscillation) input General-purpose input/output port TOT3 43 to 47, 50 to 52 Output compare output pin Clock input/output pin of LIN-USART0 Free-run timer input pin I/O A I/O A General-purpose input/output port Data output pin of LIN-USART0 General-purpose input/output port Data input pin of LIN-USART0 Page 8 of 81 CY91460N Series Pin No. Pin Name I/O Circuit Type[1] I/O P14_3 General-purpose input/output port ICU3 59 I/O TIN3 A TTG3 I/O TIN2 A TTG2 Input capture input pin External trigger input pin of reload timer PPG timer input pin P14_1 General-purpose input/output port ICU1 I/O TIN1 A TTG1 Input capture input pin External trigger input pin of reload timer PPG timer input pin P14_0 General-purpose input/output port ICU0 62 External trigger input pin of reload timer General-purpose input/output port ICU2 61 Input capture input pin PPG timer input pin P14_2 60 Function I/O TIN0 A TTG0 Input capture input pin External trigger input pin of reload timer PPG timer input pin 1. For I/O circuit type, refer to “ I/O Circuit Type”. 3.1 Power Supply/GND Pins Pin No. Pin Name I/O 17, 33, 49 VSS - GND pins 16, 48 VCC - 3.3 V/5 V power supply pins 64 AVSS - Analog GND pin for A/D converter 1 AVCC - 3.3 V/5 V power supply pin for A/D converter 63 AVRH - Reference power supply pin for A/D converter 18 C - Capacitor connection pin for internal regulator Document Number: 002-04604 Rev. *C Function Page 9 of 81 CY91460N Series 4. I/O Circuit Type Type Circuit Remarks A ■ CMOS level output Pull-up control P-ch P-ch Driver strength control Data line N-ch (programmable IOL = 5mA, IOH   5mA, IOL = 2mA,  IOH   2mA) ■ 2 different CMOS hysteresis inputs with input shutdown function ■ Automotive input with input shutdown function ■ TTL input with input shutdown function ■ Programmable pull-up resistor: approx.50 k N-ch Pull-down control R CMOS hysteresis input type1 CMOS hysteresis input type2 Automotive input TTL input Standby control for input shutdown Document Number: 002-04604 Rev. *C Page 10 of 81 CY91460N Series Type Circuit Remarks B ■ CMOS level output Pull-up control P-ch P-ch Driver strength  control Data line N-ch (programmable IOL  5 mA, IOH   5 mA, IOL  2 mA,  IOH   2 mA) ■ 2 different CMOS hysteresis inputs with input shutdown function ■ Automotive input with input shutdown function ■ TTL input with input shutdown: approx.50 k ■ Analog input N-ch Pull-down control R CMOS hysteresis input type1 CMOS hysteresis input type2 Automotive input TTL input Standby control for input shutdown Analog input Document Number: 002-04604 Rev. *C Page 11 of 81 CY91460N Series Type Circuit Remarks ■ CMOS level output (IOL  3 mA, IOH   3 mA) C Pull-up control ■ 2 different CMOS hysteresis inputs with input shutdown function ■ Automotive input with input shutdown function P-ch ■ TTL input with input shutdown function P-ch Data line N-ch ■ Programmable pull-up resistor: approx.50 k N-ch Pull-down control R CMOS hysteresis input type1 CMOS hysteresis input type2 Automotive input TTL input Standby control for input shutdown Document Number: 002-04604 Rev. *C Page 12 of 81 CY91460N Series Type Circuit Remarks G ■ MASK ROM and evaluation device: CMOS level input R CMOS level input ■ Flash device: ❐ CMOS level input ❐ 12 V resistant (for MD [2:0]) ■ CMOS hysteresis input H ■ Pull-up resistor value: approx.50 k Pull-up resistor CMOS Hysteresis inpu R ■ CMOS hysteresis input I ■ Pull-down resistor value: approx.50 k R CMOS Hysteresis inpu Pull-down resistor J Oscillation circuit X1 Xout X0 Standby control signal Document Number: 002-04604 Rev. *C Page 13 of 81 CY91460N Series 5. Precautions for Handling The Devices Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 5.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. ■ Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ Recommended Operating Conditions The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their Cypress representatives beforehand. ■ Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions  Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such over voltage or over-current conditions at the design stage. 2. Protection of Output Pins  Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins  Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. ■ Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. Note: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following:  (a) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc.  (b) Be sure that abnormal current flows do not occur during the power-on sequence. ■ Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. ■ Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Document Number: 002-04604 Rev. *C Page 14 of 81 CY91460N Series ■ Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, submarine repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with Cypress sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Document Number: 002-04604 Rev. *C Page 15 of 81 CY91460N Series 5.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mounting type. In either case, quality assurance of heat resistance are applied for mounting under the Cypress's recommended conditions only at the soldering stage. For detailed information on mount conditions, contact the sales representative. ■ Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket.Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder.In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions.If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. ■ Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. ■ Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (a) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (b) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between  5°C to  30°C. (c) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (d) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. ■ Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. ■ Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (a) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (b) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (c) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 M). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (d) Ground all fixtures and instruments, or protect with anti-static measures. (e) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. Document Number: 002-04604 Rev. *C Page 16 of 81 CY91460N Series 5.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity  Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity  When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil  Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation  Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame Note: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with Cypress sales representatives. Document Number: 002-04604 Rev. *C Page 17 of 81 CY91460N Series 6. Handling Devices ■ Power supply pins Because there are multiple VCC and VSS pins, respective pins at the same potential are interconnected to prevent malfunctions such as latch-up. However, you must connect the pins externally to the power supply and ground lines to reduce the electro-magnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Furthermore, the current supply source should be connected to the VCC and VSS pins of the device at a low impedance. It is recommended to connect a ceramic bypass capacitor of approximately 0.1 F as a bypass capacitor between the VCC and VSS near this device. ■ Crystal oscillator circuit Noise in proximity to the X0 and X1 pins can cause the device to malfunction. Printed circuit boards should be designed so that the X0 and X1 pins, crystal oscillator (or ceramic oscillator), and bypass capacitors connected to ground are located near the device and ground. It is recommended that the printed circuit board artwork be designed such that the X0 and X1 pins are surrounded by ground plane for the stable operation. Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this device. ■ Mode pins (MD0 to MD3) Connect them directly to VCC or VSS. To prevent the device from entering test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and VCC or VSS on the printed circuit board as much as possible and connect them at a low impedance. When used pulling down, design your circuit not to generate noises with a resistance 1 k or less. Test your circuit and confirm that there is no problem. ■ Operation at power-on At power-on, it is necessary to make the terminal INITX “L” level. Maintain the “L” level input to the INITX pin for the duration of the stabilization wait time immediately after the power on to ensure the stabilization wait time as required by the oscillator circuit. ■ Note on oscillator input at power-on At power-on, ensure that the clock is input until the oscillator stabilization wait time has elapsed. ■ Built-in regulator As this series includes built-in step-down regulators, always connect a bypass capacitor of 4.7 F or more to the C pin for use by the regulator. ■ Notes on power on/off Connect/disconnect the power supply pins when power on/off, or turn on/off in the following order. Power on : VCC → AVCC, AVRH Power off : AVCC, AVRH → VCC ■ Precautions for the STOP mode Set 1 to the bit 0 (OSCD1) of STCR register. When shifting to the STOP mode, a regulator switches to the stand-by regulator (for low-consumption current).Due to the limited drive current, stop the (programming/erasing) access to the A/D converter and Flash before shifting to the STOP mode. ■ Serial communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a board so as to avoid noise. Consider receiving of wrong data when designing the system. For example, apply a checksum to detect an error. If an error is detected, retransmit the data. Document Number: 002-04604 Rev. *C Page 18 of 81 CY91460N Series ■ Notes on using external clock When using the external clock, as a general rule you should simultaneously supply X0 and X1 pins. And also, the clock signal to X0 should be supplied a clock signal with the reverse phase to X1 pins. However, in this case the stop mode (oscillation stop mode) must not be used. Example of using external clock (normal) X0 X1 Note: Stop mode (oscillation stop mode) cannot be used. ■ Notes on operating in PLL clock mode If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may continue to operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this self-running operation cannot be guaranteed. Document Number: 002-04604 Rev. *C Page 19 of 81 CY91460N Series 7. Notes on Debugger 7.1 Execution of the RETI Command If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding interrupt handling routine will be executed repeatedly to the exclusion of other processing. This will prevent the main routine and the handlers for low priority level interrupts from being executed (For example, if the time-base timer interrupt is enabled, stepping over the RETI instruction will always break on the first line of the time-base timer interrupt handler). Disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debugging. 7.2 Break Function If the range of addresses that cause a hardware break (including event breaks) is set to the address of the current system stack pointer or to an area that contains the stack pointer, execution will break after each instruction regardless of whether the user program actually contains data access instructions. To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the target of the hardware break (including an event breaks). 7.3 Operand Break It may cause malfunctions if a stack pointer exists in the area which is set as the DSU operand break. Do not set the access to the areas containing the address of system stack pointer as a target of data event break. 7.4 Notes on PS Register As the PS register is processed in advance by some instructions, when the debugger is being used, the following exception handling may result in execution breaking in an interrupt handling routine or the displayed values of the flags in the PS register being updated.As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,the operation before and after the EIT always proceeds according to specification. ■ The following behavior may occur if any of the following occurs in the instruction immediately after a DIV0U/DIV0S instruction: (a) a user interrupt or NMI is accepted; (b) single-step execution is performed; or (c) execution breaks due to a data event or from the emulator menu. ❐ D0 and D1 flags are updated in advance. ❐ An EIT handling routine (user interrupt/NMI or emulator) is executed. ❐ Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated to the same values as those in 1). ■ The following behavior occurs when an ORCCR, STILM, MOV Ri or PS instruction is executed to enable a user interrupt or NMI source while that interrupt is in the active state. ❐ The PS register is updated in advance. ❐ An EIT handling routine (user interrupt/NMI or emulator) is executed. ❐ Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in 1). Document Number: 002-04604 Rev. *C Page 20 of 81 CY91460N Series 8. Block Diagram FR60 CPU core Data RAM 8 Kbytes Flash-instruction cache 4 Kbytes Bit search I-bus 32 Flash memory 288 Kbytes Instruction RAM 8 Kbytes D-bus 32 CAN 2 channels RX4,RX5 TX4,TX5 32  16 bus adapter Bus converter DMAC 5 channels R-bus 16 Interrupt controller Clock control TTG0 to TTG3 PPG0 to PPG7 PPG 8 channels TIN0 to TIN3 TOT0 to TOT3 Reload timer 4 channels  1 channel (exclusive A/D converter) CK0 to CK3 ICU0 to ICU3 OCU0 to OCU3 AIN0,AIN1 BIN0,BIN1 ZIN0,ZIN1 Document Number: 002-04604 Rev. *C Free-run timer 4 channels Input capture 4 channels Output compare 4 channels External interrupt 10 channels LIN-USART 4 channels INT0 to INT7 INT12,INT13 SIN0 to SIN3 SOT0 to SOT3 SCK0 to SCK3 I 2C 2 channels SDA2,SDA3 SCL2,SCL3 A/D converter 8 channels AN0 to AN7 Up/down counter 2 channels Page 21 of 81 CY91460N Series 9. CPU and Control Unit Internal Architecture The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced instructions for embedded applications. 9.1 Features Adoption of RISC architecture Basic instruction: 1 instruction per cycle ■ ■ General-purpose registers: 32-bit × 16 registers ■ 4 Gbytes linear memory space Multiplier installed 32-bit × 32-bit multiplication: 5 cycles 16-bit × 16-bit multiplication: 3 cycles ■ Enhanced interrupt processing function Quick response speed (6 cycles) Multiple-interrupt support Level mask function (16 levels) ■ Enhanced instructions for I/O operation Memory-to-memory transfer instruction Bit processing instruction ■ ■ Basic instruction word length: 16 bits Low-power consumption SLEEP mode/STOP mode ■ Document Number: 002-04604 Rev. *C Page 22 of 81 CY91460N Series 9.2 Internal Architecture The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent of each other. A 32-bit  16-bit bus adapter is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and peripheral resources. A Harvard  Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between the CPU and the bus controller. The following figure shows the internal architecture structure. FR60 CPU core Data RAM 8 Kbytes Flash-instruction cache 4 Kbytes Bit search D-bus 32 I-bus 32 Flash memory 288 Kbytes Instruction RAM 2 Kbytes Bus converter CAN 2 channels 32 16 bus adapter R-bus 16 DMAC 5 channels Peripheral resource Document Number: 002-04604 Rev. *C Page 23 of 81 CY91460N Series 9.3 Programming Model 9.3.1 Basic Programming Model 32 bits Initial value R0 XXXX XXXXH R1 ... General-purpose registers ... R12 R13 AC ... R14 FP XXXX XXXXH R15 SP 0000 0000H Program counter PC Program status RS Table base register TBR Return pointer RP System stack pointer SSP User stack pointer USP Multiply and divide result registers MDH Document Number: 002-04604 Rev. *C ... ... ... ... ... ... ILM SCR CCR MDL Page 24 of 81 CY91460N Series 9.4 Registers 9.4.1 General-purpose Register 32 bits Initial value R0 XXXX XXXXH R1 ... ... ... ... ... ... ... ... R12 R13 AC ... R14 FP XXXX XXXXH R15 SP 0000 0000H Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation operations and as pointers for memory access. Enhanced commands are provided for some of the 16 registers to enable their use for particular applications. R13 : Virtual accumulator R14 : Frame pointer R15 : Stack pointer Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value). 9.4.2 PS (Program Status) This register holds the program status, and is divided into three parts, ILM, SCR, and CCR. All undefined bits (-) in the diagram are reserved bits. The values are always read "0". Write access to these bits is invalid. bit 31 bit 20 bit 16 ILM Document Number: 002-04604 Rev. *C bit 10 bit 8 bit 7 SCR bit 0 CCR Page 25 of 81 CY91460N Series 9.4.3 CCR (Condition Code Register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SV S I N Z V C Initial value - 000XXXXB SV: Supervisor S: Stack flag I: Interrupt enable flag N: Negative enable flag Z: Zero flag V: Overflow flag C: Carry flag 9.4.4 SCR (System Condition Register) bit 10 bit 9 D1 D0 bit 8 Initial value T XX0B Flag for step multiplication (D1, D0)  This flag stores interim data during execution of step multiplication. Step trace trap flag (T)  This flag indicates whether the step trace trap is enabled or disabled. The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution of user programs. 9.4.5 ILM (Interrupt Level Mask Register) bit 20 bit 19 bit 18 bit 17 bit 16 ILM4 ILM3 ILM2 ILM1 ILM0 Initial value 01111B This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking. The register is initialized to value “01111B” at reset. 9.4.6 PC (Program Counter) bit 31 bit 0 Initial value XXXXXXXXH The program counter indicates the address of the instruction that is being executed. The initial value at reset is undefined. Document Number: 002-04604 Rev. *C Page 26 of 81 CY91460N Series 9.4.7 TBR (Table Base Register) bit 0 Initial value bit 31 000FFC00H The table base register stores the starting address of the vector table used in EIT processing. The initial value at reset is 000FFC00H. 9.4.8 RP (Return Pointer) bit 31 bit 0 Initial value XXXXXXXXH The return pointer stores the address to return from subroutines. During execution of a CALL instruction, the PC value is transferred to this RP register. During execution of a RET instruction, the contents of the RP register are transferred to PC. The initial value at reset is undefined. 9.4.9 USP (User Stack Pointer) bit 31 bit 0 Initial value XXXXXXXXH When the S flag is “1”, the user stack pointer functions as the R15 register. ■ The USP register can also be explicitly specified. The initial value at reset is undefined. ■ This register cannot be used with RETI instructions. 9.4.10 Multiply & Divide Registers bit 31 bit 0 Initial value MDH XXXXXXXXH MDL XXXXXXXXH These registers are for multiplication and division, and are each 32 bits in length. The initial value at reset is undefined. Document Number: 002-04604 Rev. *C Page 27 of 81 CY91460N Series 10. Mode Setting In the FR family, the mode pins (MD2, MD1, MD0) and the mode register (MODR) are used to set the operating mode. 10.1 Mode Pins The three pins MD2, MD1, MD0 are used to specify the mode vector fetch. Settings other than shown in the table are prohibited. Mode Pins[1] Mode Name Reset Vector Access Area MD2 MD1 MD0 0 0 0 Internal ROM mode vector Internal 0 0 1 External ROM mode vector External Remarks Not allowed 1. Always use MD3 with “0”. 10.2 Mode Register (MODR) The data written to the mode register using mode vector fetch is called mode data. After the mode register (MODR) is set, the device operates according to the operation mode set in this register. The mode register is set by all reset sources. User programs cannot write data to the mode register. Rewriting is allowed in the emulator mode. In this case, use an 8-bit length data transfer instruction. Data cannot be written by the transfer instruction of the 16/32-bit length. Be sure to set these bits to “00000111B”. Operation is not guaranteed when any value other than “00000111B” is set. Note: The mode data needs to be allocated in 000FFFF8H as byte data. The mode data (00000111B) must be allocated in bit 31 to bit 24, as the FR family uses the big endian architecture. Document Number: 002-04604 Rev. *C Page 28 of 81 CY91460N Series 11. Recommended Setting 11.1 Setting of PLL and Clock Gear Table 1. Recommended Setting of PLL Division and Clock Gear PLL Multiplied Setting Clock Gear Setting Clock Input [MHz] DIVM DIVN DIVG MULG 11.2 11.2.1 PLL (vco) Output (X) [MHz] Base Clock [MHz] 4 2 20 16 20 160 80 4 2 19 16 20 152 76 4 2 18 16 20 144 72 4 2 17 16 16 136 68 4 2 16 16 16 128 64 4 2 15 16 16 120 60 4 2 14 16 16 112 56 4 2 13 16 12 104 52 4 2 12 16 12 96 48 4 2 11 16 12 88 44 4 4 10 16 24 160 40 4 4 9 16 24 144 36 4 4 8 16 24 128 32 4 4 7 16 24 112 28 4 6 6 16 24 144 24 4 8 5 16 28 160 20 4 10 4 16 32 160 16 4 12 3 16 32 144 12 Setting of Flash Memory Controller Setting of Flash Access Timing For executing programs with a Flash memory, follow the settings below according to the frequency of CPU clock (CLKB). This setting is the most suitable for a high-speed access to the Flash memory. Table 2. Flash Memory Read Operating CPU Clock (CLKB) ATD ALEH EQ WEXH WTC To 24 MHz 0 0 0 0 1 To 48 MHz 0 0 1 0 2 To 80 MHz 1 1 3 0 4 Table 3. Flash Memory Write Operating CPU Clock (CLKB) ATD ALEH EQ WEXH WTC To 32 MHz 1 0 1 0 4 To 48 MHz 1 0 3 0 5 To 64 MHz 1 1 3 0 6 To 80 MHz 1 1 3 0 7 Document Number: 002-04604 Rev. *C Page 29 of 81 CY91460N Series 11.3 Setting of Clock Modulator The setting values in the table are defined within the rages of base clock frequency; 32 MHz to 80 MHz. The Flash memory access needs to be configured according to the Fmax. PLL and clock gear need to be configured according to the base clock. Table 4. Setting of Clock Modulator Modulation Internal Parameter (k) (N) CMPR [hex] Base Clock [MHz] Fmin [MHz] Fmax [MHz] 026F 80 72.6 89.1 1 3 1 3 026F 76 69.1 84.5 1 5 02AE 76 65.3 90.8 2 3 046E 76 65.3 90.8 1 3 026F 72 65.5 79.9 1 5 02AE 72 62 85.8 1 7 02ED 72 58.8 92.7 2 3 046E 72 62 85.8 1 3 026F 68 62 75.3 1 5 02AE 68 58.7 80.9 1 7 02ED 68 55.7 87.3 1 9 032C 68 53 95 2 3 046E 68 58.7 80.9 2 5 04AC 68 53 95 3 3 066D 68 55.7 87.3 4 3 086C 68 53 95 1 3 026F 64 58.5 70.7 1 5 02AE 64 55.3 75.9 1 7 02ED 64 52.5 82 1 9 032C 64 49.9 89.1 2 3 046E 64 55.3 75.9 2 5 04AC 64 49.9 89.1 3 3 066D 64 52.5 82 4 3 086C 64 49.9 89.1 1 3 026F 60 54.9 66.1 1 5 02AE 60 51.9 71 1 7 02ED 60 49.3 76.7 1 9 032C 60 46.9 83.3 2 3 046E 60 51.9 71 2 5 04AC 60 46.9 83.3 3 3 066D 60 49.3 76.7 4 3 086C 60 46.9 83.3 5 3 0A6B 60 44.7 91.3 1 3 026F 56 51.4 61.6 1 5 02AE 56 48.6 66.1 1 7 02ED 56 46.1 71.4 1 9 032C 56 43.8 77.6 Document Number: 002-04604 Rev. *C Page 30 of 81 CY91460N Series Modulation (k) Internal Parameter (N) CMPR [hex] Base Clock [MHz] Fmin [MHz] Fmax [MHz] 1 11 036B 56 41.8 84.9 1 13 03AA 56 39.9 93.8 2 3 046E 56 48.6 66.1 2 5 04AC 56 43.8 77.6 2 7 04EA 56 39.9 93.8 3 3 066D 56 46.1 71.4 4 3 086C 56 43.8 77.6 5 3 0A6B 56 41.8 84.9 1 3 026F 52 47.8 57 1 5 02AE 52 45.2 61.2 1 7 02ED 52 42.9 66.1 1 9 032C 52 40.8 71.8 1 11 036B 52 38.8 78.6 1 13 03AA 52 37.1 86.8 2 3 046E 52 45.2 61.2 2 5 04AC 52 40.8 71.8 2 7 04EA 52 37.1 86.8 3 3 066D 52 42.9 66.1 3 5 06AA 52 37.1 86.8 4 3 086C 52 40.8 71.8 5 3 0A6B 52 38.8 78.6 6 3 0C6A 52 37.1 86.8 1 3 026F 48 44.2 52.5 1 5 02AE 48 41.8 56.4 1 7 02ED 48 39.6 60.9 1 9 032C 48 37.7 66.1 1 11 036B 48 35.9 72.3 1 13 03AA 48 34.3 79.9 1 15 03E9 48 32.8 89.1 2 3 046E 48 41.8 56.4 2 5 04AC 48 37.7 66.1 2 7 04EA 48 34.3 79.9 3 3 066D 48 39.6 60.9 3 5 06AA 48 34.3 79.9 4 3 086C 48 37.7 66.1 5 3 0A6B 48 35.9 72.3 6 3 0C6A 48 34.3 79.9 7 3 0E69 48 32.8 89.1 1 3 026F 44 40.6 48.1 1 5 02AE 44 38.4 51.6 1 7 02ED 44 36.4 55.7 Document Number: 002-04604 Rev. *C Page 31 of 81 CY91460N Series Modulation (k) Internal Parameter (N) CMPR [hex] Base Clock [MHz] Fmin [MHz] Fmax [MHz] 1 9 032C 44 34.6 60.4 1 11 036B 44 33 66.1 1 13 03AA 44 31.5 73 1 15 03E9 44 30.1 81.4 2 3 046E 44 38.4 51.6 2 5 04AC 44 34.6 60.4 2 7 04EA 44 31.5 73 3 3 066D 44 36.4 55.7 3 5 06AA 44 31.5 73 4 3 086C 44 34.6 60.4 4 5 08A8 44 28.9 92.1 5 3 0A6B 44 33 66.1 6 3 0C6A 44 31.5 73 7 3 0E69 44 30.1 81.4 1 3 026F 40 37 43.6 1 5 02AE 40 34.9 46.8 1 7 02ED 40 33.1 50.5 1 9 032C 40 31.5 54.8 1 11 036B 40 30 59.9 1 13 03AA 40 28.7 66.1 1 15 03E9 40 27.4 73.7 2 3 046E 40 34.9 46.8 2 5 04AC 40 31.5 54.8 2 7 04EA 40 28.7 66.1 2 9 0528 40 26.3 83.3 3 3 066D 40 33.1 50.5 3 5 06AA 40 28.7 66.1 3 7 06E7 40 25.3 95.8 4 3 086C 40 31.5 54.8 4 5 08A8 40 26.3 83.3 5 3 0A6B 40 30 59.9 6 3 0C6A 40 28.7 66.1 7 3 0E69 40 27.4 73.7 8 3 1068 40 26.3 83.3 1 3 026F 36 33.3 39.2 1 5 02AE 36 31.5 42 1 7 02ED 36 29.9 45.3 1 9 032C 36 28.4 49.2 1 11 036B 36 27.1 53.8 1 13 03AA 36 25.8 59.3 1 15 03E9 36 24.7 66.1 Document Number: 002-04604 Rev. *C Page 32 of 81 CY91460N Series Modulation (k) Internal Parameter (N) CMPR [hex] Base Clock [MHz] Fmin [MHz] Fmax [MHz] 2 3 046E 36 31.5 42 2 5 04AC 36 28.4 49.2 2 7 04EA 36 25.8 59.3 2 9 0528 36 23.7 74.7 3 3 066D 36 29.9 45.3 3 5 06AA 36 25.8 59.3 3 7 06E7 36 22.8 85.8 4 3 086C 36 28.4 49.2 4 5 08A8 36 23.7 74.7 5 3 0A6B 36 27.1 53.8 6 3 0C6A 36 25.8 59.3 7 3 0E69 36 24.7 66.1 8 3 1068 36 23.7 74.7 9 3 1267 36 22.8 85.8 1 3 026F 32 29.7 34.7 1 5 02AE 32 28 37.3 1 7 02ED 32 26.6 40.2 1 9 032C 32 25.3 43.6 1 11 036B 32 24.1 47.7 1 13 03AA 32 23 52.5 1 15 03E9 32 22 58.6 2 3 046E 32 28 37.3 2 5 04AC 32 25.3 43.6 2 7 04EA 32 23 52.5 2 9 0528 32 21.1 66.1 2 11 0566 32 19.5 89.1 3 3 066D 32 26.6 40.2 3 5 06AA 32 23 52.5 3 7 06E7 32 20.3 75.9 4 3 086C 32 25.3 43.6 4 5 08A8 32 21.1 66.1 5 3 0A6B 32 24.1 47.7 5 5 0AA6 32 19.5 89.1 6 3 0C6A 32 23 52.5 7 3 0E69 32 22 58.6 8 3 1068 32 21.1 66.1 9 3 1267 32 20.3 75.9 10 3 1466 32 19.5 89.1 Document Number: 002-04604 Rev. *C Page 33 of 81 CY91460N Series 12. Memory Space 12.1 Memory space The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access. ■ Direct addressing area The following address space area is used for I/O. This area is called direct addressing area, and the address of an operand can be specified directly in an instruction. The size of directly addressable area depends on the length of the data to be accessed as shown below. Byte data access: 000H to 0FFH Half word access: 000H to 1FFH Word data access: 000H to 3FFH Document Number: 002-04604 Rev. *C Page 34 of 81 CY91460N Series 12.2 Memory Map 00000000H I/O Direct addressing area Refer to “I/O Map”. 00000400H I/O 00001000H 0002E000H Data RAM (8 Kbytes) 00030000H Instruction/data RAM (2 Kbytes) 00030800H 000C0000H Flash memory 256 Kbytes 00100000H 00148000H Flash memory 32 Kbytes 00150000H FFFFFFFFH Document Number: 002-04604 Rev. *C Page 35 of 81 CY91460N Series 12.3 Flash Memory Sector Configuration CY91F463NC addr 0014:FFFFH 0014:E000H 0014:DFFFH 0014:C000H 0014:BFFFH 0014:A000H 0014:9FFFH 0014:8000H 0014:7FFFH 0014:6000H 0014:5FFFH 0014:4000H 0014:3FFFH 0014:2000H 0014:1FFFH 0014:0000H 0013:FFFFH 0013:0000H 0012:FFFFH 0012:0000H 0011:FFFFH 0011:0000H 0010:FFFFH 0010:0000H 000F:FFFFH 000F:0000H 000E:FFFFH 000E:0000H 000D:FFFFH 000D:0000H 000C:FFFFH 000C:0000H 000B:FFFFH 000B:0000H 000A:FFFFH 000A:0000H 0009:FFFFH 0009:0000H 0008:FFFFH 0008:0000H 0007:FFFFH 0007:0000H 0006:FFFFH 0006:0000H 0005:FFFFH 0005:0000H 0004:FFFFH 0004:0000H 16-bit write mode 32-bit read mode SA7(8 Kbytes) SA6(8 Kbytes) SA5(8 Kbytes) SA4(8 Kbytes) SA3(8 Kbytes) SA2(8 Kbytes) SA1(8 Kbytes) SA0(8 Kbytes) SA23(64 Kbytes) SA22(64 Kbytes) SA21(64 Kbytes) SA20(64 Kbytes) SA19(64 Kbytes) SA18(64 Kbytes) SA17(64 Kbytes) SA16(64 Kbytes) SA15(64 Kbytes) SA14(64 Kbytes) SA13(64 Kbytes) SA12(64 Kbytes) SA11(64 Kbytes) SA10(64 Kbytes) SA9(64 Kbytes) The shaded area is unusable. SA8(64 Kbytes) addr+0 addr+1 addr+2 addr+3 dat[31:16] dat[15:0] dat[31:0] Note: CY91F463NC has a different sector map for the flash memory to that of CY91F463NA. The sector map showed above is suited for CY91F463NC, not for CY91F463NA. Document Number: 002-04604 Rev. *C Page 36 of 81 CY91460N Series 13. I/O Map Address 000000H Register 0 1 2 3 PDR0 [R/W] XXXXXXXX PDR1 [R/W] XXXXXXXX PDR2 [R/W] XXXXXXXX PDR3 [R/W] XXXXXXXX Block T-unit port data register Read/write attribute Initial value of register after reset Register name (column 1 register at address 4n, column 2 register at address  4n + 1...) Leftmost register address (for word access, the register in column 1 is the MSB side of the data.) Note: Initial values of register bits are represented as follows: “ 1 ”: Initial value “ 1 ” “ 0 ”: Initial value “ 0 ” “ X ”: Initial value “ undefined ” “ - ”: No physical register at this location Access is prohibited to areas where the data access attributes are undefined. Document Number: 002-04604 Rev. *C Page 37 of 81 CY91460N Series Address Register 0 1 000000H to 000008H 2 3 PDR14 [R/W] - - - - XXXX PDR15 [R/W] - - - - XXXX Block Reserved 00000CH Reserved 000010H Reserved PDR17 [R/W] XXXXXXXX 000014H PDR20 [R/W] -XXX-XXX PDR21 [R/W] -XXX-XXX 000018H PDR24 [R/W] XXXXXXXX 00001CH Reserved Reserved PDR22 [R/W] - - - - XXXX Reserved R-bus Port Data Register Reserved PDR29 [R/W] XXXXXXXX Reserved 000020H Reserved 000024H to 00002CH Reserved Reserved 000030H EIRR0 [R/W] 00000000 ENIR0 [R/W] 00000000 ELVR0 [R/W] 00000000 00000000 External interrupt 0 to 7 000034H EIRR1 [R/W] 00000000 ENIR1 [R/W] 00000000 ELVR1 [R/W] 00000000 00000000 External interrupt 12, 13 000038H DICR [R/W] -------0 HRCL [R/W] 0 - - 11111 Reserved DLYI/I-unit 00003CH Reserved SCR00 [R/W, W] 00000000 SMR00 [R/W, W] 00000000 000044H ESCR00 [R/W] 00000X00 ECCR00 [R/W, R, W] 000000XX 000048H SCR01 [R/W, W] 00000000 SMR01 [R/W, W] 00000000 00004CH ESCR01 [R/W] 00000X00 ECCR01 [R/W, R, W] 000000XX 000050H SCR02 [R/W, W] 00000000 SMR02 [R/W, W] 00000000 000054H ESCR02 [R/W] 00000X00 ECCR02 [R/W, R, W] 000000XX 000058H SCR03 [R/W, W] 00000000 SMR03 [R/W, W] 00000000 00005CH ESCR03 [R/W] 00000X00 ECCR03 [R/W, R, W] 000000XX 000040H Document Number: 002-04604 Rev. *C Reserved SSR00 [R/W, R] 00001000 RDR00/TDR00 [R/W] 00000000 LIN-USART0 Reserved SSR01 [R/W, R] 00001000 RDR01/TDR01 [R/W] 00000000 LIN-USART1 Reserved SSR02 [R/W, R] 00001000 RDR02/TDR02 [R/W] 00000000 LIN-USART2 Reserved SSR03 [R/W, R] 00001000 RDR03/TDR03 [R/W] 00000000 LIN-USART3 Reserved Page 38 of 81 CY91460N Series Address Register 0 1 000060H to 00007CH 2 3 Reserved Reserved 000080H BGR100 [R/W] 00000000 BGR000 [R/W] 00000000 BGR101 [R/W] 00000000 BGR001 [R/W] 00000000 000084H BGR102 [R/W] 00000000 BGR002 [R/W] 00000000 BGR103 [R/W] 00000000 BGR003 [R/W] 00000000 000088H, 00008CH Reserved 000090H to 0000FCH Reserved Block Baud rate Generator LIN-USART0 to 3 Reserved 000100H GCN10 [R/W] 00110010 00010000 Reserved GCN20 [R/W] - - - - 0000 PPG Control 0 to 3 000104H GCN11 [R/W] 00110010 00010000 Reserved GCN21 [R/W] - - - - 0000 PPG Control 4 to 7 000108H Reserved 000110H PTMR00 [R] 11111111 11111111 000114H PDUT00 [W] XXXXXXXX XXXXXXXX 000118H PTMR01 [R] 11111111 11111111 00011CH PDUT01 [W] XXXXXXXX XXXXXXXX 000120H PTMR02 [R] 11111111 11111111 000124H PDUT02 [W] XXXXXXXX XXXXXXXX 000128H PTMR03 [R] 11111111 11111111 00012CH PDUT03 [W] XXXXXXXX XXXXXXXX 000130H PTMR04 [R] 11111111 11111111 000134H PDUT04 [W] XXXXXXXX XXXXXXXX 000138H PTMR05 [R] 11111111 11111111 00013CH PDUT05 [W] XXXXXXXX XXXXXXXX 000140H PTMR06 [R] 11111111 11111111 000144H PDUT06 [W] XXXXXXXX XXXXXXXX 000148H PTMR07 [R] 11111111 11111111 00014CH PDUT07 [W] XXXXXXXX XXXXXXXX Document Number: 002-04604 Rev. *C Reserved PCSR00 [W] XXXXXXXX XXXXXXXX PCNH00 [R/W] 0000000 - PCNL00 [R/W] 000000 - 0 PCSR01 [W] XXXXXXXX XXXXXXXX PCNH01 [R/W] 0000000 - PCNL01 [R/W] 000000 - 0 PCSR02 [W] XXXXXXXX XXXXXXXX PCNH02 [R/W] 0000000 - PCNL02 [R/W] 000000 - 0 PCSR03 [W] XXXXXXXX XXXXXXXX PCNH03 [R/W] 0000000 - PCNL03 [R/W] 000000 - 0 PCSR04 [W] XXXXXXXX XXXXXXXX PCNH04 [R/W] 0000000 - PCNL04 [R/W] 000000 - 0 PCSR05 [W] XXXXXXXX XXXXXXXX PCNH05 [R/W] 0000000 - PCNL05 [R/W] 000000 - 0 PCSR06 [W] XXXXXXXX XXXXXXXX PCNH06 [R/W] 0000000 - PCNL06 [R/W] 000000 - 0 PCSR07 [W] XXXXXXXX XXXXXXXX PCNH07 [R/W] 0000000 - PCNL07 [R/W] 000000 - 0 PPG 0 PPG 1 PPG 2 PPG 3 PPG 4 PPG 5 PPG 6 PPG 7 Page 39 of 81 CY91460N Series Address Register 0 1 000150H to 00017CH 000180H 2 3 Reserved ICS01 [R/W] 00000000 Reserved Reserved Reserved ICS23 [R/W] 00000000 000184H IPCP0 [R] XXXXXXXX XXXXXXXX IPCP1 [R] XXXXXXXX XXXXXXXX 000188H IPCP2 [R] XXXXXXXX XXXXXXXX IPCP3 [R] XXXXXXXX XXXXXXXX 00018CH OCS01 [R/W] - - - 0 - - 00 0000 - - 00 OCS23 [R/W] - - - 0 - - 00 0000 - - 00 000190H OCCP0 [R/W] XXXXXXXX XXXXXXXX OCCP1 [R/W] XXXXXXXX XXXXXXXX 000194H OCCP2 [R/W] XXXXXXXX XXXXXXXX OCCP3 [R/W] XXXXXXXX XXXXXXXX 000198H, 00019CH Reserved 0001A0H ADCS1 [R/W] 00000000 ADCS0 [R/W] 00000000 ADCR1 [R] 000000XX ADCR0 [R] XXXXXXXX 0001A8H ADCT1 [R/W] 00010000 ADCT0 [R/W] 00101100 ADSCH [R/W] - - - 00000 ADECH [R/W] - - - 00000 Reserved TMRLR0 [W] XXXXXXXX XXXXXXXX 0001B4H Reserved 0001B8H TMRLR1 [W] XXXXXXXX XXXXXXXX 0001BCH Reserved 0001C0H TMRLR2 [W] XXXXXXXX XXXXXXXX 0001C4H Reserved 0001C8H TMRLR3 [W] XXXXXXXX XXXXXXXX 0001CCH TMCSRH0 [R/W] - - - 00000 Document Number: 002-04604 Rev. *C TMCSRL0 [R/W] 0 - 000000 TMR1 [R] XXXXXXXX XXXXXXXX TMCSRH1 [R/W] - - - 00000 TMCSRL1 [R/W] 0 - 000000 TMR2 [R] XXXXXXXX XXXXXXXX TMCSRH2 [R/W] - - - 00000 TMCSRL2 [R/W] 0 - 000000 TMR3 [R] XXXXXXXX XXXXXXXX TMCSRH3 [R/W] - - - 00000 Reserved A/D Converter Reserved TMR0 [R] XXXXXXXX XXXXXXXX Reserved 0001D0H to 0001E7H Output Compare 0 to 3 ADERL [R/W] 00000000 0001A4H 0001B0H Input Capture 0 to 3 Reserved Reserved 0001ACH Block TMCSRL3 [R/W] 0 - 000000 Reload Timer 0 (PPG0, PPG1) Reload Timer 1 (PPG2, PPG3) Reload Timer 2 (PPG4, PPG5) Reload Timer 3 (PPG6, PPG7) Reserved Page 40 of 81 CY91460N Series Address 0001E8H Register 0 1 2 TMRLR7 [W] XXXXXXXX XXXXXXXX 3 TMR7 [R] XXXXXXXX XXXXXXXX Reload Timer 7 (A/D converter) 0001ECH Reserved TMCSRH7 [R/W] - - - 00000 0001F0H TCDT0 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS0 [R/W] 00000000 Free-run Timer 0 (ICU0, ICU1) 0001F4H TCDT1 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS1 [R/W] 00000000 Free-run Timer 1 (ICU2, ICU3) 0001F8H TCDT2 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS2 [R/W] 00000000 Free-run Timer 2 (OCU0, OCU1) 0001FCH TCDT3 [R/W] XXXXXXXX XXXXXXXX Reserved TCCS3 [R/W] 00000000 Free-run Timer 3 (OCU2, OCU3) 000200H DMACA0 [R/W] * 00000000 0000XXXX XXXXXXXX XXXXXXXX 000204H DMACB0 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000208H DMACA1 [R/W] * 00000000 0000XXXX XXXXXXXX XXXXXXXX 00020CH DMACB1 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000210H DMACA2 [R/W] * 00000000 0000XXXX XXXXXXXX XXXXXXXX 000214H DMACB2 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000218H DMACA3 [R/W] * 00000000 0000XXXX XXXXXXXX XXXXXXXX 00021CH DMACB3 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000220H DMACA4 [R/W] * 00000000 0000XXXX XXXXXXXX XXXXXXXX 000224H DMACB4 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX 000228H to 00023CH Reserved 000240H DMACR [R/W] 0- - - 0000 TMCSRL7 [R/W] 0 - 000000 Block DMAC Reserved 000244H to 0002FCH Reserved Reserved 000300H UDRC1 [W] 00000000 UDRC0 [W] 00000000 UDCR1 [R] 00000000 UDCR0 [R] 00000000 000304H UDCCH0 [R/W] 00000000 UDCCL0 [R/W] 00001000 Reserved UDCS0 [R/W] 00000000 000308H UDCCH1 [R/W] 00000000 UDCCL1 [R/W] 00001000 Reserved UDCS1 [R/W] 00000000 Document Number: 002-04604 Rev. *C Up/Down Counter 0, 1 Page 41 of 81 CY91460N Series Address Register 0 1 00030CH to 000364H 2 3 Reserved Reserved 000368H IBCR2 [R/W] 00000000 IBSR2 [R] 00000000 ITBAH2 [R/W] - - - - - - 00 ITBAL2 [R/W] 00000000 00036CH ITMKH2 [R/W] 00 - - - - 11 ITMKL2 [R/W] 11111111 ISMK2 [R/W] 01111111 ISBA2 [R/W] - 0000000 000370H Reserved IDAR2 [R/W] 00000000 ICCR2 [R/W] - 0011111 Reserved 000374H IBCR3 [R/W] 00000000 IBSR3 [R] 00000000 ITBAH3 [R/W] - - - - - - 00 ITBAL3 [R/W] 00000000 000378H ITMKH3 [R/W] 00 - - - - 11 ITMKL3 [R/W] 11111111 ISMK3 [R/W] 01111111 ISBA3 [R/W] - 0000000 00037CH Reserved IDAR3 [R/W] 00000000 ICCR3 [R/W] - 0011111 Reserved 000380H to 00038CH 000390H Reserved I2 C 2 I2 C 3 Reserved ROMS [R] 11111111 01001111 Reserved 000394H to 0003ECH Reserved 0003F0H BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4H BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8H BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FCH BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000400H to 00043CH Reserved ROM Select Register Reserved Bit Search Module Reserved 000440H ICR00 [R/W] - - - 11111 ICR01 [R/W] - - - 11111 ICR02 [R/W] - - - 11111 ICR03 [R/W] - - - 11111 000444H ICR04[R/W] - - - 11111 ICR05 [R/W] - - - 11111 ICR06 [R/W] - - - 11111 ICR07 [R/W] - - - 11111 000448H ICR08 [R/W] - - - 11111 ICR09 [R/W] - - - 11111 ICR10[R/W] - - - 11111 ICR11 [R/W] - - - 11111 00044CH ICR12 [R/W] - - - 11111 ICR13[R/W] - - - 11111 ICR14[R/W] - - - 11111 ICR15[R/W] - - - 11111 000450H ICR16[R/W] - - - 11111 ICR17[R/W] - - - 11111 ICR18 [R/W] - - - 11111 ICR19 [R/W] - - - 11111 Document Number: 002-04604 Rev. *C Block Interrupt Control Unit Page 42 of 81 CY91460N Series Address Register 0 1 2 3 000454H ICR20 [R/W] - - - 11111 ICR21 [R/W] - - - 11111 ICR22 [R/W] - - - 11111 ICR23 [R/W] - - - 11111 000458H ICR24[R/W] - - - 11111 ICR25[R/W] - - - 11111 ICR26[R/W] - - - 11111 ICR27[R/W] - - - 11111 00045CH ICR28[R/W] - - - 11111 ICR29 [R/W] - - - 11111 ICR30[R/W] - - - 11111 ICR31[R/W] - - - 11111 000460H ICR32[R/W] - - - 11111 ICR33[R/W] - - - 11111 ICR34[R/W] - - - 11111 ICR35[R/W] - - - 11111 000464H ICR36[R/W] - - - 11111 ICR37[R/W] - - - 11111 ICR38 [R/W] - - - 11111 ICR39 [R/W] - - - 11111 000468H ICR40[R/W] - - - 11111 ICR41[R/W] - - - 11111 ICR42 [R/W] - - - 11111 ICR43 [R/W] - - - 11111 00046CH ICR44[R/W] - - - 11111 ICR45[R/W] - - - 11111 ICR46[R/W] - - - 11111 ICR47[R/W] - - - 11111 000470H ICR48 [R/W] - - - 11111 ICR49 [R/W] - - - 11111 ICR50 [R/W] - - - 11111 ICR51 [R/W] - - - 11111 000474H ICR52[R/W] - - - 11111 ICR53[R/W] - - - 11111 ICR54[R/W] - - - 11111 ICR55[R/W] - - - 11111 000478H ICR56 [R/W] - - - 11111 ICR57[R/W] - - - 11111 ICR58 [R/W] - - - 11111 ICR59 [R/W] - - - 11111 00047CH ICR60[R/W] - - - 11111 ICR61 [R/W] - - - 11111 ICR62 [R/W] - - - 11111 ICR63 [R/W] - - - 11111 000480H RSRR [R/W] 10000000 STCR [R/W] 001100-1 TBCR [R/W] 00XXXX00 CTBR [W] XXXXXXXX 000484H CLKR [R/W] - - - - - 000 WPR [W] XXXXXXXX DIVR0 [R/W] 00000011 DIVR1 [R/W] 00000000 000488H Reserved 00048CH PLLDIVM [R/W] - - - - 0000 000490H PLLCTRL [R/W] - - - - 0000 PLLDIVN [R/W] - - 000000 PLLMULG [R/W] 00000000 Port Input Enable Control Reserved 0004A4H Reserved 0004A8H WTHR [R/W] - - - 00000 WTCER [R/W] - - - - - - 00 Reserved WTCR [R/W] 00000000 000 - 00 - 0 WTBR [R/W] - - - XXXXX XXXXXXXX XXXXXXXX WTMR [R/W] - - 000000 Reserved 0004B0H, 0004B4H Document Number: 002-04604 Rev. *C PLL Clock Gear Unit Reserved Reserved 00049CH 0004ACH PLLDIVG [R/W] - - - - 0000 PORTEN [R/W] - - - - - - 00 Reserved Clock Control Unit Reserved Reserved 0004A0H Interrupt Control Unit Reserved 000494H 000498H Block Reserved WTSR [R/W] - - 000000 Reserved CSCFG [R/W] 0X000000 CMCFG [R/W] 00000000 Real Time Clock (Watch Timer) Clock Monitor Reserved Page 43 of 81 CY91460N Series Address Register 0 1 0004B8H CMPR [R/W] - - 000010 11111101 0004BCH CMT1 [R/W] 00000000 1 - - - 0000 CANPRE [R/W] 00000000 CANCKD [R/W] - - 00 - - - - 0004C4H Reserved LVDET [R/W] 00000 - 00 0004C8H OSCRH [R/W] 000 - - 001 OSCRL [R/W] - - - - - 000 Reserved CMCR [R/W] - 001 - - 00 Reserved HWWDE [R/W] - - - - - - 00 Reserved 0004D0H to 0007F8H Reserved Reserved 000D00H to 000D08H Reserved 000D10H Reserved PDRD17 [R] XXXXXXXX 000D14H PDRD20 [R] - XXX- XXX PDRD21 [R] - XXX- XXX 000D18H PDRD24 [R] XXXXXXXX 000D1CH Reserved Low-voltage Detection Main-Oscillation Stabilization Timer Mode Register Reserved PDRD14 [R] - - - - XXXX Reserved PDRD15 [R] - - - - XXXX Reserved PDRD22 [R] - - - - XXXX Reserved R-bus Port Data Direct Read Register Reserved PDRD29 [R] XXXXXXXX Reserved 000D20H Reserved 000D24H to 000D3CH Reserved Document Number: 002-04604 Rev. *C HWWD [R/W, W] 00011000 Reserved 000800H to 000CFCH Clock Modulator Reserved MODR [W] XXXXXXXX Reserved Block CAN Clock Control Reserved 0004CCH 000D0CH 3 CMT2 [R/W] - - 000000 - - 000000 0004C0H 0007FCH 2 Reserved Page 44 of 81 CY91460N Series Address Register 0 1 000D40H to 000D48H 3 DDR14 [R/W] - - - - 0000 DDR15 [R/W] - - - - 0000 Block Reserved 000D4CH Reserved 000D50H Reserved DDR17 [R/W] 00000000 000D54H DDR20 [R/W] -000- 000 DDR21 [R/W] -000- 000 000D58H DDR24 [R/W] 00000000 000D5CH Reserved Reserved DDR22 [R/W] - - - - 0000 DDR29 [R/W] 00000000 000D64H to 000D7CH Reserved 000D80H to 000D88H Reserved Reserved PFR14 [R/W] - - - - 0000 Reserved 000D90H Reserved PFR17 [R/W] 00000000 000D94H PFR20 [R/W] -000- 000 PFR21 [R/W] -000- 000 000D98H PFR24 [R/W] 00000000 000D9CH Reserved PFR15 [R/W] - - - - 0000 Reserved PFR22 [R/W] - - - - 0000 Reserved R-bus Port Function Register Reserved PFR29 [R/W] 00000000 Reserved 000DA0H Reserved 000DA4H to 000DBCH Reserved 000DC0H to 000DC8H Reserved 000DCCH R-bus Port Direction Register Reserved Reserved 000D8CH Reserved Reserved 000D60H Reserved EPFR14 [R/W] - - - - 0000 Reserved 000DD0H 000DD4H 2 EPFR15 [R/W] - - - - 0000 R-bus Extension Port Function Register Reserved EPFR20 [R/W] - 000- 000 EPFR21 [R/W] - 0- - - 0- - Reserved 000DD8H Reserved 000DDCH Reserved 000DE0H Reserved 000DE4H to 000DFCH Reserved Document Number: 002-04604 Rev. *C R-bus Extension Port Function Register Reserved Page 45 of 81 CY91460N Series Address Register 0 1 000E00H to 000E08H 2 3 PODR14 [R/W] - - - - 0000 PODR15 [R/W] - - - - 0000 Block Reserved 000E0CH Reserved 000E10H Reserved PODR17 [R/W] 00000000 000E14H PODR20 [R/W] - 000- 000 PODR21 [R/W] - 000- 000 000E18H PODR24 [R/W] 00000000 000E1CH Reserved Reserved PODR22 [R/W] - - - - 0000 Reserved PODR29 [R/W] 00000000 Reserved 000E20H Reserved 000E24H to 000E3CH Reserved 000E40H to 000E48H Reserved 000E4CH Reserved PILR14 [R/W] - - - - 0000 Reserved 000E50H Reserved PILR17 [R/W] 00000000 000E54H PILR20 [R/W] - 000- 000 PILR21 [R/W] -000- 000 000E58H PILR24 [R/W] 00000000 000E5CH Reserved PILR15 [R/W] - - - - 0000 Reserved PILR22 [R/W] - - - - 0000 Reserved R-bus Pin Input Level Select Register Reserved PILR29 [R/W] 00000000 Reserved 000E60H Reserved 000E64H to 000E7CH Reserved 000E80H to 000E88H Reserved 000E8CH Reserved R-bus Port Output Drive Select Register EPILR14 [R/W] - - - - 0000 Reserved 000E90H Reserved EPILR17 [R/W] 00000000 000E94H EPILR20 [R/W] - 000- 000 EPILR21 [R/W] - 000- 000 000E98H EPILR24 [R/W] 00000000 000E9CH, 000EA0H Document Number: 002-04604 Rev. *C Reserved EPILR15 [R/W] - - - - 0000 Reserved EPILR22 [R/W] - - - - 0000 Reserved R-bus Port Extra Input Level Select Register Reserved Reserved Page 46 of 81 CY91460N Series Address Register 0 1 2 000EA4H to 000EBCH Reserved 000EC0H to 000EC8H Reserved 000ECCH 3 Reserved PPER14 [R/W] - - - - 0000 Reserved 000ED0H Reserved PPER17 [R/W] 00000000 000ED4H PPER20 [R/W] -000- 000 PPER21 [R/W] -000- 000 000ED8H PPER24 [R/W] 00000000 000EDCH Reserved Block PPER15 [R/W] - - - - 0000 Reserved PPER22 [R/W] - - - - 0000 Reserved R-bus Port Pull-up/down Enable Register Reserved PPER29 [R/W] 00000000 Reserved 000EE0H Reserved 000EE4H to 000EFCH Reserved Reserved 000F00H to 000F08H Reserved R-bus Port Pull-up/down ControlRegister 000F0CH PPCR14 [R/W] - - - - 1111 Reserved 000F10H Reserved PPCR17 [R/W] 11111111 000F14H PPCR20 [R/W] -111-111 PPCR21 [R/W] -111-111 000F18H PPCR24 [R/W] 11111111 000F1CH Reserved Reserved PPCR22 [R/W] - - - - 1111 Reserved Reserved PPCR29 [R/W] 11111111 R-bus Port Pull-up/down Control Register Reserved 000F20H Reserved 000F24H to 000F3CH Reserved Document Number: 002-04604 Rev. *C PPCR15 [R/W] - - - - 1111 Reserved Page 47 of 81 CY91460N Series Address Register 0 1 2 3 001000H DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001004H DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001008H DMASA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00100CH DMADA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001010H DMASA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001014H DMADA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001018H DMASA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00101CH DMADA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001020H DMASA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001024H DMADA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 001028H to 006FFCH Reserved 007000H 007004H FMCS [R/W] 01101000 FMCR [R/W] - - - -0000 Block DMAC Reserved FCHCR [R/W] - - - - - - 00 10000011 FMWT [R/W] 11111111 01011101 FMWT2 [R/W] - 101 - - - - FMPS [R/W] - - - - - 000 Flash Memory/ I-Cache Control Register 007008H FMAC [R] - - - - - - - - - - - 00000 00000000 00000000 00700CH FCHA0 [R/W] - - - - - - - - - 0000000 00000000 00000000 007010H FCHA1 [R/W] - - - - - - - - - 0000000 00000000 00000000 I-Cache Non-cacheable area setting Register 007014H to 00AFFCH Reserved Reserved 00B000H to 00BFFCH BI-ROM size is 4 Kbytes : 00B000H to 00BFFFH BI-ROM 4 Kbytes 00C000H to 00C3FCH Reserved Reserved Document Number: 002-04604 Rev. *C Page 48 of 81 CY91460N Series Address Register 0 1 2 3 00C400H CTRLR4 [R/W] 00000000 00000001 STATR4 [R/W] 00000000 00000000 00C404H ERRCNT4 [R] 00000000 00000000 BTR4 [R/W] 00100011 00000001 00C408H INTR4 [R] 00000000 00000000 TESTR4 [R/W] 00000000 X0000000 00C40CH BRPE4 [R/W] 00000000 00000000 Reserved 00C410H IF1CREQ4 [R/W] 00000000 00000001 IF1CMSK4 [R/W] 00000000 00000000 00C414H IF1MSK24 [R/W] 11111111 11111111 IF1MSK14 [R/W] 11111111 11111111 00C418H IF1ARB24 [R/W] 00000000 00000000 IF1ARB14 [R/W] 00000000 00000000 00C41CH IF1MCTR4 [R/W] 00000000 00000000 Reserved 00C420H IF1DTA14 [R/W] 00000000 00000000 IF1DTA24 [R/W] 00000000 00000000 00C424H IF1DTB14 [R/W] 00000000 00000000 IF1DTB24 [R/W] 00000000 00000000 00C428H, 00C42CH Block CAN 4 Control Register CAN 4 IF1 Register Reserved 00C430H IF1DTA24 [R/W] 00000000 00000000 IF1DTA14 [R/W] 00000000 00000000 00C434H IF1DTB24 [R/W] 00000000 00000000 IF1DTB14 [R/W] 00000000 00000000 00C438H, 00C43CH Document Number: 002-04604 Rev. *C CAN 4 IF1 Register Reserved Page 49 of 81 CY91460N Series Address Register 0 1 2 3 00C440H IF2CREQ4 [R/W] 00000000 00000001 IF2CMSK4 [R/W] 00000000 00000000 00C444H IF2MSK24 [R/W] 11111111 11111111 IF2MSK14 [R/W] 11111111 11111111 00C448H IF2ARB24 [R/W] 00000000 00000000 IF2ARB14 [R/W] 00000000 00000000 00C44CH IF2MCTR4 [R/W] 00000000 00000000 Reserved 00C450H IF2DTA14 [R/W] 00000000 00000000 IF2DTA24 [R/W] 00000000 00000000 00C454H IF2DTB14 [R/W] 00000000 00000000 IF2DTB24 [R/W] 00000000 00000000 00C458H, 00C45CH Block CAN 4 IF2 Register Reserved 00C460H IF2DTA24 [R/W] 00000000 00000000 IF2DTA14 [R/W] 00000000 00000000 00C464H IF2DTB24 [R/W] 00000000 00000000 IF2DTB14 [R/W] 00000000 00000000 00C468H to 00C47CH Reserved 00C480H TREQR24 [R] 00000000 00000000 TREQR14 [R] 00000000 00000000 00C484H TREQR44 [R] 00000000 00000000 TREQR34 [R] 00000000 00000000 00C488H TREQR64 [R] 00000000 00000000 TREQR54 [R] 00000000 00000000 00C48CH TREQR84 [R] 00000000 00000000 TREQR74 [R] 00000000 00000000 00C490H NEWDT24 [R] 00000000 00000000 NEWDT14 [R] 00000000 00000000 00C494H NEWDT44 [R] 00000000 00000000 NEWDT34 [R] 00000000 00000000 Document Number: 002-04604 Rev. *C CAN 4 Status Flags Page 50 of 81 CY91460N Series Address Register 0 1 2 3 00C498H NEWDT64 [R] 00000000 00000000 NEWDT54 [R] 00000000 00000000 00C49CH NEWDT84 [R] 00000000 00000000 NEWDT74 [R] 00000000 00000000 00C4A0H INTPND24 [R] 00000000 00000000 INTPND14 [R] 00000000 00000000 00C4A4H INTPND44 [R] 00000000 00000000 INTPND34 [R] 00000000 00000000 00C4A8H INTPND64 [R] 00000000 00000000 INTPND54 [R] 00000000 00000000 00C4ACH INTPND84 [R] 00000000 00000000 INTPND74 [R] 00000000 00000000 00C4B0H MSGVAL24 [R] 00000000 00000000 MSGVAL14 [R] 00000000 00000000 00C4B4H MSGVAL44 [R] 00000000 00000000 MSGVAL34 [R] 00000000 00000000 00C4B8H MSGVAL64 [R] 00000000 00000000 MSGVAL54 [R] 00000000 00000000 00C4BCH MSGVAL84 [R] 00000000 00000000 MSGVAL74 [R] 00000000 00000000 00C4C0H to 00C4FCH Block CAN 4 Status Flags Reserved 00C500H CTRLR5 [R/W] 00000000 00000001 STATR5 [R/W] 00000000 00000000 00C504H ERRCNT5 [R] 00000000 00000000 BTR5 [R/W] 00100011 00000001 00C508H INTR5 [R] 00000000 00000000 TESTR5 [R/W] 00000000 X0000000 00C50CH BRPE5 [R/W] 00000000 00000000 Reserved 00C510H IF1CREQ5 [R/W] 00000000 00000001 IF1CMSK5 [R/W] 00000000 00000000 00C514H IF1MSK25 [R/W] 11111111 11111111 IF1MSK15 [R/W] 11111111 11111111 00C518H IF1ARB25 [R/W] 00000000 00000000 IF1ARB15 [R/W] 00000000 00000000 00C51CH IF1MCTR5 [R/W] 00000000 00000000 Reserved 00C520H IF1DTA15 [R/W] 00000000 00000000 IF1DTA25 [R/W] 00000000 00000000 Document Number: 002-04604 Rev. *C CAN 5 Control Register CAN 5 IF1 Register Page 51 of 81 CY91460N Series Address 00C524H Register 0 1 2 IF1DTB15 [R/W] 00000000 00000000 00C528H, 00C52CH 3 Block IF1DTB25 [R/W] 00000000 00000000 Reserved 00C530H IF1DTA25 [R/W] 00000000 00000000 IF1DTA15 [R/W] 00000000 00000000 00C534H IF1DTB25 [R/W] 00000000 00000000 IF1DTB15 [R/W] 00000000 00000000 00C538H, 00C53CH CAN 5 IF1 Register Reserved 00C540H IF2CREQ5 [R/W] 00000000 00000001 IF2CMSK5 [R/W] 00000000 00000000 00C544H IF2MSK25 [R/W] 11111111 11111111 IF2MSK15 [R/W] 11111111 11111111 00C548H IF2ARB25 [R/W] 00000000 00000000 IF2ARB15 [R/W] 00000000 00000000 00C54CH IF2MCTR5 [R/W] 00000000 00000000 Reserved 00C550H IF2DTA15 [R/W] 00000000 00000000 IF2DTA25 [R/W] 00000000 00000000 00C554H IF2DTB15 [R/W] 00000000 00000000 IF2DTB25 [R/W] 00000000 00000000 00C558H, 00C55CH CAN 5 IF2 Register Reserved 00C560H IF2DTA25 [R/W] 00000000 00000000 IF2DTA15 [R/W] 00000000 00000000 00C564H IF2DTB25 [R/W] 00000000 00000000 IF2DTB15 [R/W] 00000000 00000000 00C568H to 00C57CH Document Number: 002-04604 Rev. *C Reserved Page 52 of 81 CY91460N Series Address Register 0 1 2 3 00C580H TREQR25 [R] 00000000 00000000 TREQR15 [R] 00000000 00000000 00C584H TREQR45 [R] 00000000 00000000 TREQR35 [R] 00000000 00000000 00C588H TREQR65 [R] 00000000 00000000 TREQR55 [R] 00000000 00000000 00C58CH TREQR85 [R] 00000000 00000000 TREQR75 [R] 00000000 00000000 00C590H NEWDT25 [R] 00000000 00000000 NEWDT15 [R] 00000000 00000000 00C594H NEWDT45 [R] 00000000 00000000 NEWDT35 [R] 00000000 00000000 00C598H NEWDT65 [R] 00000000 00000000 NEWDT55 [R] 00000000 00000000 00C59CH NEWDT85 [R] 00000000 00000000 NEWDT75 [R] 00000000 00000000 00C5A0H INTPND25 [R] 00000000 00000000 INTPND15 [R] 00000000 00000000 00C5A4H INTPND45 [R] 00000000 00000000 INTPND35 [R] 00000000 00000000 00C5A8H INTPND65 [R] 00000000 00000000 INTPND55 [R] 00000000 00000000 00C5ACH INTPND85 [R] 00000000 00000000 INTPND75 [R] 00000000 00000000 00C5B0H MSGVAL25 [R] 00000000 00000000 MSGVAL15 [R] 00000000 00000000 00C5B4H MSGVAL45 [R] 00000000 00000000 MSGVAL35 [R] 00000000 00000000 00C5B8H MSGVAL65 [R] 00000000 00000000 MSGVAL55 [R] 00000000 00000000 00C5BCH MSGVAL85 [R] 00000000 00000000 MSGVAL75 [R] 00000000 00000000 00C5C0H to 00EFFCH Document Number: 002-04604 Rev. *C Block CAN 5 Status Flags Reserved Page 53 of 81 CY91460N Series Address Register 0 1 2 00F000H BCTRL [R/W] - - - - - - - - - - - - - - - - 11111100 00000000 00F004H BSTAT [R/W] - - - - - - - - - - - - - 000 00000000 10 - - 0000 00F008H BIAC [R] 00000000 00000000 00000000 00000000 00F00CH BOAC [R] 00000000 00000000 00000000 00000000 00F010H BIRQ [R/W] 00000000 00000000 00000000 00000000 00F014H to 00F01CH Reserved 00F020H BCR0 [R/W] - - - - - - - - 00000000 00000000 00000000 00F024H BCR1 [R/W] - - - - - - - - 00000000 00000000 00000000 00F028H BCR2 [R/W] - - - - - - - - 00000000 00000000 00000000 00F02CH BCR3 [R/W] - - - - - - - - 00000000 00000000 00000000 00F030H to 00F03CH Reserved 00F040H to 00F07CH Reserved 00F080H BAD0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F084H BAD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F088H BAD2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F08CH BAD3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F090H BAD4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F094H BAD5 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F098H BAD6 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F09CH BAD7 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0A0H BAD8 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Document Number: 002-04604 Rev. *C 3 Block EDSU / MPU Reserved EDSU / MPU Page 54 of 81 CY91460N Series Address Register 0 1 2 3 Block 00F0A4H BAD9 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0A8H BAD10 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0ACH BAD11 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0B0H BAD12 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0B4H BAD13 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0B8H BAD14 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0BCH BAD15 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00F0C0H to 00F0FCH Reserved 00F100H to 02DFFCH Reserved Reserved 02E000H to 02FFFCH CY91F463NA/F463NC Data RAM size is 8 Kbytes: 02E000H to 02FFFFH (data access is 0 wait cycle) D-RAM 8 Kbytes 030000H to 0307FCH CY91F463NA/F463NC Instruction/data RAM size is 2 Kbytes: 030000H to 0307FFH (instruction access is 0 wait cycle, data access is 1 wait cycle) I/D-RAM 2 Kbytes 030800H to 0BFFFCH Reserved Reserved 0C0000H to 0DFFFCH ROMS04 area (128 Kbytes) 0E0000H to 0FFFF4H ROMS05 area (128 Kbytes) 0FFFF8H FMV [R] XXXXXXXXH 0FFFFCH FRV [R] XXXXXXXXH 100000H to 147FFCH Reserved Reserved 148000H to 14FFFCH ROMS07 area (32 Kbytes) Flash memory 32 Kbytes 148000H to 4FFFFCH Reserved Reserved EDSU / MPU Flash memory 256 Kbytes Reset/Mode Vector 1. The lower 16 bits (DTC15 to DTC0) of DMACA0 to DMACA4 cannot be accessed in bytes. Document Number: 002-04604 Rev. *C Page 55 of 81 CY91460N Series 14. Interrupt Source Table Interrupt number Interrupt source HexaDecimal decimal Interrupt level Interrupt vector Setting register Register address Offset Default vector address Resource number[1] Reset 0 00 - - 3FCH 000FFFFCH - Mode vector 1 01 - - 3F8H 000FFFF8H - System reserved 2 02 - - 3F4H 000FFFF4H - System reserved 3 03 - - 3F0H 000FFFF0H - System reserved 4 04 - - 3ECH 000FFFECH - CPU supervisor mode (INT #5 instruction) [2] 5 05 - - 3E8H 000FFFE8H - Memory protection exception [2] 6 06 - - 3E4H 000FFFE4H - System reserved 7 07 - - 3E0H 000FFFE0H - System reserved 8 08 - - 3DCH 000FFFDCH - System reserved 9 09 - - 3D8H 000FFFD8H - System reserved 10 0A - - 3D4H 000FFFD4H - System reserved 11 0B - - 3D0H 000FFFD0H - System reserved 12 0C - - 3CCH 000FFFCCH - System reserved 13 0D - - 3C8H 000FFFC8H - Undefined instruction exception 14 0E - NMI request 15 0F External interrupt 0 16 10 External interrupt 1 17 11 External interrupt 2 18 12 External interrupt 3 19 13 External interrupt 4 20 14 External interrupt 5 21 15 External interrupt 6 22 16 External interrupt 7 23 17 System reserved 24 18 System reserved 25 19 System reserved 26 1A System reserved 27 1B External interrupt 12 28 1C External interrupt 13 29 1D System reserved 30 1E System reserved 31 1F Reload timer 0 32 20 Reload timer 1 33 21 Reload timer 2 34 22 Reload timer 3 35 23 System reserved 36 24 System reserved 37 25 Document Number: 002-04604 Rev. *C FH fixed ICR00 440H ICR01 441H ICR02 442H ICR03 443H ICR04 444H ICR05 445H ICR06 446H ICR07 447H ICR08 448H ICR09 449H ICR10 44AH 3C4H 000FFFC4H - 3C0H 000FFFC0H - 3BCH 000FFFBCH 0, 16 3B8H 000FFFB8H 1, 17 3B4H 000FFFB4H 2, 18 3B0H 000FFFB0H 3, 19 3ACH 000FFFACH 20 3A8H 000FFFA8H 21 3A4H 000FFFA4H 22 3A0H 000FFFA0H 23 39CH 000FFF9CH - 398H 000FFF98H - 394H 000FFF94H - 390H 000FFF90H - 38CH 000FFF8CH - 388H 000FFF88H - 384H 000FFF84H - 380H 000FFF80H - 37CH 000FFF7CH 4, 32 378H 000FFF78H 5, 33 374H 000FFF74H 34 370H 000FFF70H 35 36CH 000FFF6CH 36 368H 000FFF68H 37 Page 56 of 81 CY91460N Series Interrupt number Interrupt source HexaDecimal decimal System reserved 38 26 Reload timer 7 39 27 Free-run timer 0 40 28 Free-run timer 1 41 29 Free-run timer 2 42 2A Free-run timer 3 43 2B System reserved 44 2C System reserved 45 2D System reserved 46 2E System reserved 47 2F System reserved 48 30 System reserved 49 31 System reserved 50 32 System reserved 51 33 CAN 4 52 34 CAN 5 53 35 LIN-USART0 RX 54 36 LIN-USART0 TX 55 37 LIN-USART1 RX 56 38 LIN-USART1 TX 57 39 LIN-USART2 RX 58 3A LIN-USART2 TX 59 3B LIN-USART3 RX 60 3C LIN-USART3 TX 61 3D System reserved 62 3E 63 3F Delayed interrupt [4] 64 40 System reserved [4] 65 41 System reserved 66 42 System reserved 67 43 System reserved 68 44 System reserved 69 45 System reserved 70 46 System reserved System reserved 71 47 System reserved 72 48 System reserved 73 49 I2 C 2 74 4A I2 C 3 75 4B Document Number: 002-04604 Rev. *C Interrupt level Setting register Register address ICR11 44BH ICR12 44CH ICR13 44DH ICR14 44EH ICR15 44FH ICR16 450H ICR17 451H ICR18 452H ICR19 453H ICR20 454H ICR21 455H ICR22 456H ICR23 [3] 457H (ICR24) (458H) ICR25 459H ICR26 45AH ICR27 45BH ICR28 45CH ICR29 45DH Interrupt vector Resource number[1] Offset Default vector address 364H 000FFF64H 38 360H 000FFF60H 39 35CH 000FFF5CH 40 358H 000FFF58H 41 354H 000FFF54H 42 350H 000FFF50H 43 34CH 000FFF4CH 44 348H 000FFF48H 45 344H 000FFF44H 46 340H 000FFF40H 47 33CH 000FFF3CH - 338H 000FFF38H - 334H 000FFF34H - 330H 000FFF30H - 32CH 000FFF2CH - 328H 000FFF28H - 324H 000FFF24H 6, 48 320H 000FFF20H 7, 49 31CH 000FFF1CH 8, 50 318H 000FFF18H 9, 51 314H 000FFF14H 52 310H 000FFF10H 53 30CH 000FFF0CH 54 308H 000FFF08H 55 304H 000FFF04H - 300H 000FFF00H - 2FCH 000FFEFCH - 2F8H 000FFEF8H - 2F4H 000FFEF4H 10, 56 2F0H 000FFEF0H 11, 57 2ECH 000FFEECH 12, 58 2E8H 000FFEE8H 13, 59 2E4H 000FFEE4H 60 2E0H 000FFEE0H 61 2DCH 000FFEDCH 62 2D8H 000FFED8H 63 2D4H 000FFED4H - 2D0H 000FFED0H - Page 57 of 81 CY91460N Series Interrupt number Interrupt source HexaDecimal decimal System reserved 76 4C System reserved 77 4D System reserved 78 4E System reserved 79 4F System reserved 80 50 System reserved 81 51 System reserved 82 52 System reserved 83 53 System reserved 84 54 System reserved 85 55 System reserved 86 56 System reserved 87 57 System reserved 88 58 System reserved 89 59 System reserved 90 5A System reserved 91 5B Input capture 0 92 5C Input capture 1 93 5D Input capture 2 94 5E Input capture 3 95 5F System reserved 96 60 System reserved 97 61 System reserved 98 62 System reserved 99 63 Output compare 0 100 64 Output compare 1 101 65 Output compare 2 102 66 Output compare 3 103 67 System reserved 104 68 System reserved 105 69 System reserved 106 6A System reserved 107 6B System reserved 108 6C Phase Frequency modulator 109 6D System reserved 110 6E System reserved 111 6F PPG0 112 70 PPG1 113 71 Document Number: 002-04604 Rev. *C Interrupt level Setting register Register address ICR30 45EH ICR31 45FH ICR32 460H ICR33 461H ICR34 462H ICR35 463H ICR36 464H ICR37 465H ICR38 466H ICR39 467H ICR40 468H ICR41 469H ICR42 46AH ICR43 46BH ICR44 46CH ICR45 46DH ICR46 46EH ICR47 [4] 46FH ICR48 470H Interrupt vector Resource number[1] Offset Default vector address 2CCH 000FFECCH 64 2C8H 000FFEC8H 65 2C4H 000FFEC4H 66 2C0H 000FFEC0H 67 2BCH 000FFEBCH 68 2B8H 000FFEB8H 69 2B4H 000FFEB4H 70 2B0H 000FFEB0H 71 2ACH 000FFEACH 72 2A8H 000FFEA8H 73 2A4H 000FFEA4H 74 2A0H 000FFEA0H 75 29CH 000FFE9CH 76 298H 000FFE98H 77 294H 000FFE94H 78 290H 000FFE90H 79 28CH 000FFE8CH 80 288H 000FFE88H 81 284H 000FFE84H 82 280H 000FFE80H 83 27CH 000FFE7CH 84 278H 000FFE78H 85 274H 000FFE74H 86 270H 000FFE70H 87 26CH 000FFE6CH 88 268H 000FFE68H 89 264H 000FFE64H 90 260H 000FFE60H 91 25CH 000FFE5CH 92 258H 000FFE58H 93 254H 000FFE54H 94 250H 000FFE50H 95 24CH 000FFE4CH - 248H 000FFE48H - 244H 000FFE44H - 240H 000FFE40H - 23CH 000FFE3CH 15, 96 238H 000FFE38H 97 Page 58 of 81 CY91460N Series Interrupt number Interrupt source HexaDecimal decimal PPG2 114 72 PPG3 115 73 PPG4 116 74 PPG5 117 75 PPG6 118 76 PPG7 119 77 System reserved 120 78 System reserved 121 79 System reserved 122 7A System reserved 123 7B System reserved 124 7C System reserved 125 7D System reserved 126 7E System reserved 127 7F Up/down counter 0 128 80 Up/down counter 1 129 81 System reserved 130 82 System reserved 131 83 Real time clock 132 84 Calibration unit 133 85 A/D converter 0 134 86 System reserved 135 87 System reserved 136 88 System reserved 137 89 Low voltage detection 138 8A System reserved 139 8B Interrupt level Setting register Register address ICR49 471H ICR50 472H ICR51 473H ICR52 474H ICR53 475H ICR54 476H ICR55 477H ICR56 478H ICR57 479H ICR58 47AH ICR59 47BH ICR60 47CH ICR61 47DH ICR62 47EH ICR63 47FH Interrupt vector Resource number[1] Offset Default vector address 234H 000FFE34H 98 230H 000FFE30H 99 22CH 000FFE2CH 100 228H 000FFE28H 101 224H 000FFE24H 102 220H 000FFE20H 103 21CH 000FFE1CH 104 218H 000FFE18H 105 214H 000FFE14H 106 210H 000FFE10H 107 20CH 000FFE0CH 108 208H 000FFE08H 109 204H 000FFE04H 110 200H 000FFE00H 111 1FCH 000FFDFCH - 1F8H 000FFDF8H - 1F4H 000FFDF4H - 1F0H 000FFDF0H - 1ECH 000FFDECH - 1E8H 000FFDE8H - 1E4H 000FFDE4H 14, 112 1E0H 000FFDE0H - 1DCH 000FFDDCH - 1D8H 000FFDD8H - 1D4H 000FFDD4H - 1D0H 000FFDD0H - 1CCH 000FFDCCH - 1C8H 000FFDC8H - 1C4H 000FFDC4H - Time-base overflow 140 8C PLL clock gear 141 8D DMA controller 142 8E Main OSC stability wait 143 8F 1C0H 000FFDC0H - System reserved 144 90 - - 1BCH 000FFDBCH - Used by the INT instruction 145 to 255 91 to FF - - 1B8H to 000H 000FFDB8H to 000FFC00H - 1.The peripheral resources to which RN (Resource Number) is assigned are capable of being DMA transfer activation sources. In addition,  RN respectively corresponds to an IS (Input Source)of the DMAC channel control register A(DMACA0 to DMACA4), and the IS (Input Source) can be obtained by representing RN in a binary number and adding “1” to the head of it. 2.Memory Protection Unit (MPU) support 3.ICR23 can be switched to ICR47 by setting REALOS compatibility bit (address 0C03H ISO[0]). 4.Used by REALOS Document Number: 002-04604 Rev. *C Page 59 of 81 CY91460N Series 15. Electrical Characteristics 15.1 Absolute Maximum Rating Parameter Power supply voltage[1] Symbol Rating Min Max Unit Remarks VCC VSS  0.5 VSS  6.0 V [1] AVCC VSS  0.5 VSS  6.0 V [2] Analog power supply voltage[1] AVRH VSS  0.5 VSS  6.0 V [2] VI VSS  0.3 VCC  0.3 V [3] VIA VSS  0.3 AVCC  0.3 V VO VSS  0.3 VCC  0.3 V [3] ICLAMP  2.0 2.0 mA [4] |ICLAMP| - 20 mA [4] IOL - 10 mA [5] “L” level average output current IOLAV - 4 mA [6] “L” level total maximum output current IOL - 100 mA IOLAV - 50 mA [7] IOH -  10 mA [5] “H” level average output current IOHAV - 4 mA [6] “H” level total maximum output current IOH -  100 mA IOHAV -  20 mA Power consumption PD - 700 mW Operation temperature TA 40 105 °C When using VCC = 3.3 V 40 85 °C When using VCC = 5.0 V  55  125 °C Analog power supply voltage Input voltage [1] Analog pin input voltage[1] Output voltage [1] Maximum clamp current Total maximum clamp current “L” level maximum output current “L” level total average output current “H” level maximum output current “H” level total average output current Storage temperature Tstg [7] 1. The parameter is based on VSS  AVSS  0.0 V. 2. AVCC and AVRH must not exceed VCC  0.3 V, for example, at power on. AVCC must not exceed VCC. 3. VI and VO must not exceed VCC  0.3V. However, when the maximum value of the current to the input or the current from the input is limited by using outside parts, ICLAMP ratings are applied in place of VI ratings. Document Number: 002-04604 Rev. *C Page 60 of 81 CY91460N Series 4. ■ Corresponding pins: Pin name P29_0 to P29_7, P24_0 to P24_7, P22_0 to P22_3, P20_0 to P20_2, P20_4 to P20_6, P15_0 to P15_3, P17_0 to P17_7, P21_0 to P21_2, P21_4 to P21_6, P14_0 to P14_3 ■ Use within recommended operating conditions. ■ Use at DC voltage (current). ■ The  B signal is an input signal exceeding VCC voltage. The  B signal should always be applied by connecting a limiting resistor between the  B signal and the microcontroller. ■ The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values at any time regardless of instantaneously or constantly when the  B signal is input. ■ Note that when the microcontroller drive current is low, such as in the low power consumption modes, the  B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other devices. ■ Note that if the  B signal is input when the microcontroller is off (not fixed at 0 V), since the power is supplied through the pin, the microcontroller may operate incompletely. ■ Note that if the  B signal is input at power-on, since the power is supplied through the pin, the power supply voltage may become the voltage at which a power-on reset does not work. ■ Do not leave  B input pins open. Note that analog input/output pins can input the  B signal only at using as a port. 5. Maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. 6. Average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 100 ms period. 7. Total average output current is defined as the value of the average current flowing through all of the corresponding pins for a 100 ms period. Figure 1. Sample Recommended Circuit : Input/output equivalent circuit Protective diode VCC Limiting resistor P-ch B input (0 V to 16 V) N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-04604 Rev. *C Page 61 of 81 CY91460N Series 15.2 Recommended Operating Conditions (VSS  AVSS  0.0 V) Parameter Symbol VCC Power supply voltage AVCC Smoothing capacitor CS Operating temperature TA Value Unit Remarks Min Max 3.0 3.6 V When using VCC = 3.3 V 4.5 5.5 V When using VCC = 5.0 V 3.0 3.6 V When using VCC = 3.3 V 4.5 5.5 V When using VCC = 5.0 V F Use a ceramic capacitor or a  capacitor that has the similar  frequency characteristics. Use a capacitor with a capacitance greater than CS as the smoothing capacitor on the VCC pin. 4.7 (accuracy within  50) 40 105 C When using VCC = 3.3 V 40 85 C When using VCC = 5.0 V WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. C VSS AVSS CS Document Number: 002-04604 Rev. *C Page 62 of 81 CY91460N Series 15.3 DC Characteristics (VCC  3.0 V to 3.6 V/ 4.5 V to 5.5 V, VSS  AVSS  0 V, TA  40°C to  105°C/40°C to  85°C) Parameter “H” level  input voltage Symbol Pin Name VIHS Port pin VIHC Unit Typ Max When CMOS hysteresis input type1 are selected 0.7 VCC - VCC  0.3 V Port pin When CMOS hysteresis input type2 are selected 0.8 VCC - VCC  0.3 V VIHA Port pin When Automotive inputs are selected 0.8 VCC - VCC  0.3 V VIHT Port pin When TTL input levels are  selected 2.0 - VCC  0.3 V VIH1 MD2 to MD0 0.7 VCC - VCC  0.3 V CMOS level input MD3, INITX CMOS hysteresis input 0.7 VCC - VCC  0.3 V VSS  0.3 - 0.3 VCC V VILS Port pin When CMOS hysteresis  input type1 are selected VILC Port pin When CMOS hysteresis  input type2 are selected VSS  0.3 - 0.2 VCC V VILA Port pin When Automotive inputs are selected VSS  0.3 - 0.5 VCC V VILT Port pin When TTL input levels are  selected VSS  0.3 - 0.8 V VIL1 MD2 to MD0 CMOS level input VSS  0.3 - 0.3 VCC V VSS  0.3 - 0.3 VCC V VCC  0.5 - - V VIL2 “H” level output  voltage Value Min VIH2 “L” level  input  voltage Condition MD3, INITX CMOS hysteresis input VOH1 Port pin VCC  5.0 V, IOH  2.0 mA/ VCC  3.3 V, IOH  1.0 mA VOH2 I2 C common port pin VCC  5.0 V, IOH  3.0 mA/ VCC  3.3 V, IOH  3.0 mA VCC  0.5 - - V Port pin VCC  5.0 V, IOH  5.0 mA/ VCC  3.3 V, IOH  3.0 mA VCC  0.5 - - V VOH3 Document Number: 002-04604 Rev. *C Remarks [1] [1] Page 63 of 81 CY91460N Series (VCC  3.0 V to 3.6 V/ 4.5 V to 5.5 V, VSS  AVSS  0 V, TA  40°C to  105°C/40°C to  85°C) Parameter “L” level output  voltage Input leak current Pull-up resistance value Pull-down  resistance  value Symbol Pin name Condition Value Unit Min Typ Max - - 0.4 V VOL1 Port pin VCC  5.0 V, IOH  2.0 mA/ VCC  3.3 V, IOH  1.0 mA VOL2 I2 C common port pin VCC  5.0 V, IOH  3.0 mA/ VCC  3.3 V, IOH  3.0 mA - - 0.4 V VOL3 Port pin VCC  5.0 V, IOH  5.0 mA/ VCC  3.3 V, IOH  3.0 mA - - 0.4 V IIL - 5 - 5 A RUP Port pin - 25 50 100 k RDOWN Port pin - 25 50 100 k VCC  AVCC  5.0 V, VSS < VI < VCC Document Number: 002-04604 Rev. *C Remarks [1] [1] Page 64 of 81 CY91460N Series (VCC  3.0 V to 3.6 V/ 4.5 V to 5.5 V, VSS  AVSS  0 V, TA  40°C to  105°C/40°C to  85°C) Parameter Symbol Pin name Condition ICC3 VCC ICC5 Input  capacitance Unit Remarks Min Typ Max VCC  3.3 V CPU core: 80 MHz, - 75 102 mA TA  40°C to 105°C VCC VCC  5.0 V CPU core: 80 MHz, - 75 102 mA TA  40°C to 85°C ICCS3 VCC VCC  3.3 V sleep mode - 15 45 mA ICCS5 VCC VCC  5.0 V sleep mode - 15 45 mA VCC VCC  3.3 V stop mode at using RTC) [3] ICTS5 VCC VCC  5.0 V stop mode at using RTC) [3] - 200 ICCH3 VCC VCC  3.3 V stop modeoscillation stop) [4] - 100 ICCH5 VCC VCC  5.0 V stop modeoscillation stop) [4] - 150 ICCF VCC Flash programming (Write/Erase) - CIN Except VCC, AVCC, VSS, AVSS - ICTS3 Power supply current Value - - A TA   25°C When the CR oscillator is  operating and low voltage detection is enabled. 650 A TA   25°C When the CR oscillator is  operating and low voltage detection is enabled. 500 A TA   25°C When the CR oscillator is stopping and low voltage detection is enabled. 600 A TA   25°C When the CR oscillator is stopping and low voltage detection is enabled. 25 50 mA [2] 5 15 pF 100 550 1. The drive power varies depending on the power supply voltage (3.3 V, 5.0 V). 2. The power supply current when writing or erasing by executing the automatic algorithm. 3. When the main clock oscillator is stopped and CR oscillator is operating (using the CR oscillator clock in the RTC) and the low voltage detection is enabled. 4. When the main clock oscillator is stopped, the CR oscillator is stopped and the low voltage detection is enabled. Document Number: 002-04604 Rev. *C Page 65 of 81 CY91460N Series 15.4 AC Characteristics 15.4.1 Clock Timing (VCC  3.0 V to 3.6 V/ 4.5 V to 5.5 V, VSS  AVSS  0 V, TA  40°C to  125°C/40°C to  85°C) Parameter Clock frequency Clock cycle time Symbol FC tC Pin Name Condition Value Unit Remarks Min Typ Max 3.5 4 16 MHz When using the oscillator circuit 3.5 - 32 MHz When using an external clock 62.5 - 285.7 ns When using the oscillator circuit 31.25 - 285.7 ns When using an external clock - - 80 MHz CPU clock, when using PLL[1] Peripheral clock X0, X1 X0, X1 - FCP - FCPP - - - 40 MHz tCP - 12.5 - - ns CPU clock, when using PLL tCPP - 25 - - ns Peripheral clock Input clock pulse width PWH, PWL X0 30 - - ns Input clock rise/fall time tcf, tcr X0 - - 5 ns Internal operation clock  frequency Internal operation clock cycle time 1. When using the clock modulator, set such that the maximum value of the modulated frequency is 96 MHz or less. Figure 2. Clock Timing tC 0.8 VCC 0.2 VCC X0,X1 tcf PWH Document Number: 002-04604 Rev. *C tcr PWL Page 66 of 81 CY91460N Series 15.4.2 Reset Input (VCC  3.0 V to 3.6 V/ 4.5 V to 5.5 V, VSS  AVSS  0 V, TA  40°C to  105°C/40°C to  85°C) Parameter INITX input time (at power-on or stop mode) INITX input time (other than the above) Symbol Pin Name tINTL Value Condition INITX - Unit Min Max Oscillation stabilization time of oscillator  2.6 - ms 20 - s tINTL 0.2VCC INITX 15.4.3 Specification for Power-on (VCC  3.0 V to 3.6 V/ 4.5 V to 5.5 V, VSS  AVSS  0 V, TA  40°C to  105°C/40°C to  85°C) Parameter Symbol Pin Name Condition Power supply rising time tR VCC Power supply start time - Power supply end time - Value Unit Min Max - 0.1 100 ms - - 0.2 - V - - - 0.9 VCC V tR 0.9 VCC VCC Document Number: 002-04604 Rev. *C 0.2 V Page 67 of 81 CY91460N Series 15.4.4 LIN-USART Timing (VCC  3.0 V to 3.6 V/ 4.5 V to 5.5 V, VSS  AVSS  0 V, TA  40°C to  105°C/40°C to  85°C) Parameter Serial clock cycle time SCK ↓→ SOT delay time Symbol Pin Name tSCYC SCK0 to SCK3 tSLOV SCK0 to SCK3, SOT0 to SOT3 Condition Internal shift clock mode Value Unit Min Max 8 tCLKP - ns  80  80 ns 100 - ns Valid SIN → SCK ↑ tIVSH SCK0 to SCK3, SIN0 to SIN3 SCK ↑→ valid SIN hold time tSHIX SCK0 to SCK3, SIN0 to SIN3 60 - ns Serial clock “H” pulse width tSHSL SCK0 to SCK3 4 tCLKP - ns Serial clock “L” pulse width tSLSH SCK0 to SCK3 4 tCLKP - ns SCK ↓→ SOT delay time tSLOV SCK0 to SCK3, SOT0 to SOT3 - 150 ns Valid SIN → SCK ↑ tIVSH SCK0 to SCK3, SIN0 to SIN3 60 - ns SCK ↑→ Valid SIN hold time tSHIX SCK0 to SCK3, SIN0 to SIN3 60 - ns External shift clock mode Notes: ■ Above values are AC characteristics for CLK synchronous mode. ■ tCLKP is the cycle time of the peripheral clock. Document Number: 002-04604 Rev. *C Page 68 of 81 CY91460N Series Figure 3. Internal Shift Clock Mode tSCYC SCK0 to SCK3 VOH VOL VOL tSLOV VOH VOL SOT0 to SOT3 tIVSH tSHIX VIH VIL SIN0 to SIN3 VIH VIL Figure 4. External Shift Clock Mode tSLSH SCK0 to SCK3 tSHSL VOL VOL VOH VOL tSLOV SOT0 to SOT3 VOH VOL tIVSH SIN0 to SIN3 Document Number: 002-04604 Rev. *C VIH VIL tSHIX VIH VIL Page 69 of 81 CY91460N Series 15.4.5 Trigger Input Timing (VCC  3.0 V to 3.6 V/ 4.5 V to 5.5 V, VSS  AVSS  0 V, TA  40°C to  105°C/40°C to  85°C) Parameter Symbol Pin Name tTRGH tTRGL INT0 to INT7 INT12, INT13 External interrupt input pulse width Value Min Max 4 tCLKP - Unit ns Note: tCLKP is the cycle time of the peripheral clock. tTRGH VIH tTRGL VIH INT0 to INT7 INT12, INT13 VIL VIL 15.4.6 Timer Related Resource Input Timing (VCC  3.0 V to 3.6 V/ 4.5 V to 5.5 V, VSS  AVSS  0 V, TA  40°C to  105°C/40°C to  85°C) Parameter Symbol Value Pin Name Min Max Unit Free-run timer input clock pulse width CK0 to CK3 4 tCLKP  ns Up/down counter input pulse width AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 4 tCLKP  ns Reload timer input pulse width TIN0 to TIN3 4 tCLKP  ns Input capture input pulse width ICU0 to ICU3 4 × tCLKP  ns tTIWH tTIWL Note: tCLKP is the cycle time of the peripheral clock. tTIWH CK0 to CK3 AIN0, BIN0, ZIN0 AIN1, BIN1, ZIN1 TIN0 to TIN3 ICU0 to ICU3 VIH Document Number: 002-04604 Rev. *C tTIWL VIH VIL VIL Page 70 of 81 CY91460N Series 15.4.7 I2C Timing (VCC  3.0 V to 3.6 V/ 4.5 V to 5.5 V, VSS  AVSS  0 V, TA  40 C to  105 C/40 C to  85 C) Parameter Symbol Pin Name Condition Standard Mode Fast Mode [1] Min Max Min Max Unit SCL clock frequency fSCL 0 100 0 400 kHz “L” width of the SCL clock tLOW 4.7  1.3  s “H” width of the SCL clock tHIGH 4.0  0.6  s Bus free time between STOP and START conditions tBUS 4.7  1.3  s SCL ↑→ SDA output delay time tDLDAT  5 × tCLKP  5 × tCLKP ns Setup time for a repeated START condition SCL ↑→ SDA ↓ tSUSTA 4.7  0.6  s Hold time for a repeated START condition SDA ↓→ SCL↓ tHDSTA 4.0  0.6  s Setup time for STOP condition SCL ↑→ SDA ↑ tSUSTO 4.0  0.6  s SDA data input hold time SCL ↓→ SDA ↓↑ tHDDAT 2 × tCLKP  2 × tCLKP  s SDA data input setup time SDA ↓↑ → SCL ↑ tSUDAT 250  100  ns SDA2, SDA3, SCL2, SCL3 R  1 k, C  50 pF[2] 1. For use at over 100 kHz, set the peripheral clock to at least 6 MHz. 2. R and C are the pull-up resistance and load capacitance of the SCL and SDA lines. Note: tCLKP is the cycle time of the peripheral clock. SDA2, SDA3 tBUS tSUDAT tLOW tHDSTA SCL2, SCL3 tHDSTA tHIGH tHDDAT Document Number: 002-04604 Rev. *C tSUSTA tSUSTO Page 71 of 81 CY91460N Series 15.5 Electrical Characteristics for A/D Converter (VCC  3.0 V to 3.6 V/ 4.5 V to 5.5 V, VSS  AVSS  0 V, TA  40 C to  105 C/40 C to  85 C) Parameter Resolution Total error[1] Linearity error[1] Differential linearity Zero transition error[1] voltage[1] Full scale transition voltage[1] Symbol Pin Name  Value Unit Typ Max    10 bit     3 LSB      2.5 LSB      1.9 LSB VOT AN0 to AN7 AVSS1.5 LSB AVSS0.5 LSB AVSS2.5 LSB V VFST AN0 to AN7 AVRH3.5 LSB AVRH1.5 LSB AVRH0.5 LSB V 1 [2]   s Using at 5 V [2]   s Using at 3.3 V   Analog port input current IAIN AN0 to AN7   10 A Analog input voltage Conversion time Remarks Min 3 VAIN AN0 to AN7 AVSS  AVRH V Reference voltage  AVRH AVSS  AVCC V Analog power supply current (analog + digital) IA AVCC  2.4 4.7 mA Reference voltage supply  current IR AVRH  0.65 1.0 mA Analog input equivalent  capacitance Cin AN0 to AN7   8.5 pF Analog input equivalent  resistance Rin AN0 to AN7   2.6 k AVcc  4.5 V   12.1 k AVcc  3.0 V Output impedance of analog signal source Rext    4.2 k Including  reference supply 1. Measured in the CPU sleep state 2. Set no shorter than this time period in the peripheral clock and conversion setting register Document Number: 002-04604 Rev. *C Page 72 of 81 CY91460N Series 15.6 Notes on the A/D Converter The diagram below shows the equivalent circuit of the sampling circuit in the A/D converter. Apply the output impedance in the external circuit for the analog output under the following conditions. ■ The recommended output impedance for the external circuit is 4.2 k or less. ■ If an external capacitor is used, remember to consider the capacitive voltage divider effect due to the external capacitor and the internal capacitor in the chip. Accordingly, an external capacitance several thousand times that of the internal capacitance is recommended. ■ The analog voltage sampling period may be too short if the output impedance of the external circuit is high.In this case, select Rext and Tsamp to satisfy the following condition. Rext  Tsamp/ (7  Cin)  Rin Rext: Tsamp: Cin: Rin: Output impedance of the analog signal source Sampling time Equivalent capacitance of analog input Equivalent resistance of analog input Input impedance Analog signal source Rext Analog input pin Analog SW Rin:12.1 kW (Max) Cin:8.5 pF (Max) A/D converter CY91460N series Document Number: 002-04604 Rev. *C Page 73 of 81 CY91460N Series 15.7 Definition of A/D Converter Terms Resolution Analog variation that is recognizable by an A/D converter. ■ Linearity error Deviation between actual conversion characteristics and a straight line connecting zero transition point  (00 0000 0000  00 0000 0001) and full scale transition point (11 1111 1110  11 1111 1111). ■ Differential linearity error Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. ■ Total error This error indicates the difference between actual and theoretical values, including the zero transition error/full scale transition error/linearity error. ■ Total error 3FFH Digital output 3FEH 1.5 LSB Actual conversion characteristics 3FDH {1 LSB (N − 1) + 0.5 LSB} 004H VNT (measurement value) 003H Actual conversion characteristics 002H Ideal characteristics 001H 0.5 LSB' AVSS 1LSB' (ideal value)  Analog input AVRH  AVSS 1024 Total error of digital output N  AVRH [V] VNT  {1 LSB'  (N  1)  0.5 LSB'} 1 LSB' N: A/D converter digital output value VOT' (ideal value)  AVSS  0.5 LSB' [V] VFST' (ideal value)  AVRH  1.5 LSB' [V] VNT: A voltage at which digital output transits from (N  1) to N (Continued) Document Number: 002-04604 Rev. *C Page 74 of 81 CY91460N Series Linearity error 3FFH Differential linearity error Actual conversion characteristics Actual conversion characteristics 3FEH N+1 {1 LSB (N − 1) + VOT} VFST Digital output 004H VNT (measure- ment value) 003H Digital output (measure- ment value) 3FDH Ideal characteristics N N-1 VFST Actual conversion characteristics 002H VNT (measure- ment value) Ideal characteristics 001H N-2 Actual conversion characteristics VOT (measurement value) AVSS AVRH AVSS Analog input Linearity error of digital output N  Differential linearity error of digital output N  1LSB  VFST  VOT 1022 (measure- ment value) AVRH Analog input VNT  {1LSB  (N  1)  VOT} 1LSB V (N  1) T  VNT 1LSB [LSB]  1 [LSB] [V] N: A/D converter digital output value VOT : A voltage at which digital output transits from 000H to 001H. VFST : A voltage at which digital output transits from 3FEH to 3FFH. Document Number: 002-04604 Rev. *C Page 75 of 81 CY91460N Series 15.8 Flash Memory Program/Erase Characteristics Parameter Conditions Unit Remarks 3.6 s Excludes programming prior to erasure 9  s Excludes programming prior to erasure  23 370 s Except for the overhead time of the  system level  10000   cycle Average TA   85 C 20   year Min Typ Max  0.9 TA   25 C VCC  5.0 V  Sector erase time Chip erase time Word (16-bit width) programming time Program/Erase cycle Flash memory data retention time Value [1] 1. The value is translated high-temperature measurement results of the technology reliability evaluation into average value at  85 C. Document Number: 002-04604 Rev. *C Page 76 of 81 CY91460N Series 16. Ordering Information Part Number Package Remarks CY91F463NAPMC-GS-UJE1 64-pin plastic LQFP (LQG064) Lead-free package CY91F463NCPMC-GS-UJE1 64-pin plastic LQFP (LQG064) Lead-free package Document Number: 002-04604 Rev. *C Page 77 of 81 CY91460N Series 17. Package Dimension 48 E1 E 3 % 0.75 0.50 0.70 ș 0° 8° 2 7  ( 1 $ / 3  * 1 , 7 $ ( 6 < ( +' 72 % 0  2( 5* )$ . ( & &$ 13 $ 7( 6+ , 7 '  ) ( 2 + 77 1 6 , $2 3 '  (7 16 , ( ) (: '2 / 6  , (   + $7        Page 78 of 81 Document Number: 002-04604 Rev. *C ' $ ( /  ( + 7  )  23 , 7 1  2' ,$ 7 &( / ( 6( + 7 $7 / )0 2 ( 5 +) 7 P 2 7P  <   / 3 3' $1 $ 6  1P 2P , 6  1 (  01 ,( ' ( ( 6: (7 +( % 7       0.60 0.30 5 $E1 % 2 0'  $(' '(( &7 ( ;$ +( & 7 2 2  7/ 1  2( ,+% 7 6  8'7 , 2 5: 7 1 2' 1 5$$ (& 3/  5 5 ( (+ $ %7 %7 0 2 0 $($2 '6')  8 '   ( '$P$ & P( 8 / /7  &2 ( 11+  ,/ 1 7  7 /  2$$5 + 2 1+7  6( 6 6 8 ( , 5 262' ' 0$ 1 5 E