Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY91460P Series
FR60 32-bit Microcontroller
CY91460P series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control applications which require
high-speed real-time processing, such as consumer devices and on-board vehicle systems. This series uses the FR60 CPU, which
is compatible with the FR family of CPUs.
This series contains the LIN-USART and CAN controllers.
Features
FR60 CPU core
■
32-bit RISC, load/store architecture, five-stage pipeline
■
16-bit fixed-length instructions (basic instructions)
■
Instruction execution speed: 1 instruction per cycle
■
Instructions including memory-to-memory transfer, bit
manipulation, and barrel shift instructions: Instructions suitable
for embedded applications
■
Function entry/exit instructions and register data multi-load
store instructions : Instructions supporting C language
■
Register interlock function: Facilitating assembly-language
coding
■
Built-in multiplier with instruction-level support
❐ Signed 32-bit multiplication: 5 cycles
❐ Signed 16-bit multiplication: 3 cycles
■
Interrupts (save PC/PS) : 6 cycles (16 priority levels)
■
Harvard architecture enabling program access and data
access to be performed simultaneously
■
Instructions compatible with the FR family
■
Bit search module (for REALOS)
❐ Function to search the first bit position of “1”, “0”, “changed”
from the MSB (most significant bit) within one word
■
LIN-USART (full duplex double buffer): 12 channels, 4
channels with FIFO *
❐ Clock synchronous/asynchronous selectable
❐ Sync-break detection
❐ Internal dedicated baud rate generator
■
■
CAN controller (C-CAN): up to 4 channels
❐ Maximum transfer speed: 1 Mbps
❐ 32 transmission/reception message buffers
■
Sound generator : 1 channel
❐ Tone frequency : PWM frequency divide-by-two
(reload value + 1)
■
16-bit PPG timer : 32 channels *
■
16-bit PFM timer : 1 channel
■
16-bit reload timer: 16 channels
❐ 8 reload timers can be used as up to 4 32-bit reload timers
(by cascading 2 reload timers each).
■
16-bit free-run timer: 8 channels (1 channel each for ICU and
OCU)
■
Input capture: 8 channels (operates in conjunction with the
free-run timer)
■
Output compare: 8 channels (operates in conjunction with the
free-run timer)
■
Up/Down counter: 4 channels (4*8-bit or 2*16-bit) *
■
Watchdog timer
■
Real-time clock
■
Low-power consumption modes : Sleep/stop mode function
■
Low voltage detection circuit
■
Clock supervisor
❐ Monitors the sub-clock (32 kHz) and the main clock
(4 MHz) , and switches to a recovery clock (CR oscillator,
etc.) when the oscillations stop.
Internal peripheral resources
■
General-purpose ports : Maximum 141 ports
■
DMAC (DMA Controller)
❐ Maximum of 5 channels able to operate simultaneously
❐ 2 transfer sources (internal peripheral/software)
❐ Activation source can be selected using software
❐ Addressing mode specifies full 32-bit addresses
(increment/decrement/fixed)
❐ Transfer mode (demand transfer/burst transfer/step
transfer/block transfer)
❐ Transfer data size selectable from 8/16/32-bit
❐ Multi-byte transfer enabled (by software)
❐ DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H)
■
■
A/D converter (successive approximation type)
❐ 10-bit resolution: maximum 41 channels *
❐ Conversion time: minimum 1 μs
I2C bus interface (supports 400 kbps): 4 channels
❐ Master/slave transmission and reception
❐ Arbitration function, clock synchronization function
External interrupt inputs : 16 channels *
2
❐ 9 channels shared with CAN RX or I C pins
Note: * The maximum channel count is given; the real number depends on port multiplexing.
Cypress Semiconductor Corporation
Document Number: 002-04619 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 18, 2018
CY91460P Series
■
Clock modulator
■
Clock monitor
■
Sub-clock calibration
❐ Corrects the real-time clock timer when operating with the
32 kHz or CR oscillator
■
Main oscillator stabilization timer
❐ Generates an interrupt in sub-clock mode after the
stabilization wait time has elapsed on the 23-bit stabilization
wait time counter
Document Number: 002-04619 Rev. *B
■
Sub-oscillator stabilization timer
❐ Generates an interrupt in main clock mode after the
stabilization wait time has elapsed on the 15-bit stabilization
wait time counter
Package and technology
■
Package : QFP-176
■
CMOS 0.18 μm technology
■
Power supply range 3 V to 5 V (1.8 V internal logic provided by
a step-down voltage converter)
■
Operating temperature range: between − 40°C and + 125°C
Page 2 of 193
CY91460P Series
Contents
Product Lineup ................................................................. 4
Pin Assignment ................................................................ 7
CY91F465PA .............................................................. 7
CY91F467PA .............................................................. 8
Pin Description ................................................................. 9
CY91F465PA, CY91F467PA ...................................... 9
I/O Circuit Types ............................................................. 23
Port Multiplexing ............................................................ 29
PPMUX Register ....................................................... 29
PPMUX2 Register (CY91F467PA) ............................ 29
Multiplex Pinout CY91F465PA .................................. 30
Multiplex Pinout CY91F467PA .................................. 31
Reload Timer / New Features ........................................ 32
Overview ................................................................... 32
Features .................................................................... 32
Registers ................................................................... 33
Cascading Operation ................................................. 35
Additional PPGs ............................................................. 36
Register ..................................................................... 36
A/D Converter / New Features (CY91F467PA) ............. 38
A/D Converter Features ............................................ 38
Analog Input Connections ......................................... 38
A/D Converter / Range Comparator (CY91F467PA) .... 40
Overview of A/D Converter and
A/D Range Comparator ............................................. 40
A/D Converter Input Impedance ................................ 41
Block Diagram of A/D Converter ............................... 42
Registers of the A/D Converter ................................. 43
Range Comparator .................................................... 53
Operation of A/D Converter ....................................... 60
ADC Interrupt Generation and DMA Access ............. 63
Handling Devices ............................................................ 64
Preventing Latch-up .................................................. 64
Handling of unused input pins ................................... 64
Power supply pins ..................................................... 64
Crystal oscillator circuit .............................................. 64
Notes on using external clock ................................... 64
Mode pins (MD_x) ..................................................... 65
Notes on operating in PLL clock mode ...................... 65
Pull-up control ........................................................... 65
Notes on Debugger ........................................................ 66
Execution of the RETI Command .............................. 66
Break function ........................................................... 66
Operand break .......................................................... 66
Notes on PS register ................................................. 66
Document Number: 002-04619 Rev. *B
Block Diagram ................................................................ 67
CY91F465PA, CY91F467PA .................................... 67
CPU and Control Unit ..................................................... 68
Features .................................................................... 68
Internal architecture ................................................... 68
Programming model .................................................. 69
Registers ................................................................... 70
Embedded Program/Data Memory (Flash) ................... 73
Flash features ............................................................ 73
Operation modes: ...................................................... 73
Flash access in CPU mode ....................................... 74
Parallel Flash programming mode ............................ 78
Poweron Sequence in parallel programming mode .. 79
Flash Security ............................................................ 80
Notes About Flash Memory CRC Calculation ........... 82
Embedded Data Flash (CY91F467PA) .......................... 83
Data Flash Features .................................................. 83
Data Flash Block Diagram ......................................... 83
Data Flash Operation Modes .................................... 84
Data Flash access in CPU mode .............................. 85
Data Flash Registers ................................................. 88
Data Flash Interrupts and DMA Access .................... 94
Data Flash parallel programming mode .................... 95
Data Flash Security ................................................... 97
Memory Space .............................................................. 101
Memory Maps ................................................................ 102
CY91F465PA, CY91F467PA .................................. 102
I/O Map ........................................................................... 103
CY91F465PA, CY91F467PA .................................. 103
Flash Memory, Data Flash and External Bus Area . 138
Data Flash memory sector organisation .................. 140
Interrupt Vector Table .................................................. 141
Recommended Settings ............................................... 146
PLL and Clockgear settings .................................... 146
Clock Modulator settings ......................................... 147
Electrical Characteristics ............................................. 152
Absolute maximum ratings ...................................... 152
Recommended operating conditions ....................... 155
DC characteristics ................................................... 156
A/D converter characteristics .................................. 160
FLASH memory program/erase characteristics ...... 164
AC characteristics ................................................... 166
Ordering Information .................................................... 188
Package Dimension ...................................................... 189
Revision History ........................................................... 190
Major Changes .............................................................. 191
Document History ......................................................... 192
Page 3 of 193
CY91460P Series
1. Product Lineup
Emulation Devices
Feature
CY91F465PA
CY91F467PA
100 MHz
100 MHz
100 MHz
40 MHz
50 MHz
50 MHz
50 MHz
40 MHz
50 MHz
50 MHz
50 MHz
Max. CAN frequency (CLKCAN)
20 MHz
50 MHz
50 MHz
50 MHz
Max. FlexRay frequency (SCLK)
-
-
-
-
0.35μm
0.18μm
0.18μm
0.18μm
yes
yes
yes
yes
yes (disengageable)
yes
yes
yes
yes
yes
yes
yes
Reset input (INITX)
yes
yes
yes
yes
Hardware standby input (HSTX)
yes
no
no
no
Clock Modulator
yes
yes
yes
yes
Clock Monitor
yes
yes
yes
yes
CY91V460A
CY91FV460B
Max. core frequency (CLKB)
80 MHz
Max. resource frequency (CLKP)
Max. external bus frequency
(CLKT)
Technology
Watchdog timer
Watchdog timer (RC osc. based)
Bit Search
Low Power Mode
yes
yes
yes
yes
DMA
5 ch
5 ch
5 ch
5 ch
MPU (16 ch)*1
MPU (16 ch)*1
MPU (8 ch)*1
MPU (8 ch)*1
Emulation SRAM
32bit read data
Internal Flash memory
2112KB +
external emulation
SRAM with 64bit read
data
544 KByte
1088 KByte
Satellite Flash memory
-
Data Flash 64 KByte
-
Data Flash 64 KByte
Flash Protection
-
yes
yes
yes
D-RAM
64 KByte
64 KByte
24 KByte
48 KByte
ID-RAM
64 KByte
64 KByte
16 KByte
32 KByte
Flash-Cache (Instruction cache)
16 KByte
16 KByte
8 KByte
8 KByte
4 KByte fixed
16 KByte Boot Flash
4 KByte
4 KByte
1 ch
1 ch
1 ch
1 ch
MMU/MPU
Flash memory
Boot-ROM / BI-ROM
RTC
ch*2
8 ch*2
Free Running Timer
8 ch
12 ch
8
ICU
8 ch
10 ch
8 ch*2
8 ch*2
OCU
8 ch
8 ch
8 ch*2
8 ch*2
Reload Timer
8 ch
16 ch
16 ch
16 ch
2
32 ch*2
PPG 16-bit
16 ch
32 ch
32 ch*
PFM 16-bit
1 ch
1 ch
1 ch
1 ch
Sound Generator
1 ch
1 ch
1 ch
1 ch
Document Number: 002-04619 Rev. *B
Page 4 of 193
CY91460P Series
Emulation Devices
Feature
Up/Down Counter (8/16 bit)
C_CAN
CY91F465PA
CY91F467PA
4 ch (8-bit) / 2 ch
(16-bit)
4 ch (8-bit) / 2 ch
(16-bit)*2
4 ch (8-bit) / 2 ch
(16-bit)*2
6 ch (128msg)
3 ch (32msg)
4 ch (32msg)
CY91V460A
CY91FV460B
4 ch (8-bit) / 2 ch
(16-bit)
6 ch (128msg)
2
8 ch + 4 ch FIFO*2
(2 more pin
relocations)
LIN-USART
4 ch + 4 ch FIFO + 8 ch
16 ch FIFO
8 ch + 4 ch FIFO*
I2C (400K)
4 ch
8 ch
4 ch*2
4 ch*2
yes (32bit addr, 32bit
data)
yes (32bit addr, 32bit
data)
yes (24bit addr, 16bit
data)
yes (24bit addr, 16bit
data)
External Interrupts
16 ch
16 ch
16 ch*2
16 ch*2
NMI Interrupts
1 ch
1 ch
1 ch
1 ch
General I/O ports
288
328 (24 non-multiplexed)
141
141
SMC
6 ch
328 (24 non-multiplexed)
-
-
LCD controller (40x4)
1 ch
1 ch
-
-
ADC (10-bit)
32 ch
32 ch + 22 ch
(2 ADC macros)
32 ch*2
32 ch *2 + 9 ch
(2 ADC macros)
Alarm Comparator
2 ch
2 ch
-
-
Supply Supervisor (low voltage
detection)
yes
yes
yes
yes
Clock Supervisor
yes
yes
yes
yes
Main clock oscillator
4 MHz
4 MHz
4 MHz
4 MHz
Sub clock oscillator
32kHz
32kHz
32kHz
32kHz
RC oscillator
100kHz
100kHz / 2MHz
100kHz / 2MHz
100kHz / 2MHz
PLL
x 20
x 25
x 25
x 25
DSU4
yes
yes
FR external bus
EDSU
Supply voltage
yes (32
BP)*1
yes (32 BP)
no
*1
no
*1
yes (16 BP)
yes (16 BP)*1
3V/5V
3V/5V
3V/5V
3V/5V
Regulator
yes
yes
yes
yes
Power consumption
n.a.
n.a.
< 1.4 W
< 1.4 W
0..70 C
0..70 C
-40..125 C
-40..125 C
Temperature Range (Ta)
Document Number: 002-04619 Rev. *B
Page 5 of 193
CY91460P Series
Feature
Emulation Devices
CY91F465PA
CY91F467PA
BGA896
LQFP-176
LQFP-176
< 20 ms
< 20 ms
< 20 ms
< 20 ms
n.a.
< 8 sec. typical
< 5 sec. typical
< 6 sec. typical
CY91V460A
CY91FV460B
Package
BGA660
Power on to PLL run
Flash Download Time
*1: MPU channels use EDSU breakpoint registers (shared operation between MPU and EDSU).
*2: Maximum channel count is shown; function is multiplexed with external bus addresses.
Document Number: 002-04619 Rev. *B
Page 6 of 193
CY91460P Series
2. Pin Assignment
2.1 CY91F465PA
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VDD35
P32_7/PPG31
P32_3/PPG30
P33_7/PPG29
P33_3/PPG28
P07_7/A7 or P26_7/AN31
P07_6/A6 or P26_6/AN30
P07_5/A5 or P26_5/AN29
P07_4/A4 or P26_4/AN28
P07_3/A3 or P26_3/AN27
P07_2/A2 or P26_2/AN26
P07_1/A1 or P26_1/AN25
P07_0/A0 or P26_0/AN24
P20_6/SCK3/ZIN1/CK3 or P27_7/AN23
P20_5/SOT3/BIN1 or P27_6/AN22
P20_4/SIN3/AIN1 or P27_5/AN21
P20_2/SCK2/ZIN0/CK2 or P27_4/AN20
P20_1/SOT2/BIN0 or P27_3/AN19
P20_0/SIN2/AIN0 or P27_2/AN18
P16_1/PPG9 or P27_1/AN17
P16_0/PPG8 or P27_0/AN16
VSS5
VDD5
P24_7/INT7/SCL3 or P28_7/AN15
P24_6/INT6/SDA3 or P28_6/AN14
P24_5/INT5/SCL2 or P28_5/AN13
P24_4/INT4/SDA2 or P28_4/AN12
P24_3/INT3 or P28_3/AN11
P24_2/INT2 or P28_2/AN10
P24_1/INT1 or P28_1/AN9
P24_0/INT0 or P28_0/AN8
P29_7/AN7
P29_6/AN6
P35_6/SCK9 or P29_5/AN5
P35_5/SOT9 or P29_4/AN4
P35_4/SIN9 or P29_3/AN3
P35_2/SCK8 or P29_2/AN2
P35_1/SOT8 or P29_1/AN1
P35_0/SIN8 or P29_0/AN0
P34_7/PPG27
P34_3/PPG26
P35_7/PPG25
P35_3/PPG24
VSS5
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
QFP-176
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VDD5
AVCC5
AVRH5
AVSS5
P25_1
P25_0
P17_7/PPG7
P17_6/PPG6
P17_5/PPG5
P18_6/SCK7/ZIN3/CK7
P18_5/SOT7/BIN3
P18_4/SIN7/AIN3
P18_2/SCK6/ZIN2/CK6
P18_1/SOT6/BIN2
P18_0/SIN6/AIN2
P19_6/SCK5/CK5
P19_5/SOT5
P19_4/SIN5
P19_2/SCK4/CK4
P19_1/SOT4
P19_0/SIN4
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X0
X1
MD_3
MONCLK
MD_2
MD_1
MD_0
P23_7
P23_6/INT11
P23_5/TX2
P23_4/RX2/INT10
VSS5
VSS5
P30_0/PPG16
P30_1/PPG17
P30_2/PPG18
P30_3/PPG19
P10_0/SYSCLK
P10_1/ASX
P10_3/WEX
P09_0/CSX0
P09_1/CSX1
P09_2/CSX2
P08_0/WRX0
P08_1/WRX1
P08_4/RDX
P08_7/RDY
P16_2/PPG10
P16_3/PPG11
P16_4/PPG12/SGA
P16_5/PPG13/SGO
P16_6/PPG14/PFM
P16_7/PPG15/AGTX
VDD5
VSS5
P23_0/RX0/INT8
P23_1/TX0
P23_2/RX1/INT9
P23_3/TX1
P22_4/SDA0/INT14
P22_5/SCL0
P22_6/SDA1/INT15
P22_7/SCL1
P14_0/ICU0/TIN8/0/TTG24/16/8/0
P14_1/ICU1/TIN9/1/TTG25/17/9/1
P14_2/ICU2/TIN10/2/TTG26/18/10/2
P14_3/ICU3/TIN11/3/TTG27/19/11/3
P15_0/OCU0/TOT0
P15_1/OCU1/TOT1
P15_2/OCU2/TOT2
P15_3/OCU3/TOT3
P30_4/PPG20
P30_5/PPG21
P30_6/PPG22
P30_7/PPG23
VDD5
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VSS5
P21_4/SIN1
P21_5/SOT1
P21_6/SCK1/CK1
P21_7
P06_0/A8 or P21_0/SIN0
P06_1/A9 or P21_1/SOT0
P06_2/A10 or P21_2/SCK0/CK0
P06_3/A11 or P17_4/PPG4
P06_4/A12 or P14_4/ICU4/TIN12/4/TTG28/20/12/4
P06_5/A13 or P14_5/ICU5/TIN13/5/TTG29/21/13/5
P06_6/A14 or P14_6/ICU6/TIN14/6/TTG30/22/14/6
P06_7/A15 or P14_7/ICU7/TIN15/7/TTG31/23/15/7
P05_0/A16 or P16_0/PPG8
P05_1/A17 or P16_1/PPG9
P05_2/A18 or (P20_0/SIN2/AIN0 or P34_0/SIN10)
P05_3/A19 or (P20_1/SOT2/BIN0 or P34_1/SOT10)
P05_4/A20 or (P20_2/SCK2/ZIN0/CK2 or P34_2/SCK10)
P05_5/A21 or (P20_4/SIN3/AIN1 or P34_4/SIN11)
P05_6/A22 or (P20_5/SOT3/BIN1 or P34_5/SOT11)
P05_7/A23 or (P20_6/SCK3/ZIN1/CK3 or P34_6/SCK11)
VDD35
VSS5
P01_0/D16 or P17_0/PPG0
P01_1/D17 or P17_1/PPG1
P01_2/D18 or P17_2/PPG2
P01_3/D19 or P17_3/PPG3
P01_4/D20 or P15_4/OCU4/TOT4
P01_5/D21 or P15_5/OCU5/TOT5
P01_6/D22 or P15_6/OCU6/TOT6
P01_7/D23 or P15_7/OCU7/TOT7
P00_0/D24 or P24_0/INT0
P00_1/D25 or P24_1/INT1
P00_2/D26 or P24_2/INT2
P00_3/D27 or P24_3/INT3
P00_4/D28 or P24_4/INT4
P00_5/D29 or P24_5/INT5
P00_6/D30 or P24_6/INT6
P00_7/D31 or P24_7/INT7
P22_0/INT12
P22_1
P22_2/INT13
P22_3
VDD35
Document Number: 002-04619 Rev. *B
Page 7 of 193
CY91460P Series
2.2 CY91F467PA
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VDD35
P32_7/PPG31
P32_3/PPG30
P33_7/PPG29
P33_3/PPG28
P07_7/A7 or P26_7/AN31
P07_6/A6 or P26_6/AN30
P07_5/A5 or P26_5/AN29
P07_4/A4 or P26_4/AN28
P07_3/A3 or P26_3/AN27
P07_2/A2 or P26_2/AN26
P07_1/A1 or P26_1/AN25
P07_0/A0 or P26_0/AN24
P20_6/SCK3/ZIN1/CK3 or P27_7/AN23
P20_5/SOT3/BIN1 or P27_6/AN22
P20_4/SIN3/AIN1 or P27_5/AN21
P20_2/SCK2/ZIN0/CK2 or P27_4/AN20
P20_1/SOT2/BIN0 or P27_3/AN19
P20_0/SIN2/AIN0 or P27_2/AN18
P16_1/PPG9 or P27_1/AN17
P16_0/PPG8 or P27_0/AN16
VSS5
VDD5
P24_7/INT7/SCL3 or P28_7/AN15
P24_6/INT6/SDA3 or P28_6/AN14
P24_5/INT5/SCL2 or P28_5/AN13
P24_4/INT4/SDA2 or P28_4/AN12
P24_3/INT3 or P28_3/AN11
P24_2/INT2 or P28_2/AN10
P24_1/INT1 or P28_1/AN9
P24_0/INT0 or P28_0/AN8
P29_7/AN7
P29_6/AN6
P35_6/SCK9 or P29_5/AN5
P35_5/SOT9 or P29_4/AN4
P35_4/SIN9 or P29_3/AN3
P35_2/SCK8 or P29_2/AN2
P35_1/SOT8 or P29_1/AN1
P35_0/SIN8 or P29_0/AN0
P34_7/PPG27
P34_3/PPG26
P35_7/PPG25
P35_3/PPG24
VSS5
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
QFP-176
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VDD5
AVCC5
AVRH5
AVSS5
P25_1
P25_0
P17_7/PPG7/AN39
P17_6/PPG6/AN38
P17_5/PPG5/AN37
P18_6/SCK7/ZIN3/CK7/AN46
P18_5/SOT7/BIN3/AN45
P18_4/SIN7/AIN3/AN44
P18_2/SCK6/ZIN2/CK6/AN42
P18_1/SOT6/BIN2/AN41
P18_0/SIN6/AIN2/AN40
P19_6/SCK5/CK5
P19_5/SOT5
P19_4/SIN5
P19_2/SCK4/CK4
P19_1/SOT4
P19_0/SIN4
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X1
X0
MD_3
MONCLK
MD_2
MD_1
MD_0
P23_7/TX3
P23_6/RX3/INT11
P23_5/TX2
P23_4/RX2/INT10
VSS5
VSS5
P30_0/PPG16
P30_1/PPG17
P30_2/PPG18
P30_3/PPG19
P10_0/SYSCLK or P34_0/SIN10
P10_1/ASX or P34_1/SOT10
P10_3/WEX or P34_2/SCK10
P09_0/CSX0 or P34_4/SIN11
P09_1/CSX1 or P34_5/SOT11
P09_2/CSX2 or P34_6/SCK11
P08_0/WRX0
P08_1/WRX1
P08_4/RDX
P08_7/RDY
P16_2/PPG10
P16_3/PPG11
P16_4/PPG12/SGA
P16_5/PPG13/SGO
P16_6/PPG14/PFM
P16_7/PPG15/AGTX
VDD5
VSS5
P23_0/RX0/INT8
P23_1/TX0
P23_2/RX1/INT9
P23_3/TX1
P22_4/SDA0/INT14
P22_5/SCL0
P22_6/SDA1/INT15
P22_7/SCL1
P14_0/ICU0/TIN8/0/TTG24/16/8/0
P14_1/ICU1/TIN9/1/TTG25/17/9/1
P14_2/ICU2/TIN10/2/TTG26/18/10/2
P14_3/ICU3/TIN11/3/TTG27/19/11/3
P15_0/OCU0/TOT0
P15_1/OCU1/TOT1
P15_2/OCU2/TOT2
P15_3/OCU3/TOT3
P30_4/PPG20
P30_5/PPG21
P30_6/PPG22
P30_7/PPG23
VDD5
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VSS5
P21_4/SIN1
P21_5/SOT1
P21_6/SCK1/CK1
P21_7
P06_0/A8 or P21_0/SIN0
P06_1/A9 or P21_1/SOT0
P06_2/A10 or P21_2/SCK0/CK0
P06_3/A11 or P17_4/PPG4
P06_4/A12 or P14_4/ICU4/TIN12/4/TTG28/20/12/4
P06_5/A13 or P14_5/ICU5/TIN13/5/TTG29/21/13/5
P06_6/A14 or P14_6/ICU6/TIN14/6/TTG30/22/14/6
P06_7/A15 or P14_7/ICU7/TIN15/7/TTG31/23/15/7
P05_0/A16 or P16_0/PPG8
P05_1/A17 or P16_1/PPG9
P05_2/A18 or (P20_0/SIN2/AIN0 or P34_0/SIN10)
P05_3/A19 or (P20_1/SOT2/BIN0 or P34_1/SOT10)
P05_4/A20 or (P20_2/SCK2/ZIN0/CK2 or P34_2/SCK10)
P05_5/A21 or (P20_4/SIN3/AIN1 or P34_4/SIN11)
P05_6/A22 or (P20_5/SOT3/BIN1 or P34_5/SOT11)
P05_7/A23 or (P20_6/SCK3/ZIN1/CK3 or P34_6/SCK11)
VDD35
VSS5
P01_0/D16 or P17_0/PPG0
P01_1/D17 or P17_1/PPG1
P01_2/D18 or P17_2/PPG2
P01_3/D19 or P17_3/PPG3
P01_4/D20 or P15_4/OCU4/TOT4
P01_5/D21 or P15_5/OCU5/TOT5
P01_6/D22 or P15_6/OCU6/TOT6
P01_7/D23 or P15_7/OCU7/TOT7
P00_0/D24 or P24_0/INT0
P00_1/D25 or P24_1/INT1
P00_2/D26 or P24_2/INT2
P00_3/D27 or P24_3/INT3
P00_4/D28 or P24_4/INT4
P00_5/D29 or P24_5/INT5
P00_6/D30 or P24_6/INT6
P00_7/D31 or P24_7/INT7
P22_0/INT12
P22_1
P22_2/INT13
P22_3
VDD35
The pinout of CY91F467PA differs versus CY91F465PA at the following pins:
• Pins 50-55:
Added re-located LIN-USART10/11
• Pins 92-93:
Added CAN3 RX3,TX3
• Pins 118-126:
Added ADC channels AN37-42, AN44-46
• Pins 99-100:
X0/X1 are mirrored
Document Number: 002-04619 Rev. *B
Page 8 of 193
CY91460P Series
3. Pin Description
3.1 CY91F465PA, CY91F467PA
Pin no.
2
3
Pin name
P21_4
SIN1
P21_5
SOT1
I/O
I/O circuit
type*1
Mux
I/O
A
—
I/O
A
—
P21_6
4
SCK1
5
P21_7
A8
I/O
A
—
I/O
A
—
Data input pin of USART1
General-purpose input/output port
Data output pin of USART1
I/O
A
PPMUX.PS4=0
Clock input/output pin of USART1
External clock input pin of free-run timer 1
6
General-purpose input/output port
General-purpose input/output port
Signal pin of external address bus (bit8)
OR
P21_0
SIN0
P06_1
A9
I/O
A
PPMUX.PS4=1
I/O
A
PPMUX.PS4=0
7
General-purpose input/output port
Data input pin of USART0
General-purpose input/output port
Signal pin of external address bus (bit9)
OR
P21_1
SOT0
P06_2
A10
8
General-purpose input/output port
General-purpose input/output port
CK1
P06_0
Function
I/O
A
PPMUX.PS4=1
I/O
A
PPMUX.PS4=0
General-purpose input/output port
Data output pin of USART0
General-purpose input/output port
Signal pin of external address bus (bit10)
OR
P21_2
SCK0
General-purpose input/output port
I/O
A
PPMUX.PS4=1
CK0
P06_3
A11
Clock input/output pin of USART0
External clock input pin of free-run timer 0
I/O
A
9
PPMUX.PS4=0
General-purpose input/output port
Signal pin of external address bus (bit11)
OR
P17_4
PPG4
Document Number: 002-04619 Rev. *B
I/O
A
PPMUX.PS4=1
General-purpose input/output port
Output pin of PPG timer
Page 9 of 193
CY91460P Series
Pin no.
Pin name
I/O
I/O circuit
type*1
Mux
I/O
A
PPMUX.PS4=0
P06_4 to P06_7
A12 to A15
Function
General-purpose input/output ports
Signal pins of external address bus (bit12 to
bit15)
OR
10 to 13
P14_4 to P14_7
General-purpose input/output ports
ICU4 to ICU7
TIN12/4 to
TIN15/7
Input capture input pins
I/O
A
PPMUX.PS4=1
TTG28/20/12/4 to
TTG31/23/15/7
External trigger input pins of PPG timer
P05_0
A16
External trigger input pins of reload timer
General-purpose input/output port
I/O
A
14
PPMUX.PR10=0
Signal pin of external address bus (bit16 to
bit17)
OR
P16_0
PPG8
I/O
A
PPMUX.PR10=1
I/O
A
PPMUX.PR11=0
P05_1
A17
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
15
Signal pin of external address bus (bit16 to
bit17)
OR
P16_1
PPG9
P05_2
A18
I/O
A
PPMUX.PR11=1
I/O
A
PPMUX.PR12=0
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Signal pin of external address bus (bit18)
OR
P20_0
16
SIN2
I/O
A
AIN0
General-purpose input/output port
PPMUX.PR12=1 and
Data input pin of USART2
PPMUX.PRPS0=1
Up/down counter input pin
OR
P34_0
SIN10
P05_3
A19
I/O
A
I/O
A
PPMUX.PR12=1 and General-purpose input/output port
PPMUX.PRPS0=0 Data input pin of USART10
PPMUX.PR13=0
General-purpose input/output port
Signal pin of external address bus (bit19)
OR
P20_1
17
SOT2
I/O
A
BIN0
General-purpose input/output port
PPMUX.PR13=1 and
Data output pin of USART2
PPMUX.PRPS0=1
Up/down counter input pin
OR
P34_1
SOT10
Document Number: 002-04619 Rev. *B
I/O
A
PPMUX.PR13=1 and General-purpose input/output port
PPMUX.PRPS0=0 Data output pin of USART10
Page 10 of 193
CY91460P Series
Pin no.
Pin name
P05_4
A20
I/O
I/O circuit
type*1
Mux
I/O
A
PPMUX.PR14=0
Function
General-purpose input/output port
Signal pin of external address bus (bit20)
OR
P20_2
18
SCK2
ZIN0
General-purpose input/output port
I/O
A
PPMUX.PR14=1 and Clock input/output pin of USART2
PPMUX.PRPS0=1 Up/down counter input pin
CK2
External clock input pin of free-run timer 2
OR
P34_2
SCK10
P05_5
A21
I/O
A
I/O
A
PPMUX.PR14=1 and General-purpose input/output port
PPMUX.PRPS0=0 Clock input/output pin of USART10
PPMUX.PR15=0
General-purpose input/output port
Signal pin of external address bus (bit21)
OR
P20_4
19
SIN3
I/O
A
AIN1
General-purpose input/output port
PPMUX.PR15=1 and
Data input pin of USART3
PPMUX.PRPS0=1
Up/down counter input pin
OR
P34_4
SIN11
P05_6
A22
I/O
A
I/O
A
PPMUX.PR15=1 and General-purpose input/output port
PPMUX.PRPS0=0 Data input pin of USART11
PPMUX.PR16=0
General-purpose input/output port
Signal pin of external address bus (bit22)
OR
P20_5
20
SOT3
I/O
A
BIN1
General-purpose input/output port
PPMUX.PR16=1 and
Data output pin of USART3
PPMUX.PRPS0=1
Up/down counter input pin
OR
P34_5
SOT11
P05_7
A23
I/O
A
I/O
A
PPMUX.PR16=1 and General-purpose input/output port
PPMUX.PRPS0=0 Data output pin of USART11
PPMUX.PR17=0
General-purpose input/output port
Signal pin of external address bus (bit23)
OR
General-purpose input/output port
P20_6
21
SCK3
ZIN1
I/O
A
PPMUX.PR17=1 and Clock input/output pin of USART3
PPMUX.PRPS0=1 Up/down counter input pin
CK3
External clock input pin of free-run timer 3
OR
P34_6
SCK11
Document Number: 002-04619 Rev. *B
I/O
A
PPMUX.PR17=1 and General-purpose input/output port
PPMUX.PRPS0=0 Clock input/output pin of USART11
Page 11 of 193
CY91460P Series
Pin no.
Pin name
P01_0 to P01_3
D16 to D19
I/O
I/O circuit
type*1
Mux
I/O
A
PPMUX.PS3=0
24 to 27
PPG0 to PPG3
P01_4 to P01_7
D20 to D23
I/O
A
PPMUX.PS3=1
I/O
A
PPMUX.PS3=0
P15_4 to P15_7
P00_0 to P00_7
D24 to D31
I/O
A
INT0 to INT7
46 to 49
General-purpose input/output ports
Signal pins of external data bus (bit20 to bit23)
PPMUX.PS3=1
Output compare output pins
I/O
A
PPMUX.PR0=0
General-purpose input/output ports
Signal pins of external data bus (bit24 to bit31)
OR
P24_0 to P24_7
43
Output pins of PPG timer
Reload timer output pins
32 to 39
42
General-purpose input/output ports
General-purpose input/output ports
TOT4 to TOT7
41
Signal pins of external data bus (bit16 to bit19)
OR
OCU4 to OCU7
40
General-purpose input/output ports
OR
P17_0 to P17_3
28 to 31
Function
P22_0
INT12
P22_1
P22_2
INT13
P22_3
P30_0 to P30_3
PPG16 to PPG19
P10_0
SYSCLK
I/O
A
PPMUX.PR0=1
I/O
A
—
I/O
A
—
I/O
A
—
I/O
A
—
I/O
A
—
I/O
A
—
50
General-purpose input/output ports
External interrupt input pins
General-purpose input/output port
External interrupt input pin
General-purpose input/output port
General-purpose input/output port
External interrupt input pin
General-purpose input/output port
General-purpose input/output ports
Output pins of PPG timer
General-purpose input/output port
External bus clock output pin
OR (CY91F467PA only)
P34_0
SIN10
P10_1
ASX
I/O
A
PPMUX2.PR0=1
I/O
A
—
51
General-purpose input/output port
Data input pin of USART10
General-purpose input/output port
Address strobe output pin
OR (CY91F467PA only)
P34_1
SOT10
P10_3
WEX
I/O
A
PPMUX2.PR1=1
I/O
A
—
52
General-purpose input/output port
Data output pin of USART10
General-purpose input/output port
Write enable output pin
OR (CY91F467PA only)
P34_2
SCK10
Document Number: 002-04619 Rev. *B
I/O
A
PPMUX2.PR2=1
General-purpose input/output port
Clock input/output pin of USART10
Page 12 of 193
CY91460P Series
Pin no.
Pin name
P09_0
CSX0
I/O
I/O circuit
type*1
Mux
I/O
A
—
53
SIN11
P09_1
CSX1
I/O
A
PPMUX2.PR3=1
I/O
A
—
54
SOT11
P09_2
CSX2
I/O
A
PPMUX2.PR4=1
I/O
A
—
55
P34_6
60, 61
P08_0, P08_1
WRX0, WRX1
P08_4
RDX
P08_7
RDY
P16_2, P16_3
PPG10, PPG11
I/O
A
PPMUX2.PR5=1
I/O
A
—
I/O
A
—
I/O
A
—
I/O
A
—
P16_4
62
63
PPG12
I/O
A
—
General-purpose input/output port
Data output pin of USART11
General-purpose input/output port
Chip select output pin
General-purpose input/output port
Clock input/output pin of USART11
General-purpose input/output ports
External write strobe output pins
General-purpose input/output port
External read strobe output pin
General-purpose input/output port
External ready input pin
General-purpose input/output ports
Output pins of PPG timer
Output pin of PPG timer
SGA output pin of sound generator
General-purpose input/output port
PPG13
I/O
A
—
PPG14
PPG15
Output pin of PPG timer
SGO output pin of sound generator
General-purpose input/output port
I/O
A
—
Output pin of PPG timer
Pulse frequency modulator output pin
P16_7
General-purpose input/output port
I/O
A
—
Output pin of PPG timer
ATGX
A/D converter external trigger input pin
P23_0
General-purpose input/output port
RX0
I/O
A
—
INT8
69
Chip select output pin
SGA
PFM
68
General-purpose input/output port
P16_5
P16_6
65
Data input pin of USART11
General-purpose input/output port
SGO
64
General-purpose input/output port
OR (CY91F467PA only)
SCK11
59
Chip select output pin
OR (CY91F467PA only)
P34_5
58
General-purpose input/output port
OR (CY91F467PA only)
P34_4
56, 57
Function
P23_1
TX0
Document Number: 002-04619 Rev. *B
RX input pin of CAN0
External interrupt input pin
I/O
A
—
General-purpose input/output port
TX output pin of CAN0
Page 13 of 193
CY91460P Series
Pin no.
Pin name
I/O
I/O circuit
type*1
Mux
P23_2
70
RX1
General-purpose input/output port
I/O
A
—
INT9
71
P23_3
TX1
SDA0
I/O
A
—
I/O
C
—
P22_5
SCL0
SDA1
I/O
C
—
P22_7
SCL1
I/O
C
—
I/O
C
—
80 to 83
A
—
General-purpose input/output ports
OCU0 to OCU3
I/O
A
—
P30_4 to P30_7
PPG20 to PPG23
RX2
P23_5
TX2
RX3
P23_7
TX3
Output compare output pins
Reload timer output pins
I/O
A
—
I/O
A
—
General-purpose input/output ports
Output pins of PPG timer
General-purpose input/output port
RX input pin of CAN2
External interrupt input pin
I/O
A
—
General-purpose input/output port
TX output pin of CAN2
General-purpose input/output ports
I/O
A
—
INT11
93
External trigger input pins of reload timer
P15_0 to P15_3
P23_6
92
I2C bus clock input/output pin (open drain)
External trigger input pins of PPG timer
INT10
91
General-purpose input/output port
TTG24/16/8/0 to
TTG27/19/11/3
P23_4
90
I2C bus DATA input/output pin (open drain)
Input capture input pins
I/O
TOT0 to TOT3
84 to 87
I2C bus clock input/output pin (open drain)
General-purpose input/output ports
ICU0 to ICU3
TIN8/0 to TIN11/3
General-purpose input/output port
External interrupt input pin
P14_0 to P14_3
76 to 79
I2C bus DATA input/output pin (open drain)
General-purpose input/output port
INT15
75
TX output pin of CAN1
External interrupt input pin
P22_6
74
General-purpose input/output port
General-purpose input/output port
INT14
73
RX input pin of CAN1
External interrupt input pin
P22_4
72
Function
RX input pin of CAN3 *4
External interrupt input pin
I/O
A
—
General-purpose input/output port
TX output pin of CAN3 *4
94
MD_0
I
G
—
Mode setting pin
95
MD_1
I
G
—
Mode setting pin
96
MD_2
I
G
—
Mode setting pin
97
MONCLK
O
M
—
Clock Monitor pin
98
MD_3
I
G
—
Fast clock input pin
Document Number: 002-04619 Rev. *B
Page 14 of 193
CY91460P Series
I/O
I/O circuit
type*1
Mux
—
J1
—
—
J1
—
X0A
—
J2
—
103
X1A
—
J2
—
Sub clock (oscillation) output
104
INITX
I
H
—
External reset input pin
105
NMIX
I
H
—
Non-maskable interrupt input pin
I/O
A
—
I/O
A
—
Pin no.
99
100
102
112
113
Pin name
X1
X0
X0
X1
P19_0
SIN4
P19_1
SOT4
P19_2
114
SCK4
116
P19_4
SIN5
P19_5
SOT5
I/O
A
—
SCK5
I/O
A
—
I/O
A
—
I/O
A
—
CK5
SIN6
AIN2
BIN2
I/O
—
Data input pin of USART4
General-purpose input/output port
Data output pin of USART4
Clock input/output pin of USART4
General-purpose input/output port
Data input pin of USART5
General-purpose input/output port
Data output pin of USART5
Clock input/output pin of USART5
Data input pin of USART6
Up/down counter input pin
Analog input pin of A/D converter 2 *3
I/O
A
or
B *2
—
Data output pin of USART6
Up/down counter input pin
AN41
Analog input pin of A/D converter 2 *3
P18_2
General-purpose input/output port
ZIN2
I/O
CK6
A
or
B *2
Clock input/output pin of USART6
—
External clock input pin of free-run timer 6
P18_4
SIN7
AIN3
AN44
Document Number: 002-04619 Rev. *B
Up/down counter input pin
Analog input pin of A/D converter 2 *3
AN42
121
General-purpose input/output port
General-purpose input/output port
SCK6
120
Sub clock (oscillation) input
General-purpose input/output port
A
or
B *2
P18_1
SOT6
Clock (oscillation) output, F467PA
External clock input pin of free-run timer 5
AN40
119
Clock (oscillation) input, F465PA
General-purpose input/output port
P18_0
118
Clock (oscillation) input, F467PA
External clock input pin of free-run timer 4
P19_6
117
Clock (oscillation) output, F465PA
General-purpose input/output port
CK4
115
Function
General-purpose input/output port
I/O
A
or
B *2
—
Data input pin of USART7
Up/down counter input pin
Analog input pin of A/D converter 2 *3
Page 15 of 193
CY91460P Series
Pin no.
Pin name
I/O
I/O circuit
type*1
I/O
A
or
B *2
Mux
P18_5
122
SOT7
BIN3
General-purpose input/output port
—
P18_6
General-purpose input/output port
SCK7
ZIN3
I/O
CK7
A
or
B *2
Clock input/output pin of USART7
—
Analog input pin of A/D converter 2 *3
P17_5 to P17_7
PPG5 to PPG7
134
135
136
137
P25_0, P25_1
P35_3
PPG24
P35_7
PPG25
P34_3
PPG26
P34_7
PPG27
P35_0
SIN8
General-purpose input/output ports
A
or
B *2
—
I/O
A
—
I/O
A
—
I/O
A
—
I/O
A
—
I/O
A
—
I/O
B
PPMUX.PS5=0
I/O
AN37 to AN39
127, 128
Up/down counter input pin
External clock input pin of free-run timer 7
AN46
124 to 126
Data output pin of USART7
Up/down counter input pin
Analog input pin of A/D converter 2 *3
AN45
123
Function
138
Output pin of PPG timer
Analog input pins of A/D converter 2 *3
General-purpose input/output ports
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Data input pin of USART8
OR
P29_0
AN0
P35_1
SOT8
I/O
I/O
B
B
139
PPMUX.PS5=1
PPMUX.PS5=0
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Data output pin of USART8
OR
P29_1
AN1
P35_2
SCK8
I/O
B
PPMUX.PS5=1
I/O
B
PPMUX.PS5=0
140
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Clock input/output pin of USART8
OR
P29_2
AN2
Document Number: 002-04619 Rev. *B
I/O
B
PPMUX.PS5=1
General-purpose input/output port
Analog input pin of A/D converter
Page 16 of 193
CY91460P Series
Pin no.
Pin name
P35_4
SIN9
I/O
I/O circuit
type*1
Mux
I/O
B
PPMUX.PS5=0
141
AN3
P35_5
SOT9
I/O
B
PPMUX.PS5=1
I/O
B
PPMUX.PS5=0
142
AN4
P35_6
SCK9
I/O
I/O
B
B
143
AN5
P29_6, P29_7
AN6, AN7
P24_0 to P24_3
INT0 to INT3
PPMUX.PS5=1
PPMUX.PS5=0
I/O
B
PPMUX.PS5=1
I/O
B
—
I/O
B
146 to 149
Analog input pin of A/D converter
General-purpose input/output port
Data output pin of USART9
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Clock input/output pin of USART9
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output ports
Analog input pins of A/D converter
PPMUX.PS2=0 and General-purpose input/output ports
PPMUX.PR0=0
External interrupt input pins
OR
P28_0 to P28_3
AN8 to AN11
P24_4
INT4
SDA2
I/O
B
I/O
D
I/O
D
PPMUX.PS2=1 or
PPMUX.PR0=1
General-purpose input/output ports
Analog input pins of A/D converter
General-purpose input/output port
PPMUX.PS2=0 and
External interrupt input pin
PPMUX.PR0=0
I2C bus DATA input/output pin (open drain)
OR
P28_4
AN12
P24_5
INT5
SCL2
I/O
D
I/O
D
I/O
D
PPMUX.PS2=1 or
PPMUX.PR0=1
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
PPMUX.PS2=0 and
External interrupt input pin
PPMUX.PR0=0
I2C bus clock input/output pin (open drain)
OR
P28_5
AN13
I/O
D
P24_6
INT6
152
General-purpose input/output port
OR
P29_5
151
Data input pin of USART9
OR
P29_4
150
General-purpose input/output port
OR
P29_3
144, 145
Function
I/O
D
SDA3
PPMUX.PS2=1 or
PPMUX.PR0=1
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
PPMUX.PS2=0 and
External interrupt input pin
PPMUX.PR0=0
I2C bus DATA input/output pin (open drain)
OR
P28_6
AN14
Document Number: 002-04619 Rev. *B
I/O
D
PPMUX.PS2=1 or
PPMUX.PR0=1
General-purpose input/output port
Analog input pin of A/D converter
Page 17 of 193
CY91460P Series
Pin no.
Pin name
I/O
I/O circuit
type*1
P24_7
INT7
153
I/O
C
SCL3
Mux
Function
General-purpose input/output port
PPMUX.PS2=0 and
External interrupt input pin
PPMUX.PR0=0
I2C bus clock input/output pin (open drain)
OR
P28_7
AN15
P16_0
PPG8
I/O
B
I/O
A
156
PPMUX.PS2=1 or
PPMUX.PR0=1
General-purpose input/output port
Analog input pin of A/D converter
PPMUX.PS1=0 and General-purpose input/output port
PPMUX.PR10=0 Output pin of PPG timer
OR
P27_0
AN16
P16_1
PPG9
I/O
A
I/O
A
157
PPMUX.PS1=1 or
PPMUX.PR10=1
General-purpose input/output port
Analog input pin of A/D converter
PPMUX.PS1=0 and General-purpose input/output port
PPMUX.PR11=0 Output pin of PPG timer
OR
P27_1
AN17
I/O
PPMUX.PS1=1 or
PPMUX.PR11=1
A
PPMUX.PS1=0
General-purpose input/output port
and_not
Data input pin of USART2
(PPMUX.PR12=1
and
Up/down counter input pin
PPMUX.PRPS0=1)
A
PPMUX.PS1=1 or General-purpose input/output port
(PPMUX.PR12=1
and
Analog input pin of A/D converter
PPMUX.PRPS0=1)
A
PPMUX.PS1=0
General-purpose input/output port
and_not
Data output pin of USART2
(PPMUX.PR13=1
and
Up/down counter input pin
PPMUX.PRPS0=1)
P20_0
SIN2
I/O
General-purpose input/output port
A
AIN0
158
Analog input pin of A/D converter
OR
P27_2
AN18
I/O
P20_1
SOT2
I/O
BIN0
159
OR
P27_3
AN19
Document Number: 002-04619 Rev. *B
I/O
A
PPMUX.PS1=1 or General-purpose input/output port
(PPMUX.PR13=1
and
Analog input pin of A/D converter
PPMUX.PRPS0=1)
Page 18 of 193
CY91460P Series
Pin no.
Pin name
I/O
I/O circuit
type*1
Mux
A
PPMUX.PS1=0
and_not
(PPMUX.PR14=1
and
PPMUX.PRPS0=1)
P20_2
SCK2
ZIN0
160
I/O
CK2
General-purpose input/output port
Clock input/output pin of USART2
Up/down counter input pin
External clock input pin of free-run timer 2
OR
P27_4
AN20
I/O
A
PPMUX.PS1=1 or General-purpose input/output port
(PPMUX.PR14=1
and
Analog input pin of A/D converter
PPMUX.PRPS0=1)
A
PPMUX.PS1=0
General-purpose input/output port
and_not
Data input pin of USART3
(PPMUX.PR15=1
and
Up/down counter input pin
PPMUX.PRPS0=1)
P20_4
SIN3
I/O
AIN1
161
OR
P27_5
AN21
I/O
A
PPMUX.PS1=1 or General-purpose input/output port
(PPMUX.PR15=1
and
Analog input pin of A/D converter
PPMUX.PRPS0=1)
A
PPMUX.PS1=0
General-purpose input/output port
and_not
Data output pin of USART3
(PPMUX.PR16=1
and
Up/down counter input pin
PPMUX.PRPS0=1)
P20_5
SOT3
I/O
BIN1
162
OR
P27_6
AN22
I/O
A
PPMUX.PS1=1 or General-purpose input/output port
(PPMUX.PR16=1
and
Analog input pin of A/D converter
PPMUX.PRPS0=1)
A
PPMUX.PS1=0
and_not
(PPMUX.PR17=1
and
PPMUX.PRPS0=1)
P20_6
SCK3
ZIN1
163
Function
I/O
CK3
General-purpose input/output port
Clock input/output pin of USART3
Up/down counter input pin
External clock input pin of free-run timer 3
OR
P27_7
AN23
P07_0
A0
I/O
A
I/O
A
PPMUX.PS1=1 or General-purpose input/output port
(PPMUX.PR17=1
and
Analog input pin of A/D converter
PPMUX.PRPS0=1)
PPMUX.PS0=0
General-purpose input/output port
Signal pin of external address bus (bit0)
OR
164
P26_0
AN24
Document Number: 002-04619 Rev. *B
I/O
A
PPMUX.PS0=1
General-purpose input/output port
Analog input pin of A/D converter
Page 19 of 193
CY91460P Series
Pin no.
Pin name
P07_1
A1
I/O
I/O circuit
type*1
Mux
I/O
A
PPMUX.PS0=0
165
AN25
P07_2
A2
I/O
A
PPMUX.PS0=1
I/O
A
PPMUX.PS0=0
166
Signal pin of external address bus (bit1)
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Signal pin of external address bus (bit2)
OR
P26_2
AN26
P07_3
A3
I/O
A
PPMUX.PS0=1
I/O
A
PPMUX.PS0=0
167
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Signal pin of external address bus (bit3)
OR
P26_3
AN27
P07_4
A4
I/O
A
PPMUX.PS0=1
I/O
A
PPMUX.PS0=0
168
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Signal pin of external address bus (bit4)
OR
P26_4
AN28
P07_5
A5
I/O
A
PPMUX.PS0=1
I/O
A
PPMUX.PS0=0
169
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Signal pin of external address bus (bit5)
OR
P26_5
AN29
P07_6
A6
I/O
A
PPMUX.PS0=1
I/O
A
PPMUX.PS0=0
170
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Signal pin of external address bus (bit6)
OR
P26_6
AN30
P07_7
A7
I/O
A
PPMUX.PS0=1
I/O
A
PPMUX.PS0=0
171
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Signal pin of external address bus (bit7)
OR
P26_7
AN31
173
General-purpose input/output port
OR
P26_1
172
Function
P33_3
PPG28
P33_7
PPG29
Document Number: 002-04619 Rev. *B
I/O
A
PPMUX.PS0=1
I/O
A
—
I/O
A
—
General-purpose input/output port
Analog input pin of A/D converter
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Output pin of PPG timer
Page 20 of 193
CY91460P Series
Pin no.
174
175
*1:
*2:
*3:
*4:
Pin name
P32_3
PPG30
P32_7
PPG31
I/O
I/O circuit
type*1
Mux
I/O
A
—
I/O
A
—
Function
General-purpose input/output port
Output pin of PPG timer
General-purpose input/output port
Output pin of PPG timer
For information about the I/O circuit type, refer to “4. I/O Circuit Types”.
CY91F465PA has type A, CY91F467PA has type B
A/D converter channels 37-42, 44-46 only available on CY91F467PA.
CAN3 only available on CY91F467PA.
Document Number: 002-04619 Rev. *B
Page 21 of 193
CY91460P Series
[Power supply/Ground pins]
Pin no.
Pin name
1, 23, 45, 67, 89, 101, 106,
111, 133, 155
VSS5
I/O
Function
Ground pins
66, 88, 110, 132, 154
VDD5
108, 109
VDD5R
129
AVSS5
131
AVCC5
Power supply pin for A/D converter
130
AVRH5
Reference power supply pin for A/D converter
107
VCC18C
Capacitor connection pin for internal regulator
22, 44, 176
VDD35
Document Number: 002-04619 Rev. *B
Power supply pins
Power supply pins for internal regulator
Supply
Analog ground pin for A/D converter
Power supply pins for external bus part of I/O ring
Page 22 of 193
CY91460P Series
4. I/O Circuit Types
Type
Circuit
Remarks
pull-up control
driver strength
control
data line
pull- down control
R
A
CMOS hysteresis type1
CMOS hysteresis type2
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Automotive inputs
TTL input
standby control for
input shutdown
pull-up control
driver strength
control
data line
pull- down control
R
B
CMOS hysteresis type1
CMOS hysteresis type2
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
Automotive inputs
TTL input
standby control for
input shutdown
analog input
Document Number: 002-04619 Rev. *B
Page 23 of 193
CY91460P Series
Type
Circuit
Remarks
pull-up control
data line
pull- down control
R
C
CMOS hysteresis type1
CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
pull-up control
data line
pull- down control
R
D
CMOS hysteresis type1
CMOS hysteresis type2
CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
Automotive inputs
TTL input
standby control for
input shutdown
analog input
Document Number: 002-04619 Rev. *B
Page 24 of 193
CY91460P Series
Type
Circuit
Remarks
pull-up control
driver strength
control
data line
pull- down control
R
E
CMOS hysteresis type1
CMOS hysteresis type2
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA,
and IOL = 30mA, IOH = -30mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Automotive inputs
TTL input
standby control for
input shutdown
pull-up control
driver strength
control
data line
pull- down control
R
F
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA,
and IOL = 30mA, IOH = -30mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
TTL input
standby control for
input shutdown
analog input
Document Number: 002-04619 Rev. *B
Page 25 of 193
CY91460P Series
Type
Circuit
Remarks
R
G
Hysteresis
inputs
CMOS Hysteresis input pin
Pull-up resistor value: 50 kΩ approx.
Pull-up
Resistor
H
Mask ROM and EVA device:
CMOS Hysteresis input pin
Flash device:
CMOS input pin
12 V withstand (for MD [2:0])
R
Hysteresis
inputs
X1
R
0
J1
Xout
1
FCI
R
High-speed oscillation circuit:
• Programmable between oscillation mode
(external crystal or resonator connected
to X0/X1 pins) and
Fast external Clock Input (FCI) mode
(external clock connected to X0 pin)
• Feedback resistor = approx. 2 * 0.5 MΩ.
Feedback resistor is grounded in the center when the
oscillator is disabled or in FCI mode.
X0
FCI or osc disable
Xout
X1A
R
Low-speed oscillation circuit:
• Feedback resistor = approx. 2 * 5 MΩ.
Feedback resistor is grounded in the center when the
oscillator is disabled.
J2
R
X0A
osc disable
Document Number: 002-04619 Rev. *B
Page 26 of 193
CY91460P Series
Type
Circuit
Remarks
pull-up control
driver strength
control
data line
pull- down control
R
CMOS hysteresis type1
K
CMOS hysteresis type2
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
LCD SEG/COM output
Automotive inputs
TTL input
standby control for
input shutdown
LCD SEG/COM
pull-up control
driver strength
control
data line
pull- down control
R
L
CMOS hysteresis type1
CMOS hysteresis type2
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function)
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
LCD Voltage input
Automotive inputs
TTL input
standby control for
input shutdown
VLCD
Document Number: 002-04619 Rev. *B
Page 27 of 193
CY91460P Series
Type
Circuit
Remarks
tri-state control
M
N
Document Number: 002-04619 Rev. *B
data line
analog input line
CMOS level tri-state output
(IOL = 5mA, IOH = -5mA)
Analog input pin with protection
Page 28 of 193
CY91460P Series
5. Port Multiplexing
5.1 PPMUX Register
CY91460P series uses port multiplexing. This means that there are more implemented resources than actual pins. Which ports/
resources are multiplexed to which pin depends on the PPMUX register setting.
0x049A
0x049B
15
14
13
12
11
10
9
8
PR17
PR16
PR15
PR14
PR13
PR12
PR11
PR10
7
6
5
4
3
2
1
0
PRPS0
PR0
PS5
PS4
PS3
PS2
PS1
PS0
The PPMUX register can only be written as a half-word. It is writable only once.
The PPMUX register is reset by INIT or by a soft reset (the initial value is 0x0000 then).
Note: Port relocation (via PRx) always has higher priority than Port Switching (via PSx).
5.2 PPMUX2 Register (CY91F467PA)
CY91F467PA has a second port multiplexing register, PPMUX2, for multiplexing of LIN-USART10,11.
The settings of PPMUX2 have priority over the settings of PPMUX.
0x049C
0x049D
15
14
13
12
11
10
9
8
-
-
PR5
PR4
PR3
PR2
PR1
PR0
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
The PPMUX2 register can only be written as a half-word. It is writable only once.
The PPMUX2 register is reset by INIT or by a soft reset (the initial value is 0x00 then).
Document Number: 002-04619 Rev. *B
Page 29 of 193
CY91460P Series
5.3 Multiplex Pinout CY91F465PA
if ANxx channel is enabled
(via PFR & EPFR), pin is
switched to analogue input,
digital input is then disabled
(independant of
PPMUX.PS/PR bits)
1 configbit
(PPMUX.PS2) to
switch between
the two port
layouts
if ANxx channel is enabled
(via PFR), pin is switched to
analogue input, digital input
is then disabled
(independant of
PPMUX.PS/PR bits)
1 configbit
(PPMUX.PS5) to
switch between
the two port
layouts
PPG16-31
peripheral not
supported by
CY91V460A, but
portfunction
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PPG16-31
peripheral not
supported by
CY91V460A, but
portfunction
1 configbit
(PPMUX.PS1) to
switch between
the two port
layouts
if ANxx channel is enabled
(via PFR) pin is switched to
analogue input, digital input
is then disabled
(independant of
PPMUX.PS/PR bits)
VDD35
P32_7/PPG31
P32_3/PPG30
P33_7/PPG29
P33_3/PPG28
P07_7/A7 or P26_7/AN31
P07_6/A6 or P26_6/AN30
P07_5/A5 or P26_5/AN29
P07_4/A4 or P26_4/AN28
P07_3/A3 or P26_3/AN27
P07_2/A2 or P26_2/AN26
P07_1/A1 or P26_1/AN25
P07_0/A0 or P26_0/AN24
P20_6/SCK3/ZIN1/CK3 or P27_7/AN23
P20_5/SOT3/BIN1 or P27_6/AN22
P20_4/SIN3/AIN1 or P27_5/AN21
P20_2/SCK2/ZIN0/CK2 or P27_4/AN20
P20_1/SOT2/BIN0 or P27_3/AN19
P20_0/SIN2/AIN0 or P27_2/AN18
P16_1/PPG9 or P27_1/AN17
P16_0/PPG8 or P27_0/AN16
VSS5
VDD5
P24_7/INT7/SCL3 or P28_7/AN15
P24_6/INT6/SDA3 or P28_6/AN14
P24_5/INT5/SCL2 or P28_5/AN13
P24_4/INT4/SDA2 or P28_4/AN12
P24_3/INT3 or P28_3/AN11
P24_2/INT2 or P28_2/AN10
P24_1/INT1 or P28_1/AN9
P24_0/INT0 or P28_0/AN8
P29_7/AN7
P29_6/AN6
P35_6/SCK9 or P29_5/AN5
P35_5/SOT9 or P29_4/AN4
P35_4/SIN9 or P29_3/AN3
P35_2/SCK8 or P29_2/AN2
P35_1/SOT8 or P29_1/AN1
P35_0/SIN8 or P29_0/AN0
P34_7/PPG27
P34_3/PPG26
P35_7/PPG25
P35_3/PPG24
VSS5
1 configbit
(PPMUX.PS0) to
switch between
the two port
layouts
if ANxx channel is enabled
(via PFR & EPFR), pin is
switched to analogue input,
digital input is then disabled
(independant of
PPMUX.PS/PR bits)
1 configbit
(PPMUX.PS4) to
switch between
external bus
(default)
or peripheral
function
(all 8 pins)
1 configbit
(PPMUX.PRPS0) to
determine wether
PPMUX.PR17 to
PPMUX.PR12
relocate pins from
P20 or switch Pins
to P34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1 configbyte (PPMUX.PR17 to
PPMUX.PR10) to relocate
peripheral function (all 8 pins,
but not ANxx), external bus
function is disabled when
relocated
1 configbit (PPMUX.PR0) to
relocate peripheral function
(all 8 pins, but not ANxx and
not I2C), external bus function
is disabled when relocated
QFP-176
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VDD5
AVCC5
AVRH5
AVSS5
P25_1
P25_0
P17_7/PPG7
P17_6/PPG6
P17_5/PPG5
P18_6/SCK7/ZIN3/CK7
P18_5/SOT7/BIN3
P18_4/SIN7/AIN3
P18_2/SCK6/ZIN2/CK6
P18_1/SOT6/BIN2
P18_0/SIN6/AIN2
P19_6/SCK5/CK5
P19_5/SOT5
P19_4/SIN5
P19_2/SCK4/CK4
P19_1/SOT4
P19_0/SIN4
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X0
X1
MD_3
MONCLK
MD_2
MD_1
MD_0
P23_7
P23_6/INT11
P23_5/TX2
P23_4/RX2/INT10
VSS5
PPG16-31
peripheral not
supported by
CY91V460A,
but portfunction
Document Number: 002-04619 Rev. *B
VSS5
P30_0/PPG16
P30_1/PPG17
P30_2/PPG18
P30_3/PPG19
P10_0/SYSCLK
P10_1/ASX
P10_3/WEX
P09_0/CSX0
P09_1/CSX1
P09_2/CSX2
P08_0/WRX0
P08_1/WRX1
P08_4/RDX
P08_7/RDY
P16_2/PPG10
P16_3/PPG11
P16_4/PPG12/SGA
P16_5/PPG13/SGO
P16_6/PPG14/PFM
P16_7/PPG15/AGTX
VDD5
VSS5
P23_0/RX0/INT8
P23_1/TX0
P23_2/RX1/INT9
P23_3/TX1
P22_4/SDA0/INT14
P22_5/SCL0
P22_6/SDA1/INT15
P22_7/SCL1
P14_0/ICU0/TIN8/0/TTG24/16/8/0
P14_1/ICU1/TIN9/1/TTG25/17/9/1
P14_2/ICU2/TIN10/2/TTG26/18/10/2
P14_3/ICU3/TIN11/3/TTG27/19/11/3
P15_0/OCU0/TOT0
P15_1/OCU1/TOT1
P15_2/OCU2/TOT2
P15_3/OCU3/TOT3
P30_4/PPG20
P30_5/PPG21
P30_6/PPG22
P30_7/PPG23
VDD5
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
1 configbit
(PPMUX.PS3) to
switch between
external bus
(default) or
peripheral
function
(all 8 pins)
VSS5
P21_4/SIN1
P21_5/SOT1
P21_6/SCK1/CK1
P21_7
P06_0/A8 or P21_0/SIN0
P06_1/A9 or P21_1/SOT0
P06_2/A10 or P21_2/SCK0/CK0
P06_3/A11 or P17_4/PPG4
P06_4/A12 or P14_4/ICU4/TIN12/4/TTG28/20/12/4
P06_5/A13 or P14_5/ICU5/TIN13/5/TTG29/21/13/5
P06_6/A14 or P14_6/ICU6/TIN14/6/TTG30/22/14/6
P06_7/A15 or P14_7/ICU7/TIN15/7/TTG31/23/15/7
P05_0/A16 or P16_0/PPG8
P05_1/A17 or P16_1/PPG9
P05_2/A18 or (P20_0/SIN2/AIN0 or P34_0/SIN10)
P05_3/A19 or (P20_1/SOT2/BIN0 or P34_1/SOT10)
P05_4/A20 or (P20_2/SCK2/ZIN0/CK2 or P34_2/SCK10)
P05_5/A21 or (P20_4/SIN3/AIN1 or P34_4/SIN11)
P05_6/A22 or (P20_5/SOT3/BIN1 or P34_5/SOT11)
P05_7/A23 or (P20_6/SCK3/ZIN1/CK3 or P34_6/SCK11)
VDD35
VSS5
P01_0/D16 or P17_0/PPG0
P01_1/D17 or P17_1/PPG1
P01_2/D18 or P17_2/PPG2
P01_3/D19 or P17_3/PPG3
P01_4/D20 or P15_4/OCU4/TOT4
P01_5/D21 or P15_5/OCU5/TOT5
P01_6/D22 or P15_6/OCU6/TOT6
P01_7/D23 or P15_7/OCU7/TOT7
P00_0/D24 or P24_0/INT0
P00_1/D25 or P24_1/INT1
P00_2/D26 or P24_2/INT2
P00_3/D27 or P24_3/INT3
P00_4/D28 or P24_4/INT4
P00_5/D29 or P24_5/INT5
P00_6/D30 or P24_6/INT6
P00_7/D31 or P24_7/INT7
P22_0/INT12
P22_1
P22_2/INT13
P22_3
VDD35
PPG16-31
peripheral not
supported by
CY91V460A, but
portfunction
Page 30 of 193
CY91460P Series
5.4 Multiplex Pinout CY91F467PA
if ANxx channel is enabled
(via PFR& EPFR), pin is
switched to analogue input,
digital input is then disabled
(independant of
PPMUX.PS/PRbits)
1 con gbit
(PPMUX.PS2) to
switch between
the two port
layouts
1 con gbit
(PPMUX.PS5) to
switch between
the two port
layouts
PPG16-31
peripheral not
supported by
CY91V460A, but
portfunction
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PPG16-31
peripheral not
supported by
CY91V460A, but
portfunction
1 con gbit
(PPMUX.PS1) to
switch between
the two port
layouts
if ANxx channel is enabled
(via PFR), pin is switched to
analogue input, digital input
is then disabled
(independant of
PPMUX.PS/PRbits)
VDD35
P32_7/PPG31
P32_3/PPG30
P33_7/PPG29
P33_3/PPG28
P07_7/A7 or P26_7/AN31
P07_6/A6 or P26_6/AN30
P07_5/A5 or P26_5/AN29
P07_4/A4 or P26_4/AN28
P07_3/A3 or P26_3/AN27
P07_2/A2 or P26_2/AN26
P07_1/A1 or P26_1/AN25
P07_0/A0 or P26_0/AN24
P20_6/SCK3/ZIN1/CK3 or P27_7/AN23
P20_5/SOT3/BIN1 or P27_6/AN22
P20_4/SIN3/AIN1 or P27_5/AN21
P20_2/SCK2/ZIN0/CK2 or P27_4/AN20
P20_1/SOT2/BIN0 or P27_3/AN19
P20_0/SIN2/AIN0 or P27_2/AN18
P16_1/PPG9 or P27_1/AN17
P16_0/PPG8 or P27_0/AN16
VSS5
VDD5
P24_7/INT7/SCL3 or P28_7/AN15
P24_6/INT6/SDA3 or P28_6/AN14
P24_5/INT5/SCL2 or P28_5/AN13
P24_4/INT4/SDA2 or P28_4/AN12
P24_3/INT3 or P28_3/AN11
P24_2/INT2 or P28_2/AN10
P24_1/INT1 or P28_1/AN9
P24_0/INT0 or P28_0/AN8
P29_7/AN7
P29_6/AN6
P35_6/SCK9 or P29_5/AN5
P35_5/SOT9 or P29_4/AN4
P35_4/SIN9 or P29_3/AN3
P35_2/SCK8 or P29_2/AN2
P35_1/SOT8 or P29_1/AN1
P35_0/SIN8 or P29_0/AN0
P34_7/PPG27
P34_3/PPG26
P35_7/PPG25
P35_3/PPG24
VSS5
1 con gbit
(PPMUX.PS0) to
switch between
the two port
layouts
if ANxx channel is enabled
(via PFR) pin is switched to
analogue input, digital input
is then disabled
(independant of
PPMUX.PS/PRbits)
if ANxx channel is enabled
(via PFR& EPFR), pin is
switched to analogue input,
digital input is then disabled
(independant of
PPMUX.PS/PRbits)
1 con gbit
(PPMUX.PS4) to
switch between
external bus
(default)
or peripheral
function
(all 8 pins)
1 con gbit
(PPMUX.PRPS0) to
determine wether
PPMUX.PR17 to
PPMUX.PR12
relocate pins from
P20 or switch Pins
to P34
1 con gbyte (PPMUX.PR17 to
PPMUX.PR10) to relocate
peripheral function (all 8 pins,
but not ANxx), external bus
function is disabled when
relocated
1 con gbit (PPMUX.PR0) to
relocate peripheral function
(all 8 pins, but not ANxx and
not I2C), external bus function
is disabled when relocated
QFP-176
1 con gbyte (PPMUX2.PR0 to
PPMUX2.PR5) to relocate
peripheral function
(SIN10,SOT10,SCK10,
SIN11,SO
T11,SCK11)
, external
bus function is disabled when
relocated
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VDD5
AVCC5
AVRH5
AVSS5
P25_1
P25_0
P17_7/PPG7/AN39
P17_6/PPG6/AN38
P17_5/PPG5/AN37
P18_6/SCK7/ZIN3/CK7/AN4
P18_5/SO
T7/BIN3/AN45
P18_4/SIN7/AIN3/AN44
P18_2/SCK6/ZIN2/CK6/AN4
P18_1/SO
T6/BIN2/AN41
P18_0/SIN6/AIN2/AN40
P19_6/SCK5/CK5
P19_5/SO
T5
P19_4/SIN5
P19_2/SCK4/CK4
P19_1/SO
T4
P19_0/SIN4
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X1
X0
MD_3
MONCLK
MD_2
MD_1
MD_0
P23_7/TX3
P23_6/RX3/INT11
P23_5/TX2
P23_4/RX2/INT10
VSS5
PPG16-31
peripheral not
supported by
CY91V460A,
but portfunction
Document Number: 002-04619 Rev. *B
VSS5
P30_0/PPG16
P30_1/PPG17
P30_2/PPG18
P30_3/PPG19
P10_0/SYSCLK or P34_0/SIN10
P10_1/ASX or P34_1/SOT10
P10_3/WEX or P34_2/SCK10
P09_0/CSX0 or P34_4/SIN11
P09_1/CSX1 or P34_5/SOT11
P09_2/CSX2 or P34_6/SCK11
P08_0/WRX0
P08_1/WRX1
P08_4/RDX
P08_7/RDY
P16_2/PPG10
P16_3/PPG11
P16_4/PPG12/SGA
P16_5/PPG13/SGO
P16_6/PPG14/PFM
P16_7/PPG15/AGTX
VDD5
VSS5
P23_0/RX0/INT8
P23_1/TX0
P23_2/RX1/INT9
P23_3/TX1
P22_4/SDA0/INT14
P22_5/SCL0
P22_6/SDA1/INT15
P22_7/SCL1
P14_0/ICU0/TIN8/0/TTG24/16/8/0
P14_1/ICU1/TIN9/1/TTG25/17/9/1
P14_2/ICU2/TIN10/2/TTG26/18/10/2
P14_3/ICU3/TIN11/3/TTG27/19/11/3
P15_0/OCU0/TOT0
P15_1/OCU1/TOT1
P15_2/OCU2/TOT2
P15_3/OCU3/TOT3
P30_4/PPG20
P30_5/PPG21
P30_6/PPG22
P30_7/PPG23
VDD5
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
1 con gbit
(PPMUX.PS3) to
switch between
external bus
(default) or
peripheral
function
(all 8 pins)
VSS5
1
P21_4/SIN1
2
P21_5/SO
T1
3
P21_6/SCK1/CK1 4
P21_7
5
P06_0/A8 or P21_0/SIN0 6
P06_1/A9 or P21_1/SO
T0
7
P06_2/A10 or P21_2/SCK0/CK0 8
P06_3/A11 or P17_4/PPG4 9
P06_4/A12 or P14_4/ICU4/TIN12/4/T
TG28/20/12/4
10
P06_5/A13 or P14_5/ICU5/TIN13/5/T
TG29/21/13/5
11
P06_6/A14 or P14_6/ICU6/TIN14/6/T
TG30/22/14/6
12
P06_7/A15 or P14_7/ICU7/TIN15/7/T
TG31/23/15/7
13
P05_0/A16 or P16_0/PPG8 14
P05_1/A17 or P16_1/PPG9 15
P05_2/A18 or (P20_0/SIN2/AIN0 or P34_0/SIN10)16
P05_3/A19 or (P20_1/SO
T2/BIN0 or P34_1/SO
T10)
17
P05_4/A20 or (P20_2/SCK2/ZIN0/CK2 or P34_2/SCK10)
18
P05_5/A21 or (P20_4/SIN3/AIN1 or P34_4/SIN11)19
P05_6/A22 or (P20_5/SO
T3/BIN1 or P34_5/SO
T11)
20
P05_7/A23 or (P20_6/SCK3/ZIN1/CK3 or P34_6/SCK11)
21
VDD35
22
VSS5
23
P01_0/D16 or P17_0/PPG0 24
P01_1/D17 or P17_1/PPG1 25
P01_2/D18 or P17_2/PPG2 26
P01_3/D19 or P17_3/PPG3 27
P01_4/D20 or P15_4/OCU4/T
OT4
28
P01_5/D21 or P15_5/OCU5/T
OT5
29
P01_6/D22 or P15_6/OCU6/T
OT6
30
P01_7/D23 or P15_7/OCU7/T
OT7
31
P00_0/D24 or P24_0/INT0 32
P00_1/D25 or P24_1/INT1 33
P00_2/D26 or P24_2/INT2 34
P00_3/D27 or P24_3/INT3 35
P00_4/D28 or P24_4/INT4 36
P00_5/D29 or P24_5/INT5 37
P00_6/D30 or P24_6/INT6 38
P00_7/D31 or P24_7/INT7 39
P22_0/INT12
40
P22_1
41
P22_2/INT13
42
P22_3
43
VDD35
44
PPG16-31
peripheral not
supported by
CY91V460A, but
portfunction
Page 31 of 193
CY91460P Series
6. Reload Timer / New Features
6.1 Overview
The reload timer uses a 16 bit down counter to detect the input signal trigger and perform a count down.
The count length is 16 bits.
6.2 Features
Format: 16 bit down counter with reload register
Quantity: 16 (Output: 8 channels TOT[0 to 7])
Cascading clock mode: (only available for Reload timers 8,10,12,14)
• Count clock for Reload timer 8: Output of Reload timer 9
• Count clock for Reload timer 10: Output of Reload timer 11
• Count clock for Reload timer 12: Output of Reload timer 13
• Count clock for Reload timer 14: Output of Reload timer 15
Count active edge: When in external event mode, choose from 3 types.
• External trigger (rising /falling/both edges)
Interrupt: Request generated by underflow
Other 1: Counter stop in software/can be reopened
Other 2: Control of other peripheral functions possible
• PPG activation trigger source:
Reload timer 8 : PPG16, PPG17
Reload timer 9 : PPG18, PPG19
Reload timer 10 : PPG20, PPG21
Reload timer 11 : PPG22, PPG23
Reload timer 12 : PPG24, PPG25
Reload timer 13 : PPG26, PPG27
Reload timer 14 : PPG28, PPG29
Reload timer 15 : PPG30, PPG31
• A/D converter activation trigger source (Reload timer 7 : A/D)
Document Number: 002-04619 Rev. *B
Page 32 of 193
CY91460P Series
6.3 Registers
6.3.1 TMCSR: Reload Timer Control Status Register
The control status register controls the operation mode of the reload timer and interrupts.
• TMCSR8 (Reload timer 8): Address: 00596H (Access: Byte, Half-word)
• TMCSR9 (Reload timer 9): Address: 0059EEH (Access: Byte, Half-word)
• TMCSR10 (Reload timer 10): Address: 005A6H (Access: Byte, Half-word)
• TMCSR11 (Reload timer 11): Address: 005AEH (Access: Byte, Half-word)
• TMCSR12 (Reload timer 12): Address: 005B6H (Access: Byte, Half-word)
• TMCSR13 (Reload timer 13): Address: 005BEH (Access: Byte, Half-word)
• TMCSR14 (Reload timer 14): Address: 005C6H (Access: Byte, Half-word)
• TMCSR15 (Reload timer 15): Address: 005CEH (Access: Byte, Half-word)
15
14
13
12
11
10
9
8
bit
CSL2
CSL1
CSL0
MOD2
MOD1
-
-
-
0
0
0
0
0
Initial Value
RX/WX
RX/WX
RX/WX
R/W
R/W
R/W
R/W0
R/W
Attribute
Rewrite during
operation
7
6
MOD0
5
4
3
2
1
0
OULT
RELD
INTE
UF
CNTE
TRG
bit
0
-
0
0
0
0
0
0
Initial Value
R/W
RX/WX
R/W
R/W
R/W
R(RM1),W
R/W
R0/W
Attribute
O
O
O
Rewrite during
operation
(O: can be rewritten, x: cannot be rewritten)
bit12-10: Count clock selection
CLKP: peripheral clock
CSL2
CSL1
CSL0
0
0
0
Internal clock CLKP/2
0
0
1
Internal clock CLKP/8
0
1
0
Internal clock CLKP/32
0
1
1
External event (external clock)
1
0
1
Internal clock CLKP/64
1
1
0
Internal clock CLKP/128
1
1
1
RLT n+1 output
Document Number: 002-04619 Rev. *B
Count clock
Remarks
only allowed for RLT 8, 10, 12, 14
Page 33 of 193
CY91460P Series
6.3.2 TMR: Timer Register
• TMR8 (Reload timer 8): Address: 0592H (Access: Half-word)
• TMR9 (Reload timer 9): Address: 059AH (Access: Half-word)
• TMR10 (Reload timer 10): Address: 05A2H (Access: Half-word)
• TMR11 (Reload timer 11): Address: 05AAH (Access: Half-word)
• TMR12 (Reload timer 12): Address: 05B2H (Access: Half-word)
• TMR13 (Reload timer 13): Address: 05BAH (Access: Half-word)
• TMR14 (Reload timer 14): Address: 05C2H (Access: Half-word)
• TMR15 (Reload timer 15): Address: 05CAH (Access: Half-word)
6.3.3 TMRC: Consistent Timer Register
• TMR89 (Reload timer 8, 9): Address: 05D0H (Access: Word)
• TMR1011 (Reload timer 10, 11): Address: 05D4H (Access: Word)
• TMR1213 (Reload timer 12, 13): Address: 05D8H (Access: Word)
• TMR1415 (Reload timer 14, 15): Address: 05DCH (Access: Word)
31
30
29
28
27
26
25
24
D31
D30
D29
D28
D27
D26
D25
D24
bit
X
X
X
X
X
X
X
X
Initial Value
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
Attribute
23
22
21
20
19
18
17
16
bit
D23
D22
D21
D20
D19
D18
D17
D16
X
X
X
X
X
X
X
X
Initial Value
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
Attribute
bit
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D9
D8
X
X
X
X
X
X
X
X
Initial Value
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
Attribute
7
6
5
4
3
2
1
0
bit
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
Initial Value
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
R/WX
Attribute
The count values of cascaded reload timers can be read out through the timer register TMRC at the same time. Upper halfword
contain TMRn, lower halfword TMRn+1.
Please perform the read out using word access.
6.3.4 TMRLR: Reload register
• TMRLR8 (Reload timer 8): Address: 0590H (Access: Half-word)
• TMRLR9 (Reload timer 9): Address: 0598H (Access: Half-word)
• TMRLR10 (Reload timer 10): Address: 05A0H (Access: Half-word)
• TMRLR11 (Reload timer 11): Address: 05A8H (Access: Half-word)
• TMRLR12 (Reload timer 12): Address: 05B0H (Access: Half-word)
• TMRLR13 (Reload timer 13): Address: 05B8H (Access: Half-word)
• TMRLR14 (Reload timer 14): Address: 05C0H (Access: Half-word)
• TMRLR15 (Reload timer 15): Address: 05C8H (Access: Half-word)
Document Number: 002-04619 Rev. *B
Page 34 of 193
CY91460P Series
6.4 Cascading Operation
In reload mode Reload timer 9 Output is set as Count event for Reload timer 8, both edge modes.
TMLR9
n
...
TMLR8
m
...
CLKP
...
TMR9
0
n
n-1
0
...
n
(1)
TOUT9
n-1
(1)
...
(2)
TMR8
1
(2)
0
...
m
TMR
(3)
TOUT8
...
(1) TOUT9 signal change caused by underflow TMR9
(2) TMR8 decreased by TOUT9
(3) TOUT8 signal change caused by underflow of TMR8
Document Number: 002-04619 Rev. *B
Page 35 of 193
CY91460P Series
7. Additional PPGs
7.1 Register
7.1.1 PCSR: PPG Cycle Setting Register
Controls the cycle of the PPG.
• PCSR16 (PPG16): Address 0512h (Access: Half-word)
• PCSR17 (PPG17): Address 0518h (Access: Half-word)
• PCSR18 (PPG18): Address 0522h (Access: Half-word)
• PCSR19 (PPG19): Address 0528h (Access: Half-word)
• PCSR20 (PPG20): Address 0532h (Access: Half-word)
• PCSR21 (PPG21): Address 0538h (Access: Half-word)
• PCSR22 (PPG22): Address 0542h (Access: Half-word)
• PCSR23 (PPG23): Address 0548h (Access: Half-word)
• PCSR24 (PPG24): Address 0552h (Access: Half-word)
• PCSR25 (PPG25): Address 0558h (Access: Half-word)
• PCSR26 (PPG26): Address 0562h (Access: Half-word)
• PCSR27 (PPG27): Address 0568h (Access: Half-word)
• PCSR28 (PPG28): Address 0572h (Access: Half-word)
• PCSR29 (PPG29): Address 0578h (Access: Half-word)
• PCSR30 (PPG30): Address 0582h (Access: Half-word)
• PCSR31 (PPG31): Address 0588h (Access: Half-word)
7.1.2 PDUT: PPG Duty Setting Register
Sets the duty of the PPG output waveform.
• PDUT16 (PPG16): Address 0514h (Access: Half-word)
• PDUT17 (PPG17): Address 051Ch (Access: Half-word)
• PDUT18 (PPG18): Address 0524h (Access: Half-word)
• PDUT19 (PPG19): Address 052Ch (Access: Half-word)
• PDUT20 (PPG20): Address 0534h (Access: Half-word)
• PDUT21 (PPG21): Address 053Ch (Access: Half-word)
• PDUT22 (PPG22): Address 0544h (Access: Half-word)
• PDUT23 (PPG23): Address 054Ch (Access: Half-word)
• PDUT24 (PPG24): Address 0554h (Access: Half-word)
• PDUT25 (PPG25): Address 055Ch (Access: Half-word)
• PDUT26 (PPG26): Address 0564h (Access: Half-word)
• PDUT27 (PPG27): Address 056Ch (Access: Half-word)
• PDUT28 (PPG28): Address 0574h (Access: Half-word)
• PDUT29 (PPG29): Address 057Ch (Access: Half-word)
• PDUT30 (PPG30): Address 0584h (Access: Half-word)
• PDUT31 (PPG31): Address 058Ch (Access: Half-word)
7.1.3 PCN: PPG Control Status register
Controls the operations and status of PPGs.
• PCN16 (PPG16): Address 0516h (Access: Byte, Half-word)
• PCN17 (PPG17): Address 051Eh (Access: Byte, Half-word)
• PCN18 (PPG18): Address 0526h (Access: Byte, Half-word)
• PCN19 (PPG19): Address 052Eh (Access: Byte, Half-word)
• PCN20 (PPG20): Address 0536h (Access: Byte, Half-word)
• PCN21 (PPG21): Address 053Eh (Access: Byte, Half-word)
• PCN22 (PPG22): Address 0546h (Access: Byte, Half-word)
• PCN23 (PPG23): Address 054Eh (Access: Byte, Half-word)
• PCN24 (PPG24): Address 0556h (Access: Byte, Half-word)
• PCN25 (PPG25): Address 055Eh (Access: Byte, Half-word)
• PCN26 (PPG26): Address 0566h (Access: Byte, Half-word)
• PCN27 (PPG27): Address 056Eh (Access: Byte, Half-word)
• PCN28 (PPG28): Address 0576h (Access: Byte, Half-word)
• PCN29 (PPG29): Address 057Eh (Access: Byte, Half-word)
• PCN30 (PPG30): Address 0586h (Access: Byte, Half-word)
• PCN31 (PPG31): Address 058Eh (Access: Byte, Half-word)
Document Number: 002-04619 Rev. *B
Page 36 of 193
CY91460P Series
7.1.4 GCN1: General Control register 1
Selects a trigger input to PPG0 PPG16-PPG19, PPG20-PPG23, PPG24-PPG27 and PPG28-PPG31.
• GCN14 (PPG16-PPG19): Address 0500h (Access: Half-word)
• GCN15 (PPG20-PPG23): Address 0504h (Access: Half-word)
• GCN16 (PPG24-PPG27): Address 0505h (Access: Half-word)
• GCN17 (PPG28-PPG31): Address 050Ch (Access: Half-word)
7.1.5 GCN2: General Control register 2
Generates PPG16-PPG19, PPG20-PPG23, PPG24-PPG27 and PPG28-PPG31 internal trigger levels using software.
• GCN24 (PPG16-PPG19): Address 0503h (Access: Byte)
• GCN25 (PPG20-PPG23): Address 0507h (Access: Byte)
• GCN26 (PPG24-PPG27): Address 050Bh (Access: Byte)
• GCN27 (PPG28-PPG31): Address 050Fh (Access: Byte)
7.1.6 PTMR: PPG Timer Register
Reads the counts of PPGs.
• PTMR16 (PPG16): Address 0510h (Access: Half-word)
• PTMR17 (PPG17): Address 0518h (Access: Half-word)
• PTMR18 (PPG18): Address 0520h (Access: Half-word)
• PTMR19 (PPG19): Address 0528h (Access: Half-word)
• PTMR20 (PPG20): Address 0530h (Access: Half-word)
• PTMR21 (PPG21): Address 0538h (Access: Half-word)
• PTMR22 (PPG22): Address 0540h (Access: Half-word)
• PTMR23 (PPG23): Address 0548h (Access: Half-word)
• PTMR24 (PPG24): Address 0550h (Access: Half-word)
• PTMR25 (PPG25): Address 0558h (Access: Half-word)
• PTMR26 (PPG26): Address 0560h (Access: Half-word)
• PTMR27 (PPG27): Address 0568h (Access: Half-word)
• PTMR28 (PPG28): Address 0570h (Access: Half-word)
• PTMR29 (PPG29): Address 0578h (Access: Half-word)
• PTMR30 (PPG30): Address 0581h (Access: Half-word)
• PTMR31 (PPG31): Address 0588h (Access: Half-word)
Document Number: 002-04619 Rev. *B
Page 37 of 193
CY91460P Series
8. A/D Converter / New Features (CY91F467PA)
CY91F467PA has two 10-bit A/D Converter macros. The original ADC, which is available on all CY91460 series devices, is now called
“ADC 0”, the second macro is called “ADC 1”.
8.1 A/D Converter Features
• Both ADC 0 and ADC 1 are 10-bit / 1 μs macros used on other CY91460 series devices.
• Both ADCs have the new digital part with separated A/D Result registers and 4-channel Range Comparator,
see chapter 9.“A/D Converter / Range Comparator (CY91F467PA)”.
• Both ADCs can be triggered from Reload Timer RLT7.
• Both ADCs can be triggered from the same external ATGX pin (GP16_7).
• On CY91F467PA, ADC0 and ADC1 share the same analog power and reference supply (AVCC5,AVRH5,AVSS).
8.2 Analog Input Connections
8.2.1 Global ADC Analog Channel Enable
The global ADC channel enable feature makes the ADC analog inputs independend of PFR/EPFR settings. It was introduced for
2 reasons:
• Some new ADC channels are assigned to ports whose PFR/EPFR combinations are already used completely for other
resources.
• Customers may measure digital output signals with the ADC to check for external shortages.
PFR/EPFR settings for ADC always switch the digital port to HiZ mode.
The global ADC channel enable is controlled by bit ADCHE in PORTEN register:
PORTEN Register Address: 0x0498 Access: Byte
7
X
RX, W0
6
X
RX, W0
5
X
RX, W0
4
X
RX, W0
3
X
RX, W0
2
ADCHE
0
R, W
1
CPORTEN
0
R, W
0
GPORTEN
0
R, W
Bit
Initial value
Attribute
Bit7-3: Reserved bits. Always write 0 to these bits.
Bit2: ADCHE Global A/D Channel Enable.
ADCHE
Function
0 [initial]
Global A/D Channel Enable is OFF.
The ADC analog lines of channels 0-31 are enabled by setting of the ADC enable bits (ADEn) in the
ADERH,ADERL register and PFR/EPFR. PFR/EPFR will set the digital output to HiZ mode and disable the digital
input lines of the port.
1
Global A/D Channel Enable is ON.
The ADC analog lines of channels 6-7 are enabled by setting of the ADC enable bits (ADEn) in the
ADERH,ADERL register only. ADEn will disable the digital input lines of the port, but the digital outputs are not
changed. For analog measurement, the user has to switch the port to input direction.
This bit is cleared by software reset (RST) and can be written and read by CPU.
Note: For new ADC channels (AN32 to AN53, device depending), the ADCHE feature is always ON.
For old ADC channels (AN0 to AN31), the ADCHE feature is always OFF if the channels are re-located to other pins. On
CY91F467PA, the ADCHE feature is only available on the non-relocated ADC channels 6-7 on ports P29[6,7].
Document Number: 002-04619 Rev. *B
Page 38 of 193
CY91460P Series
Bit1:0: CPORTEN,GPORTEN Global Port Input Enable
CPORTEN
GPORTEN
Function
0 [initial]
0 [initial]
1
0
The Port Input for LIN-USART 4 is enabled. This functionality is used by the Boot ROM to establish
a serial communication with Softune for flash programming.
X
1
All port input lines are enabled.
All port input lines are disabled.
- These bits are cleared by software reset (RST) and can be written and read by CPU.
- After execution of the Boot ROM the bits are in initial state.
8.2.2 ADC 0 Analog Inputs
ADC 0 serves the analog inputs AN0 to AN31. There are 2 methods for enabling the analog inputs:
• For all channels: Set ADC channel enable bits (ADEn) in the ADERH,ADERL register and set PFR/EPFR of the attached I/O port
• For channels 6-7: Set ADC channel enable bits (ADEn) in the ADERH,ADERL register and set global ADC channel enable,
see 8.2.1“Global ADC Analog Channel Enable”.
Note : To use the channels AN0 to AN5 and AN8 to AN31, port multiplexing must be set. See chapter 5.“Port Multiplexing” and chapter
3.“Pin Description” for details. The ADC channel enable feature ADCHE is not available on the re-located channels.
8.2.3 ADC 1 Analog Inputs
ADC 1 serves the analog inputs AN37 to AN42, AN44 to AN46.
The analog inputs are enabled just by setting the ADC channel enable bits ADEn in the AD1ERH, AD1ERL registers. The Global ADC
Analog Channel Enable feature is fixed ON here.
Document Number: 002-04619 Rev. *B
Page 39 of 193
CY91460P Series
9. A/D Converter / Range Comparator (CY91F467PA)
The new A/D Converter with Range Comparator is available on CY91FV460B and CY91F467PA and is backward compatible to the
A/D converter used on older devices.
This chapter provides an overview of the A/D converter, describes the register structure and functions, and describes the operation
of the A/D converter.
9.1 Overview of A/D Converter and A/D Range Comparator
The A/D converter converts analog input voltages into digital values and provides the following features. Any ADC channel can be
assigned to one of 4 Range Comparators.
9.1.1
•
•
•
•
•
•
•
•
•
Features of the A/D converter:
Conversion time: minimum 1μs per channel.
RC type successive approximation conversion with sample & hold circuit
10-bit or 8-bit resolution
Program section analog input from 32 channels
1 common result data register and 32 dedicated channel result data registers
Single conversion mode:
Convert the specified channel(s) only once.
Continuous mode:
Repeatedly convert the specified channels.
Scan conversion mode:
Continuous conversion of multiple channels, programmable for up to 32 channels
Stop mode:
Convert one channel, then temporarily halt until the next activation.
(Enables synchronization of the conversion start timing.)
• A/D conversion can be followed by an A/D conversion interrupt request to CPU. This interrupt, an option that is ideal for
continuous processing can be used to start a DMA transfer of the results of A/D conversion to memory.
• A/D conversion of all enabled channels (scan conversion) can be followed by an A/D End of Scan interrupt request to CPU. The
data is stored into dedicated channel result registers, which can be read out using DMA transfer.
• Conversion startup may be by software, external trigger (falling edge) or timer (rising edge).
9.1.2 Features of the A/D Range Comparator (RCO):
• 4 conversion result Range Comparator channels, comparing the upper 8 bit of the conversion result with an upper and a lower
threshold. The thresholds are programmable for the 4 comparators independently.
• Any ADC channel can be assigned to one of the 4 range comparators.
• The comparison results will set “overflow” and “interrupt” flags per ADC channel, depending on the configuration. It is possible
to configure the comparison for:
- “out of range”: The flags are set if the A/D result is below the lower OR above the upper threshold.
- “inside range”: The flags are set if the A/D result is above the lower AND below the upper threshold.
• The configuration can be set individually per ADC channel.
• Range comparison can be followed by an A/D Range Comparator interrupt request to CPU.
Document Number: 002-04619 Rev. *B
Page 40 of 193
CY91460P Series
9.2 A/D Converter Input Impedance
The following figure shows the sampling circuit of the A/D converter:
ADC
Analog
signal
source
Rext
ANx
Rin
Analog SW
Cin
Do not set Rext over maximum sampling time (Tsamp).
Rext = Tsamp / (7*Cin) - Rin
Document Number: 002-04619 Rev. *B
Page 41 of 193
CY91460P Series
9.3 Block Diagram of A/D Converter
The following figure shows block diagram of A/D converter.
AVCC AVRH AVRL AVSS
MPX
D/A converter
Sequential
comparison register
Comparator
ADC
Range
Comparator
Sample & Hold
circuit
4 digital
comparators
with upper
and lower
threshold
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
32
A/D channel
data registers
R - Bus
Input Circuit
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
ADCD00
to
ADCD31
32 * 2 flags
(2 flags per
ADC channel)
RCO Flags
RCO INT
A/D data register
A/D control register 2
Decoder
INT2
A/D control register 0
A/D control register 1
INT
ADC S 0/1
ATGX
Operating
Clock
16- bit
Reload Timer
CLKP
Document Number: 002-04619 Rev. *B
Prescaler
Page 42 of 193
CY91460P Series
9.4 Registers of the A/D Converter
The A/D converter with Range Comparator has the following registers:
Address
(ADC 0)
Address
(ADC 1)
0001A0H
0005E0H
x=0 or 1 for ADC0, ADC1 respectively
+0
+1
+2
ADxERH
+3
ADxERL
Register
A/D channel Enable register
0001A4H
0005E4H
ADxCS1
ADxCS0
ADxCR1
ADxCR0
A/D Control / Status register 0 + 1,
A/D Conversion Result register
0001A8H
0005E8H
ADxCT1
ADxCT0
ADxSCH
ADxECH
Sampling timer setting register,
Start Channel setting register,
End Channel setting register
0006B0H
0006DCH
ADxCS2
-
-
-
A/D Control / Status register 2
000688H
0006B4H
RCOxH0
RCOxL0
RCOxH1
RCOxL1
Range Comparator 0,1 High/Low threshold
registers
00068CH
0006B8H
RCOxH2
RCOxL2
RCOxH3
RCOxL3
Range Comparator 2,3 High/Low threshold
registers
000690H
0006BCH
RCOxIRS
Range Comparator Inverted Range Select control
000694H
0006C0H
RCOxOF
Range Comparator Overflow flags
000698H
0006C4H
RCOxINT
Range Comparator Interrupt flags
0006A0H
0006CCH
ADxCC0
ADxCC1
ADxCC2
ADxCC3
Channel control for ch 0 to 7
0006A4H
0006D0H
ADxCC4
ADxCC5
ADxCC6
ADxCC7
Channel control for ch 8 to 16
0006A8H
0006D4H
ADxCC8
ADxCC9
ADxCC10
ADxCC11 Channel control for ch 16 to 23
0006ACH
0006D8H
ADxCC12
ADxCC13
ADxCC14
ADxCC15 Channel control for ch 24 to 31
0006E0H
000720H
ADCxD0
ADCxD1
ADC Channel Data register, channel 0,1
0006E4H
000724H
ADCxD2
ADCxD3
ADC Channel Data register, channel 2,3
0006E8H
000728H
ADCxD4
ADCxD5
ADC Channel Data register, channel 4,5
0006ECH
00072CH
ADCxD6
ADCxD7
ADC Channel Data register, channel 6,7
0006F0H
000730H
ADCxD8
ADCxD9
ADC Channel Data register, channel 8,9
0006F4H
000734H
ADCxD10
ADCxD11
ADC Channel Data register, channel 10,11
0006F8H
000738H
ADCxD12
ADCxD13
ADC Channel Data register, channel 12,13
0006FCH
00073CH
ADCxD14
ADCxD15
ADC Channel Data register, channel 14,15
000700H
000740H
ADCxD16
ADCxD17
ADC Channel Data register, channel 16,17
000704H
000744H
ADCxD18
ADCxD19
ADC Channel Data register, channel 18,19
000708H
000748H
ADCxD20
ADCxD21
ADC Channel Data register, channel 20,21
00070CH
00074CH
ADCxD22
ADCxD23
ADC Channel Data register, channel 22,23
000710H
000750H
ADCxD24
ADCxD25
ADC Channel Data register, channel 24,25
000714H
000754H
ADCxD26
ADCxD27
ADC Channel Data register, channel 26,27
000718H
000758H
ADCxD28
ADCxD29
ADC Channel Data register, channel 28,29
00071CH
00075CH
ADCxD30
ADCxD31
ADC Channel Data register, channel 30,31
Document Number: 002-04619 Rev. *B
Page 43 of 193
CY91460P Series
9.4.1 A/D Input Enable Register (ADER)
This register enables the analog input functions of the A/D converter. On CY91F467PA, additionally the bit ADCHE in PORTEN
register influences the enabling of analog input.
ADERH : Access: Word, Half-word, Byte
31
ADE31
0
R/W
30
ADE30
0
R/W
29
ADE29
0
R/W
28
ADE28
0
R/W
27
ADE27
0
R/W
26
ADE26
0
R/W
25
ADE25
0
R/W
24
ADE24
0
R/W
23
ADE23
0
R/W
22
ADE22
0
R/W
21
ADE21
0
R/W
20
ADE20
0
R/W
19
ADE19
0
R/W
18
ADE18
0
R/W
17
ADE17
0
R/W
16
ADE16
0
R/W
Bit
Initial value
Attribute
Bit
Initial value
Attribute
ADERL : Access: Word, Half-word, Byte
15
ADE15
0
R/W
14
ADE14
0
R/W
13
ADE13
0
R/W
12
ADE12
0
R/W
11
ADE11
0
R/W
10
ADE10
0
R/W
9
ADE9
0
R/W
8
ADE8
0
R/W
7
ADE7
0
R/W
6
ADE6
0
R/W
5
ADE5
0
R/W
4
ADE4
0
R/W
3
ADE3
0
R/W
2
ADE2
0
R/W
1
ADE1
0
R/W
0
ADE0
0
R/W
Bit
Initial value
Attribute
Bit
Initial value
Attribute
[ADE31-0]: A/D Input Enable
ADEn
0 [initial]
PORTEN.ADCHE
X
Function
Analog input of A/D channel n is disabled.
The ADC will not sample/convert this channel.
0 [initial]
Analog input of the channel n is enabled. Additionally, the port function register (PFR,EPFR)
of the corresponding port must be set . The PFR/EPFR will switch the port to input direction
(output driver = HiZ) and disable the digital input lines.
1
Analog input of the channel n is enabled. Setting the port function register(s) is not necessary.
ADEn will disable the digital input lines of the ports, but it does not change the port’s direction.
1
• Software reset (RST) clears ADEn and PORTEN.ADCHE to 0.
• Be sure to set start channel and end channel to cover all enabled channels.
Document Number: 002-04619 Rev. *B
Page 44 of 193
CY91460P Series
9.4.2 A/D Control Status Registers (ADCS2, ADCS1, ADCS0)
The A/D control status registers control and show the status of A/D converter. Do not overwrite ADCS0 register during A/D converting.
ADCS2 : Access: Byte
15
BUSY
0
R
14
INT
0
R
13
INTE
0
R
12
PAUS
0
R
11
0
R0
10
0
R0
9
INT2
0
R/W
8
INTE2
0
R/W
Bit
Initial value
Attribute
[bits 15:12] BUSY, INT, INTE, PAUS
These bits are a mirror of the corresponding bits in ADCS1, intended to quickly read out all status and interrupt information using only
one register access. To write the bits, access them via ADCS1.
[bits 11:10] These bits do not exist. Read operation returns 0.
[bit 9] INT2 (End of Scan Flag)
The End of Scan flag is set when conversion data of the last channel is stored in ADCR, whereas the last channel is defined by ADECH
register setting.
• If bit 8 (INTE2) is "1" when this bit is set, and the ADC runs in continuous conversion mode, an End of Scan interrupt request is
generated or, if activation of DMA is enabled, DMA is activated.
• Only clear this bit by writing "0" when A/D conversion is halted.
• Initialized to "0" by a reset.
• If DMA is used, this bit is cleared at the end of DMA transfer.
• Read-modify-write operations read this bit as “1”.
[bit 8] INTE2 (Enable End of Scan Interrupt)
INTE2 enables the End of Scan interrupt in continuous conversion mode. In the other conversion modi, this bit has no effect.
Additionally, setting INTE2 changes the protect function of converted data (see description of ADCS1.PAUS).
INTE2
0 [initial]
1
Function
Disable End of Scan interrupt,
ADC result protection protects the ADCR register data.
Enable End of Scan interrupt,
ADC result protection protects the ADCD0...ADCD31 register data (in continuous conversion mode only)
Document Number: 002-04619 Rev. *B
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CY91460P Series
ADCS1 : Access: Half-word, Byte
15
BUSY
0
R/W
14
INT
0
R/W
13
INTE
0
R/W
12
PAUS
0
R/W
11
STS1
0
R/W
10
STS0
0
R/W
9
STRT
0
R/W
8
reserved
0
R/W
Bit
Initial value
Attribute
[bit 15] BUSY (busy flag and stop)
BUSY
Reading
Writing
•
•
•
•
•
Function
A/D converter operation indication bit. Set on activation of A/D conversion and cleared on completion.
Writing "0" to this bit during A/D conversion forcibly terminates conversion. Use to forcibly terminate in continuous
and stop modes.
Read-modify-write instructions read the bit as "1".
Cleared on the completion of A/D conversion in single conversion mode.
In continuous and stop mode, the flag is not cleared until conversion is terminated by writing "0".
Initialized to "0" by a software reset (RST).
Do not specify forcible termination and software activation (BUSY="0" and STRT="1") at the same time.
[bit 14] INT (End of Conversion Interrupt flag)
This bit is set when conversion data is stored in ADCR.
• If bit 5 (INTE) is "1" when this bit is set, an interrupt request is generated or, if activation of DMA is enabled, DMA is activated.
• Only clear this bit by writing "0" when A/D conversion is halted.
• Initialized to "0" by a software reset (RST).
• If DMA is used, this bit is cleared at the end of DMA transfer.
[bit 13] INTE (End of Conversion Interrupt enable)
This bit is enables or disables the conversion completion interrupt.
INTE
Function
0
Disable interrupt [Initial value]
1
Enable interrupt
• Cleared by a software reset (RST).
Document Number: 002-04619 Rev. *B
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CY91460P Series
[bit 12] PAUS (A/D converter pause)
This bit is set when A/D conversion temporarily halts.
The A/D converter has one register to store the conversion result (ADCR) and additionally 32 ADC channel data registers. If a
conversion is finished and the data of the previous conversion has not been read out before, previous data would be overwritten.
To avoid this problem, the next conversion data is not stored in the data registers until the previous value has been read out (e.g. by
DMA). A/D conversion halts during this time. A/D conversion resumes when the ADC interrupt flag ADCR1.INT is cleared.
The register protection function depends on the conversion mode and the setting of ADCR2.INTE2:
Mode
INTE2
Single, Stop
X
Protect ADCR (the common result register)
0
Protect ADCR (the common result register)
1
Protect ADCD0...ADCD31 (the dedicated channel data registers)
Continuous
Function
• In continuous mode with INTE2==1, PAUS is set when data of the start channel (set by ADSCH) is ready for writing to the
registers, but IRQ2 (End of Scan interrupt) is active.
• In the other modes or if INTE2==0, PAUS is set when data of any channel is ready for writing to the registers, but IRQ (End of
Conversion) is active.
• PAUS is cleared by writing “0” or by a reset. (Not cleared at the end of DMA transfer.) However when waiting condition of DMA
transfer, this bit cannot be cleared.
• Regarding protect function of converted data, see Section 9.6“Operation of A/D Converter”.
[bit 11, 10] STS1, STS0 (Start source select)
These bits select the A/D activation source.
STS1
STS0
Function
0
0
Software activation [Initial value]
0
1
External trigger pin activation and software activation
1
0
Timer activation and software activation
1
1
External trigger pin activation, timer activation and software activation
• These bits are initialized "00" by software reset (RST).
• In multiple-activation modes, the first activation to occur starts A/D conversion.
• The activation source changes immediately on writing to the register. Therefore care is required when switching activation mode
during A/D operation.
• The A/D converter detects falling edges on the external trigger pin. When external trigger level is “L” and if these bits are changed
to external trigger activation mode, A/D converting may starts.
• Selecting the timer selects the 16-bit reload timer 7.
Document Number: 002-04619 Rev. *B
Page 47 of 193
CY91460P Series
[bit 9] STRT (Start)
Writing "1" to this bit starts A/D conversion (software activation).
• Write "1" again to restart conversion.
• Initialized to "0" by a software reset (RST).
• In continuous and stop mode, restarting is not occurred. Check BUSY bit before writing "1". (Activate conversion after clearing.)
• Do not specify forcible termination and software activation (BUSY="0" and STRT="1") at the same time.
[bit 8] reserved bit
Always write "0" to this bit.
ADCS0 : Access: Half-word, Byte
7
6
5
4
3
2
1
MD1
MD0
S10
ACH4
ACH3
ACH2
ACH1
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
ACH0 /
ACHMD
0
R,W
Bit
Initial value
Attribute
[bit 7, 6] MD1, MD0 (A/D converter mode set)
These bits the operation mode.
MD1
MD0
0
0
Single mode 1 (Reactivation during A/D conversion is allowed)
Operating mode
0
1
Single mode 2 (Reactivation during A/D conversion is not allowed)
1
0
Continuous mode (Reactivation during A/D conversion is not allowed)
1
1
Stop mode (Reactivation during A/D conversion is not allowed)
• Single mode:
A/D conversion is continuous performed from the selected start channel (ADSCH) to the selected end
channel (ADECH). The conversion stops once it has been done for all these channels.
• Continuous mode:
A/D conversion is repeatedly performed from the selected start channel (ADSCH) to the selected end
channel (ADECH) in a row.
• Stop mode:
A/D conversion is performed from the selected start channel (ADSCH) to the selected end channel
(ADECH), followed by a pause after each channel.
The conversion is resumed upon activation.
When A/D conversion is started in continuous mode or stop mode, conversion operation continued until stopped by the BUSY bit.
Conversion is stopped by writing “0” to the BUSY bit.
On activation after forcibly stopping, conversion starts from the start channel, selected by ADSCH register.
Reactivation during A/D conversion is disabled for any of the timer, external trigger and software start sources in single mode 2,
continuous and stop mode.
Document Number: 002-04619 Rev. *B
Page 48 of 193
CY91460P Series
[bit 5] S10
This bit defines resolution of A/D conversion. If this bit set "0", the resolution is 10-bit. In the other case, resolution is 8-bit and the
conversion result is stored to ADCR0 and in the lower 8 bits of the dedicated ADC result registers.
Initialized to "0" by a reset.
[bit 4 to 0] ACH4-0 (Analog convert select channel, read-only)
These bits show the number of the currently or previously converted analog channel, depending on bit ACHMD (see below).
ACH4
ACH3
ACH2
ACH1
ACH0
Converted channel
0
0
0
0
0
AN0
0
0
0
0
1
AN1
...
...
1
1
1
1
0
AN30
1
1
1
1
1
AN31
• Writing these bits has no effect (bit 0 is writable with special function ADCHMD).
• Initialized to "0000" by software reset (RST).
[bit 0] ACHMD (ACH register mode, write-only)
For reading out the ACH4-0 register bits (see below), there is a direct mode and a latched mode.
In direct mode, ACH4-0 shows the number of the ADC channel which is currently in conversion, e.g. the internal conversion channel
pointer. This pointer is incremented immediately after a conversion is finished.
In latched mode, ACH4-0 shows the number of the ADC channel whose conversion was finished previously. After a conversion is
finished, the conversion channel pointer is latched and the latched data can be read in this mode. At the end of the next conversion,
the latch is overwritten if no PAUSE condition exists.
ACHMD
Function
0
Direct ACH register mode [Initial value]
1
Latched ACH register mode
• ACHMD is a write-only bit.
• Read- or read-modify-write access returns the value of bit ACH0, see below.
• Initial value is 0.
Document Number: 002-04619 Rev. *B
Page 49 of 193
CY91460P Series
9.4.3 Common Data Register (ADCR1, ADCR0)
These registers store the conversion results of the A/D converter. ADCR0 stores lower 8-bit. ADCR1 stores upper 2-bit. The register
values are updated at the completion of each conversion. The registers normally store the results of the previous conversion.
ADCR1 : Access: Word, Half-word, Byte
15
0
R0, W0
14
0
R0, W0
13
0
R0, W0
12
0
R0, W0
11
0
R0, W0
10
0
R0, W0
9
D9
X
R
8
D8
X
R
3
D3
X
R
2
D2
X
R
1
D1
X
R
0
D0
X
R
Bit
Initial value
Attribute
ADCR0 : Access: Word, Half-word, Byte
7
D7
X
R
6
D6
X
R
5
D5
X
R
4
D4
X
R
Bit
Initial value
Attribute
• Bit 15 to 10 of ADCR1 are read as "0".
• The A/D converter has a conversion data protection function. See the "Operation" section for further information.
9.4.4 Dedicated A/D Channel Data Register (ADCD0 to ADCD31)
There are 32 ADC result data registers, one per channel. The registers are written by hardware at the end of conversion of the attached
channel. ADCD0 is attached to channel 0, ADCD31 is attached to channel 31.
ADCD0 ... ADCD31 : Access: Word, Half-word, Byte
15
0
R0
14
0
R0
13
0
R0
12
0
R0
11
0
R0
10
0
R0
9
D9
X
R
8
D8
X
R
7
D7
X
R
6
D6
X
R
5
D5
X
R
4
D4
X
R
3
D3
X
R
2
D2
X
R
1
D1
X
R
0
D0
X
R
Bit
Initial value
Attribute
Bit
Initial value
Attribute
• Bit 15 to 10 of the ADCD registers are read as "0".
• The A/D converter has a conversion data protection function. In continuous conversion mode, the protection function can be
changed to protect the A/D Channel Data registers rather then the A/D Data Register (ADCR1).
See section 9.6.6“Protection of the ADC Channel Data Registers” for further information.
Document Number: 002-04619 Rev. *B
Page 50 of 193
CY91460P Series
9.4.5 Sampling Timer Setting Register (ADCT)
ADCT register controls the sampling time and comparison time of analog input. This register sets A/D conversion time. Do not update
value of this register during A/D conversion operation.
ADCT1: Access: Word, Half-word, Byte
15
CT5
0
R/W
14
CT4
0
R/W
13
CT3
0
R/W
12
CT2
1
R/W
11
CT1
0
R/W
10
CT0
0
R/W
9
ST9
0
R/W
8
ST8
0
R/W
4
ST4
0
R/W
3
ST3
1
R/W
2
ST2
1
R/W
1
ST1
0
R/W
0
ST0
0
R/W
Bit
Initial value
Attribute
ADCT0: Access: Word, Half-word, Byte
7
ST7
0
R/W
6
ST6
0
R/W
5
ST5
1
R/W
Bit
Initial value
Attribute
[bit 15 to 10] CT5-0 (A/D comparison time set)
These bits specify clock division of comparison time.
• Setting "000001" means one division (=CLKP).
• Do not set these bits "000000".
• Initialized these bits to "000100" by software reset (RST).
• Comparison time = CT value * CLKP cycle * 10 + (4 * CLKP)
• Do not set comparison time over 500 μs.
[bit 9 to 0] ST9-0 (Analog input sampling time set)
These bits specify sampling time of analog input.
• Initialized these bits to "0000101100" by software reset (RST).
• Sampling time = ST value * CLKP cycle
• Do not set sampling time below 1.2 μs when AVCC is below 4.5 V.
Necessary sampling time and ST value are calculated by following.
• Necessary sampling time (Tsamp) = (Rext + Rin) * Cin * 7
• ST9 to ST0 = Tsamp / CLKP cycle
ST has to be set that sampling time is over Tsamp.
Example: CLKP = 32MHz, AVCC >= 4.5V, Rext = 200KΩ
Tsamp = ( 200 * 103 + 2.52 * 103 ) * 10.7 * 10-12 * 7 = 15.17 [μs]
ST = 15.17-6 / 31.25-9 = 485.44
ST has to be set over 486D (111100110B).
Tsamp is decided by Rext. Thus conversion time should be considered together with Rext.
Document Number: 002-04619 Rev. *B
Page 51 of 193
CY91460P Series
9.4.6 A/D Channel Setting Register (ADSCH, ADECH)
These registers specify the channels for the A/D converter to convert. Do not update these registers while the A/D converting is
operating.
ADSCH: Access: Word, Half-word, Byte
15
RX, W0
14
RX, W0
13
RX, W0
12
ANS4
0
R/W
11
ANS3
0
R/W
10
ANS2
0
R/W
9
ANS1
0
R/W
8
ANS0
0
R/W
Bit
Initial value
Attribute
ADECH : Access: Word, Half-word, Byte
7
RX, W0
6
RX, W0
5
RX, W0
4
ANE4
0
R/W
3
ANE3
0
R/W
2
ANE2
0
R/W
1
ANE1
0
R/W
0
ANE0
0
R/W
Bit
Initial value
Attribute
These bits set the start and end channel for A/D converter.
• Setting of ANE4 to ANE0 the same channel as in ANS4 to ANS0 specifies conversion for that channel only. (Single conversion)
• In continuous or stop mode, conversion is performed up to the channel specified by ANE4 to ANE0. Conversion then starts
again from the start channel specified by ANS4 to ANS0.
• If ANS > ANE, conversion starts with the channel specified by ANS, continuous up to channel 31, starts again from channel 0,
and ends with the channel specified by ANE.
• Initialized to ANS="00000", ANE="00000" by a software reset (RST).
Example: Channel Setting ANS=30ch, ANE=3ch, single conversion mode
Operation : Conversion channel 30ch -> 31ch -> 0ch -> 1ch -> 2ch -> 3ch end
[bit 12 to 8] ANS4-0 (Analog start channel set)
[bit 4 to 0] ANE4-0 (Analog end channel set)
ANS4
ANE4
ANS3
ANE3
ANS2
ANE2
ANS1
ANE1
ANS0
ANE0
Start / End Channel
0
0
0
0
0
AN0
0
0
0
0
1
AN1
0
0
0
1
0
AN2
0
0
0
1
1
AN3
...
...
1
1
1
0
1
AN29
1
1
1
1
0
AN30
1
1
1
1
1
AN31
Document Number: 002-04619 Rev. *B
Page 52 of 193
CY91460P Series
9.5 Range Comparator
9.5.1 Range Comparator Structure
The Range Comparator has 4 comparison groups with an upper and a lower threshold register each. The 32 ADC channels can be
enabled for range comparison and assigned to one of the 4 comparators individually. If enabled, the comparison will set up to 2 flags
for this ADC channel:
• An interrupt flag RCOINT, signalling that the ADC result is outside the range or, by “inverted” configuration, inside the range.
• An overflow flag RCOOF, showing that the range violation was an overflow and no underflow.
Furthermore, each ADC channel can be enabled to send an interrupt request to the CPU, if the RCOINT flag is set.
A/D Conversion result SAR[9:2]
Upper/lower threshold regs
Comparators
RCOH0[7:0]
>
RCOL0[7:0]
<
RCOOF
[0:31]
RCOH1[7:0]
>
32
Overflow
flags
RCOL1[7:0]
<
RCOH2[7:0]
>
RCOL2[7:0]
<
RCOH3[7:0]
>
RCOL3[7:0]
<
to R-Bus
RCOINT
[0:31]
to R-Bus
32
Interrupt
flags
Flag
setting
logic
AS[4:0] A/D Conversion current channel number
A/D Conversion result register load pulse (strobe)
ADE[31:0] A/D Channel Enable
AND
OR
RCOIRQ
A/D Channel Control registers (per ADC channel)
ADCC0 : RCOIE, RCOE, RCOS[1:0]
ADCC1 : RCOIE, RCOE, RCOS[1:0]
ADCC2 : RCOIE, RCOE, RCOS[1:0]
RCOIE[0:31]
ADCC3 : RCOIE, RCOE, RCOS[1:0]
...
ADCC30 : RCOIE, RCOE, RCOS[1:0]
ADCC31 : RCOIE, RCOE, RCOS[1:0]
RCOS[1:0]: Select one of the 4 comparators for this channel
RCOE : Enable Comparision for this ADC channel
RCOIE: Enable Comparision Interrupt for this ADC channel
Document Number: 002-04619 Rev. *B
RCOIRS[0:31]
Inverted Range Selection register:
Set the flags, if the ADC result is
inside upper and lower threshold,
instead of outside upper or lower
threshold (default).
Page 53 of 193
CY91460P Series
9.5.2 Range Comparator Registers
The Range Comparator (RCO) has the following registers:
• RCOHx[7:0] :
Upper threshold register, one register per comparator block (x = 0...3)
• RCOLx[7:0] :
Lower threshold register, one register per comparator block (x = 0...3)
• ADCCm[7:0] :
ADC channel control, one register per 2 ADC channels (m = 0...15)
• RCOIRS[0:31] : RCO Inverted Range Selection, one bit per ADC channel
• RCOOF[0:31] :
RCO Overflow Flags, one bit per ADC channel, read-only
• RCOINT[0:31] :
RCO Interrupt Flags, one bit per ADC channel
Range Comparator Threshold registers (RCOH0/L0 to RCOH3/L3)
RCOH0-3 : Higher threshold, access: Word, Half-word, Byte
15
RCOH7
1
R/W
14
RCOH6
1
R/W
13
RCOH5
1
R/W
12
RCOH4
1
R/W
11
RCOH3
1
R/W
10
RCOH2
1
R/W
9
RCOH1
1
R/W
8
RCOH0
1
R/W
Bit
Initial value
Attribute
[bit 7:0] RCOH[7:0] (Range Comparator High threshold)
The RCOH bits define the higher comparison threshold of the Range Comparator channel.
The upper Range Comparator compares that the upper 8 bits of the ADC conversion result are higher then RCOH[7:0] .
RCOL0-3 : Lower threshold, access: Word, Half-word, Byte
7
RCOL7
0
R/W
6
RCOL6
0
R/W
5
RCOL5
0
R/W
4
RCOL4
0
R/W
3
RCOL3
0
R/W
2
RCOL2
0
R/W
1
RCOL1
0
R/W
0
RCOL0
0
R/W
Bit
Initial value
Attribute
[bit 7:0] RCOL[7:0] (Range Comparator Low threshold)
The RCOL bits define the lower comparison threshold of the Range Comparator channel.
The lower Range Comparator compares that the upper 8 bits of the ADC conversion result are lower then RCOL[7:0] .
Document Number: 002-04619 Rev. *B
Page 54 of 193
CY91460P Series
A/D Converter Channel Control registers (ADCC0 to ADCC15)
The A/D channel control registers serve 2 ADC channels per register and control the range comparison for these channels.
ADCC0 register controls A/D channels 0 + 1,
ADCC1 register controls A/D channels 2 + 3,
...
ADCC15 register controls A/D channels 30 + 31
ADCC0-15: Access: Word, Half-word, Byte
7
6
5
4
RCOIE1
RCOE1
RCOS11
RCOS10
0
0
0
0
R/W
R/W
R/W
R/W
Bits 7:4 control A/D channels 1,3,5,7,...31
3
2
1
0
RCOIE0
RCOE0
RCOS01
RCOS00
0
0
0
0
R/W
R/W
R/W
R/W
Bits 3:0 control A/D channels 0,2,4,6,...,30
Bit
Initial value
Attribute
[bit 7,3] RCOIE1, RCOIE0 (Range Comparator Interrupt enable)
The RCOIE bits enable the Range Comparator interrupt for the corresponding ADC channel.
RCOIE
Function
0
RCO interrupt for this ADC channel is disabled [default]
1
RCO interrupt for this ADC channel is enabled
[bit 6,2] RCOE1, RCOE0 (Range Comparator operation enable)
The RCOE bits enable the Range Comparison for the corresponding ADC channel:
RCOE
Function
0
RCO disabled,
RCO flags for this ADC channel will not be set [default]
1
RCO enabled for this ADC channel
[bits 5:4,1:0] RCOS1[1:0], RCOS0[1:0] (converter channel select)
These bits select the A/D converter channel to be assigned to the Range Comparator channel:
RCOS[1:0]
Function
00
Select range comparator channel 0 for this ADC channel [default]
01
Select range comparator channel 1 for this ADC channel
10
Select range comparator channel 2 for this ADC channel
11
Select range comparator channel 3 for this ADC channel
Document Number: 002-04619 Rev. *B
Page 55 of 193
CY91460P Series
Inverted Range Selection register
The RCOIRS register controls that the comparison should check for “out of range” or “inside range”.
The 32 bits of RCOIRS is organized “per ADC channel”. ADC channel 0 is located on the MSB of the register and ADC channel 31
is on the LSB.
RCOnIRS : Access: Word, Half-word, Byte
31
RCOIRS0
0
R/W
30
RCOIRS1
0
R/W
29
RCOIRS2
0
R/W
28
RCOIRS3
0
R/W
27
RCOIRS4
0
R/W
26
RCOIRS5
0
R/W
259
RCOIRS6
0
R/W
24
RCOIRS7
0
R/W
23
RCOIRS8
0
R/W
22
RCOIRS9
0
R/W
21
RCOIRS10
0
R/W
20
RCOIRS11
0
R/W
19
RCOIRS12
0
R/W
18
RCOIRS13
0
R/W
17
RCOIRS14
0
R/W
16
RCOIRS15
0
R/W
15
RCOIRS16
0
R/W
14
RCOIRS17
0
R/W
13
RCOIRS18
0
R/W
12
RCOIRS19
0
R/W
11
RCOIRS20
0
R/W
10
RCOIRS21
0
R/W
9
RCOIRS22
0
R/W
8
RCOIRS23
0
R/W
7
RCOIRS24
0
R/W
6
RCOIRS25
0
R/W
5
RCOIRS26
0
R/W
4
RCOIRS27
0
R/W
3
RCOIRS28
0
R/W
2
RCOIRS29
0
R/W
1
RCOIRS30
0
R/W
0
RCOIRS31
0
R/W
Bit
Initial value
Attribute
Bit
Initial value
Attribute
Bit
Initial value
Attribute
Bit
Initial value
Attribute
Note that bit[31] is assigned to ADC channel 0, bit[30] is assigned to ADC channel one and so on.
[bits 31:0] RCOIRS[0:31] (Inverted Range Select)
The RCOIRS bits control how the Range Comparator result flags are set.
• If the RCOIRS[n] is 0, the flags are set when the ADC result is above the upper threshold
OR below the lower threshold. That is called “out of range” mode.
• If the RCOIRS[n] is 1, the flags are set when the ADC result is below or equal the upper threshold
AND above or equal the lower threshold. That is called “inside range” mode.
RCOIRSn
Function
0
Range comparison for this ADC channel checks for “out of range” (default)
1
Range comparison for this ADC channel checks for “inside range”
Document Number: 002-04619 Rev. *B
Page 56 of 193
CY91460P Series
Range Comparator Result Flags
The result of range comparison is stored in 2 flag registers:
• RCOINT[0:31]:Range comparison interrupt flags
• RCOOF[0:31]: Range comparison overflow flags
The Range Comparator Result flags are organized “per ADC channel”. There are 32 Range Comparator overflow flags and 32 interrupt
flags. In case of a RCO interrupt, all interrupt flags can be read out by one 32-bit read operation and analyzed using the Bit Search
Unit. The Bit Search Unit will return the number of the interrupting channel. Since bit search works from MSB to LSB (from left to right),
ADC channel 0 is located on the MSB of the registers and ADC channel 31 is on LSB.
RCOnINT : Access: Word, Half-word, Byte
31
RCOINT0
0
R/W0
30
RCOINT1
0
R/W0
29
RCOINT2
0
R/W0
28
RCOINT3
0
R/W0
27
RCOINT4
0
R/W0
26
RCOINT5
0
R/W0
259
RCOINT6
0
R/W0
24
RCOINT7
0
R/W0
23
RCOINT8
0
R/W0
22
RCOINT9
0
R/W0
21
RCOINT10
0
R/W0
20
RCOINT11
0
R/W0
19
RCOINT12
0
R/W0
18
RCOINT13
0
R/W0
17
RCOINT14
0
R/W0
16
RCOINT15
0
R/W0
15
RCOINT16
0
R/W0
14
RCOINT17
0
R/W0
13
RCOINT18
0
R/W0
12
RCOINT19
0
R/W0
11
RCOINT20
0
R/W0
10
RCOINT21
0
R/W0
9
RCOINT22
0
R/W0
8
RCOINT23
0
R/W0
7
RCOINT24
0
R/W0
6
RCOINT25
0
R/W0
5
RCOINT26
0
R/W0
4
RCOINT27
0
R/W0
3
RCOINT28
0
R/W0
2
RCOINT29
0
R/W0
1
RCOINT30
0
R/W0
0
RCOINT31
0
R/W0
Bit
Initial value
Attribute
Bit
Initial value
Attribute
Bit
Initial value
Attribute
Bit
Initial value
Attribute
Note that bit[31] is assigned to ADC channel 0, bit[30] is assigned to ADC channel one and so on.
[bits 31:0] RCOINT[0:31] (Range Comparator Interrupt flags)
The RCOINT flags show that a “out of range” or “inside range” condition has been found on the ADC channel.
The bits are set under the following condition:
• the ADC channel is enabled
ADER.ADE[i] is set
and
• the range comparison for this channel is enabled
ADCCn.RCOE[i] is set
and
• the conversion of the ADC channel is just finished
and
• an interrupt condition was found (see the table on next page).
• The bits are cleared by writing 0 or by software reset (RST). Writing 1 has no effect.
• Read-modify-write operations read 1.
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CY91460P Series
The interrupt condition depends on the comparison results and the RCOIRS setting for this channel:
Mode
out of
range
inside
range
RCOIRS
0
1
Upper
threshold
comparator
Lower
threshold
comparator
1
x
INT condition: above range, RCOOF is set
0
0
-
x
1
INT condition: below range, RCOOF is cleared
1
x
-
0
0
INT condition: inside range
x
1
-
Interrupt condition
Note: The upper threshold comparator returns 1 if the upper 8 bits of the ADC result are greater then the threshold value in RCOH[7:0].
The lower threshold comparator returns 1 if the upper 8 bits of the ADC result are smaller then the threshold value in
RCOL[7:0].
RCOnOF : Access: Read-only, Word, Half-word, Byte
31
RCOOF0
0
R
30
RCOOF1
0
R
29
RCOOF2
0
R
28
RCOOF3
0
R
27
RCOOF4
0
R
26
RCOOF5
0
R
259
RCOOF6
0
R
24
RCOOF7
0
R
23
RCOOF8
0
R
22
RCOOF9
0
R
21
RCOOF10
0
R
20
RCOOF11
0
R
19
RCOOF12
0
R
18
RCOOF13
0
R
17
RCOOF14
0
R
16
RCOOF15
0
R
15
RCOOF16
0
R
14
RCOOF17
0
R
13
RCOOF18
0
R
12
RCOOF19
0
R
11
RCOOF20
0
R
10
RCOOF21
0
R
9
RCOOF22
0
R
8
RCOOF23
0
R
7
RCOOF24
0
R
6
RCOOF25
0
R
5
RCOOF26
0
R
4
RCOOF27
0
R
3
RCOOF28
0
R
2
RCOOF29
0
R
1
RCOOF30
0
R
0
RCOOF31
0
R
Bit
Initial value
Attribute
Bit
Initial value
Attribute
Bit
Initial value
Attribute
Bit
Initial value
Attribute
Note that bit[31] is assigned to ADC channel 0, bit[30] is assigned to ADC channel one and so on.
[bits 31:0] RCOOF[0:31] (Range Comparator Overflow flag)
The RCOOF read-only flags store the output signal of the upper threshold comparator at the time when an interrupt condition (see
above) appeared and the corresponding RCOINT flag was not set. So the RCOOF flags indicate the upper comparator state when
the RCOINT flag had the last rising edge.
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CY91460P Series
The RCOOF flag for a ADC channel is loaded with the upper threshold comparator output signal under the following condition:
• the corresponding RCOINT flag is not yet setand
• the corresponding RCOINT flag has a set condition in this cycle.
The flags are initialized by software reset (RST).
RCOOFn
Function
0
The output of the upper threshold comparator was 0 [default]
1
The output of the upper threshold comparator was 1
9.5.3 Range Comparator Interrupt request
The Range Comparator has one interrupt output line RCOIRQ. The interrupt output line becomes active if at least one of the Range
Comparator interrupt flags RCOINT[31:0] is set and the corresponding interrupt enable bit in the ADCC registers is set.
It is not possible to activate a DMA request from the range comparator interrupts.
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CY91460P Series
9.6 Operation of A/D Converter
The A/D converter operates using the successive approximation method with 10-bit or 8-bit resolution. There is one 16-bit register
provided to store conversion results (ADCR), which is updated each time conversion completes. Additionally, there is one ADC Channel
Data register per channel (ADCD0...31), which is updated each time the assigned channel is converted. The Channel Data registers
especially improve the continuous conversion mode.
It is recommended to use the DMA service. The following describes the operation modes.
9.6.1 Single Mode
In single conversion mode, the analog input signals selected by the ANS bits and ANE bits are converted in order until the completion
of conversion on the end channel determined by the ANE bits. A/D conversion then ends. If the start channel and end channel are
the same (ANS=ANE), only a single channel conversion is performed.
Examples:
• ANS=00000b, ANE=00011b
Start -> AN0 -> AN1 -> AN2 -> AN3 -> End
• ANS=00010b, ANE=00010b
Start -> AN2 -> End
9.6.2 Continuous Mode
In continuous mode the analog input signals selected by the ANS bits and ANE bits are converted in order until the completion of
conversion on the end channel determined by the ANE bits, then the converter returns to the ANS channel for analog input and repeats
the process continuously. When the start and end channels are the same (ANS=ANE), conversion is performed continuously for that
channel.
Examples:
• ANS=00000b, ANE=00011b
Start -> AN0 -> AN1 -> AN2 -> AN3 -> AN0 ... -> repeat
• ANS=00010b, ANE=00010b
Start -> AN2 -> AN2 -> AN2 ... -> repeat
In continuous mode, conversion is repeated until '0' is written to the BUSY bit. (Writing '0' to the BUSY bit forcibly stops the conversion
operation.) Note that forcibly terminating operation halts the current conversion during mid-conversion. (If operation is forcibly
terminated, the value in the conversion register is the result of the most recently completed conversion.)
9.6.3 Stop Mode
In stop mode the analog input signal selected by the ANS bits and ANE bits are converted in order, but conversion operation pauses
after each channel. The pause is released by applying another start signal.
At the completion of conversion on the end channel determined by the ANE bits, the converter returns to the ANS channel for analog
input signal and repeats the conversion process continuously. When the start and end channel are the same (ANS=ANE), only a signal
channel conversion is performed.
Examples:
• ANS=00000b, ANE=00011b
Start -> AN0 -> stop -> start -> AN1 -> stop -> start -> AN2 -> stop -> start -> AN3 -> stop -> start -> AN0 ... -> repeat
• ANS=00010b, ANE=00010b
Start -> AN2 -> stop -> start -> AN2 -> stop -> start -> AN2 ... -> repeat
In stop mode the startup source is the source determined by the STS1, STS0 bits. This mode enables synchronization of the
conversion start signal.
Document Number: 002-04619 Rev. *B
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CY91460P Series
9.6.4 Single-shot Conversion
The following figure shows the operation of A/D converter in Single-shot conversion mode
AN input
(1)
Channel
selection
(2)
Activation
(trigger)
(4)
Internal level
Sample
hold
Conversion
value
Conversion Conversion Conversion
a
b
c
Conversion in progress
Previous conversion value
New conversion value
Flag clear on A/D conversion activation
(3)
BUSY
Conversion time
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Finalized
(7)
Buffer
(ADT)
Conversion end
(INT)
(5)
(8)
(6) Flag clear
(A/D conversion
activation,
or software)
Channel selection
A/D conversion activation (Trigger input: Software trigger/Reload timer/External trigger)
INT flag clear, BUSY flag set
Sample hold
Conversion (Conversion a + Conversion b + Conversion c)
Conversion end, INT flag set, BUSY flag clear
Buffers the conversion value. Buffered data storage
Software-based INT flag clear
Document Number: 002-04619 Rev. *B
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CY91460P Series
9.6.5 Scan Conversion
The following figure shows the operation of A/D converter in Scan conversion mode
AN input
Scan start
channel
selection
(1)
AN0
Activation (2)
(trigger)
(4)
AN1
Sample hold
AN2
(6)
AN3
AN1
AN0
AN2
AN3
AN0
(10)
(7)
(5)
a, b, c
Result registers
ADCD0
AN0 conversion value
ADCD1
AN1 conversion value
ADCD2
AN2 conversion value
ADCD3
AN3 conversion value
End of Scan INT
(3)
AN0 next conversion value
AN1 next value
AN2 next value
(8)
(9)
PAUS
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
Activation channel selection
A/D activation (Trigger: Software trigger/Reload timer/External trigger)
INT flag clear, PAUS flag clear
AN0 conversion
a. Sample hold, conversion (conversion a + conversion b + conversion c)
b. Conversion end
c. Buffers the conversion value.
AN1 conversion
AN2 conversion
AN3 conversion
INT2 (End of Scan) flag is set, AN0 conversion starts
Because INT2 has not been cleared yet, the ADC protects the result register of AN0
against overwriting and enters PAUSE state.
INT2 flag cleared by DMA or by software, the ADC stores the result of AN0 and continues sampling AN1.
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CY91460P Series
9.6.6 Protection of the ADC Channel Data Registers
There are 32 ADC result data registers, one register per channel. The registers are written by hardware at the end of conversion of
the attached channel. ADCD0 is attached to channel 0, ADCD31 is attached to channel 31.
The CPU can read the data registers any time.
If a conversion is finished and the data of the previous conversion has not been read out before, previous data would be overwritten.
To avoid this problem, the next conversion data is not stored in the data registers until the previous value has been read out (e.g. by
DMA). A/D conversion halts during this time and the PAUS flag is set. A/D conversion restarts when the ADC interrupt flag ADCR1.INT
is cleared.
The register protection function depends on the conversion mode and the setting of ADCR2.INTE2:
Mode
INTE2
Single, Stop
X
Protection of ADCR
0
Protection of ADCR
1
Protection of ADCD0...ADCD31
Continuous
Function
Protection of ADCD0...31
In continuous mode with INTE2==1, PAUS is set when data of the start channel (set by ADSCH) is ready for writing to the registers,
but IRQ2 (End of Scan interrupt) is already active.
Example: Start channel =4, end channel=7, continous mode, ADCS1.INTE=0, ADCS2.INTE2=1
Start by CPU --> convert channel 4 + safe data to ADCD4,
convert channel 5 + safe data to ADCD5,
convert channel 6 + safe data to ADCD6,
convert channel 7 + safe data to ADCD7 ---> End of Scan interrupt (IRQ2),
convert channel 4 + set PAUS (protect ADCD4...7).
After the CPU or DMA have read the data registers and cleared IRQ2, the scan conversion continues.
Protection of ADCR
In the other modes or if INTE2==0, PAUS is set when data of any channel is ready for writing to the registers, but IRQ (End of
Conversion) is active. Because in this mode the protection function is active after each single conversion, the ADCR register is
protected.
9.7 ADC Interrupt Generation and DMA Access
There are 2 ADC interrupt sources: End of Conversion and End of Scan.
9.7.1 End of Conversion
The End of Conversion (EoC) interrupt is enabled by ADCS1.INTE bit and is compatible to the A/D converts in old devices of CY91460
series. If EoC is enabled, it appears after any conversion cycle. It is recommended to use DMA transfer to read out the data from
ADCR.
9.7.2 End of Scan
The End of Scan (EoS) interrupt is enabled by ADCS2.INTE2 bit. If EoS is enabled, it appeares after the conversion of the end channel,
which is defined by the setting of ADECH register.
If the End of Conversion interrupt is enabled in parallel, both interrupt bits are set. In this case it is recommended that the interrupt
routine reads out ADCS2 register (containing mirrored bits of ADCS1[7:4]) to check where the interrupt comes from.
9.7.3 DMA Transfer
DMA transfer can be triggered by End of Conversion interrupt or by End of Scan interrupt. The interrupts are assigned to separate
DMA resource numbers (please refer to the Interrupt Vector Table).
The automatic interrupt clear after DMA transfer works for End of Conversion and for End of Scan separately.
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CY91460P Series
10. Handling Devices
10.1 Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage higher than (VDD5, VDD35 or HVDD5 *1) or less than (VSS5 or HVSS5 *1) is applied to
an input or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground pins. If latch-up occurs,
the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, be very careful not
to apply voltages in excess of the absolute maximum ratings.
Note *1: HVDD5, HVSS5 are available only on devices having Stepper Motor Controller.
10.2 Handling of unused input pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down
resistor (2KΩ to 10KΩ) or enable internal pullup or pulldown resisters (PPER/PPCR) before the input enable (PORTEN) is activated
by software. The mode pins MD_x can be connected to VSS5 or VDD5 directly. Unused ALARM input pins can be connected to AVSS5
directly.
10.3 Power supply pins
In CY91460 series, devices including multiple power supply pins and ground pins are designed as follows; pins necessary to be at
the same potential are interconnected internally to prevent malfunctions such as latch-up. All of the power supply pins and ground
pins must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation, to prevent
strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. Furthermore, the power supply
pins and ground pins of the CY91460 series must be connected to the current supply source via a low impedance.
It is also recommended to connect a ceramic capacitor of approximately 0.1 μF as a bypass capacitor between power supply pin and
ground pin near this device.
This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 μF (use a X7R ceramic capacitor) to VCC18C pin
for the regulator.
10.4 Crystal oscillator circuit
Noise in proximity to the X0 (X0A) and X1 (X1A) pins can cause the device to operate abnormally. Printed circuit boards should be
designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass capacitors connected to ground, are located
near the device and ground.
It is recommended that the printed circuit board layout be designed such that the X0 and X1 pins or X0A and X1A pins are surrounded
by ground plane for the stable operation.
Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this device.
10.5 Notes on using external clock
When using the external clock, it is necessary to simultaneously supply the X0 (X0A) and the X1 (X1A) pins. In the described
combination, X1 (X1A) should be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. At X0 and X1, a
frequency up to 16 MHz is possible.
Example of using opposite phase supply
X0 (X0A)
X1 (X1A)
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CY91460P Series
10.6 Mode pins (MD_x)
These pins should be connected directly to the power supply or ground pins. To prevent the device from entering test mode accidentally
due to noise, minimize the lengths of the patterns between each mode pin and power supply pin or ground pin on the printed circuit
board as possible and connect them with low impedance.
10.7 Notes on operating in PLL clock mode
If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may continue to operate
at the free-running frequency of the self-oscillating circuit of the PLL. However, this self-running operation cannot be guaranteed.
10.8 Pull-up control
The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin.
Document Number: 002-04619 Rev. *B
Page 65 of 193
CY91460P Series
11. Notes on Debugger
11.1 Execution of the RETI Command
If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding interrupt handling routine
will be executed repeatedly to the exclusion of other processing. This will prevent the main routine and the handlers for low priority
level interrupts from being executed (For example, if the time-base timer interrupt is enabled, stepping over the RETI instruction will
always break on the first line of the time-base timer interrupt handler).
Disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debugging.
11.2 Break function
If the range of addresses that cause a hardware break (including event breaks) is set to the address of the current system stack pointer
or to an area that contains the stack pointer, execution will break after each instruction regardless of whether the user program actually
contains data access instructions.
To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the target of the hardware
break (including an event breaks).
11.3 Operand break
It may cause malfunctions if a stack pointer exists in the area which is set as the DSU operand break. Do not set the access to the
areas containing the address of system stack pointer as a target of data event break.
11.4 Notes on PS register
As the PS register is processed in advance by some instructions, when the debugger is being used, the exception handling may result
in execution breaking in an interrupt handling routine or the displayed values of the flags in the PS register being updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, the operation before
and after the EIT always proceeds according to specification.
The following behavior may occur if any of the following occurs in the instruction immediately after a
DIV0U/DIV0S instruction:
(a) a user interrupt or NMI is accepted;
(b) single-step execution is performed;
(c) execution breaks due to a data event or from the emulator menu.
1. D0 and D1 flags are updated in advance.
2. An EIT handling routine (user interrupt/NMI or emulator) is executed.
3. Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated to the same values
as those in 1.
The following behavior occurs when an ORCCR, STILM, MOV Ri,PS instruction is executed to enable a user
interrupt or NMI source while that interrupt is in the active state.
1. The PS register is updated in advance.
2. An EIT handling routine (user interrupt/NMI or emulator) is executed.
3. Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in 1.
Document Number: 002-04619 Rev. *B
Page 66 of 193
CY91460P Series
12. Block Diagram
12.1 CY91F465PA, CY91F467PA
FR60 CPU
core
Flash-Cache
8 Kbytes
I-bus
32
D-RAM
24 KByte (CY91F465PA)
48 KByte (CY91F467PA)
CY91F465PA: 3 channels
CY91F467PA: 4 channels
Bit search
Flash memory
544 KByte (CY91F465PA)
1088 KByte (CY91F467PA)
D-bus
32
CAN
3/4 channels
RX0 to RX2,RX3
TX0 to TX2,TX3
32 16
bus adapter
ID-RAM
16 KByte (CY91F465PA)
32 KByte (CY91F467PA)
Bus converter
Data Flash
64 KByte / 8 bit
(CY91F467PA)
External
bus
interface
WEX
ASX
RDX
WRX0 to WRX1
SYSCLK
RDY
CSX0 to CSX2
A0 to A23
D16 to D31
DMAC
5 channels
R-bus
16
Clock modulator
Clock supervisor
Clock control
TTG0/8 to TTG23/31
PPG0 to PPG31
PPG timer
32 channels
TIN0/8 to TIN7/15
TOT0 to TOT7
Reload timer
16 channels
CK0 to CK7
ICU0 to ICU7
Free-run timer
8 channels
Input capture
8 channels
Clock monitor
MONCLK
Interrupt controller
External interrupt
16 channels
INT0 to INT15
LIN-USART
12 channels
SIN0 to SIN11
SOT0 to SOT11
SCK0 to SCK11
I2C
4 channels
SDA0 to SDA3
SCL0 to SCL3
Real time clock
OCU0 to OCU7
AIN0 to AIN3
BIN0 to BIN3
ZIN0 to ZIN3
PFM
Document Number: 002-04619 Rev. *B
Output compare
8 channels
Up/down counter
4 channels
PFM timer
1 channel
A/D converter
32 channels
A/D converter 2
9 ch., CY91F467PA only
Sound generator
1 channel
AN0 to AN31
ATGX
AN37 to AN42,
AN44 to AN46
SGA
SGO
Page 67 of 193
CY91460P Series
13. CPU and Control Unit
The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced instructions for
embedded applications.
13.1 Features
• Adoption of RISC architecture
Basic instruction: 1 instruction per cycle
• General-purpose registers: 32-bit × 16 registers
• 4 Gbytes linear memory space
• Multiplier installed
32-bit × 32-bit multiplication: 5 cycles
16-bit × 16-bit multiplication: 3 cycles
• Enhanced interrupt processing function
Quick response speed (6 cycles)
Multiple-interrupt support
Level mask function (16 levels)
• Enhanced instructions for I/O operation
Memory-to-memory transfer instruction
Bit processing instruction
Basic instruction word length: 16 bits
• Low-power consumption
Sleep mode/stop mode
13.2 Internal architecture
• The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent of each other.
• A 32-bit ↔ 16-bit buffer is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and peripheral resources.
• A Harvard ↔ Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between the CPU and
the bus controller.
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CY91460P Series
13.3 Programming model
13.3.1 Basic programming model
32 bits
Initial value
R0
XXXX XXXXH
...
R1
General-purpose registers
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Program counter
PC
Program status
RS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiply & divide registers
MDH
ILM
SCR
CCR
MDL
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CY91460P Series
13.4 Registers
13.4.1 General-purpose register
32 bits
Initial value
R0
XXXX XXXXH
R1
...
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation operations and as
pointers for memory access.
Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular applications.
R13 : Virtual accumulator
R14 : Frame pointer
R15 : Stack pointer
Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value).
13.4.2 PS (Program Status)
This register holds the program status, and is divided into three parts, ILM, SCR, and CCR.
All undefined bits (-) in the diagram are reserved bits. The read values are always “0”. Write access to these bits is invalid.
Bit position → bit 31
bit 20
bit 16
ILM
Document Number: 002-04619 Rev. *B
bit 10 bit 8 bit 7
SCR
bit 0
CCR
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CY91460P Series
13.4.3 CCR (Condition Code Register)
bit 7
SV
S
I
N
Z
V
C
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SV
S
I
N
Z
V
C
Initial value
- 000XXXXB
: Supervisor flag
: Stack flag
: Interrupt enable flag
: Negative enable flag
: Zero flag
: Overflow flag
: Carry flag
13.4.4 SCR (System Condition Register)
bit 10 bit 9
D1
D0
bit 8
Initial value
T
XX0B
Flag for step division (D1, D0)
This flag stores interim data during execution of step division.
Step trace trap flag (T)
This flag indicates whether the step trace trap is enabled or disabled.
The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution of user programs.
13.4.5 ILM (Interrupt Level Mask register)
bit 20 bit 19 bit 18 bit 17 bit 16
ILM4 ILM3 ILM2 ILM1 ILM0
Initial value
01111B
This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking.
The register is initialized to value “01111B” at reset.
13.4.6 PC (Program Counter)
bit 31
bit 0
Initial value
XXXXXXXXH
The program counter indicates the address of the instruction that is being executed.
The initial value at reset is undefined.
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CY91460P Series
13.4.7 TBR (Table Base Register)
bit 31
bit 0 Initial value
000FFC00H
The table base register stores the starting address of the vector table used in EIT processing.
The initial value at reset is 000FFC00H.
13.4.8 RP (Return Pointer)
bit 31
Initial value
bit 0
XXXXXXXXH
The return pointer stores the address for return from subroutines.
During execution of a CALL instruction, the PC value is transferred to this RP register.
During execution of a RET instruction, the contents of the RP register are transferred to PC.
The initial value at reset is undefined.
13.4.9 USP (User Stack Pointer)
bit 31
Initial value
bit 0
XXXXXXXXH
The user stack pointer, when the S flag is “1”, this register functions as the R15 register.
• The USP register can also be explicitly specified.
The initial value at reset is undefined.
• This register cannot be used with RETI instructions.
13.4.10 Multiply & divide registers
bit 31
bit 0
MDH
MDL
These registers are for multiplication and division, and are each 32 bits in length.
The initial value at reset is undefined.
Document Number: 002-04619 Rev. *B
Page 72 of 193
CY91460P Series
14. Embedded Program/Data Memory (Flash)
14.1 Flash features
•
•
•
•
•
•
CY91F465PA: 544 KBytes (8 × 64 Kbytes + 4 × 8 KBytes = 4.25 Mbits)
CY91F467PA: 1088 KBytes (16 × 64 Kbytes + 8 × 8 KBytes = 8.5 Mbits)
Programmable wait states for read/write access
Flash and Boot security with security vector at 0x0014:8000 - 0x0014:800F
Boot security
Basic specification: Same as MBM29LV400TC (except size and part of sector configuration)
14.2 Operation modes:
1. 64-bit CPU mode (available on CY91F467PA only) :
• CPU reads and executes programs in word (32-bit) length units.
• Flash writing is not possible.
• Actual Flash Memory access is performed in d-word (64-bit) length units.
2. 32-bit CPU mode:
• CPU reads and executes programs in word (32-bit) length units.
• Actual Flash Memory access is performed in word (32-bit) length units.
3. 16-bit CPU mode:
• CPU reads and writes in half-word (16-bit) length units.
• Program execution from the Flash is not possible.
• Actual Flash Memory access is performed in word (16-bit) length units.
Note: The operation mode of the flash memory can be selected using a Boot-ROM function. The function start address is 0xBF60.
The parameter description is given in the Hardware Manual in chapter 54.6 “Flash Access Mode Switching”.
Document Number: 002-04619 Rev. *B
Page 73 of 193
CY91460P Series
14.3 Flash access in CPU mode
14.3.1 Flash configuration
Flash memory map CY91F465PA
Addr
0014:FFFFh
0014:C000h
SA6 (8KB)
SA7 (8KB)
0014:BFFFh
0014:8000h
SA4 (8KB)
SA5 (8KB)
0014:7FFFh
0014:4000h
SA2 (8KB)
SA3 (8KB)
0014:3FFFh
0014:0000h
SA0 (8KB)
SA1 (8KB)
0013:FFFFh
0012:0000h
SA22 (64KB)
SA23 (64KB)
0011:FFFFh
0010:0000h
SA20 (64KB)
SA21 (64KB)
000F:FFFFh
000E:0000h
SA18 (64KB)
SA19 (64KB)
ROMS5
000D:FFFFh
000C:0000h
SA16 (64KB)
SA17 (64KB)
ROMS4
000B:FFFFh
000A:0000h
SA14 (64KB)
SA15 (64KB)
ROMS3
0009:FFFFh
0008:0000h
SA12 (64KB)
SA13 (64KB)
ROMS2
0007:FFFFh
0006:0000h
SA10 (64KB)
SA11 (64KB)
ROMS1
0005:FFFFh
0004:0000h
SA8 (64KB)
SA9 (64KB)
ROMS0
ROMS7
ROMS6
addr+0
16bit read/write
addr+1
addr+2
dat[31:16]
addr+3
dat[15:0]
addr+4
addr+5
addr+6
dat[31:16]
32bit read
dat[31:0]
dat[31:0]
Legend
Memory not available in this area
Memory available in this area
Document Number: 002-04619 Rev. *B
addr+7
dat[15:0]
Page 74 of 193
CY91460P Series
Flash memory map CY91F467PA
Address
0014:FFFFh
0014:C000h
SA6 (8KB)
SA7 (8KB)
0014:BFFFh
0014:8000h
SA4 (8KB)
SA5 (8KB)
0014:7FFFh
0014:4000h
SA2 (8KB)
SA3 (8KB)
0014:3FFFh
0014:0000h
SA0 (8KB)
SA1 (8KB)
0013:FFFFh
0012:0000h
SA22 (64KB)
SA23 (64KB)
ROMS7
ROMS6
0011:FFFFh
0010:0000h
SA20 (64KB)
SA21 (64KB)
000F:FFFFh
000E:0000h
SA18 (64KB)
SA19 (64KB)
ROMS5
000D:FFFFh
000C:0000h
SA16 (64KB)
SA17 (64KB)
ROMS4
000B:FFFFh
000A:0000h
SA14 (64KB)
SA15 (64KB)
ROMS3
0009:FFFFh
0008:0000h
SA12 (64KB)
SA13 (64KB)
ROMS2
0007:FFFFh
0006:0000h
SA10 (64KB)
SA11 (64KB)
ROMS1
0005:FFFFh
0004:0000h
SA8 (64KB)
SA9 (64KB)
ROMS0
addr+0
16bit read/write
addr+1
addr+2
dat[31:16]
32bit read/write
64bit read
Document Number: 002-04619 Rev. *B
addr+3
addr+4
dat[15:0]
addr+5
addr+6
dat[31:16]
dat[31:0]
addr+7
dat[15:0]
dat[31:0]
dat[63:0]
Page 75 of 193
CY91460P Series
14.3.2 Flash access timing settings in CPU mode
The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or maximum clock modulation)
for Flash read and write access.
Flash read timing settings (synchronous read)
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
to 24 MHz
0
0
0
-
1
to 48 MHz
0
0
1
-
2
to 100 MHz
1
1
3
-
4
Remark
Flash write timing settings (synchronous write)
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
to 16 MHz
0
-
-
0
3
to 32 MHz
0
-
-
0
4
to 48 MHz
0
-
-
0
5
to 64 MHz
1
-
-
0
6
to 96 MHz
1
-
-
0
7
to 100 MHz
1
-
-
1
8
Document Number: 002-04619 Rev. *B
Remark
Page 76 of 193
CY91460P Series
14.3.3 Address mapping from CPU to parallel programming mode
The following tables show the calculation from CPU addresses to flash macro addresses which are used in parallel programming.
Address mapping CY91F465PA
CPU Address
(addr)
Condition
Flash
sectors
FA (flash address) Calculation
14:8000h
to
14:FFFFh
addr[2]==0
SA4, SA6
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2 (addr/2)%4 + addr%4 - 0D:0000h
14:8000h
to
14:FFFFh
addr[2]==1
SA5, SA7
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2 +
00:2000h - (addr/2)%4 + addr%4 - 0D:0000h
08:0000h
to
13F:FFFFh
addr[2]==0
SA12, SA14, SA16, SA18
(64 Kbyte)
FA := addr - addr%02:0000 + (addr%02:0000h)/2 (addr/2)%4 + addr%4
08:0000h
to
13F:FFFFh
addr[2]==1
SA13, SA15, SA17, SA19
(64 Kbyte)
FA := addr - addr%02:0000h + (addr%02:0000h)/2 +
01:0000h - (addr/2)%4 + addr%4
Note: FA result is without 10:0000h offset for parallel Flash programming.
Set offset by keeping FA[20] = 1 as described in section “Parallel Flash programming mode”.
Address mapping CY91F467PA
CPU Address
(addr)
Condition
Flash
sectors
FA (flash address) Calculation
14:0000h
to
14:FFFFh
addr[2]==0
SA0, SA2, SA4, SA6
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 05:0000h
14:0000h
to
14:FFFFh
addr[2]==1
SA1, SA3, SA5, SA7
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 05:0000h
+ 00:2000h
04:0000h
to
13:FFFFh
addr[2]==0
SA8, SA10, SA12, SA14, SA16,
SA18, SA20, SA22
(64 Kbyte)
FA := addr - addr%02:0000 + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 + 0C:0000h
04:0000h
to
13:FFFFh
addr[2]==1
SA9, SA11, SA13, SA15, SA17,
SA19, SA21, SA23
(64 Kbyte)
FA := addr - addr%02:0000h + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 + 0C:0000h
+ 01:0000h
Note: FA result is without 20:0000h offset for parallel Flash programming.
Set offset by keeping FA[21] = 1 as described in section “Parallel Flash programming mode”.
Document Number: 002-04619 Rev. *B
Page 77 of 193
CY91460P Series
14.4 Parallel Flash programming mode
14.4.1 Flash configuration in parallel Flash programming mode
Parallel Flash programming mode (MD[2:0] = 111):
CY91F465PA
CY91F467PA
FA[20:0]
FA[21:0]
001F:FFFFh
001F:0000h
SA19 (64KB)
003F:FFFFh
003F:0000h
SA23 (64KB)
001E:FFFFh
001E:0000h
SA18 (64KB)
003E:FFFFh
003E:0000h
SA22 (64KB)
001D:FFFFh
001D:0000h
SA17 (64KB)
003D:FFFFh
003D:0000h
SA21 (64KB)
001C:FFFFh
001C:0000h
SA16 (64KB)
003C:FFFFh
003C:0000h
SA20 (64KB)
001B:FFFFh
001B:0000h
003B:FFFFh
003B:0000h
SA19 (64KB)
SA15 (64KB)
001A:FFFFh
001A:0000h
003A:FFFFh
003A:0000h
SA18 (64KB)
SA14 (64KB)
0039:FFFFh
0039:0000h
SA17 (64KB)
0019:FFFFh
0019:0000h
SA13 (64KB)
0038:FFFFh
0038:0000h
SA16 (64KB)
0018:FFFFh
0018:0000h
SA12 (64KB)
0037:FFFFh
0037:0000h
SA15 (64KB)
0036:FFFFh
0036:0000h
SA14 (64KB)
SA10 (64KB)
0035:FFFFh
0035:0000h
SA13 (64KB)
SA9 (64KB)
0034:FFFFh
0034:0000h
SA12 (64KB)
SA8 (64KB)
0033:FFFFh
0033:0000h
SA11 (64KB)
0017:FFFFh
0017:E000h
SA7 (8KB)
0032:FFFFh
0032:0000h
SA10 (64KB)
0017:DFFFh
0017:C000h
SA6 (8KB)
0031:FFFFh
0031:0000h
SA9 (64KB)
0017:BFFFh
0017:A000h
SA5 (8KB)
0030:FFFFh
0030:0000h
SA8 (64KB)
0017:9FFFh
0017:8000h
002F:FFFFh
002F:E000h
SA7 (8KB)
SA4 (8KB)
002F:DFFFh
002F:C000h
SA6 (8KB)
002F:BFFFh
002F:A000h
SA5 (8KB)
002F:9FFFh
002F:8000h
SA4 (8KB)
002F:7FFFh
002F:6000h
SA3 (8KB)
002F:5FFFh
002F:4000h
SA2 (8KB)
002F:3FFFh
002F:2000h
SA1 (8KB)
002F:1FFFh
002F:0000h
SA0 (8KB)
SA11 (64KB)
SA3 (8KB)
SA2 (8KB)
SA1 (8KB)
SA0 (8KB)
16bit write mode
FA[1:0]=00
FA[1:0]=10
DQ[15:0]
DQ[15:0]
Remark: Always keep FA[0] = 0 and FA[20] = 1
Legend
Memory available in this area
16bit write mode
FA[1:0]=00
FA[1:0]=10
DQ[15:0]
DQ[15:0]
Memory not available in this area
Remark: Always keep FA[0] = 0 and FA[21] = 1
Document Number: 002-04619 Rev. *B
Page 78 of 193
CY91460P Series
14.4.2 Pin connections in parallel programming mode
Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory's interface circuit enables
direct control of the Flash memory unit from external pins by directly linking some of the signals to GP-Ports. Please see table below
for signal mapping.
In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set when writing/erasing
using the parallel Flash programmer. In this mode, all operations of the 8.5 Mbits Flash memory's Auto Algorithms are available.
Correspondence between MBM29LV400TC and Flash Memory Control Signals
CY91F465PA, CY91F467PA external pins
MBM29LV400TCEx
ternal pins
FR-CPU mode
Flash memory
mode
Normal function
Pin number
-
INITX
-
INITX
104
RESET
-
FRSTX
NMIX
105
-
-
MD_2
MD_2
96
Set to ‘1’
-
-
MD_1
MD_1
95
Set to ‘1’
-
-
MD_0
MD_0
94
Set to ‘1’
RY/BY
FMCS:RDY bit
RY/BYX
P19_0
112
BYTE
Internally fixed to ‘H’
BYTEX
P19_2
114
WE
WEX
P18_0
118
OE
OEX
P19_6
117
CEX
P19_5
116
CE
-
Internal control signal +
control via interface
circuit
Comment
ATDIN
MD_3
98
Set to ‘0’
EQIN
MONCLK
97
Set to ‘0’
-
TESTX
P19_4
115
Set to ‘1’
-
RDYI
P19_1
113
Set to ‘0’
Set to ‘0’
-
A-1
FA0
P17_5
124
A0 to A7
FA1 to FA8
P06_0 to P06_7
6 to 13
A8 to A15
FA9 to FA16
P05_0 to P05_7
14 to 21
FA17 to FA19
P18_1, P18_2, P18_4
119, 120, 121
FA20
P18_5
122
Set to ‘1’ on
CY91F465PA
Not needed on
CY91F465PA;
Set to ‘1’ on
CY91F467PA
A16 to A18
A19
Internal address bus
—
DQ0 to DQ7
DQ8 to DQ15
Internal data bus
FA21
P18_6
123
DQ0 to DQ7
P01_0 to P01_7
24 to 31
DQ8 to DQ15
P00_0 to P00_7
32 to 39
14.5 Poweron Sequence in parallel programming mode
The flash memory can be accessed in programming mode after a certain wait time, which is needed for Security Vector fetch:
• Minimum wait time after VDD5/VDD5R power on:
2.76 ms
• Minimum wait time after INITX rising:
1.0 ms
Document Number: 002-04619 Rev. *B
Page 79 of 193
CY91460P Series
14.6 Flash Security
14.6.1 Vector addresses
Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1, BSV2) controlling the protection
functions of the Flash Security Module:
FSV1: 0x14:8000
BSV1: 0x14:8004
FSV2: 0x14:8008
BSV2: 0x14:800C
14.6.2 Security Vector FSV1
The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes and the individual write protection
of the 8 Kbytes sectors.
FSV1 (bit31 to bit16)
The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write protection modes.
Explanation of the bits in the Flash Security Vector FSV1[31:16]
FSV1[31:19]
FSV1[18]
Write Protection
Level
FSV1[17]
Write Protection
FSV1[16]
Read Protection
Flash Security Mode
set all to ‘0’
set to ‘0’
set to ‘0’
set to ‘1’
Read Protection (all device modes, except
INTVEC mode MD[2:0]=”000”)
set all to ‘0’
set to ‘0’
set to ‘1’
set to ‘0’
Write Protection (all device modes, without
exception)
set all to ‘0’
set to ‘0’
set to ‘1’
set to ‘1’
Read Protection (all device modes, except
INTVEC mode MD[2:0]=”000”) and Write
Protection (all device modes)
set all to ‘0’
set to ‘1’
set to ‘0’
set to ‘1’
Read Protection (all device modes, except
INTVEC mode MD[2:0]=”000”)
set all to ‘0’
set to ‘1’
set to ‘1’
set to ‘0’
Write Protection (all device modes, except
INTVEC mode MD[2:0]=”000”)
set to ‘1’
Read Protection (all device modes, except
INTVEC mode MD[2:0]=”000”) and Write
Protection (all device modes except INTVEC
mode MD[2:0]=”000”)
set all to ‘0’
set to ‘1’
Document Number: 002-04619 Rev. *B
set to ‘1’
Page 80 of 193
CY91460P Series
FSV1 (bit15 to bit0)
The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write protection of the 8 Kbytes sectors. It is
only evaluated if write protection bit FSV1[17] is set.
Explanation of the bits in the Flash Security Vector FSV1[15:0]
Note:
FSV1 bit
Sector
Enable Write
Protection
Disable Write
Protection
FSV1[0]
SA0 (CY91F467PA)
set to “0”
set to “1”
not available
FSV1[1]
SA1 (CY91F467PA)
set to “0”
set to “1”
not available
FSV1[2]
SA2 (CY91F467PA)
set to “0”
set to “1”
not available
FSV1[3]
SA3 (CY91F467PA)
set to “0”
set to “1”
Comment
not available
Write protection is
mandatory!
FSV1[4]
SA4
set to “0”
—
FSV1[5]
SA5
set to “0”
set to “1”
FSV1[6]
SA6
set to “0”
set to “1”
FSV1[7]
SA7
set to “0”
set to “1”
FSV1[8]
—
set to “0”
set to “1”
not available
FSV1[9]
—
set to “0”
set to “1”
not available
FSV1[10]
—
set to “0”
set to “1”
not available
FSV1[11]
—
set to “0”
set to “1”
not available
FSV1[12]
—
set to “0”
set to “1”
not available
FSV1[13]
—
set to “0”
set to “1”
not available
FSV1[14]
—
set to “0”
set to “1”
not available
FSV1[15]
—
set to “0”
set to “1”
not available
It is mandatory to always set the sector where the Flash Security Vectors FSV1 and FSV2 are located to write protected (here
sector SA4). Otherwise it is possible to overwrite the Security Vector to a setting where it is possible to either read out the
Flash content or manipulate data by writing.
See section “Flash access in CPU mode” for an overview about the sector organization of the Flash Memory.
Document Number: 002-04619 Rev. *B
Page 81 of 193
CY91460P Series
14.6.3 Security Vector FSV2
The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write protection of the 64 kByte sectors. It is
only evaluated if write protection bit FSV1[17] is set.
Explanation of the bits in the Flash Security Vector FSV2[31:0]
FSV2 bit
Sector
Enable Write Protection
Disable Write Protection
FSV2[0]
SA8 (CY91F467PA)
set to “0”
set to “1”
FSV2[1]
SA9 (CY91F467PA)
set to “0”
set to “1”
FSV2[2]
SA10 (CY91F467PA)
set to “0”
set to “1”
FSV2[3]
SA11 (CY91F467PA)
set to “0”
set to “1”
FSV2[4]
SA12
set to “0”
set to “1”
FSV2[5]
SA13
set to “0”
set to “1”
FSV2[6]
SA14
set to “0”
set to “1”
FSV2[7]
SA15
set to “0”
set to “1”
FSV2[8]
SA16
set to “0”
set to “1”
FSV2[9]
SA17
set to “0”
set to “1”
FSV2[10]
SA18
set to “0”
set to “1”
FSV2[11]
SA19
set to “0”
set to “1”
FSV2[12]
SA20 (CY91F467PA)
set to “0”
set to “1”
FSV2[13]
SA21 (CY91F467PA)
set to “0”
set to “1”
FSV2[14]
SA22 (CY91F467PA)
set to “0”
set to “1”
FSV2[15]
SA23 (CY91F467PA)
set to “0”
set to “1”
FSV2[31:16]
—
set to “0”
set to “1”
Comment
not available
Note : See section “Flash access in CPU mode” for an overview about the sector organisation of the Flash Memory.
14.7 Notes About Flash Memory CRC Calculation
The Flash Security macro contains a feature to calculate the 32-bit checksum over addresses located in the Flash Memory address
space. This feature is described in the CY91460 Series Hardware Manual, chapter 55.4.1 “Flash Security Control Register”.
Additional notes are given here:
The CRC calculation runs on the internal RC clock. It is recommended to switch the RC clock frequency to 2 MHz for shortening the
calculation time. However, the CPU clock (CLKB) must be faster then RC clock, otherwise the CRC calculation may not start correctly.
Document Number: 002-04619 Rev. *B
Page 82 of 193
CY91460P Series
15. Embedded Data Flash (CY91F467PA)
CY91F467PA contains a 64 KByte internal data flash.
15.1 Data Flash Features
•
•
•
•
•
•
•
•
•
•
CY91F467PA: 64 Kbytes (4 × 16 Kbytes + 1 × 256 bytes security sector)
Data width of flash macro: 8 bit
Synchronous flash interface and flash macro
2 access modes (direct access, command sequencer access)
Read access 8/16/32-bit by internal sequencer hardware
Write access 8-bit in direct access mode, 8/16/32-bit in command sequencer write mode
Programmable wait states for read/write access
Data Flash Security feature (read and write protection)
CRC calculation feature
Interrupt- and DMA request, DMA stop request
15.2 Data Flash Block Diagram
The Data Flash consists of the flash macro and interface, control, status, command sequencer and security logic.
On CY91460 series devices, the Data Flash is connected to the X-Bus in parallel to the External Bus interface:
BAAX
WEX
ASX
RDX
WRX0 to WRX3
BRQ
MCLKE
MCLKO
MCLKI
SYSCLK
BGRNTX
RDY
CSX0 to CSX7
8
direct mode write data
32
read data
Data Flash
Control/Status
Registers
Document Number: 002-04619 Rev. *B
External
bus
interface
DMA Interrupt Clear
DMA STOP Request
Data Flash
Write Command
Sequencer
32
Data
Flash
bus
interface
DMA Request
Interrupt Request
X-bus 32
A0 to A31
D0 to D31
8
8
Data
Flash
macro
interface
Data
Flash
Security
8
Data
Flash
macro
mask
&
8
RDY
Data Flash
Page 83 of 193
CY91460P Series
15.3 Data Flash Operation Modes
The data flash is located in the top address space of external bus area. Per default (after software reset RST), the data flash is
disabled and does not accept any read/write access. The data flash can be enabled by setting the bit DFCS:FLASHEN (DFCS is the
Data Flash Control/Status register).
15.3.1 Direct Access mode:
The Direct Access mode provides data flash access similar to the access of the embedded program/data flash (main flash). For
write/program operations, the flash command sequences must be written by the CPU. The command sequences are the same as
used for the embedded program/data flash (main flash).
• CPU reads data in byte, halfword or word (8/16/32-bit) length units, whereas 16- or 32-bit read operations are split into 2 or 4
sequential 8-bit flash macro read accesses by hardware.
• CPU writes data in byte (8-bit) width units.
• For write/program operations, the flash command sequences must be written by the CPU.
• The flash macro auto algorithms (Chip Erase, Sector Erase, Sector Erase Suspend,...) can only be activated in direct access
mode.
• Direct access mode is the default mode after software reset (RST).
15.3.2 Command Sequencer Mode:
In command sequencer mode, the flash macro command sequences for data write operation are generated by hardware.
• CPU reads data in byte, halfword or word (8/16/32-bit) length units (same as in direct access mode).
• CPU writes data in byte, halfword or word (8/16/32-bit) length units using normal “store” instructions. The flash macro command
sequences are generated by internal command sequencer hardware. For 16- or 32-bit write, 2 or 4 command sequences are
generated, respectively.
• The data flash interface will not issue wait states after a command sequencer write operation was started. The CPU can continue
working during data flash programming.
• If a command sequencer write operation is ongoing, and the CPU writes data again, this second write request is ignored! The
error flag DFWS:PAERF is set in case of such a prohibited access. It is recommended to use the data flash interrupts, which
indicate that the proceeding write sequence was finished and successful.
• If a command sequencer write operation is ongoing, and the CPU tries to read data, 0x00 is returned and the error flag
DFWS:PAERF is set.
• The flash macro auto algorithms (Chip Erase, Sector Erase, Sector Erase Suspend,...) cannot be activated.
• Command Sequencer mode is enabled by setting the bit DFWC:WE (Data Flash Write Control register).
• After software reset (RST), the command sequencer mode is disabled.
15.3.3 Parallel Programming mode:
• The parallel programming mode works similar to the main flash memory. The function/timing of some external control lines are
different.
• In parallel programming mode, it is not necessary to set the Data Flash enable bit (DFCS:FLASHEN).
• Data Flash Memory access is performed in byte (8-bit) length units.
Document Number: 002-04619 Rev. *B
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CY91460P Series
15.4 Data Flash access in CPU mode
15.4.1 Data Flash memory map CY91F467PA
The Data Flash macro is 8 bit wide. It is located in the top address space of external bus area:
CPU
address
Parallel
programming
mode
address
0050 0000H
External bus area
FFFB F000H
Dummy addresses for auto algorithm
FFFB FF00H
Data Flash Security Sector (256 Byte)
FFFC 0000H
FFFC 4000H
FFFC 8000H
FFFC C000H
Data Flash Sector 0 (16 KB)
Data Flash Sector 1 (16 KB)
Data Flash Sector 2 (16 KB)
Data Flash Sector 3 (16 KB)
FFFD 0000H
00 FF00H
01 0000H
01 4000H
01 8000H
01 C000H
01 FFFFH
External bus area
FFFF FFFFH
Note: The address in parallel programming mode is listed here without 10:0000h offset.
Set the offset by keeping FA[22:20] = 001 the same kind as used for programming of the main flash.
Note: The “Dummy addresses for auto algorithm” are accepted although they are located below the physical addresses of the flash
macro. This address space is needed to apply correct addresses in auto algorithms.
See the example in 15.4.4“Auto Program Algorithms”. However, toggle flags cannot be read using the dummy addresses.
15.4.2 Data Flash and External Bus
If the Data Flash is disabled (see 15.3“Data Flash Operation Modes”), the complete address space can be used for the external bus.
If the Data Flash is enabled, the user should take care that no external bus chip select area overlaps the address range of the Data
Flash.
If a chip select area overlaps the Data Flash addresses, the following scenario may appear:
• Write operations will be sent to data flash and external bus in parallel. This may cause heavy problems, especially if the data
flash is written in direct mode, where the CPU sends the command sequences for programming
(see 15.3.1“Direct Access mode:”).
• Read operations will return unpredictable results.
15.4.3 Flash access timing settings in CPU mode
The Data Flash can be accessed up to CLKB = 100 MHz. For timing and wait state setup, please refer to the description of the bits
TMG2, TMG1, TMG0 in 15.5.1“Data Flash Control and Status Register”.
Although the data flash is located in the address space of external bus, there is no dependency between external bus timing and data
flash timing.
Document Number: 002-04619 Rev. *B
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CY91460P Series
15.4.4 Auto Program Algorithms
The auto program algorithms can only be applied in direct access mode, while the “Program” sequence can be generated by hardware
if the Command Sequencer Mode is used.
The data flash supports command sequences similar to the main flash:
Command B u s
Sequenc
Write
e
Cycle
Read/Reset
1
Read/Reset
3
Program
4
Chip Erase
6
Sector Erase
6
Sector Erase Suspend
Sector Erase Resume
Unlock
Bypass
3
set
Unlock
Bypass
2
program
Unlock
2
Bypass
Reset
1 s t
b u s 2 n d b u s 3 r d
b u s 4 t h
b u s
Write cycle
Write cycle
Write cycle
Write cycle
Address D a t a Address D a t a Address D a t a
XXX
F0
RA
RD
AA8
AA
554
55
AA8
F0
RA
RD
AA8
AA
554
55
AA8
A0
PA
PD
AA8
AA
554
55
AA8
80
AA8
AA
AA8
AA
554
55
AA8
80
AA8
AA
Sector Erase Suspend by input of address “XXX" and data “B0”
Sector Erase Resume by input of address “XXX" and data “30”
AA8
AA
554
55
XXX
A0
PA
PD
XXX
90
XXX
F0/
00
AA8
5 t h b u s
Write cycle
Address D a t a
554
554
55
55
6 t h b u s
Write cycle
Address Data
AA8
SA
10
30
20
PA: Program Address
PD: Program Data. Data to be programmed at location PA.
RA: Read Address
RD: Data to read at location RA.
SA: Sector Address (points into the sector to be erased)
It is recommended that the addresses “AA8” and “554” point to the sector which is to be programmed.
For example, to program a byte into sector SAS, the following sequence should be used:
AddressPA=0xFFFBFF83 is inside sector SAS.
1. write
addr=0xFFFBFAA8
data=0xAA
2. write
addr=0xFFFBF554
data=0x55
3. write
addr=0xFFFBFAA8
data=0xA0
4. write
addr=0xFFFBFF83 =PA
data=PD
Note: The address for the write sequence (1., 2., 3. write) points into the “Dummy addresses for auto algorithm” here. For polling of
toggle bits, an address pointing inside the programmed sector has to be used, for example the programmed address (PA) itself.
Document Number: 002-04619 Rev. *B
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CY91460P Series
15.4.5 Data Flash Hardware Sequence Flags (Toggle Bits)
In direct access mode, the data flash returns toggle bits shown in the following table.
In command sequencer mode, it is not necessary to read the toggle bits because they are observed by the command sequencer
automatically.
Status
Embedded Program Algorithm
Embedded Erase Algorithm
(Erase Suspended Sector)
In
Progress
DQ5
DQ4
DQ3
DQ2
~DQ7
Toggle
0
0
0
1
0
Toggle
0
1
Toggle
1
1
1
0
Ready to suspend
Busy to suspend
1
0
Toggle
0
0
Ready to suspend
Erase Suspend Read
(Erase Suspended Sector)
Exceeded
Time
Limits
DQ6
Busy to suspend
Embedded Erase Algorithm
(Non-Erase Suspended Sector)
Erase
Mode
DQ7
Suspended
1
1
0
0
0
Toggle
Erase Suspend Read
(Non-Erase Suspended Sector)
Erase Suspend Program
(Non-Erase Suspended Sector)
Embedded Program Algorithm
Embedded Erase Algorithm
Data
Data
Data
Data
Data
Data
~DQ7
Toggle
0
0
0
1
~DQ7
0
Toggle
Toggle
1
1
0
N/A
0
1
1
N/A
Erase
Mode
~DQ7
Toggle
1
0
0
N/A
Suspended
Erase Suspend Program
(Non-Erase Suspended Sector)
Note: For polling of toggle bits, an address pointing inside the programmed sector has to be used, for example the programmed
address itself. Do not use a “Dummy addresses for auto algorithm”.
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CY91460P Series
15.5 Data Flash Registers
The Data Flash has the following control/status registers:
DFCS : Data Flash Control and Status Register
Address
07114H
31
RDYI
0
R/W
30
TMG2
1
R/W
29
TMG1
1
R/W
28
TMG0
1
R/W
27
FLASHEN
0
R/W
26
INTE
0
R/W
25
RDYINT
0
R/W0
24
RDY
1
R
19
FININTE
0
R/W
18
IDLINTE
0
R/W
17
IDLDMAE
0
R/W
16
WE
0
R/W
11
FININT
0
R/W0
10
IDLINT
0
R/W0
9
ST1
0
R
8
ST0
0
R
bit
Initial value
Attribute
DFWC : Data Flash Write Command Sequencer Control Register
Address
07115H
23
x
-
22
x
-
21
x
-
20
ERINTE
0
R/W
bit
Initial value
Attribute
DFWS : Data Flash Write Command Sequencer Status Register
Address
07116H
15
PAERF
0
R/W0
14
WIERINT
0
R/W0
13
WERINT
0
R/W0
12
TOERINT
0
R/W0
bit
Initial value
Attribute
DFSCR0 : Data Flash Security Control Register 0
Address
07118H
31:24
23:16
15:8
7:0
bit
1111 1111
R
1111 1111
R
Initial value
Attribute
15:8
7:0
bit
0000 0000
R, R/W
0000 0000
R, R/W
Initial value
Attribute
DFSCR0[31:0]
1111 1111
R/W, R
1111 1111
R
DFSCR1 : Data Flash Security Control Register 1
Address
0711CH
31:24
23:16
DFSCR1[31:0]
0 - - - 0001
R, R/W
Document Number: 002-04619 Rev. *B
0000 0000
R, R/W
Page 88 of 193
CY91460P Series
15.5.1 Data Flash Control and Status Register
This section explains the Data Flash Control and Status register.
DFCS : Data Flash Control and Status register
Addr:
0x07114
31
30
29
28
27
26
25
24
RDYI
TMG2
TMG1
TMG0
FLASHEN
INTE
RDYINT
RDY
0
1
1
1
0
0
0
1
initial
R/W
R/W
R/W
R/W
R/W
R/W
R/W0
R
attribute
RDYI
bit
Ready Inversion
0
(default) Normal flash operation
1
Setting this bit to ’1’ activates the RDYI input of the Flash. As a result, the RDY output of the Flash goes to ’0’ (used
for test purposes only). Always write 0 to this bit.
• This bit is cleared by software reset (RST).
• Always write 0 to this bit.
Data Flash Timing Control
TMG2
TMG1
TMG0
CLKB Frequency
up to
CLKB Cycles per
Read Operation
CLKB Cycles per
Write Operation
0
0
0
6.2 MHz
3
3
0
0
1
16.7 MHz
4
3
0
1
0
33.3 MHz
5
3
0
1
1
50 MHz
6
3
1
0
0
66.6 MHz
8
4
1
0
1
83.3 MHz
9
5
1
1
0
100 MHz
10
6
1
1
1
(default) 100 MHz
11
6
• These bits control the number of wait cycles for read and write operations.
• The bits are set to “111” by software reset (RST) and can be read and written
FLASHEN
Data Flash Enable
0
(default) Data Flash is disabled and does not accept read and write access
1
Data Flash is enabled and can be read and written depending on data flash security settings.
• This bit is cleared by software reset (RST) and can be read and written
• Before setting this bit, the user has to take care that no External Bus Chip Select area overlaps the data flash address space.
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CY91460P Series
INTE
Ready Interrupt Enable
0
(default) Disable the interrupt of the RDYINT flag
1
Enable the interrupt of the RDYINT flag
• If this bit is cleared, no interrupt is generated when the RDYINT flag is set.
• If this bit is set, the interrupt by RDYINT flag is enabled.
• This bit is cleared by software reset (RST) and can be read and written.
RDYINT
Ready Interrupt Flag
0
(default) The flash macro has not entered the READY state
1
The flash macro has entered the READY state
• This bit is set after a rising edge of the RDY status line of the flash macro.
• This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
• Read-modify-write operations will read 1.
RDY
Flash Macro Ready Status
0
Indicates that a program/erase command is currently executed. Only the reset and suspend commands are
accepted in this state.
1
(default) Indicates that no program/erase command is currently executed. Any command can be written to the Flash.
• This bit shows the RDY status line of the flash macro after a certain response time tBUSY:
In direct access mode, tBUSY is minimum 90 ns after the last write access of a program sequence.
In write sequencer mode, the command sequencer cares about RDY signal. There is no need to poll RDY.
• This bit is read-only.
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CY91460P Series
15.5.2 Data Flash Write Command Sequencer Control Register
This section explaines the Data Flash Sequencer Control register
DFWC : Data Flash Write Command Sequencer Control
Addr:
0x07115
23
22
21
20
19
18
17
16
-
-
-
ERINTE
FININTE
IDLINTE
IDLDMAE
WE
x
x
x
0
0
0
0
0
initial
R/W
R/W
R/W
R/W
R/W
attribute
• Always write 0 to the bits 7:5.
ERINTE
bit
Error Interrupt Enable
0
(default) Disable the interrupt of the error flags
1
Enable the interrupt of the error flag
• If this bit is cleared, no interrupt is generated when a error flag (TOERINT, WERINT and WIERINT) is set.
• If this bit is set, an interrupt is generated when one of the error flags is set.
• This bit is cleared by software reset (RST) and can be read and written.
FININTE
Finish Interrupt Enable
0
(default) Disable the interrupt of the FININT flag
1
Enable the interrupt of the FININT flag
• If this bit is cleared, no interrupt is generated when the FININT flag is set.
• If this bit is set, an interrupt is generated when the FININT flag is set.
• This bit is cleared by software reset (RST) and can be read and written.
IDLINTE
Idle Interrupt Enable
0
(default) Disable the interrupt of the IDLINT flag
1
Enable the interrupt of the IDLINT flag
• If this bit is cleared, no interrupt is generated when the IDLINT flag is set.
• If this bit is set, an interrupt is generated when the IDLINT flag is set.
• This bit is cleared by software reset (RST) and can be read and written.
IDLDMAE
Idle DMA Enable
0
(default) Disable the DMA transfer request
1
Enable the DMA transfer request if the IDLINT flag is set
• If this bit is cleared, no DMA transfer request is generated when the IDLINT flag is set.
• If this bit is set, an DMA transfer request is generated when the IDLINT flag is set.
• This bit is cleared by software reset (RST) and can be read and written.
WE
Write Command Sequencer Enable
0
(default) Disable the Write Command Sequencer, Data Flash operates in direct mode
1
Enable the Write Command Sequencer Mode
• This bit enables the Command Sequencer mode.
• This bit is cleared by software reset (RST) and can be read and written.
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CY91460P Series
15.5.3 Data Flash Write Command Sequencer Status Register
This section explaines the Data Flash Command Sequencer Status register.
DFWS : Data Flash Write Command Sequencer Status
Addr:
0x07116
15
14
13
12
11
10
9
8
bit
PAERF
WIERINT
WERINT
TOERINT
FININT
IDLINT
ST1
ST0
0
0
0
0
0
0
0
0
initial
R/W0
R/W0
R/W0
R/W0
R/W0
R/W0
R
R
attribute
The command sequencer status flags are only set if the command sequencer is enabled (DFWC:WE=1).
PAERF
Prohibited Access Error Flag
0
(default) No prohibited access detected
1
Prohibited access detected
• This flag is set if the CPU tried to read or write into the Data Flash area while the Data Flash is accessed by the Command
Sequencer.
• This flag cannot generate an interrupt.
• This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
• Read-modify-write operations will read 1.
WIERINT
•
•
•
•
•
Write Incomplete Error Flag
0
(default) Command sequencer write operation was completed
1
Command sequencer was disabled while a write operation was ongoing
This flag is set when the command sequencer is disabled (set DFWC:WE=0) in “not idle” state.
If this flag is 0, it is no guarantee that the write operation was successful. Use the FININT flag!
This flag can generate an interrupt if DFWC:ERINTE is set.
This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
Read-modify-write operations will read 1.
WERINT
Write Error Flag
0
(default) No write error detected
1
Write operation returned error
• This flag is set after a write access returned error:
- tried to write to an erase-suspended or write-protected sector,
- tried to write a bit “1” although it is already “0” in flash.
• This flag can generate an interrupt if DFWC:ERINTE is set.
• This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
• Read-modify-write operations will read 1.
TOERINT
•
•
•
•
Timeout Error Flag
0
(default) No timeout error detected
1
A write operation ended with timeout error
This flag is set after a write operation ended in timeout state.
This flag can generate an interrupt if DFWC:ERINTE is set.
This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
Read-modify-write operations will read 1.
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CY91460P Series
FININT
•
•
•
•
•
Command Sequence Finished Flag
0
(default) Write command was not (yet) finished successfully
1
Write command was finished successfully
This flag is set after a command sequencer write operation was finished successfully.
This flag can generate an interrupt if DFWC:FININTE is set.
This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
This bit is also cleared after a DMA transfer (caused by IDLINT) was finished.
Read-modify-write operations will read 1.
IDLINT
Command Sequencer Idle Flag
0
(default) Command sequencer is disabled or not in IDLE state
1
Command sequencer entered the IDLE state
• This flag is set after the command sequencer was enabled (set DFWC:WE=1) or entered the IDLE state after a write operation
was finished.
• This flag can generate an interrupt if DFWC:INTE is set.
• This flag can generate a DMA transfer request if DFWC:IDLDMAE is set.
• This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
• This bit is also cleared after a DMA transfer was finished.
• Read-modify-write operations will read 1.
ST1
ST0
Command Sequencer Status Flags
0
0
(default) Command sequencer is disabled or in IDLE state
0
1
Command sequencer is submitting the write command
1
0
Command sequencer is waiting for Flash program finish
1
1
Command sequencer was disabled in "not idle" state
• Status bit {ST1,ST0} =2’b11 show that the command sequencer was disabled in "not idle" state and direct access to Flash is
not yet permitted (wait for proceeding Flash sequence to finish). Max duration of this wait can be 11 clock cycle after disabling
Command Sequencer.
15.5.4 Data Flash security Control Register 0,1
Please refer to 15.8.5“Data Flash Security Registers”.
Document Number: 002-04619 Rev. *B
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CY91460P Series
15.6 Data Flash Interrupts and DMA Access
If a command sequencer write operation is ongoing, and the CPU writes data again, this second write request is ignored!
Therefore, it is recommended to use the data flash interrupts or DMA, which indicates that the write sequence is finished and
successful.
15.6.1 Data Flash Interrupt Flag Overview
The Data Flash interface has 6 interrupt flags with certain relationship to the 3 output lines for interrupt / DMA request:
Interrupt Flags:
• IDLINT
IDLE flag, indicates that the command sequencer has entered the IDLE state
after a write sequence. This flag is also set just after the command sequencer was
enabled by setting DFWC:WE.
• RDYINT
READY flag, indicates that the flash macro has entered READY state.
• FININT
FINISH flag, indicates that the command sequencer finished a write sequence successfully.
• TOERINT
TIMEOUT Error flag, indicates that a command sequencer write sequence
ended in TIMEOUT error state.
• WERINT
Suspend Sector Write Error flag, indicates that there was a write request to a sector which is
erase suspended or write-protected and not ready for writing.
• WIERINT
Write Incomplete Error flag, indicates that the command sequencer was disabled
(DFWC:WE = 0) while a write sequence was ongoing.
• PAERF
Prohibited Access Error flag, indicates that the CPU tried a read or write access while a
command sequencer write was ongoing. PAERF is a status flag and cannot generate
an interrupt.
The following picture shows the interrupt flags and their enable bits.
INTE
IDLDMAE
DMA Request
RDYINT
IDLINT
IDLINTE
IDLINT
Interrupt Request to CPU
FININTE
FININT
ERINTE
TOERINT
DMA Stop Request
WERINT
WIERINT
The DMA request can be activated by the IDLE flag only and has a separate enable bit (DFWC:IDLDMAE).
DMA Stop request is activated by the error flags.
The CPU interrupt can be activated by all interrupt flags.
Document Number: 002-04619 Rev. *B
Page 94 of 193
CY91460P Series
15.7 Data Flash parallel programming mode
Note: The currently available parallel flash programmers do not support the programming of the data flash. The programmers may be
updated on request. This chapter is for information only.
15.7.1 Flash configuration in parallel Flash programming mode
Parallel Flash programming mode (MD[2:0] = 111):
CY91F467PA
CPU
address
Parallel
programming
mode
address
0050 0000H
External bus area
FFFB F000H
Dummy addresses for auto algorithm
FFFB FF00H
Data Flash Security Sector (256 Byte)
FFFC 0000H
FFFC 4000H
FFFC 8000H
FFFC C000H
Data Flash Sector 0 (16 KB)
Data Flash Sector 1 (16 KB)
Data Flash Sector 2 (16 KB)
Data Flash Sector 3 (16 KB)
FFFD 0000H
00 FF00H
01 0000H
01 4000H
01 8000H
01 C000H
01 FFFFH
External bus area
FFFF FFFFH
Note: The address in parallel programming mode is listed here without 10:0000h offset.
Set the offset by keeping FA[22:20] = 001 the same kind as used for programming of the main flash.
Note: The “Dummy addresses for auto algorithm” are accepted although they are located below the physical addresses of the flash
macro. This address space is needed to apply correct addresses in auto algorithms.
See the example in 15.4.4“Auto Program Algorithms”.
15.7.2 Address mapping from CPU to parallel programming mode
The following tables show the calculation from CPU addresses to data flash macro addresses which are used in parallel programming.
Address mapping CY91F467PA
CPU Address
(addr)
Condition
Flash
sectors
FA (flash address) Calculation
FFFB:FF00h
to
FFFC:FFFFh
-
SAS, SA0, SA1, SA2, SA3
(256 Byte + 64 Kbyte)
FA := addr - 0B:0000h
Note: FA result is without 10:0000h offset for parallel Flash programming .
Set the offset by keeping FA[22:20] = 001 the same kind as used for programming of the main flash.
Document Number: 002-04619 Rev. *B
Page 95 of 193
CY91460P Series
15.7.3 Pin connections in parallel programming mode
Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory’s interface circuit enables
direct control of the Flash memory unit from external pins by directly linking some of the signals to General Purpose Ports. Please
see table below for signal mapping.
In this mode, the Data Flash memory appears to the external pins as a stand-alone unit. This mode is generally set when
writing/erasing using the parallel Flash programmer. In this mode, all operations of the Data Flash memory’s Auto Algorithms are
available.
Correspondence between flash macro and Flash Memory Control Signasl
CY91F467PA external pins
Data Flash
macro pins
FR-CPU mode
—
INITX
—
INITX
104
FRSTX
—
FRSTX
NMIX
105
—
—
MD_2
MD_2
96
Set to ‘1’
—
—
MD_1
MD_1
95
Set to ‘1’
—
—
MD_0
MD_0
94
Set to ‘1’
RDY
FMCS:RDY bit
RY/BYX
P19_0
112
FCLK
FCLK
P19_2
114
WEX
WEX
P18_0
118
OEX
OEX
P19_6
117
CEX
CEX
P19_5
116
RAS
MD_3
98
EQIN
MONCLK
97
LTIN
LTIN
P23_0
68
Set to ‘0’
—
TESTX
P19_4
115
Set to ‘1’
—
RDYI
P19_1
113
Set to ‘0’
FA0
P17_5
125
FA1 to FA8
P06_0 to P06_7
6 to 13
FA9 to FA16
P05_0 to P05_7
14 to 21
FA17 to FA19
P18_1, P18_2, P18_4
119, 120, 121
Set to ‘0’
FA20,FA21
P18_5, P18_6
122, 123
Set to “10”
DQ0 to DQ7
P01_0 to P01_7
24 - 31
RAS
EQIN
FA0
FA1 to FA8
Internal control signal +
control via interface circuit
Internal address bus
FA9 to FA16
—
Internal address bus
—
DI0 to DI7,
DO0 to DO7
Internal data bus
Comment
Clock input
15.7.4 Wait time before data flash access in parallel programming mode
After power-on or the end of a Setting Initialization Request (INITX), the internal data flash security module fetches the security
information. The parallel programmer cannot access the flash until the security vector fetch is finished and has to wait for the following
time:
• Min waittime after VDD5/VDD5R power on :
2.9 ms
• Min waittime after INITX rising :
1.0 ms
Document Number: 002-04619 Rev. *B
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CY91460P Series
15.8 Data Flash Security
15.8.1 Data Flash Security Operation
The data flash security protects the flash against unauthorized read and write access.
• A read access to protected flash will return data=0x00 without notification. There is no flag indicating that the read access was
masked by data flash security module.
• A write access to a write-protected sector will be cancelled.
The flash macro will be put into RESET state, and the security macro will re-fetch the security information.
It may take up to 600μs until the data flash can be accessed again.
In direct access mode, the toggle bits will not change and the bit DFCS:RDY will not go to low state.
In command sequencer mode, the flag DFWS:WERINT is set, indicating that the write operation was not successful.
• The only possible write operation to a protected sector is Chip Erase.
• The data flash security can be disabled by setting the external pin FSC_DISABLE = 1.
• After INIT, please wait 3 ms before accessing the data flash. This time is needed for the security vector fetch as well as internal
signal synchronization. This time is valid also if FSC_DISABLE = 1.
15.8.2 Security Vectors
Two 16-bit Data Flash Security Vectors (DFSV1, DFSV2) are located in the 256 byte security sector, controlling the protection functions
of the Data Flash Security module:
DFSV1[15:0]: 0xFFFB:FF00
DFSV2[15:0]: 0xFFFB:FF02
Vectors
Address
+0
FFFBFF00H
+1
+2
DFSV1[15:0]
+3
DFSV2[15:0]
Block
Data Flash
Security Vectors
15.8.3 Security Vector DFSV1 (bit15 to bit0)
The setting of the Flash Security Vector DFSV1 is responsible for the read and write protection modes.
Explanation of the bits in the Flash Security Vector DFSV1 [15:0]
DFSV1[15:3]
DFSV1[2]
Write
Protection
Level
DFSV1[1]
Write
Protection
DFSV1[0]
Read
Protection
set all to “0”
set to “0”
set to “0”
set to “1”
Read Protection (all device modes, except INTVEC 1 )
set all to “0”
set to “0”
set to “1”
set to “0”
Write Protection (all device modes, without exception)
set all to “0”
set to “0”
set to “1”
set to “1”
Read Protection (all device modes, except INTVEC) and
Write Protection (all device modes, without exception)
set all to “0”
set to “1”
set to “0”
set to “1”
Read Protection (all device modes, except INTVEC)
set all to “0”
set to “1”
set to “1”
set to “0”
Write Protection (all device modes, except INTVEC)
set all to “0”
set to “1”
set to “1”
set to “1”
Read Protection (all device modes, except INTVEC) and
Write Protection (all device modes, except INTVEC)
Flash Security Mode
1. INTVEC mode is the Internal Vector Fetch mode (MD[2:0] = “000”)
Note : If Read Protection is set and the device is not in INTVEC mode and the data flash is written using the Command Sequencer
write access, then the command sequencer will set the error flag because it cannot check that the flash programming was
successful.
Document Number: 002-04619 Rev. *B
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CY91460P Series
15.8.4 Security Vector DFSV2
The setting of the Flash Security Vector DFSV2 bits [15:0] is responsible for the individual write protection of the Data Flash sectors.
It is only evaluated if write protection bit DFSV1 [1] is set.
Explanation of the bits in the Flash Security Vector DFSV2[15:0]
DFSV2 bit
Sector
Enable Write
Protection
Disable Write Protection
DFSV2[0]
SA0
set to “0”
set to “1”
DFSV2[1]
SA1
set to “0”
set to “1”
DFSV2[2]
SA2
set to “0”
set to “1”
Comment
DFSV2[3]
SA3
set to “0”
set to “1”
DFSV2[7:4]
—
—
—
sectors not available
DFSV2[8]
SAS
set to “0”
—
write protection is mandatory!
DFSV2[15:9]
—
—
—
sectors not available
Note : It is mandatory to always set the sector where the Flash Security Vectors DFSV1 and DFSV2 are located to write protected
(here sector SAS). Otherwise it is possible to overwrite the Security Vector to a setting where it is possible to either read out
the Flash content or manipulate data by writing.
See section 15.4“Data Flash access in CPU mode” for an overview about the sector organisation of the Flash Memory.
15.8.5 Data Flash Security Registers
The Data Flash Security module can be used to calculate a CRC over the Data Flash contents. And it is possible to force a security
vector re-fetch by using the following registers.
DFSCR0 : Data Flash Security Control Register 0
Address
07118H
31:24
S[7:0]
CRC[31:24]
23:16
1111 1111
1111 1111
1111 1111
1111 1111
W, R
R
R
R
S[7:0]
15:8
7:0
bit
CRC[23:0]
Initial
value
Attribute
Sequence Activation
0xA5 --> 0x5A
Start of a Flash Security Vector Re-Fetch Sequence (write only)
0xF0 --> 0x0F
Start of a Flash Memory CRC32 Checksum Sequence (write only)
• Continuously writing “A5H”, “5AH” in the DFSCR0[31:24] register will start a Flash Security Vector Re-fetch sequence immediately
after writing “5AH”. There is no time restrictions between “A5H” and “5AH”, but if “A5H” is written followed by the one other than
“5AH”, it must be written “A5H” again. If not, the Re-Fetch sequence cannot be started even if “5AH” is written.
• Continuously writing “F0H”, “0FH” in the DFSCR0[31:24] register will start a CRC32 checksum sequence immediately after writing
“0FH”. There is no time restrictions between “F0H” and “0FH”, but if “F0H” is written followed by the one other than “0FH”, it must
be written “F0H” again. If not, the CRC checksum sequence cannot be started even if “0FH” is written.
• These bits are cleared by an INIT signal from external pin (INITX) or hardware watchdog and can be written only.
Note: The Flash Security Vector Re-Fetch sequence is especially intended to be used after a chip erase command to update the
security status without the need of applying an external INITX reset or after changing the status of the DFSV1 security vector.
Note: The CRC calculation runs on the internal RC clock. It is recommended to switch the RC clock frequency to 2 MHz for shortening
the calculation time. However, the CPU clock (CLKB) must be faster then RC clock, otherwise the CRC calculation may not
start correctly.
Document Number: 002-04619 Rev. *B
Page 98 of 193
CY91460P Series
CRC[31:0]
CRC checksum result
CRC checksum result (read only)
• This register contains the CRC32 checksum result after completion of the CRC32 checksum sequence (the sequence completion
is indicated by DFSCR1.RDY). The CRC checksum is calculated in a standard
CRC32/AAL5 algorithm with the polygon
x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1.
• These bits are set to 0xFFFFFFFF by an INIT signal from external pin (INITX) or hardware watchdog and can be read only.
DFSCR1 : Data Flash Security Control Register 1
Address
0711CH
31:24
SVF_RDY--- --- RDY
23:16
- - - - CSZ[3:0]
15:8
7:0
0xxx xxx1
0000 0000
0000 0000
0000 0000
R/Wx
R, R/W
R/W
R/W
bit
CSA[15:0]
Initial
value
Attribute
• Bit30-25: Reserved bits. The read value is always “X”.
• Bit23-20: Reserved bits. The read value is always “0”.
Bit 31:
SVF_RDY
Security Vector Fetch Ready (flag)
0
The security vector has not been fetched. The data flash is protected against read and write access. Read
operations to data flash return 0x00. Write operations are ignored.
1
The security vector has been done. The data flash can be accessed according to the security settings.
Bit 24:
RDY
CRC Sequence Ready (flag)
0
CRC sequence running or not yet started
1
CRC sequence ready (data in the DFSCR0 register is valid)
Bit 19-16:
CSZ[3:0]
CRC Size Mask
0000
CRC size mask is 256 Byte
0001
CRC size mask is 512 Byte
0010
CRC size mask is 1 KByte
0011
CRC size mask is 2 KByte
0100
CRC size mask is 4 KByte
0101
CRC size mask is 8 KByte
0110
CRC size mask is 16 KByte
0111
CRC size mask is 32 KByte
1000
CRC size mask is 64 KByte
1001 - 1111
Not supported
• CSZ3-0 is used as an OR-mask for the address given by CSA15-0. See address calculation below.
• These bits are cleared by an INIT signal from external pin (INITX) or hardware watchdog.
Document Number: 002-04619 Rev. *B
Page 99 of 193
CY91460P Series
Bit 15-0
CSA[15:0]
CRC Calculation Start Address
0x00FF
CRC start address is 0x0FF00 (sector SAS start)
0x0100
CRC start address is 0x10000 (sector SA0 start)
0x0140
CRC start address is 0x14000 (sector SA1 start)
Notes: The values given above are just examples. The addresses to be written in this register are flash memory addresses like used
in the flash parallel programming mode and not the mapped addresses which are used in CPU mode.
See 15.7.2“Address mapping from CPU to parallel programming mode”.
• The CSA register contains the CRC start address which is aligned to 256 Byte addresses. It is only possible to calculate the
CRC checksum over addresses located in the Data Flash Memory address space. Other addresses are invalid and might lead
to wrong checksums.
Calculation of the CRC Start- and End-addresses
The CSZ3-0 setting is first translated into a mask value:
CSZ3-0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001-1111
MASK
0000_0000_0000_0000
0000_0000_0000_0001
0000_0000_0000_0011
0000_0000_0000_0111
0000_0000_0000_1111
0000_0000_0001_1111
0000_0000_0011_1111
0000_0000_0111_1111
0000_0000_1111_1111
and so on...
• CRC Start address = CSA[15:0] 1.65V
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
VCC18C
VSS5
AVSS5
CS
Document Number: 002-04619 Rev. *B
Page 155 of 193
CY91460P Series
21.3 DC characteristics
Note: In the following tables, “VDD” means VDD35 for pins of ext. bus or VDD5 for other pins.
In the following tables, “VSS” means ground Pins VSS5 for the other pins.
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 125 °C)
Parameter
Symbol
Pin name
Value
Unit
Remarks
Min
Typ
Max
0.8 × VDD
—
VDD + 0.3
V
CMOS hysteresis
input
0.7 × VDD
—
VDD + 0.3
V
4.5 V < VDD < 5.5 V
0.74 × VDD
—
VDD + 0.3
V
3 V < VDD < 4.5 V
—
Port inputs if CMOS
Hysteresis 0.8/0.2
input is selected
—
Port inputs if CMOS
Hysteresis 0.7/0.3
input is selected
—
AUTOMOTIVE
Hysteresis input is
selected
0.8 × VDD
—
VDD + 0.3
V
—
Port inputs if TTL
input is selected
2.0
—
VDD + 0.3
V
VIH
Input “H”
voltage
Condition
VIHR
INITX
—
0.8 × VDD
—
VDD + 0.3
V
INITX input pin
(CMOS Hysteresis)
VIHM
MD_2 to MD_0
—
VDD − 0.3
—
VDD + 0.3
V
Mode input pins
VIHX0S
X0, X0A
—
2.5
—
VDD + 0.3
V
External clock in
“Oscillation mode”
VIHX0F
X0
—
0.8 × VDD
—
VDD + 0.3
V
External clock in “Fast
Clock Input mode”
—
Port inputs if CMOS
Hysteresis 0.8/0.2
input is selected
VSS − 0.3
—
0.2 × VDD
V
—
Port inputs if CMOS
Hysteresis 0.7/0.3
input is selected
VSS − 0.3
—
0.3 × VDD
V
VSS − 0.3
—
0.5 × VDD
V
4.5 V < VDD < 5.5 V
—
Port inputs if
AUTOMOTIVE
Hysteresis input is
selected
VSS − 0.3
—
0.46 × VDD
V
3 V < VDD < 4.5 V
—
Port inputs if TTL
input is selected
VSS − 0.3
—
0.8
V
VIL
Input “L”
voltage
VILR
INITX
—
VSS − 0.3
—
0.2 × VDD
V
INITX input pin
(CMOS Hysteresis)
VILM
MD_2 to MD_0
—
VSS − 0.3
—
VSS + 0.3
V
Mode input pins
VILXDS
X0, X0A
—
VSS − 0.3
—
0.5
V
External clock in
“Oscillation mode”
Document Number: 002-04619 Rev. *B
Page 156 of 193
CY91460P Series
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 125 °C)
Parameter
Input “L” voltage
Symbol
Pin
name
Condition
VILXDF
X0
—
Remarks
Typ
Max
VSS − 0.3
—
0.2 × VDD
V
External clock in
“Fast Clock Input
mode”
VOH2
4.5V ≤ VDD ≤ 5.5V,
Normal IOH = − 2mA
outputs 3.0V ≤ VDD ≤ 4.5V,
IOH = − 1.6mA
VDD − 0.5
—
—
V
Driving strength set
to 2 mA
VOH5
4.5V ≤ VDD ≤ 5.5V,
Normal IOH = − 5mA
outputs 3.0V ≤ VDD ≤ 4.5V,
IOH = − 3mA
VDD − 0.5
—
—
V
Driving strength set
to 5 mA
VOH3
I2C
3.0V ≤ VDD ≤ 5.5V,
outputs IOH = − 3mA
VDD − 0.5
—
—
V
VOL2
4.5V ≤ VDD ≤ 5.5V,
Normal IOL = + 2mA
outputs 3.0V ≤ VDD ≤ 4.5V,
IOL = + 1.6mA
—
—
0.4
V
Driving strength set
to 2 mA
VOL5
4.5V ≤ VDD ≤ 5.5V,
Normal IOL = + 5mA
outputs 3.0V ≤ VDD ≤ 4.5V,
IOL = + 3mA
—
—
0.4
V
Driving strength set
to 5 mA
VOL3
I2C
3.0V ≤ VDD ≤ 5.5V,
outputs IOL = + 3mA
—
—
0.4
V
−1
—
+1
IIL
3.0V ≤ VDD ≤ 5.5V
VSS5 < VI < VDD
Pnn_m TA=25 °C
*1
3.0V ≤ VDD ≤ 5.5V
VSS5 < VI < VDD
TA=125 °C
Output “L” voltage
Analog input
leakage current
IAIN
Pull-up
resistance
RUP
Pull-down
resistance
RDOWN
Input
capacitance
Unit
Min
Output “H” voltage
Input leakage
current
Value
CIN
3.0V ≤ VDD ≤ 5.5V
TA=25 °C
ANn *2
3.0V ≤ VDD ≤ 5.5V
TA=125 °C
μA
−3
—
+3
−1
—
+1
μA
−3
—
+3
μA
Pnn_m*
3, INITX
3.0V ≤ VDD ≤ 3.6V
40
100
160
4.5V ≤ VDD ≤ 5.5V
25
50
100
Pnn_m*
3.0V ≤ VDD ≤ 3.6V
40
100
180
4.5V ≤ VDD ≤ 5.5V
25
50
100
-
5
15
4
All except
VDD5,
VDD5R,
f = 1 MHz
VSS5,
AVCC5,
AVSS5,
AVRH5
Document Number: 002-04619 Rev. *B
kΩ
kΩ
pF
Page 157 of 193
CY91460P Series
Parameter
Symbol
ICC
Pin
name
Condition
CLKB:
100 MHz
CLKP:
50 MHz
VDD5R CLKT:
50 MHz
CLKCAN: 50 MHz
TA = + 25 °C
TA = + 105 °C
TA = + 125 °C
TA = + 25 °C
ICCH
Power
supply
current
CY91-F465PA
VDD5R TA = + 105 °C
TA = + 125 °C
TA = + 25 °C
TA = + 105 °C
TA = + 125 °C
Value
Unit
Min
Typ
Max
-
110
140
mA
-
30
150
μA
-
0.3
2.0
mA
-
0.75
5.0
mA
-
100
500
μA
-
0.5
2.4
mA
-
0.85
5.4
mA
-
50
250
μA
-
0.4
2.2
mA
-
0.8
5.2
mA
Remarks
Code fetch from
Flash
At stop mode *5
RTC :
4 MHz mode *5
RTC :
100 kHz mode *5
ILVE
VDD5
—
—
70
150
μA
External low voltage
detection
ILVI
VDD5R
—
—
50
100
μA
Internal low voltage
detection
-
-
250
500
μA
Main clock
(4 MHz)
-
-
20
40
μA
Sub clock
(32 kHz)
-
130
160
mA
Code fetch from
Flash, Data Flash
enabled
-
30
150
μA
-
0.3
2.0
mA
-
0.75
5.0
mA
-
100
500
μA
-
0.5
2.4
mA
-
0.85
5.4
mA
-
50
250
μA
-
0.4
2.2
mA
-
0.8
5.2
mA
IOSC
ICC
VDD5
CLKB:
100 MHz
50 MHz
VDD5R CLKP:
CLKT:
50 MHz
CLKCAN: 50 MHz
TA = + 25 °C
TA = + 105 °C
TA = + 125 °C
TA = + 25 °C
ICCH
VDD5R TA = + 105 °C
TA = + 125 °C
Power
supply
current
CY91-F467PA *6
TA = + 25 °C
TA = + 105 °C
TA = + 125 °C
At stop mode *7
RTC :
4 MHz mode
RTC :
100 kHz mode
ILVE
VDD5
—
—
70
150
μA
External low voltage
detection
ILVI
VDD5R
—
—
50
100
μA
Internal low voltage
detection
-
-
250
500
μA
Main clock
(4 MHz)
-
-
20
40
μA
Sub clock
(32 kHz)
IOSC
VDD5
1. Pnn_m includes all GPIO pins. Analog (AN) channels and PullUp/PullDown are disabled.
2. ANn includes all pins where AN channels are enabled.
3. Pnn_m includes all GPIO pins. The pull up resistors must be enabled by PPER/PPCR setting and the pins must be in input
direction.
Document Number: 002-04619 Rev. *B
Page 158 of 193
CY91460P Series
4. Pnn_m includes all GPIO pins. The pull down resistors must be enabled by PPER/PPCR setting and the pins must be in input
direction.
5. Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled.
6. CY91F467PA target data
7. Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled.
Document Number: 002-04619 Rev. *B
Page 159 of 193
CY91460P Series
21.4 A/D converter characteristics
Parameter
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 125 °C)
Symbol
Pin name
Resolution
—
Total error
Value
Unit
Min
Typ
Max
—
—
—
10
bit
—
—
−3
—
+3
LSB
Nonlinearity error
—
—
− 2.5
—
+ 2.5
LSB
Differential nonlinearity error
—
—
− 1.9
—
+ 1.9
LSB
AVRL + 0.5
LSB
AVRL + 2.5
LSB
V
Remarks
Zero reading voltage
VOT
ANn
AVRL−1.5
LSB
Full scale reading voltage
VFST
ANn
AVRH−3.5
LSB
AVRH−1.5
LSB
AVRH + 0.5
LSB
V
Compare time
Tcomp
—
0.6
—
16,500
μs
4.5 V < AVCC5
