Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY91F467BA/466BA
CY91F465BB/464BB
FR60 CY91460B Series,
32-bit Microcontroller Datasheet
CY91460B series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control applications which
require high-speed real-time processing, such as consumer devices and on-board vehicle systems. This series uses the FR60 CPU,
which is compatible with the FR family of CPUs.
This series contains the LIN-USART and CAN controllers.
Features
FR60 CPU Core
■
32-bit RISC, load/store architecture, five-stage pipeline
■
16-bit fixed-length instructions (basic instructions)
■
Instruction execution speed: 1 instruction per cycle
■
Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions suitable for
embedded applications
■
Function entry/exit instructions and register data multi-load
store instructions: Instructions supporting C language
■
Register interlock function: Facilitating assembly-language
coding
■
Built-in multiplier with instruction-level support
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
■
Interrupts (save PC/PS): 6 cycles (16 priority levels)
■
Harvard architecture enabling program access and data
access to be performed simultaneously
■
Instructions compatible with the FR family
■
CAN controller (C-CAN): 3 or 6 channels (depending on the
device)
Internal Peripheral Resources
■
General-purpose ports: Maximum 108 ports
■
DMAC (DMA Controller)
Maximum of 5 channels able to operate simultaneously
2 transfer sources (internal peripheral/software)
Activation source can be selected using software
Maximum transfer speed: 1 Mbps
32 transmission/reception message buffers
■
Sound generator: 1 channel
Tone frequency : PWM frequency divide-by-two (reload value
+ 1)
■
Alarm comparator: 1 channel
Monitor external voltage
Generate an interrupt in case of voltage lower/higher than the
defined thresholds (reference voltage)
■
16-bit PPG timer: maximum 16 channels
■
16-bit reload timer: 8 channels
■
16-bit free-run timer: 8 channels (1 channel each for ICU and
OCU)
■
Input capture: maximum 8 channels (operates in conjunction
with the free-run timer)
■
Output compare: maximum 8 channels (operates in
conjunction with the free-run timer)
■
Up/Down counter: 2 channels (2*8-bit or 1*16-bit)
■
Watchdog timer
■
Real-time clock
■
Low-power consumption modes: Sleep/stop mode function
■
Low voltage detection circuit
■
Clock supervisor
Monitors the sub-clock (32 kHz) and the main clock (4 MHz) ,
Addressing mode specifies full 32-bit addresses
(increment/decrement/fixed)
Transfer mode (demand transfer/burst transfer/step
transfer/block transfer)
Transfer data size selectable from 8/16/32-bit
Multi-byte transfer enabled (by software)
DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H)
A/D converter (successive approximation type)
10-bit resolution: maximum 32 channels
Conversion time: minimum 1 μs
■
■
External interrupt inputs: maximum 16 channels
6 channels shared with CAN RX or I2C pins
Bit search module (for REALOS)
Function to search the first bit position of ‘’1’’, ‘’0’’, ‘’changed’’
from the MSB (most significant bit) within one word
■
LIN-USART (full duplex double buffer): 4 or 7 channels,
depending on pin multiplexing
Clock synchronous/asynchronous selectable
Sync-break detection
Internal dedicated baud rate generator
■
I2C bus interface (supports 400 kbps): 2 channels
Master/slave transmission and reception
Arbitration function, clock synchronization function
Cypress Semiconductor Corporation
Document Number: 002-04608 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 24, 2019
CY91460B Series
and switches to a recovery clock (CR oscillator, etc.) when the
oscillations stop.
■
Clock modulator
■
Clock monitor
■
Sub-clock calibration
Corrects the real-time clock timer when operating with the 32
kHz or CR oscillator
■
Main oscillator stabilization timer
Generates an interrupt in sub-clock mode after the stabilization
wait time has elapsed on the 23-bit stabilization wait time
counter
■
Sub-oscillator stabilization timer
Generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization wait time
counter
■
Power supply range 3 V to 5 V (1.8 V internal logic provided by
a step-down voltage converter)
■
Operating temperature range: between − 40°C and + 125°C
Package and Technology
■
Package: QFP-144
■
CMOS 180 nm technology
Document Number: 002-04608 Rev. *C
Page 2 of 127
CY91460B Series
Contents
1.
Product Lineup............................................................. 4
8.4
Registers....................................................................... 36
2.
2.1
2.2
2.3
2.4
Pin Assignment ............................................................ 7
CY91F467BA/466BA with MD_3=1 ............................... 7
CY91F467BA/466BA with MD_3=0 ............................... 8
CY91F465BB/464BB with MD_3=1 ............................... 9
CY91F465BB/464BB with MD_3=0 ............................. 10
3.
3.1
Pin Description........................................................... 11
CY91F467BA/466BA AND CY91F465BB/464BB with
MD_3=1 ....................................................................... 11
CY91F467BA/466BA AND CY91F465BB/464BB with
MD_3=0 ....................................................................... 16
9.
9.1
9.2
9.3
9.4
9.5
9.6
Embedded Program/Data Memory (Flash) ............... 39
Flash Features .............................................................. 39
Operation Modes .......................................................... 39
Flash Access in CPU Mode .......................................... 40
Parallel Flash Programming Mode................................ 47
Poweron Sequence in Parallel Programming Mode ..... 50
Flash Security ............................................................... 50
10.
Memory Space ............................................................ 53
3.2
4.
I/O Circuit Types......................................................... 21
5.
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Handling Devices .......................................................
Preventing Latch-up.....................................................
Handling of unused Input Pins .....................................
Power Supply Pins.......................................................
Crystal Oscillator Circuit...............................................
Notes on Using External Clock ....................................
Mode Pins (MD_x) .......................................................
Notes on Operating in PLL Clock Mode.......................
Pull-up Control .............................................................
27
27
27
27
27
27
28
28
28
6.
6.1
6.2
6.3
6.4
Notes on Debugger....................................................
Execution of the RETI Command ................................
Break Function.............................................................
Operand Break.............................................................
Notes on PS Register ..................................................
29
29
29
29
29
7.
7.1
7.2
7.3
7.4
Block Diagram............................................................
CY91F467BA/466BA with MD_3=1 .............................
CY91F467BA/466BA with MD_3=0 .............................
CY91F465BB/464BB with MD_3=1 .............................
CY91F465BB/464BB with MD_3=0 .............................
30
30
31
32
33
8.
8.1
8.2
8.3
CPU and Control Unit ................................................
Features.......................................................................
Internal Architecture.....................................................
Programming Model.....................................................
34
34
34
35
Document Number: 002-04608 Rev. *C
11. Memory Maps .............................................................. 54
11.1 CY91F467BA, CY91F466BA ........................................ 54
11.2 CY91F465BB, CY91F464BB ........................................ 55
12. I/O Map ......................................................................... 56
12.1 CY91F467BA/466BA, CY91F465BB/464BB ................ 56
12.2 Flash Memory and External Bus Area .......................... 83
13.
Interrupt Vector Table ................................................. 87
14. Recommended Settings ............................................. 91
14.1 PLL and Clock Gear Settings........................................ 91
14.2 Clock Modulator Settings .............................................. 92
15.
15.1
15.2
15.3
15.4
15.5
15.6
15.7
Electrical Characteristics ........................................... 97
Absolute Maximum Ratings .......................................... 97
Recommended Operating Conditions......................... 100
DC Characteristics ...................................................... 101
A/D Converter Characteristics .................................... 104
Alarm Comparator Characteristics.............................. 108
Flash Memory Program/Erase Characteristics ........... 109
AC Characteristics ...................................................... 110
16.
Ordering Information ................................................ 122
17.
Package Dimension .................................................. 123
18.
Revision History........................................................ 124
19. Main Changes in This Edition.................................. 125
Document History ..............................................................126
Page 3 of 127
CY91460B Series
1. Product Lineup
Feature
CY91V460
CY91F465BB/464BB
CY91F467BA/466BA
Max. core frequency (CLKB)
80 MHz
100 MHz
96 MHz
Max. resource frequency (CLKP)
40 MHz
50 MHz
48 MHz
Max. external bus frequency
(CLKT)
40 MHz
50 MHz
48 MHz
Max. CAN frequency (CLKCAN)
20 MHz
50 MHz
48 MHz
Technology
0.35μm
0.18μm
0.18μm
yes
yes
yes
yes (disengageable)
yes
yes
Bit Search
yes
yes
yes
Reset input (INITX)
yes
yes
yes
Hardware standby input (HSTX)
yes
no
no
Clock Modulator
yes
yes
yes
Watchdog
Watchdog (RC osc. based)
Clock Monitor
yes
yes
yes
Low Power Mode
yes
yes
yes
DMA
5 ch
5 ch
5 ch
MMU/MPU
Flash memory
[1]
MPU (16 ch)
Emulation SRAM 32bit read
data
ch)[1]
MPU (8
CY91F465BB: 544 KByte
CY91F464BB: 416 KByte
MPU (8 ch)[1]
CY91F467BA: 1088 KByte
CY91F466BA: 832 KByte
Satellite Flash memory
-
-
-
Flash Protection
-
yes
yes
D-RAM
64 KByte
24 KByte
24 KByte
ID-RAM
64 KByte
16 KByte
16 KByte
Flash-Cache (Instruction cache)
16 KByte
8 KByte
8 KByte
4 KByte fixed
4 KByte
4 KByte
1 ch
1 ch
1 ch
Boot-ROM / BI-ROM
RTC
[2]
8 ch
ICU
8 ch
MD_3=0: 8 ch
MD_3=1: 4 ch[3]
MD_3=0: 8 ch
MD_3=1: 4 ch[3]
OCU
8 ch
MD_3=0: 8 ch
MD_3=1: 4 ch[4]
MD_3=0: 8 ch
MD_3=1: 4 ch[4]
Reload Timer
8 ch
8 ch[5]
8 ch[5]
PPG 16-bit
16 ch
MD_3=0: 16 ch
MD_3=1: 8 ch[6]
MD_3=0: 16 ch
MD_3=1: 8 ch[6]
PFM 16-bit
1 ch
-
-
Sound Generator
1 ch
1 ch
1 ch
4 ch (8-bit) / 2 ch (16-bit)
MD_3=0: 2 ch (8-bit) / 1 ch (16bit)
MD_3=1: NA[7]
MD_3=0: 2 ch (8-bit) / 1 ch (16bit)
MD_3=1: NA[7]
6 ch (128msg)
3 ch (32msg)
6 ch (32msg)
Up/Down Counter (8/16 bit)
C_CAN
Document Number: 002-04608 Rev. *C
8 ch
8 ch[2]
Free Running Timer
Page 4 of 127
CY91460B Series
Feature
CY91V460
LIN-USART
4 ch + 4 ch FIFO + 8 ch
I2C (400K)
4 ch
FR external bus
yes (32bit addr, 32bit data)
CY91F465BB/464BB
FIFO[8]
MD_3=0: 3 ch + 4 ch
MD_3=1: 4 ch FIFO
2 ch
CY91F467BA/466BA
MD_3=0: 3 ch + 4 ch FIFO[8]
MD_3=1: 4 ch FIFO
2 ch
MD_3=0: no
MD_3=0: no
MD_3=1: yes (22bit addr, 16bit data) MD_3=1: yes (22bit addr, 16bit data)
External Interrupts
16 ch
MD_3=0: 16 ch
MD_3=1: 12 ch[9]
MD_3=0: 16 ch
MD_3=1: 12 ch[9]
NMI Interrupts
1 ch
1 ch
1 ch
SMC
6 ch
-
-
LCD controller (40x4)
1 ch
-
-
ADC (10-bit)
32 ch
MD_3=0: 32 ch
MD_3=1: 16 ch
MD_3=0: 32 ch
MD_3=1: 16 ch
Alarm Comparator
2 ch
1 ch
1 ch
Supply Supervisor (low voltage
detection)
yes
yes
yes
Clock Supervisor
yes
yes
yes
Main clock oscillator
4 MHz
4 MHz
4 MHz
Sub clock oscillator
32kHz
32kHz
32kHz
RC oscillator
100kHz
100kHz / 2MHz
100kHz / 2MHz
x 20
x 25
x 25
PLL
DSU4
yes
no
no
EDSU
yes (32 BP)[1]
yes (16 BP)[1]
yes (16 BP)[1]
3V/5V
3V/5V
3V/5V
Supply voltage
Regulator
yes
yes
yes
Power consumption
n.a.
< 1.3 W
< 1.3 W
0..70 C
-40..125 C
-40..125 C
Package
BGA-660
QFP-144
QFP-144
Power on to PLL run
< 20 ms
< 20 ms
< 20 ms
Flash Download Time
n.a.
< 5 sec. typical
< 6 sec. typical
Temperature Range (Ta)
1. MPU channels use EDSU breakpoint registers (shared operation between MPU and EDSU).
2. Free Running Timer: MD3=0 : CH 1 and 0 cannot select external clock (bit7 of TCCS1,0)
MD3=1: CH 3, 2, 1, and 0 cannot select external clock (bit7 of TCCS3,2,1,0)
Document Number: 002-04608 Rev. *C
Page 5 of 127
CY91460B Series
3. ICU: MD3=1: Do not set PFR = 1 & EPFR = 1 (for LIN Synch Field detect).
4. OCU: MD3=1: You cannot use external out-port (but, OCU-function is active.)
5. Reload Timer: MD3=1: CH 7, 6, 5, and 4 cannot select external event
6. PPG: MD3=1: You can use CH15 to 8 of PPG. CH15 to12 cannot select external trigger.
7. Up/Down Counter: MD3=1: You can use Timer-mode only.
8. LIN-USART CH 0 (shared with external bus) can be used for asynchronous mode only.
9. External Interrupts: INT7 to INT4(shared with external bus) can be used for MD3=0 mode only. INT0 (shared with external bus) can be used for
MD3=0 mode only.
Document Number: 002-04608 Rev. *C
Page 6 of 127
VSS5
P10_0/SYSCLK
P09_0/CSX0
P09_1/CSX1
P08_0/WRX0
P08_4/RDX
P08_7/RDY
WRX1
P24_1/INT1
P23_0/RX0/INT8
P23_1/TX0
P23_2/RX1/INT9
P23_3/TX1
P23_4/RX2/INT10
P23_5/TX2
P23_6/RX3/INT11
P23_7/TX3
VDD5
VSS5
P22_0/RX4/INT12
P22_1/TX4
P22_2/RX5/INT13
P22_3/TX5
P22_4/SDA0/INT14
P22_5/SCL0
P22_6/SDA1/INT15
P22_7/SCL1
P16_0/PPG8
P16_1/PPG9
P16_2/PPG10
P16_3/PPG11
P16_4/PPG12/SGA
P16_5/PPG13/SGO
P16_6/PPG14
P16_7/PPG15/ATGX
VDD5
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD35
P07_5/A5
P07_4/A4
P07_3/A3
P07_2/A2
P07_1/A1
P07_0/A0
P15_3/OCU3/TOT3
P15_2/OCU2/TOT2
P15_1/OCU1/TOT1
P15_0/OCU0/TOT0
P14_3/ICU3/TIN3/TTG3/11
P14_2/ICU2/TIN2/TTG2/10
P14_1/ICU1/TIN1/TTG1/9
P14_0/ICU0/TIN0/TTG0/8
P24_3/INT3
P24_2/INT2
VSS5
VDD5
P28_7/AN15
P28_6/AN14
P28_5/AN13
P28_4/AN12
P28_3/AN11
P28_2/AN10
P28_1/AN9
P28_0/AN8
P29_7/AN7
P29_6/AN6
P29_5/AN5
P29_4/AN4
P29_3/AN3
P29_2/AN2
P29_1/AN1
P29_0/AN0
VSS5
CY91460B Series
2. Pin Assignment
2.1
CY91F467BA/466BA with MD_3=1
(TOP VIEW)
VSS5
P07_6/A6
P07_7/A7
P06_0/A8
P06_1/A9
P06_2/A10
P06_3/A11
P06_4/A12
P06_5/A13
P06_6/A14
P06_7/A15
P05_0/A16
P05_1/A17
P05_2/A18
P05_3/A19
P05_4/A20
P05_5/A21
VDD35
VSS5
P01_0/D16
P01_1/D17
P01_2/D18
P01_3/D19
P01_4/D20
P01_5/D21
P01_6/D22
P01_7/D23
P00_0/D24
P00_1/D25
P00_2/D26
P00_3/D27
P00_4/D28
P00_5/D29
P00_6/D30
P00_7/D31
VDD35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Document Number: 002-04608 Rev. *C
LQS144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD5
AVCC5
AVRH5
AVSS5
ALARM_0
P18_6/SCK7/CK
P18_5/SO
T7
P18_4/SIN7
P18_2/SCK6/CK
P18_1/SO
T6
P18_0/SIN6
P19_6/SCK5/CK
P19_5/SO
T5
P19_4/SIN5
P19_2/SCK4/CK
P19_1/SO
T4
P19_0/SIN4
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X0
X1
MD_3
MONCLK
MD_2
MD_1
MD_0
VSS5
Page 7 of 127
VSS5
P20_0/SIN2/AIN0
P20_1/SOT2/BIN0
P20_2/SCK2/ZIN0/CK2
P20_4/SIN3/AIN1
P20_5/SOT3/BIN1
P20_6/SCK3/ZIN1/CK3
P24_0/INT0
P24_1/INT1
P23_0/RX0/INT8
P23_1/TX0
P23_2/RX1/INT9
P23_3/TX1
P23_4/RX2/INT10
P23_5/TX2
P23_6/RX3/INT11
P23_7/TX3
VDD5
VSS5
P22_0/RX4/INT12
P22_1/TX4
P22_2/RX5/INT13
P22_3/TX5
P22_4/SDA0/INT14
P22_5/SCL0
P22_6/SDA1/INT15
P22_7/SCL1
P16_0/PPG8
P16_1/PPG9
P16_2/PPG10
P16_3/PPG11
P16_4/PPG12/SGA
P16_5/PPG13/SGO
P16_6/PPG14
P16_7/PPG15/ATGX
VDD5
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD35
P27_5/AN21
P27_4/AN20
P27_3/AN19
P27_2/AN18
P27_1/AN17
P27_0/AN16
P15_3/OCU3/TOT3
P15_2/OCU2/TOT2
P15_1/OCU1/TOT1
P15_0/OCU0/TOT0
P14_3/ICU3/TIN3/TTG3/11
P14_2/ICU2/TIN2/TTG2/10
P14_1/ICU1/TIN1/TTG1/9
P14_0/ICU0/TIN0/TTG0/8
P24_3/INT3
P24_2/INT2
VSS5
VDD5
P28_7/AN15
P28_6/AN14
P28_5/AN13
P28_4/AN12
P28_3/AN11
P28_2/AN10
P28_1/AN9
P28_0/AN8
P29_7/AN7
P29_6/AN6
P29_5/AN5
P29_4/AN4
P29_3/AN3
P29_2/AN2
P29_1/AN1
P29_0/AN0
VSS5
CY91460B Series
2.2
CY91F467BA/466BA with MD_3=0
(TOP VIEW)
VSS5
P27_6/AN22
P27_7/AN23
P26_0/AN24
P26_1/AN25
P26_2/AN26
P26_3/AN27
P26_4/AN28
P26_5/AN29
P26_6/AN30
P26_7/AN31
P24_4/INT4
P24_5/INT5
P24_6/INT6
P24_7/INT7
P21_0/SIN0
P21_1/SO
T0
VDD35
VSS5
P14_4/ICU4/TIN4/T
TG12/4
P14_5/ICU5/TIN5/T
TG13/5
P14_6/ICU6/TIN6/T
TG14/6
P14_7/ICU7/TIN7/T
TG15/7
P15_4/OCU4/T
OT4
P15_5/OCU5/T
OT5
P15_6/OCU6/T
OT6
P15_7/OCU7/T
OT7
P17_0/PPG0
P17_1/PPG1
P17_2/PPG2
P17_3/PPG3
P17_4/PPG4
P17_5/PPG5
P17_6/PPG6
P17_7/PPG7
VDD35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Document Number: 002-04608 Rev. *C
LQS144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD5
AVCC5
AVRH5
AVSS5
ALARM_0
P18_6/SCK7/CK
P18_5/SO
T7
P18_4/SIN7
P18_2/SCK6/CK
P18_1/SO
T6
P18_0/SIN6
P19_6/SCK5/CK
P19_5/SO
T5
P19_4/SIN5
P19_2/SCK4/CK
P19_1/SO
T4
P19_0/SIN4
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X0
X1
MD_3
MONCLK
MD_2
MD_1
MD_0
VSS5
Page 8 of 127
VSS5
P10_0/SYSCLK
P09_0/CSX0
P09_1/CSX1
P08_0/WRX0
P08_4/RDX
P08_7/RDY
P08_1/WRX1
P24_1/INT1
P23_0/RX0/INT8
P23_1/TX0
P23_2/RX1/INT9
P23_3/TX1
P23_4/RX2/INT10
P23_5/TX2
P23_6/INT11
P23_7
VDD5
VSS5
P22_0/INT12
P22_1
P22_2/INT13
P22_3
P22_4/SDA0/INT14
P22_5/SCL0
P22_6/SDA1/INT15
P22_7/SCL1
P16_0/PPG8
P16_1/PPG9
P16_2/PPG10
P16_3/PPG11
P16_4/PPG12/SGA
P16_5/PPG13/SGO
P16_6/PPG14
P16_7/PPG15/ATGX
VDD5
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD35
P07_5/A5
P07_4/A4
P07_3/A3
P07_2/A2
P07_1/A1
P07_0/A0
P15_3/OCU3/TOT3
P15_2/OCU2/TOT2
P15_1/OCU1/TOT1
P15_0/OCU0/TOT0
P14_3/ICU3/TIN3/TTG3/11
P14_2/ICU2/TIN2/TTG2/10
P14_1/ICU1/TIN1/TTG1/9
P14_0/ICU0/TIN0/TTG0/8
P24_3/INT3
P24_2/INT2
VSS5
VDD5
P28_7/AN15
P28_6/AN14
P28_5/AN13
P28_4/AN12
P28_3/AN11
P28_2/AN10
P28_1/AN9
P28_0/AN8
P29_7/AN7
P29_6/AN6
P29_5/AN5
P29_4/AN4
P29_3/AN3
P29_2/AN2
P29_1/AN1
P29_0/AN0
VSS5
CY91460B Series
2.3
CY91F465BB/464BB with MD_3=1
(TOP VIEW)
VSS5
P07_6/A6
P07_7/A7
P06_0/A8
P06_1/A9
P06_2/A10
P06_3/A11
P06_4/A12
P06_5/A13
P06_6/A14
P06_7/A15
P05_0/A16
P05_1/A17
P05_2/A18
P05_3/A19
P05_4/A20
P05_5/A21
VDD35
VSS5
P01_0/D16
P01_1/D17
P01_2/D18
P01_3/D19
P01_4/D20
P01_5/D21
P01_6/D22
P01_7/D23
P00_0/D24
P00_1/D25
P00_2/D26
P00_3/D27
P00_4/D28
P00_5/D29
P00_6/D30
P00_7/D31
VDD35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Document Number: 002-04608 Rev. *C
LQS144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD5
AVCC5
AVRH5
AVSS5
ALARM_0
P18_6/SCK7/CK
P18_5/SO
T7
P18_4/SIN7
P18_2/SCK6/CK
P18_1/SO
T6
P18_0/SIN6
P19_6/SCK5/CK
P19_5/SO
T5
P19_4/SIN5
P19_2/SCK4/CK
P19_1/SO
T4
P19_0/SIN4
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X0
X1
MD_3
MONCLK
MD_2
MD_1
MD_0
VSS5
Page 9 of 127
VSS5
P20_0/SIN2/AIN0
P20_1/SOT2/BIN0
P20_2/SCK2/ZIN0/CK2
P20_4/SIN3/AIN1
P20_5/SOT3/BIN1
P20_6/SCK3/ZIN1/CK3
P24_0/INT0
P24_1/INT1
P23_0/RX0/INT8
P23_1/TX0
P23_2/RX1/INT9
P23_3/TX1
P23_4/RX2/INT10
P23_5/TX2
P23_6/INT11
P23_7
VDD5
VSS5
P22_0/INT12
P22_1
P22_2/INT13
P22_3
P22_4/SDA0/INT14
P22_5/SCL0
P22_6/SDA1/INT15
P22_7/SCL1
P16_0/PPG8
P16_1/PPG9
P16_2/PPG10
P16_3/PPG11
P16_4/PPG12/SGA
P16_5/PPG13/SGO
P16_6/PPG14
P16_7/PPG15/ATGX
VDD5
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD35
P27_5/AN21
P27_4/AN20
P27_3/AN19
P27_2/AN18
P27_1/AN17
P27_0/AN16
P15_3/OCU3/TOT3
P15_2/OCU2/TOT2
P15_1/OCU1/TOT1
P15_0/OCU0/TOT0
P14_3/ICU3/TIN3/TTG3/11
P14_2/ICU2/TIN2/TTG2/10
P14_1/ICU1/TIN1/TTG1/9
P14_0/ICU0/TIN0/TTG0/8
P24_3/INT3
P24_2/INT2
VSS5
VDD5
P28_7/AN15
P28_6/AN14
P28_5/AN13
P28_4/AN12
P28_3/AN11
P28_2/AN10
P28_1/AN9
P28_0/AN8
P29_7/AN7
P29_6/AN6
P29_5/AN5
P29_4/AN4
P29_3/AN3
P29_2/AN2
P29_1/AN1
P29_0/AN0
VSS5
CY91460B Series
2.4
CY91F465BB/464BB with MD_3=0
(TOP VIEW)
VSS5
P27_6/AN22
P27_7/AN23
P26_0/AN24
P26_1/AN25
P26_2/AN26
P26_3/AN27
P26_4/AN28
P26_5/AN29
P26_6/AN30
P26_7/AN31
P24_4/INT4
P24_5/INT5
P24_6/INT6
P24_7/INT7
P21_0/SIN0
P21_1/SO
T0
VDD35
VSS5
P14_4/ICU4/TIN4/T
TG12/4
P14_5/ICU5/TIN5/T
TG13/5
P14_6/ICU6/TIN6/T
TG14/6
P14_7/ICU7/TIN7/T
TG15/7
P15_4/OCU4/T
OT4
P15_5/OCU5/T
OT5
P15_6/OCU6/T
OT6
P15_7/OCU7/T
OT7
P17_0/PPG0
P17_1/PPG1
P17_2/PPG2
P17_3/PPG3
P17_4/PPG4
P17_5/PPG5
P17_6/PPG6
P17_7/PPG7
VDD35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Document Number: 002-04608 Rev. *C
LQS144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD5
AVCC5
AVRH5
AVSS5
ALARM_0
P18_6/SCK7/CK
P18_5/SO
T7
P18_4/SIN7
P18_2/SCK6/CK
P18_1/SO
T6
P18_0/SIN6
P19_6/SCK5/CK
P19_5/SO
T5
P19_4/SIN5
P19_2/SCK4/CK
P19_1/SO
T4
P19_0/SIN4
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X0
X1
MD_3
MONCLK
MD_2
MD_1
MD_0
VSS5
Page 10 of 127
CY91460B Series
3. Pin Description
3.1
CY91F467BA/466BA AND CY91F465BB/464BB with MD_3=1
Pin no.
2, 3
4 to 11
12 to 17
20 to 27
28 to 35
38
39
40
41
42
43
Pin Name
P07_6, P07_7
A6, A7
P06_0 to P06_7
A8 to A15
P05_0 to P05_5
A16 to A21
P01_0 to P01_7
D16 to D23
P00_0 to P00_7
D24 to D31
P10_0
SYSCLK
P09_0
CSX0
P09_1
CSX1
P08_0
WRX0
P08_4
RDX
P08_7
RDY
I/O
I/O Circuit
Type[1]
I/O
B
I/O
B
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
P08_1
Not on CY91F467BA/CY91F466BA
44
WRX1
P24_1
INT1
I/O
A
RX0
I/O
A
P23_1
TX0
Document Number: 002-04608 Rev. *C
Signal pins of external address bus (bit8 to bit15)
General-purpose input/output port
Signal pins of external address bus (bit16 to bit21)
General-purpose input/output port
Signal pins of external data bus (bit16 to bit23)
General-purpose input/output port
Signal pins of external data bus (bit24 to bit31)
General-purpose input/output port
External bus clock output pin
General-purpose input/output port
Chip select output pins
General-purpose input/output port
Chip select output pins
General-purpose input/output port
External write strobe output pins
General-purpose input/output port
External read strobe output pin
General-purpose input/output port
External ready input pin
External write strobe output pins
General-purpose input/output port
External interrupt input pins
General-purpose input/output port
I/O
A
INT8
47
General-purpose input/output port
External interrupt input, can only be used in general-purpose IO
port mode
P23_0
46
General-purpose input/output port
Signal pins of external address bus (bit6 to bit7)
General-purpose input/output port
INT0
Not on CY91F467BA/CY91F466BA
45
Function
RX input pin of CAN0
External interrupt input pins
I/O
A
General-purpose input/output port
TX output pin of CAN0
Page 11 of 127
CY91460B Series
Pin no.
Pin Name
I/O
I/O Circuit
Type[1]
P23_2
48
RX1
General-purpose input/output port
I/O
A
INT9
49
P23_3
TX1
RX2
I/O
A
I/O
A
P23_5
TX2
INT11
I/O
A
I/O
A
56
A
I/O
A
INT13
A
I/O
A
General-purpose input/output port
I/O
A
I/O
C
P22_4
60
SDA0
P22_5
SCL0
SDA1
I/O
C
P22_7
SCL1
Document Number: 002-04608 Rev. *C
General-purpose input/output port
I2C bus clock input/output pin (open drain)
General-purpose input/output port
I/O
C
INT15
63
I2C bus DATA input/output pin (open drain)
External interrupt input pin
P22_6
62
TX output pin of CAN5
General-purpose input/output port
INT14
61
External interrupt input pin
RX input pin of CAN5
P22_3
CY91F467BA/CY91F466BA: TX5
TX output pin of CAN4
General-purpose input/output port
CY91F467BA/CY91F466BA: RX5
59
External interrupt input pin
General-purpose input/output port
I/O
P22_2
58
TX output pin of CAN3
RX input pin of CAN4
P22_1
CY91F467BA/CY91F466BA: TX4
External interrupt input pin
General-purpose input/output port
CY91F467BA/CY91F466BA: RX4
57
TX output pin of CAN2
General-purpose input/output port
I/O
P22_0
INT12
General-purpose input/output port
RX input pin of CAN3
P23_7
CY91F467BA/CY91F466BA: TX3
RX input pin of CAN2
General-purpose input/output port
CY91F467BA/CY91F466BA: RX3
53
TX output pin of CAN1
External interrupt input pin
P23_6
52
General-purpose input/output port
General-purpose input/output port
INT10
51
RX input pin of CAN1
External interrupt input pins
P23_4
50
Function
I2C bus DATA input/output pin (open drain)
External interrupt input pin
I/O
C
General-purpose input/output port
I2C bus clock input/output pin (open drain)
Page 12 of 127
CY91460B Series
Pin no.
64
65
66
67
Pin Name
P16_0
PPG8
P16_1
PPG9
P16_2
PPG10
P16_3
PPG11
I/O
I/O Circuit
Type[1]
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
P16_4
68
PPG12
P16_6
PPG14
A
PPG15
74 to 76
Output pins of PPG timer
General-purpose input/output port
Output pins of PPG timer
General-purpose input/output port
Output pins of PPG timer
Output pins of PPG timer
Output pins of PPG timer
SG0 output pin of sound generator
I/O
A
P16_7
71
General-purpose input/output port
General-purpose input/output port
I/O
SGO
70
Output pins of PPG timer
SGA output pin of sound generator
P16_5
PPG13
General-purpose input/output port
General-purpose input/output port
SGA
69
Function
General-purpose input/output port
Output pins of PPG timer
General-purpose input/output port
I/O
A
MD_0 to MD_2
I
G
Mode setting pins
77
MONCLK
O
M
Clock monitor pin
78
MD_3
I
H
Mode setting pin
79
X1
—
J1
Clock (oscillation) output
80
X0
—
J1
Clock (oscillation) input
82
X0A
—
J2
Sub clock (oscillation) input
83
X1A
—
J2
Sub clock (oscillation) output
84
INITX
I
H
External reset input pin
85
NMIX
I
H
Non-maskable interrupt input pin
I/O
A
I/O
A
ATGX
92
93
P19_0
SIN4
P19_1
SOT4
A/D converter external trigger input pin
P19_2
94
SCK4
96
P19_4
SIN5
P19_5
SOT5
Document Number: 002-04608 Rev. *C
General-purpose input/output port
Data input pin of USART4
General-purpose input/output port
Data output pin of USART4
General-purpose input/output port
I/O
A
CK4
95
Output pins of PPG timer
Clock input/output pin of USART4
External clock input pin of free-run timer 4
I/O
A
I/O
A
General-purpose input/output port
Data input pin of USART5
General-purpose input/output port
Data output pin of USART5
Page 13 of 127
CY91460B Series
Pin no.
Pin Name
I/O
I/O Circuit
Type[1]
P19_6
97
SCK5
General-purpose input/output port
I/O
A
CK5
98
99
P18_0
SIN6
P18_1
SOT6
SCK6
I/O
A
I/O
A
102
P18_4
SIN7
P18_5
SOT7
I/O
A
SCK7
I/O
A
I/O
A
110 to 117
118 to 125
128
129
ALARM_0
P29_0 to P29_7
AN0 to AN7
P28_0 to P28_7
AN8 to AN15
P24_2
INT2
P24_3
INT3
I/O
A
ICU0 to ICU3
TIN0 to TIN3
O
N
I/O
B
I/O
B
I/O
A
I/O
A
I/O
A
P07_0 to P07_5
A0 to A5
Document Number: 002-04608 Rev. *C
General-purpose input/output port
Data output pin of USART7
Clock input/output pin of USART7
Alarm comparator input pin
General-purpose input/output port
Analog input pins of A/D converter
General-purpose input/output port
Analog input pins of A/D converter
General-purpose input/output port
External interrupt input pin
General-purpose input/output port
External interrupt input pin
Input capture input pins
External trigger input pins of reload timer
General-purpose input/output port
I/O
A
TOT0 to TOT3
138 to 143
Data input pin of USART7
External trigger input pins of PPG timer
P15_0 to P15_3
OCU0 to OCU3
General-purpose input/output port
General-purpose input/output port
TTG0/8 to TTG3/11
134 to 137
Clock input/output pin of USART6
External clock input pin of free-run timer 7
P14_0 to P14_3
130 to 133
General-purpose input/output port
Data output pin of USART6
General-purpose input/output port
CK7
104
Data input pin of USART6
External clock input pin of free-run timer 6
P18_6
103
General-purpose input/output port
General-purpose input/output port
CK6
101
Clock input/output pin of USART5
External clock input pin of free-run timer 5
P18_2
100
Function
Output compare output pins
Reload timer output pins
I/O
B
General-purpose input/output port
Signal pins of external address bus (bit0 to bit5)
Page 14 of 127
CY91460B Series
3.1.1
Power Supply/Ground Pins
Pin no.
Pin Name
I/O
Function
1, 19, 37, 55, 73, 81, 86, 91,
109, 127
VSS5
Ground pins
54, 72, 90, 108, 126
VDD5
Power supply pins
88, 89
VDD5R
Power supply pins for internal regulator
105
AVSS5
107
AVCC5
Power supply pin for A/D converter
106
AVRH5
Reference power supply pin for A/D converter
87
VCC18C
Capacitor connection pin for internal regulator
18, 36, 144
VDD35
Document Number: 002-04608 Rev. *C
Supply
Analog ground pin for A/D converter
Power supply pins for external bus part of I/O ring
Page 15 of 127
CY91460B Series
3.2
CY91F467BA/466BA AND CY91F465BB/464BB with MD_3=0
Pin no.
2 to 3
4 to 11
12 to 15
16
17
Pin Name
P27_6 to P27_7
AN22 to AN23
P26_0 to P26_7
AN24 to AN31
P24_4 to P24_7
INT4 to INT7
P21_0
SIN0
P21_1
SOT0
I/O
I/O Circuit
Type[1]
I/O
B
I/O
B
I/O
A
I/O
A
I/O
A
P14_4 to P14_7
20 to 23
ICU4 to ICU7
TIN4 to TIN7
I/O
A
P17_0 to P17_7
PPG0 to PPG7
I/O
A
SIN2
I/O
A
I/O
A
I/O
A
ZIN0
I/O
A
I/O
A
I/O
A
BIN1
SCK3
ZIN1
CK3
Document Number: 002-04608 Rev. *C
General-purpose input/output ports
Output pins of PPG timer
Data input pin of USART2
Data output pin of USART2
Clock input/output pin of USART2
Up/down counter input pin
Data input pin of USART3
General-purpose input/output ports
Data output pin of USART3
Up/down counter input pin
P20_6
43
Output compare output pins
Up/down counter input pin
P20_5
SOT3
External trigger input pins of reload timer
General-purpose input/output ports
AIN1
42
Input capture input pins
External clock input pin of free-run timer 2
P20_4
SIN3
General-purpose input/output ports
Data output pin of USART0
General-purpose input/output ports
CK2
41
Data input pin of USART0
Up/down counter input pin
P20_2
SCK2
General-purpose input/output ports
General-purpose input/output ports
BIN0
40
External interrupt input pins
Up/down counter input pin
P20_1
SOT2
General-purpose input/output ports
General-purpose input/output ports
AIN0
39
Analog input pins of A/D converter
Reload timer output pins
P20_0
38
General-purpose input/output ports
General-purpose input/output ports
TOT4 to TOT7
28 to 35
Analog input pins of A/D converter
External trigger input pins of PPG timer
P15_4 to P15_7
OCU4 to OCU7
General-purpose input/output ports
General-purpose input/output ports
TTG4/12 to TTG7/15
24 to 27
Function
General-purpose input/output ports
I/O
A
Clock input/output pin of USART3
Up/down counter input pin
External clock input pin of free-run timer 3
Page 16 of 127
CY91460B Series
Pin no.
44
45
Pin Name
P24_0
INT0
P24_1
INT1
I/O
I/O Circuit
Type[1]
I/O
A
I/O
A
P23_0
46
RX0
P23_1
TX0
I/O
A
RX1
I/O
A
I/O
A
P23_3
TX1
51
RX2
I/O
A
I/O
A
TX2
I/O
A
TX output pin of CAN1
RX input pin of CAN2
CY91F467BA/
CY91F466BA: RX3
P23_7
CY91F467BA/
CY91F466BA: TX3
CY91F467BA/
CY91F466BA: RX4
CY91F467BA/
CY91F466BA: TX4
INT13
I/O
A
General-purpose input/output ports
I/O
A
TX output pin of CAN3
General-purpose input/output port
I/O
A
RX input pin of CAN4
External interrupt input pin
General-purpose input/output port
I/O
A
TX output pin of CAN4
General-purpose input/output port
I/O
A
External interrupt input pin
RX input pin of CAN5
P22_3
Document Number: 002-04608 Rev. *C
RX input pin of CAN3
External interrupt input pin
CY91F467BA/
CY91F466BA: RX5
CY91F467BA/
CY91F466BA: TX5
TX output pin of CAN2
General-purpose input/output ports
P22_2
59
General-purpose input/output ports
External interrupt input pin
P22_1
58
RX input pin of CAN1
General-purpose input/output ports
INT12
57
TX output pin of CAN0
INT10
P22_0
56
General-purpose input/output ports
P23_5
INT11
53
RX input pin of CAN0
General-purpose input/output ports
P23_6
52
External interrupt input pin
External interrupt input pin
P23_4
50
General-purpose input/output ports
General-purpose input/output ports
INT9
49
External interrupt input pin
External interrupt input pin
P23_2
48
General-purpose input/output ports
General-purpose input/output ports
INT8
47
Function
General-purpose input/output port
I/O
A
TX output pin of CAN5
Page 17 of 127
CY91460B Series
Pin no.
Pin Name
I/O
I/O Circuit
Type[1]
P22_4
60
61
SDA0
General-purpose input/output ports
I/O
C
INT14
External interrupt input pin
General-purpose input/output ports
SCL0
I/O
C
SDA1
I/O
C
64 to 67
P22_7
SCL1
P16_0 to P16_3
PPG8 to PPG11
69
PPG12
I/O
C
I/O
A
I2C bus clock input/output pin (open drain)
General-purpose input/output ports
Output pins of PPG timer
I/O
A
Output pins of PPG timer
SGA
SGA output pin of sound generator
P16_5
General-purpose input/output ports
PPG13
I/O
A
P16_6
PPG14
PPG15
Output pins of PPG timer
SG0 output pin of sound generator
I/O
A
I/O
A
P16_7
71
General-purpose input/output ports
General-purpose input/output ports
SGO
70
I2C bus DATA input/output pin (open drain)
External interrupt input pin
P16_4
68
I2C bus clock input/output pin (open drain)
General-purpose input/output ports
INT15
63
I2C bus DATA input/output pin (open drain)
P22_5
P22_6
62
Function
General-purpose input/output ports
Output pins of PPG timer
General-purpose input/output ports
ATGX
Output pins of PPG timer
A/D converter external trigger input pin
74 to 76
MD_0 to MD_2
I
G
Mode setting pins
77
MONCLK
O
M
Clock monitor pin
78
MD_3
I
H
Mode setting pins
79
X1
—
J1
Clock (oscillation) output
80
X0
—
J1
Clock (oscillation) input
82
X0A
—
J2
Sub clock (oscillation) input
83
X1A
—
J2
Sub clock (oscillation) output
84
INITX
I
H
External reset input pin
NMIX
I
H
Non-maskable interrupt input pin
I/O
A
I/O
A
85
92
93
P19_0
SIN4
P19_1
SOT4
P19_2
94
SCK4
CK4
Document Number: 002-04608 Rev. *C
General-purpose input/output ports
Data input pin of USART4
General-purpose input/output ports
Data output pin of USART4
General-purpose input/output ports
I/O
A
Clock input/output pin of USART4
External clock input pin of free-run timer 4
Page 18 of 127
CY91460B Series
Pin no.
95
96
Pin Name
P19_4
SIN5
P19_5
SOT5
I/O
I/O Circuit
Type[1]
I/O
A
I/O
A
P19_6
97
SCK5
99
P18_0
SIN6
P18_1
SOT6
I/O
A
SCK6
I/O
A
I/O
A
101
102
SIN7
P18_5
SOT7
I/O
A
SCK7
104
ALARM_0
I/O
A
I/O
A
118 to 125
128
129
P29_0 to P29_7
AN0 to AN7
P28_0 to P28_7
AN8 to AN15
P24_2
INT2
P24_3
INT3
ICU0 to ICU3
TIN0 to TIN3
P27_0 to P27_5
AN16 to AN21
General-purpose input/output ports
Data input pin of USART7
General-purpose input/output ports
Data output pin of USART7
I
N
Alarm comparator input pin
I/O
B
I/O
B
I/O
A
External clock input pin of free-run timer 7
I/O
A
General-purpose input/output ports
Analog input pins of A/D converter
General-purpose input/output ports
Analog input pins of A/D converter
General-purpose input/output ports
External interrupt input pin
General-purpose input/output ports
External interrupt input pin
General-purpose input/output ports
I/O
A
Input capture input pins
External trigger input pins of reload timer
External trigger input pins of PPG timer
General-purpose input/output ports
I/O
A
TOT0 to TOT3
138 to 143
Clock input/output pin of USART6
Clock input/output pin of USART7
P15_0 to P15_3
OCU0 to OCU3
General-purpose input/output ports
Data output pin of USART6
A
TTG0/8 to TTG3/11
134 to 137
Data input pin of USART6
I/O
P14_0 to P14_3
130 to 133
General-purpose input/output ports
General-purpose input/output ports
CK7
110 to 117
Clock input/output pin of USART5
External clock input pin of free-run timer 6
P18_6
103
General-purpose input/output ports
Data output pin of USART5
General-purpose input/output ports
CK6
P18_4
Data input pin of USART5
External clock input pin of free-run timer 5
P18_2
100
General-purpose input/output ports
General-purpose input/output ports
CK5
98
Function
Output compare output pins
Reload timer output pins
I/O
B
General-purpose input/output ports
Analog input pins of A/D converter
1. For information about the I/O circuit type, refer to “I/O Circuit Types”.
Document Number: 002-04608 Rev. *C
Page 19 of 127
CY91460B Series
3.2.1
Power Supply/Ground Pins
Pin no.
Pin Name
I/O
Function
1, 19, 37, 55, 73, 81, 86, 91,
109, 127
VSS5
Ground pins
54, 72, 90, 108, 126
VDD5
Power supply pins
88, 89
VDD5R
Power supply pins for internal regulator
105
AVSS5
107
AVCC5
Power supply pin for A/D converter
106
AVRH5
Reference power supply pin for A/D converter
87
VCC18C
Capacitor connection pin for internal regulator
18, 36, 144
VDD35
Supply
Analog ground pin for A/D converter
Power supply pins for external bus part of I/O ring
1. For information about the I/O circuit type, refer to “I/O Circuit Types”.
Document Number: 002-04608 Rev. *C
Page 20 of 127
CY91460B Series
4. I/O Circuit Types
Type
Circuit
A
Remarks
pull-up control
driver strength
control
data line
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input shutdown
function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
B
pull-up control
driver strength
control
data line
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input shutdown
function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
analog input
Document Number: 002-04608 Rev. *C
Page 21 of 127
CY91460B Series
Type
Circuit
C
Remarks
pull-up control
data line
CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input shutdown
function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
D
pull-up control
data line
CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input shutdown
function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
analog input
Document Number: 002-04608 Rev. *C
Page 22 of 127
CY91460B Series
Type
Circuit
E
Remarks
pull-up control
driver strength
control
data line
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA,
and IOL = 30mA, IOH = -30mA)
2 different CMOS hysteresis inputs with input shutdown
function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
F
pull-up control
driver strength
control
data line
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA,
and IOL = 30mA, IOH = -30mA)
2 different CMOS hysteresis inputs with input shutdown
function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
analog input
Document Number: 002-04608 Rev. *C
Page 23 of 127
CY91460B Series
Type
Circuit
Remarks
G
R
Hysteresis
inputs
H
Mask ROM and EVA device:
CMOS Hysteresis input pin
Flash device:
CMOS input pin
12 V withstand (for MD [2:0])
CMOS Hysteresis input pin
Pull-up resistor value: 50 kΩ approx.
Pull-up
Resistor
R
Hysteresis
inputs
J1
High-speed oscillation circuit:
■ Programmable between oscillation mode (external crystal
or resonator connected to X0/X1 pins) and Fast external
Clock Input (FCI) mode (external clock connected to X0
pin)
X1
R
■ Feedback resistor = approx. 2 * 0.5 MΩ.
Feedback resistor is grounded in the center when the
oscillator is disabled or in FCI mode.
0
Xout
1
FCI
R
X0
FCI or osc disable
J2
Low-speed oscillation circuit:
Xout
X1A
■ Feedback resistor = approx. 2 * 5 MΩ.
Feedback resistor is grounded in the center when the
oscillator is disabled.
R
R
X0A
osc disable
Document Number: 002-04608 Rev. *C
Page 24 of 127
CY91460B Series
Type
Circuit
K
Remarks
pull-up control
driver strength
control
data line
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input shutdown
function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
LCD SEG/COM output
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
LCD SEG/COM
L
pull-up control
driver strength
control
data line
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input shutdown
function
Automotive input with input shutdown function)
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
LCD Voltage input
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
VLCD
Document Number: 002-04608 Rev. *C
Page 25 of 127
CY91460B Series
Type
Circuit
Remarks
M
CMOS level tri-state output
(IOL = 5mA, IOH = -5mA)
tri-state control
data line
N
Analog input pin with protection
analog input line
Document Number: 002-04608 Rev. *C
Page 26 of 127
CY91460B Series
5. Handling Devices
5.1
Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage higher than (VDD5, VDD35 or HVDD5 [1]) or less than (VSS5 or HVSS5 [1]) is applied to
an input or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground pins. If latch-up
occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, be very
careful not to apply voltages in excess of the absolute maximum ratings.
Note: 1. HVDD5, HVSS5 are available only on devices having Stepper Motor Controller.
5.2
Handling of Unused Input Pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down
resistor (2KΩ to 10KΩ) or enable internal pullup or pulldown resisters (PPER/PPCR) before the input enable (PORTEN) is activated
by software. The mode pins MD_x can be connected to VSS5 or VDD5 directly. Unused ALARM input pins can be connected to
AVSS5 directly.
5.3
Power Supply Pins
In CY91460 series, devices including multiple power supply pins and ground pins are designed as follows; pins necessary to be at
the same potential are interconnected internally to prevent malfunctions such as latch-up. All of the power supply pins and ground
pins must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation, to prevent
strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. Furthermore, the power supply
pins and ground pins of the CY91460 series must be connected to the current supply source via a low impedance. It is also
recommended to connect a ceramic capacitor of approximately 0.1 μF as a bypass capacitor between power supply pin and ground
pin near this device. This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 μF (use a X7R ceramic
capacitator) to VCC18C pin for the regulator.
5.4
Crystal Oscillator Circuit
Noise in proximity to the X0 (X0A) and X1 (X1A) pins can cause the device to operate abnormally. Printed circuit boards should be
designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass capacitors connected to ground, are
located near the device and ground.
It is recommended that the printed circuit board layout be designed such that the X0 and X1 pins or X0A and X1A pins are
surrounded by ground plane for the stable operation. Please request the oscillator manufacturer to evaluate the oscillational
characteristics of the crystal and this device.
5.5
Notes on Using External Clock
When using the external clock, it is necessary to simultaneously supply the X0 (X0A) and the X1 (X1A) pins. In the described
combination, X1 (X1A) should be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. At X0 and X1, a
frequency up to 16 MHz is possible.
Figure 1. Example of Using Opposite Phase Supply
X0 (X0A)
X1 (X1A)
Document Number: 002-04608 Rev. *C
Page 27 of 127
CY91460B Series
5.6
Mode Pins (MD_x)
These pins should be connected directly to the power supply or ground pins. To prevent the device from entering test mode
accidentally due to noise, minimize the lengths of the patterns between each mode pin and power supply pin or ground pin on the
printed circuit board as possible and connect them with low impedance.
5.7
Notes on Operating in PLL Clock Mode
If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may continue to operate
at the free-running frequency of the self-oscillating circuit of the PLL. However, this self-running operation cannot be guaranteed.
5.8
Pull-up Control
The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin.
Document Number: 002-04608 Rev. *C
Page 28 of 127
CY91460B Series
6. Notes on Debugger
6.1
Execution of the RETI Command
If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding interrupt handling routine
will be executed repeatedly to the exclusion of other processing. This will prevent the main routine and the handlers for low priority
level interrupts from being executed (For example, if the time-base timer interrupt is enabled, stepping over the RETI instruction will
always break on the first line of the time-base timer interrupt handler).
Disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debugging.
6.2
Break Function
If the range of addresses that cause a hardware break (including event breaks) is set to the address of the current system stack
pointer or to an area that contains the stack pointer, execution will break after each instruction regardless of whether the user
program actually contains data access instructions.
To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the target of the hardware
break (including an event breaks).
6.3
Operand Break
It may cause malfunctions if a stack pointer exists in the area which is set as the DSU operand break. Do not set the access to the
areas containing the address of system stack pointer as a target of data event break.
6.4
Notes on PS Register
As the PS register is processed in advance by some instructions, when the debugger is being used, the exception handling may
result in execution breaking in an interrupt handling routine or the displayed values of the flags in the PS register being updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,the operation before
and after the EIT always proceeds according to specification.
■
The following behavior may occur if any of the following occurs in the instruction immediately after a DIV0U/DIV0S
instruction:
(a) a user interrupt or NMI is accepted;
(b) single-step execution is performed;
(c) execution breaks due to a data event or from the emulator menu.
1. D0 and D1 flags are updated in advance.
2. An EIT handling routine (user interrupt/NMI or emulator) is executed.
3. Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated to the same
values as those in 1.
■
The following behavior occurs when an ORCCR, STILM, MOV Ri,PS instruction is executed to enable a user interrupt or
NMI source while that interrupt is in the active state.
1. The PS register is updated in advance.
2. An EIT handling routine (user interrupt/NMI or emulator) is executed.
3. Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in 1.
Document Number: 002-04608 Rev. *C
Page 29 of 127
CY91460B Series
7. Block Diagram
7.1
CY91F467BA/466BA with MD_3=1
FR60 CPU
core
Flash-Cache
8 Kbytes
I-bus
32
D-RAM
24 Kbytes
Bit search
Flash memory
1088 Kbytes (CY91F467BA)
832 Kbytes (CY91F466BA)
D-bus
32
CAN
6 channels
RX0 to RX5
TX0 to TX5
32 16
bus adapter
ID-RAM
16 Kbytes
External
bus
interface
Bus converter
RDX
WRX0 to WRX1
SYSCLK
RDY
CSX0 to CSX1
A0 to A21
D16 to D31
DMAC
5 channels
R-bus
16
Clock modulator
Clock supervisor
Clock control
TTG0/8 to TTG3/11
PPG8 to PPG15
TIN0 to TIN3
TOT0 to TOT3
CK4 to CK7
ICU0 to ICU3
PPG timer
8 channels
Reload timer
8 channels
Free-run timer
8 channels
Input capture
4 channels
Clock monitor
MONCLK
Interrupt controller
External interrupt
12 channels
INT0 to INT3,
INT8 to to INT15
LIN-USART
4 channels
SIN4 to SIN7
SOT4 to SOT7
SCK4 to SCK7
I2C
2 channels
SDA0 to SDA1
SCL0 to SCL1
Real time clock
OCU0 to OCU3
ALARM_0
Document Number: 002-04608 Rev. *C
Output compare
4 channels
Alarm comparator
1 channel
A/D converter
16 channels
Sound generator
1 channel
AN0 to AN15
ATGX
SGA
SG0
Page 30 of 127
CY91460B Series
7.2
CY91F467BA/466BA with MD_3=0
FR60 CPU
core
Flash-Cache
8 Kbytes
I-bus
32
D-RAM
24 Kbytes
Bit search
Flash memory
1088 Kbytes (CY91F467BA)
832 Kbytes (CY91F466BA)
D-bus
32
CAN
6 channels
RX0 to RX5
TX0 to TX5
32 16
bus adapter
ID-RAM
16 Kbytes
Bus converter
DMAC
5 channels
R-bus
16
Clock modulator
Clock supervisor
Clock monitor
Clock control
Interrupt controller
TTG0/8 to TTG7/15
PPG0 to PPG15
PPG timer
16 channels
TIN0 to TIN7
TOT0 to TOT7
Reload timer
8 channels
CK2 to CK7
ICU0 to ICU7
Free-run timer
8 channels
Input capture
8 channels
External interrupt
16 channels
MONCLK
INT0 to INT15
LIN-USART
7 channels
SIN2 to SIN7,SIN0
SOT2 to SOT7,SOT0
SCK2 to SCK7
I2C
2 channels
SDA0 to SDA1
SCL0 to SCL1
Real time clock
OCU0 to OCU7
AIN0 to AIN1
BIN0 to BIN1
ZIN0 to ZIN1
ALARM_0
Document Number: 002-04608 Rev. *C
Output compare
8 channels
Up/down counter
2 channels
Alarm comparator
1 channel
A/D converter
32 channels
Sound generator
1 channel
AN0 to AN31
ATGX
SGA
SG0
Page 31 of 127
CY91460B Series
7.3
CY91F465BB/464BB with MD_3=1
FR60 CPU
core
Flash-Cache
8 Kbytes
I-bus
32
D-RAM
24 Kbytes
Bit search
Flash memory
544 Kbytes (CY91F465BB)
416 Kbytes (CY91F464BB)
D-bus
32
CAN
3 channels
RX0 to RX2
TX0 to TX2
32 16
bus adapter
ID-RAM
16 Kbytes
External
bus
interface
Bus converter
RDX
WRX0 to WRX1
SYSCLK
RDY
CSX0 to CSX1
A0 to A21
D16 to D31
DMAC
5 channels
R-bus
16
Clock modulator
TTG0/8 to TTG3/11
PPG8 to PPG15
TIN0 to TIN3
TOT0 to TOT3
CK4 to CK7
ICU0 to ICU3
Clock supervisor
Clock monitor
Clock control
Interrupt controller
PPG timer
8 channels
Reload timer
8 channels
Free-run timer
8 channels
Input capture
4 channels
External interrupt
12 channels
MONCLK
INT0 to INT3,
INT8 to to INT15
LIN-USART
4 channels
SIN4 to SIN7
SOT4 to SOT7
SCK4 to SCK7
I2C
2 channels
SDA0 to SDA1
SCL0 to SCL1
Real time clock
OCU0 to OCU3
ALARM_0
Document Number: 002-04608 Rev. *C
Output compare
4 channels
Alarm comparator
1 channel
A/D converter
16 channels
Sound generator
1 channel
AN0 to AN15
ATGX
SGA
SG0
Page 32 of 127
CY91460B Series
7.4
CY91F465BB/464BB with MD_3=0
FR60 CPU
core
Flash-Cache
8 Kbytes
I-bus
32
D-RAM
16Kbytes
Bit search
Flash memory
D-bus
32
416 Kbytes (CY91F464HB)
CAN
1 channel
RX0
TX0
32 16
bus adapter
ID-RAM
16 Kbytes
Bus converter
DMAC
5 channels
R-bus
16
Clock modulator
Clock supervisor
Clock monitor
Clock control
Interrupt controller
TTG0/8 to TTG7/15
PPG0 to PPG15
PPG timer
16 channels
TIN0 to TIN7
TOT0 to TOT7
Reload timer
8 channels
Free-run timer
8 channels
CK2 to CK7
Input capture
8 channels
ICU0 to ICU7
External interrupt
16 channels
MONCLK
INT0 to INT15
LIN-USART
7 channels
SIN2 to SIN7,SIN0
SOT2 to SOT7,SOT0
SCK2 to SCK7
I2C
2 channels
SDA0 to SDA1
SCL0 to SCL1
Real time clock
Output compare
8 channels
OCU0 to OCU7
AIN0 to AIN1
BIN0 to BIN1
ZIN0 to ZIN1
ALARM_0
Up/down counter
2 channels
Alarm comparator
1 channel
Document Number: 002-04608 Rev. *C
A/D converter
32 channels
Sound generator
1 channel
AN0 to AN31
ATGX
SGA
SG0
Page 33 of 127
CY91460B Series
8. CPU and Control Unit
The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced instructions for
embedded applications.
8.1
Features
■
Adoption of RISC architecture
Basic instruction: 1 instruction per cycle
■
General-purpose registers: 32-bit × 16 registers
■
4 Gbytes linear memory space
■
Multiplier installed
32-bit × 32-bit multiplication: 5 cycles
16-bit × 16-bit multiplication: 3 cycles
■
Enhanced interrupt processing function
Quick response speed (6 cycles)
Multiple-interrupt support
Level mask function (16 levels)
■
Enhanced instructions for I/O operation
Memory-to-memory transfer instruction
Bit processing instruction
Basic instruction word length: 16 bits
■
Low-power consumption
Sleep mode/stop mode
8.2
Internal Architecture
■
The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent of each other.
■
A 32-bit ↔ 16-bit buffer is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and peripheral resources.
■
A Harvard ↔ Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between the CPU and the
bus controller.
Document Number: 002-04608 Rev. *C
Page 34 of 127
CY91460B Series
8.3
Programming Model
8.3.1
Basic Programming Model
32 bits
Initial value
R0
XXXX XXXXH
R1
...
General-purpose registers
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Program counter
PC
Program status
RS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiply & divide registers
MDH
ILM
SCR
CCR
MDL
Document Number: 002-04608 Rev. *C
Page 35 of 127
CY91460B Series
8.4
Registers
8.4.1
General-Purpose Register
32 bits
Initial value
R0
XXXX XXXXH
R1
...
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation operations and as
pointers for memory access.
Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular applications.
R13 : Virtual accumulator
R14 : Frame pointer
R15 : Stack pointer
Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value).
8.4.2
PS (Program Status)
This register holds the program status, and is divided into three parts, ILM, SCR, and CCR.
All undefined bits (-) in the diagram are reserved bits. The read values are always “0”. Write access to these bits is invalid.
Bit position → bit 31
bit 20
bit 16
ILM
Document Number: 002-04608 Rev. *C
bit 10 bit 8 bit 7
SCR
bit 0
CCR
Page 36 of 127
CY91460B Series
8.4.3
CCR (Condition Code Register)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SV
S
I
N
Z
V
C
Initial value
- 000XXXXB
SV: Supervisor flag
S: Stack flag
I: Interrupt enable flag
N: Negative enable flag
Z: Zero flag
V: Overflow flag
C: Carry flag
8.4.4
SCR (System Condition Register)
bit 10 bit 9
D1
D0
bit 8
Initial value
T
XX0B
Flag for step division (D1, D0)
This flag stores interim data during execution of step division.
Step trace trap flag (T)
This flag indicates whether the step trace trap is enabled or disabled.
The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution of user programs.
8.4.5
ILM (Interrupt Level Mask Register)
bit 20 bit 19 bit 18 bit 17 bit 16
ILM4 ILM3 ILM2 ILM1 ILM0
Initial value
01111B
This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking.
The register is initialized to value “01111B” at reset.
8.4.6
PC (Program Counter)
bit 31
bit 0
Initial value
XXXXXXXXH
The program counter indicates the address of the instruction that is being executed.
The initial value at reset is undefined.
Document Number: 002-04608 Rev. *C
Page 37 of 127
CY91460B Series
8.4.7
TBR (Table Base Register)
bit 0 Initial value
bit 31
000FFC00H
The table base register stores the starting address of the vector table used in EIT processing.
The initial value at reset is 000FFC00H.
8.4.8
RP (Return Pointer)
bit 31
bit 0
Initial value
XXXXXXXXH
The return pointer stores the address for return from subroutines.
During execution of a CALL instruction, the PC value is transferred to this RP register.
During execution of a RET instruction, the contents of the RP register are transferred to PC.
The initial value at reset is undefined.
8.4.9
USP (User Stack Pointer)
bit 31
bit 0
Initial value
XXXXXXXXH
The user stack pointer, when the S flag is “1”, this register functions as the R15 register.
The USP register can also be explicitly specified.
The initial value at reset is undefined.
■
■
This register cannot be used with RETI instructions.
8.4.10 Multiply & Divide Registers
bit 31
bit 0
MDH
MDL
These registers are for multiplication and division, and are each 32 bits in length.
The initial value at reset is undefined.
Document Number: 002-04608 Rev. *C
Page 38 of 127
CY91460B Series
9. Embedded Program/Data Memory (Flash)
9.1
Flash Features
■
CY91F467BA: 1088 Kbytes (16 × 64 Kbytes + 8 × 8 Kbytes = 8.5 Mbits)
■
CY91F466BA: 832 Kbytes (12 × 64 Kbytes + 8 × 8 Kbytes = 6.5 Mbits)
■
CY91F465BB: 544 Kbytes (8 × 64 Kbytes + 4 × 8 Kbytes = 4.25 Mbits)
■
CY91F464BB: 416 Kbytes (6 × 64 Kbytes + 4 × 8 Kbytes = 3.25 Mbits)
■
Programmable wait states for read/write access
■
Flash and Boot security with security vector at 0x0014:8000 - 0x0014:800F
■
Boot security
■
Basic specification: Same as MBM29LV400TC (except size and part of sector configuration)
9.2
Operation Modes
9.2.1
64-bit CPU Mode (Available on CY91F467BA/466BA Only) :
■
CPU reads and executes programs in word (32-bit) length units.
■
Flash writing is not possible.
■
Actual Flash Memory access is performed in d-word (64-bit) length units.
9.2.2
32-bit CPU Mode:
■
CPU reads and executes programs in word (32-bit) length units.
■
Actual Flash Memory access is performed in word (32-bit) length units.
9.2.3
16-bit CPU Mode:
■
CPU reads and writes in half-word (16-bit) length units.
■
Program execution from the Flash is not possible.
■
Actual Flash Memory access is performed in word (16-bit) length units.
9.2.4
Flash Memory Mode (External Access to Flash Memory Enabled)
Note: The operation mode of the flash memory can be selected using a Boot-ROM function. The function start address is 0xBF60.
The parameter description is given in the Hardware Manual in chapter 54.6 "Flash Access Mode Switching".
Document Number: 002-04608 Rev. *C
Page 39 of 127
CY91460B Series
9.3
Flash Access in CPU Mode
9.3.1
Flash Configuration
9.3.1.1
Flash Memory Map CY91F467BA
Address
0014:FFFFh
0014:C000h
SA6 (8KB)
SA7 (8KB)
0014:BFFFh
0014:8000h
SA4 (8KB)
SA5 (8KB)
0014:7FFFh
0014:4000h
SA2 (8KB)
SA3 (8KB)
0014:3FFFh
0014:0000h
SA0 (8KB)
SA1 (8KB)
0013:FFFFh
0012:0000h
SA22 (64KB)
SA23 (64KB)
0011:FFFFh
0010:0000h
SA20 (64KB)
SA21 (64KB)
000F:FFFFh
000E:0000h
SA18 (64KB)
SA19 (64KB)
ROMS5
000D:FFFFh
000C:0000h
SA16 (64KB)
SA17 (64KB)
ROMS4
000B:FFFFh
000A:0000h
SA14 (64KB)
SA15 (64KB)
ROMS3
0009:FFFFh
0008:0000h
SA12 (64KB)
SA13 (64KB)
ROMS2
0007:FFFFh
0006:0000h
SA10 (64KB)
SA11 (64KB)
ROMS1
0005:FFFFh
0004:0000h
SA8 (64KB)
SA9 (64KB)
ROMS0
ROMS7
ROMS6
addr+0
16bit read/write
addr+1
addr+2
dat[31:16]
32bit read/write
64bit read
Document Number: 002-04608 Rev. *C
addr+3
addr+4
dat[15:0]
addr+5
addr+6
dat[31:16]
dat[31:0]
addr+7
dat[15:0]
dat[31:0]
dat[63:0]
Page 40 of 127
CY91460B Series
9.3.1.2
Flash Memory Map CY91F466BA
Addr
0014:FFFFh
0014:C000h
SA6 (8KB)
SA7 (8KB)
0014:BFFFh
0014:8000h
SA4 (8KB)
SA5 (8KB)
0014:7FFFh
0014:4000h
SA2 (8KB)
SA3 (8KB)
0014:3FFFh
0014:0000h
SA0 (8KB)
SA1 (8KB)
0013:FFFFh
0012:0000h
SA22 (64KB)
SA23 (64KB)
0011:FFFFh
0010:0000h
SA20 (64KB)
SA21 (64KB)
000F:FFFFh
000E:0000h
SA18 (64KB)
SA19 (64KB)
ROMS5
000D:FFFFh
000C:0000h
SA16 (64KB)
SA17 (64KB)
ROMS4
000B:FFFFh
000A:0000h
SA14 (64KB)
SA15 (64KB)
ROMS3
0009:FFFFh
0008:0000h
SA12 (64KB)
SA13 (64KB)
ROMS2
0007:FFFFh
0006:0000h
SA10 (64KB)
SA11 (64KB)
ROMS1
0005:FFFFh
0004:0000h
SA8 (64KB)
SA9 (64KB)
ROMS0
ROMS7
ROMS6
addr+0
16bit read/write
addr+1
addr+2
dat[31:16]
32bit read
addr+4
addr+5
addr+6
dat[31:16]
dat[31:0]
addr+7
dat[15:0]
dat[31:0]
dat[63:0]
64bit read
Legend
addr+3
dat[15:0]
Memory not available in this area
Document Number: 002-04608 Rev. *C
Memory available in this area
Page 41 of 127
CY91460B Series
9.3.1.3
Flash Memory Map CY91F465BB
Addr
0014:FFFFh
0014:C000h
SA6 (8KB)
SA7 (8KB)
0014:BFFFh
0014:8000h
SA4 (8KB)
SA5 (8KB)
0014:7FFFh
0014:4000h
SA2 (8KB)
SA3 (8KB)
0014:3FFFh
0014:0000h
SA0 (8KB)
SA1 (8KB)
0013:FFFFh
0012:0000h
SA22 (64KB)
SA23 (64KB)
ROMS7
ROMS6
0011:FFFFh
0010:0000h
SA20 (64KB)
SA21 (64KB)
000F:FFFFh
000E:0000h
SA18 (64KB)
SA19 (64KB)
ROMS5
000D:FFFFh
000C:0000h
SA16 (64KB)
SA17 (64KB)
ROMS4
000B:FFFFh
000A:0000h
SA14 (64KB)
SA15 (64KB)
ROMS3
0009:FFFFh
0008:0000h
SA12 (64KB)
SA13 (64KB)
ROMS2
0007:FFFFh
0006:0000h
SA10 (64KB)
SA11 (64KB)
ROMS1
0005:FFFFh
0004:0000h
SA8 (64KB)
SA9 (64KB)
ROMS0
addr+0
16bit read/write
addr+1
addr+2
dat[31:16]
addr+3
dat[15:0]
addr+4
addr+5
addr+6
dat[31:16]
dat[15:0]
32bit read
dat[31:0]
dat[31:0]
Legend
Memory not available in this area
Memory available in this area
Document Number: 002-04608 Rev. *C
addr+7
Page 42 of 127
CY91460B Series
9.3.1.4
Flash Memory Map CY91F464BB
Address
0014:FFFFh
0014:C000h
SA6 (8KB)
SA7 (8KB)
0014:BFFFh
0014:8000h
SA4 (8KB)
SA5 (8KB)
0014:7FFFh
0014:4000h
SA2 (8KB)
SA3 (8KB)
0014:3FFFh
0014:0000h
SA0 (8KB)
SA1 (8KB)
0013:FFFFh
0012:0000h
SA22 (64KB)
SA23 (64KB)
0011:FFFFh
0010:0000h
SA20 (64KB)
SA21 (64KB)
000F:FFFFh
000E:0000h
SA18 (64KB)
SA19 (64KB)
ROMS5
000D:FFFFh
000C:0000h
SA16 (64KB)
SA17 (64KB)
ROMS4
000B:FFFFh
000A:0000h
SA14 (64KB)
SA15 (64KB)
ROMS3
0009:FFFFh
0008:0000h
SA12 (64KB)
SA13 (64KB)
ROMS2
0007:FFFFh
0006:0000h
SA10 (64KB)
SA11 (64KB)
ROMS1
0005:FFFFh
0004:0000h
SA8 (64KB)
SA9 (64KB)
ROMS0
ROMS7
ROMS6
addr+0
16bit read/write
addr+1
addr+2
dat[31:16]
addr+3
dat[15:0]
addr+4
addr+5
addr+6
dat[31:16]
dat[15:0]
32bit read
dat[31:0]
dat[31:0]
Legend
Memory not available in this area
Memory available in this area
Document Number: 002-04608 Rev. *C
addr+7
Page 43 of 127
CY91460B Series
9.3.2
Flash Access Timing Settings in CPU Mode
The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or maximum clock
modulation) for Flash read and write access.
9.3.2.1
Flash Read Timing Settings (Synchronous Read)
Core Clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
to 24 MHz
0
0
0
-
1
to 48 MHz
0
0
1
-
2
to 96 MHz
1
1
3
-
4
to 100 MHz
1
1
3
-
4
not available on CY91F467BA/CY91F466BA
Remark
9.3.2.2
Remark
Flash Write Timing Settings (Synchronous Write)
Core Clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
to 16 MHz
0
-
-
0
3
to 32 MHz
0
-
-
0
4
to 48 MHz
0
-
-
0
5
to 64 MHz
1
-
-
0
6
to 96 MHz
1
-
-
0
7
to 100 MHz
1
-
-
0
7
Document Number: 002-04608 Rev. *C
not available on CY91F467BA/CY91F466BA
Page 44 of 127
CY91460B Series
9.3.3
Address Mapping from CPU to Parallel Programming Mode
The following tables show the calculation from CPU addresses to flash macro addresses which are used in parallel programming.
9.3.3.1
Address Mapping CY91F467BA
CPU Address
(addr)
Condition
Flash
Sectors
FA (Flash Address) Calculation
14:0000h
to
14:FFFFh
addr[2]==0
SA0, SA2, SA4, SA6
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 +
addr%4 - 05:0000h
14:0000h
to
14:FFFFh
addr[2]==1
SA1, SA3, SA5, SA7
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2 + 00:2000h (addr/2)%4 + addr%4 - 05:0000h
04:0000h
to
13:FFFFh
addr[2]==0
SA8, SA10, SA12, SA14, SA16,
SA18, SA20, SA22
(64 Kbyte)
FA := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 +
addr%4 + 0C:0000h
04:0000h
to
13:FFFFh
addr[2]==1
SA9, SA11, SA13, SA15, SA17,
SA19, SA21, SA23
(64 Kbyte)
FA := addr - addr%02:0000h + (addr%02:0000h)/2 + 01:0000h (addr/2)%4 + addr%4 + 0C:0000h
Note: FA result is without 20:0000h offset for parallel Flash programming . Set offset by keeping FA[21] = 1 as described in section
“Parallel Flash programming mode”.
9.3.3.2
Address Mapping CY91F466BA
CPU Address
(addr)
Condition
Flash
Sectors
FA (Flash Address) Calculation
14:0000h
to
14:FFFFh
addr[2]==0
SA0, SA2, SA4, SA6
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 +
addr%4 - 05:0000h
14:0000h
to
14:FFFFh
addr[2]==1
SA1, SA3, SA5, SA7
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2 + 00:2000h - (addr/2)%4 + addr%4 - 05:0000h
04:0000h
to
0F:FFFFh
addr[2]==0
SA8, SA10, SA12, SA14, SA16,
SA18
(64 Kbyte)
FA := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 + 0C:0000h
04:0000h
to
0F:FFFFh
addr[2]==1
SA9, SA11, SA13, SA15, SA17,
SA19
(64 Kbyte)
FA := addr - addr%02:0000h + (addr%02:0000h)/2 + 01:0000h - (addr/2)%4 + addr%4 + 0C:0000h
Note: FA result is without 20:0000h offset for parallel Flash programming . Set offset by keeping FA[21] = 1 as described in section
“Parallel Flash programming mode”.
Document Number: 002-04608 Rev. *C
Page 45 of 127
CY91460B Series
9.3.3.3
Address Mapping CY91F465BB
CPU Address
(addr)
Condition
Flash
Sectors
FA (Flash Address) Calculation
14:8000h
to
14:FFFFh
addr[2]==0
SA4, SA6
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4
+ addr%4 - 0D:0000h
14:8000h
to
14:FFFFh
addr[2]==1
SA5, SA7
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2 + 00:2000h (addr/2)%4 + addr%4 - 0D:0000h
08:0000h
to
0F:FFFFh
addr[2]==0
SA12, SA14, SA16, SA18
(64 Kbyte)
FA := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 +
addr%4
08:0000h
to
0F:FFFFh
addr[2]==1
SA13, SA15, SA17, SA19
(64 Kbyte)
FA := addr - addr%02:0000h + (addr%02:0000h)/2 + 01:0000h (addr/2)%4 + addr%4
Note: FA result is without 20:0000h offset for parallel Flash programming . Set offset by keeping FA[21] = 1 as described in section
“Parallel Flash programming mode”.
9.3.3.4
Address Mapping CY91F464BB
CPU Address
(addr)
Condition
Flash
Sectors
FA (Flash Address) Calculation
14:8000h
to
14:FFFFh
addr[2]==0
SA4, SA6
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4
+ addr%4 - 0D:0000h
14:8000h
to
14:FFFFh
addr[2]==1
SA5, SA7
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2 + 00:2000h (addr/2)%4 + addr%4 - 0D:0000h
0A:0000h
to
0F:FFFFh
addr[2]==0
SA14, SA16, SA18
(64 Kbyte)
FA := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 +
addr%4
0A:0000h
to
0F:FFFFh
addr[2]==1
SA15, SA17, SA19
(64 Kbyte)
FA := addr - addr%02:0000h + (addr%02:0000h)/2 + 01:0000h (addr/2)%4 + addr%4
Note: FA result is without 20:0000h offset for parallel Flash programming . Set offset by keeping FA[21] = 1 as described in section
“Parallel Flash programming mode”.
Document Number: 002-04608 Rev. *C
Page 46 of 127
CY91460B Series
9.4
Parallel Flash Programming Mode
9.4.1
Flash Configuration in Parallel Flash Programming Mode
9.4.1.1
Parallel Flash Programming Mode (MD[2:0] = 111):
CY91F466BA
CY91F467BA
FA[21:0]
FA[21:0]
003F:FFFFh
003F:0000h
SA23 (64KB)
SA23 (64KB)
003E:FFFFh
003E:0000h
SA22 (64KB)
SA22 (64KB)
003D:FFFFh
003D:0000h
SA21 (64KB)
SA21 (64KB)
003C:FFFFh
003C:0000h
SA20 (64KB)
SA20 (64KB)
003B:FFFFh
003B:0000h
SA19 (64KB)
003B:FFFFh
003B:0000h
SA19 (64KB)
003A:FFFFh
003A:0000h
SA18 (64KB)
003A:FFFFh
003A:0000h
SA18 (64KB)
0039:FFFFh
0039:0000h
SA17 (64KB)
0039:FFFFh
0039:0000h
SA17 (64KB)
0038:FFFFh
0038:0000h
SA16 (64KB)
0038:FFFFh
0038:0000h
SA16 (64KB)
0037:FFFFh
0037:0000h
SA15 (64KB)
0037:FFFFh
0037:0000h
SA15 (64KB)
0036:FFFFh
0036:0000h
SA14 (64KB)
0036:FFFFh
0036:0000h
SA14 (64KB)
0035:FFFFh
0035:0000h
SA13 (64KB)
0035:FFFFh
0035:0000h
SA13 (64KB)
0034:FFFFh
0034:0000h
SA12 (64KB)
0034:FFFFh
0034:0000h
SA12 (64KB)
0033:FFFFh
0033:0000h
SA11 (64KB)
0033:FFFFh
0033:0000h
SA11 (64KB)
0032:FFFFh
0032:0000h
SA10 (64KB)
0032:FFFFh
0032:0000h
SA10 (64KB)
0031:FFFFh
0031:0000h
SA9 (64KB)
0031:FFFFh
0031:0000h
SA9 (64KB)
0030:FFFFh
0030:0000h
SA8 (64KB)
0030:FFFFh
0030:0000h
SA8 (64KB)
002F:FFFFh
002F:E000h
SA7 (8KB)
002F:FFFFh
002F:E000h
SA7 (8KB)
002F:DFFFh
002F:C000h
SA6 (8KB)
002F:DFFFh
002F:C000h
SA6 (8KB)
002F:BFFFh
002F:A000h
SA5 (8KB)
002F:BFFFh
002F:A000h
SA5 (8KB)
002F:9FFFh
002F:8000h
SA4 (8KB)
002F:9FFFh
002F:8000h
SA4 (8KB)
002F:7FFFh
002F:6000h
SA3 (8KB)
002F:7FFFh
002F:6000h
SA3 (8KB)
002F:5FFFh
002F:4000h
SA2 (8KB)
002F:5FFFh
002F:4000h
SA2 (8KB)
002F:3FFFh
002F:2000h
SA1 (8KB)
002F:3FFFh
002F:2000h
SA1 (8KB)
002F:1FFFh
002F:0000h
SA0 (8KB)
002F:1FFFh
002F:0000h
16bit write mode
FA[1:0]=00
FA[1:0]=10
DQ[15:0]
DQ[15:0]
16bit write mode
SA0 (8KB)
FA[1:0]=00
FA[1:0]=10
DQ[15:0]
DQ[15:0]
Remark: Always keep FA[0] = 0 and FA[21] = 1
Document Number: 002-04608 Rev. *C
Page 47 of 127
CY91460B Series
CY91F465BB
CY91F464BB
FA[20:0]
FA[20:0]
001F:FFFFh
001F:0000h
SA19 (64KB)
001F:FFFFh
001F:0000h
SA19 (64KB)
001E:FFFFh
001E:0000h
SA18 (64KB)
001E:FFFFh
001E:0000h
SA18 (64KB)
001D:FFFFh
001D:0000h
SA17 (64KB)
001D:FFFFh
001D:0000h
SA17 (64KB)
001C:FFFFh
001C:0000h
SA16 (64KB)
001C:FFFFh
001C:0000h
SA16 (64KB)
001B:FFFFh
001B:0000h
SA15 (64KB)
001B:FFFFh
001B:0000h
SA15 (64KB)
001A:FFFFh
001A:0000h
SA14 (64KB)
001A:FFFFh
001A:0000h
SA14 (64KB)
0019:FFFFh
0019:0000h
SA13 (64KB)
SA13 (64KB)
0018:FFFFh
0018:0000h
SA12 (64KB)
SA12 (64KB)
SA11 (64KB)
SA11 (64KB)
SA10 (64KB)
SA10 (64KB)
SA9 (64KB)
SA9 (64KB)
SA8 (64KB)
SA8 (64KB)
0017:FFFFh
0017:E000h
SA7 (8KB)
0017:FFFFh
0017:E000h
SA7 (8KB)
0017:DFFFh
0017:C000h
SA6 (8KB)
0017:DFFFh
0017:C000h
SA6 (8KB)
0017:BFFFh
0017:A000h
SA5 (8KB)
0017:BFFFh
0017:A000h
SA5 (8KB)
0017:9FFFh
0017:8000h
SA4 (8KB)
0017:9FFFh
0017:8000h
SA4 (8KB)
16bit write mode
SA3 (8KB)
SA3 (8KB)
SA2 (8KB)
SA2 (8KB)
SA1 (8KB)
SA1 (8KB)
SA0 (8KB)
SA0 (8KB)
FA[1:0]=00
FA[1:0]=10
DQ[15:0]
DQ[15:0]
16bit write mode
Remark: Always keep FA[0] = 0 and FA[20] = 1
Legend
Memory available in this area
Remark: Always keep FA[0] = 0 and FA[21] = 1
Memory not available in this area
Document Number: 002-04608 Rev. *C
FA[1:0]=00
FA[1:0]=10
DQ[15:0]
DQ[15:0]
Remark: Always keep FA[0] = 0 and FA[20] = 1
Legend
Memory available in this area
Memory not available in this area
Page 48 of 127
CY91460B Series
9.4.2
Pin Connections in Parallel Programming Mode
Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory's interface circuit enables
direct control of the Flash memory unit from external pins by directly linking some of the signals to GP-Ports. Please see table below
for signal mapping.
In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set when writing/erasing
using the parallel Flash programmer. In this mode, all operations of the 8.5 Mbits Flash memory's Auto Algorithms are available.
Table 1. Correspondence between MBM29LV400TC and Flash Memory Control Signals
MBM29LV400TCE
CY91F467BA/466BA/F465BB/F464BB
FR-CPU Mode
xternal pins
External Pins
Flash Memory
Mode
Normal Function
Pin Number
-
INITX
-
INITX
84
RESET
-
FRSTX
GP16_6
70
-
-
MD2
MD2
76
Set to ‘1’
-
-
MD1
MD1
75
Set to ‘1’
-
-
MD0
MD0
74
Set to ‘1’
RY/BY
FMCS:RDY bit
RY/BYX
GP18_2
100
BYTE
Internally fixed to ‘H’
BYTEX
GP16_4
68
WE
WEX
GP16_7
71
OE
OEX
GP07_7
3
CEX
GP07_6
2
ATDIN
GP18_6
103
Set to ‘0’
-
EQIN
GP18_5
102
Set to ‘0’
-
TESTX
GP16_5
69
Set to ‘1’
-
RDYI
GP18_4
101
Set to ‘0’
A-1
FA0
GP05_5
17
Set to ‘0’
A0 to A3
FA1 to FA4
GP19_0 to GP19_2,
GP19_4
92 to 95
A4 to A7
FA5 to FA8
GP19_5 to GP19_6,
GP18_0 to GP18_1
96 to 99
FA9 to FA12
GP06_0 to GP06_3
4 to 7
A12 to A15
FA13 to FA16
GP06_4 to GP06_7
8 to 11
A16 to A18
FA17 to FA19
GP05_0 to GP05_2
12 to 14
A19
FA20
GP05_3
15
See note [1]
-
FA21
GP05_4
16
See note [2]
DQ0 to DQ7
GP00_0 to GP00_7
28 to 35
DQ8 to DQ15
GP01_0 to GP01_7
20 to 27
CE
-
A8 to A11
DQ0 to DQ7
DQ8 to DQ15
1.
2.
Comment
Internal control signal +
control via interface circuit
Internal address bus
Internal data bus
A19 is used as address bit on CY91F467BA/F466BA. For CY91F465BB/F464BB, set this pin to ‘1’.
For CY91F467BA/F466BA, set this pin to ‘1’. For CY91F465BB/F464BB, this pin can be left open.
Document Number: 002-04608 Rev. *C
Page 49 of 127
CY91460B Series
9.5
Poweron Sequence in Parallel Programming Mode
The flash memory can be accessed in programming mode after a certain wait time, which is needed for Security Vector fetch:
■
Minimum wait time after VDD5/VDD5R power on: 2.76 ms
■
Minimum wait time after INITX rising: 1.0 ms
9.6
Flash Security
9.6.1
Vector Addresses
Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1, BSV2) controlling the protection
functions of the Flash Security Module:
FSV1: 0x14:8000
FSV2: 0x14:8008
9.6.2
BSV1: 0x14:8004
BSV2: 0x14:800C
Security Vector FSV1
The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes and the individual
write protection of the 8 KBytes sectors.
9.6.2.1
FSV1 (bit31 to bit16)
The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write protection modes.
Table 2. Explanation of the bits in the Flash Security Vector FSV1[31:16]
FSV1[18]
FSV1[17]
FSV1[16]
FSV1[31:19] Write Protection Write
Protection
Read
Protection
Level
Flash Security Mode
set all to ‘0’
set to ‘0’
set to ‘0’
set to ‘1’
Read Protection (all device modes, except INTVEC
mode MD[2:0]=”000”)
set all to ‘0’
set to ‘0’
set to ‘1’
set to ‘0’
Write Protection (all device modes, without
exception)
set all to ‘0’
set to ‘0’
set to ‘1’
set to ‘1’
Read Protection (all device modes, except INTVEC
mode MD[2:0]=”000”) and Write Protection
(all device modes)
set all to ‘0’
set to ‘1’
set to ‘0’
set to ‘1’
Read Protection (all device modes, except INTVEC
mode MD[2:0]=”000”)
set all to ‘0’
set to ‘1’
set to ‘1’
set to ‘0’
Write Protection (all device modes, except INTVEC
mode MD[2:0]=”000”)
set to ‘1’
Read Protection (all device modes, except INTVEC
mode MD[2:0]=”000”) and Write Protection
(all device modes except INTVEC mode
MD[2:0]=”000”)
set all to ‘0’
set to ‘1’
Document Number: 002-04608 Rev. *C
set to ‘1’
Page 50 of 127
CY91460B Series
9.6.2.2
FSV1 (bit15 to bit0) CY91F467BA/466BA
The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write protection of the 8 KBytes sectors. It
is only evaluated if write protection bit FSV1[17] is set.
Table 3. Explanation of the Bits in the Flash Security Vector FSV1[15:0]
Enable Write
FSV1 bit
Sector
Protection
Disable Write
Protection
FSV1[0]
SA0
set to “0”
set to “1”
FSV1[1]
SA1
set to “0”
set to “1”
FSV1[2]
SA2
set to “0”
set to “1”
FSV1[3]
SA3
set to “0”
set to “1”
FSV1[4]
SA4
set to “0”
−
FSV1[5]
SA5
set to “0”
set to “1”
FSV1[6]
SA6
set to “0”
set to “1”
FSV1[7]
SA7
set to “0”
set to “1”
FSV1[15:8]
−
−
−
Comment
Write protection is mandatory!
not available
Note: It is mandatory to always set the sector where the Flash Security Vectors FSV1 and FSV2 are located to write protected (here
sector SA4). Otherwise it is possible to overwrite the Security Vector to a setting where it is possible to either read out the Flash
content or manipulate data by writing. See section “Flash access in CPU mode” for an overview about the sector organisation of the
Flash Memory.
9.6.2.3
FSV1 (bit15 to bit0) CY91F465BB/464BB
The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write protection of the 8 KBytes sectors. It
is only evaluated if write protection bit FSV1[17] is set.
Table 4. Explanation of the bits in the Flash Security Vector FSV1[15:0]
Enable Write
FSV1 bit
Sector
Protection
Disable Write
Protection
Comment
FSV1[3:0]
−
−
−
not available
FSV1[4]
SA4
set to “0”
—
Write protection is mandatory!
FSV1[5]
SA5
set to “0”
set to “1”
FSV1[6]
SA6
set to “0”
set to “1”
FSV1[7]
SA7
set to “0”
set to “1”
FSV1[15:8]
−
−
−
not available
Note: It is mandatory to always set the sector where the Flash Security Vectors FSV1 and FSV2 are located to write protected (here
sector SA4). Otherwise it is possible to overwrite the Security Vector to a setting where it is possible to either read out the Flash
content or manipulate data by writing. See section “Flash access in CPU mode” for an overview about the sector organisation of the
Flash Memory.
Document Number: 002-04608 Rev. *C
Page 51 of 127
CY91460B Series
9.6.3
Security Vector FSV2 CY91F467BA/466BA
The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write protection of the 64 KByte sectors. It
is only evaluated if write protection bit FSV1[17] is set.
Table 5. Explanation of the Bits in the Flash Security Vector FSV2[31:0]
Enable Write
FSV2 bit
Sector
Protection
Disable Write
Protection
FSV2[0]
SA8
set to “0”
set to “1”
FSV2[1]
SA9
set to “0”
set to “1”
FSV2[2]
SA10
set to “0”
set to “1”
FSV2[3]
SA11
set to “0”
set to “1”
FSV2[4]
SA12
set to “0”
set to “1”
FSV2[5]
SA13
set to “0”
set to “1”
FSV2[6]
SA14
set to “0”
set to “1”
FSV2[7]
SA15
set to “0”
set to “1”
FSV2[8]
SA16
set to “0”
set to “1”
FSV2[9]
SA17
set to “0”
set to “1”
FSV2[10]
SA18
set to “0”
set to “1”
FSV2[11]
SA19
set to “0”
set to “1”
FSV2[12]
SA20 (CY91F467BA)
set to “0”
set to “1”
FSV2[13]
SA21 (CY91F467BA)
set to “0”
set to “1”
FSV2[14]
SA22 (CY91F467BA)
set to “0”
set to “1”
FSV2[15]
SA23 (CY91F467BA)
set to “0”
set to “1”
FSV2[31:16]
−
set to “0”
set to “1”
Comment
not available
Note: See section “Flash access in CPU mode” for an overview about the sector organisation of the Flash Memory.
9.6.4
Security Vector FSV2 CY91F465BB/464BB
The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write protection of the 64 KByte sectors. It
is only evaluated if write protection bit FSV1[17] is set.
Table 6. Explanation of the Bits in the Flash Security Vector FSV2[31:0]
Enable Write
FSV2 bit
Sector
Protection
Disable Write
Protection
FSV2[3:0]
−
−
−
FSV2[4]
SA12 (CY91F465BB)
set to “0”
set to “1”
FSV2[5]
SA13 (CY91F465BB)
set to “0”
set to “1”
FSV2[6]
SA14
set to “0”
set to “1”
FSV2[7]
SA15
set to “0”
set to “1”
FSV2[8]
SA16
set to “0”
set to “1”
FSV2[9]
SA17
set to “0”
set to “1”
FSV2[10]
SA18
set to “0”
set to “1”
FSV2[11]
SA19
set to “0”
set to “1”
FSV2[31:12]
−
−
−
Comment
not available
not available
Note: See section “Flash access in CPU mode” for an overview about the sector organisation of the Flash Memory.
Document Number: 002-04608 Rev. *C
Page 52 of 127
CY91460B Series
10. Memory Space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
Direct addressing area
The following address space area is used for I/O.
■
This area is called direct addressing area, and the address of an operand can be specified directly in an instruction.
The size of directly addressable area depends on the length of the data being accessed as shown below.
Byte data access: 000H to 0FFH
Half word access: 000H to 1FFH
Word data access: 000H to 3FFH
Document Number: 002-04608 Rev. *C
Page 53 of 127
CY91460B Series
11. Memory Maps
11.1
CY91F467BA, CY91F466BA
CY91F467BA
00000000H
00000400H
00001000H
CY91F466BA
00000000H
I/O (direct addressing area)
00000400H
I/O
00001000H
DMA
00004000H
Flash-Cache (8 KBytes)
00007000H
Flash memory control
0000C000H
0000B000H
Boot ROM (4 Kbytes)
0000C000H
CAN
00030000H
Flash memory control
Boot ROM (4 Kbytes)
CAN
0000D000H
0000D000H
0002A000H
Flash-Cache (8 KBytes)
00008000H
00008000H
0000B000H
DMA
00006000H
00006000H
00007000H
I/O
00002000H
00002000H
00004000H
I/O (direct addressing area)
D-RAM (0 wait, 24 Kbytes)
ID-RAM (16 Kbytes)
0002A000H
00030000H
00034000H
00034000H
00040000H
00040000H
D-RAM (0 wait, 24 Kbytes)
ID-RAM (16 Kbytes)
External bus area
00080000H
Flash memory (768 Kbytes)
Flash memory (1088 Kbytes)
00100000H
00140000H
00150000H
00150000H
00180000H
00180000H
External bus area
00500000H
External bus area
00500000H
External data bus
FFFFFFFFH
Note:
Flash memory (64 Kbytes)
External data bus
FFFFFFFFH
Access prohibited areas
Document Number: 002-04608 Rev. *C
Note:
Access prohibited areas
Page 54 of 127
CY91460B Series
11.2
CY91F465BB, CY91F464BB
CY91F465BB
00000000H
00000400H
00001000H
CY91F464BB
I/O (direct addressing area)
00000000H
I/O
00000400H
DMA
00001000H
00002000H
00004000H
Flash-Cache (8 KBytes)
0000C000H
Flash memory control
00030000H
00004000H
Flash-Cache (8 KBytes)
00007000H
Flash memory control
00008000H
Boot ROM (4 Kbytes)
0000B000H
CAN
0000C000H
0000D000H
0002A000H
DMA
00006000H
00008000H
0000B000H
I/O
00002000H
00006000H
00007000H
I/O (direct addressing area)
Boot ROM (4 Kbytes)
CAN
0000D000H
D-RAM (0 wait, 24 Kbytes)
ID-RAM (16 Kbytes)
0002A000H
00030000H
00034000H
00034000H
00040000H
00040000H
External bus area
00080000H
D-RAM (0 wait, 24 Kbytes)
ID-RAM (16 Kbytes)
External bus area
00080000H
Flash memory (512 Kbytes)
000A0000H
Flash memory (384 Kbytes)
00100000H
00148000H
External bus area
Flash memory (32 Kbytes)
00150000H
00100000H
00148000H
Flash memory (32 Kbytes)
00150000H
00180000H
00180000H
External bus area
00500000H
External bus area
00500000H
External data bus
FFFFFFFFH
Note:
External bus area
External data bus
FFFFFFFFH
Access prohibited areas
Document Number: 002-04608 Rev. *C
Note:
Access prohibited areas
Page 55 of 127
CY91460B Series
12. I/O Map
12.1
CY91F467BA/466BA, CY91F465BB/464BB
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W]
XXXXXXXX
PDR1 [R/W]
XXXXXXXX
PDR2 [R/W]
XXXXXXXX
PDR3 [R/W]
XXXXXXXX
Block
T-unit
port data register
Read/write attribute
Register initial value after reset
Register name (column 1 register at address 4n, column 2 register at address
4n + 1...)
Leftmost register address (for word access, the register in column 1 becomes
the MSB side of the data.)
Note: Initial values of register bits are represented as follows:
“ 1 ”: Initial value “ 1 ”
“ 0 ”: Initial value “ 0 ”
“ X ”: Initial value “ undefined ”
“ - ”: No physical register at this location
Access is barred with an undefined data access attribute.
Document Number: 002-04608 Rev. *C
Page 56 of 127
CY91460B Series
Address
Register
Block
+0
+1
+2
+3
000000H
PDR00 [R/W]
XXXXXXXX
PDR01 [R/W]
XXXXXXXX
Reserved
Reserved
000004H
Reserved
PDR05 [R/W]
- - XXXXXX
PDR06 [R/W]
XXXXXXXX
PDR07 [R/W]
XXXXXXXX
000008H
PDR08 [R/W]
X--X---X
PDR09 [R/W]
- - - - - - XX
PDR10 [R/W]
-------X
Reserved
00000CH
Reserved
Reserved
PDR14 [R/W]
XXXXXXXX
PDR15 [R/W]
XXXXXXXX
000010H
PDR16 [R/W]
XXXXXXXX
PDR17 [R/W]
XXXXXXXX
PDR18 [R/W]
- XXX - XXX
PDR19 [R/W]
- XXX - XXX
000014H
PDR20 [R/W]
- XXX - XXX
PDR21 [R/W]
- - - - - - XX
PDR22 [R/W]
XXXXXXXX
PDR23 [R/W]
XXXXXXXX
000018H
PDR24 [R/W]
XXXXXXXX
Reserved
PDR26 [R/W]
XXXXXXXX
PDR27 [R/W]
XXXXXXXX
00001CH
PDR28 [R/W]
XXXXXXXX
PDR29 [R/W]
XXXXXXXX
Reserved
Reserved
000020H to
00002CH
000030H
R-bus Port Data Register
Reserved
EIRR0 [R/W]
CY91F467BA:
00000000:MD3=0
11110000:MD3=1
ENIR0 [R/W]
00000000
ELVR0 [R/W]
00000000 00000000
External interrupt
(INT 0 to INT 7)
ENIR1 [R/W]
00000000
ELVR1 [R/W]
00000000 00000000
External interrupt
(INT 8 to INT 15)
HRCL [R/W]
0 - - 11111
RBSYNC
Delay interrupt
CY91F465BB:
XXXXXXXX
000034H
EIRR1 [R/W]
CY91F467BA:
00000000
CY91F465BB:
XXXXXXXX
000038H
DICR [R/W]
-------0
00003CH
Reserved
000040H
SCR00 [R/W,W]
00000000
SMR00 [R/W,W]
00000000
000044H
ESCR00 [R/W]
00000X00
ECCR00
[R/W,R,W]
-00000XX
000048H
00004CH
Reserved
SSR00 [R/W,R]
00001000
RDR00/TDR00 [R/W]
00000000
LIN-USART 0
Reserved
Reserved
000050H
SCR02 [R/W,W]
00000000
SMR02 [R/W,W]
00000000
000054H
ESCR02 [R/W]
00000X00
ECCR02
[R/W,R,W]
-00000XX
Document Number: 002-04608 Rev. *C
Reserved
SSR02 [R/W,R]
00001000
RDR02/TDR02 [R/W]
00000000
LIN-USART 2
Reserved
Page 57 of 127
CY91460B Series
Address
Register
Block
+0
+1
+2
+3
000058H
SCR03 [R/W,W]
00000000
SMR03 [R/W,W]
00000000
SSR03 [R/W,R]
00001000
RDR03/TDR03 [R/W]
00000000
00005CH
ESCR03 [R/W]
00000X00
ECCR03
[R/W,R,W]
-00000XX
000060H
SCR04 [R/W,W]
00000000
SMR04 [R/W,W]
00000000
SSR04 [R/W,R]
00001000
RDR04/TDR04 [R/W]
00000000
000064H
ESCR04 [R/W]
00000X00
ECCR04
[R/W,R,W]
-00000XX
FSR04 [R]
- - - 00000
FCR04 [R/W]
0001 - 000
000068H
SCR05 [R/W,W]
00000000
SMR05 [R/W,W]
00000000
SSR05 [R/W,R]
00001000
RDR05/TDR05 [R/W]
00000000
00006CH
ESCR05 [R/W]
00000X00
ECCR05
[R/W,R,W]
-00000XX
FSR05 [R]
- - - 00000
FCR05 [R/W]
0001 - 000
000070H
SCR06 [R/W,W]
00000000
SMR06 [R/W,W]
00000000
SSR06 [R/W,R]
00001000
RDR06/TDR06 [R/W]
00000000
000074H
ESCR06 [R/W]
00000X00
ECCR06
[R/W,R,W]
-00000XX
FSR06 [R]
- - - 00000
FCR06 [R/W]
0001 - 000
000078H
SCR07 [R/W,W]
00000000
SMR07 [R/W,W]
00000000
SSR07 [R/W,R]
00001000
RDR07/TDR07 [R/W]
00000000
00007CH
ESCR07 [R/W]
00000X00
ECCR07
[R/W,R,W]
-00000XX
FSR07 [R]
- - - 00000
FCR07 [R/W]
0001 - 000
000080H
BGR100 [R/W]
00000000
BGR000 [R/W]
00000000
Reserved
Reserved
000084H
BGR102 [R/W]
00000000
BGR002 [R/W]
00000000
BGR103 [R/W]
00000000
BGR003 [R/W]
00000000
000088H
BGR104 [R/W]
00000000
BGR004 [R/W]
00000000
BGR105 [R/W]
00000000
BGR005 [R/W]
00000000
00008CH
BGR106 [R/W]
00000000
BGR006 [R/W]
00000000
BGR107 [R/W]
00000000
BGR007 [R/W]
00000000
000090H
to
0000CCH
LIN-USART 3
Reserved
Reserved
LIN-USART 5
with FIFO
LIN-USART 6
with FIFO
LIN-USART 7
with FIFO
Baud rate Generator
LIN-USART
0 to 7
Reserved
0000D0H
IBCR0 [R/W]
00000000
IBSR0 [R]
00000000
ITBAH0 [R/W]
- - - - - - 00
ITBAL0 [R/W]
00000000
0000D4H
ITMKH0 [R/W]
00 - - - - 11
ITMKL0 [R/W]
11111111
ISMK0 [R/W]
01111111
ISBA0 [R/W]
- 0000000
0000D8H
Reserved
IDAR0 [R/W]
00000000
ICCR0 [R/W]
- 0011111
Reserved
0000DCH
IBCR1 [R/W]
00000000
IBSR1 [R]
00000000
ITBAH1 [R/W]
- - - - - - 00
ITBAL1 [R/W]
00000000
0000E0H
ITMKH1 [R/W]
00 - - - - 11
ITMKL1 [R/W]
11111111
ISMK1 [R/W]
01111111
ISBA1 [R/W]
- 0000000
0000E4H
Reserved
IDAR1 [R/W]
00000000
ICCR1 [R/W]
- 0011111
Reserved
Document Number: 002-04608 Rev. *C
LIN-USART 4
with FIFO
I2 C 0
I2 C 1
Page 58 of 127
CY91460B Series
Address
Register
+0
+1
0000E8H
to
0000FCH
Block
+2
+3
Reserved
Reserved
000100H
GCN10 [R/W]
00110010 00010000
Reserved
GCN20 [R/W]
- - - - 0000
PPG Control
0 to 3
000104H
GCN11 [R/W]
00110010 00010000
Reserved
GCN21 [R/W]
- - - - 0000
PPG Control
4 to 7
000108H
GCN12 [R/W]
00110010 00010000
Reserved
GCN22 [R/W]
- - - - 0000
PPG Control
8 to 11
000110H
PTMR00 [R]
11111111 11111111
000114H
PDUT00 [W]
XXXXXXXX XXXXXXXX
000118H
PTMR01 [R]
11111111 11111111
00011CH
PDUT01 [W]
XXXXXXXX XXXXXXXX
000120H
PTMR02 [R]
11111111 11111111
000124H
PDUT02 [W]
XXXXXXXX XXXXXXXX
000128H
PTMR03 [R]
11111111 11111111
00012CH
PDUT03 [W]
XXXXXXXX XXXXXXXX
000130H
PTMR04 [R]
11111111 11111111
000134H
PDUT04 [W]
XXXXXXXX XXXXXXXX
000138H
PTMR05 [R]
11111111 11111111
00013CH
PDUT05 [W]
XXXXXXXX XXXXXXXX
000140H
PTMR06 [R]
11111111 11111111
000144H
PDUT06 [W]
XXXXXXXX XXXXXXXX
000148H
PTMR07 [R]
11111111 11111111
00014CH
PDUT07 [W]
XXXXXXXX XXXXXXXX
000150H
PTMR08 [R]
11111111 11111111
000154H
PDUT08 [W]
XXXXXXXX XXXXXXXX
Document Number: 002-04608 Rev. *C
PCSR00 [W]
XXXXXXXX XXXXXXXX
PCNH00 [R/W]
0000000 -
PCNL00 [R/W]
000000 - 0
PCSR01 [W]
XXXXXXXX XXXXXXXX
PCNH01 [R/W]
0000000 -
PCNL01 [R/W]
000000 - 0
PCSR02 [W]
XXXXXXXX XXXXXXXX
PCNH02 [R/W]
0000000 -
PCNL02 [R/W]
000000 - 0
PCSR03 [W]
XXXXXXXX XXXXXXXX
PCNH03 [R/W]
0000000 -
PCNL03 [R/W]
000000 - 0
PCSR04 [W]
XXXXXXXX XXXXXXXX
PCNH04 [R/W]
0000000 -
PCNL04 [R/W]
000000 - 0
PCSR05 [W]
XXXXXXXX XXXXXXXX
PCNH05 [R/W]
0000000 -
PCNL05 [R/W]
000000 - 0
PCSR06 [W]
XXXXXXXX XXXXXXXX
PCNH06 [R/W]
0000000 -
PCNL06 [R/W]
000000 - 0
PCSR07 [W]
XXXXXXXX XXXXXXXX
PCNH07 [R/W]
0000000 -
PCNL07 [R/W]
000000 - 0
PCSR08 [W]
XXXXXXXX XXXXXXXX
PCNH08 [R/W]
0000000 -
PCNL08 [R/W]
000000 - 0
PPG 0
PPG 1
PPG 2
PPG 3
PPG 4
PPG 5
PPG 6
PPG 7
PPG 8
Page 59 of 127
CY91460B Series
Address
Register
+0
+1
000158H
PTMR09 [R]
11111111 11111111
00015CH
PDUT09 [W]
XXXXXXXX XXXXXXXX
000160H
PTMR10 [R]
11111111 11111111
000164H
PDUT10 [W]
XXXXXXXX XXXXXXXX
000168H
PTMR11 [R]
11111111 11111111
00016CH
PDUT11 [W]
XXXXXXXX XXXXXXXX
000170H to
00017CH
000180H
Block
+2
+3
PCSR09 [W]
XXXXXXXX XXXXXXXX
PCNH09 [R/W]
0000000 -
PCNL09 [R/W]
000000 - 0
PCSR10 [W]
XXXXXXXX XXXXXXXX
PCNH10 [R/W]
0000000 -
PCNL10 [R/W]
000000 - 0
PCSR11 [W]
XXXXXXXX XXXXXXXX
PCNH11 [R/W]
0000000 -
PCNL11 [R/W]
000000 - 0
Reserved
ICS01 [R/W]
00000000
Reserved
Reserved
IPCP1 [R]
XXXXXXXX XXXXXXXX
000188H
IPCP2 [R]
XXXXXXXX XXXXXXXX
IPCP3 [R]
XXXXXXXX XXXXXXXX
00018CH
OCS01 [R/W]
- - - 0 - - 00 0000 - - 00
OCS23 [R/W]
- - - 0 - - 00 0000 - - 00
000190H
OCCP0 [R/W]
XXXXXXXX XXXXXXXX
OCCP1 [R/W]
XXXXXXXX XXXXXXXX
000194H
OCCP2 [R/W]
XXXXXXXX XXXXXXXX
OCCP3 [R/W]
XXXXXXXX XXXXXXXX
SGCRL [R/W]
- - 0 - - 000
00019CH
SGAR [R/W]
00000000
Reserved
0001A0H
ADERH [R/W]
00000000 00000000
SGFR [R/W, R]
XXXXXXXX XXXXXXXX
SGTR [R/W]
XXXXXXXX
SGDR [R/W]
XXXXXXXX
ADCS1 [R/W]
00000000
ADCS0 [R/W]
00000000
ADCR1 [R]
000000XX
ADCR0 [R]
XXXXXXXX
0001A8H
ADCT1 [R/W]
00010000
ADCT0 [R/W]
00101100
ADSCH [R/W]
- - - 00000
ADECH [R/W]
- - - 00000
0001ACH
Reserved
ACSR0 [R/W]
-11XXX00
Reserved
Reserved
TMRLR0 [W]
XXXXXXXX XXXXXXXX
0001B4H
Reserved
0001B8H
TMRLR1 [W]
XXXXXXXX XXXXXXXX
0001BCH
Reserved
Document Number: 002-04608 Rev. *C
Input Capture
0 to 3
Output Compare
0 to 3
Sound Generator
ADERL [R/W]
00000000 00000000
0001A4
0001B0H
PPG 11
ICS23 [R/W]
00000000
IPCP0 [R]
XXXXXXXX XXXXXXXX
SGCRH [R/W]
0000 - - 00
PPG 10
Reserved
000184H
000198H
PPG 9
TMR0 [R]
XXXXXXXX XXXXXXXX
TMCSRH0
[R/W]
- - - 00000
TMCSRL0
[R/W]
0 - 000000
TMR1 [R]
XXXXXXXX XXXXXXXX
TMCSRH1
[R/W]
- - - 00000
TMCSRL1
[R/W]
0 - 000000
A/D Converter
Alarm Comparator
0 to 1
Reload Timer 0
(PPG 0, PPG 1)
Reload Timer 1
(PPG 2, PPG 3)
Page 60 of 127
CY91460B Series
Address
Register
+0
0001C0H
+1
TMRLR2 [W]
XXXXXXXX XXXXXXXX
0001C4H
Reserved
0001C8H
TMRLR3 [W]
XXXXXXXX XXXXXXXX
0001CCH
Reserved
0001D0H
TMRLR4 [W]
XXXXXXXX XXXXXXXX
0001D4H
Reserved
0001D8H
TMRLR5 [W]
XXXXXXXX XXXXXXXX
0001DCH
Reserved
0001E0H
TMRLR6 [W]
XXXXXXXX XXXXXXXX
0001E4H
Reserved
0001E8H
TMRLR7 [W]
XXXXXXXX XXXXXXXX
Block
+2
+3
TMR2 [R]
XXXXXXXX XXXXXXXX
TMCSRH2
[R/W]
- - - 00000
TMCSRL2
[R/W]
0 - 000000
TMR3 [R]
XXXXXXXX XXXXXXXX
TMCSRH3
[R/W]
- - - 00000
TMCSRL3
[R/W]
0 - 000000
TMR4 [R]
XXXXXXXX XXXXXXXX
TMCSRH4
[R/W]
- - - 00000
TMCSRL4
[R/W]
0 - 000000
TMR5 [R]
XXXXXXXX XXXXXXXX
TMCSRH5
[R/W]
- - - 00000
TMCSRL5
[R/W]
0 - 000000
TMR6 [R]
XXXXXXXX XXXXXXXX
TMCSRH6
[R/W]
- - - 00000
TMCSRL6
[R/W]
0 - 000000
TMR7 [R]
XXXXXXXX XXXXXXXX
TMCSRL7
[R/W]
0 - 000000
Reload Timer 2
(PPG 4, PPG 5)
Reload Timer 3
(PPG 6, PPG 7)
Reload Timer 4
(PPG 8, PPG 9)
Reload Timer 5
(PPG 10, PPG 11)
Reload Timer 6
(PPG 12, PPG 13)
Reload Timer 7
(PPG 14, PPG 15)
(A/D Converter)
0001ECH
Reserved
TMCSRH7
[R/W]
- - - 00000
0001F0H
TCDT0 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS0 [R/W]
00000000
Free Running Timer 0
(ICU 0, ICU 1)
0001F4H
TCDT1 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS1 [R/W]
00000000
Free Running Timer 1
(ICU 2, ICU 3)
0001F8H
TCDT2 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS2 [R/W]
00000000
Free Running Timer 2
(OCU 0, OCU 1)
0001FCH
TCDT3 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS3 [R/W]
00000000
Free Running Timer 3
(OCU 2, OCU 3)
Document Number: 002-04608 Rev. *C
Page 61 of 127
CY91460B Series
Address
Register
+0
+1
Block
+2
000200H
DMACA0 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
to 00023CH
Reserved
000240H
DMACR [R/W]
00 - - 0000
DMAC
DMAC
Reserved
000244H
to 0002CCH
0002D0H
+3
Reserved
Reserved
ICS045 [R/W]
00000000
Reserved
Reserved
ICS67 [R/W]
00000000
0002D4H
IPCP4 [R]
XXXXXXXX XXXXXXXX
IPCP5 [R]
XXXXXXXX XXXXXXXX
0002D8H
IPCP6 [R]
XXXXXXXX XXXXXXXX
IPCP7 [R]
XXXXXXXX XXXXXXXX
0002DCH
OCS45 [R/W]
- - - 0 - - 00 0000 - - 00
OCS67 [R/W]
- - - 0 - - 00 0000 - - 00
0002E0H
OCCP4 [R/W]
XXXXXXXX XXXXXXXX
OCCP5 [R/W]
XXXXXXXX XXXXXXXX
0002E4H
OCCP6 [R/W]
XXXXXXXX XXXXXXXX
OCCP7 [R/W]
XXXXXXXX XXXXXXXX
0002E8H
to 0002ECH
Reserved
Input Capture
4 to 7
Output Compare
4 to 7
Reserved
0002F0H
TCDT4 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS4 [R/W]
00000000
Free Running Timer 4
(ICU 4, ICU 5)
0002F4H
TCDT5 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS5 [R/W]
00000000
Free Running Timer 5
(ICU 6, ICU 7)
0002F8H
TCDT6 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS6 [R/W]
00000000
Free Running Timer 6
(OCU 4, OCU 5)
0002FCH
TCDT7 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS7 [R/W]
00000000
Free Running Timer 7
(OCU 6, OCU 7)
Document Number: 002-04608 Rev. *C
Page 62 of 127
CY91460B Series
Address
Register
Block
+0
+1
+2
+3
000300H
UDRC1 [W]
00000000
UDRC0 [W]
00000000
UDCR1 [R]
00000000
UDCR0 [R]
00000000
000304H
UDCCH0 [R/W]
00000000
UDCCL0 [R/W]
00001000
Reserved
UDCS0 [R/W]
00000000
000308H
UDCCH1 [R/W]
00000000
UDCCL1 [R/W]
00001000
Reserved
UDCS1 [R/W]
00000000
00030CH to
00031CH
000320H
Reserved
GCN13 [R/W]
00110010 00010000
000324H
to 00032CH
PTMR12 [R]
11111111 11111111
000334H
PDUT12 [W]
XXXXXXXX XXXXXXXX
000338H
PTMR13 [R]
11111111 11111111
00033CH
PDUT13 [W]
XXXXXXXX XXXXXXXX
000340H
PTMR14 [R]
11111111 11111111
000344H
PDUT14 [W]
XXXXXXXX XXXXXXXX
000348H
PTMR15 [R]
11111111 11111111
00034CH
PDUT15 [W]
XXXXXXXX XXXXXXXX
000350H to
00038CH
000390H
Reserved
GCN23 [R/W]
- - - - 0000
Reserved
Reserved
000330H
PCNH12 [R/W]
0000000 -
PCNL12 [R/W]
000000 - 0
PCSR13 [W]
XXXXXXXX XXXXXXXX
PCNH13 [R/W]
0000000 -
PCNL13 [R/W]
000000 - 0
PCSR14 [W]
XXXXXXXX XXXXXXXX
PCNH14 [R/W]
0000000 -
PCNL14 [R/W]
000000 - 0
PCSR15 [W]
XXXXXXXX XXXXXXXX
PCNH15 [R/W]
0000000 -
PCNL15 [R/W]
000000 - 0
Reserved
PPG 12
PPG 13
PPG 14
PPG 15
Reserved
Reserved
000394H
to 0003ECH
Reserved
0003F0H
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000400H
to 00043CH
Reserved
Document Number: 002-04608 Rev. *C
PPG Control
12 to 15
Reserved
PCSR12 [W]
XXXXXXXX XXXXXXXX
ROMS [R]
11111111 00000000 (CY91F467BA/466BA)
11111111 01000011 (CY91F465BB/464BB)
Up/Down Counter
0 to 1
ROM Select Register
Reserved
Bit Search Module
Page 63 of 127
CY91460B Series
Address
Register
Block
+0
+1
+2
+3
000440H
ICR00 [R/W]
---11111
ICR01 [R/W]
---11111
ICR02 [R/W]
---11111
ICR03 [R/W]
---11111
000444H
ICR04 [R/W]
---11111
ICR05 [R/W]
---11111
ICR06 [R/W]
---11111
ICR07 [R/W]
---11111
000448H
ICR08 [R/W]
---11111
ICR09 [R/W]
---11111
ICR10 [R/W]
---11111
ICR11 [R/W]
---11111
00044CH
ICR12 [R/W]
---11111
ICR13 [R/W]
---11111
ICR14 [R/W]
---11111
ICR15 [R/W]
---11111
000450H
ICR16 [R/W]
---11111
ICR17 [R/W]
---11111
ICR18 [R/W]
---11111
ICR19 [R/W]
---11111
000454H
ICR20 [R/W]
---11111
ICR21 [R/W]
---11111
ICR22 [R/W]
---11111
ICR23 [R/W]
---11111
000458H
ICR24 [R/W]
---11111
ICR25 [R/W]
---11111
ICR26 [R/W]
---11111
ICR27 [R/W]
---11111
00045CH
ICR28 [R/W]
---11111
ICR29 [R/W]
---11111
ICR30 [R/W]
---11111
ICR31 [R/W]
---11111
000460H
ICR32 [R/W]
---11111
ICR33 [R/W]
---11111
ICR34[R/W]
---11111
ICR35 [R/W]
---11111
000464H
ICR36 [R/W]
---11111
ICR37 [R/W]
---11111
ICR38 [R/W]
---11111
ICR39 [R/W]
---11111
000468H
ICR40 [R/W]
---11111
ICR41 [R/W]
---11111
ICR42 [R/W]
---11111
ICR43 [R/W]
---11111
00046CH
ICR44 [R/W]
---11111
ICR45 [R/W]
---11111
ICR46 [R/W]
---11111
ICR47 [R/W]
---11111
000470H
ICR48 [R/W]
---11111
ICR49 [R/W]
---11111
ICR50 [R/W]
---11111
ICR51 [R/W]
---11111
000474H
ICR52 [R/W]
---11111
ICR53 [R/W]
---11111
ICR54 [R/W]
---11111
ICR55 [R/W]
---11111
000478H
ICR56 [R/W]
---11111
ICR57 [R/W]
---11111
ICR58 [R/W]
---11111
ICR59 [R/W]
---11111
00047CH
ICR60 [R/W]
---11111
ICR61 [R/W]
---11111
ICR62 [R/W]
---11111
ICR63 [R/W]
---11111
000480H
RSRR [R/W]
10000000
STCR [R/W]
00110011
TBCR [R/W]
00XXXX00
CTBR [W]
XXXXXXXX
000484H
CLKR [R/W]
- - - - 0000
WPR [W]
XXXXXXXX
DIVR0 [R/W]
00000011
DIVR1 [R/W]
00000000
00048CH
PLLDIVM [R/W]
- - - - 0000
PLLDIVN [R/W]
- - 000000
PLLDIVG [R/W]
- - - - 0000
PLLMULG [R/W]
00000000
000490H
PLLCTRL [R/W]
- - - - 0000
000494H
OSCC1 [R/W]
- - - - - 010
000498H
PORTEN [R/W]
- - - - - - 00
000488H
Reserved
Document Number: 002-04608 Rev. *C
Interrupt Controller
Interrupt Controller
Clock
Control
Reserved
PLL Interface
Reserved
OSCS1 [R/W]
00001111
OSCC2 [R/W]
- - - - - 010
Reserved
OSCS2 [R/W]
00001111
Main/Sub Oscillator
Control (Reserved)
Port Input Enable Control
Page 64 of 127
CY91460B Series
Address
Register
Block
+0
+1
+2
+3
0004A0H
Reserved
WTCER [R/W]
- - - - - - 00
0004A4H
Reserved
0004A8H
WTHR [R/W]
- - - 00000
WTMR [R/W]
- - 000000
WTSR [R/W]
- - 000000
Reserved
0004ACH
CSVTR [R/W]
- - - 00010
CSVCR [R/W]
- 011100
CSCFG [R/W]
0X000000
CMCFG [R/W]
00000000
WTCR [R/W]
00000000 000 - 00 - 0
Real Time Clock
(Watch Timer)
WTBR [R/W]
- - - XXXXX XXXXXXXX XXXXXXXX
0004B0H
CUCR [R/W]
- - - - - - - - - - - 0 - - 00
CUTD [R/W]
10000000 00000000
0004B4H
CUTR1 [R]
- - - - - - - - 00000000
CUTR2 [R]
00000000 00000000
0004B8H
CMPR [R/W]
- - 000010 11111101
0004BCH
CMT1 [R/W]
00000000 1 - - - 0000
CMCR [R/W]
- 001 - - 00
Reserved
CMT2 [R/W]
- - 000000 - - 000000
Clock- Supervisor /
Selector/ Monitor
Calibration of Sub Clock
Clock
Modulator
0004C0H
CANPRE [R/W]
0 - - - 0000
CANCKD [R/W]
- - 000000
0004C4H
LVSEL [R/W]
00000111
LVDET [R/W]
00000 - 00
HWWDE [R/W]
- - - - - - 00
HWWD [R/W,W]
00011000
Low Voltage Detection/
Hardware Watchdog
0004C8H
OSCRH [R/W]
000 - - 001
OSCRL [R/W]
- - - - - 000
WPCRH [R/W]
000 - - 001
WPCRL [R/W]
- - - - - - 00
Main-/Sub-Oscillation Stabilisation Timer
0004CCH
OSCCR [R/W]
- - - - - - 00
Reserved
REGSEL [R/W]
- - 000110
REGCTR [R/W]
- - - 0 - - 00
Main- Oscillation Standby
Control / Main/
Sub Regulator Control
0004D0H to
00063CH
Document Number: 002-04608 Rev. *C
Reserved
Reserved
CAN Clock Control
Reserved
Page 65 of 127
CY91460B Series
Address
Register
+0
+1
Block
+2
+3
000640H
ASR0 [R/W]
00000000 00000000
ACR0 [R/W]
1111**00 00000000[2]
000644H
ASR1 [R/W]
XXXXXXXX XXXXXXXX
ACR1 [R/W]
XXXXXXXX XXXXXXXX
000648H
ASR2 [R/W]
XXXXXXXX XXXXXXXX
ACR2 [R/W]
XXXXXXXX XXXXXXXX
00064CH
ASR3 [R/W]
XXXXXXXX XXXXXXXX
ACR3 [R/W]
XXXXXXXX XXXXXXXX
000650H
ASR4 [R/W]
XXXXXXXX XXXXXXXX
ACR4 [R/W]
XXXXXXXX XXXXXXXX
000654H
ASR5 [R/W]
XXXXXXXX XXXXXXXX
ACR5 [R/W]
XXXXXXXX XXXXXXXX
000658H
ASR6 [R/W]
XXXXXXXX XXXXXXXX
ACR6 [R/W]
XXXXXXXX XXXXXXXX
00065CH
ASR7 [R/W]
XXXXXXXX XXXXXXXX
ACR7 [R/W]
XXXXXXXX XXXXXXXX
000660H
AWR0 [R/W]
01111111 11111*11
AWR1 [R/W]
XXXXXXXX XXXXXXXX
000664H
AWR2 [R/W]
XXXXXXXX XXXXXXXX
AWR3 [R/W]
XXXXXXXX XXXXXXXX
000668H
AWR4 [R/W]
XXXXXXXX XXXXXXXX
AWR5 [R/W]
XXXXXXXX XXXXXXXX
00066CH
AWR6 [R/W]
XXXXXXXX XXXXXXXX
AWR7 [R/W]
XXXXXXXX XXXXXXXX
000670H
MCRA [R/W]
XXXXXXXX
MCRB [R/W]
XXXXXXXX
000674H
Reserved
Reserved
IOWR0 [R/W]
XXXXXXXX
IOWR1 [R/W]
XXXXXXXX
000680H
CSER [R/W]
00000001
CHER [R/W]
11111111
000684H
RCRH [R/W]
00XXXXXX
RCRL [R/W]
XXXX0XXX
000678H
IOWR2 [R/W]
XXXXXXXX
IOWR3 [R/W]
XXXXXXXX
Reserved
TCR [R/W]
0000**** [3]
Reserved
00067CH
000688H
to 0007F8H
0007FCH
External Bus Unit
Reserved
Reserved
Reserved
000800H
to 000CFCH
Document Number: 002-04608 Rev. *C
MODR [W]
XXXXXXXX
External Bus Unit
Reserved
Reserved
Mode Register
Reserved
Page 66 of 127
CY91460B Series
Address
Register
Block
+0
+1
000D00H
PDRD00 [R]
XXXXXXXX
PDRD01 [R]
XXXXXXXX
000D04H
Reserved
PDRD05 [R]
- - XXXXXX
PDRD06 [R]
XXXXXXXX
PDRD07 [R]
XXXXXXXX
000D08H
PDRD08 [R]
X - - X - - -X
PDRD09 [R]
- - - - - - XX
PDRD10 [R]
-------X
Reserved
PDRD14 [R]
XXXXXXXX
PDRD15 [R]
XXXXXXXX
000D0CH
+2
+3
Reserved
Reserved
000D10H
PDRD16 [R]
XXXXXXXX
PDRD17 [R]
XXXXXXXX
PDRD18 [R]
- XXX - XXX
PDRD19 [R]
- XXX - XXX
000D14H
PDRD20 [R]
- XXX - XXX
PDRD21 [R]
-------X
PDRD22 [R]
XXXXXXXX
PDRD23 [R]
XXXXXXXX
000D18H
PDRD24 [R]
XXXXXXXX
Reserved
PDRD26 [R]
XXXXXXXX
PDRD27 [R]
XXXXXXXX
000D1CH
PDRD28 [R]
XXXXXXXX
PDRD29 [R]
XXXXXXXX
000D20H to
000D3CH
R-bus Port Data
Direct Read Register
Reserved
Reserved
000D40H
DDR00 [R/W]
00000000
DDR01 [R/W]
00000000
000D44H
Reserved
DDR05 [R/W]
- - 000000
DDR06 [R/W]
00000000
DDR07 [R/W]
00000000
000D48H
DDR08 [R/W]
0 - - 0 - - -0
DDR09 [R/W]
- - - - - - 00
DDR10 [R/W]
- - - - - - -0
Reserved
DDR14 [R/W]
00000000
DDR15 [R/W]
00000000
000D4CH
Reserved
Reserved
000D50H
DDR16 [R/W]
00000000
DDR17 [R/W]
00000000
DDR18 [R/W]
- 000 - 000
DDR19 [R/W]
- 000 - 000
000D54H
DDR20 [R/W]
- 000 - 000
DDR21 [R/W]
- - - - - - 00
DDR22 [R/W]
00000000
DDR23 [R/W]
00000000
000D58H
DDR24 [R/W]
00000000
Reserved
DDR26 [R/W]
00000000
DDR27 [R/W]
00000000
000D5CH
DDR28 [R/W]
00000000
DDR29 [R/W]
00000000
000D60H to
000D7CH
Document Number: 002-04608 Rev. *C
Reserved
R-bus Port Direction
Register
Reserved
Reserved
Page 67 of 127
CY91460B Series
Address
Register
Block
+0
+1
000D80H
PFR00 [R/W]
11111111
PFR01 [R/W]
11111111
000D84H
Reserved
PFR05 [R/W]
- - 111111
PFR06 [R/W]
11111111
PFR07 [R/W]
11111111
000D88H
PFR08 [R/W]
1 - - 1 - - 11
PFR09 [R/W]
- - - - - - 11
PFR10 [R/W]
- - - - - - -1
Reserved
PFR14 [R/W]
00000000
PFR15 [R/W]
00000000
000D8CH
+2
Reserved
+3
Reserved
000D90H
PFR16 [R/W]
00000000
PFR17 [R/W]
00000000
PFR18 [R/W]
- 000 - 000
PFR19 [R/W]
- 000 - 000
000D94H
PFR20 [R/W]
- 000 - 000
PFR21 [R/W]
- - - - - - 00
PFR22 [R/W]
0000-0-0
PFR23 [R/W]
-0000000
000D98H
PFR24 [R/W]
00000000
Reserved
PFR26 [R/W]
00000000
PFR27 [R/W]
00000000
000D9CH
PFR28 [R/W]
00000000
PFR29 [R/W]
00000000
000DA0H
to 000DC4H
Reserved
Reserved
000DC8H
Reserved
EPFR10 [R/W]
-------0
Reserved
000DCCH
Reserved
EPFR14 [R/W]
00000000
EPFR15 [R/W]
00000000
EPFR18 [R/W]
- 000 - 000
EPFR19 [R/W]
- 0- - - 0- -
000DD0H
EPFR16 [R/W]
0 - 00 - - - -
Reserved
000DD4H
EPFR20 [R/W]
- 000 - 000
EPFR21 [R/W]
---- ----
000DD8H
EPFR27 [R/W]
00000000
Reserved
Reserved
000E00H
PODR00 [R/W]
00000000
PODR01 [R/W]
00000000
000E04H
Reserved
PODR05 [R/W]
- - 000000
PODR06 [R/W]
00000000
PODR07 [R/W]
00000000
000E08H
PODR08 [R/W]
0--0---0
PODR09 [R/W]
- - - - - - 00
PODR10 [R/W]
-------0
Reserved
PODR14 [R/W]
00000000
PODR15 [R/W]
00000000
Reserved
Reserved
000E10H
PODR16 [R/W]
00000000
PODR17 [R/W]
00000000
PODR18 [R/W]
- 000 - 000
PODR19 [R/W]
- 000 - 000
000E14H
PODR20 [R/W]
- 000 - 000
PODR21 [R/W]
- - - - - - 00
PODR22 [R/W]
00000000
PODR23 [R/W]
00000000
000E18H
PODR24 [R/W]
00000000
Reserved
PODR26 [R/W]
00000000
PODR27 [R/W]
00000000
000E1CH
PODR28 [R/W]
00000000
PODR29 [R/W]
00000000
000E20H
to 000E3CH
Document Number: 002-04608 Rev. *C
Reserved
R-bus Port Extra Function
Register
Reserved
EPFR26 [R/W]
00000000
Reserved
000DDCH
to 000DFCH
000E0CH
R-bus Port Function
Register
R-bus Port Output Drive
Select Register
Reserved
Reserved
Page 68 of 127
CY91460B Series
Address
Register
Block
+0
+1
000E40H
PILR00 [R/W]
00000000
PILR01 [R/W]
00000000
000E44H
Reserved
PILR05 [R/W]
- - 000000
PILR06 [R/W]
00000000
PILR07 [R/W]
00000000
000E48H
PILR08 [R/W]
0--0---0
PILR09 [R/W]
- - - - - - 00
PILR10 [R/W]
-------0
Reserved
PILR14 [R/W]
00000000
PILR15 [R/W]
00000000
000E4CH
+2
Reserved
+3
Reserved
000E50H
PILR16 [R/W]
00000000
PILR17 [R/W]
00000000
PILR18 [R/W]
- - - - - 000
PILR19 [R/W]
- 000 - 000
000E54H
PILR20 [R/W]
- 000 - 000
PILR21 [R/W]
- - - - - - 00
PILR22 [R/W]
00000000
PILR23 [R/W]
00000000
000E58H
PILR24 [R/W]
00000000
Reserved
PILR26 [R/W]
00000000
PILR27 [R/W]
00000000
000E5CH
PILR28 [R/W]
00000000
PILR29 [R/W]
00000000
000E60H
to 000E7CH
Reserved
Reserved
Reserved
000E80H
EPILR00 [R/W]
00000000
EPILR01 [R/W]
00000000
000E84H
Reserved
EPILR05 [R/W]
- - 000000
EPILR06 [R/W]
00000000
EPILR07 [R/W]
00000000
000E88H
EPILR08 [R/W]
0 - - 0- - - 0
EPILR09 [R/W]
- - - - - - 00
EPILR10 [R/W]
-------0
Reserved
EPILR14 [R/W]
00000000
EPILR15 [R/W]
00000000
000E8CH
Reserved
Reserved
000E90H
EPILR16 [R/W]
00000000
EPILR17 [R/W]
00000000
EPILR18 [R/W]
- - - - - 000
EPILR19 [R/W]
- 000 - 000
000E94H
EPILR20 [R/W]
- 000 - 000
EPILR21 [R/W]
- - - - - - 00
EPILR22 [R/W]
00000000
EPILR23 [R/W]
00000000
000E98H
EPILR24 [R/W]
00000000
Reserved
EPILR26 [R/W]
00000000
EPILR27 [R/W]
00000000
000E9CH
EPILR28 [R/W]
00000000
EPILR29 [R/W]
00000000
000EA0H
to 000EBCH
Document Number: 002-04608 Rev. *C
Reserved
R-bus Port Input Level
Select Register
R-bus Port Extra Input
Level Select Register
Reserved
Reserved
Page 69 of 127
CY91460B Series
Address
Register
Block
+0
+1
000EC0H
PPER00 [R/W]
00000000
PPER01 [R/W]
00000000
000EC4H
Reserved
PPER05 [R/W]
- - 000000
PPER06 [R/W]
00000000
PPER07 [R/W]
00000000
000EC8H
PPER08 [R/W]
0--0---0
PPER09 [R/W]
- - - - - - 00
PPER10 [R/W]
-------0
Reserved
PPER14 [R/W]
00000000
PPER15 [R/W]
00000000
000ECCH
+2
Reserved
+3
Reserved
000ED0H
PPER16 [R/W]
00000000
PPER17 [R/W]
00000000
PPER18 [R/W]
- 000 - 000
PPER19 [R/W]
- 000 - 000
000ED4H
PPER20 [R/W]
- 000 - 000
PPER21 [R/W]
- - - - - - 00
PPER22 [R/W]
00000000
PPER23 [R/W]
00000000
000ED8H
PPER24 [R/W]
00000000
Reserved
PPER26 [R/W]
00000000
PPER27 [R/W]
00000000
000EDCH
PPER28 [R/W]
00000000
PPER29 [R/W]
00000000
000EE0H to
000EFCH
Reserved
Reserved
Reserved
000F00H
PPCR00 [R/W]
11111111
PPCR01 [R/W]
11111111
000F04H
Reserved
PPCR05 [R/W]
- - 111111
PPCR06 [R/W]
11111111
PPCR07 [R/W]
11111111
000F08H
PPCR08 [R/W]
1--1---1
PPCR09 [R/W]
- - - - - - 11
PPCR10 [R/W]
-------1
Reserved
PPCR14 [R/W]
00000000
PPCR15 [R/W]
11111111
000F0CH
Reserved
Reserved
000F10H
PPCR16 [R/W]
00000000
PPCR17 [R/W]
00000000
PPCR18 [R/W]
- 111- 111
PPCR19 [R/W]
- 111- 111
000F14H
PPCR20 [R/W]
- 111- 111
PPCR21 [R/W]
- - - - - - 11
PPCR22 [R/W]
11111111
PPCR23 [R/W]
11111111
000F18H
PPCR24 [R/W]
11111111
Reserved
PPCR26 [R/W]
11111111
PPCR27 [R/W]
11111111
000F1CH
PPCR28 [R/W]
11111111
PPCR29 [R/W]
11111111
000F20H to
000F3CH
Document Number: 002-04608 Rev. *C
Reserved
R-bus Port
Pull-Up/Down Enable
Register
R-bus Port
Pull-Up/Down Control
Register
Reserved
Reserved
Page 70 of 127
CY91460B Series
Address
Register
+0
+1
Block
+2
+3
001000H
DMASA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
to 003FFCH
Reserved
Reserved
002000H
to 006FFCH
Flash-cache size is 8 Kbytes : 004000H to 005FFCH
Flash-cache / I-RAM area
007000H
007004H
FMCS [R/W]
01101000
FMCR [R/W]
- - - - 0000
DMAC
FCHCR [R/W]
- - - - - - 00 10000011
FMWT [R/W]
11111111 11111111
FMPS [R/W]
- - - - - 000
Reserved
Flash Memory/ I-Cache
Control Register
007008H
FMAC [R]
00000000 00000000 00000000 00000000
00700CH
FCHA0 [R/W]
- - - - - - - - - - 000000 00000000 00000000
007010H
FCHA1 [R/W]
- - - - - - - - - - 000000 00000000 00000000
007014H
to 007FFCH
Reserved
Reserved
008000H
to 00BFFCH
Boot-ROM size is 4 Kbytes : 00B000H to 00BFFCH
(instruction access is 1 wait cycle, data access is 1 wait cycle)
Boot ROM area
00C000H
CTRLR0 [R/W]
00000000 00000001
STATR0 [R/W]
00000000 00000000
00C004H
ERRCNT0 [R]
00000000 00000000
BTR0 [R/W]
00100011 00000001
00C008H
INTR0 [R]
00000000 00000000
TESTR0 [R/W]
00000000 X0000000
00C00CH
BRPE0 [R/W]
00000000 00000000
CBSYNC0
Document Number: 002-04608 Rev. *C
I-Cache Non-cacheable
area setting Register
CAN 0
Control Register
Page 71 of 127
CY91460B Series
Address
Register
+0
+1
Block
+2
+3
00C010H
IF1CREQ0 [R/W]
00000000 00000001
IF1CMSK0 [R/W]
00000000 00000000
00C014H
IF1MSK20 [R/W]
11111111 11111111
IF1MSK10 [R/W]
11111111 11111111
00C018H
IF1ARB20 [R/W]
00000000 00000000
IF1ARB10 [R/W]
00000000 00000000
00C01CH
IF1MCTR0 [R/W]
00000000 00000000
Reserved
00C020H
IF1DTA10 [R/W]
00000000 00000000
IF1DTA20 [R/W]
00000000 00000000
00C024H
IF1DTB10 [R/W]
00000000 00000000
IF1DTB20 [R/W]
00000000 00000000
00C028H
to 00C02CH
CAN 0
IF 1 Register
Reserved
00C030H
IF1DTA20 [R/W]
00000000 00000000
IF1DTA10 [R/W]
00000000 00000000
00C034H
IF1DTB20 [R/W]
00000000 00000000
IF1DTB10 [R/W]
00000000 00000000
00C038H
to 00C03CH
Reserved
00C040H
IF2CREQ0 [R/W]
00000000 00000001
IF2CMSK0 [R/W]
00000000 00000000
00C044H
IF2MSK20 [R/W]
11111111 11111111
IF2MSK10 [R/W]
11111111 11111111
00C048H
IF2ARB20 [R/W]
00000000 00000000
IF2ARB10 [R/W]
00000000 00000000
00C04CH
IF2MCTR0 [R/W]
00000000 00000000
Reserved
00C050H
IF2DTA10 [R/W]
00000000 00000000
IF2DTA20 [R/W]
00000000 00000000
00C054H
IF2DTB10 [R/W]
00000000 00000000
IF2DTB20 [R/W]
00000000 00000000
00C058H
to 00C05CH
CAN 0
IF 2 Register
Reserved
00C060H
IF2DTA20 [R/W]
00000000 00000000
IF2DTA10 [R/W]
00000000 00000000
00C064H
IF2DTB20 [R/W]
00000000 00000000
IF2DTB10 [R/W]
00000000 00000000
00C068H
to 00C07CH
Document Number: 002-04608 Rev. *C
Reserved
Page 72 of 127
CY91460B Series
Address
Register
+0
+1
Block
+2
+3
00C080H
TREQR20 [R]
00000000 00000000
TREQR10 [R]
00000000 00000000
00C084H to
00C08CH
Reserved
Reserved
00C090H
NEWDT20 [R]
00000000 00000000
NEWDT10 [R]
00000000 00000000
00C094H to
00C09CH
Reserved
Reserved
00C0A0H
INTPND20 [R]
00000000 00000000
INTPND10 [R]
00000000 00000000
00C0A4H to
00C0ACH
Reserved
Reserved
00C0B0H
MSGVAL20 [R]
00000000 00000000
MSGVAL10 [R]
00000000 00000000
00C0B4H to
00C0FCH
Reserved
Reserved
00C100H
CTRLR1 [R/W]
00000000 00000001
STATR1 [R/W]
00000000 00000000
00C104H
ERRCNT1 [R]
00000000 00000000
BTR1 [R/W]
00100011 00000001
00C108H
INTR1 [R]
00000000 00000000
TESTR1 [R/W]
00000000 X0000000
00C10CH
BRPE1 [R/W]
00000000 00000000
CBSYNC1
00C110H
IF1CREQ1 [R/W]
00000000 00000001
IF1CMSK1 [R/W]
00000000 00000000
00C114H
IF1MSK21 [R/W]
11111111 11111111
IF1MSK11 [R/W]
11111111 11111111
00C118H
IF1ARB21 [R/W]
00000000 00000000
IF1ARB11 [R/W]
00000000 00000000
00C11CH
IF1MCTR1 [R/W]
00000000 00000000
Reserved
00C120H
IF1DTA11 [R/W]
00000000 00000000
IF1DTA21 [R/W]
00000000 00000000
00C124H
IF1DTB11 [R/W]
00000000 00000000
IF1DTB21 [R/W]
00000000 00000000
00C128H
to 00C12CH
CAN 0
Status Flags
CAN 1
Control Register
CAN 1
IF 1 Register
Reserved
00C130H
IF1DTA21 [R/W]
00000000 00000000
IF1DTA11 [R/W]
00000000 00000000
00C134H
IF1DTB21 [R/W]
00000000 00000000
IF1DTB11 [R/W]
00000000 00000000
00C138H
to 00C13CH
Document Number: 002-04608 Rev. *C
Reserved
Page 73 of 127
CY91460B Series
Address
Register
+0
+1
Block
+2
+3
00C140H
IF2CREQ1 [R/W]
00000000 00000001
IF2CMSK1 [R/W]
00000000 00000000
00C144H
IF2MSK21 [R/W]
11111111 11111111
IF2MSK11 [R/W]
11111111 11111111
00C148H
IF2ARB21 [R/W]
00000000 00000000
IF2ARB11 [R/W]
00000000 00000000
00C14CH
IF2MCTR1 [R/W]
00000000 00000000
Reserved
00C150H
IF2DTA11 [R/W]
00000000 00000000
IF2DTA21 [R/W]
00000000 00000000
00C154H
IF2DTB11 [R/W]
00000000 00000000
IF2DTB21 [R/W]
00000000 00000000
00C158H
to 00C15CH
CAN 1
IF 2 Register
Reserved
00C160H
IF2DTA21 [R/W]
00000000 00000000
IF2DTA11 [R/W]
00000000 00000000
00C164H
IF2DTB21 [R/W]
00000000 00000000
IF2DTB11 [R/W]
00000000 00000000
00C168H
to 00C17CH
Reserved
00C180H
TREQR21 [R]
00000000 00000000
TREQR11 [R]
00000000 00000000
00C184H to
00C18CH
Reserved
Reserved
00C190H
NEWDT21 [R]
00000000 00000000
NEWDT11 [R]
00000000 00000000
00C194H to
00C19CH
Reserved
Reserved
00C1A0H
INTPND21 [R]
00000000 00000000
INTPND11 [R]
00000000 00000000
00C1A4H to
00C1ACH
Reserved
Reserved
00C1B0H
MSGVAL21 [R]
00000000 00000000
MSGVAL11 [R]
00000000 00000000
00C1B4H to
00C1FCH
Reserved
Reserved
00C200H
CTRLR2 [R/W]
00000000 00000001
STATR2 [R/W]
00000000 00000000
00C204H
ERRCNT2 [R]
00000000 00000000
BTR2 [R/W]
00100011 00000001
00C208H
INTR2 [R]
00000000 00000000
TESTR2 [R/W]
00000000 X0000000
00C20CH
BRPE2 [R/W]
00000000 00000000
CBSYNC2
Document Number: 002-04608 Rev. *C
CAN 1
Status Flags
CAN 2
Control Register
Page 74 of 127
CY91460B Series
Address
Register
+0
+1
Block
+2
+3
00C210H
IF1CREQ2 [R/W]
00000000 00000001
IF1CMSK2 [R/W]
00000000 00000000
00C214H
IF1MSK22 [R/W]
11111111 11111111
IF1MSK12 [R/W]
11111111 11111111
00C218H
IF1ARB22 [R/W]
00000000 00000000
IF1ARB12 [R/W]
00000000 00000000
00C21CH
IF1MCTR2 [R/W]
00000000 00000000
Reserved
00C220H
IF1DTA12 [R/W]
00000000 00000000
IF1DTA22 [R/W]
00000000 00000000
00C224H
IF1DTB12 [R/W]
00000000 00000000
IF1DTB22 [R/W]
00000000 00000000
00C228H
to 00C22CH
CAN 2
IF 1 Register
Reserved
00C230H
IF1DTA22 [R/W]
00000000 00000000
IF1DTA12 [R/W]
00000000 00000000
00C234H
IF1DTB22 [R/W]
00000000 00000000
IF1DTB12 [R/W]
00000000 00000000
00C238H
to
00C23CH
Reserved
00C240H
IF2CREQ2 [R/W]
00000000 00000001
IF2CMSK2 [R/W]
00000000 00000000
00C244H
IF2MSK22 [R/W]
11111111 11111111
IF2MSK12 [R/W]
11111111 11111111
00C248H
IF2ARB22 [R/W]
00000000 00000000
IF2ARB12 [R/W]
00000000 00000000
00C24CH
IF2MCTR2 [R/W]
00000000 00000000
Reserved
00C250H
IF2DTA12 [R/W]
00000000 00000000
IF2DTA22 [R/W]
00000000 00000000
00C254H
IF2DTB12 [R/W]
00000000 00000000
IF2DTB22 [R/W]
00000000 00000000
00C258H
to 00C25CH
CAN 2
IF 2 Register
Reserved
00C260H
IF2DTA22 [R/W]
00000000 00000000
IF2DTA12 [R/W]
00000000 00000000
00C264H
IF2DTB22 [R/W]
00000000 00000000
IF2DTB12 [R/W]
00000000 00000000
00C268H
to 00C27CH
Document Number: 002-04608 Rev. *C
Reserved
Page 75 of 127
CY91460B Series
Address
Register
+0
+1
Block
+2
+3
00C280H
TREQR22 [R]
00000000 00000000
TREQR12 [R]
00000000 00000000
00C284H to
00C28CH
Reserved
Reserved
00C290H
NEWDT22 [R]
00000000 00000000
NEWDT12 [R]
00000000 00000000
00C294H to
00C29CH
Reserved
Reserved
00C2A0H
INTPND22 [R]
00000000 00000000
INTPND12 [R]
00000000 00000000
00C2A4H to
00C2ACH
Reserved
Reserved
00C2B0H
MSGVAL22 [R]
00000000 00000000
MSGVAL12 [R]
00000000 00000000
00C2B4H to
00C2FCH
Reserved
Reserved
00C300H
CTRLR3 [R/W]
00000000 00000001
STATR3 [R/W]
00000000 00000000
00C304H
ERRCNT3 [R]
00000000 00000000
BTR3 [R/W]
00100011 00000001
00C308H
INTR3 [R]
00000000 00000000
TESTR3 [R/W]
00000000 X0000000
00C30CH
BRPE3 [R/W]
00000000 00000000
CBSYNC3
Document Number: 002-04608 Rev. *C
CAN 2
Status Flags
CAN 3
Control Register
Note: Not on
CY91F465BB/CY91F464
BB
Page 76 of 127
CY91460B Series
Address
Register
+0
+1
Block
+2
+3
00C310H
IF1CREQ3 [R/W]
00000000 00000001
IF1CMSK3 [R/W]
00000000 00000000
00C314H
IF1MSK23 [R/W]
11111111 11111111
IF1MSK13 [R/W]
11111111 11111111
00C318H
IF1ARB23 [R/W]
00000000 00000000
IF1ARB13 [R/W]
00000000 00000000
00C31CH
IF1MCTR3 [R/W]
00000000 00000000
Reserved
00C320H
IF1DTA13 [R/W]
00000000 00000000
IF1DTA23 [R/W]
00000000 00000000
00C324H
IF1DTB13 [R/W]
00000000 00000000
IF1DTB23 [R/W]
00000000 00000000
00C328H
to
00C32CH
Reserved
00C330H
IF1DTA23 [R/W]
00000000 00000000
IF1DTA13 [R/W]
00000000 00000000
00C334H
IF1DTB23 [R/W]
00000000 00000000
IF1DTB13 [R/W]
00000000 00000000
00C338H
to
00C33CH
CAN 3
IF 1 Register
Note: Not on
CY91F465BB/CY91F464
BB
Reserved
00C340H
IF2CREQ3 [R/W]
00000000 00000001
IF2CMSK3 [R/W]
00000000 00000000
00C344H
IF2MSK23 [R/W]
11111111 11111111
IF2MSK13 [R/W]
11111111 11111111
00C348H
IF2ARB23 [R/W]
00000000 00000000
IF2ARB13 [R/W]
00000000 00000000
00C34CH
IF2MCTR3 [R/W]
00000000 00000000
Reserved
00C350H
IF2DTA13 [R/W]
00000000 00000000
IF2DTA23 [R/W]
00000000 00000000
00C354H
IF2DTB13 [R/W]
00000000 00000000
IF2DTB23 [R/W]
00000000 00000000
00C358H
to
00C35CH
Reserved
00C360H
IF2DTA23 [R/W]
00000000 00000000
IF2DTA13 [R/W]
00000000 00000000
00C364H
IF2DTB23 [R/W]
00000000 00000000
IF2DTB13 [R/W]
00000000 00000000
00C368H
to
00C37CH
Document Number: 002-04608 Rev. *C
CAN 3
IF 2 Register
Note: Not on
CY91F465BB/CY91F464
BB
Reserved
Page 77 of 127
CY91460B Series
Address
Register
+0
00C380H
+1
00C390H
TREQR13 [R]
00000000 00000000
NEWDT23 [R]
00000000 00000000
NEWDT13 [R]
00000000 00000000
Reserved
INTPND23 [R]
00000000 00000000
00C3A4H to
00C3ACH
00C3B0H
+3
Reserved
00C394H to
00C39CH
00C3A0H
+2
TREQR23 [R]
00000000 00000000
00C384H to
00C38CH
Block
INTPND13 [R]
00000000 00000000
CAN 3
Status Flags
Note: Not on
CY91F465BB/CY91F464
BB
Reserved
MSGVAL23 [R]
00000000 00000000
00C3B4H
to 00C3FCH
MSGVAL13 [R]
00000000 00000000
Reserved
00C400H
CTRLR4 [R/W]
00000000 00000001
STATR4 [R/W]
00000000 00000000
00C404H
ERRCNT4 [R]
00000000 00000000
BTR4 [R/W]
00100011 00000001
00C408H
INTR4 [R]
00000000 00000000
TESTR4 [R/W]
00000000 X0000000
00C40CH
BRPE4 [R/W]
00000000 00000000
CBSYNC4
00C410H
IF1CREQ4 [R/W]
00000000 00000001
IF1CMSK4 [R/W]
00000000 00000000
00C414H
IF1MSK24 [R/W]
11111111 11111111
IF1MSK14 [R/W]
11111111 11111111
00C418H
IF1ARB24 [R/W]
00000000 00000000
IF1ARB14 [R/W]
00000000 00000000
00C41CH
IF1MCTR4 [R/W]
00000000 00000000
Reserved
00C420H
IF1DTA14 [R/W]
00000000 00000000
IF1DTA24 [R/W]
00000000 00000000
00C424H
IF1DTB14 [R/W]
00000000 00000000
IF1DTB24 [R/W]
00000000 00000000
00C428H
to
00C42CH
Reserved
00C430H
IF1DTA24 [R/W]
00000000 00000000
IF1DTA14 [R/W]
00000000 00000000
00C434H
IF1DTB24 [R/W]
00000000 00000000
IF1DTB14 [R/W]
00000000 00000000
00C438H
to
00C43CH
Document Number: 002-04608 Rev. *C
CAN 4
Control Register
Note: Not on
CY91F465BB/CY91F464
BB
CAN 4
IF 1 Register
Note: Not on
CY91F465BB/CY91F464
BB
Reserved
Page 78 of 127
CY91460B Series
Address
Register
+0
+1
Block
+2
+3
00C440H
IF2CREQ4 [R/W]
00000000 00000001
IF2CMSK4 [R/W]
00000000 00000000
00C444H
IF2MSK24 [R/W]
11111111 11111111
IF2MSK14 [R/W]
11111111 11111111
00C448H
IF2ARB24 [R/W]
00000000 00000000
IF2ARB14 [R/W]
00000000 00000000
00C44CH
IF2MCTR4 [R/W]
00000000 00000000
Reserved
00C450H
IF2DTA14 [R/W]
00000000 00000000
IF2DTA24 [R/W]
00000000 00000000
00C454H
IF2DTB14 [R/W]
00000000 00000000
IF2DTB24 [R/W]
00000000 00000000
00C458H
to
00C45CH
Reserved
00C460H
IF2DTA24 [R/W]
00000000 00000000
IF2DTA14 [R/W]
00000000 00000000
00C464H
IF2DTB24 [R/W]
00000000 00000000
IF2DTB14 [R/W]
00000000 00000000
00C468H
to
00C47CH
00C480H
TREQR24 [R]
00000000 00000000
NEWDT24 [R]
00000000 00000000
NEWDT14 [R]
00000000 00000000
Reserved
INTPND24 [R]
00000000 00000000
00C4A4H to
00C4ACH
00C4B0H
TREQR14 [R]
00000000 00000000
Reserved
00C494H to
00C49CH
00C4A0H
Note: Not on
CY91F465BB/CY91F464
BB
Reserved
00C484H to
00C48CH
00C490H
CAN 4
IF 2 Register
INTPND14 [R]
00000000 00000000
CAN 4
Status Flags
Note: Not on
CY91F465BB/CY91F464
BB
Reserved
MSGVAL24 [R]
00000000 00000000
00C4B4H
to 00C4FCH
MSGVAL14 [R]
00000000 00000000
Reserved
00C500H
CTRLR5 [R/W]
00000000 00000001
STATR5 [R/W]
00000000 00000000
00C504H
ERRCNT5 [R]
00000000 00000000
BTR5 [R/W]
00100011 00000001
00C508H
INTR5 [R]
00000000 00000000
TESTR5 [R/W]
00000000 X0000000
00C50CH
BRPE5 [R/W]
00000000 00000000
CBSYNC5
Document Number: 002-04608 Rev. *C
CAN 5
Control Register
Note: Not on
CY91F465BB/CY91F464
BB
Page 79 of 127
CY91460B Series
Address
Register
+0
+1
Block
+2
+3
00C510H
IF1CREQ5 [R/W]
00000000 00000001
IF1CMSK5 [R/W]
00000000 00000000
00C514H
IF1MSK25 [R/W]
11111111 11111111
IF1MSK15 [R/W]
11111111 11111111
00C518H
IF1ARB25 [R/W]
00000000 00000000
IF1ARB15 [R/W]
00000000 00000000
00C51CH
IF1MCTR5 [R/W]
00000000 00000000
Reserved
00C520H
IF1DTA15 [R/W]
00000000 00000000
IF1DTA25 [R/W]
00000000 00000000
00C524H
IF1DTB15 [R/W]
00000000 00000000
IF1DTB25 [R/W]
00000000 00000000
00C528H
to
00C52CH
Reserved
00C530H
IF1DTA25 [R/W]
00000000 00000000
IF1DTA15 [R/W]
00000000 00000000
00C534H
IF1DTB25 [R/W]
00000000 00000000
IF1DTB15 [R/W]
00000000 00000000
00C538H
to
00C53CH
CAN 5
IF 1 Register
Note: Not on
CY91F465BB/CY91F464
BB
Reserved
00C540H
IF2CREQ5 [R/W]
00000000 00000001
IF2CMSK5 [R/W]
00000000 00000000
00C544H
IF2MSK25 [R/W]
11111111 11111111
IF2MSK15 [R/W]
11111111 11111111
00C548H
IF2ARB25 [R/W]
00000000 00000000
IF2ARB15 [R/W]
00000000 00000000
00C54CH
IF2MCTR5 [R/W]
00000000 00000000
Reserved
00C550H
IF2DTA15 [R/W]
00000000 00000000
IF2DTA25 [R/W]
00000000 00000000
00C554H
IF2DTB15 [R/W]
00000000 00000000
IF2DTB25 [R/W]
00000000 00000000
00C558H
to
00C55CH
Reserved
00C560H
IF2DTA25 [R/W]
00000000 00000000
IF2DTA15 [R/W]
00000000 00000000
00C564H
IF2DTB25 [R/W]
00000000 00000000
IF2DTB15 [R/W]
00000000 00000000
00C568H
to
00C57CH
Document Number: 002-04608 Rev. *C
CAN 5
IF 2 Register
Note: Not on
CY91F465BB/CY91F464
BB
Reserved
Page 80 of 127
CY91460B Series
Address
Register
+0
00C580H
+1
00C590H
TREQR15 [R]
00000000 00000000
NEWDT25 [R]
00000000 00000000
NEWDT15 [R]
00000000 00000000
CAN 5
Status Flags
Reserved
INTPND25 [R]
00000000 00000000
00C5A4H to
00C5ACH
00C5B0H
+3
Reserved
00C594H to
00C59CH
00C5A0H
+2
TREQR25 [R]
00000000 00000000
00C584H to
00C58CH
Block
INTPND15 [R]
00000000 00000000
Reserved
MSGVAL25 [R]
00000000 00000000
00C5B4H
to
00EFFCH
Note: Not on
CY91F465BB/CY91F464
BB
MSGVAL15 [R]
00000000 00000000
Reserved
00F000H
BCTRL [R/W]
- - - - - - - - - - - - - - - - 11111100 00000000
00F004H
BSTAT [R/W]
- - - - - - - - - - - - - 000 00000000 10 - - 000000
00F008H
BIAC [R]
- - - - - - - - - - - - - - - - 00000000 00000000
00F00CH
BOAC [R]
- - - - - - - - - - - - - - - - 00000000 00000000
00F010H
BIRQ [R/W]
- - - - - - - - - - - - - - - - 00000000 00000000
00F014H
to 00F01CH
Reserved
00F020H
BCR0 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F024H
BCR1 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F028H
BCR2 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F02CH
BCR3 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F030H to
00F07CH
Reserved
Document Number: 002-04608 Rev. *C
EDSU / MPU
Reserved
Page 81 of 127
CY91460B Series
Address
Register
+0
+1
Block
+2
+3
00F080H
BAD0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F084H
BAD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F088H
BAD2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F08CH
BAD3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F090H
BAD4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F094H
BAD5 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F098H
BAD6 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F09CH
BAD7 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A0H
BAD8 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A4H
BAD9 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A8H
BAD10 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0ACH
BAD11 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B0H
BAD12 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B4H
BAD13 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B8H
BAD14 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0BCH
BAD15 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0C0H to
01FFFCH
Reserved
EDSU / MPU
020000H
to 02FFFCH
D-RAM size is 24 Kbytes : 02A000H - 02FFFCH
(data access is 0 wait cycles)
D-RAM area
030000H
to 03FFFCH
ID-RAM size is 16 Kbytes : 030000H - 033FFCH
(instruction access is 0 wait cycles, data access is 1 wait cycle)
ID-RAM area
EDSU / MPU
1. depends on the number of available CAN channels
2. ACR0 [11 : 10] depends on Mode vector fetch information on bus width
3. TCR [3 : 0] INIT value = 0000, keeps value after RST
Document Number: 002-04608 Rev. *C
Page 82 of 127
CY91460B Series
12.2
Flash Memory and External Bus Area
12.2.1 CY91F467BA/466BA
64bit read
dat[63:0]
32bit read/write
16bit read/write
Address
dat[31:0]
dat[31:16]
dat[31:0]
dat[15:0]
dat[31:16]
dat[15:0]
Register
+0
+1
+2
+3
+4
+5
+6
+7
Block
040000H to 05FFF8H
SA8 (64KB)
SA9 (64KB)
ROMS0
060000H to 07FFF8H
SA10 (64KB)
SA11 (64KB)
ROMS1
080000H to 09FFF8H
SA12 (64KB)
SA13 (64KB)
ROMS2
0A0000H to 0BFFF8H
SA14 (64KB)
SA15 (64KB)
ROMS3
0C0000H to 0DFFF8H
SA16 (64KB)
SA17 (64KB)
ROMS4
0E0000H to 0FFFF0H
SA18 (64KB)
SA19 (64KB)
0FFFF8H
FMV [R]
06 00 00 00H
FRV [R]
00 00 BF F8H
100000H to 11FFF8H
SA20 (64KB, CY91F467BA)
Reserved (CY91F466BA)
SA21 (64KB, CY91F467BA)
Reserved (CY91F466BA)
120000H to 13FFF8H
SA22 (64KB, CY91F467BA)
Reserved (CY91F466BA)
SA23 (64KB, CY91F467B)
Reserved (CY91F466BA)
140000H to 143FF8H
SA0 (8KB)
SA1 (8KB)
144000H to 17FF8H
SA2 (8KB)
SA3 (8KB)
148000H to 14BFF8H
SA4 (8KB)
SA5 (8KB)
14C000H to 14FFF8H
SA6 (8KB)
SA7 (8KB)
150000H to17FFF8H
Document Number: 002-04608 Rev. *C
ROMS5
ROMS6
ROMS7
Reserved
Page 83 of 127
CY91460B Series
64bit read
dat[63:0]
32bit read/write
16bit read/write
Address
dat[31:0]
dat[31:16]
dat[31:0]
dat[15:0]
dat[31:16]
dat[15:0]
Register
+0
+1
+2
+3
+4
+5
+6
+7
Block
180000H
to
1BFFF8H
ROMS8
1C0000H
to
1FFFF8H
ROMS9
200000H
to
27FFF8H
ROMS10
280000H
to
2FFFF8H
ROMS11
300000H
to
37FFF8H
External Bus Area
ROMS12
380000H
to
3FFFF8H
ROMS13
400000H
to
47FFF8H
ROMS14
480000H
to
4FFFF8H
ROMS15
Notes: Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown
above will be read.
Document Number: 002-04608 Rev. *C
Page 84 of 127
CY91460B Series
12.2.2 CY91F465BB/464BB
32bit read
16bit read/write
Address
dat[31:0]
dat[31:16]
dat[31:0]
dat[15:0]
dat[31:16]
dat[15:0]
Register
+0
+1
+2
+3
+4
+5
+6
+7
Block
040000H to 05FFF8H
Reserved
Reserved
ROMS0
060000H to 07FFF8H
Reserved
Reserved
ROMS1
080000H to 09FFF8H
SA12 (64KB)
Reserved (CY91F464BB)
SA13 (64KB)
Reserved (CY91F464BB)
ROMS2
0A0000H to 0BFFF8H
SA14 (64KB)
SA15 (64KB)
ROMS3
0C0000H to 0DFFF8H
SA16 (64KB)
SA17 (64KB)
ROMS4
0E0000H to 0FFFF0H
SA18 (64KB)
SA19 (64KB)
0FFFF8H
FMV [R]
06 00 00 00H
FRV [R]
00 00 BF F8H
100000H to 11FFF8H
External Bus Area
120000H to 13FFF8H
140000H to 143FF8H
ROMS6
External Bus Area
144000H to 17FF8H
148000H to 14BFF8H
SA4 (8KB)
SA5 (8KB)
14C000H to 14FFF8H
SA6 (8KB)
SA7 (8KB)
150000H to17FFF8H
Document Number: 002-04608 Rev. *C
ROMS5
ROMS7
Reserved
Page 85 of 127
CY91460B Series
32bit read/write
16bit read/write
Address
dat[31:0]
dat[31:16]
dat[31:0]
dat[15:0]
dat[31:16]
dat[15:0]
Register
+0
+1
+2
+3
+4
+5
+6
+7
Block
180000H
to
1BFFF8H
ROMS8
1C0000H
to
1FFFF8H
ROMS9
200000H
to
27FFF8H
ROMS10
280000H
to
2FFFF8H
ROMS11
300000H
to
37FFF8H
External Bus Area
ROMS12
380000H
to
3FFFF8H
ROMS13
400000H
to
47FFF8H
ROMS14
480000H
to
4FFFF8H
ROMS15
Notes: Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown
above will be read. On CY91F465BB/F464BB, write access to the flash is only possible in 16-bit mode.
Document Number: 002-04608 Rev. *C
Page 86 of 127
CY91460B Series
13. Interrupt Vector Table
Interrupt number
Interrupt
Reset
HexaDecimal Decimal
0
00
Interrupt Level [1]
Interrupt Vector [2]
DMA
Resource
Number
Setting
Register
Register
Address
Offset
Default Vector
Address
—
—
3FCH
000FFFFCH
—
Mode vector
1
01
—
—
3F8H
000FFFF8H
—
System reserved
2
02
—
—
3F4H
000FFFF4H
—
System reserved
3
03
—
—
3F0H
000FFFF0H
—
System reserved
4
04
—
—
3ECH
000FFFECH
—
CPU supervisor mode
(INT #5 instruction) [5]
5
05
—
—
3E8H
000FFFE8H
—
Memory Protection exception [5]
6
06
—
—
3E4H
000FFFE4H
—
System reserved
7
07
—
—
3E0H
000FFFE0H
—
System reserved
8
08
—
—
3DCH
000FFFDCH
—
System reserved
9
09
—
—
3D8H
000FFFD8H
—
System reserved
10
0A
—
—
3D4H
000FFFD4H
—
System reserved
11
0B
—
—
3D0H
000FFFD0H
—
System reserved
12
0C
—
—
3CCH
000FFFCCH
—
System reserved
13
0D
—
—
3C8H
000FFFC8H
—
Undefined instruction
exception
14
0E
—
—
3C4H
000FFFC4H
—
NMI request
15
0F
External Interrupt 0
16
10
External Interrupt 1
17
11
External Interrupt 2
18
12
External Interrupt 3
19
13
External Interrupt 4
20
14
External Interrupt 5
21
15
External Interrupt 6
22
16
External Interrupt 7
23
17
External Interrupt 8
24
18
External Interrupt 9
25
19
External Interrupt 10
26
1A
External Interrupt 11
27
1B
External Interrupt 12
28
1C
External Interrupt 13
29
1D
External Interrupt 14
30
1E
External Interrupt 15
31
1F
Reload Timer 0
32
20
Reload Timer 1
33
21
Reload Timer 2
34
22
Reload Timer 3
35
23
Document Number: 002-04608 Rev. *C
FH fixed
ICR00
440H
ICR01
441H
ICR02
442H
ICR03
443H
ICR04
444H
ICR05
445H
ICR06
446H
ICR07
447H
ICR08
448H
ICR09
449H
3C0H
000FFFC0H
—
3BCH
000FFFBCH
0, 16
3B8H
000FFFB8H
1, 17
3B4H
000FFFB4H
2, 18
3B0H
000FFFB0H
3, 19
3ACH
000FFFACH
20
3A8H
000FFFA8H
21
3A4H
000FFFA4H
22
3A0H
000FFFA0H
23
39CH
000FFF9CH
—
398H
000FFF98H
—
394H
000FFF94H
—
390H
000FFF90H
—
38CH
000FFF8CH
—
388H
000FFF88H
—
384H
000FFF84H
—
380H
000FFF80H
—
37CH
000FFF7CH
4, 32
378H
000FFF78H
5, 33
374H
000FFF74H
34
370H
000FFF70H
35
Page 87 of 127
CY91460B Series
Interrupt number
Interrupt
Reload Timer 4
HexaDecimal Decimal
36
24
Reload Timer 5
37
25
Reload Timer 6
38
26
Reload Timer 7
39
27
Free Run Timer 0
40
28
Free Run Timer 1
41
29
Free Run Timer 2
42
2A
Free Run Timer 3
43
2B
Free Run Timer 4
44
2C
Free Run Timer 5
45
2D
Free Run Timer 6
46
2E
Free Run Timer 7
47
2F
CAN 0
48
30
CAN 1
49
31
CAN 2
50
32
CAN 3
Not on CY91F465BB/464BB
51
33
CAN 4
Not on CY91F465BB/464BB
52
34
CAN 5
Not on CY91F465BB/464BB
53
35
LIN-USART 0 RX
54
36
LIN-USART 0 TX
55
37
Reserved
56
38
Reserved
57
39
LIN-USART 2 RX
58
3A
LIN-USART 2 TX
59
3B
LIN-USART 3 RX
60
3C
LIN-USART 3 TX
61
3D
System Reserved
62
3E
63
3F
Delayed Interrupt
[4]
64
40
System Reserved [4]
65
41
LIN-USART (FIFO) 4 RX
66
42
LIN-USART (FIFO) 4 TX
67
43
LIN-USART (FIFO) 5 RX
68
44
LIN-USART (FIFO) 5 TX
69
45
LIN-USART (FIFO) 6 RX
70
46
LIN-USART (FIFO) 6 TX
71
47
System Reserved
LIN-USART (FIFO) 7 RX
72
48
LIN-USART (FIFO) 7 TX
73
49
Document Number: 002-04608 Rev. *C
Interrupt Level [1]
Setting
Register
Register
Address
ICR10
44AH
ICR11
44BH
ICR12
44CH
ICR13
44DH
ICR14
44EH
ICR15
44FH
ICR16
450H
ICR17
451H
ICR18
452H
ICR19
453H
ICR20
454H
ICR21
455H
ICR22
456H
ICR23 *3
457H
ICR24
458H
ICR25
459H
ICR26
45AH
ICR27
45BH
ICR28
45CH
Interrupt Vector [2]
DMA
Resource
Number
Offset
Default Vector
Address
36CH
000FFF6CH
36
368H
000FFF68H
37
364H
000FFF64H
38
360H
000FFF60H
39
35CH
000FFF5CH
40
358H
000FFF58H
41
354H
000FFF54H
42
350H
000FFF50H
43
34CH
000FFF4CH
44
348H
000FFF48H
45
344H
000FFF44H
46
340H
000FFF40H
47
33CH
000FFF3CH
—
338H
000FFF38H
—
334H
000FFF34H
—
330H
000FFF30H
—
32CH
000FFF2CH
—
328H
000FFF28H
—
324H
000FFF24H
6, 48
320H
000FFF20H
7, 49
31CH
000FFF1CH
8, 50
318H
000FFF18H
9, 51
314H
000FFF14H
52
310H
000FFF10H
53
30CH
000FFF0CH
54
308H
000FFF08H
55
304H
000FFF04H
—
300H
000FFF00H
—
2FCH
000FFEFCH
—
2F8H
000FFEF8H
—
2F4H
000FFEF4H
10, 56
2F0H
000FFEF0H
11, 57
2ECH
000FFEECH
12, 58
2E8H
000FFEE8H
13, 59
2E4H
000FFEE4H
60
2E0H
000FFEE0H
61
2DCH
000FFEDCH
62
2D8H
000FFED8H
63
Page 88 of 127
CY91460B Series
Interrupt number
Interrupt
I2 C 0
2
HexaDecimal Decimal
74
4A
I C1
75
4B
Reserved
76
4C
Reserved
77
4D
Reserved
78
4E
Reserved
79
4F
Reserved
80
50
Reserved
81
51
Reserved
82
52
Reserved
83
53
Reserved
84
54
Reserved
85
55
Reserved
86
56
Reserved
87
57
Reserved
88
58
Reserved
89
59
Reserved
90
5A
Reserved
91
5B
Input Capture 0
92
5C
Input Capture 1
93
5D
Input Capture 2
94
5E
Input Capture 3
95
5F
Input Capture 4
96
60
Input Capture 5
97
61
Input Capture 6
98
62
Input Capture 7
99
63
Output Compare 0
100
64
Output Compare 1
101
65
Output Compare 2
102
66
Output Compare 3
103
67
Output Compare 4
104
68
Output Compare 5
105
69
Output Compare 6
106
6A
Output Compare 7
107
6B
Sound Generator
108
6C
Reserved
109
6D
System Reserved
110
6E
System Reserved
111
6F
PPG 0
112
70
PPG 1
113
71
Document Number: 002-04608 Rev. *C
Interrupt Level [1]
Setting
Register
Register
Address
ICR29
45DH
ICR30
45EH
ICR31
45FH
ICR32
460H
ICR33
461H
ICR34
462H
ICR35
463H
ICR36
464H
ICR37
465H
ICR38
466H
ICR39
467H
ICR40
468H
ICR41
469H
ICR42
46AH
ICR43
46BH
ICR44
46CH
ICR45
46DH
ICR46
46EH
ICR47 [3]
46FH
ICR48
470H
Interrupt Vector [2]
Offset
Default Vector
Address
2D4H
000FFED4H
DMA
Resource
Number
—
2D0H
000FFED0H
—
2CCH
000FFECCH
64
2C8H
000FFEC8H
65
2C4H
000FFEC4H
66
2C0H
000FFEC0H
67
2BCH
000FFEBCH
68
2B8H
000FFEB8H
69
2B4H
000FFEB4H
70
2B0H
000FFEB0H
71
2ACH
000FFEACH
72
2A8H
000FFEA8H
73
2A4H
000FFEA4H
74
2A0H
000FFEA0H
75
29CH
000FFE9CH
76
298H
000FFE98H
77
294H
000FFE94H
78
290H
000FFE90H
79
28CH
000FFE8CH
80
288H
000FFE88H
81
284H
000FFE84H
82
280H
000FFE80H
83
27CH
000FFE7CH
84
278H
000FFE78H
85
274H
000FFE74H
86
270H
000FFE70H
87
26CH
000FFE6CH
88
268H
000FFE68H
89
264H
000FFE64H
90
260H
000FFE60H
91
25CH
000FFE5CH
92
258H
000FFE58H
93
254H
000FFE54H
94
250H
000FFE50H
95
24CH
000FFE4CH
—
248H
000FFE48H
—
244H
000FFE44H
—
240H
000FFE40H
—
23CH
000FFE3CH
15, 96
238H
000FFE38H
97
Page 89 of 127
CY91460B Series
Interrupt number
Interrupt
HexaDecimal Decimal
PPG 2
114
72
PPG 3
115
73
PPG 4
116
74
PPG 5
117
75
PPG 6
118
76
PPG 7
119
77
PPG 8
120
78
PPG 9
121
79
PPG 10
122
7A
PPG 11
123
7B
PPG 12
124
7C
PPG 13
125
7D
PPG 14
126
7E
PPG 15
127
7F
Up/Down Counter 0
128
80
Up/Down Counter 1
129
81
Reserved
130
82
Reserved
131
83
Real Time Clock
132
84
Calibration Unit
133
85
A/D Converter 0
134
86
System reserved
135
87
Alarm Comparator 0
136
88
Reserved
137
89
Low Voltage Detection
138
8A
Reserved
139
8B
Interrupt Level [1]
Setting
Register
Register
Address
ICR49
471H
ICR50
472H
ICR51
473H
ICR52
474H
ICR53
475H
ICR54
476H
ICR55
477H
ICR56
478H
ICR57
479H
ICR58
47AH
ICR59
47BH
ICR60
47CH
ICR61
47DH
ICR62
47EH
ICR63
47FH
Interrupt Vector [2]
Offset
Default Vector
Address
234H
000FFE34H
DMA
Resource
Number
98
230H
000FFE30H
99
22CH
000FFE2CH
100
228H
000FFE28H
101
224H
000FFE24H
102
220H
000FFE20H
103
21CH
000FFE1CH
104
218H
000FFE18H
105
214H
000FFE14H
106
210H
000FFE10H
107
20CH
000FFE0CH
108
208H
000FFE08H
109
204H
000FFE04H
110
200H
000FFE00H
111
1FCH
000FFDFCH
—
1F8H
000FFDF8H
—
1F4H
000FFDF4H
—
1F0H
000FFDF0H
—
1ECH
000FFDECH
—
1E8H
000FFDE8H
—
1E4H
000FFDE4H
14, 112
1E0H
000FFDE0H
—
1DCH
000FFDDCH
—
1D8H
000FFDD8H
—
1D4H
000FFDD4H
—
1D0H
000FFDD0H
—
1CCH
000FFDCCH
—
1C8H
000FFDC8H
—
1C4H
000FFDC4H
—
Time base Overflow
140
8C
PLL Clock Gear
141
8D
DMA Controller
142
8E
Main/Sub OSC stability wait
143
8F
1C0H
000FFDC0H
—
Security vector
144
90
—
—
1BCH
000FFDBCH
—
Used by the INT
instruction.
145
to
255
91
to
FF
—
—
1B8H to
000H
000FFDB8H
to
000FFC00H
—
1. The Interrupt Control Registers (ICRs) are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is provided
for each interrupt request.
2. The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (TBR) . The
TBR specifies the top of the EIT vector table. The addresses listed in the table are for the default TBR value (000FFC00H) . The TBR is initialized
to this value by a reset. The TBR is set to 000FFC00H after the internal boot ROM is executed.
3. ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0])
4. Used by REALOS
5. Memory Protection Unit (MPU) support
Document Number: 002-04608 Rev. *C
Page 90 of 127
CY91460B Series
14. Recommended Settings
14.1
PLL and Clock Gear Settings
Please note that for CY91F467BA/466BA and CY91F465BB/464BB the core base clock frequencies are valid in the 1.8V operation
mode of the Main regulator and Flash.
Table 7. Recommended PLL Divider and Clock Gear Settings
PLL
Input (CLK)
[MHz]
Frequency Parameter
Clock Gear Parameter
PLL
Output (X)
[MHz]
Core Base
Clock
[MHz]
DIVM
DIVN
DIVG
MULG
4
2
25
16
24
200
100
4
2
24
16
24
192
96
4
2
23
16
24
184
92
4
2
22
16
24
176
88
4
2
21
16
20
168
84
4
2
20
16
20
160
80
4
2
19
16
20
152
76
4
2
18
16
20
144
72
4
2
17
16
16
136
68
4
2
16
16
16
128
64
4
2
15
16
16
120
60
4
2
14
16
16
112
56
4
2
13
16
12
104
52
4
2
12
16
12
96
48
4
2
11
16
12
88
44
4
4
10
16
24
160
40
4
4
9
16
24
144
36
4
4
8
16
24
128
32
4
4
7
16
24
112
28
4
6
6
16
24
144
24
4
8
5
16
28
160
20
4
10
4
16
32
160
16
4
12
3
16
32
144
12
Document Number: 002-04608 Rev. *C
Remarks
MULG
Not on
CY91F467BA/466BA
Page 91 of 127
CY91460B Series
14.2
Clock Modulator settings
The following table shows all possible settings for the Clock Modulator in a base clock frequency range from 32MHz up to 88MHz.
The Flash access time settings need to be adjusted according to Fmax while the PLL and clock gear settings should be set
according to base clock frequency.
Table 8. Clock Modulator Settings, Frequency Range and Supported Supply Voltage
Modulation
Random No
CMPR
Baseclk
Fmin
Degree
(N)
[hex]
[MHz]
[MHz]
(k)
Fmax
[MHz]
1
3
026F
88
79.5
98.5
Not on CY91F467BA/466BA
1
3
026F
84
76.1
93.8
1
3
026F
80
72.6
89.1
1
5
02AE
80
68.7
95.8
2
3
046E
80
68.7
95.8
1
3
026F
76
69.1
84.5
1
5
02AE
76
65.3
90.8
1
7
02ED
76
62
98.1
Not on CY91F467BA/466BA
2
3
046E
76
65.3
90.8
3
3
066D
76
62
98.1
Not on CY91F467BA/466BA
1
3
026F
72
65.5
79.9
1
5
02AE
72
62
85.8
1
7
02ED
72
58.8
92.7
2
3
046E
72
62
85.8
3
3
066D
72
58.8
92.7
1
3
026F
68
62
75.3
1
5
02AE
68
58.7
80.9
1
7
02ED
68
55.7
87.3
1
9
032C
68
53
95
2
3
046E
68
58.7
80.9
2
5
04AC
68
53
95
3
3
066D
68
55.7
87.3
4
3
086C
68
53
95
1
3
026F
64
58.5
70.7
1
5
02AE
64
55.3
75.9
1
7
02ED
64
52.5
82
1
9
032C
64
49.9
89.1
1
11
036B
64
47.6
97.6
Not on CY91F467BA/466BA
2
3
046E
64
55.3
75.9
2
5
04AC
64
49.9
89.1
3
3
066D
64
52.5
82
4
3
086C
64
49.9
89.1
Document Number: 002-04608 Rev. *C
Page 92 of 127
CY91460B Series
Modulation
Degree
(k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
5
3
0A6B
64
47.6
97.6
Not on CY91F467BA/466BA
1
3
026F
60
54.9
66.1
1
5
02AE
60
51.9
71
1
7
02ED
60
49.3
76.7
1
9
032C
60
46.9
83.3
1
11
036B
60
44.7
91.3
2
3
046E
60
51.9
71
2
5
04AC
60
46.9
83.3
3
3
066D
60
49.3
76.7
4
3
086C
60
46.9
83.3
5
3
0A6B
60
44.7
91.3
1
3
026F
56
51.4
61.6
1
5
02AE
56
48.6
66.1
1
7
02ED
56
46.1
71.4
1
9
032C
56
43.8
77.6
1
11
036B
56
41.8
84.9
1
13
03AA
56
39.9
93.8
2
3
046E
56
48.6
66.1
2
5
04AC
56
43.8
77.6
2
7
04EA
56
39.9
93.8
3
3
066D
56
46.1
71.4
3
5
06AA
56
39.9
93.8
4
3
086C
56
43.8
77.6
5
3
0A6B
56
41.8
84.9
6
3
0C6A
56
39.9
93.8
1
3
026F
52
47.8
57
1
5
02AE
52
45.2
61.2
1
7
02ED
52
42.9
66.1
1
9
032C
52
40.8
71.8
1
11
036B
52
38.8
78.6
1
13
03AA
52
37.1
86.8
1
15
03E9
52
35.5
96.9
Not on CY91F467BA/466BA
2
3
046E
52
45.2
61.2
2
5
04AC
52
40.8
71.8
2
7
04EA
52
37.1
86.8
3
3
066D
52
42.9
66.1
3
5
06AA
52
37.1
86.8
4
3
086C
52
40.8
71.8
Document Number: 002-04608 Rev. *C
Page 93 of 127
CY91460B Series
Modulation
Degree
(k)
Random No
(N)
5
6
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
3
0A6B
52
38.8
78.6
3
0C6A
52
37.1
86.8
7
3
0E69
52
35.5
96.9
Not on CY91F467BA/466BA
1
3
026F
48
44.2
52.5
1
5
02AE
48
41.8
56.4
1
7
02ED
48
39.6
60.9
1
9
032C
48
37.7
66.1
1
11
036B
48
35.9
72.3
1
13
03AA
48
34.3
79.9
1
15
03E9
48
32.8
89.1
2
3
046E
48
41.8
56.4
2
5
04AC
48
37.7
66.1
2
7
04EA
48
34.3
79.9
3
3
066D
48
39.6
60.9
3
5
06AA
48
34.3
79.9
4
3
086C
48
37.7
66.1
5
3
0A6B
48
35.9
72.3
6
3
0C6A
48
34.3
79.9
7
3
0E69
48
32.8
89.1
1
3
026F
44
40.6
48.1
1
5
02AE
44
38.4
51.6
1
7
02ED
44
36.4
55.7
1
9
032C
44
34.6
60.4
1
11
036B
44
33
66.1
1
13
03AA
44
31.5
73
1
15
03E9
44
30.1
81.4
2
3
046E
44
38.4
51.6
2
5
04AC
44
34.6
60.4
2
7
04EA
44
31.5
73
2
9
0528
44
28.9
92.1
3
3
066D
44
36.4
55.7
3
5
06AA
44
31.5
73
4
3
086C
44
34.6
60.4
4
5
08A8
44
28.9
92.1
5
3
0A6B
44
33
66.1
6
3
0C6A
44
31.5
73
7
3
0E69
44
30.1
81.4
8
3
1068
44
28.9
92.1
1
3
026F
40
37
43.6
Document Number: 002-04608 Rev. *C
Fmax
[MHz]
Page 94 of 127
CY91460B Series
Modulation
Degree
(k)
Random No
(N)
1
1
CMPR
[hex]
Baseclk
[MHz]
5
02AE
40
34.9
46.8
7
02ED
40
33.1
50.5
1
9
032C
40
31.5
54.8
1
11
036B
40
30
59.9
1
13
03AA
40
28.7
66.1
1
15
03E9
40
27.4
73.7
2
3
046E
40
34.9
46.8
2
5
04AC
40
31.5
54.8
2
7
04EA
40
28.7
66.1
2
9
0528
40
26.3
83.3
3
3
066D
40
33.1
50.5
3
5
06AA
40
28.7
66.1
3
7
06E7
40
25.3
95.8
4
3
086C
40
31.5
54.8
4
5
08A8
40
26.3
83.3
5
3
0A6B
40
30
59.9
6
3
0C6A
40
28.7
66.1
7
3
0E69
40
27.4
73.7
8
3
1068
40
26.3
83.3
9
3
1267
40
25.3
95.8
1
3
026F
36
33.3
39.2
1
5
02AE
36
31.5
42
1
7
02ED
36
29.9
45.3
1
9
032C
36
28.4
49.2
1
11
036B
36
27.1
53.8
1
13
03AA
36
25.8
59.3
1
15
03E9
36
24.7
66.1
2
3
046E
36
31.5
42
2
5
04AC
36
28.4
49.2
2
7
04EA
36
25.8
59.3
2
9
0528
36
23.7
74.7
3
3
066D
36
29.9
45.3
3
5
06AA
36
25.8
59.3
3
7
06E7
36
22.8
85.8
4
3
086C
36
28.4
49.2
4
5
08A8
36
23.7
74.7
5
3
0A6B
36
27.1
53.8
6
3
0C6A
36
25.8
59.3
7
3
0E69
36
24.7
66.1
8
3
1068
36
23.7
74.7
Document Number: 002-04608 Rev. *C
Fmin
[MHz]
Fmax
[MHz]
Page 95 of 127
CY91460B Series
Modulation
Degree
(k)
Random No
(N)
9
1
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
3
1267
36
22.8
85.8
3
026F
32
29.7
34.7
1
5
02AE
32
28
37.3
1
7
02ED
32
26.6
40.2
1
9
032C
32
25.3
43.6
1
11
036B
32
24.1
47.7
1
13
03AA
32
23
52.5
1
15
03E9
32
22
58.6
2
3
046E
32
28
37.3
2
5
04AC
32
25.3
43.6
2
7
04EA
32
23
52.5
2
9
0528
32
21.1
66.1
2
11
0566
32
19.5
89.1
3
3
066D
32
26.6
40.2
3
5
06AA
32
23
52.5
3
7
06E7
32
20.3
75.9
4
3
086C
32
25.3
43.6
4
5
08A8
32
21.1
66.1
5
3
0A6B
32
24.1
47.7
5
5
0AA6
32
19.5
89.1
6
3
0C6A
32
23
52.5
7
3
0E69
32
22
58.6
8
3
1068
32
21.1
66.1
9
3
1267
32
20.3
75.9
10
3
1466
32
19.5
89.1
Document Number: 002-04608 Rev. *C
Page 96 of 127
CY91460B Series
15. Electrical Characteristics
15.1
Absolute Maximum Ratings
Parameter
Symbol
Power supply slew rate
Power supply voltage 1[1]
Power supply voltage 2
[1]
Relationship of the supply voltages
Rating
Min
Max
Unit
Remarks
−
−
50
V/ms
VDD5R
− 0.3
+ 6.0
V
VDD5
− 0.3
+ 6.0
V
VDD5-0.3
VDD35-0.3
VDD5+0.3
VDD35+0.3
V
At least one pin of the Ports 26
to 29 (ANn) is used as digital
input or output.
VSS5-0.3
VDD35-0.3
VDD5+0.3
VDD35+0.3
V
All pins of the Ports 26 to 29
(ANn) follow the condition of VIA
AVCC5
Analog power supply voltage[1]
AVCC5
− 0.3
+ 6.0
V
[2]
Analog reference
power supply voltage[1]
AVRH
− 0.3
+ 6.0
V
[2]
VI1
Vss5 − 0.3
VDD5 + 0.3
V
VIA
AVss5 − 0.3
AVcc5 + 0.3
V
Input voltage 1[1]
Analog pin input
voltage[1]
1[1]
VO1
Vss5 − 0.3
VDD5 + 0.3
V
ICLAMP
− 4.0
+ 4.0
mA
[3]
Σ |ICLAMP|
−
20
mA
[3]
IOL
−
10
mA
IOLAV
−
8
mA
“L” level total maximum output current
ΣIOL
−
100
mA
“L” level total average output current[6]
ΣIOLAV
−
50
mA
IOH
−
− 10
mA
IOHAV
−
−4
mA
ΣIOH
−
− 100
mA
mA
Output voltage
Maximum clamp current
Total maximum clamp current
“L” level maximum output current[4]
“L” level average output current
[5]
“H” level maximum output current
“H” level average output
[4]
current[5]
“H” level total maximum output current
“H” level total average output current
[6]
ΣIOHAV
−
− 25
fmax, CLKB
−
100
fmax, CLKP
−
50
fmax, CLKT
−
50
fmax, CLKCAN
−
50
fmax, CLKB
−
96
fmax, CLKP
−
48
fmax, CLKT
−
48
fmax, CLKCAN
−
48
fmax, CLKB
−
96
fmax, CLKP
−
48
fmax, CLKT
−
48
fmax, CLKCAN
−
48
Permitted operating frequency
CY91F465BB/F464BB
Permitted operating frequency
CY91F465BB/F464BB
Permitted operating frequency
CY91F467BA/F466BA
Document Number: 002-04608 Rev. *C
MHz
TA ≤ 105 °C
MHz
TA ≤ 125 °C
MHz
TA ≤ 105 °C
Page 97 of 127
CY91460B Series
Parameter
Symbol
Min
Max
fmax, CLKB
−
92
fmax, CLKP
−
46
fmax, CLKT
−
46
fmax, CLKCAN
−
46
−
Permitted operating frequency
CY91F467BA/F466BA
Permitted power dissipation
Rating
[7]
Operating temperature
Storage temperature
Unit
Remarks
MHz
TA ≤ 125 °C
1200 *8
mW
TA ≤ 85 °C
−
600 *8
mW
TA ≤ 105 °C
−
1300 *8
mW
TA ≤ 105 °C, no Flash
program/erase [9]
−
1000 *8
mW
TA ≤ 115 °C, no Flash
program/erase [9]
−
750 *8
mW
TA ≤ 125 °C, no Flash
program/erase [9]
TA
− 40
+ 125
°C
Tstg
− 55
+ 150
°C
PD
1. The parameter is based on VSS5 = AVSS5 = 0.0 V.
2. AVCC5 and AVRH5 must not exceed VDD5 + 0.3 V.
3.
■ Use within recommended operating conditions.
■ Use with DC voltage (current).
■ +B signals are input signals that exceed the VDD5 voltage. +B signals should always be applied by connecting a limiting resistor between the +B
signal and the microcontroller.
■ The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed the rated value at any time, either
instantaneously or for an extended period, when the +B signal is input.
■ Note that when the microcontroller drive current is low, such as in the low power consumption modes, the +B input potential can increase the potential
at the power supply pin via a protective diode, possibly affecting other devices.
■ Note that if the +B signal is input when the microcontroller is off (not fixed at 0 V), power is supplied through the +B input pin; therefore, the
microcontroller may partially operate.
■ Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not function in the power supply
voltage.
■
Do not leave +B input pins open.
Figure 2. Example of Recommended Circuit :
Input/output equivalent circuit
Protective diode
VCC
Limiting
resistor
P-ch
+B input (0 V to 16 V)
N-ch
R
Document Number: 002-04608 Rev. *C
Page 98 of 127
CY91460B Series
4. Maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
5. Average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 100 ms period.
6. Total average output current is defined as the value of the average current flowing through all of the corresponding pins for a 100 ms period.
7. The maximum permitted power dissipation depends onm the ambient temperature, the air flow velocity and the thermal conductance of the package
on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = Σ (VOL * IOL + VOH + IOH) (IO load power dissipation, sum is performed on all IO ports)
PINT = VDD5R * ICC + AVCC5 * IA + AVRH5 * IR (internal power dissipation)
8. Worst case value for the QFP package mounted on a 4-layer PCB at specified TA without air flow.
9. Please contact Cypress for reliability limitations when using under these conditions.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-04608 Rev. *C
Page 99 of 127
CY91460B Series
15.2
Recommended Operating Conditions
(VSS5 = AVSS5 = 0.0 V)
Parameter
Power supply voltage
Smoothing capacitor at
VCC18C pin
Symbol
Max
VDD5
3.0
-
5.5
V
VDD5R
3.0
-
5.5
V
Internal regulator
AVCC5
3.0
-
5.5
V
A/D converter
CS
-
4.7
-
mF
-
-
50
V/ms
- 40
-
+ 125
°C
TA
10
0.6
Vsurge
2
fRC100kHz
fRC2MHz
50
1
Use a X7R ceramic capacitor or a
capacitor that has similar frequency
characteristics.
ms
Lock-up time PLL
(4 MHz ->16 ...100MHz)
RC Oscillator
Remarks
Typ
Main Oscillation
stabilisation time
ESD Protection
(Human body model)
Unit
Min
Power supply slew rate
Operating temperature
Value
100
2
200
4
ms
kV
Rdischarge = 1.5kW
Cdischarge = 100pF
kHz
MHz
VDDCORE ≥ 1.65V
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
VCC18C
VSS5
AVSS5
CS
Document Number: 002-04608 Rev. *C
Page 100 of 127
CY91460B Series
15.3
DC Characteristics
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 125 °C)
Parameter
Symbol
Pin Name
Condition
Value
Unit
Remarks
VDD + 0.3
V
CMOS hysteresis input
-
VDD + 0.3
V
4.5 V ? VDD ? 5.5 V
0.74 × VDD
-
VDD + 0.3
V
3 V ? VDD < 4.5 V
0.8 × VDD
-
VDD + 0.3
V
Min
Typ
Max
0.8 × VDD
-
0.7 × VDD
-
Port inputs if CMOS
Hysteresis 0.8/0.2
input is selected
-
Port inputs if CMOS
Hysteresis 0.7/0.3 input
is selected
-
AUTOMOTIVE
Hysteresis input is selected
-
Port inputs if TTL input is
selected
2.0
-
VDD + 0.3
V
VIHR
INITX
-
0.8 × VDD
-
VDD + 0.3
V
INITX input pin (CMOS
Hysteresis)
VIHM
MD_3 to MD_0
-
VDD - 0.3
-
VDD + 0.3
V
Mode input pins
VIHX0S
X0, X0A
-
2.5
-
VDD + 0.3
V
External clock in
“Oscillation mode”
VIHX0F
X0
-
0.8 × VDD
-
VDD + 0.3
V
External clock in “Fast
Clock Input mode”
-
Port inputs if CMOS
Hysteresis 0.8/0.2 input
is selected
VSS - 0.3
-
0.2 × VDD
V
-
Port inputs if CMOS
Hysteresis 0.7/0.3 input
is selected
VSS - 0.3
-
0.3 × VDD
V
VSS - 0.3
-
0.5 × VDD
V
4.5 V ≤ VDD ≤ 5.5 V
-
Port inputs if
AUTOMOTIVE
Hysteresis input is
selected
VSS - 0.3
-
0.46 × VDD
V
3 V ≤ VDD < 4.5 V
-
Port inputs if TTL input is
selected
VSS - 0.3
-
0.8
V
VILR
INITX
-
VSS - 0.3
-
0.2 × VDD
V
INITX input pin (CMOS
Hysteresis)
VILM
MD_3 to MD_0
-
VSS - 0.3
-
VSS + 0.3
V
Mode input pins
VILXDS
X0, X0A
-
VSS - 0.3
-
0.5
V
External clock in
“Oscillation mode”
VIH
Input “H”
voltage
VIL
Input “L”
voltage
Document Number: 002-04608 Rev. *C
Page 101 of 127
CY91460B Series
Parameter
Input “L”
voltage
Output “H”
voltage
Output “L“ voltage
Input leakage
current
Symbol
Pin
Name
Condition
VILXDF
X0
-
VOH2
Normal
outputs
VOH5
Normal
outputs
VOH3
I 2C
outputs
VOL2
Normal
outputs
VOL5
Normal
outputs
VOL3
I 2C
outputs
IIL
Pnn_m[1]
Analog input
leakage current
IAIN
Pull-up
resistance
RUP
Pnn_m [3]
INITX
Pull-down
resistance
RDOWN
Pnn_m [4]
Input
capacitance
CIN
ANn[2]
Value
Unit
Remarks
Min
Typ
Max
VSS - 0.3
-
0.2 × VDD
V
External clock in
“Fast Clock Input
mode”
VDD - 0.5
-
-
V
Driving strength set to
2 mA
VDD - 0.5
-
-
V
Driving strength set to
5 mA
VDD - 0.5
-
-
V
-
-
0.4
V
Driving strength set to
2 mA
-
-
0.4
V
Driving strength set to
5 mA
3.0V ≤ VDD ≤ 5.5V,
IOH = + 3mA
-
-
0.4
V
3.0V ≤ VDD ≤ 5.5V
VSS5 < VI < VDD
TA=25 °C
-1
-
+1
3.0V ≤ VDD ≤ 5.5V
VSS5 < VI < VDD
TA=125 °C
-3
-
+3
3.0V ≤ VDD ≤ 5.5V
TA=25 °C
-1
-
+1
μA
3.0V ≤ VDD ≤ 5.5V
TA=125 °C
-3
-
+3
μA
3.0V ≤ VDD ≤ 3.6V
40
100
160
4.5V ≤ VDD ≤ 5.5V
25
50
100
3.0V ≤ VDD ≤ 3.6V
40
100
180
4.5V ≤ VDD ≤ 5.5V
25
50
100
-
5
15
4.5V ≤ VDD ≤ 5.5V,
IOH = - 2mA
3.0V ≤ VDD ≤ 4.5V,
IOH = - 1.6mA
4.5V ≤ VDD ≤ 5.5V,
IOH = - 5mA
3.0V ≤ VDD ≤ 4.5V,
IOH = - 3mA
3.0V ≤ VDD ≤ 5.5V,
IOH = - 3mA
4.5V ≤ VDD ≤ 5.5V,
IOH = + 2mA
3.0V ≤ VDD ≤ 4.5V,
IOH = + 1.6mA
4.5V ≤ VDD ≤ 5.5V,
IOH = + 5mA
3.0V ≤ VDD ≤ 4.5V,
IOH = + 3mA
All except
VDD5,
VDD5R,
f = 1 MHz
VSS5,
AVCC5,
AVSS5,
AVRH5
Document Number: 002-04608 Rev. *C
μA
kΩ
kΩ
pF
Page 102 of 127
CY91460B Series
Parameter
Symbol
ICC
Power supply
current
F467BA
F466BA
ICCH
1.
2.
3.
4.
5.
Condition
VDD5R
VDD5R
Value
Min
Typ
Max
CLKB: 96 MHz
CLKP: 48 MHz
CLKT: 48 MHz
CLKCAN: 48 MHz
−
120
150
Unit
mA
TA = + 25 °C
−
30
150
μA
TA = + 105 °C
−
0.4
2.0
mA
TA = + 125 °C
−
1.0
5.0
mA
TA = + 25 °C
−
100
500
μA
TA = + 105 °C
−
0.5
2.4
mA
TA = + 125 °C
−
1.1
5.4
mA
TA = + 25 °C
−
50
250
μA
TA = + 105 °C
−
0.45
2.2
mA
TA = + 125 °C
−
1.05
5.2
mA
Remarks
Code fetch from
Flash
At stop mode [5]
RTC: 4 MHz mode [5]
RTC: 100 kHz mode
[5]
ILVE
VDD5
−
−
70
150
μA
External low voltage
detection
ILVI
VDD5R
−
−
50
100
μA
Internal low voltage
detection
IOSC
VDD5
−
−
250
500
μA
Main clock (4 MHz)
−
−
20
40
μA
Sub clock (32 kHz)
-
110
140
mA
Code fetch from
Flash
ICC
Power supply
current
F465BB
F464BB
Pin
Name
ICCH
VDD5R
VDD5R
CLKB: 100 MHz
CLKP: 50 MHz
CLKT: 50 MHz
CLKCAN: 50 MHz
TA = + 25 °C
-
30
150
μA
TA = + 105 °C
-
0.3
2.0
mA
TA = + 125 °C
-
0.75
5.0
mA
TA = + 25 °C
-
100
500
μA
TA = + 105 °C
-
0.5
2.4
mA
TA = + 125 °C
-
0.85
5.4
mA
TA = + 25 °C
-
50
250
μA
TA = + 105 °C
-
0.4
2.2
mA
TA = + 125 °C
-
0.8
5.2
mA
At stop mode [5]
RTC: 4 MHz mode [5]
RTC: 100 kHz
mode[5]
ILVE
VDD5
−
−
70
150
μA
External low voltage
detection
ILVI
VDD5R
−
−
50
100
μA
Internal low voltage
detection
IOSC
VDD5
-
-
250
500
μA
Main clock (4 MHz)
-
-
20
40
μA
Sub clock (32 kHz)
Pnn_m includes all GPIO pins. Analog (AN) channels and PullUp/PullDown are disabled.
ANn includes all pins where AN channels are enabled.
Pnn_m includes all GPIO pins. The pull up resistors must be enabled by PPER/PPCR setting and the pins must be in input direction.
Pnn_m includes all GPIO pins. The pull down resistors must be enabled by PPER/PPCR setting and the pins must be in input direction.
Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled.
Document Number: 002-04608 Rev. *C
Page 103 of 127
CY91460B Series
15.4
A/D Converter Characteristics
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 125 °C)
Parameter
Symbol Pin Name
Value
Unit
Min
Typ
Max
−
−
10
bit
Remarks
Resolution
−
−
Total error
−
−
−3
−
+3
LSB
Nonlinearity error
−
−
− 2.5
−
+ 2.5
LSB
Differential nonlinearity
error
−
−
− 1.9
−
+ 1.9
LSB
Zero reading voltage
VOT
ANn
AVRL−1.5 LSB
AVRL + 0.5 LSB
AVRL + 2.5 LSB
V
Full scale reading voltage
VFST
ANn
AVRH−3.5
LSB
AVRH−1.5 LSB
AVRH + 0.5 LSB
V
Compare time
Tcomp
−
0.6
−
16,500
μs
4.5 V ≤ AVCC5 ≤ 5.5 V
2.0
−
−
μs
3.0 V ≤ AVCC5 ≤ 4.5 V
0.4
−
−
μs
4.5 V ≤ AVCC5 ≤ 5.5 V,
REXT < 2 kΩ
1.0
−
−
μs
3.0 V ≤ AVCC5 ≤ 4.5 V,
REXT < 1 kΩ
1.0
−
−
μs
4.5 V ≤ AVCC5 ≤ 5.5 V
3.0
−
−
μs
3.0 V ≤ AVCC5 ≤ 4.5 V
−
−
11
pF
−
−
2.6
kΩ
4.5 V ≤ AVCC5 ≤ 5.5 V
−
−
12.1
kΩ
3.0 V ≤ AVCC5 ≤ 4.5 V
−1
−
+1
μA
TA = + 25 °C
−3
−
+3
μA
TA = + 125 °C
Sampling time
Tsamp
−
Tconv
−
Input capacitance
CIN
ANn
Input resistance
RIN
ANn
Analog input leakage
current
IAIN
ANn
Analog input voltage
range
VAIN
ANn
AVRL
−
AVRH
V
Offset between input
channels
−
ANn
−
−
4
LSB
Conversion time
Note: The accuracy gets worse as AVRH - AVRL becomes smaller
Document Number: 002-04608 Rev. *C
Page 104 of 127
CY91460B Series
Parameter
Reference voltage range
Symbol
Pin Name
AVRH
Value
Unit
Remarks
Min
Typ
Max
AVRH5
0.75 × AVCC5
-
AVCC5
AVRL
AVSS5
AVSS5
-
AVCC5 × 0.25
V
IA
AVCC5
-
2.5
5
mA
A/D Converter active
IAH
AVCC5
-
-
5
μA
A/D Converter not
operated [1]
IR
AVRH5
-
0.7
1
mA
A/D Converter active
IRH
AVRH5
-
-
5
μA
A/D Converter not
operated [2]
Power supply current
per ADC macro [3]
Reference voltage current
per ADC macro [3]
V
1. Supply current at AVCC5, if A/D converter and ALARM comparator are not operating, (VDD5 = AVCC5 = AVRH = 5.0 V)
2. Input current at AVRH5, if A/D converter is not operating, (VDD5 = AVCC5 = AVRH = 5.0 V)
3. The current consumption per ADC macro is given here. On devices having more then one A/D converter, the
current values have to be multiplied by the number of macros.
Sampling Time Calculation
Tsamp = ( 2.6 kOhm + REXT) × 11pF × 7; for 4.5V ≤ AVCC5 ≤ 5.5V
Tsamp = (12.1 kOhm + REXT) × 11pF × 7; for 3.0V ≤ AVCC5 ≤ 4.5V
Conversion Time Calculation
Tconv = Tsamp + Tcomp
15.4.1 Definition of A/D Converter Terms
Resolution
Analog variation that is recognizable by the A/D converter.
■
Nonlinearity error
Deviation between actual conversion characteristics and a straight line connecting the zero transition point
(00 0000 0000B ↔ 00 0000 0001B) and the full scale transition point (11 1111 1110B ↔ 11 1111 1111B).
■
Differential nonlinearity error
Deviation of the input voltage from the ideal value that is required to change the output code by 1 LSB.
■
Total error
This error indicates the difference between actual and theoretical values, including the zero transition error, full scale transition
error, and nonlinearity error.
■
Document Number: 002-04608 Rev. *C
Page 105 of 127
CY91460B Series
Total error
3FFH
1.5 LSB’
3FEH
Actual conversion
characteristics
3FDH
Digital output
{1 LSB’ (N - 1) + 0.5 LSB’}
004H
VNT
(measurement value)
Actual conversion
characteristics
003H
002H
Ideal characteristics
001H
0.5 LSB'
AVSS5
AVRH
Analog input
1LSB' (ideal value) =
AVRH − AVSS5
1024
Total error of digital output N =
[V]
VNT - {1 LSB' × (N - 1) + 0.5 LSB'}
1 LSB'
N: A/D converter digital output value
VOT' (ideal value) = AVSS5 + 0.5 LSB' [V]
VFST' (ideal value) = AVRH − 1.5 LSB' [V]
VNT: Voltage at which the digital output changes from (N + 1) H to NH
Document Number: 002-04608 Rev. *C
Page 106 of 127
CY91460B Series
Nonlinearity error
3FFH
Differential nonlinearity error
Actual conversion characteristics
Actual conversion characteristics
(N+1)H
3FEH
{1 LSB (N - 1) + VOT}
VFST
VNT
(measurement
value)
003H
Digital output
Digital output
004H
002H
Ideal
characteristics
(measurement
value)
3FDH
NH
(N-1)H
VFST
(measurement
value)
(measurement value)
Actual conversion
characteristics
VNT
Ideal characteristics
(N-2)H
001H
Actual conversion
characteristics
VTO (measurement value)
AVSS5
AVRH
AVSS5
AVRH
Analog input
Nonlinearity error of digital output N =
Differential nonlinearity error of digital output N =
1LSB =
VFST − VOT
1022
Analog input
VNT − {1LSB × (N − 1) + VOT}
1LSB
V (N + 1) T − VNT
1LSB
[LSB]
− 1 [LSB]
[V]
N: A/D converter digital output value
VOT: Voltage at which the digital output changes from 000H to 001H.
VFST: Voltage at which the digital output changes from 3FEH to 3FFH.
Document Number: 002-04608 Rev. *C
Page 107 of 127
CY91460B Series
15.5
Alarm Comparator Characteristics
Parameter
Symbol
Pin
Name
IA5ALMF
Power supply
current
IA5ALMS
AVCC5
IA5ALMH
Value
Unit
Remarks
40
μA
Alarm comparator enabled in fast mode
(per channel) [1]
7
10
μA
Alarm comparator enabled in normal mode
(per channel) [1]
−
−
5
μA
Alarm comparator disabled
−1
−
+1
μA
TA=25 °C
−3
−
+3
μA
TA=125 °C
Min
Typ
Max
−
25
−
ALARM pin input
current
IALIN
ALARM pin input
voltage range
VALIN
0
−
AVCC5
V
Alarm upper limit
voltage
VIAH
AVCC5 × 0.78 - 3%
AVCC5 × 0.78
AVCC5 × 0.78 + 3%
V
Alarm lower limit
voltage
VIAL
AVCC5 × 0.36 - 5%
AVCC5 × 0.36
AVCC5 × 0.36 + 5%
V
Alarm hysteresis
voltage
VIAHYS
50
-
250
mV
RIN
5
−
−
MΩ
tCOMPF
−
0.1
0.2
μs
Alarm comparator
enabled in fast mode [1]
tCOMPS
−
1
2
μs
Alarm comparator
enabled in normal
mode [1]
Alarm input
resistance
ALARM_n
Comparion time
1. The fast Alarm Comparator mode is enabled by setting ACSR.MD=1 Setting ACSR.MD=0 sets the normal mode.
Document Number: 002-04608 Rev. *C
Page 108 of 127
CY91460B Series
15.6
Flash Memory Program/Erase Characteristics
15.6.1 CY91F467BA/466BA
(VDD5 = 3.0 V to 5.5 V, VDD5R = 3.0 V to 5.5 V, VSS5 = 0 V, TA = −40 °C to + 105 °C)
Value
Parameter
Unit
Remarks
Min
Typ
Max
Sector erase time
-
0.5
2.0
s
Erasure programming time not included
Chip erase time
-
n*0.5
n*2.0
s
n is the number of Flash sector of the device
Word (16-bit width) programming time
-
6
100
μs
System overhead time not included
Program/Erase cycle
Flash data retention time
10 000
cycle
20
year
[1]
1. This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature
measurements into normalized value at 85oC)
15.6.2 CY91F465BB/464BB
(VDD5 = 3.0 V to 5.5 V, VDD5R = 3.0 V to 5.5 V, VSS5 = 0 V, TA = −40 °C to + 105 °C)
Value
Parameter
Unit
Remarks
Min
Typ
Max
Sector erase time
-
0.9
3.6
s
Erasure programming time not included
Chip erase time
-
n*0.9
n*3.6
s
n is the number of Flash sector of the device
Word (16-bit or 32-bit width)
programming time
-
23
370
μs
System overhead time not included
Program/Erase cycle
Flash data retention time
10 000
cycle
20
year
[1]
1. This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85oC)
Document Number: 002-04608 Rev. *C
Page 109 of 127
CY91460B Series
15.7
AC Characteristics
15.7.1 Clock Timing
(VDD5 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 125 °C)
Parameter
Clock frequency
Symbol
Pin Name
fC
Value
Unit
Condition
16
MHz
Opposite phase external
supply or crystal
100
kHz
Min
Typ
Max
X0
X1
3.5
4
X0A
X1A
32
32.768
Figure 3. Clock Timing Condition
tC
X0,
X1,
X0A,
X1A
0.8 VCC
0.2 VCC
PWH
PWL
15.7.2 Reset Input Ratings
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 125 °C)
Parameter
INITX input time (at power-on)
INITX input time (other than the above)
Symbol
Pin name
Condition
tINTL
INITX
−
Value
Unit
Min
Max
8
−
ms
20
−
μs
tINTL
INITX
Document Number: 002-04608 Rev. *C
0.2 VCC
Page 110 of 127
CY91460B Series
15.7.3
LIN-USART Timings at VDD5 = 3.0 to 5.5 V
■
Conditions during AC measurements
■
All AC tests were measured under the following conditions:
❐ - IOdrive = 5 mA
❐ - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA
❐ - VSS5 = 0 V
❐ - Ta = -40 °C to +125× °C
❐ - Cl = 50 pF (load capacity value of pins when testing)
❐ - VOL = 0.2 x VDD5
❐ - VOH = 0.8 x VDD5
❐ - EPILR = 0, PILR = 1 (Automotive Level = worst case)
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 125 °C)
Parameter
Symbol
Pin Name
Serial clock cycle time
tSCYCI
SCK ↓ → SOT delay
time
Condition
VDD5 = 3.0 V to 4.5 V
VDD5 = 4.5 V to 5.5 V
Unit
Min
Max
Min
Max
SCKn
4 tCLKP
-
4 tCLKP
-
ns
tSLOVI
SCKn
SOTn
- 30
30
- 20
20
ns
SOT → SCK ↓ delay
time
tOVSHI
SCKn
SOTn
-
m × tCLKP - 20[1]
-
ns
Valid SIN → SCK ↑
setup time
tIVSHI
SCKn
SINn
-
tCLKP + 45
-
ns
SCK ↑ → valid SIN
hold time
tSHIXI
SCKn
SINn
0
-
0
-
ns
Serial clock “H” pulse
width
tSHSLE
SCKn
tCLKP + 10
-
tCLKP + 10
-
ns
Serial clock“L” pulse
width
tSLSHE
SCKn
tCLKP + 10
-
tCLKP + 10
-
ns
SCK ↓ → SOT delay
time
tSLOVE
SCKn
SOTn
-
2 tCLKP + 55
-
2 tCLKP + 45
ns
Valid SIN → SCK ↑
setup time
tIVSHE
SCKn
SINn
10
-
10
-
ns
SCK ↑ → valid SIN
hold time
tSHIXE
SCKn
SINn
tCLKP + 10
-
tCLKP + 10
-
ns
SCK rising time
tFE
SCKn
-
20
-
20
ns
SCK falling time
tRE
SCKn
-
20
-
20
ns
Internal clock
m × tCLKP - 30[1]
operation
(master mode)
tCLKP + 55
External clock
operation
(slave mode)
1. Parameter m depends on tSCYCI and can be calculated as :
■ if tSCYCI = 2*k*tCLKP, then m = k, where k is an integer > 2
■ if tSCYCI = (2*k + 1)*tCLKP, then m = k + 1, where k is an integer > 1
Notes :
■
The above values are AC characteristics for CLK synchronous mode.
■ tCLKP
is the cycle time of the peripheral clock.
Document Number: 002-04608 Rev. *C
Page 111 of 127
CY91460B Series
Figure 4. Internal Clock Mode (Master Mode)
tSCYCI
SCKn
for ESCR:SCES = 0
VOH
VOL
VOL
VOH
SCKn
for ESCR:SCES = 1
VOH
VOL
tSLOVI
tOVSHI
VOH
VOL
SOTn
tIVSHI
tSHIXI
VOH
VOL
SINn
VOH
VOL
Figure 5. External Clock Mode (Slave Mode)
tSLSHE
SCKn
for ESCR:SCES = 0
VOH
SCKn
for ESCR:SCES = 1
VOL
tSHSLE
VOH
VOL
VOL
VOH
VOH
VOL
VOH
VOL
tRE
tFE
tSLOVE
SOTn
VOH
VOL
tIVSHE
SINn
Document Number: 002-04608 Rev. *C
VOH
VOL
tSHIXE
VOH
VOL
Page 112 of 127
CY91460B Series
15.7.4 I 2C AC Timings at VDD5 = 3.0 to 5.5 V
■
Conditions during AC measurements
All AC tests were measured under the following conditions:
❐ -IOdrive = 3 mA
❐ -VDD5 = 3.0 V to 5.5 V, Iload = 3 mA
❐ -VSS5 = 0 V
❐ -Ta = - 40 °C to + 125 °C
❐ -Cl = 50 pF
❐ -VOL = 0.3 × VDD5
❐ -VOH = 0.7 × VDD5
❐ -EPILR = 0, PILR = 0 (CMOS Hysteresis 0.3 × VDD5/0.7 × VDD5)
15.7.4.1 Fast Mode:
(VDD5 = 3.5 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 125 °C)
Parameter
Symbol
Pin Name
fSCL
Value
Unit
Min
Max
SCLn
0
400
kHz
tHD;STA
SCLn, SDAn
0.6
−
μs
LOW period of the SCL clock
tLOW
SCLn
1.3
−
μs
HIGH period of the SCL clock
tHIGH
SCLn
0.6
−
μs
tSU;STA
SCLn, SDAn
0.6
−
μs
tHD;DAT
SCLn, SDAn
0
0.9
μs
SCL clock frequency
Hold time (repeated) START condition.
After this period, the first clock pulse is generated
Setup time for a repeated START condition
2C-bus
Data hold time for I
devices
tSU;DAT
SCLn SDAn
100
−
ns
Rise time of both SDA and SCL signals
tr
SCLn, SDAn
20 + 0.1Cb
300
ns
Fall time of both SDA and SCL signals
tf
SCLn, SDAn
20 + 0.1Cb
300
ns
tSU;STO
SCLn, SDAn
0.6
−
μs
tBUF
SCLn, SDAn
1.3
−
μs
Capacitive load for each bus line
Cb
SCLn, SDAn
−
400
pF
Pulse width of spike suppressed by input
filter
tSP
SCLn, SDAn
0
(1..1.5) × tCLKP
ns
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START
condition
Remark
[1]
1. The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles of peripheral clock, depending on the phase
relationship between I2C signals (SDA, SCL) and peripheral clock.
Note: tCLKP is the cycle time of the peripheral clock.
Document Number: 002-04608 Rev. *C
Page 113 of 127
Document Number: 002-04608 Rev. *C
SCL
SDA
tHD;STA
tf
S
tr
tHD;DAT
tLOW
tHIGH
tSU;DAT
tSU;STA
Sr
tHD;STA
tSP
tr
P
tSU;ST0
tBUF
S
tf
CY91460B Series
Page 114 of 127
CY91460B Series
15.7.5 Free-Run Timer Clock
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 125 °C)
Parameter
Input pulse width
Symbol
Pin Name
Condition
tTIWH
tTIWL
CKn
−
Value
Min
Max
4tCLKP
−
Unit
ns
Note: tCLKP is the cycle time of the peripheral clock.
CKn
VIH
VIH
VIL
VIL
tTIWH
tTIWL
15.7.6 Trigger Input Timing
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 125 °C)
Parameter
Symbol
Pin Name
Condition
tINP
ICUn
tATGX
ATGX
Input capture input trigger
A/D converter trigger
Value
Unit
Min
Max
−
5tCLKP
−
ns
−
5tCLKP
−
ns
Note: tCLKP is the cycle time of the peripheral clock.
tATGX, tINP
ICUn,
ATGX
Document Number: 002-04608 Rev. *C
Page 115 of 127
CY91460B Series
15.7.7 External Bus AC Timings at VDD35 = 3.0 to 5.5 V
Note: This chapter is applicable to CY91F467BA/F466BA
Conditions during AC measurements
All AC tests were measured under the following conditions:
■
-IOdrive = 5 mA
-VDD35 = 4.5 V to 5.5 V, Iload = 3 mA
❐ -VSS5 = 0 V
❐ -Ta = − 40 °C to + 125 °C
❐ -Cl = 50 pF
❐ -VOL = 0.5 × VDD35
❐ -VOH = 0.5 × VDD35
❐ -EPILR = 0, PILR = 1 (Automotive Level = worst case)
❐
❐
15.7.7.1
Basic Timing
(VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 125 °C)
Parameter
SYSCLK
SYSCLK ↓ to CSXn delay time
SYSCLK ↑ to CSXn delay time (Addr → CS delay)
SYSCLK ↓ to Address valid delay time
Symbol
tCLCH
tCHCL
tCLCSL
tCLCSH
Pin Name
SYSCLK
SYSCLK
CSXn
tCHCSL
tCLAV
SYSCLK
A21 to A0
Value
Unit
Min
Max
1/2 x tCLKT - 1
1/2 × tCLKT + 9
ns
1/2 × tCLKT - 9
1/2 × tCLKT + 1
ns
-
8
ns
-
12
ns
-6
+1
ns
-
13
ns
Note: tCLKT is the cycle time of the external bus clock.
Document Number: 002-04608 Rev. *C
Page 116 of 127
CY91460B Series
tCLCH
tCHCL
tCYC
SYSCLK
tCLCSL
tCLCSH
CSXn
tCHCSL
delayed CSXn
tCLASH
tCLASL
ASX
tCLAV
ADDRESS
tCLBAH
tCLBAL
BAAX
Document Number: 002-04608 Rev. *C
Page 117 of 127
CY91460B Series
15.7.7.2
Synchronous/Asynchronous Read Access
(VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 125 °C)
Parameter
SYSCLK ↑ to RDX delay time
Symbol
Pin Name
TCHRL
SYSCLK
RDX
TCHRH
Value
Unit
Min
Max
-7
1
ns
-4
2
ns
Data valid to RDX ↑ setup time
TDSRH
RDX
D31 to D16
33
-
ns
RDX ↑ to Data valid hold time
TRHDX
RDX
D31 to D16
0
-
ns
-
8
ns
0
-
ns
-
8
ns
-
12
ns
SYSCLK ↓ to WRXn (as byte enable) delay time
TCLWRL
TCLWRH
TCLCSL
SYSCLK ↓ to CSXn delay time
TCLCSH
SYSCLK
WRXn
SYSCLK
CSXn
SYSCLK
tCLCSL
tCLCSH
CSXn
tCLWRL
tCLWRH
WRXn
(as byte enable)
tCHRH
tCHRL
RDX
tDSRH
tRHDX
DATA IN
Document Number: 002-04608 Rev. *C
Page 118 of 127
CY91460B Series
15.7.7.3
Synchronous Write Access
(VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 125 °C)
Parameter
SYSCLK ↓ to WRXn delay time
Symbol
Pin Name
TCLWRL
SYSCLK
WRXn
TCLWRH
Value
Unit
Min
Max
-
8
ns
0
-
ns
Data valid to WRXn ↓ setup time
TDSWRL
WRXn
D31 to D16
-7
-
ns
WRXn ↑ to Data valid hold time
TWRHDH
WRXn
D31 to D16
tCLKT - 20
-
ns
-
8
ns
-
12
ns
SYSCLK ↓ to CSXn delay time
TCLCSL
TCLCSH
SYSCLK
CSXn
SYSCLK
tCLCSH
tCLCSL
CSXn
tCLWRH
tCLWRL
WRXn
tDSWRL
tWRHDH
DATA OUT
Document Number: 002-04608 Rev. *C
Page 119 of 127
CY91460B Series
15.7.7.4
Asynchronous Write Access
(VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 125 °C)
Parameter
Symbol
Pin Name
WRXn ↓ to WRXn ↑ pulse width
TWRLWRH
Data valid to WRXn ↓ setup time
WRXn ↑ to Data valid hold time
WRXn to CSXn delay time
Value
Unit
Min
Max
WRXn
tCLKT
-
ns
TDSWRL
WRXn
D31 to D16
1/2 × tCLKT - 10
-
ns
TWRHDH
WRXn
D31 to D16
1/2 × tCLKT - 19
-
ns
-
1/2 × tCLKT
ns
1/2 × tCLKT
-
ns
TCLWRL
WRXn
CSXn
TWRHCH
CSXn
TWRHCH
TCLWRL
TWRLWRH
WRXn
TDSWRL
TWRHDH
DATA OUT
Document Number: 002-04608 Rev. *C
Page 120 of 127
CY91460B Series
15.7.7.5
RDY Wait Cycle Insertion
(VDD35 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 125 °C)
Parameter
Symbol
Pin Name
RDY setup time
TRDYS
RDY hold time
TRDYH
Value
Unit
Min
Max
SYSCLK
RDY
34
−
ns
SYSCLK
RDY
0
−
ns
SYSCLK
tRDYS
tRDYH
RDY
Document Number: 002-04608 Rev. *C
Page 121 of 127
CY91460B Series
16. Ordering Information
Part number
CY91F467BAPMC-GS-UJE2
Document Number: 002-04608 Rev. *C
Package
Remarks
144-pin plastic LQFP
(LQS144)
Page 122 of 127
CY91460B Series
17. Package Dimension
4
D
D1
108
4
5 7
7 5
73
109
73
72
D
D1
108
109
72
E1
E
5
7
E
4
4
E1
5
7
3
3
6
144
37
1
144
37
1
36
36
BOTTOM VIEW
2 5 7
e
3
0.10 C A-B D
0.20 C A-B D
b
0.08
TOP VIEW
C A-B
D
8
2
A
9 c
A
A'
0.08 C
SEATING
PLANE
L1
0.25
L
A1
10
b
SECTION A-A'
SIDE VIEW
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
1.70
A
A1
0.05
0.15
b
0.17
c
0.09
0.22
D
22.00 BSC
D1
20.00 BSC
e
0.50 BSC
E
22.00 BSC
E1
0.27
0.20
20.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
PACKAGE OUTLINE, 144 LEAD LQFP
20.0X20.0X1.7 MM LQS144 REV*A
Document Number: 002-04608 Rev. *C
002-13015 *A
Page 123 of 127
CY91460B Series
18. Revision History
Spansion Publication Number: DS07-16609-1E
Version
Date
Remark
2.0
2008-06-19
Initial version
2.1
2008-08-15
Proof reading results from FJ incorporated;
Corrected pinout drawings;
IO CIRCUIT TYPES: corrected some typos like on the other datasheets;
HANDLING DEVICES: updated the section "Notes on PS register" for better understanding;
Interrupt Vector Table: corrected the footnotes
FLASH: added note about the operation mode switching capability in Boot ROM; corrected flash
security vector FSV2 assignments, corrected section about parallel programming,
corrected section pin connections in parallel programming mode so that there is only one page
added section "Poweron Sequence in parallel programming mode";
ELECTRICAL CHARACTERISTICS: removed the note that analog input/output pins cannot accept +B signal input; splitted ILV into external and internal LV detection current
ADC Characteristics: Corrected the items about nonlinearity error;
Corrected the company name
3.0
2009-01-09
Page 1: Corrected document name field in top header
Block Diagram: Removed SCK0 (LIN-USART0 is asynchronous only)
Added Ta=125C characteristics
Document Number: 002-04608 Rev. *C
Page 124 of 127
CY91460B Series
19. Main Changes in This Edition
Page
Section
15. Electrical Characteristics
15.4. A/D converter characteristics
Corrected the column “Value” and “Unit” of the parameter “Zero reading voltage”
and “Full scale reading voltage”.
(Value :
AVRL - 1.5 → AVRL - 1.5 LSB
AVRL + 0.5 → AVRL + 0.5 LSB
AVRL + 2.5 → AVRL + 2.5 LSB
AVRH - 3.5 → AVRH - 3.5 LSB
AVRH - 1.5 → AVRH - 1.5 LSB
AVRH + 0.5 → AVRH + 0.5 LSB
Unit : LSB → V )
-
-
104
*B
7
122
123
Marketing Part Numbers changed from an MB prefix to a CY prefix.
2.Pin Assignment
16.Ordering Information
17.Package Dimension
Package description modified to JEDEC description.
16.Ordering Information
Deleted the following Marketing part number as follows:
MB91F465BBPMC-GSE2
Revised Marketing Part Numbers as follows:
before)
MB91F467BAPMC-GSE2
after)
CY91F467BAPMC-GS-UJE2
122
*C
Change Results
-
-
15.3 DC Characteristics
Revised the Unit.
before)
Input leakage current: mA
Analog input leakage current: mA
Pull-up resistance: kW
Pull-down resistance: kW
after)
Input leakage current: μA
Analog input leakage current: μA
Pull-up resistance: kΩ
Pull-down resistance: kΩ
102
NOTE: Please see “Document History” for later revised information.
Document Number: 002-04608 Rev. *C
Page 125 of 127
CY91460B Series
Document History
Document Title: CY91F467BA/466BA, CY91F465BB/464BB, FR60 CY91460B Series, 32-bit Microcontroller Datasheet
Document Number: 002-04608
Revision
ECN
Orig. of
Change
Submission
Date
**
−
AKIH
08/17/2009
Description of Change
Migrated to Cypress and assigned document number 002-04608.
No change to document contents or format.
*A
5221423
AKIH
04/25/2016
Updated to Cypress template
*B
6314451
SHUS
09/19/2018
Marketing Part Numbers changed from an MB prefix to a CY prefix.
2.Pin Assignments
16.Package Dimension
17.Ordering Information
For details, please see 19. Main Changes in this Edition
*C
6456716
SHUS
01/24/2019
Revised the Unit.
For details, please see 19. Main Changes in this Edition
Document Number: 002-04608 Rev. *C
Page 126 of 127
CY91460B Series
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation 2009-2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-04608 Rev. *C
Revised January 24, 2019
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