Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY96310 Series
F2MC-16FX 16-bit Proprietary
Microcontroller
CY96310 series is based on Cypress advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The
CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new
16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the
same operation frequency, reduced power consumption and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 56MHz
operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going together with
excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum. The
emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select
suitable operation frequencies for peripheral resources independent of the CPU speed.
Features
Technology
■
Code Security
0.18m CMOS
■
CPU
2
■ F MC-16FX
Protects ROM content from unintended read-out
Memory Patch Function
CPU
■
Replaces ROM content
Can also be used to implement embedded debug support
■
Up to 56 MHz internal, 17.8 ns instruction cycle time
■
■
Optimized instruction set for controller applications (bit, byte,
word and long-word data types; 23 different addressing modes;
barrel shift; variety of pointers)
DMA
■
8-byte instruction execution queue
■
Signed multiply (16-bit ×16-bit) and divide (32-bit/16-bit)
instructions available
System clock
■
Automatic transfer function independent of CPU, can be
assigned freely to resources
Interrupts
■
Fast Interrupt processing
■
8 programmable priority levels
Non-Maskable Interrupt (NMI)
■
On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)
■
■
3 MHz - 16 MHz external crystal oscillator clock (maximum
frequency when using ceramic resonator depends on
Q-factor).
Timers
■
Up to 56 MHz external clock
■
32-100 kHz subsystem quartz clock
■
100kHz/2MHz internal RC clock for quick and safe startup,
oscillator stop detection, watchdog
■
■
■
■
Three independent clock timers (23-bit RC clock timer, 23-bit
Main clock timer, 17-bit Sub clock timer)
■
Watchdog Timer
CAN
■
Supports CAN protocol version 2.0 part A and B
Clock source selectable from main- and subclock oscillator
(part number suffix “W”) and on-chip RC oscillator,
independently for CPU and 2 clock domains of peripherals.
■
ISO16845 certified
■
Bit rates up to 1 Mbit/s
Low Power Consumption - 13 operating modes : (different Run,
Sleep, Timer modes, Stop mode)
■
32 message objects
■
Each message object has its own identifier mask
■
Programmable FIFO mode (concatenation of message
objects)
■
Maskable interrupt
■
Disabled Automatic Retransmission mode for Time Triggered
CAN applications
■
Programmable loop-back mode for self-test operation
Clock modulator
On-chip voltage regulator
■
Internal voltage regulator supports reduced internal MCU
voltage, offering low EMI and low power consumption figures
Low voltage reset
■
Reset is generated when supply voltage is below minimum.
Cypress Semiconductor Corporation
Document Number: 002-04592 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 23, 2019
CY96310 Series
USART
■
Full duplex USARTs (SCI/LIN)
■
Wide range of baud rate settings using a dedicated reload timer
■
Special synchronous options for adapting to different
synchronous serial protocols
■
LIN functionality working either as master or slave LIN device
A/D converter
Real Time Clock
■
Can be clocked either from sub oscillator (devices with part
number suffix “W”), main oscillator or from the RC oscillator
■
Facility to correct oscillation deviation of Sub clock or RC
oscillator clock (clock calibration)
■
Read/write accessible second/minute/hour registers
■
Can signal interrupts every half
second/second/minute/hour/day
Internal clock divider and prescaler provide exact 1s clock
■
SAR-type
■
■
10-bit resolution
External Interrupts
■
Signals interrupt on conversion end, single conversion mode,
continuous conversion mode, stop conversion mode, activation
by software, external trigger or reload timer
Reload Timers
■
16-bit wide
■
Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral
clock frequency
■
Event count function
Free Running Timers
■
Signals an interrupt on overflow, supports timer clear upon
match with Output Compare (0, 4), Prescaler with 1, 1/21, 1/22,
1/23, 1/24, 1/25, 1/26, 1/27,1/28 of peripheral clock frequency
Input Capture Units
■
16-bit wide
■
Signals an interrupt upon external event
■
Rising edge, falling edge or rising & falling edge sensitive
Output Compare Units
■
16-bit wide
■
Signals an interrupt when a match with 16-bit I/O Timer occurs
■
A pair of compare registers can be used to generate an output
signal.
Programmable Pulse Generator
■
16-bit down counter, cycle and duty setting registers
■
Interrupt at trigger, counter borrow and/or duty match
■
PWM operation and one-shot operation
■
Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock
as counter clock and Reload timer underflow as clock input
■
Can be triggered by software or reload timer
Document Number: 002-04592 Rev. *C
■
Edge sensitive or level sensitive
■
Interrupt mask and pending bit per channel
■
Each available CAN channel RX has an external interrupt for
wake-up
■
Selected USART channels SIN have an external interrupt for
wake-up
Non Maskable Interrupt
■
Disabled after reset
■
Once enabled, can not be disabled other than by reset.
■
Level high or level low sensitive
■
Pin shared with external interrupt 0.
I/O Ports
■
Virtually all external pins can be used as general purpose I/O
■
All push-pull outputs
■
Bit-wise programmable as input/output or peripheral signal
■
Bit-wise programmable input enable
■
Bit-wise programmable input levels: Automotive /
CMOS-Schmitt trigger / TTL
■
Bit-wise programmable pull-up resistor
■
Bit-wise programmable output driving strength for EMI
optimization
Packages
■
48-pin plastic LQFP M26
Page 2 of 82
CY96310 Series
Flash Memory
■
Supports automatic programming, Embedded Algorithm
■
Write/Erase/Erase-Suspend/Resume commands
■
A flag indicating completion of the algorithm
■
Number of erase cycles: 10,000 times
■
Data retention time: 20 years
■
Erase can be performed on each sector individually
■
Sector protection
■
Flash Security feature to protect the content of the Flash
■
Low voltage detection during Flash erase
Document Number: 002-04592 Rev. *C
Page 3 of 82
CY96310 Series
Contents
Product Lineup ................................................................. 5
Block Diagram .................................................................. 6
Pin Assignments .............................................................. 7
Pin Function Description ................................................. 8
Pin Circuit Type .............................................................. 10
I/O Circuit Type ............................................................... 11
Memory Map .................................................................... 13
RAMSTART Addresses .................................................. 14
User ROM Memory Map for Flash Devices .................. 15
Serial Programming Communication Interface ........... 16
I/O Map ............................................................................. 17
Interrupt Vector Table .................................................... 39
Handling Devices ............................................................ 42
Latch-up prevention ................................................... 42
Unused pins handling ................................................ 42
External clock usage ................................................. 42
Unused sub clock signal ............................................ 43
Notes on PLL clock mode operation ......................... 43
Power supply pins (VCC/VSS) .................................. 43
Crystal oscillator and ceramic resonator circuit ......... 43
Turn on sequence of power supply to
A/D converter and analog inputs ............................... 43
Document Number: 002-04592 Rev. *C
Pin handling when not using the A/D converter ........ 43
Notes on Power-on .................................................... 43
Stabilization of power supply voltage ........................ 44
Serial communication ................................................ 44
Electrical Characteristics ............................................... 45
Absolute Maximum Ratings ....................................... 45
Recommended Operating Conditions ....................... 47
DC characteristics ..................................................... 48
AC Characteristics ..................................................... 55
Analog Digital Converter ........................................... 63
Low Voltage Detector characteristics ........................ 67
FLASH memory program/erase characteristics ........ 69
Example Characteristics ................................................ 70
Temperature dependency of
power supply currents ............................................... 70
Frequency dependency of
power supply currents in PLL Run mode .................. 75
Package Dimension CY96(F)31x LQFP48 .................... 76
Ordering Information ...................................................... 77
Revision History ............................................................. 78
Major Changes ................................................................ 79
Document History ........................................................... 81
Page 4 of 82
CY96310 Series
1. Product Lineup
Features
CY96V300C
CY96(F)31x
Product type
Evaluation sample
Flash product: CY96F31x
Mask ROM product: CY9631x
NA
Low voltage reset persistently on / Single clock devices
Product options
YS
RS
Low voltage reset can be disabled / Single clock devices
YW
Low voltage reset persistently on / Dual clock devices
RW
Low voltage reset can be disabled / Dual clock devices
AS
No CAN / Low voltage reset can be disabled / Single clock devices
AW
No CAN / Low voltage reset can be disabled / Dual clock devices
Flash/ROM
RAM
96KB
8KB
160KB
8KB
ROM/Flash memory
emulation by external
RAM, 92KB internal
RAM
CY96F313Y, CY96F313R, CY96F313A
CY96F315Y, CY96F315R, CY96F315A
Package
BGA416
LQA048
DMA
16 channels
4 channels
USART
10 channels
3 channels
A/D Converter
40 channels
12 channels
A/D Converter Reference
Voltage switch
yes
No
16-bit Reload Timer
6 channels + 1
channel (for PPG)
4 channels + 1 channel (for PPG)
16-bit Free-Running Timer
4 channels
4 channels (without external clock input pin)
16-bit Output Compare
12 channels
2 channels
16-bit Input Capture
12 channels
4 channels (plus 3 channels for LIN USART)
16-bit Programmable Pulse
Generator
20 channels
14 channels
CAN Interface
5 channels
1 channel
External Interrupts
16 channels
11 channels
Non-Maskable Interrupt
1 channel
Real Time Clock
1
I/O Ports
136
34 for part number with suffix “W”, 36 for part number with suffix “S”
Clock output function
2 channels
Low voltage reset
Yes
On-chip RC-oscillator
Yes
Document Number: 002-04592 Rev. *C
Page 5 of 82
CY96310 Series
2. Block Diagram
Block Diagram of CY96(F)31x
CKOT0_R, CKOT1, CKOT1_R
CKOTX1
X0, X1
X0A, X1A *1
RSTX
MD0...MD2
NMI
16FX
CPU
Interrupt
Controller
Flash
Memory A
Memory Patch
Unit
Clock &
Mode Controller
16FX Core Bus (CLKB)
TIN1
TOT0_R, TOT2_R
TOT1, TOT3
Peripheral
Bus Bridge
Peripheral
Bus Bridge
Peripheral Bus 2 (CLKP2)
AVCC
AVSS
AVRH
AN0, AN1, AN3, AN4
AN6 ... AN10
AN12, AN14, AN16
ADTG_R
Watchdog
10-bit ADC
12 ch.
16-bit Reload
Timer
4 ch.
IN0, IN1
I/O Timer 0
ICU 0/1
IN4, IN5
OUT6, OUT7
I/O Timer 1
ICU 4/5/6
OCU 6/7
Peripheral Bus 1 (CLKP1)
DMA
Controller
I/O Timer 2
ICU 9
I/O Timer 3
ICU 10
USART
3 ch.
16-bit PPG
14 ch.
RLT6
RAM
Boot ROM
Voltage
Regulator
VCC
VSS
C
CAN
Interface
1 ch.
TX2
RX2
SIN2, SIN2_R, SIN7_R, SIN8_R
SOT2, SOT2_R, SOT7_R, SOT8_R
SCK2, SCK2_R, SCK7_R, SCK8_R
TTG0, TTG1, TTG4, TTG8, TTG9, TTG12
TTG8_R, TTG9_R, TTG16_R, TTG17_R
PPG0, PPG1, PPG3, PPG4
PPG6, PPG7, PPG12, PPG14
PPG8_R, PPG9_R, PPG16_R ... PPG19_R
Real Time
Clock
External
Interrupt
INT0, INT8 ... INT13
INT2_R, INT4_R
INT7_R, INT10_R
INT3_R1
*1: X0A, X1A only available on devices with suffix “W”
Document Number: 002-04592 Rev. *C
Page 6 of 82
CY96310 Series
3. Pin Assignments
P01_1 / CKOTX1 / TOT1 / TTG17_R
P01_4 / PPG16_R
P01_5 / SIN2_R / INT7_R / PPG17_R
P01_6 / SOT2_R / PPG18_R
P01_7 / SCK2_R / PPG19_R
P02_0 / PPG12 / CKOT1_R
P02_2 / PPG14 / CKOT0_R
P02_4 / IN0 / TTG8 / TTG0
X1
RSTX
Vss
Vcc
X0
Pin assignment of CY96(F)31x
36 35 34 33 32 31 30 29 28 27 26 25
24
37
P01_0 / CKOT1 / TIN1 / TTG16_R
C
38
23
P00_3 / INT11 / SCK8_R
P02_5 / IN1 / TTG1 / TTG9 / ADTG_R
39
22
P00_5/ INT13 / SIN8_R / PPG9_R
P03_0 / IN4 / TTG4 / TTG12 / TOT0_R
40
21
P00_4 / INT12 / SOT8_R / PPG8_R
P03_1 / IN5 / TOT2_R
41
20
P00_2 / INT10 / SIN7_R
P03_2 / INT10_R / RX2
42
19
P00_1 / INT9 / SOT7_R / TTG9_R
LQFP - 48
Package code (mold)
P03_3 / TX2
43
P03_6 / OUT6
44
P03_7 / OUT7
45
P06_0 / AN0 / PPG0
46
15
P06_1 /AN1 / PPG1
47
14
X1A / P04_1 *1
13
X0A / P04_0 *1
MD0
MD1
MD2
9 10 11 12
P07_0 / AN16 / INT0 / NMI
8
P05_6 / AN14 / INT4_R
P06_4 / AN4 / PPG4
7
P05_4 / AN12 / TOT3 / INT2_R
P06_3 / AN3 / PPG3
6
P00_0 / INT8 / SCK7_R / TTG8_R
17
16
P05_2 / AN10 / SCK2
AVRH
5
P05_1 / AN9 / SOT2
4
P05_0 / AN8 / SIN2 / INT_3R1
3
P06_7 / AN7 / PPG7
2
P06_6 / AN6 / PPG6
48
1
AVss
AVcc
LQA048
18
*1: Devices with suffix W: X0A, X1A
Devices with suffix S: P04_0, P04_1
(LQA048)
Document Number: 002-04592 Rev. *C
Page 7 of 82
CY96310 Series
4. Pin Function Description
Pin Function description (1 of 2)
Pin name
Feature
Description
ADTG_R
ADC
Relocated A/D converter trigger input
ANn
ADC
A/D converter channel n input
AVCC
Supply
Analog circuits power supply
AVRH
ADC
A/D converter high reference voltage input
AVSS
Supply
Analog circuits power supply
C
Voltage regulator
Internally regulated power supply stabilization capacitor pin
CKOTn
Clock output function
Clock Output function n output
CKOTn_R
Clock output function
Relocated Clock Output function n output
CKOTXn
Clock output function
Clock Output function n inverted output
INn
ICU
Input Capture Unit n input
INTn
External Interrupt
External Interrupt n input
INTn_R
External Interrupt
Relocated External Interrupt n input
MDn
Core
Input pins for specifying the operating mode.
NMI
External Interrupt
Non-Maskable Interrupt input
OUTn
OCU
Output Compare Unit n waveform output
Pxx_n
GPIO
General purpose IO
PPGn
PPG
Programmable Pulse Generator n output
PPGn_R
PPG
Relocated Programmable Pulse Generator n output
RSTX
Core
Reset input
RXn
CAN
CAN interface n RX input
SCKn
USART
USART n serial clock input/output
SCKn_R
USART
Relocated USART n serial clock input/output
SINn
USART
USART n serial data input
SINn_R
USART
Relocated USART n serial data input
SOTn
USART
USART n serial data output
SOTn_R
USART
Relocated USART n serial data output
TINn
Reload Timer
Reload Timer n event input
TINn_R
Reload Timer
Relocated Reload Timer n event input
TOTn
Reload Timer
Reload Timer n output
TOTn_R
Reload Timer
Relocated Reload Timer n output
Document Number: 002-04592 Rev. *C
Page 8 of 82
CY96310 Series
Pin Function description (2 of 2)
Pin name
Feature
Description
TTGn
PPG
Programmable Pulse Generator n trigger input
TTGn_R
PPG
Relocated Programmable Pulse Generator n trigger input
TXn
CAN
CAN interface n TX output
VCC
Supply
Power supply
VSS
Supply
Power supply
X0
Clock
Oscillator input
X0A
Clock
Subclock Oscillator input (only for devices with suffix “W”)
X1
Clock
Oscillator output
X1A
Clock
Subclock Oscillator output (only for devices with suffix “W”)
Document Number: 002-04592 Rev. *C
Page 9 of 82
CY96310 Series
5. Pin Circuit Type
Pin circuit types
LQA048
Pin no.
Circuit type *1
1
Supply
2
G
3 to 12
I
13, 14
B *2
13, 14
H *3
15 to 17
C
18 to 32
H
33
E
34, 35
A
36, 37
Supply
38
F
39 to 45
H
46, 47
I
48
Supply
*1: Please refer to “6.“I/O Circuit Type”” for details on the I/O circuit types
*2: Devices with suffix “W”
*3: Devices without suffix “W”
Document Number: 002-04592 Rev. *C
Page 10 of 82
CY96310 Series
6. I/O Circuit Type
Type
Circuit
Remarks
X1
R
A
0
MRFBE
Xout
1
FCI
R
High-speed oscillation circuit:
• Programmable between oscillation mode (external
crystal or resonator connected to X0/X1 pins) and
Fast external Clock Input (FCI) mode (external clock
connected to X0 pin)
• Programmable feedback resistor = approx.
2 * 0.5 M. Feedback resistor is grounded in the
center when the oscillator is disabled or in FCI mode
X0
FCI or osc disable
Xout
X1A
R
B
Low-speed oscillation circuit:
• Programmable feedback resistor = approx.
2 * 5 M. Feedback resistor is grounded in the center
when the oscillator is disabled
SRFBE
R
X0A
osc disable
C
E
R
Hysteresis
inputs
• Mask ROM and EVA device:
CMOS Hysteresis input pin
• Flash device:
CMOS input pin
• CMOS Hysteresis input pin
• Pull-up resistor value: approx. 50 k
Pull-up
Resistor
R
Document Number: 002-04592 Rev. *C
Hysteresis
inputs
Page 11 of 82
CY96310 Series
Type
Circuit
Remarks
F
• Power supply input protection circuit
ANE
G
AVR
• A/D converter ref+ (AVRH) power supply input pin
with protection circuit
• Flash devices do not have a protection circuit against
VCC for pin AVRH
ANE
pull-up control
Pout
Nout
H
R
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• CMOS hysteresis input with input shutdown function
• Automotive input with input shutdown function
• Programmable pull-up resistor: 50k approx.
Hysteresis input
Standby control
for input shutdown
Automotive input
Standby control
for input shutdown
Pull-up control
Pout
Nout
I
R
Standby control
for input shutdown
Standby control
for input shutdown
Hysteresis input
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• CMOS hysteresis input with input shutdown function
• Automotive input with input shutdown function
• Programmable pull-up resistor: 50k approx.
• Analog input
Automotive input
Analog input
Document Number: 002-04592 Rev. *C
Page 12 of 82
CY96310 Series
7. Memory Map
CY96V300C
CY96(F)31x
Emulation ROM
USER ROM /
Reserved*4
External Bus
Reserved
Boot-ROM
Boot-ROM
FF:FFFFH
DE:0000H
10:0000H
0F:E000H
Reserved
0E:0000H
External RAM
Reserved
02:0000H
Internal RAM
bank 1
01:0000H
ROM/RAM MIRROR
ROM/RAM MIRROR
00:8000H
Internal RAM
bank 0
Internal RAM
bank 0
Reserved
RAMSTART0*3
00:0C00H
RAMSTART0*2
External Bus
Peripherals
Peripherals
GPR*1
GPR*1
DMA
DMA
External Bus
Reserved
Peripheral
Peripheral
00:0380H
00:0180H
00:0100H
00:00F0H
00:0000H
*1: Unused GPR banks can be used as RAM area
*2: For RAMSTART0 addresses, please refer to the table on the next page.
*3: For EVA device, RAMSTART0 depends on the configuration of the emulated device.
*4: For details about USER ROM area, see the ■ User ROM Memory Map for Flash Devices on the following
pages.
The DMA area is only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device.
Document Number: 002-04592 Rev. *C
Page 13 of 82
CY96310 Series
8. RAMSTART Addresses
Devices
RAM size
RAMSTART0
CY96F313/F315
8KByte
00:6240H
Document Number: 002-04592 Rev. *C
Page 14 of 82
CY96310 Series
9. User ROM Memory Map for Flash Devices
CY96F313
CY96F315
Alternative mode
CPU address
Flash memory
mode address
Flash size
96kByte
Flash size
160kByte
FF:FFFFH
FF:0000H
3F:FFFFH
3F:0000H
S39 - 64K
S39 - 64K
FE:FFFFH
FE:0000H
3E:FFFFH
3E:0000H
FD:FFFFH
FD:0000H
3D:FFFFH
3D:0000H
FC:FFFFH
FC:0000H
3C:FFFFH
3C:0000H
FB:FFFFH
FB:0000H
3B:FFFFH
3B:0000H
FA:FFFFH
FA:0000H
3A:FFFFH
3A:0000H
F9:FFFFH
F9:0000H
39:FFFFH
39:0000H
F8:FFFFH
F8:0000H
38:FFFFH
38:0000H
F7:FFFFH
F7:0000H
37:FFFFH
37:0000H
F6:FFFFH
F6:0000H
36:FFFFH
36:0000H
F5:FFFFH
F5:0000H
35:FFFFH
35:0000H
F4:FFFFH
F4:0000H
34:FFFFH
34:0000H
F3:FFFFH
F3:0000H
33:FFFFH
33:0000H
F2:FFFFH
F2:0000H
32:FFFFH
32:0000H
F1:FFFFH
F1:0000H
31:FFFFH
31:0000H
F0:FFFFH
F0:0000H
30:FFFFH
30:0000H
S38 - 64K
Reserved
Flash A
Reserved
E0:FFFFH
DF:FFFFH
DF:8000H
DF:7FFFH
DF:6000H
1F:7FFFH
1F:6000H
SA3 - 8K
SA3 - 8K
DF:5FFFH
DF:4000H
1F:5FFFH
1F:4000H
SA2 - 8K
SA2 - 8K
DF:3FFFH
DF:2000H
1F:3FFFH
1F:2000H
SA1 - 8K
SA1 - 8K
DF:1FFFH
DF:0000H
1F:1FFFH
1F:0000H
SA0 - 8K *1
SA0 - 8K *1
Reserved
Reserved
DE:FFFFH
DE:0000H
Flash A
*1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH
Document Number: 002-04592 Rev. *C
Page 15 of 82
CY96310 Series
10. Serial Programming Communication Interface
USART pins for Flash serial programming (MD[2:0] = 010)
CY96F31x
Pin number
USART Number
Normal function
LQFP-48
7
8
SIN2
USART2
SOT2
9
SCK2
20
SIN7_R
19
USART7
SOT7_R
18
SCK7_R
22
SIN8_R
21
23
USART8
SOT8_R
SCK8_R
Note: If a Flash programmer and its software needs to use a handshaking pin, Cypress suggests to the tool vendor to support at least
port P00_1 on pin 19.
If handshaking is used by the tool but P00_1 is not available in customer’s application, Cypress suggests to the customer to
check the tool manual or to contact the tool vendor for alternative handshaking pins.
Document Number: 002-04592 Rev. *C
Page 16 of 82
CY96310 Series
11. I/O Map
I/O map CY96(F)315x (Sheet 1 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000000H
I/O Port P00 - Port Data Register
PDR00
R/W
000001H
I/O Port P01 - Port Data Register
PDR01
R/W
000002H
I/O Port P02 - Port Data Register
PDR02
R/W
000003H
I/O Port P03 - Port Data Register
PDR03
R/W
000004H
Reserved
000005H
I/O Port P05 - Port Data Register
PDR05
R/W
000006H
I/O Port P06 - Port Data Register
PDR06
R/W
000007H
I/O Port P07 - Port Data Register
PDR07
R/W
000008H000017H
Reserved
000018H
ADC0 - Control Status register Low
ADCSL
000019H
ADC0 - Control Status register High
ADCSH
00001AH
ADC0 - Data Register Low
ADCRL
00001BH
ADC0 - Data Register High
ADCRH
00001CH
ADC0 - Setting Register
00001DH
ADC0 - Setting Register
00001EH
ADC0 - Extended Configuration Register
00001FH
Reserved
000020H
FRT0 - Data register of free-running timer
000021H
FRT0 - Data register of free-running timer
000022H
FRT0 - Control status register of free-running timer Low
TCCSL0
000023H
FRT0 - Control status register of free-running timer High
TCCSH0
000024H
FRT1 - Data register of free-running timer
000025H
FRT1 - Data register of free-running timer
000026H
FRT1 - Control status register of free-running timer Low
TCCSL1
000027H
FRT1 - Control status register of free-running timer High
TCCSH1
000028H000039H
Reserved
00003AH
OCU6 - Output Compare Control Status
OCS6
R/W
00003BH
OCU7 - Output Compare Control Status
OCS7
R/W
Document Number: 002-04592 Rev. *C
-
ADCS
R/W
R/W
ADCR
R
R
ADSR
R/W
R/W
ADECR
R/W
TCDT0
R/W
R/W
TCCS0
R/W
R/W
TCDT1
R/W
R/W
TCCS1
R/W
R/W
-
Page 17 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 2 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
OCCP6
R/W
00003CH
OCU6 - Compare Register
00003DH
OCU6 - Compare Register
00003EH
OCU7 - Compare Register
00003FH
OCU7 - Compare Register
000040H
ICU0/ICU1 - Control Status Register
ICS01
R/W
000041H
ICU0/ICU1 - Edge register
ICE01
R/W
000042H
ICU0 - Capture Register Low
IPCPL0
000043H
ICU0 - Capture Register High
IPCPH0
000044H
ICU1 - Capture Register Low
IPCPL1
000045H
ICU1 - Capture Register High
IPCPH1
R/W
OCCP7
R/W
R/W
IPCP0
R
R
IPCP1
R
R
000046H 00004BH
Reserved
00004CH
ICU4/ICU5 - Control Status Register
ICS45
R/W
00004DH
ICU4/ICU5 - Edge register
ICE45
R/W
00004EH
ICU4 - Capture Register Low
IPCPL4
00004FH
ICU4 - Capture Register High
IPCPH4
000050H
ICU5 - Capture Register Low
IPCPL5
000051H
ICU5 - Capture Register High
IPCPH5
R
000052H
ICU6/ICU7 - Control Status Register
ICS67
R/W
000053H
ICU6/ICU7 - Edge register
ICE67
R/W
000054H
ICU6 - Capture Register Low
IPCPL6
000055H
ICU6 - Capture Register High
IPCPH6
000056H
ICU7 - Capture Register Low
IPCPL7
000057H
ICU7 - Capture Register High
IPCPH7
R
000058H
EXTINT0 - External Interrupt Enable Register
ENIR0
R/W
000059H
EXTINT0 - External Interrupt Interrupt request Register
EIRR0
R/W
00005AH
EXTINT0 - External Interrupt Level Select Low
ELVRL0
00005BH
EXTINT0 - External Interrupt Level Select High
ELVRH0
R/W
00005CH
EXTINT1 - External Interrupt Enable Register
ENIR1
R/W
00005DH
EXTINT1 - External Interrupt Interrupt request Register
EIRR1
R/W
00005EH
EXTINT1 - External Interrupt Level Select Low
Document Number: 002-04592 Rev. *C
-
ELVRL1
IPCP4
R
R
IPCP5
IPCP6
R
R
R
IPCP7
ELVR0
ELVR1
R
R/W
R/W
Page 18 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 3 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
00005FH
EXTINT1 - External Interrupt Level Select High
000060H
RLT0 - Timer Control Status Register Low
TMCSRL0
000061H
RLT0 - Timer Control Status Register High
TMCSRH0
000062H
RLT0 - Reload Register - for writing
TMRLR0
W
000062H
RLT0 - Reload Register - for reading
TMR0
R
000063H
RLT0 - Reload Register - for writing
W
000063H
RLT0 - Reload Register - for reading
R
000064H
RLT1 - Timer Control Status Register Low
TMCSRL1
000065H
RLT1 - Timer Control Status Register High
TMCSRH1
000066H
RLT1 - Reload Register - for writing
TMRLR1
W
000066H
RLT1 - Reload Register - for reading
TMR1
R
000067H
RLT1 - Reload Register - for writing
W
000067H
RLT1 - Reload Register - for reading
R
000068H
RLT2 - Timer Control Status Register Low
TMCSRL2
000069H
RLT2 - Timer Control Status Register High
TMCSRH2
00006AH
RLT2 - Reload Register - for writing
TMRLR2
W
00006AH
RLT2 - Reload Register - for reading
TMR2
R
00006BH
RLT2 - Reload Register - for writing
W
00006BH
RLT2 - Reload Register - for reading
R
00006CH
RLT3 - Timer Control Status Register Low
TMCSRL3
00006DH
RLT3 - Timer Control Status Register High
TMCSRH3
00006EH
RLT3 - Reload Register - for writing
TMRLR3
W
00006EH
RLT3 - Reload Register - for reading
TMR3
R
00006FH
RLT3 - Reload Register - for writing
W
00006FH
RLT3 - Reload Register - for reading
R
000070H
RLT6 - Timer Control Status Register Low (dedic. RLT for
PPG)
TMCSRL6
000071H
RLT6 - Timer Control Status Register High (dedic. RLT for
PPG)
TMCSRH6
000072H
RLT6 - Reload Register (dedic. RLT for PPG) - for writing
TMRLR6
W
000072H
RLT6 - Reload Register (dedic. RLT for PPG) - for reading
TMR6
R
Document Number: 002-04592 Rev. *C
ELVRH1
Access
R/W
TMCSR0
R/W
R/W
TMCSR1
R/W
R/W
TMCSR2
R/W
R/W
TMCSR3
R/W
R/W
TMCSR6
R/W
R/W
Page 19 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 4 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000073H
RLT6 - Reload Register (dedic. RLT for PPG) - for writing
W
000073H
RLT6 - Reload Register (dedic. RLT for PPG) - for reading
R
000074H
PPG3-PPG0 - General Control register 1 Low
GCN1L0
000075H
PPG3-PPG0 - General Control register 1 High
GCN1H0
000076H
PPG3-PPG0 - General Control register 2 Low
GCN2L0
000077H
PPG3-PPG0 - General Control register 2 High
GCN2H0
000078H
PPG0 - Timer register
000079H
PPG0 - Timer register
00007AH
PPG0 - Period setting register
00007BH
PPG0 - Period setting register
00007CH
PPG0 - Duty cycle register
00007DH
PPG0 - Duty cycle register
00007EH
PPG0 - Control status register Low
PCNL0
00007FH
PPG0 - Control status register High
PCNH0
000080H
PPG1 - Timer register
000081H
PPG1 - Timer register
000082H
PPG1 - Period setting register
000083H
PPG1 - Period setting register
000084H
PPG1 - Duty cycle register
000085H
PPG1 - Duty cycle register
000086H
PPG1 - Control status register Low
PCNL1
000087H
PPG1 - Control status register High
PCNH1
000088H00008FH
Reserved
000090H
PPG3 - Timer register
000091H
PPG3 - Timer register
000092H
PPG3 - Period setting register
000093H
PPG3 - Period setting register
000094H
PPG3 - Duty cycle register
000095H
PPG3 - Duty cycle register
000096H
PPG3 - Control status register Low
Document Number: 002-04592 Rev. *C
GCN10
R/W
R/W
GCN20
R/W
R/W
PTMR0
R
R
PCSR0
W
W
PDUT0
W
W
PCN0
R/W
R/W
PTMR1
R
R
PCSR1
W
W
PDUT1
W
W
PCN1
R/W
R/W
-
PTMR3
R
R
PCSR3
W
W
PDUT3
W
W
PCNL3
PCN3
R/W
Page 20 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 5 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000097H
PPG3 - Control status register High
PCNH3
R/W
000098H
PPG7-PPG4 - General Control register 1 Low
GCN1L1
000099H
PPG7-PPG4 - General Control register 1 High
GCN1H1
00009AH
PPG7-PPG4 - General Control register 2 Low
GCN2L1
00009BH
PPG7-PPG4 - General Control register 2 High
GCN2H1
00009CH
PPG4 - Timer register
00009DH
PPG4 - Timer register
00009EH
PPG4 - Period setting register
00009FH
PPG4 - Period setting register
0000A0H
PPG4 - Duty cycle register
0000A1H
PPG4 - Duty cycle register
0000A2H
PPG4 - Control status register Low
PCNL4
0000A3H
PPG4 - Control status register High
PCNH4
0000A4H0000D3H
Reserved
0000D4H
USART2 - Serial Mode Register
SMR2
R/W
0000D5H
USART2 - Serial Control Register
SCR2
R/W
0000D6H
USART2 - TX Register
TDR2
W
0000D6H
USART2 - RX Register
RDR2
R
0000D7H
USART2 - Serial Status
SSR2
R/W
0000D8H
USART2 - Control/Com. Register
ECCR2
R/W
0000D9H
USART2 - Ext. Status Register
ESCR2
R/W
0000DAH
USART2 - Baud Rate Generator Register Low
BGRL2
0000DBH
USART2 - Baud Rate Generator Register High
BGRH2
R/W
0000DCH
USART2 - Extended Serial Interrupt Register
ESIR2
R/W
0000DDH0000FFH
Reserved
GCN11
R/W
R/W
GCN21
R/W
R/W
PTMR4
R
R
PCSR4
W
W
PDUT4
W
W
PCN4
R/W
R/W
-
BGR2
R/W
-
000100H
DMA0 - Buffer address pointer low byte
BAPL0
R/W
000101H
DMA0 - Buffer address pointer middle byte
BAPM0
R/W
000102H
DMA0 - Buffer address pointer high byte
BAPH0
R/W
000103H
DMA0 - DMA control register
DMACS0
R/W
Document Number: 002-04592 Rev. *C
Page 21 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 6 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
IOA0
R/W
000104H
DMA0 - I/O register address pointer low byte
IOAL0
000105H
DMA0 - I/O register address pointer high byte
IOAH0
000106H
DMA0 - Data counter low byte
DCTL0
000107H
DMA0 - Data counter high byte
DCTH0
R/W
000108H
DMA1 - Buffer address pointer low byte
BAPL1
R/W
000109H
DMA1 - Buffer address pointer middle byte
BAPM1
R/W
00010AH
DMA1 - Buffer address pointer high byte
BAPH1
R/W
00010BH
DMA1 - DMA control register
DMACS1
R/W
00010CH
DMA1 - I/O register address pointer low byte
IOAL1
00010DH
DMA1 - I/O register address pointer high byte
IOAH1
00010EH
DMA1 - Data counter low byte
DCTL1
00010FH
DMA1 - Data counter high byte
DCTH1
R/W
000110H
DMA2 - Buffer address pointer low byte
BAPL2
R/W
000111H
DMA2 - Buffer address pointer middle byte
BAPM2
R/W
000112H
DMA2 - Buffer address pointer high byte
BAPH2
R/W
000113H
DMA2 - DMA control register
DMACS2
R/W
000114H
DMA2 - I/O register address pointer low byte
IOAL2
000115H
DMA2 - I/O register address pointer high byte
IOAH2
000116H
DMA2 - Data counter low byte
DCTL2
000117H
DMA2 - Data counter high byte
DCTH2
R/W
000118H
DMA3 - Buffer address pointer low byte
BAPL3
R/W
000119H
DMA3 - Buffer address pointer middle byte
BAPM3
R/W
00011AH
DMA3 - Buffer address pointer high byte
BAPH3
R/W
00011BH
DMA3 - DMA control register
DMACS3
R/W
00011CH
DMA3 - I/O register address pointer low byte
IOAL3
00011DH
DMA3 - I/O register address pointer high byte
IOAH3
00011EH
DMA3 - Data counter low byte
DCTL3
00011FH
DMA3 - Data counter high byte
DCTH3
000120H00017FH
Reserved
Document Number: 002-04592 Rev. *C
R/W
DCT0
IOA1
R/W
R/W
R/W
DCT1
IOA2
R/W
R/W
R/W
DCT2
IOA3
R/W
R/W
R/W
DCT3
R/W
R/W
-
Page 22 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 7 of 22)
Address
Register
000180H00037FH
CPU - General Purpose registers (RAM access)
000380H
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
GPR_RAM
R/W
DMA0 - Interrupt select
DISEL0
R/W
000381H
DMA1 - Interrupt select
DISEL1
R/W
000382H
DMA2 - Interrupt select
DISEL2
R/W
000383H
DMA3 - Interrupt select
DISEL3
R/W
000384H00038FH
Reserved
000390H
DMA - Status register low byte
DSRL
000391H
DMA - Status register high byte
DSRH
000392H
DMA - Stop status register low byte
DSSRL
000393H
DMA - Stop status register high byte
DSSRH
000394H
DMA - Enable register low byte
DERL
000395H
DMA - Enable register high byte
DERH
000396H00039FH
Reserved
0003A0H
Interrupt level register
ILR
0003A1H
Interrupt index register
IDX
0003A2H
Interrupt vector table base register Low
TBRL
0003A3H
Interrupt vector table base register High
TBRH
R/W
0003A4H
Delayed Interrupt register
DIRR
R/W
0003A5H
Non Maskable Interrupt register
NMI
R/W
0003A6H0003ABH
Reserved
0003ACH
EDSU communication interrupt selection Low
EDSU2L
0003ADH
EDSU communication interrupt selection High
EDSU2H
R/W
0003AEH
ROM mirror control register
ROMM
R/W
0003AFH
EDSU configuration register
EDSU
R/W
0003B0H
Memory patch control/status register ch 0/1
0003B1H
Memory patch control/status register ch 0/1
0003B2H
Memory patch control/status register ch 2/3
0003B3H
Memory patch control/status register ch 2/3
Document Number: 002-04592 Rev. *C
DSR
R/W
R/W
DSSR
R/W
R/W
DER
R/W
R/W
-
ICR
R/W
R/W
TBR
R/W
EDSU2
PFCS0
R/W
R/W
R/W
PFCS1
R/W
R/W
Page 23 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 8 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
PFCS2
R/W
0003B4H
Memory patch control/status register ch 4/5
0003B5H
Memory patch control/status register ch 4/5
0003B6H
Memory patch control/status register ch 6/7
0003B7H
Memory patch control/status register ch 6/7
0003B8H
Memory Patch function - Patch address 0 low
PFAL0
R/W
0003B9H
Memory Patch function - Patch address 0 middle
PFAM0
R/W
0003BAH
Memory Patch function - Patch address 0 high
PFAH0
R/W
0003BBH
Memory Patch function - Patch address 1 low
PFAL1
R/W
0003BCH
Memory Patch function - Patch address 1 middle
PFAM1
R/W
0003BDH
Memory Patch function - Patch address 1 high
PFAH1
R/W
0003BEH
Memory Patch function - Patch address 2 low
PFAL2
R/W
0003BFH
Memory Patch function - Patch address 2 middle
PFAM2
R/W
0003C0H
Memory Patch function - Patch address 2 high
PFAH2
R/W
0003C1H
Memory Patch function - Patch address 3 low
PFAL3
R/W
0003C2H
Memory Patch function - Patch address 3 middle
PFAM3
R/W
0003C3H
Memory Patch function - Patch address 3 high
PFAH3
R/W
0003C4H
Memory Patch function - Patch address 4 low
PFAL4
R/W
0003C5H
Memory Patch function - Patch address 4 middle
PFAM4
R/W
0003C6H
Memory Patch function - Patch address 4 high
PFAH4
R/W
0003C7H
Memory Patch function - Patch address 5 low
PFAL5
R/W
0003C8H
Memory Patch function - Patch address 5 middle
PFAM5
R/W
0003C9H
Memory Patch function - Patch address 5 high
PFAH5
R/W
0003CAH
Memory Patch function - Patch address 6 low
PFAL6
R/W
0003CBH
Memory Patch function - Patch address 6 middle
PFAM6
R/W
0003CCH
Memory Patch function - Patch address 6 high
PFAH6
R/W
0003CDH
Memory Patch function - Patch address 7 low
PFAL7
R/W
0003CEH
Memory Patch function - Patch address 7 middle
PFAM7
R/W
0003CFH
Memory Patch function - Patch address 7 high
PFAH7
R/W
0003D0H
Memory Patch function - Patch data 0 Low
PFDL0
0003D1H
Memory Patch function - Patch data 0 High
PFDH0
Document Number: 002-04592 Rev. *C
R/W
PFCS3
R/W
R/W
PFD0
R/W
R/W
Page 24 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 9 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
PFD1
R/W
0003D2H
Memory Patch function - Patch data 1 Low
PFDL1
0003D3H
Memory Patch function - Patch data 1 High
PFDH1
0003D4H
Memory Patch function - Patch data 2 Low
PFDL2
0003D5H
Memory Patch function - Patch data 2 High
PFDH2
0003D6H
Memory Patch function - Patch data 3 Low
PFDL3
0003D7H
Memory Patch function - Patch data 3 High
PFDH3
0003D8H
Memory Patch function - Patch data 4 Low
PFDL4
0003D9H
Memory Patch function - Patch data 4 High
PFDH4
0003DAH
Memory Patch function - Patch data 5 Low
PFDL5
0003DBH
Memory Patch function - Patch data 5 High
PFDH5
0003DCH
Memory Patch function - Patch data 6 Low
PFDL6
0003DDH
Memory Patch function - Patch data 6 High
PFDH6
0003DEH
Memory Patch function - Patch data 7 Low
PFDL7
0003DFH
Memory Patch function - Patch data 7 High
PFDH7
0003E0H0003F0H
Reserved
0003F1H
Memory Control Status Register A
MCSRA
0003F2H
Memory Timing Configuration Register A Low
MTCRAL
0003F3H
Memory Timing Configuration Register A High
MTCRAH
0003F4H0003F8H
Reserved
0003F9H
Flash Memory Write Control register 1
FMWC1
R/W
0003FAH
Flash Memory Write Control register 2
FMWC2
R/W
0003FBH
Flash Memory Write Control register 3
FMWC3
R/W
0003FCH
Flash Memory Write Control register 4
FMWC4
R/W
0003FDH
Flash Memory Write Control register 5
FMWC5
R/W
0003FEH0003FFH
Reserved
000400H
Standby Mode control register
SMCR
R/W
000401H
Clock select register
CKSR
R/W
000402H
Clock Stabilization select register
CKSSR
R/W
000403H
Clock monitor register
CKMR
R
Document Number: 002-04592 Rev. *C
R/W
PFD2
R/W
R/W
PFD3
R/W
R/W
PFD4
R/W
R/W
PFD5
R/W
R/W
PFD6
R/W
R/W
PFD7
R/W
R/W
R/W
MTCRA
R/W
R/W
-
-
Page 25 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 10 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
CKFCR
R/W
000404H
Clock Frequency control register Low
CKFCRL
000405H
Clock Frequency control register High
CKFCRH
000406H
PLL Control register Low
PLLCRL
000407H
PLL Control register High
PLLCRH
R/W
000408H
RC clock timer control register
RCTCR
R/W
000409H
Main clock timer control register
MCTCR
R/W
00040AH
Sub clock timer control register
SCTCR
R/W
00040BH
Reset cause and clock status register with clear function
RCCSRC
R
00040CH
Reset configuration register
RCR
R/W
00040DH
Reset cause and clock status register
RCCSR
R
00040EH
Watch dog timer configuration register
WDTC
R/W
00040FH
Watch dog timer clear pattern register
WDTCP
W
000410H000414H
Reserved
000415H
Clock output activation register
000416H
R/W
PLLCR
R/W
COAR
R/W
Clock output configuration register 0
COCR0
R/W
000417H
Clock output configuration register 1
COCR1
R/W
000418H
Clock Modulator control register
CMCR
R/W
000419H
Reserved
00041AH
Clock Modulator Parameter register Low
CMPRL
00041BH
Clock Modulator Parameter register High
CMPRH
00041CH00042BH
Reserved
00042CH
Voltage Regulator Control register
VRCR
R/W
00042DH
Clock Input and LVD Control Register
CILCR
R/W
00042EH00042FH
Reserved
000430H
I/O Port P00 - Data Direction Register
DDR00
R/W
000431H
I/O Port P01 - Data Direction Register
DDR01
R/W
000432H
I/O Port P02 - Data Direction Register
DDR02
R/W
000433H
I/O Port P03 - Data Direction Register
DDR03
R/W
000434H
Reserved
Document Number: 002-04592 Rev. *C
CMPR
R/W
R/W
-
-
Page 26 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 11 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000435H
I/O Port P05 - Data Direction Register
DDR05
R/W
000436H
I/O Port P06 - Data Direction Register
DDR06
R/W
000437H
I/O Port P07 - Data Direction Register
DDR07
R/W
000438H000443H
Reserved
000444H
I/O Port P00 - Port Input Enable Register
PIER00
R/W
000445H
I/O Port P01 - Port Input Enable Register
PIER01
R/W
000446H
I/O Port P02 - Port Input Enable Register
PIER02
R/W
000447H
I/O Port P03 - Port Input Enable Register
PIER03
R/W
000448H
Reserved
000449H
I/O Port P05 - Port Input Enable Register
PIER05
R/W
00044AH
I/O Port P06 - Port Input Enable Register
PIER06
R/W
00044BH
I/O Port P07 - Port Input Enable Register
PIER07
R/W
00044CH000457H
Reserved
000458H
I/O Port P00 - Port Input Level Register
PILR00
R/W
000459H
I/O Port P01 - Port Input Level Register
PILR01
R/W
00045AH
I/O Port P02 - Port Input Level Register
PILR02
R/W
00045BH
I/O Port P03 - Port Input Level Register
PILR03
R/W
00045CH
Reserved
00045DH
I/O Port P05 - Port Input Level Register
PILR05
R/W
00045EH
I/O Port P06 - Port Input Level Register
PILR06
R/W
00045FH
I/O Port P07 - Port Input Level Register
PILR07
R/W
000460H00046BH
Reserved
00046CH
I/O Port P00 - Extended Port Input Level Register
EPILR00
R/W
00046DH
I/O Port P01 - Extended Port Input Level Register
EPILR01
R/W
00046EH
I/O Port P02 - Extended Port Input Level Register
EPILR02
R/W
00046FH
I/O Port P03 - Extended Port Input Level Register
EPILR03
R/W
000470H
Reserved
000471H
I/O Port P05 - Extended Port Input Level Register
EPILR05
R/W
000472H
I/O Port P06 - Extended Port Input Level Register
EPILR06
R/W
Document Number: 002-04592 Rev. *C
-
-
-
-
-
-
Page 27 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 12 of 22)
Address
Register
Abbreviation
8-bit access
Access
000473H
I/O Port P07 - Extended Port Input Level Register
000474H00047FH
Reserved
000480H
I/O Port P00 - Port Output Drive Register
PODR00
R/W
000481H
I/O Port P01 - Port Output Drive Register
PODR01
R/W
000482H
I/O Port P02 - Port Output Drive Register
PODR02
R/W
000483H
I/O Port P03 - Port Output Drive Register
PODR03
R/W
000484H
Reserved
000485H
I/O Port P05 - Port Output Drive Register
PODR05
R/W
000486H
I/O Port P06 - Port Output Drive Register
PODR06
R/W
000487H
I/O Port P07 - Port Output Drive Register
PODR07
R/W
000488H0004A7H
Reserved
0004A8H
I/O Port P00 - Pull-Up resistor Control Register
PUCR00
R/W
0004A9H
I/O Port P01 - Pull-Up resistor Control Register
PUCR01
R/W
0004AAH
I/O Port P02 - Pull-Up resistor Control Register
PUCR02
R/W
0004ABH
I/O Port P03 - Pull-Up resistor Control Register
PUCR03
R/W
0004ACH
Reserved
0004ADH
I/O Port P05 - Pull-Up resistor Control Register
PUCR05
R/W
0004AEH
I/O Port P06 - Pull-Up resistor Control Register
PUCR06
R/W
0004AFH
I/O Port P07 - Pull-Up resistor Control Register
PUCR07
R/W
0004B0H0004BBH
Reserved
0004BCH
I/O Port P00 - External Pin State Register
EPSR00
R
0004BDH
I/O Port P01 - External Pin State Register
EPSR01
R
0004BEH
I/O Port P02 - External Pin State Register
EPSR02
R
0004BFH
I/O Port P03 - External Pin State Register
EPSR03
R
0004C0H
Reserved
0004C1H
I/O Port P05 - External Pin State Register
EPSR05
R
0004C2H
I/O Port P06 - External Pin State Register
EPSR06
R
0004C3H
I/O Port P07 - External Pin State Register
EPSR07
R
Document Number: 002-04592 Rev. *C
EPILR07
Abbreviation
16-bit access
R/W
-
-
-
-
-
-
Page 28 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 13 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0004C4H0004CFH
Reserved
0004D0H
ADC analog input enable register 0
ADER0
R/W
0004D1H
ADC analog input enable register 1
ADER1
R/W
0004D2H
ADC analog input enable register 2
ADER2
R/W
0004D3H
ADC analog input enable register 3
ADER3
R/W
0004D4H
ADC analog input enable register 4
ADER4
R/W
0004D5H
Reserved
0004D6H
Peripheral Resource Relocation Register 0
PRRR0
R/W
0004D7H
Peripheral Resource Relocation Register 1
PRRR1
R/W
0004D8H
Peripheral Resource Relocation Register 2
PRRR2
R/W
0004D9H
Peripheral Resource Relocation Register 3
PRRR3
R/W
0004DAH
Peripheral Resource Relocation Register 4
PRRR4
R/W
0004DBH
Peripheral Resource Relocation Register 5
PRRR5
R/W
0004DCH
Peripheral Resource Relocation Register 6
PRRR6
R/W
0004DDH
Peripheral Resource Relocation Register 7
PRRR7
R/W
0004DEH
Peripheral Resource Relocation Register 8
PRRR8
R/W
0004DFH
Peripheral Resource Relocation Register 9
PRRR9
R/W
0004E0H
RTC - Sub Second Register L
WTBRL0
0004E1H
RTC - Sub Second Register M
WTBRH0
R/W
0004E2H
RTC - Sub-Second Register H
WTBR1
R/W
0004E3H
RTC - Second Register
WTSR
R/W
0004E4H
RTC - Minutes
WTMR
R/W
0004E5H
RTC - Hour
WTHR
R/W
0004E6H
RTC - Timer Control Extended Register
WTCER
R/W
0004E7H
RTC - Clock select register
WTCKSR
R/W
0004E8H
RTC - Timer Control Register Low
WTCRL
0004E9H
RTC - Timer Control Register High
WTCRH
R/W
0004EAH
CAL - Calibration unit Control register
CUCR
R/W
0004EBH
Reserved
0004ECH
CAL - Duration Timer Data Register Low
Document Number: 002-04592 Rev. *C
-
-
WTBR0
WTCR
R/W
R/W
CUTDL
CUTD
R/W
Page 29 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 14 of 22)
Address
Register
Abbreviation
8-bit access
0004EDH
CAL - Duration Timer Data Register High
CUTDH
0004EEH
CAL - Calibration Timer Register 2 Low
CUTR2L
0004EFH
CAL - Calibration Timer Register 2 High
CUTR2H
0004F0H
CAL - Calibration Timer Register 1 Low
CUTR1L
0004F1H
CAL - Calibration Timer Register 1 High
CUTR1H
0004F2H0004F9H
Reserved
0004FAH
RLT - Timer input select (for Cascading)
0004FBH-00
04FFH
Abbreviation
16-bit access
Access
R/W
CUTR2
R
R
CUTR1
R
R
-
TMISR
R/W
Reserved
-
000500H
FRT2 - Data register of free-running timer
000501H
FRT2 - Data register of free-running timer
000502H
FRT2 - Control status register of free-running timer Low
TCCSL2
000503H
FRT2 - Control status register of free-running timer High
TCCSH2
000504H
FRT3 - Data register of free-running timer
000505H
FRT3 - Data register of free-running timer
000506H
FRT3 - Control status register of free-running timer Low
TCCSL3
000507H
FRT3 - Control status register of free-running timer High
TCCSH3
000508H000513H
Reserved
000514H
ICU8/ICU9 - Control Status Register
ICS89
R/W
000515H
ICU8/ICU9 - Edge Register
ICE89
R/W
000516H
ICU8 - Capture Register Low
IPCPL8
000517H
ICU8 - Capture Register High
IPCPH8
000518H
ICU9 - Capture Register Low
IPCPL9
000519H
ICU9 - Capture Register High
IPCPH9
R
00051AH
ICU10/ICU11 - Control Status Register
ICS1011
R/W
00051BH
ICU10/ICU11 - Edge Register
ICE1011
R/W
00051CH
ICU10 - Capture Register Low
IPCPL10
00051DH
ICU10 - Capture Register High
IPCPH10
00051EH
ICU11 - Capture Register Low
IPCPL11
00051FH
ICU11 - Capture Register High
IPCPH11
Document Number: 002-04592 Rev. *C
TCDT2
R/W
R/W
TCCS2
R/W
R/W
TCDT3
R/W
R/W
TCCS3
R/W
R/W
-
IPCP8
R
R
IPCP9
IPCP10
R
R
R
IPCP11
R
R
Page 30 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 15 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000520H00053DH
Reserved
00053EH
USART7 - Serial Mode Register
SMR7
R/W
00053FH
USART7 - Serial Control Register
SCR7
R/W
000540H
USART7 - Serial TX Register
TDR7
W
000540H
USART7 - Serial RX Register
RDR7
R
000541H
USART7 - Serial Status Register
SSR7
R/W
000542H
USART7 - Ext. Control/Com. Register
ECCR7
R/W
000543H
USART7 - Ext. Status Com. Register
ESCR7
R/W
000544H
USART7 - Baud Rate Generator Register Low
BGRL7
000545H
USART7 - Baud Rate Generator Register High
BGRH7
R/W
000546H
USART7 - Extended Serial Interrupt Register
ESIR7
R/W
000547H
Reserved
000548H
USART8 - Serial Mode Register
SMR8
R/W
000549H
USART8 - Serial Control Register
SCR8
R/W
00054AH
USART8 - Serial TX Register
TDR8
W
00054AH
USART8 - Serial RX Register
RDR8
R
00054BH
USART8 - Serial Status Register
SSR8
R/W
00054CH
USART8 - Ext. Control/Com. Register
ECCR8
R/W
00054DH
USART8 - Ext. Status Com. Register
ESCR8
R/W
00054EH
USART8 - Baud Rate Generator Register Low
BGRL8
00054FH
USART8 - Baud Rate Generator Register High
BGRH8
R/W
000550H
USART8 - Extended Serial Interrupt Register
ESIR8
R/W
000551H000563H
Reserved
000564H
PPG6 - Timer register
000565H
PPG6 - Timer register
000566H
PPG6 - Period setting register
000567H
PPG6 - Period setting register
000568H
PPG6 - Duty cycle register
000569H
PPG6 - Duty cycle register
Document Number: 002-04592 Rev. *C
-
BGR7
R/W
-
BGR8
R/W
PTMR6
R
R
PCSR6
W
W
PDUT6
W
W
Page 31 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 16 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
PCN6
R/W
00056AH
PPG6 - Control status register Low
PCNL6
00056BH
PPG6 - Control status register High
PCNH6
00056CH
PPG7 - Timer register
00056DH
PPG7 - Timer register
00056EH
PPG7 - Period setting register
00056FH
PPG7 - Period setting register
000570H
PPG7 - Duty cycle register
000571H
PPG7 - Duty cycle register
000572H
PPG7 - Control status register Low
PCNL7
000573H
PPG7 - Control status register High
PCNH7
000574H
PPG11-PPG8 - General Control register 1 Low
GCN1L2
000575H
PPG11-PPG8 - General Control register 1 High
GCN1H2
000576H
PPG11-PPG8 - General Control register 2 Low
GCN2L2
000577H
PPG11-PPG8 - General Control register 2 High
GCN2H2
000578H
PPG8 - Timer register
000579H
PPG8 - Timer register
00057AH
PPG8 - Period setting register
00057BH
PPG8 - Period setting register
00057CH
PPG8 - Duty cycle register
00057DH
PPG8 - Duty cycle register
00057EH
PPG8 - Control status register Low
PCNL8
00057FH
PPG8 - Control status register High
PCNH8
000580H
PPG9 - Timer register
000581H
PPG9 - Timer register
000582H
PPG9 - Period setting register
000583H
PPG9 - Period setting register
000584H
PPG9 - Duty cycle register
000585H
PPG9 - Duty cycle register
000586H
PPG9 - Control status register Low
PCNL9
000587H
PPG9 - Control status register High
PCNH9
Document Number: 002-04592 Rev. *C
R/W
PTMR7
R
R
PCSR7
W
W
PDUT7
W
W
PCN7
R/W
R/W
GCN12
R/W
R/W
GCN22
R/W
R/W
PTMR8
R
R
PCSR8
W
W
PDUT8
W
W
PCN8
R/W
R/W
PTMR9
R
R
PCSR9
W
W
PDUT9
W
W
PCN9
R/W
R/W
Page 32 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 17 of 22)
Address
Register
Abbreviation
8-bit access
000588H000597H
Reserved
000598H
PPG15-PPG12 - General Control register 1 Low
GCN1L3
000599H
PPG15-PPG12 - General Control register 1 High
GCN1H3
00059AH
PPG15-PPG12 - General Control register 2 Low
GCN2L3
00059BH
PPG15-PPG12 - General Control register 2 High
GCN2H3
00059CH
PPG12 - Timer register
00059DH
PPG12 - Timer register
00059EH
PPG12 - Period setting register
00059FH
PPG12 - Period setting register
0005A0H
PPG12 - Duty cycle register
0005A1H
PPG12 - Duty cycle register
0005A2H
PPG12 - Control status register Low
PCNL12
0005A3H
PPG12 - Control status register High
PCNH12
0005A4H0005ABH
Reserved
0005ACH
PPG14 - Timer register
0005ADH
PPG14 - Timer register
0005AEH
PPG14 - Period setting register
0005AFH
PPG14 - Period setting register
0005B0H
PPG14 - Duty cycle register
0005B1H
PPG14 - Duty cycle register
0005B2H
PPG14 - Control status register Low
PCNL14
0005B3H
PPG14 - Control status register High
PCNH14
0005B4H0005BBH
Reserved
0005BCH
PPG19-PPG16 - General Control register 1 Low
GCN1L4
0005BDH
PPG19-PPG16 - General Control register 1 High
GCN1H4
0005BEH
PPG19-PPG16 - General Control register 2 Low
GCN2L4
0005BFH
PPG19-PPG16 - General Control register 2 High
GCN2H4
0005C0H
PPG16 - Timer register
0005C1H
PPG16 - Timer register
Document Number: 002-04592 Rev. *C
Abbreviation
16-bit access
Access
-
GCN13
R/W
R/W
GCN23
R/W
R/W
PTMR12
R
R
PCSR12
W
W
PDUT12
W
W
PCN12
R/W
R/W
-
PTMR14
R
R
PCSR14
W
W
PDUT14
W
W
PCN14
R/W
R/W
-
GCN14
R/W
R/W
GCN24
R/W
R/W
PTMR16
R
R
Page 33 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 18 of 22)
Address
Register
Abbreviation
8-bit access
0005C2H
PPG16 - Period setting register
0005C3H
PPG16 - Period setting register
0005C4H
PPG16 - Duty cycle register
0005C5H
PPG16 - Duty cycle register
0005C6H
PPG16 - Control status register Low
PCNL16
0005C7H
PPG16 - Control status register High
PCNH16
0005C8H
PPG17 - Timer register
0005C9H
PPG17 - Timer register
0005CAH
PPG17 - Period setting register
0005CBH
PPG17 - Period setting register
0005CCH
PPG17 - Duty cycle register
0005CDH
PPG17 - Duty cycle register
0005CEH
PPG17 - Control status register Low
PCNL17
0005CFH
PPG17 - Control status register High
PCNH17
0005D0H
PPG18 - Timer register
0005D1H
PPG18 - Timer register
0005D2H
PPG18 - Period setting register
0005D3H
PPG18 - Period setting register
0005D4H
PPG18 - Duty cycle register
0005D5H
PPG18 - Duty cycle register
0005D6H
PPG18 - Control status register Low
PCNL18
0005D7H
PPG18 - Control status register High
PCNH18
0005D8H
PPG19 - Timer register
0005D9H
PPG19 - Timer register
0005DAH
PPG19 - Period setting register
0005DBH
PPG19 - Period setting register
0005DCH
PPG19 - Duty cycle register
0005DDH
PPG19 - Duty cycle register
0005DEH
PPG19 - Control status register Low
PCNL19
0005DFH
PPG19 - Control status register High
PCNH19
Document Number: 002-04592 Rev. *C
Abbreviation
16-bit access
Access
PCSR16
W
W
PDUT16
W
W
PCN16
R/W
R/W
PTMR17
R
R
PCSR17
W
W
PDUT17
W
W
PCN17
R/W
R/W
PTMR18
R
R
PCSR18
W
W
PDUT18
W
W
PCN18
R/W
R/W
PTMR19
R
R
PCSR19
W
W
PDUT19
W
W
PCN19
R/W
R/W
Page 34 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 19 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0005E0H00065FH
Reserved
000660H
Peripheral Resource Relocation Register 10
PRRR10
R/W
000661H
Peripheral Resource Relocation Register 11
PRRR11
R/W
000662H
Peripheral Resource Relocation Register 12
PRRR12
R/W
000663H
Peripheral Resource Relocation Register 13
PRRR13
W
000664H0008FFH
Reserved
000900H
CAN2 - Control register Low
CTRLRL2
000901H
CAN2 - Control register High (reserved)
CTRLRH2
000902H
CAN2 - Status register Low
STATRL2
000903H
CAN2 - Status register High (reserved)
STATRH2
000904H
CAN2 - Error Counter Low (Transmit)
ERRCNTL2
000905H
CAN2 - Error Counter High (Receive)
ERRCNTH2
000906H
CAN2 - Bit Timing Register Low
BTRL2
000907H
CAN2 - Bit Timing Register High
BTRH2
000908H
CAN2 - Interrupt Register Low
INTRL2
000909H
CAN2 - Interrupt Register High
INTRH2
00090AH
CAN2 - Test Register Low
TESTRL2
00090BH
CAN2 - Test Register High (reserved)
TESTRH2
00090CH
CAN2 - BRP Extension register Low
BRPERL2
00090DH
CAN2 - BRP Extension register High (reserved)
BRPERH2
00090EH00090FH
Reserved
000910H
CAN2 - IF1 Command request register Low
IF1CREQL2
000911H
CAN2 - IF1 Command request register High
IF1CREQH2
000912H
CAN2 - IF1 Command Mask register Low
IF1CMSKL2
000913H
CAN2 - IF1 Command Mask register High (reserved)
IF1CMSKH2
000914H
CAN2 - IF1 Mask 1 Register Low
IF1MSK1L2
000915H
CAN2 - IF1 Mask 1 Register High
IF1MSK1H2
000916H
CAN2 - IF1 Mask 2 Register Low
IF1MSK2L2
000917H
CAN2 - IF1 Mask 2 Register High
IF1MSK2H2
Document Number: 002-04592 Rev. *C
-
CTRLR2
R/W
R
STATR2
R/W
R
ERRCNT2
R
R
BTR2
R/W
R/W
INTR2
R
R
TESTR2
R/W
R
BRPER2
R/W
R
-
IF1CREQ2
R/W
R/W
IF1CMSK2
R/W
R
IF1MSK12
R/W
R/W
IF1MSK22
R/W
R/W
Page 35 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 20 of 22)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
IF1ARB12
R/W
000918H
CAN2 - IF1 Arbitration 1 Register Low
IF1ARB1L2
000919H
CAN2 - IF1 Arbitration 1 Register High
IF1ARB1H2
00091AH
CAN2 - IF1 Arbitration 2 Register Low
IF1ARB2L2
00091BH
CAN2 - IF1 Arbitration 2 Register High
IF1ARB2H2
00091CH
CAN2 - IF1 Message Control Register Low
IF1MCTRL2
00091DH
CAN2 - IF1 Message Control Register High
IF1MCTRH2
00091EH
CAN2 - IF1 Data A1 Low
IF1DTA1L2
00091FH
CAN2 - IF1 Data A1 High
IF1DTA1H2
000920H
CAN2 - IF1 Data A2 Low
IF1DTA2L2
000921H
CAN2 - IF1 Data A2 High
IF1DTA2H2
000922H
CAN2 - IF1 Data B1 Low
IF1DTB1L2
000923H
CAN2 - IF1 Data B1 High
IF1DTB1H2
000924H
CAN2 - IF1 Data B2 Low
IF1DTB2L2
000925H
CAN2 - IF1 Data B2 High
IF1DTB2H2
000926H00093FH
Reserved
000940H
CAN2 - IF2 Command request register Low
IF2CREQL2
000941H
CAN2 - IF2 Command request register High
IF2CREQH2
000942H
CAN2 - IF2 Command Mask register Low
IF2CMSKL2
000943H
CAN2 - IF2 Command Mask register High (reserved)
IF2CMSKH2
000944H
CAN2 - IF2 Mask 1 Register Low
IF2MSK1L2
000945H
CAN2 - IF2 Mask 1 Register High
IF2MSK1H2
000946H
CAN2 - IF2 Mask 2 Register Low
IF2MSK2L2
000947H
CAN2 - IF2 Mask 2 Register High
IF2MSK2H2
000948H
CAN2 - IF2 Arbitration 1 Register Low
IF2ARB1L2
000949H
CAN2 - IF2 Arbitration 1 Register High
IF2ARB1H2
00094AH
CAN2 - IF2 Arbitration 2 Register Low
IF2ARB2L2
00094BH
CAN2 - IF2 Arbitration 2 Register High
IF2ARB2H2
00094CH
CAN2 - IF2 Message Control Register Low
IF2MCTRL2
00094DH
CAN2 - IF2 Message Control Register High
IF2MCTRH2
00094EH
CAN2 - IF2 Data A1 Low
IF2DTA1L2
Document Number: 002-04592 Rev. *C
R/W
IF1ARB22
R/W
R/W
IF1MCTR2
R/W
R/W
IF1DTA12
R/W
R/W
IF1DTA22
R/W
R/W
IF1DTB12
R/W
R/W
IF1DTB22
R/W
R/W
-
IF2CREQ2
R/W
R/W
IF2CMSK2
R/W
R
IF2MSK12
R/W
R/W
IF2MSK22
R/W
R/W
IF2ARB12
R/W
R/W
IF2ARB22
R/W
R/W
IF2MCTR2
R/W
R/W
IF2DTA12
R/W
Page 36 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 21 of 22)
Address
Register
Abbreviation
8-bit access
00094FH
CAN2 - IF2 Data A1 High
IF2DTA1H2
000950H
CAN2 - IF2 Data A2 Low
IF2DTA2L2
000951H
CAN2 - IF2 Data A2 High
IF2DTA2H2
000952H
CAN2 - IF2 Data B1 Low
IF2DTB1L2
000953H
CAN2 - IF2 Data B1 High
IF2DTB1H2
000954H
CAN2 - IF2 Data B2 Low
IF2DTB2L2
000955H
CAN2 - IF2 Data B2 High
IF2DTB2H2
000956H00097FH
Reserved
000980H
CAN2 - Transmission Request 1 Register Low
TREQR1L2
000981H
CAN2 - Transmission Request 1 Register High
TREQR1H2
000982H
CAN2 - Transmission Request 2 Register Low
TREQR2L2
000983H
CAN2 - Transmission Request 2 Register High
TREQR2H2
000984H00098FH
Reserved
000990H
CAN2 - New Data 1 Register Low
NEWDT1L2
000991H
CAN2 - New Data 1 Register High
NEWDT1H2
000992H
CAN2 - New Data 2 Register Low
NEWDT2L2
000993H
CAN2 - New Data 2 Register High
NEWDT2H2
000994H00099FH
Reserved
0009A0H
CAN2 - Interrupt Pending 1 Register Low
INTPND1L2
0009A1H
CAN2 - Interrupt Pending 1 Register High
INTPND1H2
0009A2H
CAN2 - Interrupt Pending 2 Register Low
INTPND2L2
0009A3H
CAN2 - Interrupt Pending 2 Register High
INTPND2H2
0009A4H0009AFH
Reserved
0009B0H
CAN2 - Message Valid 1 Register Low
MSGVAL1L2
0009B1H
CAN2 - Message Valid 1 Register High
MSGVAL1H2
0009B2H
CAN2 - Message Valid 2 Register Low
MSGVAL2L2
0009B3H
CAN2 - Message Valid 2 Register High
MSGVAL2H2
Document Number: 002-04592 Rev. *C
Abbreviation
16-bit access
Access
R/W
IF2DTA22
R/W
R/W
IF2DTB12
R/W
R/W
IF2DTB22
R/W
R/W
-
TREQR12
R
R
TREQR22
R
R
-
NEWDT12
R
R
NEWDT22
R
R
-
INTPND12
R
R
INTPND22
R
R
-
MSGVAL12
R
R
MSGVAL22
R
R
Page 37 of 82
CY96310 Series
I/O map CY96(F)315x (Sheet 22 of 22)
Address
Register
0009B4H0009CDH
Reserved
0009CEH
CAN2 - Output enable register
0009CFH000BFFH
Reserved
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
-
COER2
R/W
-
Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved address results
in reading ‘X’.
Registers of resources which are described in this table, but which are not supported by the device, should also be handled
as “Reserved”.
Document Number: 002-04592 Rev. *C
Page 38 of 82
CY96310 Series
12. Interrupt Vector Table
Vector
number
Offset in
vector table
Vector name
Cleared by
DMA
Index in ICR
to program
0
3FCH
CALLV0
No
-
1
3F8H
CALLV1
No
-
2
3F4H
CALLV2
No
-
3
3F0H
CALLV3
No
-
4
3ECH
CALLV4
No
-
5
3E8H
CALLV5
No
-
6
3E4H
CALLV6
No
-
7
3E0H
CALLV7
No
-
8
3DCH
RESET
No
-
9
3D8H
INT9
No
-
10
3D4H
EXCEPTION
No
-
11
3D0H
NMI
No
-
12
3CCH
DLY
No
12
Delayed Interrupt
13
3C8H
RC_TIMER
No
13
RC Timer
14
3C4H
MC_TIMER
No
14
Main Clock Timer
15
3C0H
SC_TIMER
No
15
Sub Clock Timer
16
3BCH
PLL_UNLOCK
No
16
Reserved
17
3B8H
EXTINT0
Yes
17
External Interrupt 0
18
3B4H
19
3B0H
EXTINT2
Yes
19
External Interrupt 2
20
3ACH
EXTINT3
Yes
20
External Interrupt 3
21
3A8H
EXTINT4
Yes
21
External Interrupt 4
22
3A4H
23
3A0H
EXTINT7
Yes
23
External Interrupt 7
24
39CH
EXTINT8
Yes
24
External Interrupt 8
25
398H
EXTINT9
Yes
25
External Interrupt 9
26
394H
EXTINT10
Yes
26
External Interrupt 10
27
390H
EXTINT11
Yes
27
External Interrupt 11
28
38CH
EXTINT12
Yes
28
External Interrupt 12
29
388H
EXTINT13
Yes
29
External Interrupt 13
30
384H
Reserved
31
380H
Reserved
32
37CH
Reserved
33
378H
CAN2
No
33
CAN Controller 2
34
374H
PPG0
Yes
34
Programmable Pulse Generator 0
35
370H
PPG1
Yes
35
Programmable Pulse Generator 1
Description
Non-Maskable Interrupt
Reserved
Reserved
Document Number: 002-04592 Rev. *C
Page 39 of 82
CY96310 Series
Vector
number
Offset in
vector table
36
36CH
37
368H
PPG3
Yes
37
Programmable Pulse Generator 3
38
364H
PPG4
Yes
38
Programmable Pulse Generator 4
39
360
40
35CH
PPG6
Yes
40
Programmable Pulse Generator 6
41
358H
PPG7
Yes
41
Programmable Pulse Generator 7
42
354H
PPG8
Yes
42
Programmable Pulse Generator 8
43
350H
PPG9
Yes
43
Programmable Pulse Generator 9
44
34CH
Reserved
45
348H
Reserved
46
344H
47
340H
48
33CH
49
338H
50
334H
PPG16
Yes
50
Programmable Pulse Generator 16
51
330H
PPG17
Yes
51
Programmable Pulse Generator 17
52
32CH
PPG18
Yes
52
Programmable Pulse Generator 18
53
328H
PPG19
Yes
53
Programmable Pulse Generator 19
54
324H
RLT0
Yes
54
Reload Timer 0
55
320H
RLT1
Yes
55
Reload Timer 1
56
31CH
RLT2
Yes
56
Reload Timer 2
57
318H
RLT3
Yes
57
Reload Timer 3
58
314H
PPGRLT
Yes
58
Reload Timer 6 - dedicated for PPG
59
310H
ICU0
Yes
59
Input Capture Unit 0
60
30CH
ICU1
Yes
60
Input Capture Unit 1
61
308H
Reserved
62
304H
Reserved
63
300H
ICU4
Yes
63
Input Capture Unit 4
64
2FCH
ICU5
Yes
64
Input Capture Unit 5
65
2F8H
ICU6
Yes
65
Input Capture Unit 6
66
2F4H
Reserved
67
2F0H
Reserved
68
2ECH
ICU9
Yes
68
Input Capture Unit 9
69
2E8H
ICU10
Yes
69
Input Capture Unit 10
70
2E4H
Reserved
71
2E0H
Reserved
72
2DCH
Reserved
Vector name
Cleared by
DMA
Index in ICR
to program
Description
Reserved
Reserved
PPG12
Yes
46
Programmable Pulse Generator 12
Reserved
PPG14
Yes
48
Programmable Pulse Generator 14
Reserved
Document Number: 002-04592 Rev. *C
Page 40 of 82
CY96310 Series
Vector
number
Offset in
vector table
Vector name
Cleared by
DMA
Index in ICR
to program
73
2D8H
OCU6
Yes
73
Output Compare Unit 6
74
2D4H
OCU7
Yes
74
Output Compare Unit 7
75
2D0H
Reserved
76
2CCH
Reserved
77
2C8H
FRT0
Yes
77
Free Running Timer 0
78
2C4H
FRT1
Yes
78
Free Running Timer 1
79
2C0H
FRT2
Yes
79
Free Running Timer 2
80
2BCH
FRT3
Yes
80
Free Running Timer 3
81
2B8H
RTC0
No
81
Real Timer Clock
82
2B4H
CAL0
No
82
Clock Calibration Unit
83
2B0H
84
2ACH
ADC0
Yes
84
A/D Converter
85
2A8H
LINR2
Yes
85
LIN USART 2 RX
86
2A4H
LINT2
Yes
86
LIN USART 2 TX
87
2A0H
Reserved
88
29CH
Reserved
89
298H
LINR7
Yes
89
LIN USART 7 RX
90
294H
LINT7
Yes
90
LIN USART 7 TX
91
290H
LINR8
Yes
91
LIN USART 8 RX
92
28CH
LINT8
Yes
92
LIN USART 8 TX
93
288H
FLASH_A
No
93
Flash memory A (only Flash devices)
Description
Reserved
Document Number: 002-04592 Rev. *C
Page 41 of 82
CY96310 Series
13. Handling Devices
Special care is required for the following when handling the device:
•
•
•
•
•
•
•
•
•
•
•
•
Latch-up prevention
Unused pins handling
External clock usage
Unused sub clock signal
Notes on PLL clock mode operation
Power supply pins (VCC/VSS)
Crystal oscillator circuit
Turn on sequence of power supply to A/D converter and analog inputs
Pin handling when not using the A/D converter
Notes on energization
Stabilization of power supply voltage
Serial communication
13.1 Latch-up prevention
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC pins and VSS pins.
Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
13.2 Unused pins handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0).
Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device.
They must therefore be pulled up or pulled down through resistors. To prevent latch-up, those resistors should be more than 2 k.
Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or
external pull-up/pull-down resistor as described above.
13.3 External clock usage
The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for
detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows:
1. Single phase external clock
• When using a single phase external clock, X0 (X0A) pin must be driven and X1 (X1A) pin left open.
X0
X1
Document Number: 002-04592 Rev. *C
Page 42 of 82
CY96310 Series
2. Opposite phase external clock
• When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the opposite phase to
the X0 (X0A) pins.
X0
X1
13.4 Unused sub clock signal
If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A pin and the X1A pin
must be left open.
13.5 Notes on PLL clock mode operation
If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts
to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed.
13.6 Power supply pins (VCC/VSS)
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or
VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range.
VCC and VSS must be connected to the device from the power supply with lowest possible impedance.
As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 F between VCC and VSS as close
as possible to VCC and VSS pins.
13.7 Crystal oscillator and ceramic resonator circuit
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest
possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost
effort, that the lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area
for stabilizing the operation.
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially
when using low-Q resonators at higher frequencies.
13.8 Turn on sequence of power supply to A/D converter and analog inputs
It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital power
supply (VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, the voltage
must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable).
13.9 Pin handling when not using the A/D converter
It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS.
13.10 Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than
50s from 0.2 V to 2.7 V.
Document Number: 002-04592 Rev. *C
Page 43 of 82
CY96310 Series
13.11 Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage, a malfunction may
occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be
stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10%
of the standard Vcc power supply voltage and the transient fluctuation rate becomes 0.1V/s or less in instantaneous fluctuation for
power supply switching.
13.12 Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit the data if an error
occurs.
Document Number: 002-04592 Rev. *C
Page 44 of 82
CY96310 Series
14. Electrical Characteristics
14.1 Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS - 0.3
VSS + 6.0
V
AVCC
VSS - 0.3
VSS + 6.0
V
VCC = AVCC *1
AVRH,
AVRL
VSS - 0.3
VSS + 6.0
V
AVCC AVRH, AVCC AVRL, AVRH
AVRL, AVRL AVSS
Input voltage
VI
VSS - 0.3
VSS + 6.0
V
VI VCC + 0.3V *2
Output voltage
VO
VSS - 0.3
VSS + 6.0
V
VO VCC + 0.3V *2
ICLAMP
-4.0
+4.0
mA
Applicable to general purpose
I/O pins *3
|ICLAMP|
-
40
mA
Applicable to general purpose
I/O pins *3
IOL1
-
15
mA
Normal outputs with driving strength
set to 5mA
“L” level average output current
IOLAV1
-
5
mA
Normal outputs with driving strength
set to 5mA
“L” level maximum overall output current
IOL1
-
100
mA
Normal outputs
IOLAV1
-
50
mA
Normal outputs
IOH1
-
-15
”H” level average output current
IOHAV1
-
-5
mA
Normal outputs with driving strength
set to 5mA
”H” level maximum overall output current
IOH1
-
-100
mA
Normal outputs
IOHAV1
-
-50
mA
Normal outputs
-
220*5
mW TA = 105oC
-
450*5
mW TA = 85oC
-
615*5
mW TA = 70oC
-
280*5
mW
TA=125oC, no Flash program/
erase *6
-
500*5
mW
TA=105oC, no Flash program/
erase *6
0
+70
-40
+105
-40
+125
-55
+150
Power supply voltage
AD Converter voltage references
Maximum Clamp Current
Total Maximum Clamp Current
“L” level maximum output current
“L” level average overall output current
”H” level maximum output current
”H” level average overall output current
Permitted Power dissipation (Flash
devices) *4
Operating ambient temperature
Storage temperature
Document Number: 002-04592 Rev. *C
PD
TA
TSTG
mA
Normal outputs with driving strength
set to 5mA
CY96V300C
oC
*6
oC
Page 45 of 82
CY96310 Series
*1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog
inputs does not exceed AVCC neither when the power is switched on.
*2: VI and VO should not exceed VCC + 0.3 V. VI should also not exceed the specified ratings. However if the maximum current
to/from a input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/output
voltages of standard ports depend on VCC.
*3: Applicable to all general purpose I/O pins (Pnn_m)
Use within recommended operating conditions.
Use at DC voltage (current)
The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller
pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass
through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided
from the pins, so that incomplete operation may result.
Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage
may not be sufficient to operate the Power reset (except devices with persistent low voltage reset in internal vector mode).
Sample recommended circuits:
Protective Diode
VCC
Limiting
resistance
P-ch
+B input (0V to 16V)
N-ch
R
*4: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance
of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports)
PINT = VCC * (ICC + IA) (internal power dissipation)
ICC is the total core current consumption into VCC as described in the “3. DC characteristics” and depends on the selected
operation mode and clock frequency and the usage of functions like Flash programming or the clock modulator.
IA is the analog current consumption into AVCC.
*5: Worst case value for a package mounted on single layer PCB at specified TA without air flow.
*6: Please contact Cypress for reliability limitations when using under these conditions.
WARNING:
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-04592 Rev. *C
Page 46 of 82
CY96310 Series
14.2 Recommended Operating Conditions
Parameter
Symbol
Value
Min
Typ
Max
Unit
Power supply voltage
VCC
3.0
-
5.5
V
Smoothing capacitor at C pin
CS
3.5
4.7
15
F
WARNING:
Remarks
Use a X7R ceramic capacitor or a
capacitor that has similar frequency
characteristics
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Document Number: 002-04592 Rev. *C
Page 47 of 82
CY96310 Series
14.3 DC characteristics
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
VIH
Input H voltage
Pin
Port inputs
Condition
Unit
Typ
Max
0.7
VCC
-
VCC +
0.3
V
VCC 4.5V
0.74
VCC
-
VCC +
0.3
V
VCC < 4.5V
AUTOMOTIVE
Hysteresis input
selected
0.8
VCC
-
VCC +
0.3
V
CMOS Hysteresis
0.7/0.3 input
selected
Pnn_m
VIHX0F
X0
External clock in
“Fast Clock Input
mode”
0.8
VCC
-
VCC +
0.3
V
VIHX0S
X0,X1,
X0A,X1A
External clock in
“oscillation mode”
2.5
-
VCC +
0.3
V
VIHR
RSTX
-
0.8
VCC
-
VCC +
0.3
V
VIHM
MD2-MD0
-
VCC 0.3
-
VCC +
0.3
V
VSS 0.3
-
0.3
VCC
V
VSS 0.3
-
0.5
VCC
V
VSS 0.3
-
0.46
VCC
VIL
Port inputs
Pnn_m
Remarks
Min
CMOS Hysteresis
0.7/0.3 input
selected
Input L voltage
Value
AUTOMOTIVE
Hysteresis input
selected
CMOS Hysteresis input
VCC 4.5V
VCC < 4.5V
VILX0F
X0
External clock in
“Fast Clock Input
mode”
VSS 0.3
-
0.2 VCC
V
VILX0S
X0,X1,
X0A,X1A
External clock in
“oscillation mode”
VSS 0.3
-
0.4
V
VILR
RSTX
-
VSS 0.3
-
0.2 VCC
V
VILM
MD2-MD0
-
VSS 0.3
-
VSS +
0.3
V
VCC 0.5
-
-
V
Driving strength set to
2mA
(PODR:OD=1)
VCC 0.5
-
-
V
Driving strength set to
5mA
(PODR:OD=0)
CMOS Hysteresis input
4.5V VCC 5.5V
VOH2
Normal
outputs
IOH = -2mA
3.0V VCC 4.5V
IOH = -1.6mA
Output H voltage
4.5V VCC 5.5V
VOH5
Normal
outputs
IOH = -5mA
3.0V VCC 4.5V
IOH = -3mA
Document Number: 002-04592 Rev. *C
Page 48 of 82
CY96310 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Pin
Condition
Value
Unit
Remarks
Min
Typ
Max
-
-
0.4
V
Driving strength set to
2mA
(PODR:OD=1)
-
-
0.4
V
Driving strength set to
5mA
(PODR:OD=0)
AVSS, AVRL < VI <
AVCC, AVRH
-1
-
+1
A
Single port pin
VCC 3.3V 10
40
100
160
k
VCC 5.0V 10
25
50
100
k
4.5V VCC 5.5V
VOL2
Normal
outputs
IOL = +2mA
3.0V VCC 4.5V
IOL = +1.6mA
Output L voltage
4.5V VCC 5.5V
VOL5
Normal
outputs
IOL = +5mA
3.0V VCC 4.5V
IOL = +3mA
VSS < VI < VCC
Input leak current
IIL
Pnn_m
Pull-up resistance
RUP
Pnn_m,
RSTX
Document Number: 002-04592 Rev. *C
Page 49 of 82
CY96310 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Value
Condition (at TA)
Symbol
Typ
Max
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1 = 16MHz,
CLKP2 = 8MHz
+25°C
14.5
19.5
1 Flash/ROM wait state
+125°C
16
23
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1 = 32MHz,
CLKP2 = 16MHz
+25°C
23
29
2 Flash/ROM wait states
+125°C
25
33
PLL Run mode with
CLKS1/2 = 48MHz,
CLKB = CLKP1/2 = 24MHz
+25°C
26
38
0 Flash/ROM wait states
+125°C
28
42
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1= 56MHz,
CLKP2 = 28MHz
+25°C
40
51
2 Flash/ROM wait states
+125°C
42
55
PLL Run mode with
CLKS1/2 = 96MHz,
CLKB = CLKP1= 48MHz,
CLKP2 = 24MHz
+25°C
43
56
1 Flash/ROM wait state
+125°C
45
60
Unit
Remarks
mA
(CLKRC and CLKSC stopped)
mA
(CLKRC and CLKSC stopped)
Power supply
current in
Run modes*
ICCPLL
mA
(CLKRC and CLKSC stopped)
mA
(CLKRC and CLKSC stopped.
Core voltage at 1.9V)
mA
(CLKRC and CLKSC stopped.
Core voltage at 1.9V)
Document Number: 002-04592 Rev. *C
Page 50 of 82
CY96310 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Typ
Max
+25°C
4
5
+125°C
4.7
8
+25°C
2.5
3.5
+125°C
3.2
6.5
+25°C
0.18
0.3
+125°C
0.73
3.1
+25°C
0.15
0.25
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power mode,
no Flash programming/
erasing allowed)
+125°C
0.7
3.05
Sub Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 32kHz
+25°C
0.1
0.2
+125°C
0.65
3
Main Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 4MHz
ICCMAIN
1 Flash/ROM wait state
(CLKPLL, CLKSC and CLKRC
stopped)
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 2MHz
ICCRCH
1 Flash/ROM wait state
(CLKMC, CLKPLL and
CLKSC stopped)
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 100kHz,
SMCR:LPMS = 0
1 Flash/ROM wait state
Power supply
current in
Run modes*
Value
Condition (at TA)
Symbol
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power mode)
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 100kHz,
SMCR:LPMS = 1
ICCRCL
mA
mA
Document Number: 002-04592 Rev. *C
mA
1 Flash/ROM wait state
(CLKMC, CLKPLL and
CLKRC stopped, no Flash
programming/erasing
allowed)
Remarks
mA
1 Flash/ROM wait state
ICCSUB
Unit
mA
Page 51 of 82
CY96310 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Typ
Max
+25°C
4
6
+125°C
4.7
9
+25°C
7
9.5
+125°C
8
12.5
+25°C
7
9
+125°C
8
12
PLL Sleep mode with
CLKS1/2 = CLKP1= 56MHz,
CLKP2 = 28MHz
+25°C
11
14.5
(CLKRC and CLKSC stopped.
Core voltage at 1.9V)
+125°C
12
17.5
PLL Sleep mode with
CLKS1/2 = 96MHz,
CLKP1= 48MHz,
CLKP2 = 24MHz
+25°C
12
15
+125°C
13
18
Main Sleep mode with
CLKS1/2 = CLKP1/2 = 4MHz
+25°C
1
1.3
(CLKPLL, CLKSC and CLKRC
stopped)
+125°C
1.6
4.1
RC Sleep mode with
CLKS1/2 = CLKP1/2 = 2MHz
+25°C
0.55
1.1
(CLKMC, CLKPLL and
CLKSC stopped)
+125°C
1.15
3.9
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz,
SMCR:LPMSS = 0
+25°C
0.08
0.2
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power mode)
+125°C
0.59
2.95
RC Sleep mode with CLKS1/2
= CLKP1/2 = 100kHz,
SMCR:LPMSS = 1
+25°C
0.05
0.15
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power mode)
+125°C
0.56
2.9
Sub Sleep mode with
CLKS1/2 = CLKP1/2 = 32kHz
+25°C
0.04
0.12
(CLKMC, CLKPLL and
CLKRC stopped)
+125°C
0.54
2.9
PLL Sleep mode with
CLKS1/2 = CLKP1 = 16MHz,
CLKP2 = 8MHz
(CLKRC and CLKSC stopped)
PLL Sleep mode with
CLKS1/2 = CLKP1 = 32MHz,
CLKP2 = 16MHz
(CLKRC and CLKSC stopped)
PLL Sleep mode with
CLKS1/2 = 48MHz,
CLKP1/2 = 24MHz
ICCSPLL
Power supply
current in
Sleep modes*
(CLKRC and CLKSC stopped)
(CLKRC and CLKSC stopped.
Core voltage at 1.9V)
ICCSMAIN
ICCSRCH
ICCSRCL
Power supply
current in
Sleep modes*
ICCSSUB
Value
Condition (at TA)
Symbol
Document Number: 002-04592 Rev. *C
Unit
Remarks
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Page 52 of 82
CY96310 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Typ
Max
+25°C
1.3
1.8
+125°C
1.9
4.8
Main Timer mode with CLKMC
= 4MHz,
SMCR:LPMSS = 0
+25°C
0.11
0.2
(CLKPLL, CLKRC and CLKSC
stopped. Voltage regulator in
high power mode)
+125°C
0.63
3
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 1
+25°C
0.08
0.15
(CLKPLL, CLKRC and CLKSC
stopped. Voltage regulator in
low power mode)
+125°C
0.6
2.9
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 0
+25°C
0.1
0.2
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power mode)
+125°C
0.63
3
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 1
+25°C
0.07
0.15
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power mode)
+125°C
0.6
2.9
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 0
+25°C
0.06
0.15
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power mode)
+125°C
0.56
2.95
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 1
+25°C
0.03
0.1
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power mode)
+125°C
0.53
2.85
Sub Timer mode with
CLKSC = 32kHz
+25°C
0.035
0.1
(CLKMC, CLKPLL and
CLKRC stopped)
+125°C
0.53
2.85
PLL Timer mode with
CLKMC = 4MHz,
CLKPLL = 48MHz
ICCTPLL
(CLKRC and CLKSC stopped)
Power supply
current in
Timer modes*
ICCTMAIN
ICCTRCH
Power supply
current in
Timer modes*
ICCTRCL
Value
Condition (at TA)
Symbol
ICCTSUB
Document Number: 002-04592 Rev. *C
Unit
Remarks
mA
mA
mA
mA
mA
mA
mA
mA
Page 53 of 82
CY96310 Series
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Power supply
current in Stop Mode
Power supply
current for active
Low Voltage detector
Value
Condition (at TA)
Symbol
Typ
Max
VRCR:LPMB[2:0] = 110B
+25°C
0.02
0.08
(Core voltage at 1.8V)
+125°C
0.52
2.8
VRCR:LPMB[2:0] = 000B
+25°C
0.015
0.06
(Core voltage at 1.2V)
+125°C
0.4
2.3
+25°C
5
10
Unit
Remarks
mA
ICCH
ICCLVD
Low voltage detector enabled
(RCR:LVDE = 1)
mA
+125°C
7
20
A
Must be added to all
current above
Power supply
current for active
Clock modulator
ICCCLOMO
Clock modulator enabled (CMCR:PDX = 1)
-
3
4.5
mA
Must be added to all
current above
Flash Write/Erase
current
ICCFLASH
Current for one Flash module
-
15
40
mA
Must be added to all
current above
Input capacitance
CIN
-
-
5
15
pF
Other than C, AVCC,
AVSS, AVRH, AVRL, VCC,
VSS
* : The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock
connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for
further details about voltage regulator control.
Document Number: 002-04592 Rev. *C
Page 54 of 82
CY96310 Series
14.4 AC Characteristics
Source Clock timing
Parameter
Clock frequency
Clock frequency
Clock frequency
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Symbol
fC
Pin
X0, X1
fFCI
fCL
Value
X0A
Remarks
Typ
Max
3
-
16
MHz When using a crystal oscillator, PLL off
0
-
16
using an opposite phase external clock,
MHz When
PLL off
3.5
-
16
using a crystal oscillator or opposite
MHz When
phase external clock, PLL on
0
-
56
using a single phase external clock in
MHz When
“Fast Clock Input mode” , PLL off
3.5
-
56
using a single phase external clock in
MHz When
“Fast Clock Input mode” , PLL on
32
32.768
100
kHz
When using an oscillation circuit
0
-
100
kHz
When using an opposite phase external clock
0
-
50
kHz
When using a single phase external clock
50
100
200
kHz
When using slow frequency of RC oscillator
1
2
4
X0
X0A, X1A
Unit
Min
Clock frequency
fCR
-
RC clock
stabilization time
tRCSTAB
-
PLL Clock
frequency
fCLKVCO
-
64
-
200
PLL Phase Jitter
TPSKEW
-
-
-
5
ns
For CLKMC (PLL input clock) 4MHz, jitter
coming from external oscillator, crystal or
resonator is not covered
Input clock pulse
width
PWH, PWL
X0,X1
8
-
-
ns
Duty ratio is about 30% to 70%
Input clock pulse
width
PWHL, PWLL
X0A,X1A
5
-
-
s
Document Number: 002-04592 Rev. *C
MHz When using fast frequency of RC oscillator
Applied after any reset and when activating
the RC oscillator.
256 RC clock cycles
VCO output frequency of PLL
MHz Permitted
(CLKVCO)
Page 55 of 82
CY96310 Series
tCYL
VIH
X0
VIL
PWH
PWL
tCYLL
VIH
X0A
VIL
PWH
Document Number: 002-04592 Rev. *C
PWL
Page 56 of 82
CY96310 Series
Internal Clock timing
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Core Voltage Settings
Parameter
Symbol
1.8V
1.9V
Unit
Min
Max
Min
Max
Internal System clock
frequency (CLKS1 and
CLKS2)
fCLKS1, fCLKS2
0
92
0
96
MHz
Internal CPU clock frequency
(CLKB), internal peripheral
clock frequency (CLKP1)
fCLKB, fCLKP1
0
52
0
56
MHz
fCLKP2
0
28
0
32
MHz
Internal peripheral clock
frequency (CLKP2)
Document Number: 002-04592 Rev. *C
Remarks
Page 57 of 82
CY96310 Series
External Reset timing
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Pin
tRSTL
RSTX
Reset input time
Value
Min
Typ
Max
500
-
-
Unit
Remarks
ns
tRSTL
RSTX
0.2 VCC
Document Number: 002-04592 Rev. *C
0.2 VCC
Page 58 of 82
CY96310 Series
Power On Reset timing
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Power on rise time
Power off time
Symbol
Pin
tR
tOFF
Value
Unit
Min
Typ
Max
Vcc
0.05
-
30
ms
Vcc
1
-
-
ms
Remarks
tR
2.7V
VCC
0.2 V
0.2 V
0.2 V
tOFF
If the power supply is changed too rapidly, a power-on reset may occur.
We recommend a smooth startup by restraining voltages when changing the
power supply voltage during operation, as shown in the figure below.
VCC
3V
Document Number: 002-04592 Rev. *C
Rising edge of 50 mV/ms
maximum is allowed
Page 59 of 82
CY96310 Series
External Input timing
(TA = -40°C to 125°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Pin
Value
Condition
INTn(_R)
NMI
Min
Max
200
—
Unit
tINH
tINL
External Interrupt
ns
Pnn_m
Input pulse
width
Used Pin input function
NMI
General Purpose IO
TINn
Reload Timer
—
2*tCLKP1 + 200
(tCLKP1=1/fCLKP1)
TTGn(_R)
ADTG_R
—
ns
PPG Trigger input
AD Converter Trigger
INn
Input Capture
Note : Relocated Resource Inputs have same characteristics
External Pin input
VIH
VIH
tINH
Document Number: 002-04592 Rev. *C
VIL
VIL
tINL
Page 60 of 82
CY96310 Series
USART timing
WARNING:
The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing
described in the different tables must then be increased by 10ns.
(TA = -40°C to 125°C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
Pin
Condition
VCC = AVCC= 4.5V VCC = AVCC= 3.0V to
to 5.5V
4.5V
Min
Max
Min
Max
Unit
Serial clock cycle time
tSCYCI
SCKn
4 tCLKP1
—
4 tCLKP1
—
ns
SCK ↓ → SOT delay time
tSLOVI
SCKn,
SOTn
-20
20
-30
30
ns
SOT → SCK ↑ delay time
tOVSHI
SCKn,
SOTn
N*tCLKP1
- 20 *1
—
N*tCLKP1 30 *1
—
ns
Valid SIN → SCK ↑
tIVSHI
SCKn,
SINn
tCLKP1 +
45
—
tCLKP1 +
55
—
ns
SCK ↑ → Valid SIN hold
time
tSHIXI
SCKn,
SINn
0
—
0
—
ns
Serial clock “L” pulse width
tSLSHE
SCKn
tCLKP1 +
10
—
tCLKP1 +
10
—
ns
Serial clock “H” pulse width
tSHSLE
SCKn
tCLKP1 +
10
—
tCLKP1 +
10
—
ns
SCK ↓ → SOT delay time
tSLOVE
SCKn,
SOTn
—
2 tCLKP1
+ 45
—
2 tCLKP1
+ 55
ns
Valid SIN → SCK ↑
tIVSHE
SCKn,
SINn
tCLKP1/2
+ 10
—
tCLKP1/2 +
10
—
ns
SCK ↑ → Valid SIN hold
time
tSHIXE
SCKn,
SINn
tCLKP1 +
10
—
tCLKP1 +
10
—
ns
SCK fall time
tFE
SCKn
—
20
—
20
ns
SCK rise time
tRE
SCKn
—
20
—
20
ns
Internal Shift
Clock Mode
External Shift
Clock Mode
Notes: • AC characteristic in CLK synchronized mode.
• CL is the load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters.
These parameters are shown in “CY96300 Super series Hardware Manual”.
• tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns
*1: Parameter N depends on tSCYCI and can be calculated as follows:
• if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2
• if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1
Examples:
tSCYCI
N
4*tCLKP1
2
5*tCLKP1, 6*tCLKP1
3
7*tCLKP1, 8*tCLKP1
4
...
...
Document Number: 002-04592 Rev. *C
Page 61 of 82
CY96310 Series
tSCYCI
SCK for
ESCR:SCES = 0
0.8*VCC
0.2*VCC
0.2*VCC
SCK for
ESCR:SCES = 1
0.8*VCC
0.8*VCC
0.2*VCC
tSLOVI
tOVSHI
0.8*VCC
SOT
0.2*VCC
tSHIXI
tIVSHI
SIN
VIH
VIH
VIL
VIL
Internal Shift Clock Mode
tSLSHE
tSHSLE
SCK for
ESCR:SCES = 0
VIH
VIL
VIL
SCK for
ESCR:SCES = 1
VIH
VIH
VIL
tFE
SOT
tSLOVE
VIH
VIL
VIL
tRE
0.8*VCC
0.2*VCC
tIVSHE
SIN
VIH
tSHIXE
VIH
VIH
VIL
VIL
External Shift Clock Mode
Document Number: 002-04592 Rev. *C
Page 62 of 82
CY96310 Series
14.5 Analog Digital Converter
(TA = -40 °C to +125 °C, 3.0 V AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Pin
Resolution
-
Total error
Value
Unit
Remarks
Min
Typ
Max
-
-
-
10
bit
-
-
-
-
3
LSB
Nonlinearity error
-
-
-
-
2.5
LSB
Differential nonlinearity error
-
-
-
1.9
LSB
Zero transition voltage
VOT
ANn
AVRL - 1.5
LSB
AVRL+
0.5 LSB
AVRL +
2.5 LSB
V
Full scale transition voltage
VFST
ANn
AVRH 3.5 LSB
AVRH 1.5 LSB
AVRH +
0.5 LSB
V
Compare time
-
-
1.0
-
16,500
s
4.5V AVCC 5.5V
2.0
-
-
s
3.0V AVCC 4.5V
Sampling time
-
-
0.5
-
-
s
4.5V AVCC 5.5V
1.2
-
-
s
3.0V AVCC 4.5V
-1
-
+1
A
TA 105 °C,
AVSS, AVRL < VI < AVCC,
AVRH
-1.2
-
+1.2
A
105 °C TA 125 °C,
AVSS, AVRL < VI < AVCC,
AVRH
Analog input leakage current
(during conversion)
Analog input voltage range
Reference voltage range
Power supply current
IAIN
ANn
VAIN
ANn
AVRL
-
AVRH
V
AVRH
AVRH
0.75 AVcc
-
AVcc
V
AVRL
AVRL
AVSS
-
0.25 AVCC
V
IA
AVcc
-
2.5
5
mA
A/D Converter active
IAH
AVcc
-
-
5
A
A/D Converter not
operated
IR
AVRH/AVR
L
-
0.7
1
mA
A/D Converter active
IRH
AVRH/AVR
L
-
-
5
A
A/D Converter not
operated
-
ANn
-
-
4
LSB
Reference voltage current
Offset between input
channels
-
Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller.
Document Number: 002-04592 Rev. *C
Page 63 of 82
CY96310 Series
Definition of A/D Converter Terms
Resolution: Analog variation that is recognized by an A/D converter.
Total error: Difference between the actual value and the ideal value. The total error includes zero transition error, full-scale transition
error and nonlinearity error.
Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” “00 0000 0001”) and full-scale transition
line (“11 1111 1110” “11 1111 1111”) and actual conversion characteristics.
Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
Zero reading voltage: Input voltage which results in the minimum conversion value.
Full scale reading voltage: Input voltage which results in the maximum conversion value.
Total error
3FF
3FE
1.5 LSB
Actual conversion
characteristics
Digital output
3FD
{1 LSB × (N − 1) + 0.5 LSB}
004
VNT
(Actually-measured value)
003
Actual conversion
characteristics
Ideal characteristics
002
001
0.5 LSB
AVRL
AVRH
Analog input
Total error of digital output “N”
1 LSB (Ideal value)
VNT {1 LSB × (N 1) 0.5 LSB}
1 LSB
AVRH AVRL
1024
[LSB]
[V]
N: A/D converter digital output value
VOT (Ideal value) AVRL 0.5 LSB [V]
VFST (Ideal value) AVRH 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N 1) to N.
Document Number: 002-04592 Rev. *C
Page 64 of 82
CY96310 Series
Nonlinearity error
Differential nonlinearity error
Ideal
characteristics
3FF
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
Digital output
3FD
N+1
VFST (actual
measurement
value)
VNT (actual
measurement value)
004
Actual conversion
characteristics
003
Digital output
3FE
Actual conversion
characteristics
N
V (N + 1) T
(actual measurement
value)
VNT
(actual measurement value)
N−1
002
Ideal characteristics
Actual conversion
characteristics
N−2
001
VOT (actual measurement value)
AVRL
AVRH
AVRL
Analog input
AVRH
Analog input
Nonlinearity error of digital output N
Differential nonlinearity error of digital output N
1 LSB
VNT {1 LSB × (N 1) VOT}
1 LSB
V (N+1) T VNT
1 LSB
VFST VOT
[LSB]
1 LSB [LSB]
[V]
1022
N
: A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
Document Number: 002-04592 Rev. *C
Page 65 of 82
CY96310 Series
Accuracy and setting of the A/D Converter sampling time
If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold
capacitor is insufficient, adversely affecting the A/D conversion precision.
To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time depends on the
external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and the AVcc voltage level. The following
replacement model can be used for the calculation:
MCU
Analog
input
Rext
RADC
Comparator
Source
Cext
CIN
CADC
Sampling switch
Rext: external driving impedance
Cext: capacitance of PCB at A/D converter input
CIN: capacitance of MCU input pin: 15pF (max)
RADC: resistance within MCU: 2.6k (max) for 4.5V AVcc 5.5V
12k (max) for 3.0V AVcc 4.5V
CADC: sampling capacitance within MCU: 10pF (max)
The sampling time should be set to minimum “7“. The following approximation formula for the replacement model above can be used:
Tsamp [min] = 7 × (Rext × (Cext + CIN) + (Rext + RADC) × CADC)
• Do not select a sampling time below the absolute minimum permitted value
(0.5s for 4.5V AVcc 5.5V; 1.2 s for 3.0V AVcc 4.5V).
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. In this case the internal
sampling capacitance CADC will be charged out of this external capacitance.
• A big external driving impedance also adversely affects the A/D conversion precision due to the pin input leakage current IIL
(static current before the sampling switch) or the analog input leakage current IAIN (total leakage current of pin input and
comparator during sampling). The effect of the pin input leakage current IIL cannot be compensated by an external capacitor.
• The accuracy gets worse as |AVRH - AVRL| becomes smaller.
Document Number: 002-04592 Rev. *C
Page 66 of 82
CY96310 Series
14.6 Low Voltage Detector characteristics
(TA = -40 °C to +125 °C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V)
Parameter
Symbol
Value
Unit
Remarks
110
s
After power-up or change of detection
level
2.5
2.9
V
CILCR:LVL[3:0]=”0000”
VDL1
2.8
3.2
V
CILCR:LVL[3:0]=”0001”
Level 2
VDL2
3
3.4
V
CILCR:LVL[3:0]=”0010”
Level 3
VDL3
3.35
3.8
V
CILCR:LVL[3:0]=”0011”
Level 4
VDL4
3.5
3.95
V
CILCR:LVL[3:0]=”0100”
Level 5
VDL5
3.6
4.1
V
CILCR:LVL[3:0]=”0101”
Level 6
VDL6
3.7
4.2
V
CILCR:LVL[3:0]=”0110”
Level 7
VDL7
3.8
4.3
V
CILCR:LVL[3:0]=”0111”
Level 8
VDL8
3.9
4.4
V
CILCR:LVL[3:0]=”1000”
Level 9
VDL9
3.95
4.5
V
CILCR:LVL[3:0]=”1001”
Level 10
VDL10
not used
Level 11
VDL11
not used
Level 12
VDL12
3
V
CILCR:LVL[3:0]=”1100”
Level 13
VDL13
not used
Level 14
VDL14
not used
Level 15
VDL15
not used
Min
Max
TLVDSTAB
-
Level 0
VDL0
Level 1
Stabilization time
2.6
CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register.
dV
V
For correct detection, the slope of the voltage level must satisfy dt 0.004 s .
Faster variations are regarded as noise and may not be detected.
The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of “Level 0” (VDL0_MIN). The
electrical characteristics however are only valid in the specified range (usually down to 3.0V).
Document Number: 002-04592 Rev. *C
Page 67 of 82
CY96310 Series
Low Voltage Detector Operation
In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the reset and startup
behavior, please refer to the corresponding hardware manual chapter.
Voltage [V]
VCC
VDLx, Max
VDLx, Min
dV
dt
Time [s]
Normal Operation
Document Number: 002-04592 Rev. *C
Low Voltage Reset Assertion
Power Reset Extension Time
Page 68 of 82
CY96310 Series
14.7 FLASH memory program/erase characteristics
(TA = -40°C to 105°C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Value
Unit
Remarks
3.6
s
Without erasure pre-programming
time
n*0.9
n*3.6
s
Without erasure pre-programming
time (n is the number of Flash sector
of the device)
-
23
370
us
Without overhead time for submitting
write command
10000
-
-
cycle
20
-
-
year
Min
Typ
Max
Sector erase time
-
0.9
Chip erase time
-
Word (16-bit width) programming time
Program/Erase cycle
Flash data retention time
*1
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high
temperature measurements into normalized value at 85oC)
Document Number: 002-04592 Rev. *C
Page 69 of 82
CY96310 Series
15. Example Characteristics
15.1 Temperature dependency of power supply currents
The following diagrams show the current consumption of samples with typical wafer process parameters in different operation modes.
Common condition for all operation modes:
• VCC = AVCC = 5.0V
• Main clock = 4MHz external clock
• Sub clock = 32kHz external clock
Operation mode details:
Mode name
Details
PLL Run 56
PLL Run mode current ICCPLL with the following settings:
•
fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = 56MHz
•
fCLKP2 = 28MHz
•
Regulator in High Power Mode
•
Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)
•
2 Flash/ROM wait states (MTCRA=233AH)
•
RC oscillator and Sub oscillator stopped
PLL Run 48
PLL Run mode current ICCPLL with the following settings:
•
fCLKS1 = fCLKS2 = 96MHz
•
fCLKB = fCLKP1 = 48MHz
•
fCLKP2 = 24MHz
•
Regulator in High Power Mode
•
Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)
•
1 Flash/ROM wait states (MTCRA=6B09H)
•
RC oscillator and Sub oscillator stopped
PLL Run 24
PLL Run mode current ICCPLL with the following settings:
•
fCLKS1 = fCLKS2 = 48MHz
•
fCLKB = fCLKP1 = fCLKP2 = 24MHz
•
Regulator in High Power Mode
•
Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
•
0 Flash/ROM wait states (MTCRA=2208H)
•
RC oscillator and Sub oscillator stopped
Main Run
Main Run mode current ICCMAIN with the following settings:
•
fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 4MHz
•
Regulator in High Power Mode
•
Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
•
1 Flash/ROM wait states (MTCRA=0239H)
•
PLL, RC oscillator and Sub oscillator stopped
RC Run 2M
RC Run mode current ICCRCH with the following settings:
•
RC oscillator set to 2MHz (CKFCR:RCFS = 1)
•
fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 2MHz
•
Regulator in High Power Mode
•
Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
•
1 Flash/ROM wait states (MTCRA=0239H)
•
PLL, Main oscillator and Sub oscillator stopped
Document Number: 002-04592 Rev. *C
Page 70 of 82
CY96310 Series
Mode name
Details
RC Run 100k
RC Run mode current ICCRCL with the following settings:
•
RC oscillator set to 100kHz (CKFCR:RCFS = 0)
•
fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 100kHz
•
Regulator in Low Power Mode A (SMCR:LPMS = 1)
•
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
•
1 Flash/ROM wait states (MTCRA=0239H)
•
PLL, Main oscillator and Sub oscillator stopped
Sub Run
Sub Run mode current ICCSUB with the following settings:
•
fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 32kHz
•
Regulator in Low Power Mode A (by hardware)
•
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
•
1 Flash/ROM wait states (MTCRA=0239H)
•
PLL, RC oscillator and Main oscillator stopped
PLL Sleep 56
PLL Sleep mode current ICCSPLL with the following settings:
•
fCLKS1 = fCLKS2 = fCLKP1 = 56MHz
•
fCLKP2 = 28MHz
•
Regulator in High Power Mode
•
Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)
•
RC oscillator and Sub oscillator stopped
PLL Sleep 48
PLL Sleep mode current ICCSPLL with the following settings:
•
fCLKS1 = fCLKS2 = 96MHz
•
fCLKP1 = 48MHz
•
fCLKP2 = 24MHz
•
Regulator in High Power Mode
•
Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)
•
RC oscillator and Sub oscillator stopped
PLL Sleep 24
PLL Sleep mode current ICCSPLL with the following settings:
•
fCLKS1 = fCLKS2 = 48MHz
•
fCLKP1 = fCLKP2 = 24MHz
•
Regulator in High Power Mode
•
Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
•
RC oscillator and Sub oscillator stopped
Main Sleep
Main Sleep mode current ICCSMAIN with the following settings:
•
fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 4MHz
•
Regulator in High Power Mode
•
Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
•
PLL, RC oscillator and Sub oscillator stopped
RC Sleep 2M
RC Sleep mode current ICCSRCH with the following settings:
•
RC oscillator set to 2MHz (CKFCR:RCFS = 1)
•
fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 2MHz
•
Regulator in High Power Mode
•
Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
•
PLL, Main oscillator and Sub oscillator stopped
Document Number: 002-04592 Rev. *C
Page 71 of 82
CY96310 Series
Mode name
Details
RC Sleep 100k
RC Sleep mode current ICCSRCL with the following settings:
•
RC oscillator set to 100kHz (CKFCR:RCFS = 0)
•
fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 100kHz
•
Regulator in Low Power Mode A (SMCR:LPMSS = 1)
•
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
•
PLL, Main oscillator and Sub oscillator stopped
Sub Sleep
Sub Sleep mode current ICCSSUB with the following settings:
•
fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 32kHz
•
Regulator in Low Power Mode A (by hardware)
•
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
•
PLL, RC oscillator and Main oscillator stopped
PLL Timer 48
PLL Timer mode current ICCTPLL with the following settings:
•
fCLKS1 = fCLKS2 = 48MHz
•
Regulator in High Power Mode
•
Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
•
RC oscillator and Sub oscillator stopped
Main Timer
Main Timer mode current ICCTMAIN with the following settings:
•
fCLKS1 = fCLKS2 = 4MHz
•
Regulator in Low Power Mode A (SMCR:LPMSS = 1)
•
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
•
PLL, RC oscillator and Sub oscillator stopped
RC Timer 2M
RC Timer mode current ICCTRCH with the following settings:
•
RC oscillator set to 2MHz (CKFCR:RCFS = 1)
•
fCLKS1 = fCLKS2 = 2MHz
•
Regulator in Low Power Mode A (SMCR:LPMSS = 1)
•
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
•
PLL, Main oscillator and Sub oscillator stopped
RC Timer 100k
RC Timer mode current ICCTRCL with the following settings:
•
RC oscillator set to 100kHz (CKFCR:RCFS = 0)
•
fCLKS1 = fCLKS2 = 100kHz
•
Regulator in Low Power Mode A (SMCR:LPMSS = 1)
•
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
•
PLL, Main oscillator and Sub oscillator stopped
Sub Timer
Sub Timer mode current ICCTSUB with the following settings:
•
fCLKS1 = fCLKS2 = 32kHz
•
Regulator in Low Power Mode A (by hardware)
•
Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
•
PLL, RC oscillator and Main oscillator stopped
Stop 1.8V
Stop mode current ICCH with the following settings:
•
Regulator in Low Power Mode B (by hardware)
•
Core voltage at 1.8V (VRCR:LPMB[2:0] = 110B)
Stop 1.2V
Stop mode current ICCH with the following settings:
•
Regulator in Low Power Mode B (by hardware)
•
Core voltage at 1.2V (VRCR:LPMB[2:0] = 000B)
Document Number: 002-04592 Rev. *C
Page 72 of 82
CY96310 Series
CY96F313/F315 PLL Run and Sleep mode currents
50
PLL Run 48
Icc [mA]
40
PLL Run 56
30
PLL Run 24
20
PLL Sleep 48
10 PLL Sleep 56
PLL Sleep 24
0
-60
-40
-20
0
+20
+40
+60
+80
+100
+120
Ta [ºC]
Document Number: 002-04592 Rev. *C
Page 73 of 82
CY96310 Series
CY96F313/F315 operation modes with medium currents
5
4
Main Run
Icc [mA]
3
RC Run 2 M
2
PLL Timer 48
1
Main Sleep
RC Sleep 2 M
0
-60
-40
-20
0
+20
+40
+60
+80
+100
+120
+80
+100
+120
Ta [ºC]
CY96F313/F315 Low power mode currents
1
RC Run 100 k
0.1
Icc [mA]
Sub Run
Main Timer
RC Timer 2 M
RC Sleep 100 k
Sub Sleep
Sub Timer
RC Timer 100 k
0.01
Stop 1.8 V
Stop 1.2 V
0.001
-60
-40
-20
0
+20
+40
+60
Ta [ºC]
Document Number: 002-04592 Rev. *C
Page 74 of 82
CY96310 Series
15.2 Frequency dependency of power supply currents in PLL Run mode
The following diagrams show the current consumption of samples with typical wafer process parameters in PLL Run mode at different
frequencies and Flash timing settings.
Measurement conditions:
• VCC = AVCC = 5.0V
• Ta = 25°C
• fCLKS1 = fCLKB or fCLKS1 = 2*fCLKB as described in diagram
• fCLKS2 = fCLKS1
• fCLKP1 = fCLKB
• fCLKP2 = fCLKB/2
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) or 1.9V (VRCR:HPM[1:0] = 11B) as described in diagram
• Main clock = 4MHz external clock
• Flash memory timing settings:
• MTCRA=2128H/2208H (0 Flash wait states, fCLKS1 = 2*fCLKB)
• MTCRA=0239H/2129H (1 Flash wait state, fCLKS1 = fCLKB)
• MTCRA=4C09H/6B09H (1 Flash wait state, fCLKS1 = 2*fCLKB)
• MTCRA=233AH (2 Flash wait states, fCLKS1 = fCLKB)
• Average Flash access rate (number of read accesses to the Flash per CLKB clock cycle, no buffer hit):
• 0 Flash wait states: 0.5
• 1 Flash wait states: 0.33
• 2 Flash wait states: 0.25
CY96F313/F315 PLL Run mode currents
45
1 Flash wait state
(CLKS1=2*CLKB, 1.9 V)
40
35
1 Flash wait state
(CLKS1=2*CLKB, 1.8 V)
ICCPLL (mA)
30
2 Flash wait states
(CLKS1=CLKB, 1.9 V)
25
0 Flash wait states
(CLKS1=2*CLKB, 1.8 V)
2 Flash wait states
(CLKS1=CLKB, 1.8 V)
20
15
1 Flash wait state
(CLKS1=CLKB, 1.8V)
10
: Specified in "DC characteristics"
5
0
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
CLKB/CLKP1 (MHz)
Document Number: 002-04592 Rev. *C
Page 75 of 82
CY96310 Series
16. Package Dimension CY96(F)31x LQFP48
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