CY96F356RWBPMC1-GS-UJE2

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Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY96F353/F355 CY96F356 F2MC-16FX, CY96350 Series, 16-bit Proprietary Microcontroller CY96F353/F355, CY96F356, F2MC-16FX, CY96350 Series, 16-bit Proprietary Microcontroller CY96350 series is based on Cypress’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 56MHz operation frequency from an external 4 MHz resonator. The result is a minimum instruction cycle time of 17.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies for peripheral resources independent of the CPU speed. Features ■ Technology ❐ 0.18 μm CMOS ■ CPU 2 ❐ F MC-16FX CPU ❐ Up to 56 MHz internal, 17.8 ns instruction cycle time ❐ Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) ❐ 8-byte instruction execution queue ❐ Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available ■ System clock On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop) ❐ 3 MHz - 16 MHz external crystal oscillator clock (maximum frequency when using ceramic resonator depends on Q-factor). ❐ Up to 56 MHz external clock ❐ 32-100 kHz subsystem quartz clock ❐ 100 kHz/2 MHz internal RC clock for quick and safe startup, oscillator stop detection, watchdog ❐ Clock source selectable from main- and subclock oscillator (part number suffix “W”) and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals. ❐ Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes, Stop mode) ❐ Clock modulator ■ Interrupts ❐ Fast Interrupt processing ❐ 8 programmable priority levels ❐ Non-Maskable Interrupt (NMI) ■ Timers ❐ Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer) ❐ Watchdog Timer ■ CAN ❐ Supports CAN protocol version 2.0 part A and B ❐ ISO16845 certified ❐ Bit rates up to 1 Mbit/s ❐ 32 message objects ❐ Each message object has its own identifier mask ❐ Programmable FIFO mode (concatenation of message objects) ❐ Maskable interrupt ❐ Disabled Automatic Retransmission mode for Time Triggered CAN applications ❐ Programmable loop-back mode for self-test operation ■ USART ❐ Full duplex USARTs (SCI/LIN) ❐ Wide range of baud rate settings using a dedicated reload timer ❐ Special synchronous options for adapting to different synchronous serial protocols ❐ LIN functionality working either as master or slave LIN device ❐ ■ On-chip voltage regulator ❐ Internal voltage regulator supports reduced internal MCU voltage, offering low EMI and low power consumption figures ■ Low voltage reset ❐ Reset is generated when supply voltage is below minimum. ■ Code Security ❐ Protects ROM content from unintended read-out ■ Memory Patch Function ❐ Replaces ROM content ❐ Can also be used to implement embedded debug support ■ DMA ❐ Automatic transfer function independent of CPU, can be assigned freely to resources Cypress Semiconductor Corporation Document Number: 002-04588 Rev. *C • ■ ■ 198 Champion Court I2C ❐ Up to 400 kbps ❐ Master and Slave functionality, 7-bit and 10-bit addressing A/D converter ❐ SAR-type ❐ 10-bit resolution ❐ Signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger or reload timer • San Jose, CA 95134-1709 • 408-943-2600 Revised June 10, 2020 CY96F353/F355 CY96F356 ■ Reload Timers ❐ 16-bit wide 1 2 3 4 5 6 ❐ Prescaler with 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 of peripheral clock frequency ❐ Event count function ■ Free Running Timers ❐ Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27,1/28 of peripheral clock frequency ■ Input Capture Units ❐ 16-bit wide ❐ Signals an interrupt upon external event ❐ Rising edge, falling edge or rising & falling edge sensitive ■ Output Compare Units ❐ 16-bit wide ❐ Signals an interrupt when a match with 16-bit I/O Timer occurs ❐ A pair of compare registers can be used to generate an output signal. ■ Programmable Pulse Generator ❐ 16-bit down counter, cycle and duty setting registers ❐ Interrupt at trigger, counter borrow and/or duty match ❐ PWM operation and one-shot operation ❐ Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and Reload timer overflow as clock input ❐ Can be triggered by software or reload timer ■ Real Time Clock ❐ Can be clocked either from sub oscillator (devices with part number suffix “W”), main oscillator or from the RC oscillator ❐ Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration) ❐ Read/write accessible second/minute/hour registers ❐ Can signal interrupts every half second/second/minute/hour/day ❐ Internal clock divider and prescaler provide exact 1 s clock ■ External Interrupts ❐ Edge sensitive or level sensitive ❐ Interrupt mask and pending bit per channel ❐ Each available CAN channel RX has an external interrupt for wake-up ❐ Selected USART channels SIN have an external interrupt for wake-up Document Number: 002-04588 Rev. *C ■ Non Maskable Interrupt ❐ Disabled after reset ❐ Once enabled, can not be disabled other than by reset. ❐ Level high or level low sensitive ❐ Pin shared with external interrupt 0. ■ External bus interface ❐ 8-bit or 16-bit bidirectional data ❐ Up to 24-bit addresses ❐ 6 chip select signals ❐ Multiplexed address/data lines ❐ Wait state request ❐ External bus master possible ❐ Timing programmable ■ I/O Ports ❐ Virtually all external pins can be used as general purpose I/O 2 ❐ All push-pull outputs (except when used as I C SDA/SCL line) ❐ Bit-wise programmable as input/output or peripheral signal ❐ Bit-wise programmable input enable ❐ Bit-wise programmable input levels: Automotive / CMOS-Schmitt trigger / TTL ❐ Bit-wise programmable pull-up resistor ❐ Bit-wise programmable output driving strength for EMI optimization ■ Package ❐ 64-pin plastic LQFP ■ Flash Memory ❐ Supports automatic programming, Embedded Algorithm ❐ Write/Erase/Erase-Suspend/Resume commands ❐ A flag indicating completion of the algorithm ❐ Number of erase cycles: 10,000 times ❐ Data retention time: 20 years ❐ Erase can be performed on each sector individually ❐ Sector protection ❐ Flash Security feature to protect the content of the Flash ❐ Low voltage detection during Flash erase Page 2 of 98 CY96F353/F355 CY96F356 Contents Product Lineup ................................................................. 4 Block Diagram .................................................................. 5 Pin Assignments .............................................................. 6 Pin Function Description ................................................. 7 Pin Circuit Type ................................................................ 9 I/O Circuit Type ............................................................... 10 Memory Map .................................................................... 13 RAMSTART/END and External Bus End Addresses ... 14 User ROM Memory Map for Flash Devices .................. 14 Serial Programming Communication Interface ........... 15 I/O Map ............................................................................. 16 Interrupt Vector Table .................................................... 37 Handling Devices ............................................................ 40 Latch-up Prevention .................................................. 40 Unused Pins Handling ............................................... 40 External Clock Usage ................................................ 40 Unused Sub Clock Signal .......................................... 41 Notes on PLL Clock Mode Operation ........................ 41 Power Supply Pins (VCC/VSS) ................................. 41 Crystal Oscillator and Ceramic Resonator Circuit ..... 41 Turn on Sequence of Power Supply to A/D Converter and Analog Inputs .............................. 41 Pin Handling when Not Using the A/D Converter ...... 41 Notes on Power-on .................................................... 41 Stabilization of Power Supply Voltage ....................... 41 Serial Communication ............................................... 42 Clock modulator ........................................................ 42 Document Number: 002-04588 Rev. *C Electrical Characteristics ............................................... 43 Absolute Maximum Ratings ....................................... 43 Recommended Operating Conditions ....................... 45 DC Characteristics .................................................... 46 AC Characteristics ..................................................... 54 Analog Digital Converter ........................................... 73 Low Voltage Detector Characteristics ....................... 77 Flash Memory Program/Erase Characteristics .......... 78 Example Characteristics ................................................ 79 Package Dimension ........................................................ 88 CY96(F)35x LQFP 64 - LQG064 ............................... 88 CY96(F)35x LQFP 64 - LQD064 ............................... 89 Ordering Information ...................................................... 90 MCU with CAN Controller .......................................... 90 MCU without CAN Controller ..................................... 90 Major Changes ................................................................ 91 Revision History ........................................................ 92 Document History ........................................................... 97 Sales, Solutions, and Legal Information ...................... 98 Worldwide Sales and Design Support ....................... 98 Products .................................................................... 98 PSoC® Solutions ....................................................... 98 Cypress Developer Community ................................. 98 Technical Support ..................................................... 98 Page 3 of 98 CY96F353/F355 CY96F356 Product Lineup Features Product type CY96V300C CY96(F)35x Evaluation sample Flash product: CY96F35x Mask ROM product: CY9635x NA Low voltage reset can be disabled / Single clock devices Product options RS RW Low voltage reset can be disabled / Dual clock devices AS No CAN / Low voltage reset can be disabled / Single clock devices AW No CAN / Low voltage reset can be disabled / Dual clock devices Flash/ROM RAM 96 KB 8 KB 160 KB 8 KB 288 KB 12 KB ROM/Flash memory emulation by external RAM, 92 KB internal RAM CY96F356RS/RW/AS/AW Package BGA416 LQG064/LQD064 DMA 16 channels 4 channels USART 10 channels 4 channels I2C 2 channels 1 channel A/D Converter 40 channels 15 channels A/D Converter Reference Voltage switch yes No 16-bit Reload Timer 6 channels + 1 channel 4 channels + 1 channel (for PPG) (for PPG) 16-bit Free-Running Timer 4 channels 4 channels (2 channels with external clock input pin) 16-bit Output Compare 12 channels 4 channels 16-bit Input Capture 12 channels 6 channels (plus 2 channels for LIN USART) 16-bit Programmable Pulse Generator 20 channels 20 channels CAN Interface 5 channels CY96F35xA: no CY96F353R/F355R: 1 channel CY96F356R: 2 channels External Interrupts 16 channels 13 channels Non-Maskable Interrupt 1 channel Real Time Clock 1 I/O Ports 136 External bus interface Yes Chip select 6 signals Clock output function 2 channels Low voltage reset Yes On-chip RC-oscillator Yes Document Number: 002-04588 Rev. *C CY96F353RS/RW/AS/AW CY96F355RS/RW/AS/AW 49 for part number with suffix "W", 51 for part number with suffix "S" Page 4 of 98 CY96F353/F355 CY96F356 Block Diagram Figure 1. Block Diagram of CY96(F)35x AD00 ... AD15 A16 ... A21 ALE RDX WR(L)X, WRHX HRQ HAKX RDY ECLK CS0_R ... CS5_R External Bus Interface CKOT0_R, CKOT1, CKOT1_R CKOTX1 X0, X1 X0A, X1A *1 RSTX MD0...MD2 NMI_R Interrupt Controller 16FX CPU Flash Memory A Memory Patch Unit Clock & Mode Controller 16FX Core Bus (CLKB) AVCC AVSS AVRH AN0 ... AN14 ADTG_R TIN0_R, TIN2_R TIN1, TIN3 TOT0_R, TOT2_R TOT1, TOT3 FRCK0 IN0 ... IN1 FRCK1 IN4 ... IN7 OUT4 ... OUT7 Peripheral Bus Bridge Peripheral Bus Bridge Peripheral Bus 2 (CLKP2) SDA0 SCL0 Watchdog I2C 1 ch. 10-bit ADC 15 ch. 16-bit Reload Timer 4 ch. I/O Timer 0 ICU 0/1 Peripheral Bus 1 (CLKP1) DMA Controller I/O Timer 1 ICU 4/5/6/7 OCU 4/5/6/7 USART 4 ch. 16-bit PPG 20 ch. RLT6 Real Time Clock I/O Timer 2 ICU 9 I/O Timer 3 ICU 10 External Interrupt RAM Boot ROM Voltage Regulator VCC VSS C CAN Interface 2 ch. TX1 *2, TX2 *3 RX1*2 , RX2 *3 SIN2, SIN2_R, SIN3, SIN7_R, SIN8_R SOT2, SOT2_R, SOT3, SOT7_R, SOT8_R SCK2, SCK2_R, SCK3, SCK7_R, SCK8_R TTG0, TTG1, TTG4 ... TTG9, TTG12 ... TTG15 TTG8_R ... TTG11_R, TTG16_R ... TTG19_R PPG0 ... PPG7, PPG12 ... PPG15 PPG8_R ... PPG11_R, PPG16_R ... PPG19_R WOT INT8 ... INT15 INT0_R, INT2_R, INT4_R INT7_R, INT9_R ... INT11_R INT3_R1 *1: X0A, X1A only available on devices with suffix “W” *2: TX1, RX1 only available on CY96F356Y/R *3: TX2, RX2 only available on CY96F356Y/R and CY96F353R/F355R Document Number: 002-04588 Rev. *C Page 5 of 98 CY96F353/F355 CY96F356 Pin Assignments P01_1/AD09/CKOTX1/TOT1/TTG17_R P01_2/AD10/INT11_R/SIN3/TTG18_R P01_3/AD11/SOT3/TTG19_R P01_4/AD12/SCK3/PPG16_R P01_5/AD13/SIN2_R/INT7_R/PPG17_R P01_6/AD14/SOT2_R/PPG18_R P01_7/AD15/SCK2_R/PPG19_R P02_0/A16/PPG12/CKOT1_R P02_1/A17/PPG13 P02_2/A18/PPG14/CKOT0_R P02_3/A19/PPG15 P02_4/A20/TTG8/TTG0/IN0 RSTX X1 X0 Vss Figure 2. Pin Assignment of CY96(F)35x 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 P01_0/AD08/CKOT1/TIN1/TTG16_R C 50 31 P00_7/AD07/INT15/PPG11_R P02_5/A21/TTG9/TTG1/IN1/ADTG_R 51 30 P00_6/AD06/INT14/PPG10_R P04_4/SDA0/FRCK0/TIN0_R 52 29 P00_5/AD05/INT13/SIN8_R/PPG9_R P04_5/SCL0/FRCK1/TIN2_R 53 28 P00_4/AD04/INT12/SOT8_R/PPG8_R P03_0/ALE/IN4/TTG4/TTG12/TOT0_R 54 27 P00_3/AD03/INT11/SCK8_R/TTG11_R P03_1/RDX/IN5/TTG5/TTG13/TOT2_R 55 26 P00_2/AD02/INT10/SIN7_R/TTG10_R P03_2/WR(L)X/RX2/INT10_R *3 56 25 P00_1/AD01/INT9/SOT7_R/TTG9_R P03_3/TX2/WRHX *3 57 24 P00_0/AD00/INT8/SCK7_R/TTG8_R P03_4/HRQ/OUT4 58 23 MD0 P03_5/HAKX/OUT5 59 22 MD1 P03_6/RDY/OUT6 60 21 P03_7/ECLK/OUT7 61 20 P06_0/AN0/PPG0/CS0_R 62 19 X0A/P04_0 *1 P06_1/AN1/PPG1/CS1_R 63 18 Vss AVcc 64 17 9 10 11 12 13 14 15 16 LQFP - 64 *2: TX1, RX1 only available on CY96F356Y/R P05_6/AN14/INT4_R MD2 X1A/P04_1 *1 P04_3/IN7/TX1/TTG7/TTG15 *2 P04_2/IN6/RX1/INT9_R/TTG6/TTG14 *2 *1: Devices with suffix W: X0A, X1A Devices with suffix S: P04_0, P04_1 P05_5/AN13/INT0_R/NMI_R P05_4/AN12/TOT3/INT2_R P05_3/AN11/TIN3/WOT 8 P05_2/AN10/SCK2 7 P05_1/AN9/SOT2 P06_3/AN3/PPG3/CS3_R 6 P05_0/AN8/SIN2/INT3_R1 P06_2/AN2/PPG2/CS2_R 5 P06_7/AN7/PPG7 4 P06_6/AN6/PPG6 3 P06_5/AN5/PPG5/CS5_R 2 P06_4/AN4/PPG4/CS4_R 1 AVss Package code (mold) LQG064/LQD064 AVRH Vcc *3: TX2, RX2 only available on CY96F356Y/R and CY96F353R/F355R (LQG064/LQD064) Remark: CY96(F)35x products are pin-compatible to F2MC-16LX family CY90350 series. Document Number: 002-04588 Rev. *C Page 6 of 98 CY96F353/F355 CY96F356 Pin Function Description Table 1. Pin Function Description (1 / 2) Pin Name Feature Description ADn External bus External bus interface (multiplexed mode) address output and data input/output ADTG_R ADC Relocated A/D converter trigger input ALE External bus External bus Address Latch Enable output An External bus External bus address output ANn ADC A/D converter channel n input AVCC Supply Analog circuits power supply AVRH ADC A/D converter high reference voltage input AVSS Supply Analog circuits power supply C Voltage regulator Internally regulated power supply stabilization capacitor pin CKOTn Clock output function Clock Output function n output CKOTn_R Clock output function Relocated Clock Output function n output CKOTXn Clock output function Clock Output function n inverted output ECLK External bus External bus clock output CSn_R External bus Relocated External bus chip select n output FRCKn Free Running Timer Free Running Timer n input HAKX External bus External bus Hold Acknowledge HRQ External bus External bus Hold Request INn ICU Input Capture Unit n input INTn External Interrupt External Interrupt n input INTn_R External Interrupt Relocated External Interrupt n input MDn Core Input pins for specifying the operating mode. NMI_R External Interrupt Relocated Non-Maskable Interrupt input OUTn OCU Output Compare Unit n waveform output Pxx_n GPIO General purpose IO PPGn PPG Programmable Pulse Generator n output PPGn_R PPG Relocated Programmable Pulse Generator n output RDX External bus External bus interface read strobe output RDY External bus External bus interface external wait state request input RSTX Core Reset input RXn CAN CAN interface n RX input SCKn USART USART n serial clock input/output SCKn_R USART Relocated USART n serial clock input/output 2C I2C interface n clock I/O input/output SCLn I SDAn I2C I2C interface n serial data I/O input/output SINn USART USART n serial data input SINn_R USART Relocated USART n serial data input SOTn USART USART n serial data output SOTn_R USART Relocated USART n serial data output Document Number: 002-04588 Rev. *C Page 7 of 98 CY96F353/F355 CY96F356 Table 1. Pin Function Description (2 / 2) Pin Name Feature Description TINn Reload Timer Reload Timer n event input TINn_R Reload Timer Relocated Reload Timer n event input TOTn Reload Timer Reload Timer n output TOTn_R Reload Timer Relocated Reload Timer n output TTGn PPG Programmable Pulse Generator n trigger input TTGn_R PPG Relocated Programmable Pulse Generator n trigger input TXn CAN CAN interface n TX output VCC Supply Power supply VSS Supply Power supply WOT RTC Real Timer clock output WRHX External bus External bus High byte write strobe output WRLX/WRX External bus External bus Low byte / Word write strobe output X0 Clock Oscillator input X0A Clock Subclock Oscillator input (only for devices with suffix “W”) X1 Clock Oscillator output X1A Clock Subclock Oscillator output (only for devices with suffix “W”) Document Number: 002-04588 Rev. *C Page 8 of 98 CY96F353/F355 CY96F356 Pin Circuit Type Table 2. LQG064/LQD064 Circuit Type *1 Pin No. 1 Supply 2 G 3 to 15 I 16,17 H 18 Supply 19,20 B *2 19,20 H *3 21 to 23 C 24 to 44 H 45 E 46,47 A 48,49 Supply 50 F 51 H 52,53 N 54 to 61 H 62,63 I 64 Supply *1: Please refer to I/O Circuit Type for details on the I/O circuit types *2: Devices with suffix “W” *3: Devices without suffix “W” Document Number: 002-04588 Rev. *C Page 9 of 98 CY96F353/F355 CY96F356 I/O Circuit Type Type Circuit Remarks A High-speed oscillation circuit: ■ Programmable between oscillation mode (external crystal or resonator connected to X0/X1 pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin) ■ Programmable feedback resistor = approx. 2 * 0.5 MΩ. Feedback resistor is grounded in the center when the oscillator is disabled or in FCI mode X1 R 0 MRFBE Xout 1 FCI R X0 FCI or osc disable B Low-speed oscillation circuit: Xout X1A ■ Programmable feedback resistor = approx. 20 MΩ ( X1A:19.5 MΩ, X0A:0.5 MΩ) Feedback resistor is grounded in the center when the oscillator is disabled ■ Mask ROM and EVA device: CMOS Hysteresis input pin ■ Flash device: CMOS input pin ■ CMOS Hysteresis input pin ■ Pull-up resistor value: approx. 50 kΩ R SRFBE R X0A osc disable C R Hysteresis inputs E Pull-up Resistor R Document Number: 002-04588 Rev. *C Hysteresis inputs Page 10 of 98 CY96F353/F355 CY96F356 Type Circuit Remarks F ■ Power supply input protection circuit ■ A/D converter ref+ (AVRH) power supply input pin with protection circuit ■ Flash devices do not have a protection circuit against VCC for pin AVRH ■ CMOS level output (programmable IOL = 5 mA, IOH = -5 mA and IOL = 2 mA, IOH = -2 mA) ■ 2 different CMOS hysteresis inputs with input shutdown function ■ Automotive input with input shutdown function ■ TTL input with input shutdown function ■ Programmable pull-up resistor: 50 kΩ approx. P-ch N-ch G ANE P-ch P-ch N-ch N-ch AVR ANE H pull-up control P-ch P-ch N-ch Pout Nout R Standby control for input shutdown Hysteresis input Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input Document Number: 002-04588 Rev. *C Note: CY96F353/F355: Only Automotive input and CMOS hysteresis input (0.7/0.3) are supported Page 11 of 98 CY96F353/F355 CY96F356 Type Circuit Remarks I ■ CMOS level output (programmable IOL = 5 mA, IOH = -5 mA and IOL = 2 mA, IOH = -2 mA) ■ 2 different CMOS hysteresis inputs with input shutdown function ■ Automotive input with input shutdown function ■ TTL input with input shutdown function. ■ Programmable pull-up resistor: 50 kΩ approx. ■ Analog input Pull-up control P-ch P-ch N-ch Pout Nout R Hysteresis input Standby control for input shutdown Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input Note: CY96F353/F355: Only Automotive input and CMOS hysteresis input (0.7/0.3) are supported Analog input N pull-up control P-ch P-ch Pout N-ch Nout CMOS level output (IOL = 3 mA, IOH = -3 mA) ■ 2 different CMOS hysteresis inputs with input shutdown function ■ Automotive input with input shutdown function ■ TTL input with input shutdown function ■ Programmable pull-up resistor: 50 kΩ approx. *1 R Standby control for input shutdown Hysteresis input Standby control for input shutdown Hysteresis input Standby control for input shutdown Automotive input Standby control for input shutdown TTL input Document Number: 002-04588 Rev. *C ■ *1: N-channel transistor has slew rate control according to I2C spec, irrespective of usage Note: CY96F353/F355: Only Automotive input and CMOS hysteresis input (0.7/0.3) are supported Page 12 of 98 CY96F353/F355 CY96F356 Memory Map CY96V300C CY96(F)35x Emulation ROM USER ROM / External Bus*4 External Bus External Bus Boot-ROM Boot-ROM FF:FFFFH DE:0000H 10:0000H 0F:E000H Reserved 0E:0000H Reserved External RAM 02:0000H Reserved Internal RAM bank 1 RAMEND1*2 RAMSTART12 Internal RAM bank 1 RAM availability depending on the device Reserved 01:0000H ROM/RAM MIRROR ROM/RAM MIRROR 00:8000H Internal RAM bank 0 RAMSTART0*2 Internal RAM bank 0 Reserved External Bus end address*2 RAMSTART0 *3 00:0C00H External Bus External Bus Peripherals Peripherals GPR*1 GPR*1 00:0380H 00:0180H 00:0100H DMA DMA 00:00F0H External Bus External Bus 00:0000H Peripheral Peripheral *1: Unused GPR banks can be used as RAM area *2: For External Bus end address and RAMSTART/END addresses, please refer to the table on the next page. *3: For EVA device, RAMSTART0 depends on the configuration of the emulated device. *4: For details about USER ROM area, see the User ROM Memory Map for Flash Devices on the following pages. The External Bus area and DMA area are only available if the device contains the corresponding resource. The available RAM and ROM area depends on the device. Document Number: 002-04588 Rev. *C Page 13 of 98 CY96F353/F355 CY96F356 RAMSTART/END and External Bus End Addresses Devices Bank 0 RAM Size Bank 1 External Bus End RAM Size Address RAMSTART0 RAMSTART1 RAMEND1 CY96F353/F355 8 KByte - 00:51FFH 00:6240H - - CY96F356 12 KByte - 00:51FFH 00:5240H - - User ROM Memory Map for Flash Devices Alternative mode CPU address Flash memory mode address FF:FFFFH FF:0000H FE:FFFFH FE:0000H FD:FFFFH FD:0000H FC:FFFFH FC:0000H FB:FFFFH FB:0000H FA:FFFFH FA:0000H F9:FFFFH F9:0000H F8:FFFFH F8:0000H F7:FFFFH F7:0000H F6:FFFFH F6:0000H F5:FFFFH F5:0000H F4:FFFFH F4:0000H F3:FFFFH F3:0000H F2:FFFFH F2:0000H F1:FFFFH F1:0000H F0:FFFFH F0:0000H E0:FFFFH 3F:FFFFH 3F:0000H 3E:FFFFH 3E:0000H 3D:FFFFH 3D:0000H 3C:FFFFH 3C:0000H 3B:FFFFH 3B:0000H 3A:FFFFH 3A:0000H 39:FFFFH 39:0000H 38:FFFFH 38:0000H 37:FFFFH 37:0000H 36:FFFFH 36:0000H 35:FFFFH 35:0000H 34:FFFFH 34:0000H 33:FFFFH 33:0000H 32:FFFFH 32:0000H 31:FFFFH 31:0000H 30:FFFFH 30:0000H E0:0000H DF:FFFFH DF:8000H DF:7FFFH DF:6000H DF:5FFFH DF:4000H DF:3FFFH DF:2000H DF:1FFFH DF:0000H DE:FFFFH 1F:7FFFH 1F:6000H 1F:5FFFH 1F:4000H 1F:3FFFH 1F:2000H 1F:1FFFH 1F:0000H DE:0000H CY96F353 CY96F355 CY96F356 Flash size 96 kByte Flash size 160 kByte Flash size 288 kByte S39 - 64K S39 - 64K S39 - 64K S38 - 64K S38 - 64K S37 - 64K Flash A S36 - 64K External bus External bus External bus Reserved Reserved Reserved SA3 - 8K SA3 - 8K SA3 - 8K SA2 - 8K SA2 - 8K SA2 - 8K SA1 - 8K SA1 - 8K SA1 - 8K SA0 - 8K *1 SA0 - 8K *1 SA0 - 8K *1 Reserved Reserved Reserved Flash A *1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH Document Number: 002-04588 Rev. *C Page 14 of 98 CY96F353/F355 CY96F356 Serial Programming Communication Interface Table 3. USART pins for Flash serial programming (MD[2:0] = 010) CY96F35x Pin Number LQFP-64 9 USART Number USART2 Normal Function SIN2 10 SOT2 11 SCK2 34 USART3 35 SOT3 36 26 SIN3 SCK3 USART7 SIN7_R 25 SOT7_R 24 SCK7_R 29 USART8 SIN8_R 28 SOT8_R 27 SCK8_R Note: If a Flash programmer and its software needs to use a handshaking pin, Cypress suggests to the tool vendor to support at least port P00_1 on pin 25. If handshaking is used by the tool but P00_1 is not available in customer’s application, Cypress suggests to the customer to check the tool manual or to contact the tool vendor for alternative handshaking pins. Document Number: 002-04588 Rev. *C Page 15 of 98 CY96F353/F355 CY96F356 I/O Map Table 4. I/O Map CY96(F)35x (1 / 21) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 000000H I/O Port P00 - Port Data Register PDR00 R/W 000001H I/O Port P01 - Port Data Register PDR01 R/W 000002H I/O Port P02 - Port Data Register PDR02 R/W 000003H I/O Port P03 - Port Data Register PDR03 R/W 000004H I/O Port P04 - Port Data Register PDR04 R/W 000005H I/O Port P05 - Port Data Register PDR05 R/W 000006H I/O Port P06 - Port Data Register PDR06 R/W 000007H-000017H Reserved - 000018H ADC0 - Control Status register Low ADCSL 000019H ADC0 - Control Status register High ADCSH 00001AH ADC0 - Data Register Low ADCRL 00001BH ADC0 - Data Register High ADCRH 00001CH ADC0 - Setting Register 00001DH ADC0 - Setting Register 00001EH ADC0 - Extended Configuration Register 00001FH Reserved ADCS R/W R/W ADCR R R ADSR R/W R/W ADECR R/W - 000020H FRT0 - Data register of free-running timer 000021H FRT0 - Data register of free-running timer TCDT0 000022H FRT0 - Control status register of free-running timer Low TCCSL0 000023H FRT0 - Control status register of free-running timer High TCCSH0 R/W R/W TCCS0 R/W R/W 000024H FRT1 - Data register of free-running timer 000025H FRT1 - Data register of free-running timer 000026H FRT1 - Control status register of free-running timer Low TCCSL1 000027H FRT1 - Control status register of free-running timer High TCCSH1 000028H-000033H Reserved 000034H OCU4 - Output Compare Control Status OCS4 R/W 000035H OCU5 - Output Compare Control Status OCS5 R/W 000036H OCU4 - Compare Register 000037H OCU4 - Compare Register 000038H OCU5 - Compare Register 000039H OCU5 - Compare Register 00003AH OCU6 - Output Compare Control Status OCS6 00003BH OCU7 - Output Compare Control Status OCS7 00003CH OCU6 - Compare Register 00003DH OCU6 - Compare Register 00003EH OCU7 - Compare Register 00003FH OCU7 - Compare Register 000040H ICU0/ICU1 - Control Status Register Document Number: 002-04588 Rev. *C TCDT1 R/W R/W TCCS1 R/W R/W - OCCP4 R/W R/W OCCP5 R/W R/W R/W R/W OCCP6 R/W R/W OCCP7 R/W R/W ICS01 R/W Page 16 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (2 / 21) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 000041H ICU0/ICU1 - Edge register ICE01 000042H ICU0 - Capture Register Low IPCPL0 R/W 000043H ICU0 - Capture Register High IPCPH0 000044H ICU1 - Capture Register Low IPCPL1 000045H ICU1 - Capture Register High IPCPH1 R IPCP0 R R IPCP1 R 000046H - 00004BH Reserved 00004CH ICU4/ICU5 - Control Status Register ICS45 R/W 00004DH ICU4/ICU5 - Edge register ICE45 R/W 00004EH ICU4 - Capture Register Low IPCPL4 00004FH ICU4 - Capture Register High IPCPH4 000050H ICU5 - Capture Register Low IPCPL5 000051H ICU5 - Capture Register High IPCPH5 R IPCP4 R R IPCP5 R 000052H ICU6/ICU7 - Control Status Register ICS67 R/W 000053H ICU6/ICU7 - Edge register ICE67 R/W 000054H ICU6 - Capture Register Low IPCPL6 000055H ICU6 - Capture Register High IPCPH6 000056H ICU7 - Capture Register Low IPCPL7 000057H ICU7 - Capture Register High IPCPH7 R 000058H EXTINT0 - External Interrupt Enable Register ENIR0 R/W 000059H EXTINT0 - External Interrupt Interrupt request Register EIRR0 R/W 00005AH EXTINT0 - External Interrupt Level Select Low ELVRL0 00005BH EXTINT0 - External Interrupt Level Select High ELVRH0 R/W 00005CH EXTINT1 - External Interrupt Enable Register ENIR1 R/W 00005DH EXTINT1 - External Interrupt Interrupt request Register EIRR1 R/W 00005EH EXTINT1 - External Interrupt Level Select Low ELVRL1 00005FH EXTINT1 - External Interrupt Level Select High ELVRH1 000060H RLT0 - Timer Control Status Register Low TMCSRL0 000061H RLT0 - Timer Control Status Register High TMCSRH0 000062H RLT0 - Reload Register - for writing TMRLR0 W 000062H RLT0 - Reload Register - for reading TMR0 R 000063H RLT0 - Reload Register - for writing W 000063H RLT0 - Reload Register - for reading R 000064H RLT1 - Timer Control Status Register Low TMCSRL1 000065H RLT1 - Timer Control Status Register High TMCSRH1 000066H RLT1 - Reload Register - for writing TMRLR1 W 000066H RLT1 - Reload Register - for reading TMR1 R 000067H RLT1 - Reload Register - for writing W 000067H RLT1 - Reload Register - for reading R 000068H RLT2 - Timer Control Status Register Low Document Number: 002-04588 Rev. *C TMCSRL2 IPCP6 R R IPCP7 ELVR0 ELVR1 R R/W R/W R/W TMCSR0 R/W R/W TMCSR1 R/W R/W TMCSR2 R/W Page 17 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (3 / 21) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access TMCSRH2 Access 000069H RLT2 - Timer Control Status Register High 00006AH RLT2 - Reload Register - for writing TMRLR2 W 00006AH RLT2 - Reload Register - for reading TMR2 R 00006BH RLT2 - Reload Register - for writing 00006BH RLT2 - Reload Register - for reading 00006CH RLT3 - Timer Control Status Register Low TMCSRL3 00006DH RLT3 - Timer Control Status Register High TMCSRH3 00006EH RLT3 - Reload Register - for writing TMRLR3 W 00006EH RLT3 - Reload Register - for reading TMR3 R 00006FH RLT3 - Reload Register - for writing W 00006FH RLT3 - Reload Register - for reading R 000070H RLT6 - Timer Control Status Register Low (dedic. RLT for PPG) 000071H RLT6 - Timer Control Status Register High (dedic. RLT for TMCSRH6 PPG) 000072H RLT6 - Reload Register (dedic. RLT for PPG) - for writing TMRLR6 W 000072H RLT6 - Reload Register (dedic. RLT for PPG) - for reading TMR6 R 000073H RLT6 - Reload Register (dedic. RLT for PPG) - for writing 000073H RLT6 - Reload Register (dedic. RLT for PPG) - for reading 000074H PPG3-PPG0 - General Control register 1 Low GCN1L0 000075H PPG3-PPG0 - General Control register 1 High GCN1H0 000076H PPG3-PPG0 - General Control register 2 Low GCN2L0 000077H PPG3-PPG0 - General Control register 2 High GCN2H0 000078H PPG0 - Timer register 000079H PPG0 - Timer register 00007AH PPG0 - Period setting register 00007BH PPG0 - Period setting register 00007CH PPG0 - Duty cycle register 00007DH PPG0 - Duty cycle register 00007EH PPG0 - Control status register Low PCNL0 PCNH0 W R TMCSRL6 TMCSR3 R/W R/W TMCSR6 R/W R/W W R GCN10 R/W R/W GCN20 R/W R/W PTMR0 R R PCSR0 W PDUT0 W W W 00007FH PPG0 - Control status register High 000080H PPG1 - Timer register 000081H PPG1 - Timer register 000082H PPG1 - Period setting register 000083H PPG1 - Period setting register 000084H PPG1 - Duty cycle register 000085H PPG1 - Duty cycle register 000086H PPG1 - Control status register Low PCNL1 000087H PPG1 - Control status register High PCNH1 000088H PPG2 - Timer register Document Number: 002-04588 Rev. *C R/W PCN0 R/W PTMR1 R R/W R PCSR1 W PDUT1 W W W PCN1 R/W PTMR2 R R/W Page 18 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (4 / 21) Address Register Abbreviation 8-bit Access 000089H PPG2 - Timer register 00008AH PPG2 - Period setting register 00008BH PPG2 - Period setting register 00008CH PPG2 - Duty cycle register 00008DH PPG2 - Duty cycle register 00008EH PPG2 - Control status register Low PCNL2 00008FH PPG2 - Control status register High PCNH2 000090H PPG3 - Timer register Abbreviation 16-bit Access Access R PCSR2 W W PDUT2 W W 000091H PPG3 - Timer register 000092H PPG3 - Period setting register 000093H PPG3 - Period setting register 000094H PPG3 - Duty cycle register 000095H PPG3 - Duty cycle register 000096H PPG3 - Control status register Low PCNL3 000097H PPG3 - Control status register High PCNH3 000098H PPG7-PPG4 - General Control register 1 Low GCN1L1 000099H PPG7-PPG4 - General Control register 1 High GCN1H1 00009AH PPG7-PPG4 - General Control register 2 Low GCN2L1 00009BH PPG7-PPG4 - General Control register 2 High GCN2H1 00009CH PPG4 - Timer register PCN2 R/W R/W PTMR3 R PCSR3 W R W PDUT3 W W 00009DH PPG4 - Timer register 00009EH PPG4 - Period setting register 00009FH PPG4 - Period setting register 0000A0H PPG4 - Duty cycle register 0000A1H PPG4 - Duty cycle register 0000A2H PPG4 - Control status register Low PCNL4 0000A3H PPG4 - Control status register High PCNH4 0000A4H PPG5 - Timer register PCN3 R/W R/W GCN11 R/W R/W GCN21 R/W R/W PTMR4 R PCSR4 W R W PDUT4 W W PCN4 R/W R/W PTMR5 R PCSR5 W 0000A5H PPG5 - Timer register 0000A6H PPG5 - Period setting register 0000A7H PPG5 - Period setting register 0000A8H PPG5 - Duty cycle register 0000A9H PPG5 - Duty cycle register 0000AAH PPG5 - Control status register Low PCNL5 0000ABH PPG5 - Control status register High PCNH5 R/W 0000ACH I2C0 - Bus Status Register IBSR0 R 0000ADH I2C0 - Bus Control Register IBCR0 0000AEH I2C0 - Ten bit Slave address Register Low ITBAL0 0000AFH I2C0 - Ten bit Slave address Register High ITBAH0 Document Number: 002-04588 Rev. *C R W PDUT5 W W PCN5 R/W R/W ITBA0 R/W R/W Page 19 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (5 / 21) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access ITMK0 Access 0000B0H I2C0 - Ten bit Address mask Register Low ITMKL0 0000B1H I2C0 - Ten bit Address mask Register High ITMKH0 R/W 0000B2H I2C0 - Seven bit Slave address Register ISBA0 R/W 0000B3H I2C0 - Seven bit Address mask Register ISMK0 R/W 0000B4H I2C0 - Data Register IDAR0 R/W 0000B5H I2C0 - Clock Control Register ICCR0 R/W 0000B6H-0000D3H Reserved 0000D4H USART2 - Serial Mode Register 0000D5H 0000D6H R/W SMR2 R/W USART2 - Serial Control Register SCR2 R/W USART2 - TX Register TDR2 W 0000D6H USART2 - RX Register RDR2 R 0000D7H USART2 - Serial Status SSR2 R/W 0000D8H USART2 - Control/Com. Register ECCR2 R/W 0000D9H USART2 - Ext. Status Register ESCR2 R/W 0000DAH USART2 - Baud Rate Generator Register Low BGRL2 0000DBH USART2 - Baud Rate Generator Register High BGRH2 R/W 0000DCH USART2 - Extended Serial Interrupt Register ESIR2 R/W 0000DDH Reserved 0000DEH USART3 - Serial Mode Register SMR3 R/W 0000DFH USART3 - Serial Control Register SCR3 R/W 0000E0H USART3 - TX Register TDR3 W 0000E0H USART3 - RX Register RDR3 R 0000E1H USART3 - Serial Status SSR3 R/W 0000E2H USART3 - Control/Com. Register ECCR3 R/W 0000E3H USART3 - Ext. Status Register ESCR3 0000E4H USART3 - Baud Rate Generator Register Low BGRL3 0000E5H USART3 - Baud Rate Generator Register High BGRH3 R/W 0000E6H USART3 - Extended Serial Interrupt Register ESIR3 R/W BGR2 - R/W BGR3 0000E7H-0000EFH Reserved 0000F0H-0000FFH External Bus area R/W R/W EXTBUS0 R/W 000100H DMA0 - Buffer address pointer low byte BAPL0 R/W 000101H DMA0 - Buffer address pointer middle byte BAPM0 R/W 000102H DMA0 - Buffer address pointer high byte BAPH0 R/W 000103H DMA0 - DMA control register DMACS0 R/W 000104H DMA0 - I/O register address pointer low byte IOAL0 000105H DMA0 - I/O register address pointer high byte IOAH0 000106H DMA0 - Data counter low byte DCTL0 000107H DMA0 - Data counter high byte DCTH0 R/W 000108H DMA1 - Buffer address pointer low byte BAPL1 R/W Document Number: 002-04588 Rev. *C IOA0 R/W R/W DCT0 R/W Page 20 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (6 / 21) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 000109H DMA1 - Buffer address pointer middle byte BAPM1 R/W 00010AH DMA1 - Buffer address pointer high byte BAPH1 R/W 00010BH DMA1 - DMA control register DMACS1 R/W 00010CH DMA1 - I/O register address pointer low byte IOAL1 00010DH DMA1 - I/O register address pointer high byte IOAH1 00010EH DMA1 - Data counter low byte DCTL1 00010FH DMA1 - Data counter high byte DCTH1 R/W 000110H DMA2 - Buffer address pointer low byte BAPL2 R/W IOA1 R/W DCT1 R/W R/W 000111H DMA2 - Buffer address pointer middle byte BAPM2 R/W 000112H DMA2 - Buffer address pointer high byte BAPH2 R/W 000113H DMA2 - DMA control register DMACS2 R/W 000114H DMA2 - I/O register address pointer low byte IOAL2 000115H DMA2 - I/O register address pointer high byte IOAH2 000116H DMA2 - Data counter low byte DCTL2 000117H DMA2 - Data counter high byte DCTH2 R/W 000118H DMA3 - Buffer address pointer low byte BAPL3 R/W IOA2 R/W DCT2 R/W R/W 000119H DMA3 - Buffer address pointer middle byte BAPM3 R/W 00011AH DMA3 - Buffer address pointer high byte BAPH3 R/W 00011BH DMA3 - DMA control register DMACS3 R/W 00011CH DMA3 - I/O register address pointer low byte IOAL3 00011DH DMA3 - I/O register address pointer high byte IOAH3 00011EH DMA3 - Data counter low byte DCTL3 00011FH DMA3 - Data counter high byte DCTH3 IOA3 R/W DCT3 R/W R/W R/W 000120H-00017FH Reserved 000180H-00037FH CPU - General Purpose registers (RAM access) GPR_RAM R/W 000380H DMA0 - Interrupt select DISEL0 R/W 000381H DMA1 - Interrupt select DISEL1 R/W 000382H DMA2 - Interrupt select DISEL2 R/W 000383H DMA3 - Interrupt select DISEL3 R/W 000384H-00038FH Reserved — 000390H DMA - Status register low byte DSRL 000391H DMA - Status register high byte DSRH 000392H DMA - Stop status register low byte DSSRL 000393H DMA - Stop status register high byte DSSRH 000394H DMA - Enable register low byte DERL 000395H DMA - Enable register high byte DERH DSR R/W DSSR R/W R/W DER R/W R/W 000396H-00039FH Reserved - 0003A0H Interrupt level register ILR 0003A1H Interrupt index register IDX Document Number: 002-04588 Rev. *C R/W ICR R/W R/W Page 21 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (7 / 21) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access TBR Access 0003A2H Interrupt vector table base register Low TBRL 0003A3H Interrupt vector table base register High TBRH R/W 0003A4H Delayed Interrupt register DIRR R/W 0003A5H Non Maskable Interrupt register NMI R/W 0003A6H-0003ABH Reserved R/W - 0003ACH EDSU communication interrupt selection Low EDSU2L 0003ADH EDSU communication interrupt selection High EDSU2H R/W 0003AEH ROM mirror control register ROMM R/W EDSU 0003AFH EDSU configuration register 0003B0H Memory patch control/status register ch 0/1 0003B1H Memory patch control/status register ch 0/1 0003B2H Memory patch control/status register ch 2/3 0003B3H Memory patch control/status register ch 2/3 0003B4H Memory patch control/status register ch 4/5 0003B5H Memory patch control/status register ch 4/5 0003B6H Memory patch control/status register ch 6/7 EDSU2 R/W R/W PFCS0 R/W R/W PFCS1 R/W PFCS2 R/W R/W R/W PFCS3 R/W 0003B7H Memory patch control/status register ch 6/7 0003B8H Memory Patch function - Patch address 0 low PFAL0 R/W R/W 0003B9H Memory Patch function - Patch address 0 middle PFAM0 R/W 0003BAH Memory Patch function - Patch address 0 high PFAH0 R/W 0003BBH Memory Patch function - Patch address 1 low PFAL1 R/W 0003BCH Memory Patch function - Patch address 1 middle PFAM1 R/W 0003BDH Memory Patch function - Patch address 1 high PFAH1 R/W 0003BEH Memory Patch function - Patch address 2 low PFAL2 R/W 0003BFH Memory Patch function - Patch address 2 middle PFAM2 R/W 0003C0H Memory Patch function - Patch address 2 high PFAH2 R/W 0003C1H Memory Patch function - Patch address 3 low PFAL3 R/W 0003C2H Memory Patch function - Patch address 3 middle PFAM3 R/W 0003C3H Memory Patch function - Patch address 3 high PFAH3 R/W 0003C4H Memory Patch function - Patch address 4 low PFAL4 R/W 0003C5H Memory Patch function - Patch address 4 middle PFAM4 R/W 0003C6H Memory Patch function - Patch address 4 high PFAH4 R/W 0003C7H Memory Patch function - Patch address 5 low PFAL5 R/W 0003C8H Memory Patch function - Patch address 5 middle PFAM5 R/W 0003C9H Memory Patch function - Patch address 5 high PFAH5 R/W 0003CAH Memory Patch function - Patch address 6 low PFAL6 R/W 0003CBH Memory Patch function - Patch address 6 middle PFAM6 R/W 0003CCH Memory Patch function - Patch address 6 high PFAH6 R/W 0003CDH Memory Patch function - Patch address 7 low PFAL7 R/W Document Number: 002-04588 Rev. *C Page 22 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (8 / 21) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 0003CEH Memory Patch function - Patch address 7 middle PFAM7 R/W 0003CFH Memory Patch function - Patch address 7 high PFAH7 R/W 0003D0H Memory Patch function - Patch data 0 Low PFDL0 0003D1H Memory Patch function - Patch data 0 High PFDH0 0003D2H Memory Patch function - Patch data 1 Low PFDL1 0003D3H Memory Patch function - Patch data 1 High PFDH1 0003D4H Memory Patch function - Patch data 2 Low PFDL2 0003D5H Memory Patch function - Patch data 2 High PFDH2 0003D6H Memory Patch function - Patch data 3 Low PFDL3 0003D7H Memory Patch function - Patch data 3 High PFDH3 0003D8H Memory Patch function - Patch data 4 Low PFDL4 0003D9H Memory Patch function - Patch data 4 High PFDH4 0003DAH Memory Patch function - Patch data 5 Low PFDL5 0003DBH Memory Patch function - Patch data 5 High PFDH5 0003DCH Memory Patch function - Patch data 6 Low PFDL6 0003DDH Memory Patch function - Patch data 6 High PFDH6 0003DEH Memory Patch function - Patch data 7 Low PFDL7 0003DFH Memory Patch function - Patch data 7 High PFDH7 PFD0 R/W R/W PFD1 R/W R/W PFD2 R/W R/W PFD3 R/W R/W PFD4 R/W R/W PFD5 R/W R/W PFD6 R/W R/W PFD7 R/W R/W 0003E0H-0003F0H Reserved - 0003F1H Memory Control Status Register A MCSRA 0003F2H Memory Timing Configuration Register A Low MTCRAL 0003F3H Memory Timing Configuration Register A High MTCRAH R/W MTCRA R/W R/W 0003F4H-0003F8H Reserved - 0003F9H Flash Memory Write Control register 1 FMWC1 R/W 0003FAH Flash Memory Write Control register 2 FMWC2 R/W 0003FBH Flash Memory Write Control register 3 FMWC3 R/W 0003FCH Flash Memory Write Control register 4 FMWC4 R/W 0003FDH Flash Memory Write Control register 5 FMWC5 R/W 0003FEH-0003FFH Reserved - 000400H Standby Mode control register SMCR R/W 000401H Clock select register CKSR R/W 000402H Clock Stabilization select register CKSSR R/W 000403H Clock monitor register CKMR 000404H Clock Frequency control register Low CKFCRL 000405H Clock Frequency control register High CKFCRH 000406H PLL Control register Low PLLCRL 000407H PLL Control register High PLLCRH R/W 000408H RC clock timer control register RCTCR R/W 000409H Main clock timer control register MCTCR R/W Document Number: 002-04588 Rev. *C R CKFCR R/W R/W PLLCR R/W Page 23 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (9 / 21) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 00040AH Sub clock timer control register SCTCR R/W 00040BH Reset cause and clock status register with clear function RCCSRC R 00040CH Reset configuration register RCR R/W 00040DH Reset cause and clock status register RCCSR R 00040EH Watch dog timer configuration register WDTC R/W 00040FH Watch dog timer clear pattern register WDTCP W 000410H-000414H Reserved 000415H Clock output activation register COAR R/W 000416H Clock output configuration register 0 COCR0 R/W 000417H Clock output configuration register 1 COCR1 R/W 000418H Clock Modulator control register CMCR R/W 000419H Reserved 00041AH Clock Modulator Parameter register Low CMPRL 00041BH Clock Modulator Parameter register High CMPRH - - 00041CH-00042BH Reserved CMPR R/W R/W - 00042CH Voltage Regulator Control register VRCR R/W 00042DH Clock Input and LVD Control Register CILCR R/W 00042EH-00042FH Reserved - 000430H I/O Port P00 - Data Direction Register DDR00 R/W 000431H I/O Port P01 - Data Direction Register DDR01 R/W 000432H I/O Port P02 - Data Direction Register DDR02 R/W 000433H I/O Port P03 - Data Direction Register DDR03 R/W 000434H I/O Port P04 - Data Direction Register DDR04 R/W 000435H I/O Port P05 - Data Direction Register DDR05 R/W 000436H I/O Port P06 - Data Direction Register DDR06 R/W 000437H-000443H Reserved 000444H I/O Port P00 - Port Input Enable Register PIER00 R/W 000445H I/O Port P01 - Port Input Enable Register PIER01 R/W 000446H I/O Port P02 - Port Input Enable Register PIER02 R/W 000447H I/O Port P03 - Port Input Enable Register PIER03 R/W 000448H I/O Port P04 - Port Input Enable Register PIER04 R/W 000449H I/O Port P05 - Port Input Enable Register PIER05 R/W 00044AH I/O Port P06 - Port Input Enable Register PIER06 - 00044BH-000457H Reserved R/W - 000458H I/O Port P00 - Port Input Level Register PILR00 R/W 000459H I/O Port P01 - Port Input Level Register PILR01 R/W 00045AH I/O Port P02 - Port Input Level Register PILR02 R/W 00045BH I/O Port P03 - Port Input Level Register PILR03 R/W 00045CH I/O Port P04 - Port Input Level Register PILR04 R/W Document Number: 002-04588 Rev. *C Page 24 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (10 / 21) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access Access 00045DH I/O Port P05 - Port Input Level Register PILR05 R/W 00045EH I/O Port P06 - Port Input Level Register PILR06 R/W 00045FH-00046BH Reserved - 00046CH I/O Port P00 - Extended Port Input Level Register EPILR00 R/W 00046DH I/O Port P01 - Extended Port Input Level Register EPILR01 R/W 00046EH I/O Port P02 - Extended Port Input Level Register EPILR02 R/W 00046FH I/O Port P03 - Extended Port Input Level Register EPILR03 R/W 000470H I/O Port P04 - Extended Port Input Level Register EPILR04 R/W 000471H I/O Port P05 - Extended Port Input Level Register EPILR05 R/W 000472H I/O Port P06 - Extended Port Input Level Register EPILR06 R/W 000473H-00047FH Reserved - 000480H I/O Port P00 - Port Output Drive Register PODR00 R/W 000481H I/O Port P01 - Port Output Drive Register PODR01 R/W 000482H I/O Port P02 - Port Output Drive Register PODR02 R/W 000483H I/O Port P03 - Port Output Drive Register PODR03 R/W 000484H I/O Port P04 - Port Output Drive Register PODR04 R/W 000485H I/O Port P05 - Port Output Drive Register PODR05 R/W 000486H I/O Port P06 - Port Output Drive Register PODR06 R/W 000487H-0004A7H Reserved - 0004A8H I/O Port P00 - Pull-Up resistor Control Register PUCR00 R/W 0004A9H I/O Port P01 - Pull-Up resistor Control Register PUCR01 R/W 0004AAH I/O Port P02 - Pull-Up resistor Control Register PUCR02 R/W 0004ABH I/O Port P03 - Pull-Up resistor Control Register PUCR03 R/W 0004ACH I/O Port P04 - Pull-Up resistor Control Register PUCR04 R/W 0004ADH I/O Port P05 - Pull-Up resistor Control Register PUCR05 R/W 0004AEH I/O Port P06 - Pull-Up resistor Control Register PUCR06 R/W 0004AFH-0004BBH Reserved - 0004BCH I/O Port P00 - External Pin State Register EPSR00 R 0004BDH I/O Port P01 - External Pin State Register EPSR01 R 0004BEH I/O Port P02 - External Pin State Register EPSR02 R 0004BFH I/O Port P03 - External Pin State Register EPSR03 R 0004C0H I/O Port P04 - External Pin State Register EPSR04 R 0004C1H I/O Port P05 - External Pin State Register EPSR05 R 0004C2H I/O Port P06 - External Pin State Register EPSR06 R 0004C3H-0004CFH Reserved - 0004D0H ADC analog input enable register 0 ADER0 R/W 0004D1H ADC analog input enable register 1 ADER1 R/W 0004D2H ADC analog input enable register 2 ADER2 R/W 0004D3H ADC analog input enable register 3 ADER3 R/W Document Number: 002-04588 Rev. *C Page 25 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (11 / 21) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access ADER4 Access 0004D4H ADC analog input enable register 4 0004D5H Reserved R/W 0004D6H Peripheral Resource Relocation Register 0 PRRR0 R/W 0004D7H Peripheral Resource Relocation Register 1 PRRR1 R/W 0004D8H Peripheral Resource Relocation Register 2 PRRR2 R/W 0004D9H Peripheral Resource Relocation Register 3 PRRR3 R/W 0004DAH Peripheral Resource Relocation Register 4 PRRR4 R/W 0004DBH Peripheral Resource Relocation Register 5 PRRR5 R/W 0004DCH Peripheral Resource Relocation Register 6 PRRR6 R/W 0004DDH Peripheral Resource Relocation Register 7 PRRR7 R/W 0004DEH Peripheral Resource Relocation Register 8 PRRR8 R/W 0004DFH Peripheral Resource Relocation Register 9 PRRR9 R/W 0004E0H RTC - Sub Second Register L WTBRL0 0004E1H RTC - Sub Second Register M WTBRH0 R/W 0004E2H RTC - Sub-Second Register H WTBR1 R/W 0004E3H RTC - Second Register WTSR R/W 0004E4H RTC - Minutes WTMR R/W 0004E5H RTC - Hour WTHR R/W 0004E6H RTC - Timer Control Extended Register WTCER R/W 0004E7H RTC - Clock select register WTCKSR R/W - WTBR0 WTCR R/W 0004E8H RTC - Timer Control Register Low WTCRL 0004E9H RTC - Timer Control Register High WTCRH R/W 0004EAH CAL - Calibration unit Control register CUCR R/W 0004EBH Reserved 0004ECH CAL - Duration Timer Data Register Low CUTDL 0004EDH CAL - Duration Timer Data Register High CUTDH 0004EEH CAL - Calibration Timer Register 2 Low CUTR2L 0004EFH CAL - Calibration Timer Register 2 High CUTR2H 0004F0H CAL - Calibration Timer Register 1 Low CUTR1L 0004F1H CAL - Calibration Timer Register 1 High CUTR1H CUTD RLT - Timer input select (for Cascading) CUTR2 R R CUTR1 R R - TMISR R/W 0004FBH-0004FFH Reserved - 000500H FRT2 - Data register of free-running timer 000501H FRT2 - Data register of free-running timer 000502H FRT2 - Control status register of free-running timer Low TCCSL2 000503H FRT2 - Control status register of free-running timer High TCCSH2 000504H FRT3 - Data register of free-running timer 000505H FRT3 - Data register of free-running timer Document Number: 002-04588 Rev. *C R/W R/W 0004F2H-0004F9H Reserved 0004FAH R/W TCDT2 R/W R/W TCCS2 R/W R/W TCDT3 R/W R/W Page 26 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (12 / 21) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access TCCS3 Access 000506H FRT3 - Control status register of free-running timer Low TCCSL3 000507H FRT3 - Control status register of free-running timer High TCCSH3 R/W 000508H-000513H Reserved 000514H ICU8/ICU9 - Control Status Register 000515H ICU8/ICU9 - Edge Register ICE89 000516H ICU8 - Capture Register Low IPCPL8 000517H ICU8 - Capture Register High IPCPH8 000518H ICU9 - Capture Register Low IPCPL9 000519H ICU9 - Capture Register High IPCPH9 R 00051AH ICU10/ICU11 - Control Status Register ICS1011 R/W 00051BH ICU10/ICU11 - Edge Register ICE1011 R/W 00051CH ICU10 - Capture Register Low IPCPL10 00051DH ICU10 - Capture Register High IPCPH10 00051EH ICU11 - Capture Register Low IPCPL11 00051FH ICU11 - Capture Register High IPCPH11 R/W - ICS89 R/W R/W IPCP8 R R IPCP9 R IPCP10 R IPCP11 R R R 000520H-00053DH Reserved - 00053EH USART7 - Serial Mode Register SMR7 R/W 00053FH USART7 - Serial Control Register SCR7 R/W 000540H USART7 - Serial TX Register TDR7 W 000540H USART7 - Serial RX Register RDR7 R 000541H USART7 - Serial Status Register SSR7 R/W 000542H USART7 - Ext. Control/Com. Register ECCR7 R/W 000543H USART7 - Ext. Status Com. Register ESCR7 R/W 000544H USART7 - Baud Rate Generator Register Low BGRL7 BGR7 R/W 000545H USART7 - Baud Rate Generator Register High BGRH7 R/W 000546H USART7 - Extended Serial Interrupt Register ESIR7 R/W 000547H Reserved 000548H USART8 - Serial Mode Register 000549H USART8 - Serial Control Register SCR8 R/W 00054AH USART8 - Serial TX Register TDR8 W 00054AH USART8 - Serial RX Register RDR8 R 00054BH USART8 - Serial Status Register SSR8 R/W 00054CH USART8 - Ext. Control/Com. Register ECCR8 R/W 00054DH USART8 - Ext. Status Com. Register ESCR8 R/W 00054EH USART8 - Baud Rate Generator Register Low BGRL8 00054FH USART8 - Baud Rate Generator Register High BGRH8 R/W 000550H USART8 - Extended Serial Interrupt Register ESIR8 R/W 000551H-000563H Reserved 000564H PPG6 - Timer register Document Number: 002-04588 Rev. *C SMR8 R/W BGR8 R/W PTMR6 R Page 27 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (13 / 21) Address Register Abbreviation 8-bit Access 000565H PPG6 - Timer register 000566H PPG6 - Period setting register 000567H PPG6 - Period setting register 000568H PPG6 - Duty cycle register 000569H PPG6 - Duty cycle register 00056AH PPG6 - Control status register Low PCNL6 00056BH PPG6 - Control status register High PCNH6 00056CH PPG7 - Timer register PDUT6 PPG7 - Period setting register 00056FH PPG7 - Period setting register 000570H PPG7 - Duty cycle register 000571H PPG7 - Duty cycle register 000572H PPG7 - Control status register Low PCNL7 000573H PPG7 - Control status register High PCNH7 000574H PPG11-PPG8 - General Control register 1 Low GCN1L2 000575H PPG11-PPG8 - General Control register 1 High GCN1H2 000576H PPG11-PPG8 - General Control register 2 Low GCN2L2 000577H PPG11-PPG8 - General Control register 2 High GCN2H2 000578H PPG8 - Timer register PTMR7 R PCSR7 W W W PPG8 - Period setting register 00057BH PPG8 - Period setting register 00057CH PPG8 - Duty cycle register 00057DH PPG8 - Duty cycle register 00057EH PPG8 - Control status register Low PCNL8 00057FH PPG8 - Control status register High PCNH8 000580H PPG9 - Timer register PCN7 R/W R/W GCN12 R/W GCN22 R/W R/W R/W PTMR8 R PCSR8 W R W PDUT8 W W 000581H PPG9 - Timer register 000582H PPG9 - Period setting register 000583H PPG9 - Period setting register 000584H PPG9 - Duty cycle register 000585H PPG9 - Duty cycle register 000586H PPG9 - Control status register Low PCNL9 000587H PPG9 - Control status register High PCNH9 000588H PPG10 - Timer register Document Number: 002-04588 Rev. *C R/W PDUT7 PPG8 - Timer register PPG10 - Period setting register R/W W 000579H 00058BH PCN6 R 00057AH PPG10 - Period setting register W W PPG7 - Timer register PPG10 - Timer register W W 00056DH 000589H Access R PCSR6 00056EH 00058AH Abbreviation 16-bit Access PCN8 R/W R/W PTMR9 R PCSR9 W R W PDUT9 W W PCN9 R/W R/W PTMR10 R PCSR10 W R W Page 28 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (14 / 21) Address Register Abbreviation 8-bit Access 00058CH PPG10 - Duty cycle register 00058DH PPG10 - Duty cycle register 00058EH PPG10 - Control status register Low PCNL10 00058FH PPG10 - Control status register High PCNH10 000590H PPG11 - Timer register 000591H PPG11 - Timer register 000592H PPG11 - Period setting register 000593H PPG11 - Period setting register 000594H PPG11 - Duty cycle register 000595H PPG11 - Duty cycle register 000596H PPG11 - Control status register Low PCNL11 000597H PPG11 - Control status register High PCNH11 PDUT10 PDUT11 00059AH PPG15-PPG12 - General Control register 2 Low GCN2L3 00059BH PPG15-PPG12 - General Control register 2 High GCN2H3 00059CH PPG12 - Timer register 00059DH PPG12 - Timer register 00059EH PPG12 - Period setting register 00059FH PPG12 - Period setting register PCN11 W R/W R/W GCN13 R/W R/W GCN23 R/W R/W PTMR12 R R PCSR12 W W 0005A0H PPG12 - Duty cycle register 0005A1H PPG12 - Duty cycle register 0005A2H PPG12 - Control status register Low PCNL12 0005A3H PPG12 - Control status register High PCNH12 0005A4H PPG13 - Timer register 0005A5H PPG13 - Timer register 0005A6H PPG13 - Period setting register 0005A7H PPG13 - Period setting register PDUT12 W W PCN12 R/W R/W PTMR13 R R PCSR13 W W 0005A8H PPG13 - Duty cycle register 0005A9H PPG13 - Duty cycle register 0005AAH PPG13 - Control status register Low PCNL13 0005ABH PPG13 - Control status register High PCNH13 0005ACH PPG14 - Timer register 0005ADH PPG14 - Timer register 0005AEH PPG14 - Period setting register 0005AFH PPG14 - Period setting register Document Number: 002-04588 Rev. *C W W GCN1H3 PPG14 - Control status register Low R W GCN1L3 0005B2H R/W R/W PCSR11 PPG15-PPG12 - General Control register 1 High PPG14 - Duty cycle register W R PPG15-PPG12 - General Control register 1 Low PPG14 - Duty cycle register PCN10 PTMR11 000598H 0005B0H Access W 000599H 0005B1H Abbreviation 16-bit Access PDUT13 W W PCN13 R/W R/W PTMR14 R R PCSR14 W W PDUT14 W W PCNL14 PCN14 R/W Page 29 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (15 / 21) Address Register Abbreviation 8-bit Access 0005B3H PPG14 - Control status register High 0005B4H PPG15 - Timer register 0005B5H PPG15 - Timer register 0005B6H PPG15 - Period setting register 0005B7H PPG15 - Period setting register 0005B8H PPG15 - Duty cycle register 0005B9H PPG15 - Duty cycle register 0005BAH PPG15 - Control status register Low PCNL15 0005BBH PPG15 - Control status register High PCNH15 0005BCH PPG19-PPG16 - General Control register 1 Low GCN1L4 0005BDH PPG19-PPG16 - General Control register 1 High GCN1H4 0005BEH PPG19-PPG16 - General Control register 2 Low GCN2L4 0005BFH PPG19-PPG16 - General Control register 2 High GCN2H4 0005C0H PPG16 - Timer register 0005C1H PPG16 - Timer register 0005C2H PPG16 - Period setting register 0005C3H PPG16 - Period setting register 0005C4H PPG16 - Duty cycle register 0005C5H PPG16 - Duty cycle register 0005C6H PPG16 - Control status register Low PCNL16 0005C7H PPG16 - Control status register High PCNH16 0005C8H PPG17 - Timer register 0005C9H PPG17 - Timer register 0005CAH PPG17 - Period setting register 0005CBH PPG17 - Period setting register 0005CCH PPG17 - Duty cycle register 0005CDH PPG17 - Duty cycle register 0005CEH PPG17 - Control status register Low PCNL17 0005CFH PPG17 - Control status register High PCNH17 0005D0H PPG18 - Timer register 0005D1H PPG18 - Timer register 0005D2H PPG18 - Period setting register 0005D3H PPG18 - Period setting register 0005D4H PPG18 - Duty cycle register 0005D5H PPG18 - Duty cycle register 0005D6H PPG18 - Control status register Low PCNL18 0005D7H PPG18 - Control status register High PCNH18 0005D8H PPG19 - Timer register 0005D9H PPG19 - Timer register Document Number: 002-04588 Rev. *C Abbreviation 16-bit Access PCNH14 Access R/W PTMR15 R R PCSR15 W W PDUT15 W W PCN15 R/W R/W GCN14 R/W R/W GCN24 R/W PTMR16 R R/W R PCSR16 W W PDUT16 W W PCN16 R/W R/W PTMR17 R R PCSR17 W W PDUT17 W W PCN17 R/W R/W PTMR18 R R PCSR18 W W PDUT18 W W PCN18 R/W R/W PTMR19 R R Page 30 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (16 / 21) Address Register Abbreviation 8-bit Access 0005DAH PPG19 - Period setting register 0005DBH PPG19 - Period setting register 0005DCH PPG19 - Duty cycle register 0005DDH PPG19 - Duty cycle register 0005DEH PPG19 - Control status register Low PCNL19 0005DFH PPG19 - Control status register High PCNH19 Abbreviation 16-bit Access PCSR19 Access W W PDUT19 W W PCN19 R/W R/W 0005E0H-00065FH Reserved - 000660H Peripheral Resource Relocation Register 10 PRRR10 R/W 000661H Peripheral Resource Relocation Register 11 PRRR11 R/W 000662H Peripheral Resource Relocation Register 12 PRRR12 R/W 000663H Peripheral Resource Relocation Register 13 PRRR13 W 000664H-0006DFH Reserved - 0006E0H External Bus - Area configuration register 0 Low EACL0 0006E1H External Bus - Area configuration register 0 High EACH0 EAC0 R/W 0006E2H External Bus - Area configuration register 1 Low EACL1 0006E3H External Bus - Area configuration register 1 High EACH1 0006E4H External Bus - Area configuration register 2 Low EACL2 0006E5H External Bus - Area configuration register 2 High EACH2 0006E6H External Bus - Area configuration register 3 Low EACL3 0006E7H External Bus - Area configuration register 3 High EACH3 0006E8H External Bus - Area configuration register 4 Low EACL4 0006E9H External Bus - Area configuration register 4 High EACH4 0006EAH External Bus - Area configuration register 5 Low EACL5 0006EBH External Bus - Area configuration register 5 High EACH5 R/W R/W EAC1 R/W R/W EAC2 R/W R/W EAC3 R/W R/W EAC4 R/W R/W EAC5 R/W 0006ECH External Bus - Area select register 2 EAS2 R/W 0006EDH External Bus - Area select register 3 EAS3 R/W 0006EEH External Bus - Area select register 4 EAS4 R/W 0006EFH External Bus - Area select register 5 EAS5 R/W 0006F0H External Bus - Mode register EBM R/W 0006F1H External Bus - Clock and Function register EBCF R/W 0006F2H External Bus - Address output enable register 0 EBAE0 R/W 0006F3H External Bus - Address output enable register 1 EBAE1 R/W 0006F4H External Bus - Address output enable register 2 EBAE2 R/W 0006F5H External Bus - Control signal register EBCS R/W 0006F6H-0007FFH Reserved - 000800H CAN1 - Control register Low CTRLRL1 000801H CAN1 - Control register High (reserved) CTRLRH1 000802H CAN1 - Status register Low STATRL1 000803H CAN1 - Status register High (reserved) STATRH1 Document Number: 002-04588 Rev. *C CTRLR1 R/W R STATR1 R/W R Page 31 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (17 / 21) Address Register Abbreviation 8-bit Access 000804H CAN1 - Error Counter Low (Transmit) ERRCNTL1 000805H CAN1 - Error Counter High (Receive) ERRCNTH1 000806H CAN1 - Bit Timing Register Low BTRL1 000807H CAN1 - Bit Timing Register High BTRH1 000808H CAN1 - Interrupt Register Low INTRL1 000809H CAN1 - Interrupt Register High INTRH1 00080AH CAN1 - Test Register Low TESTRL1 00080BH CAN1 - Test Register High (reserved) TESTRH1 00080CH CAN1 - BRP Extension register Low BRPERL1 00080DH CAN1 - BRP Extension register High (reserved) BRPERH1 Abbreviation 16-bit Access ERRCNT1 R R BTR1 R/W R/W INTR1 R R TESTR1 R/W R BRPER1 R/W R 00080EH-00080FH Reserved - 000810H CAN1 - IF1 Command request register Low IF1CREQL1 000811H CAN1 - IF1 Command request register High IF1CREQH1 000812H CAN1 - IF1 Command Mask register Low IF1CMSKL1 000813H CAN1 - IF1 Command Mask register High (reserved) IF1CMSKH1 000814H CAN1 - IF1 Mask 1 Register Low IF1MSK1L1 000815H CAN1 - IF1 Mask 1 Register High IF1MSK1H1 000816H CAN1 - IF1 Mask 2 Register Low IF1MSK2L1 000817H CAN1 - IF1 Mask 2 Register High IF1MSK2H1 000818H CAN1 - IF1 Arbitration 1 Register Low IF1ARB1L1 000819H CAN1 - IF1 Arbitration 1 Register High IF1ARB1H1 00081AH CAN1 - IF1 Arbitration 2 Register Low IF1ARB2L1 00081BH CAN1 - IF1 Arbitration 2 Register High IF1ARB2H1 00081CH CAN1 - IF1 Message Control Register Low IF1MCTRL1 00081DH CAN1 - IF1 Message Control Register High IF1MCTRH1 00081EH CAN1 - IF1 Data A1 Low IF1DTA1L1 00081FH CAN1 - IF1 Data A1 High IF1DTA1H1 000820H CAN1 - IF1 Data A2 Low IF1DTA2L1 000821H CAN1 - IF1 Data A2 High IF1DTA2H1 000822H CAN1 - IF1 Data B1 Low IF1DTB1L1 000823H CAN1 - IF1 Data B1 High IF1DTB1H1 000824H CAN1 - IF1 Data B2 Low IF1DTB2L1 000825H CAN1 - IF1 Data B2 High IF1DTB2H1 IF1CREQ1 R/W R/W IF1CMSK1 R/W R IF1MSK11 R/W R/W IF1MSK21 R/W R/W IF1ARB11 R/W R/W IF1ARB21 R/W R/W IF1MCTR1 R/W IF1DTA11 R/W R/W R/W IF1DTA21 R/W IF1DTB11 R/W R/W R/W IF1DTB21 R/W R/W 000826H-00083FH Reserved - 000840H CAN1 - IF2 Command request register Low IF2CREQL1 000841H CAN1 - IF2 Command request register High IF2CREQH1 000842H CAN1 - IF2 Command Mask register Low IF2CMSKL1 000843H CAN1 - IF2 Command Mask register High (reserved) IF2CMSKH1 000844H CAN1 - IF2 Mask 1 Register Low IF2MSK1L1 Document Number: 002-04588 Rev. *C Access IF2CREQ1 R/W R/W IF2CMSK1 R/W R IF2MSK11 R/W Page 32 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (18 / 21) Address Register Abbreviation 8-bit Access 000845H CAN1 - IF2 Mask 1 Register High IF2MSK1H1 000846H CAN1 - IF2 Mask 2 Register Low IF2MSK2L1 000847H CAN1 - IF2 Mask 2 Register High IF2MSK2H1 000848H CAN1 - IF2 Arbitration 1 Register Low IF2ARB1L1 000849H CAN1 - IF2 Arbitration 1 Register High IF2ARB1H1 00084AH CAN1 - IF2 Arbitration 2 Register Low IF2ARB2L1 00084BH CAN1 - IF2 Arbitration 2 Register High IF2ARB2H1 00084CH CAN1 - IF2 Message Control Register Low IF2MCTRL1 00084DH CAN1 - IF2 Message Control Register High IF2MCTRH1 00084EH CAN1 - IF2 Data A1 Low IF2DTA1L1 00084FH CAN1 - IF2 Data A1 High IF2DTA1H1 000850H CAN1 - IF2 Data A2 Low IF2DTA2L1 000851H CAN1 - IF2 Data A2 High IF2DTA2H1 000852H CAN1 - IF2 Data B1 Low IF2DTB1L1 000853H CAN1 - IF2 Data B1 High IF2DTB1H1 000854H CAN1 - IF2 Data B2 Low IF2DTB2L1 000855H CAN1 - IF2 Data B2 High IF2DTB2H1 Abbreviation 16-bit Access R/W IF2MSK21 IF2ARB11 CAN1 - Transmission Request 1 Register Low TREQR1L1 000881H CAN1 - Transmission Request 1 Register High TREQR1H1 000882H CAN1 - Transmission Request 2 Register Low TREQR2L1 000883H CAN1 - Transmission Request 2 Register High TREQR2H1 R/W IF2ARB21 R/W R/W IF2MCTR1 R/W IF2DTA11 R/W R/W R/W IF2DTA21 R/W IF2DTB11 R/W R/W R/W IF2DTB21 R/W R/W TREQR11 R R TREQR21 R R 000884H-00088FH Reserved - 000890H CAN1 - New Data 1 Register Low 000891H CAN1 - New Data 1 Register High NEWDT1H1 000892H CAN1 - New Data 2 Register Low NEWDT2L1 000893H CAN1 - New Data 2 Register High NEWDT2H1 NEWDT1L1 NEWDT11 R NEWDT21 R R R 000894H-00089FH Reserved - 0008A0H CAN1 - Interrupt Pending 1 Register Low INTPND1L1 0008A1H CAN1 - Interrupt Pending 1 Register High INTPND1H1 0008A2H CAN1 - Interrupt Pending 2 Register Low INTPND2L1 0008A3H CAN1 - Interrupt Pending 2 Register High INTPND2H1 INTPND11 R R INTPND21 R R 0008A4H-0008AFH Reserved - 0008B0H CAN1 - Message Valid 1 Register Low MSGVAL1L1 0008B1H CAN1 - Message Valid 1 Register High MSGVAL1H1 0008B2H CAN1 - Message Valid 2 Register Low MSGVAL2L1 0008B3H CAN1 - Message Valid 2 Register High MSGVAL2H1 0008B4H-0008CDH Reserved Document Number: 002-04588 Rev. *C R/W - 000880H CAN1 - Output enable register R/W R/W 000856H-00087FH Reserved 0008CEH Access MSGVAL11 R R MSGVAL21 R R - COER1 R/W Page 33 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (19 / 21) Address Register Abbreviation 8-bit Access Abbreviation 16-bit Access 0008CFH-0008FFH Reserved - 000900H CAN2 - Control register Low CTRLRL2 000901H CAN2 - Control register High (reserved) CTRLRH2 000902H CAN2 - Status register Low STATRL2 000903H CAN2 - Status register High (reserved) STATRH2 000904H CAN2 - Error Counter Low (Transmit) ERRCNTL2 000905H CAN2 - Error Counter High (Receive) ERRCNTH2 000906H CAN2 - Bit Timing Register Low BTRL2 000907H CAN2 - Bit Timing Register High BTRH2 000908H CAN2 - Interrupt Register Low INTRL2 000909H CAN2 - Interrupt Register High INTRH2 00090AH CAN2 - Test Register Low TESTRL2 00090BH CAN2 - Test Register High (reserved) TESTRH2 00090CH CAN2 - BRP Extension register Low BRPERL2 00090DH CAN2 - BRP Extension register High (reserved) BRPERH2 CTRLR2 STATR2 R/W ERRCNT2 R R R BTR2 R/W INTR2 R R/W R TESTR2 R/W R BRPER2 R/W R - 000910H CAN2 - IF1 Command request register Low IF1CREQL2 000911H CAN2 - IF1 Command request register High IF1CREQH2 000912H CAN2 - IF1 Command Mask register Low IF1CMSKL2 000913H CAN2 - IF1 Command Mask register High (reserved) IF1CMSKH2 000914H CAN2 - IF1 Mask 1 Register Low IF1MSK1L2 000915H CAN2 - IF1 Mask 1 Register High IF1MSK1H2 000916H CAN2 - IF1 Mask 2 Register Low IF1MSK2L2 000917H CAN2 - IF1 Mask 2 Register High IF1MSK2H2 000918H CAN2 - IF1 Arbitration 1 Register Low IF1ARB1L2 000919H CAN2 - IF1 Arbitration 1 Register High IF1ARB1H2 00091AH CAN2 - IF1 Arbitration 2 Register Low IF1ARB2L2 00091BH CAN2 - IF1 Arbitration 2 Register High IF1ARB2H2 00091CH CAN2 - IF1 Message Control Register Low IF1MCTRL2 00091DH CAN2 - IF1 Message Control Register High IF1MCTRH2 00091EH CAN2 - IF1 Data A1 Low IF1DTA1L2 00091FH CAN2 - IF1 Data A1 High IF1DTA1H2 000920H CAN2 - IF1 Data A2 Low IF1DTA2L2 000921H CAN2 - IF1 Data A2 High IF1DTA2H2 000922H CAN2 - IF1 Data B1 Low IF1DTB1L2 000923H CAN2 - IF1 Data B1 High IF1DTB1H2 000924H CAN2 - IF1 Data B2 Low IF1DTB2L2 000925H CAN2 - IF1 Data B2 High IF1DTB2H2 Document Number: 002-04588 Rev. *C R/W R 00090EH-00090FH Reserved 000926H-00093FH Reserved Access IF1CREQ2 R/W R/W IF1CMSK2 R/W R IF1MSK12 R/W R/W IF1MSK22 R/W R/W IF1ARB12 R/W R/W IF1ARB22 R/W R/W IF1MCTR2 R/W R/W IF1DTA12 R/W R/W IF1DTA22 R/W R/W IF1DTB12 R/W R/W IF1DTB22 R/W R/W - Page 34 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (20 / 21) Address Register Abbreviation 8-bit Access 000940H CAN2 - IF2 Command request register Low IF2CREQL2 000941H CAN2 - IF2 Command request register High IF2CREQH2 000942H CAN2 - IF2 Command Mask register Low IF2CMSKL2 000943H CAN2 - IF2 Command Mask register High (reserved) IF2CMSKH2 000944H CAN2 - IF2 Mask 1 Register Low IF2MSK1L2 000945H CAN2 - IF2 Mask 1 Register High IF2MSK1H2 000946H CAN2 - IF2 Mask 2 Register Low IF2MSK2L2 000947H CAN2 - IF2 Mask 2 Register High IF2MSK2H2 000948H CAN2 - IF2 Arbitration 1 Register Low IF2ARB1L2 000949H CAN2 - IF2 Arbitration 1 Register High IF2ARB1H2 00094AH CAN2 - IF2 Arbitration 2 Register Low IF2ARB2L2 00094BH CAN2 - IF2 Arbitration 2 Register High IF2ARB2H2 00094CH CAN2 - IF2 Message Control Register Low IF2MCTRL2 00094DH CAN2 - IF2 Message Control Register High IF2MCTRH2 00094EH CAN2 - IF2 Data A1 Low IF2DTA1L2 00094FH CAN2 - IF2 Data A1 High IF2DTA1H2 000950H CAN2 - IF2 Data A2 Low IF2DTA2L2 000951H CAN2 - IF2 Data A2 High IF2DTA2H2 000952H CAN2 - IF2 Data B1 Low IF2DTB1L2 000953H CAN2 - IF2 Data B1 High IF2DTB1H2 000954H CAN2 - IF2 Data B2 Low IF2DTB2L2 000955H CAN2 - IF2 Data B2 High IF2DTB2H2 Abbreviation 16-bit Access IF2CREQ2 CAN2 - Transmission Request 1 Register Low IF2CMSK2 TREQR1L2 000981H CAN2 - Transmission Request 1 Register High TREQR1H2 CAN2 - Transmission Request 2 Register Low TREQR2L2 000983H CAN2 - Transmission Request 2 Register High TREQR2H2 R IF2MSK12 IF2MSK22 R/W R/W IF2ARB12 R/W R/W IF2ARB22 R/W R/W IF2MCTR2 R/W R/W IF2DTA12 R/W R/W IF2DTA22 R/W R/W IF2DTB12 R/W R/W IF2DTB22 R/W R/W TREQR12 R TREQR22 R R R - 000990H CAN2 - New Data 1 Register Low NEWDT1L2 000991H CAN2 - New Data 1 Register High NEWDT1H2 000992H CAN2 - New Data 2 Register Low NEWDT2L2 000993H CAN2 - New Data 2 Register High NEWDT2H2 NEWDT12 R R NEWDT22 R R 000994H-00099FH Reserved - 0009A0H CAN2 - Interrupt Pending 1 Register Low INTPND1L2 0009A1H CAN2 - Interrupt Pending 1 Register High INTPND1H2 0009A2H CAN2 - Interrupt Pending 2 Register Low INTPND2L2 0009A3H CAN2 - Interrupt Pending 2 Register High INTPND2H2 INTPND12 R R INTPND22 R R 0009A4H-0009AFH Reserved Document Number: 002-04588 Rev. *C R/W R/W 000984H-00098FH Reserved CAN2 - Message Valid 1 Register Low R/W - 000982H 0009B0H R/W R/W 000956H-00097FH Reserved 000980H Access MSGVAL1L2 MSGVAL12 R Page 35 of 98 CY96F353/F355 CY96F356 Table 4. I/O Map CY96(F)35x (21 / 21) Address Register Abbreviation 8-bit Access 0009B1H CAN2 - Message Valid 1 Register High MSGVAL1H2 0009B2H CAN2 - Message Valid 2 Register Low MSGVAL2L2 0009B3H CAN2 - Message Valid 2 Register High MSGVAL2H2 0009B4H-0009CDH Reserved 0009CEH CAN2 - Output enable register 0009CFH-000BFFH Reserved Abbreviation 16-bit Access Access R MSGVAL22 R R - COER2 R/W - Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved address results in reading ‘X’. Registers of resources which are described in this table, but which are not supported by the device, should also be handled as “Reserved”. Document Number: 002-04588 Rev. *C Page 36 of 98 CY96F353/F355 CY96F356 Interrupt Vector Table Table 5. Interrupt Vector Table CY96(F)35x (1 / 3) Vector Number Offset in Vector Table Vector Name Cleared by DMA Index in ICR to Program Description 0 3FCH CALLV0 No - 1 3F8H CALLV1 No - 2 3F4H CALLV2 No - 3 3F0H CALLV3 No - 4 3ECH CALLV4 No - 5 3E8H CALLV5 No - 6 3E4H CALLV6 No - 7 3E0H CALLV7 No - 8 3DCH RESET No - 9 3D8H INT9 No - 10 3D4H EXCEPTION No - 11 3D0H NMI No - Non-Maskable Interrupt 12 3CCH DLY No 12 Delayed Interrupt 13 3C8H RC_TIMER No 13 RC Timer 14 3C4H MC_TIMER No 14 Main Clock Timer 15 3C0H SC_TIMER No 15 Sub Clock Timer 16 3BCH PLL_UNLOCK No 16 Reserved 17 3B8H EXTINT0 Yes 17 External Interrupt 0 18 3B4H 19 3B0H EXTINT2 Yes 19 External Interrupt 2 20 3ACH EXTINT3 Yes 20 External Interrupt 3 21 3A8H EXTINT4 Yes 21 External Interrupt 4 22 3A4H 23 3A0H EXTINT7 Yes 23 External Interrupt 7 24 39CH EXTINT8 Yes 24 External Interrupt 8 25 398H EXTINT9 Yes 25 External Interrupt 9 26 394H EXTINT10 Yes 26 External Interrupt 10 27 390H EXTINT11 Yes 27 External Interrupt 11 28 38CH EXTINT12 Yes 28 External Interrupt 12 29 388H EXTINT13 Yes 29 External Interrupt 13 30 384H EXTINT14 Yes 30 External Interrupt 14 31 380H EXTINT15 Yes 31 External Interrupt 15 32 37CH CAN1 No 32 CAN Controller 1 (only CY96F356Y/R) 33 378H CAN2 No 33 CAN Controller 2 (only CY96F356Y/R and CY96F353R/F355R) 34 374H PPG0 Yes 34 Programmable Pulse Generator 0 35 370H PPG1 Yes 35 Programmable Pulse Generator 1 Reserved Reserved Document Number: 002-04588 Rev. *C Page 37 of 98 CY96F353/F355 CY96F356 Table 5. Interrupt Vector Table CY96(F)35x (2 / 3) Vector Number Offset in Vector Table Vector Name Cleared by DMA Index in ICR to Program Description 36 36CH PPG2 Yes 36 Programmable Pulse Generator 2 37 368H PPG3 Yes 37 Programmable Pulse Generator 3 38 364H PPG4 Yes 38 Programmable Pulse Generator 4 39 360 PPG5 Yes 39 Programmable Pulse Generator 5 40 35CH PPG6 Yes 40 Programmable Pulse Generator 6 41 358H PPG7 Yes 41 Programmable Pulse Generator 7 42 354H PPG8 Yes 42 Programmable Pulse Generator 8 43 350H PPG9 Yes 43 Programmable Pulse Generator 9 44 34CH PPG10 Yes 44 Programmable Pulse Generator 10 45 348H PPG11 Yes 45 Programmable Pulse Generator 11 46 344H PPG12 Yes 46 Programmable Pulse Generator 12 47 340H PPG13 Yes 47 Programmable Pulse Generator 13 48 33CH PPG14 Yes 48 Programmable Pulse Generator 14 49 338H PPG15 Yes 49 Programmable Pulse Generator 15 50 334H PPG16 Yes 50 Programmable Pulse Generator 16 51 330H PPG17 Yes 51 Programmable Pulse Generator 17 52 32CH PPG18 Yes 52 Programmable Pulse Generator 18 53 328H PPG19 Yes 53 Programmable Pulse Generator 19 54 324H RLT0 Yes 54 Reload Timer 0 55 320H RLT1 Yes 55 Reload Timer 1 56 31CH RLT2 Yes 56 Reload Timer 2 57 318H RLT3 Yes 57 Reload Timer 3 58 314H PPGRLT Yes 58 Reload Timer 6 - dedicated for PPG 59 310H ICU0 Yes 59 Input Capture Unit 0 60 30CH ICU1 Yes 60 Input Capture Unit 1 61 308H Reserved 62 304H Reserved 63 300H ICU4 Yes 63 Input Capture Unit 4 64 2FCH ICU5 Yes 64 Input Capture Unit 5 65 2F8H ICU6 Yes 65 Input Capture Unit 6 66 2F4H ICU7 Yes 66 Input Capture Unit 7 67 2F0H 68 2ECH ICU9 Yes 68 Input Capture Unit 9 69 2E8H ICU10 Yes 69 Input Capture Unit 10 70 2E4H 71 2E0H OCU4 Yes 71 Output Compare Unit 4 72 2DCH OCU5 Yes 72 Output Compare Unit 5 73 2D8H OCU6 Yes 73 Output Compare Unit 6 Reserved Reserved Document Number: 002-04588 Rev. *C Page 38 of 98 CY96F353/F355 CY96F356 Table 5. Interrupt Vector Table CY96(F)35x (3 / 3) Vector Number Offset in Vector Table Vector Name OCU7 Cleared by DMA 74 Description 74 2D4H 75 2D0H Reserved 76 2CCH Reserved 77 2C8H FRT0 Yes 77 Free Running Timer 0 78 2C4H FRT1 Yes 78 Free Running Timer 1 79 2C0H FRT2 Yes 79 Free Running Timer 2 80 2BCH FRT3 Yes 80 Free Running Timer 3 81 2B8H RTC0 No 81 Real Timer Clock 82 2B4H CAL0 No 82 Clock Calibration Unit 83 2B0H IIC0 Yes 83 I2C interface 84 2ACH ADC0 Yes 84 A/D Converter 85 2A8H LINR2 Yes 85 LIN USART 2 RX 86 2A4H LINT2 Yes 86 LIN USART 2 TX 87 2A0H LINR3 Yes 87 LIN USART 3 RX 88 29CH LINT3 Yes 88 LIN USART 3 TX 89 298H LINR7 Yes 89 LIN USART 7 RX 90 294H LINT7 Yes 90 LIN USART 7 TX 91 290H LINR8 Yes 91 LIN USART 8 RX 92 28CH LINT8 Yes 92 LIN USART 8 TX 93 288H FLASH_A No 93 Flash memory A (only Flash devices) Document Number: 002-04588 Rev. *C Yes Index in ICR to Program Output Compare Unit 7 Page 39 of 98 CY96F353/F355 CY96F356 Handling Devices Special care is required for the following when handling the device: ■ Latch-up prevention ■ Unused pins handling ■ External clock usage ■ Unused sub clock signal ■ Notes on PLL clock mode operation ■ Power supply pins (VCC/VSS) ■ Crystal oscillator and ceramic resonator circuit ■ Turn on sequence of power supply to A/D converter and analog inputs ■ Pin handling when not using the A/D converter ■ Notes on energization ■ Stabilization of power supply voltage ■ Serial communication ■ Clock modulator 1. Latch-up Prevention CMOS IC chips may suffer latch-up under the following conditions: ■ A voltage higher than VCC or lower than VSS is applied to an input or output pin. ■ A voltage higher than the rated voltage is applied between VCC pins and VSS pins. Latch-up may increase the power supply current dramatically, causing thermal damages to the device. 2. Unused Pins Handling Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0). Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. They must therefore be pulled up or pulled down through resistors. To prevent latch-up, those resistors should be more than 2 kΩ. Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above. 3. External Clock Usage The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows: 1. Single phase external clock ❐ When using a single phase external clock, X0 (X0A) pin must be driven and X1 (X1A) pin left open. X0 X1 Document Number: 002-04588 Rev. *C Page 40 of 98 CY96F353/F355 CY96F356 2. Opposite phase external clock ❐ When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. X0 X1 4. Unused Sub Clock Signal If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A pin and the X1A pin must be left open. 5. Notes on PLL Clock Mode Operation If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed. 6. Power Supply Pins (VCC/VSS) It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range. VCC and VSS must be connected to the device from the power supply with lowest possible impedance. As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 μF between VCC and VSS as close as possible to VCC and VSS pins. Please add the bypass capacitor of the power supply in order to not exceed 0.1V/μs. 7. Crystal Oscillator and Ceramic Resonator Circuit Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area for stabilizing the operation. It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially when using low-Q resonators at higher frequencies. 8. Turn on Sequence of Power Supply to A/D Converter and Analog Inputs It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital power supply (VCC) on. It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable). 9. Pin Handling when Not Using the A/D Converter It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS. 10. Notes on Power-on To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50 μs from 0.2 V to 2.7 V. 11. Stabilization of Power Supply Voltage If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage, a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10 % of the standard Vcc power supply voltage and the transient fluctuation rate becomes 0.1 V/μs or less in instantaneous fluctuation for power supply switching. Document Number: 002-04588 Rev. *C Page 41 of 98 CY96F353/F355 CY96F356 12. Serial Communication There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit the data if an error occurs. 13. Clock modulator Please contact Cypress before using this function. Document Number: 002-04588 Rev. *C Page 42 of 98 CY96F353/F355 CY96F356 Electrical Characteristics Absolute Maximum Ratings Parameter Rating Symbol Min Max Unit Remarks VCC VSS - 0.3 VSS + 6.0 V AVCC VSS - 0.3 VSS + 6.0 V VCC = AVCC *1 AD Converter voltage references AVRH, AVRL VSS - 0.3 VSS + 6.0 V AVCC ≥ AVRH, AVCC ≥ AVRL, AVRH > AVRL, AVRL ≥ AVSS Input voltage VI VSS - 0.3 VSS + 6.0 V VI ≤ VCC + 0.3 V *2 Output voltage VO VSS - 0.3 VSS + 6.0 V VO ≤ VCC + 0.3 V *2 Maximum Clamp Current ICLAMP -4.0 +4.0 mA Applicable to general purpose I/O pins *3 Total Maximum Clamp Current Σ|ICLAMP| - 40 mA Applicable to general purpose I/O pins *3 “L” level maximum output current IOL1 - 15 mA Outputs with driving strength set to 2 mA /3 mA /5 mA “L” level average output current IOLAV2 - 2 mA Outputs with driving strength set to 2mA IOLAV3 - 3 mA Outputs of I/O circuit type “N” IOLAV5 - 5 mA Outputs with driving strength set to 5mA “L” level maximum overall output current ΣIOL1 - 100 mA Normal outputs “L” level average overall output current ΣIOLAV1 - 50 mA Normal outputs ”H” level maximum output current IOH1 - -15 mA Outputs with driving strength set to 2 mA /3 mA /5 mA ”H” level average output current IOHAV2 - -2 mA Outputs with driving strength set to 2 mA IOHAV3 - -3 mA Outputs of I/O circuit type “N” IOHAV5 - -5 mA Outputs with driving strength set to 5 mA ΣIOH1 - -100 mA Normal outputs ΣIOHAV1 - -50 mA Normal outputs - 320 *5 mW TA=105 oC - 640 *5 mW TA=85 oC - 800 *5 mW TA=75 oC - 400 *5 mW TA=125 *6 oC, no Flash program/erase - 560 *5 mW TA=115 *6 oC, no Flash program/erase 0 +70 o CY96V300C -40 +105 -40 +125 -55 +150 Power supply voltage ”H” level maximum overall output current ”H” level average overall output current Permitted Power dissipation (Flash devices) Operating ambient temperature Storage temperature *4 PD TA TSTG C *6 o C *1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC neither when the power is switched on. Document Number: 002-04588 Rev. *C Page 43 of 98 CY96F353/F355 CY96F356 *2: VI and VO should not exceed VCC + 0.3 V. VI should also not exceed the specified ratings. However if the maximum current to/from a input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/output voltages of standard ports depend on VCC. *3: ■ Applicable to all general-purpose I/O pins (Pnn_m). ■ Use within recommended operating conditions. ■ Use at DC voltage (current) ■ The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. ■ The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. ■ Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. ■ Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. ■ Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset (except devices with persistent low voltage reset in internal vector mode). ■ Sample recommended circuits: Protective Diode VCC Limiting resistance P-ch +B input (0V to 16V) N-ch R *4: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance of the package on the PCB. The actual power dissipation depends on the customer application and can be calculated as follows: PD = PIO + PINT PIO = S (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports) PINT = VCC * (ICC + IA) (internal power dissipation) ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the selected operation mode and clock frequency and the usage of functions like Flash programming or the clock modulator. IA is the analog current consumption into AVCC. *5: Worst case value for a package mounted on single layer PCB at specified TA without air flow. *6: Please contact Cypress for reliability limitations when using under these conditions. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-04588 Rev. *C Page 44 of 98 CY96F353/F355 CY96F356 Recommended Operating Conditions Parameter Value Symbol Min Typ Max Unit Power supply voltage VCC 3.0 - 5.5 V Smoothing capacitor at C pin CS 3.5 4.7 15 μF Remarks Use a X7R ceramic capacitor or a capacitor that has similar frequency characteristics. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: 002-04588 Rev. *C Page 45 of 98 CY96F353/F355 CY96F356 DC Characteristics (TA = -40 °C to 125 °C, VCC = AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Parameter Input H voltage Symbol VIH Pin Port inputs Pnn_m Condition Value Min Max Unit VCC + 0.3 V CMOS Hysteresis 0.7 VCC 0.7/0.3 input selected 0.74 VCC VCC + 0.3 V VCC ≥ 4.5 V VCC + 0.3 V VCC < 4.5 V 0.8 VCC - VCC + 0.3 V - VCC + 0.3 V 0.8 VCC - VCC + 0.3 V - VCC + 0.3 V TTL input selected 2.0 VIHX0F X0 External clock in “Fast Clock Input mode” VIHX0S X0,X1, X0A,X1A External clock in 2.5 “oscillation mode” VIHR RSTX - 0.8 VCC - VCC + 0.3 V VIHM MD2-MD0 - VCC 0.3 - VCC + 0.3 V VIL Port inputs Pnn_m CMOS Hysteresis VSS 0.8/0.2 input 0.3 selected - 0.2 VCC V CMOS Hysteresis VSS 0.3 0.7/0.3 input selected - 0.3 VCC V VSS 0.3 - 0.5 VCC V VSS 0.3 - 0.46 VCC TTL input selected VSS 0.3 - 0.8 AUTOMOTIVE Hysteresis input selected CMOS Hysteresis input VCC ≥ 4.5 V VCC < 4.5 V V VILX0F X0 External clock in “Fast Clock Input mode” VSS 0.3 - 0.2 VCC V VILX0S X0,X1, X0A,X1A External clock in VSS “oscillation mode” 0.3 - 0.4 VILR RSTX - VSS 0.3 - 0.2 VCC V VILM MD2-MD0 - VSS 0.3 - VSS + 0.3 Document Number: 002-04588 Rev. *C Remarks CMOS Hysteresis 0.8 VCC 0.8/0.2 input selected AUTOMOTIVE Hysteresis input selected Input L voltage Typ V CMOS Hysteresis input V Page 46 of 98 CY96F353/F355 CY96F356 (TA = -40 °C to 125 °C, VCC = AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Parameter Output H voltage Symbol VOH2 Pin Normal outputs Condition Value Min 4.5 V ≤ VCC ≤ 5.5 V VCC IOH = -2 mA 0.5 Typ Max Unit Remarks - - V Driving strength set to 2 mA (PODR:OD=1) - - V Driving strength set to 5 mA (PODR:OD=0) - - V I/O circuit type "N" - 0.4 V Driving strength set to 2 mA - 0.4 V Driving strength set to 5 mA - 0.4 V I/O circuit type "N" Single port pin 3.0 V ≤ VCC < 4.5 V IOH = -1.6 mA VOH5 Normal outputs 4.5 V ≤ VCC ≤ 5.5 V VCC IOH = -5 mA 0.5 3.0 V ≤ VCC < 4.5 V IOH = -3 mA VOH3 3 mA outputs 4.5 V ≤ VCC ≤ 5.5 V VCC IOH = -3 mA 0.5 3.0 V ≤ VCC < 4.5 V IOH = -2 mA Output L voltage VOL2 Normal outputs 4.5 V ≤ VCC ≤ 5.5 V IOL = +2 mA 3.0 V ≤ VCC < 4.5 V IOL = +1.6 mA VOL5 Normal outputs 4.5 V ≤ VCC ≤ 5.5 V IOL = +5 mA 3.0 V ≤ VCC < 4.5 V IOL = +3 mA VOL3 3 mA outputs 3.0 V ≤ VCC ≤ 5.5 V IOL = +3 mA Input leak current IIL Pnn_m -1 VSS < VI < VCC AVSS, AVRL < VI < AVCC, AVRH - +1 μA Pull-up resistance RUP Pnn_m, RSTX VCC = 3.3 V+10 % 40 100 160 kΩ VCC = 5.0 V+10 % 25 50 100 kΩ Document Number: 002-04588 Rev. *C Page 47 of 98 CY96F353/F355 CY96F356 (TA = -40 °C to 125 °C, VCC = AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Power supply current ICCPLL in Run modes *1 Typ Max PLL Run mode with CLKS1/2 +25 °C = CLKB = CLKP1 = 16MHz, +125 °C CLKP2 = 8MHz 1 Flash/ROM wait state +25 °C (CLKRC and CLKSC stopped) +125 °C 14.5 19.5 16 23 15 20 16.5 23.5 PLL Run mode with CLKS1/2 +25 °C = CLKB = CLKP1= 32MHz, CLKP2 = 16MHz +125 °C 2 Flash/ROM wait states (CLKRC and CLKSC +25 °C stopped) +125 °C 23 29 25 33 24 30 26 34 PLL Run mode with CLKS1/2 +25 °C = 48MHz, +125 °C CLKB = CLKP1/2 = 24MHz 0 Flash/ROM wait states +25 °C (CLKRC and CLKSC stopped) 26 38 28 42 28 40 +125 °C 30 44 PLL Run mode with CLKS1/2 +25 °C = CLKB = CLKP1= 56MHz, +125 °C CLKP2 = 28MHz 2 Flash/ROM wait states +25 °C (CLKRC and CLKSC stopped. Core voltage at 1.9V) +125 °C 40 51 42 55 41 52 43 56 +25 °C 43 56 +125 °C 45 60 +25 °C 44 58 +125 °C 46 62 4 5 PLL Run mode with CLKS1/2 = 96MHz, CLKB = CLKP1= 48MHz, CLKP2 = 24MHz 1 Flash/ROM wait state (CLKRC and CLKSC stopped. Core voltage at 1.9V) ICCMAIN Value Condition (at TA) Main Run mode with CLKS1/2 +25 °C = CLKB = CLKP1/2 = 4 MHz 1 Flash/ROM wait state +125 °C (CLKPLL, CLKSC and +25 °C CLKRC stopped) 4.7 8 4.2 5.2 +125 °C 4.9 8.2 Document Number: 002-04588 Rev. *C Unit Remarks mA CY96F353/F355 mA CY96F356 mA CY96F353/F355 mA CY96F356 mA CY96F353/F355 mA CY96F356 mA CY96F353/F355 mA CY96F356 mA CY96F353/F355 mA CY96F356 mA CY96F353/F355 mA CY96F356 Page 48 of 98 CY96F353/F355 CY96F356 (TA = -40 °C to 125 °C, VCC = AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Power supply current ICCRCH in Run modes *1 ICCRCL ICCSUB Value Condition (at TA) Typ Max RC Run mode with CLKS1/2 = +25 °C CLKB = CLKP1/2 = 2 MHz 1 Flash/ROM wait state +125 °C (CLKMC, CLKPLL and CLKSC stopped) +25 °C 2.5 3.5 3.2 6.5 2.7 3.7 +125 °C 3.4 6.7 +25 °C 0.18 0.3 +125 °C 0.73 3.1 +25 °C 0.4 0.6 +125 °C 0.95 3.4 RC Run mode with CLKS1/2 = +25 °C CLKB = CLKP1/2 = 100 kHz, SMCR:LPMS = 1 +125 °C 1 Flash/ROM wait state (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode, no Flash programming/ erasing allowed) 0.15 0.25 0.7 3.05 Sub Run mode with CLKS1/2 = +25 °C CLKB = CLKP1/2 = 32 kHz 1 Flash/ROM wait state +125 °C (CLKMC, CLKPLL and CLKRC stopped, no Flash programming/erasing allowed) 0.1 0.2 0.65 3 RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 100 kHz, SMCR:LPMS = 0 1 Flash/ROM wait state (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) Document Number: 002-04588 Rev. *C Unit Remarks mA CY96F353/F355 mA CY96F356 mA CY96F353/F355 mA CY96F356 mA CY96F353/F355/356 mA CY96F353/F355/356 Page 49 of 98 CY96F353/F355 CY96F356 (TA = -40 °C to 125 °C, VCC = AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Power supply current ICCSPLL in Sleep modes *1 Value Condition (at TA) Typ +25 °C 4 6 +125 °C 4.7 9 +25 °C 7 9.5 8 12.5 +25 °C 7 9 +125 °C 8 12 PLL Sleep mode with CLKS1/2 = CLKP1= 56MHz, CLKP2 = 28MHz (CLKRC and CLKSC stopped. Core voltage at 1.9V) +25 °C 11 14.5 +125 °C 12 17.5 PLL Sleep mode with CLKS1/2 = 96MHz, CLKP1= 48MHz, CLKP2 = 24MHz (CLKRC and CLKSC stopped. Core voltage at 1.9V) +25 °C 12 15 +125 °C 13 18 1 1.3 1.6 4.1 +25 °C 1.3 1.8 +125 °C 1.9 4.6 0.55 1.1 1.15 3.9 +25 °C 0.8 1.4 +125 °C 1.4 4.2 PLL Sleep mode with CLKS1/2 = CLKP1 = 16MHz, CLKP2 = 8MHz (CLKRC and CLKSC stopped) PLL Sleep mode with CLKS1/2 = CLKP1= 32MHz, +125 °C CLKP2 = 16MHz (CLKRC and CLKSC stopped) PLL Sleep mode with CLKS1/2 = 48MHz, CLKP1/2 = 24MHz (CLKRC and CLKSC stopped) ICCSMAIN ICCSRCH Max Main Sleep mode with +25 °C CLKS1/2 = CLKP1/2 = 4 MHz (CLKPLL, CLKSC and CLKRC +125 °C stopped) RC Sleep mode with CLKS1/2 +25 °C = CLKP1/2 = 2 MHz (CLKMC, CLKPLL and CLKSC +125 °C stopped) Document Number: 002-04588 Rev. *C Unit Remarks mA CY96F353/F355/F356 mA CY96F353/F355/F356 mA CY96F353/F355/F356 mA CY96F353/F355/F356 mA CY96F353/F355/F356 mA CY96F353/F355 mA CY96F356 mA CY96F353/F355 mA CY96F356 Page 50 of 98 CY96F353/F355 CY96F356 (TA = -40 °C to 125 °C, VCC = AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Power supply current ICCSRCL in Sleep modes *1 Value Condition (at TA) Typ RC Sleep mode with CLKS1/2 +25 °C = CLKP1/2 = 100 kHz, SMCR:LPMSS = 0 +125 °C (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in +25 °C high power mode) 0.08 0.2 0.59 2.95 0.3 0.5 0.8 3.3 RC Sleep mode with CLKS1/2 +25 °C = CLKP1/2 = 100 kHz, SMCR:LPMSS = 1 +125 °C (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) 0.05 0.15 0.56 2.9 Sub Sleep mode with CLKS1/2 +25 °C = CLKP1/2 = 32 kHz (CLKMC, CLKPLL and CLKRC +125 °C stopped) 0.04 0.12 0.53 2.9 PLL Timer mode with CLKMC +25 °C = 4 MHz, CLKPLL = 48 MHz (CLKRC and CLKSC stopped.) +125 °C 1.3 1.8 1.9 4.8 +25 °C 1.5 2 +125 °C 2.1 5 +125 °C ICCSSUB Power supply current ICCTPLL in Timer modes *1 Max Document Number: 002-04588 Rev. *C Unit Remarks mA CY96F353/F355 mA CY96F356 mA CY96F353/F355/F356 mA CY96F353/F355/F356 mA CY96F353/F355 mA CY96F356 Page 51 of 98 CY96F353/F355 CY96F356 (TA = -40 °C to 125 °C, VCC = AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Power supply current ICCTMAIN in Timer modes * ICCTRCH ICCTRCL Value Condition (at TA) Typ Main Timer mode with CLKMC +25 °C = 4 MHz, SMCR:LPMSS = 0 +125 °C (CLKPLL, CLKRC and CLKSC stopped. Voltage regulator in +25 °C high power mode) 0.11 0.2 0.63 3 0.35 0.5 +125 °C 0.85 3.3 Main Timer mode with CLKMC +25 °C = 4 MHz, SMCR:LPMSS = 1 +125 °C (CLKPLL, CLKRC and CLKSC stopped. Voltage regulator in low power mode) 0.08 0.15 0.6 2.9 RC Timer mode with CLKRC = +25 °C 2 MHz, SMCR:LPMSS = 0 +125 °C (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in +25 °C high power mode) 0.1 0.2 0.63 3 0.35 0.5 +125 °C 0.85 3.3 RC Timer mode with CLKRC = +25 °C 2 MHz, SMCR:LPMSS = 1 +125 °C (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) 0.07 0.15 0.6 2.9 RC Timer mode with CLKRC = +25 °C 100 kHz, SMCR:LPMSS = 0 +125 °C (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in +25 °C high power mode) 0.06 0.15 0.56 2.95 0.3 0.45 0.8 3.2 RC Timer mode with CLKRC = +25 °C 100 kHz, SMCR:LPMSS = 1 +125 °C (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) 0.03 0.1 0.53 2.85 Sub Timer mode with CLKSC +25 °C = 32 kHz (CLKMC, CLKPLL and CLKRC +125 °C stopped) 0.035 0.1 0.53 2.85 +125 °C ICCTSUB Max Document Number: 002-04588 Rev. *C Unit Remarks mA CY96F353/F355 mA CY96F356 mA CY96F353/F355/F356 mA CY96F353/F355 mA CY96F356 mA CY96F353/F355/F356 mA CY96F353/F355 mA CY96F356 mA CY96F353/F355/F356 mA CY96F353/F355/F356 Page 52 of 98 CY96F353/F355 CY96F356 (TA = -40 °C to 125 °C, VCC = AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Power supply current ICCH in Stop Mode VRCR:LPMB[2:0] = 110B (Core voltage at 1.8 V) VRCR:LPMB[2:0] = 000B (Core voltage at 1.2 V) Power supply current ICCLVD for active Low Voltage detector Value Condition (at TA) Typ Max Unit Remarks +25 °C 0.02 0.08 +125 °C 0.52 2.8 +25 °C 0.015 0.06 +125 °C 0.4 2.3 5 10 7 20 +25 °C 90 140 +125 °C 100 150 - 3 4.5 mA Must be added to all current above Low voltage detector enabled +25 °C (RCR:LVDE = 1) +125 °C mA CY96F353/F355/F356 mA CY96F353/F355/F356 μA CY96F353/F355 Must be added to all current above μA CY96F356 Must be added to all current above Power supply current ICCCLOMO for active Clock modulator Clock modulator enabled (CMCR:PDX = 1) Flash Write/Erase current ICCFLASH Current for one Flash module - 15 40 mA Must be added to all current above Input capacitance CIN - 5 15 pF Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS - *: The power supply current is measured with a 4 MHz external clock connected to the Main oscillator and a 32 kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for further details about voltage regulator control. Document Number: 002-04588 Rev. *C Page 53 of 98 CY96F353/F355 CY96F356 AC Characteristics Source Clock Timing (TA = -40 °C to 125 °C, VCC = AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Parameter Clock frequency Clock frequency Clock frequency Clock frequency Symbol fC fFCI fCL fCR Value Pin X0, X1 Min Typ Max Unit Remarks 3 - 16 MHz When using a crystal oscillator, PLL off 0 - 16 MHz When using an opposite phase external clock, PLL off 3.5 - 16 MHz When using a crystal oscillator or opposite phase external clock, PLL on 0 - 56 MHz When using a single phase external clock in “Fast Clock Input mode”, PLL off 3.5 - 56 MHz When using a single phase external clock in “Fast Clock Input mode”, PLL on 32 32.768 100 kHz When using an oscillation circuit 0 - 100 kHz When using an opposite phase external clock X0A 0 - 50 kHz When using a single phase external clock - 50 100 200 kHz When using slow frequency of RC oscillator 1 2 4 MHz When using fast frequency of RC oscillator X0 X0A, X1A tRCSTAB - 64 or 256 RC clock cycles PLL Clock frequency fCLKVCO - 64 - 200 MHz Permitted VCO output frequency of PLL (CLKVCO) PLL Phase Jitter TPSKEW - - - +5 ns For CLKMC (PLL input clock) ≥ 4 MHz, jitter Input clock pulse width PWH, PWL X0, X1 8 - - ns Input clock pulse width PWHL, PWLL X0A, X1A 5 - - μs RC clock stabilization time Applied after any reset and when activating the RC oscillator. CY96F356: 64 cycles others: 256 cycles coming from external oscillator, crystal or resonator is not covered. Document Number: 002-04588 Rev. *C Duty ratio is about 30 % to 70 % Page 54 of 98 CY96F353/F355 CY96F356 tCYL VIH X0 VIL PWH PWL tCYLL VIH X0A VIL PWHL Document Number: 002-04588 Rev. *C PWLL Page 55 of 98 CY96F353/F355 CY96F356 Internal Clock Timing (TA = -40 °C to 125 °C, VCC = AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Core Voltage Settings Parameter Symbol 1.8 V Min Internal System clock fCLKS1, fCLKS2 frequency (CLKS1 and CLKS2) 1.9 V Max Unit Min Remarks Max 0 92 0 96 MHz Others than below 0 88 0 96 MHz CY96F356 Internal CPU clock frequency (CLKB), internal peripheral clock frequency (CLKP1) fCLKB, fCLKP1 0 52 0 56 MHz Internal peripheral clock frequency (CLKP2) fCLKP2 0 28 0 32 MHz External Reset Timing (TA = -40 °C to 125 °C, VCC = AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Reset input time tRSTL Pin RSTX Value Min 500 Typ - Max - Unit Remarks ns tRSTL RSTX 0.2 VCC Document Number: 002-04588 Rev. *C 0.2 VCC Page 56 of 98 CY96F353/F355 CY96F356 Power On Reset Timing (TA = -40 °C to 125 °C, VCC = AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Value Pin Min Typ Max Unit Power on rise time tR Vcc 0.05 - 30 ms Power off time tOFF Vcc 1 - - ms Remarks tR 2.7V VCC 0.2 V 0.2 V 0.2 V tOFF If the power supply is changed too rapidly, a power-on reset may occur. We recommend a smooth startup by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. VCC 3V Document Number: 002-04588 Rev. *C Rising edge of 50 mV/ms maximum is allowed Page 57 of 98 CY96F353/F355 CY96F356 External Input Timing (TA = -40 °C to 125 °C, VCC = AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Parameter Input pulse width Symbol tINH tINL Pin Value Condition INTn(_R) - Min Unit Max 200 - ns 2*tCLKP1 + 200 (tCLKP1=1/fCLKP 1) ns NMI(_R) Used Pin Input Function External Interrupt NMI Pnn_m TINn(_R) TTGn(_R) General Purpose IO Reload Timer PPG Trigger input ADTG(_R) AD Converter Trigger FRCKn(_R) Free Running Timer external clock INn(_R) Input Capture Note : Relocated Resource Inputs have same characteristics External Pin input VIH VIH tINH Document Number: 002-04588 Rev. *C VIL VIL tINL Page 58 of 98 CY96F353/F355 CY96F356 External Bus Timing Note: The values given below are for an I/O driving strength IOdrive = 5 mA. If IOdrive is 2 mA, all the maximum output timing described in the different tables must then be increased by 10 ns. Basic Timing (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10 %, VSS = 0.0 V, IOdrive = 5 mA, CL = 50 pF) Parameter ECLK Symbol ECLK → ALE time ECLK → address valid time ECLK - Min Max - tCHCL tCYC/2-5 tCYC/2+5 tCLCH tCYC/2-5 tCYC/2+5 -20 +20 -20 +20 tCLCBH -20 +20 tCLCBL -20 +20 tCHCBH tCHCBL CSn, UBX, LBX, ECLK -10 +10 tCHLL -10 +10 tCLLH -10 +10 tCLLL -10 +10 -15 +15 -15 +15 -15 +15 -15 +15 tCHLH tCHAV ALE, ECLK - - A[23:16], ECLK tCLAV tCLADV AD[15:0], ECLK tCHADV ECLK → RDX /WRX time Value Condition 25 tCYC ECLK → UBX/ LBX / CSn time Pin tCHRWH tCHRWL tCLRWH RDX, WRX, WRLX,WRHX, ECLK - tCLRWL -10 +10 -10 +10 -10 +10 -10 +10 Unit Remarks ns ns ns ns ns ns (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5 mA, CL = 50 pF) Parameter ECLK Symbol tCYC Pin ECLK - tCHCL tCLCH ECLK → UBX/ LBX / CSn time tCHCBH tCHCBL CSn, UBX, LBX, ECLK - tCLCBH Min Max 30 - tCYC/2-8 tCYC/2+8 tCYC/2-8 tCYC/2+8 -25 +25 -25 +25 -25 +25 -25 +25 -15 +15 tCHLL -15 +15 tCLLH -15 +15 tCLLL -15 +15 tCLCBL ECLK → ALE time Value Condition tCHLH Document Number: 002-04588 Rev. *C ALE, ECLK - Unit Remarks ns ns ns Page 59 of 98 CY96F353/F355 CY96F356 (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5 mA, CL = 50 pF) Parameter Symbol ECLK → address valid time tCHAV Pin A[23:16], ECLK tCLAV AD[15:0], ECLK tCLADV tCHADV ECLK → RDX /WRX time tCHRWH tCHRWL tCLRWH RDX, WRX, WRLX,WRHX, ECLK Value Condition - tCLRWL Min Max -20 +20 -20 +20 -20 +20 -20 +20 -15 +15 -15 +15 -15 +15 -15 +15 Unit Remarks ns ns ns tCYC tCHCL tCLCH 0.8*Vcc ECLK 0.2*Vcc tCLAV tCHAV A[23:0] tCHCBL tCLCBH tCLCBL tCHCBH tCHRWL tCLRWH tCLRWL tCHRWH CSn LBX UBX RDX WRX (WRLX, WRHX) tCLLH tCHLL tCHLH tCLLL ALE tCHADV tCLADV AD[15:0] Address Refer to the Hardware Manual for detailed Timing Charts Document Number: 002-04588 Rev. *C Page 60 of 98 CY96F353/F355 CY96F356 Bus Timing (Read) (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10 %, VSS = 0.0 V, IOdrive = 5 mA, CL = 50 pF) Parameter ALE pulse width Valid address  ALE ↓ time Symbol tLHLL tAVLL tADVLL ALE ↓  Address valid time tLLAX Valid address  RDX ↓ time tAVRL tADVRL Valid address  Valid data input tAVDV tADVDV Pin ALE ALE, A[23:16], ALE,AD[15:0] ALE, AD[15:0] RDX, A[23:16] Value Conditions Min Max EACL:STS=0 and EACL:ACE=0 tCYC/2-5 - EACL:STS=1 tCYC-5 - EACL:STS=0 and EACL:ACE=1 3tCYC/2-5 - EACL:STS=0 and EACL:ACE=0 tCYC-15 - EACL:STS=1 and EACL:ACE=0 3tCYC/2-15 - EACL:STS=0 and EACL:ACE=1 2tCYC-15 - EACL:STS=1 and EACL:ACE=1 5tCYC/2-15 - EACL:STS=0 and EACL:ACE=0 tCYC/2-15 - EACL:STS=1 and EACL:ACE=0 tCYC -15 - EACL:STS=0 and EACL:ACE=1 3tCYC/2-15 - EACL:STS=1 and EACL:ACE=1 2tCYC-15 - EACL:STS=0 tCYC/2-15 - EACL:STS=1 -15 - EACL:ACE=0 3tCYC/2-15 - EACL:ACE=1 5tCYC/2-15 - EACL:ACE=0 tCYC-15 - EACL:ACE=1 2tCYC -15 - A[23:16], AD[15:0] EACL:ACE=0 - 3tCYC-55 EACL:ACE=1 - 4tCYC-55 AD[15:0] EACL:ACE=0 - 5tCYC/2-55 EACL:ACE=1 - 7tCYC/2-55 RDX, AD[15:0] Unit Remarks ns ns ns ns ns ns ns w/o cycle extension ns w/o cycle extension RDX pulse width tRLRH RDX - 3 tCYC/2-5 - ns w/o cycle extension RDX ↓  Valid data input tRLDV RDX, AD[15:0] - - 3 tCYC/2-50 ns w/o cycle extension RDX ↑  Data hold time tRHDX RDX, AD[15:0] - 0 - ns Address valid  Data hold time tAXDX A[23:16], AD[15:0] - 0 - ns RDX ↑  ALE ↑ time tRHLH RDX, ALE 3tCYC/2-10 - ns EACL:STS=1 and EACL:ACE=1 other ECL:STS, tCYC/2-10 EACL:ACE setting Document Number: 002-04588 Rev. *C - Page 61 of 98 CY96F353/F355 CY96F356 (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10 %, VSS = 0.0 V, IOdrive = 5 mA, CL = 50 pF) Parameter Valid address  ECLK ↑ time Symbol Pin tAVCH A[23:16], ECLK tADVCH AD[15:0], ECLK RDX ↓  ECLK ↑ time tRLCH RDX, ECLK ALE ↓  RDX ↓ time tLLRL ALE, RDX ECLK↑  Valid data input tCHDV AD[15:0], ECLK Value Conditions - Min Max Unit tCYC-15 - tCYC/2-15 - - tCYC/2-10 - ns EACL:STS=0 tCYC/2-10 - ns EACL:STS=1 -10 - - - tCYC − 50 Remarks ns ns (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5 V, VSS = 0.0 V, IOdrive = 5 mA, CL = 50 pF) Parameter ALE pulse width Valid address  ALE ↓ time Symbol tLHLL tAVLL Pin ALE ALE, A[23:16], tADVLL ALE, AD[15:0] Value Conditions Min Max EACL:STS=0 and EACL:ACE=0 tCYC/2-8 - EACL:STS=1 tCYC-8 - EACL:STS=0 and EACL:ACE=1 3tCYC/2-8 - EACL:STS=0 and EACL:ACE=0 tCYC-20 - EACL:STS=1 and EACL:ACE=0 3tCYC/2-20 - EACL:STS=0 and EACL:ACE=1 2tCYC-20 - EACL:STS=1 and EACL:ACE=1 5tCYC/2-20 - EACL:STS=0 and EACL:ACE=0 tCYC/2-20 - EACL:STS=1 and EACL:ACE=0 tCYC-20 - EACL:STS=0 and EACL:ACE=1 3tCYC/2-20 - EACL:STS=1 and EACL:ACE=1 2tCYC-20 - EACL:STS=0 tCYC/2-20 - EACL:STS=1 -20 - ALE ↓  Address valid time tLLAX Valid address  RDX ↓ time tAVRL RDX, A[23:16] EACL:ACE=0 3tCYC/2-20 - EACL:ACE=1 5tCYC/2-20 - tADVRL RDX, AD[15:0] EACL:ACE=0 tCYC-20 - EACL:ACE=1 2tCYC-20 - A[23:16], AD[15:0] EACL:ACE=0 - 3tCYC-60 EACL:ACE=1 - 4tCYC-60 tADVDV AD[15:0] EACL:ACE=0 - 5tCYC/2-60 EACL:ACE=1 - 7tCYC/2-60 Valid address  Valid data input tAVDV Document Number: 002-04588 Rev. *C ALE, AD[15:0] Unit ns Remarks EBM:NMS =0 ns ns ns ns ns ns w/o cycle extension ns w/o cycle extension Page 62 of 98 CY96F353/F355 CY96F356 (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5 V, VSS = 0.0 V, IOdrive = 5 mA, CL = 50 pF) Parameter Symbol Pin Value Conditions Min Max Unit Remarks RDX pulse width tRLRH RDX - 3tCYC/2-8 - ns w/o cycle extension RDX ↓  Valid data input tRLDV RDX, AD[15:0] - - 3tCYC/2-55 ns w/o cycle extension RDX ↑  Data hold time tRHDX RDX, AD[15:0] - 0 - ns A[23:0] - 0 - ns RDX, ALE EACL:STS=1 and EACL:ACE=1 3tCYC/2-15 - ns other ECL:STS, EACL:ACE setting tCYC/2-15 - - tCYC-20 - tCYC/2-20 - Address valid  Data hold time tAXDX RDX ↑  ALE ↑ time tRHLH Valid address  ECLK ↑ time tAVCH RDX ↓  ECLK ↑ time tRLCH RDX, ECLK - tCYC/2-15 - ns ALE ↓  RDX ↓ time tLLRL ALE, RDX EACL:STS=0 tCYC/2-15 - ns EACL:STS=1 -15 - ECLK↑  Valid data input tCHDV AD[15:0], ECLK - - tCYC-55 A[23:0], ECLK tADVCH AD[15:0], ECLK Document Number: 002-04588 Rev. *C ns ns Page 63 of 98 CY96F353/F355 CY96F356 . tAVCH tRLCH tADVCH ECLK tCHDV 0.8*Vcc tAVLL tLLAX tADVLL ALE tRHLH 0.2*VC tLHLL tAVRL tADVRL tRLRH RDX tLLRL A[23:0] tRLDV tAVDV tAXD tRHDX tADVDV AD[15:0] Address VIH VIL Read data VIH VIL Refer to the Hardware Manual for detailed Timing Charts Document Number: 002-04588 Rev. *C Page 64 of 98 CY96F353/F355 CY96F356 Bus Timing (Write) (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10 %, VSS = 0.0 V, IOdrive = 5 mA, CL = 50 pF) Parameter Valid address  WRX ↓ time Symbol tAVWL tADVWL Pin WRX, WRLX, WRHX, A[23:16] WRX, WRLX, WRHX, AD[15:0] Value Condition Min Max EACL:ACE=0 3tCYC/2-15 - EACL:ACE=1 5tCYC/2-15 - EACL:ACE=0 tCYC-15 - EACL:ACE=1 2tCYC-15 - Unit Remarks ns ns WRX pulse width tWLWH WRX, WRXL, WRHX - tCYC-5 - ns w/o cycle extension Valid data output  WRX ↑ time tDVWH WRX, WRLX, WRHX, AD[15:0] - tCYC-20 - ns w/o cycle extension WRX ↑  Data hold time tWHDX WRX, WRLX, WRHX, AD[15:0] - tCYC/2-15 - ns WRX ↑  Address valid time tWHAX WRX, WRLX, WRHX, A[23:16] EBM:NMS=0 tCYC/2-15 - ns WRX ↑  ALE ↑ time tWHLH WRX, WRLX, WRHX, ALE EBM:ACE=1 and EACL:STS=1 2tCYC-10 - ns other EBM:ACE and EACL:STS setting tCYC-10 - WRX ↓  ECLK ↑ time tWLCH WRX, WRLX, WRHX, ECLK - tCYC/2-10 - ns CSn  WRX time tCSLWL WRX, WRLX, WRHX, CSn EACL:ACE=0 EBM:NMS=0 - 3tCYC/2-15 ns EACL:ACE=1 EBM:NMS=0 - 5tCYC/2-15 EBM:NMS=0 tCYC/2-15 - WRX  CSn time tWHCSH WRX, WRLX, WRHX, CSn ns (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5 V, VSS = 0.0 V, IOdrive = 5 mA, CL = 50 pF) Parameter Valid address  WRX ↓ time Symbol tAVWL tADVWL Pin WRX, WRLX, WRHX, A[23:16] WRX, WRLX, WRHX, AD[15:0] Document Number: 002-04588 Rev. *C Condition Value Min Max EACL:ACE=0 3tCYC/2-20 - EACL:ACE=1 5tCYC/2-20 - EACL:ACE=0 tCYC-20 - EACL:ACE=1 2tCYC-20 - Unit Remarks ns ns Page 65 of 98 CY96F353/F355 CY96F356 (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5 V, VSS = 0.0 V, IOdrive = 5 mA, CL = 50 pF) Parameter Symbol Pin Value Condition Min Max Unit Remarks WRX pulse width tWLWH WRX, WRXL, WRHX - tCYC-8 - ns w/o cycle extension Valid data output  WRX ↑ time tDVWH WRX, WRLX, WRHX, AD[15:0] - tCYC-25 - ns w/o cycle extension WRX ↑  Data hold time tWHDX WRX, WRLX, WRHX, AD[15:0] - tCYC/2-20 - ns WRX ↑  Address valid time tWHAX WRX, WRLX, WRHX, A[23:16] - tCYC/2-20 - ns WRX ↑  ALE ↑ time tWHLH WRX, WRLX, WRHX, ALE EBM:ACE=1 and EACL:STS=1 2tCYC-15 - ns other EBM:ACE and EACL:STS setting tCYC-15 - WRX ↓  ECLK ↑ time tWLCH WRX, WRLX, WRHX, ECLK - tCYC/2-15 - ns CSn  WRX time tCSLWL WRX, WRLX, WRHX, CSn EACL:ACE=0 - 3tCYC/2-20 ns EACL:ACE=1 - 5tCYC/2-20 - tCYC/2-20 - WRX  CSn time tWHCSH WRX, WRLX, WRHX, CSn Document Number: 002-04588 Rev. *C ns Page 66 of 98 CY96F353/F355 CY96F356 tWLCH 0.8*VCC ECLK tWHLH ALE tAVWL tADVWL WRX (WRLX, WRHX) tWLWH 0.2*VCC tCSLWL tWHCSH CSn tWHAX A[23:0] tDVWH AD[15:0] Address tWHDX Write data Refer to the Hardware Manual for detailed Timing Charts Document Number: 002-04588 Rev. *C Page 67 of 98 CY96F353/F355 CY96F356 Ready Input Timing (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10 %, VSS = 0.0 V, IOdrive = 5 mA, CL = 50 pF) Parameter Symbol RDY setup time tRYHS RDY RDY hold time tRYHH RDY Rated Value Test Condition Pin - Min Max Units 35 - ns 0 - ns Remarks (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5 V, VSS = 0.0 V, IOdrive = 5 mA, CL = 50 pF) Parameter Symbol RDY setup time tRYHS RDY RDY hold time tRYHH RDY Rated Value Test Condition Pin - Min Max Units 45 - ns 0 - ns Remarks Note : If the RDY setup time is insufficient, use the auto-ready function. ECLK 0.8*VCC tRYHS RDY When WAIT is not used. RDY When WAIT is used. VIH tRYHH VIH VIL Refer to the Hardware Manual for detailed Timing Charts Document Number: 002-04588 Rev. *C Page 68 of 98 CY96F353/F355 CY96F356 Hold Timing (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10 %, VSS = 0.0 V, IOdrive = 5 mA, CL = 50 pF) Parameter Symbol Pin Pin floating  HAKX ↓ time tXHAL HAKX HAKX ↑ time  Pin valid time tHAHV HAKX Value Condition Min - Units Max tCYC-20 tCYC + 20 ns tCYC-20 tCYC + 20 ns Remarks (TA = −40 °C to +125 °C, VCC = 3.0 to 4.5 V, VSS = 0.0 V, IOdrive = 5 mA, CL = 50 pF) Parameter Symbol Pin Pin floating  HAKX ↓ time tXHAL HAKX HAKX ↑ time  Pin valid time tHAHV HAKX Value Condition Min - tCYC-25 tCYC + 25 ns tCYC-25 tCYC + 25 ns Remarks 0.8*VCC HAKX 0.2*VCC tHAHV tXHAL Each pin Units Max 0.8*VCC High-Z 0.2*VCC Refer to the Hardware Manual for detailed Timing Charts Document Number: 002-04588 Rev. *C Page 69 of 98 CY96F353/F355 CY96F356 USART Timing Note: The values given below are for an I/O driving strength IOdrive = 5 mA. If IOdrive is 2 mA, all the maximum output timing described in the different tables must then be increased by 10 ns. (TA = -40 °C to 125 °C, VCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, IOdrive = 5 mA, CL = 50 pF) Parameter Symbol Pin Condition VCC = AVCC= 4.5 V VCC = AVCC= 3.0 V to to 5.5 V 4.5 V Min Internal Shift Clock Mode Max Min Unit Max Serial clock cycle time tSCYCI SCKn SCK ↓ → SOT delay time tSLOVI SCKn, SOTn SOT → SCK ↑ delay time tOVSHI SCKn, SOTn N*tCLKP1 - 20 *1 N*tCLKP1 - 30 *1 ns Valid SIN → SCK ↑ tIVSHI SCKn, SINn tCLKP1 + 45 - tCLKP1 + 55 - ns SCK ↑ → Valid SIN hold time tSHIXI SCKn, SINn 0 - 0 - ns Serial clock “L” pulse width tSLSHE SCKn tCLKP1 + 10 - tCLKP1 + 10 - ns Serial clock “H” pulse width tSHSLE SCKn tCLKP1 + 10 - tCLKP1 + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKn, SOTn - 2 tCLKP1 + 45 - ns Valid SIN → SCK ↑ tIVSHE SCKn, SINn tCLKP1/2 + 10 tCLKP1/2 + 10 ns SCK ↑ → Valid SIN hold time tSHIXE SCKn, SINn tCLKP1 + 10 - tCLKP1 + 10 - ns SCK fall time tFE SCKn - 20 - 20 ns SCK rise time tRE SCKn - 20 - 20 ns External Shift Clock Mode 4 tCLKP1 - 4 tCLKP1 - ns -20 +20 -30 +30 ns 2 tCLKP1 + 55 Notes: ■ AC characteristic in CLK synchronized mode. ■ CL is the load capacity value of pins when testing. ■ Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. These parameters are shown in “CY96300 Super series Hardware Manual” ■ tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns *1: Parameter N depends on tSCYCI and can be calculated as follows: ■ if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2 ■ if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1 Examples: tSCYCI Document Number: 002-04588 Rev. *C N 4*tCLKP1 2 5*tCLKP1, 6*tCLKP1 3 7*tCLKP1, 8*tCLKP1 4 ... ... Page 70 of 98 CY96F353/F355 CY96F356 tSCYCI SCK for ESCR:SCES = 0 0.8*VCC 0.2*VCC 0.2*VCC SCK for ESCR:SCES = 1 0.8*VCC 0.8*VCC 0.2*VCC tSLOVI tOVSHI 0.8*VCC SOT 0.2*VCC tIVSHI SIN tSHIXI VIH VIH VIL VIL Internal Shift Clock Mode tSLSHE SCK for ESCR:SCES = 0 VIH SCK for ESCR:SCES = 1 VIL VIL VIH VIH VIL tFE SOT tSHSLE tSLOVE VIH VIL VIL tRE 0.8*VCC 0.2*VCC tIVSHE SIN VIH tSHIXE VIH VIH VIL VIL External Shift Clock Mode Document Number: 002-04588 Rev. *C Page 71 of 98 CY96F353/F355 CY96F356 I2C Timing (TA = -40 °C to 125 °C, VCC = AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Parameter Fast-mode *1 Standard-mode Symbol Min Max Min Max Unit SCL clock frequency fSCL 0 100 0 400 kHz Hold time (repeated) START condition SDA↓→SCL↓ tHDSTA 4.0 - 0.6 - μs “L” width of the SCL clock tLOW 4.7 - 1.3 - μs “H” width of the SCL clock tHIGH 4.0 - 0.6 - μs Set-up time for a repeated START condition SCL↑→SDA↓ tSUSTA 4.7 - 0.6 - μs Data hold time SCL↓→SDA↓↑ tHDDAT 0 3.45 0 0.9 μs Data set-up time SDA↓↑→SCL↑ tSUDAT 250 - 100 - ns Set-up time for STOP condition SCL↑→SDA↑ tSUSTO 4.0 - 0.6 - μs Bus free time between a STOP and START condition tBUS 4.7 - 1.3 - μs Output fall time from 0.7*Vcc to 0.3*Vcc with a bus capacitance from 10 pF to 400 pF tof 20 + 0.1*Cb *2 300 20 + 0.1*Cb*2 300 ns Capacitive load for each bus line Cb - 400 - 400 pF Pulse width of spikes which will be suppressed by input noise filter tSP N/A N/A 0 1*tCLKP1* ns 3 *1: For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz. *2: Cb = capacitance of one bus line in pF. *3: tCLKP1 is the cycle time of the peripheral clock CLKP1. • VOH = 0.7 * VCC • VOL = 0.3 * VCC • CMOS Hysteresis 0.7/0.3 input selected Document Number: 002-04588 Rev. *C Page 72 of 98 CY96F353/F355 CY96F356 Analog Digital Converter (TA = -40 °C to +125 °C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Value Pin Min Typ Max Unit Remarks Resolution - - - - 10 bit Total error - - - - +3 LSB Nonlinearity error - - - - +2.5 LSB Differential nonlinearity error - - - - +1.9 LSB Zero reading voltage VOT ANn AVRL1.5 LSB AVRL+ 0.5 LSB AVRL+ 2.5 LSB V Full scale reading voltage VFST ANn AVRH3.5 LSB AVRH1.5 LSB AVRH+ 0.5 LSB V Compare time - - 1.0 - 16,500 μs 4.5 V ≤ AVCC ≤ 5.5 V 2.0 - - μs 3.0 V ≤ AVCC < 4.5 V Sampling time - - 0.5 - - μs 4.5 V ≤ AVCC ≤ 5.5 V 1.2 - - μs 3.0 V ≤ AVCC < 4.5 V -1 - +1 μA TA ≤ 105 °C, AVSS, AVRL < VI < AVCC, AVRH -1.2 - +1.2 μA 105 °C < TA ≤ 125 °C, Analog input leakage current IAIN (during conversion) ANn AVSS, AVRL < VI < AVCC, AVRH Analog input voltage range VAIN ANn AVRL Reference voltage range AVRH AVRH 0.75 AVcc - AVRL AVRL AVSS - 0.25 AVCC V Power supply current IA AVcc - 2.5 5 mA A/D Converter active IAH AVcc - - 5 μA A/D Converter not operated IR AVRH/AVRL - 0.7 1 mA A/D Converter active IRH AVRH/AVRL - - 5 μA A/D Converter not operated - ANn - - 4 LSB Reference voltage current Offset between input channels - AVRH V AVcc V Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller. Document Number: 002-04588 Rev. *C Page 73 of 98 CY96F353/F355 CY96F356 Definition of A/D Converter Terms Resolution: Analog variation that is recognized by an A/D converter. Total error: Difference between the actual value and the ideal value. The total error includes zero transition error, full-scale transition error and nonlinearity error. Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” “00 0000 0001”) and full-scale transition line (“11 1111 1110” “11 1111 1111”) and actual conversion characteristics. Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. Zero reading voltage: Input voltage which results in the minimum conversion value. Full scale reading voltage: Input voltage which results in the maximum conversion value. Total error 3FF 3FE Actual conversion characteristics 1.5 LSB Digital output 3FD {1 LSB × (N − 1) + 0.5 LSB} 004 VNT (Actually-measured value) 003 Actual conversion characteristics Ideal characteristics 002 001 0.5 LSB AVRL AVRH Analog input VNT − {1 LSB × (N − 1) + 0.5 LSB} [LSB] 1 LSB AVRH − AVRL 1 LSB = (Ideal value) [V] 1024 Total error of digital output “N” = N: A/D converter digital output value VOT (Ideal value) = AVRL + 0.5 LSB [V] VFST (Ideal value) = AVRH − 1.5 LSB [V] VNT : A voltage at which digital output transitions from (N − 1) to N. Document Number: 002-04588 Rev. *C Page 74 of 98 CY96F353/F355 CY96F356 Nonlinearity error Differential nonlinearity error Ideal characteristics 3FF Actual conversion characteristics {1 LSB × (N − 1) + VOT } Digital output 3FD N+1 VFST (actual measurement value) VNT (actual measurement value) 004 Actual conversion characteristics 003 Digital output 3FE Actual conversion characteristics N V (N + 1) T (actual measurement value) VNT (actual measurement value) N−1 002 Ideal characteristics Actual conversion characteristics N−2 001 VOT (actual measurement value) AVRL AVRH AVRL Analog input AVRH Analog input Nonlinearity error of digital output N = Differential nonlinearity error of digital output N = 1 LSB = VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N+1) T − VNT 1 LSB VFST − VOT 1022 [LSB] − 1LSB [LSB] [V] N: A/D converter digital output value VOT: Voltage at which digital output transits from “000H” to “001H.” VFST: Voltage at which digital output transits from “3FEH” to “3FFH.” Document Number: 002-04588 Rev. *C Page 75 of 98 CY96F353/F355 CY96F356 Accuracy and setting of the A/D Converter sampling time If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting the A/D conversion precision. To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time depends on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and the AVcc voltage level. The following replacement model can be used for the calculation: Document Number: 002-04588 Rev. *C Page 76 of 98 CY96F353/F355 CY96F356 The sampling time should be set to minimum “7τ“. The following approximation formula for the replacement model above can be used: Tsamp [min] = 7 × (Rext × (Cext + CIN) + (Rext + RADC) × CADC) ■ Do not select a sampling time below the absolute minimum permitted value (0.5μs for 4.5V ≤ AVcc ≤ 5.5V; 1.2 μs for 3.0V ≤ AVcc < 4.5V). ■ If the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin. In this case the internal sampling capacitance CADC will be charged out of this external capacitance. ■ A big external driving impedance also adversely affects the A/D conversion precision due to the pin input leakage current IIL (static current before the sampling switch) or the analog input leakage current IAIN (total leakage current of pin input and comparator during sampling). The effect of the pin input leakage current IIL cannot be compensated by an external capacitor. ■ The accuracy gets worse as |AVRH - AVRL| becomes smaller. Low Voltage Detector Characteristics (TA = -40 °C to +125 °C, Vcc = AVcc = 3.0 V - 5.5 V, Vss = AVss = 0 V) Parameter Value *1 Symbol Min Value *2 Max Min Unit Max Remarks Stabilization time TLVDSTAB - 75 - 110 μs After power-up or change of detection level Level 0 VDL0 2.7 2.9 2.5 2.9 V CILCR:LVL[3:0]=”0000” Level 1 VDL1 2.9 3.1 2.8 3.2 V CILCR:LVL[3:0]=”0001” Level 2 VDL2 3.1 3.3 3 3.4 V CILCR:LVL[3:0]=”0010” Level 3 VDL3 3.5 3.75 3.35 3.8 V CILCR:LVL[3:0]=”0011” Level 4 VDL4 3.6 3.85 3.5 3.95 V CILCR:LVL[3:0]=”0100” Level 5 VDL5 3.7 3.95 3.6 4.1 V CILCR:LVL[3:0]=”0101” Level 6 VDL6 3.8 4.05 3.7 4.2 V CILCR:LVL[3:0]=”0110” Level 7 VDL7 3.9 4.15 3.8 4.3 V CILCR:LVL[3:0]=”0111” Level 8 VDL8 4.0 4.25 3.9 4.4 V CILCR:LVL[3:0]=”1000” Level 9 VDL9 4.1 4.35 3.95 4.5 V CILCR:LVL[3:0]=”1001” Level 10 VDL10 not used not used - Level 11 VDL11 not used not used - Level 12 VDL12 not used Level 13 VDL13 not used not used - Level 14 VDL14 not used not used - Level 15 VDL15 not used not used - 2.6 3 V CILCR:LVL[3:0]=”1100” *1: Valid for all devices except devices listed under “*2” *2: Valid for: CY96F353/F355 CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register. dV V For correct detection, the slope of the voltage level must satisfy dt ≤ 0.004 μs . Faster variations are regarded as noise and may not be detected. The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of Vcc = 2.7 V. The electrical characteristics however are only valid in the specified range (usually down to 3.0 V). Please use the inclination of the power-supply voltage with 0.1V/μs or less. Document Number: 002-04588 Rev. *C Page 77 of 98 CY96F353/F355 CY96F356 Low Voltage Detector Operation In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the reset and startup behavior, please refer to the corresponding hardware manual chapter. Voltage [V] VCC VDLx, Max VDLx, Min dV dt Time [s] Power Reset Extension Time Low Voltage Reset Assertion Normal Operation Flash Memory Program/Erase Characteristics (TA = -40 °C to 105 °C, VCC = AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V) Value Parameter Min Typ Unit Max Remarks Sector erase time - 0.9 3.6 s Without erasure pre-programming time Chip erase time - n*0.9 n*3.6 s Without erasure pre-programming time (n is the number of Flash sector of the device) Word (16-bit width) programming time - 23 370 us Without overhead time for submitting write command Program/Erase cycle 10 000 - - cycle Flash data retention time 20 - - year *1 *1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85 oC) Document Number: 002-04588 Rev. *C Page 78 of 98 CY96F353/F355 CY96F356 Example Characteristics Temperature dependency of power supply currents The following diagrams show the current consumption of samples with typical wafer process parameters in different operation modes. Common condition for all operation modes: ■ VCC = AVCC = 5.0 V ■ Main clock = 4 MHz external clock ■ Sub clock = 32 kHz external clock Operation Mode Details Mode name PLL Run 56 PLL Run 48 Details PLL Run mode current ICCPLL with the following settings: ■ fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = 56MHz ■ fCLKP2 = 28MHz ■ Regulator in High Power Mode ■ Core voltage at 1.9V (VRCR:HPM[1:0] = 11B) ■ 2 Flash/ROM wait states (MTCRA=233AH) ■ RC oscillator and Sub oscillator stopped PLL Run mode current ICCPLL with the following settings: ■ fCLKS1 ■ fCLKB = fCLKP1 = 48MHz ■ fCLKP2 PLL Run 24 = 24MHz ■ Regulator in High Power Mode ■ Core voltage at 1.9V (VRCR:HPM[1:0] = 11B) ■ 1 Flash/ROM wait states (MTCRA=6B09H) ■ RC oscillator and Sub oscillator stopped PLL Run mode current ICCPLL with the following settings: ■ fCLKS1 ■ fCLKB Main Run = fCLKS2 = 96MHz = fCLKS2 = 48MHz = fCLKP1 = fCLKP2 = 24MHz ■ Regulator in High Power Mode ■ Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) ■ 0 Flash/ROM wait states (MTCRA=2208H) ■ RC oscillator and Sub oscillator stopped Main Run mode current ICCMAIN with the following settings: ■ fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 4MHz ■ Regulator in High Power Mode ■ Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) ■ 1 Flash/ROM wait states (MTCRA=0239H) ■ PLL, RC oscillator and Sub oscillator stopped Document Number: 002-04588 Rev. *C Page 79 of 98 CY96F353/F355 CY96F356 Operation Mode Details Mode name RC Run 2M Details RC Run mode current ICCRCH with the following settings: ■ RC oscillator set to 2MHz (CKFCR:RCFS = 1) ■ fCLKS1 RC Run 100k ■ Regulator in High Power Mode ■ Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) ■ 1 Flash/ROM wait states (MTCRA=0239H) ■ PLL, Main oscillator and Sub oscillator stopped RC Run mode current ICCRCL with the following settings: ■ RC oscillator set to 100kHz (CKFCR:RCFS = 0) ■ fCLKS1 Sub Run PLL Sleep 48 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 100kHz ■ Regulator in Low Power Mode A (SMCR:LPMS = 1) ■ Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) ■ 1 Flash/ROM wait states (MTCRA=0239H) ■ PLL, Main oscillator and Sub oscillator stopped Sub Run mode current ICCSUB with the following settings: ■ fCLKS1 PLL Sleep 56 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 2MHz = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 32kHz ■ Regulator in Low Power Mode A (by hardware) ■ Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) ■ 1 Flash/ROM wait states (MTCRA=0239H) ■ PLL, RC oscillator and Main oscillator stopped PLL Sleep mode current ICCSPLL with the following settings: ■ fCLKS1 = fCLKS2 = fCLKP1 = 56MHz ■ fCLKP2 = 28MHz ■ Regulator in High Power Mode ■ Core voltage at 1.9V (VRCR:HPM[1:0] = 11B) ■ RC oscillator and Sub oscillator stopped PLL Sleep mode current ICCSPLL with the following settings: ■ fCLKS1 = fCLKS2 = 96MHz ■ fCLKP1 = 48MHz ■ fCLKP2 = 24MHz ■ Regulator in High Power Mode ■ Core voltage at 1.9V (VRCR:HPM[1:0] = 11B) ■ RC oscillator and Sub oscillator stopped Document Number: 002-04588 Rev. *C Page 80 of 98 CY96F353/F355 CY96F356 Operation Mode Details Mode name PLL Sleep 24 Main Sleep Details PLL Sleep mode current ICCSPLL with the following settings: ■ fCLKS1 = fCLKS2 = 48MHz ■ fCLKP1 = fCLKP2 = 24MHz ■ Regulator in High Power Mode ■ Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) ■ RC oscillator and Sub oscillator stopped Main Sleep mode current ICCSMAIN with the following settings: ■ fCLKS1 RC Sleep 2M ■ Regulator in High Power Mode ■ Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) ■ PLL, RC oscillator and Sub oscillator stopped RC Sleep mode current ICCSRCH with the following settings: ■ RC oscillator set to 2MHz (CKFCR:RCFS = 1) ■ fCLKS1 RC Sleep 100k Regulator in High Power Mode ■ Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) ■ PLL, Main oscillator and Sub oscillator stopped RC Sleep mode current ICCSRCL with the following settings: RC oscillator set to 100kHz (CKFCR:RCFS = 0) ■ fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 100kHz ■ Regulator in Low Power Mode A (SMCR:LPMSS = 1) ■ Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) ■ PLL, Main oscillator and Sub oscillator stopped Sub Sleep mode current ICCSSUB with the following settings: ■ fCLKS1 PLL Timer 48 = fCLKS2 = fCLKP1 = fCLKP2 = 2MHz ■ ■ Sub Sleep = fCLKS2 = fCLKP1 = fCLKP2 = 4MHz = fCLKS2 = fCLKP1 = fCLKP2 = 32kHz ■ Regulator in Low Power Mode A (by hardware) ■ Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) ■ PLL, RC oscillator and Main oscillator stopped PLL Timer mode current ICCTPLL with the following settings: ■ fCLKS1 = fCLKS2 = 48MHz ■ Regulator in High Power Mode ■ Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) ■ RC oscillator and Sub oscillator stopped Document Number: 002-04588 Rev. *C Page 81 of 98 CY96F353/F355 CY96F356 Operation Mode Details Mode name Main Timer Details Main Timer mode current ICCTMAIN with the following settings: ■ fCLKS1 RC Timer 2M ■ Regulator in Low Power Mode A (SMCR:LPMSS = 1) ■ Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) ■ PLL, RC oscillator and Sub oscillator stopped RC Timer mode current ICCTRCH with the following settings: ■ RC oscillator set to 2MHz (CKFCR:RCFS = 1) ■ fCLKS1 RC Timer 100k Regulator in Low Power Mode A (SMCR:LPMSS = 1) ■ Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) ■ PLL, Main oscillator and Sub oscillator stopped RC Timer mode current ICCTRCL with the following settings: RC oscillator set to 100kHz (CKFCR:RCFS = 0) ■ fCLKS1 Stop 1.2V = fCLKS2 = 100kHz ■ Regulator in Low Power Mode A (SMCR:LPMSS = 1) ■ Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) ■ PLL, Main oscillator and Sub oscillator stopped Sub Timer mode current ICCTSUB with the following settings: ■ fCLKS1 Stop 1.8V = fCLKS2 = 2MHz ■ ■ Sub Timer = fCLKS2 = 4MHz = fCLKS2 = 32kHz ■ Regulator in Low Power Mode A (by hardware) ■ Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) ■ PLL, RC oscillator and Main oscillator stopped Stop mode current ICCH with the following settings: ■ Regulator in Low Power Mode B (by hardware) ■ Core voltage at 1.8V (VRCR:LPMB[2:0] = 110B) Stop mode current ICCH with the following settings: ■ Regulator in Low Power Mode B (by hardware) ■ Core voltage at 1.2V (VRCR:LPMB[2:0] = 000B) Document Number: 002-04588 Rev. *C Page 82 of 98 CY96F353/F355 CY96F356 Figure 3. CY96F353/F355 PLL Run and Sleep Mode Currents 50 PLL Run 48 40 PLL Run 56 Icc[mA] 30 PLL Run 24 20 PLL Sleep 48 PLL Sleep 56 10 PLL Sleep 24 0 -60 -40 -20 0 20 40 60 80 100 120 Ta [°C] Figure 4. CY96F353/F355 Operation Modes with Medium Currents 5 4 Main Run Icc[mA] 3 RC Run 2M 2 PLL Timer 48 1 Main Sleep RC Sleep 2M 0 -60 -40 -20 0 20 40 60 80 100 120 Ta [°C] Document Number: 002-04588 Rev. *C Page 83 of 98 CY96F353/F355 CY96F356 Figure 5. CY96F353/F355 Low Power Mode Currents 1 RC Run 100k 0.1 Icc[mA] Sub Run Main Timer RC Timer 2M RC Sleep 100k Sub Sleep Sub Timer RC Timer 100k 0.01 Stop 1.8V Stop 1.2V 0.001 -60 -40 -20 0 20 40 60 80 100 120 Ta [°C] Figure 6. CY96F356 PLL Run and Sleep Mode Currents 50 PLL Run 48 40 PLL Run 56 Icc[mA] 30 PLL Run 24 20 10 PLL Sleep 48 PLL Sleep 56 PLL Sleep 24 0 -60 -40 -20 0 20 40 60 80 100 120 Ta [°C] Document Number: 002-04588 Rev. *C Page 84 of 98 CY96F353/F355 CY96F356 Figure 7. CY96F356 Operation Modes with Medium Currents 5 4 Main Run Icc[mA] 3 RC Run 2M 2 PLL Timer 48 Main Sleep 1 RC Sleep 2M 0 -60 -40 -20 0 20 40 60 80 100 120 Ta [°C] Figure 8. CY96F356 Low Power Mode Currents 1 Icc[mA] 0.1 0.01 RC Run 100k Sub Run Main Timer RC Timer 2M Sub Sleep RC Sleep 100k Sub Timer RC Timer 100k Stop 1.8V Stop 1.2V 0.001 -60 -40 -20 0 20 40 60 80 100 120 Ta [°C] Document Number: 002-04588 Rev. *C Page 85 of 98 CY96F353/F355 CY96F356 Frequency dependency of power supply currents in PLL Run mode The following diagrams show the current consumption of samples with typical wafer process parameters in PLL Run mode at different frequencies and Flash timing settings. Measurement conditions: ■ VCC = AVCC = 5.0V ■ Ta = 25°C ■ fCLKS1 = fCLKB or fCLKS1 = 2*fCLKB as described in diagram ■ fCLKS2 = fCLKS1 ■ fCLKP1 = fCLKB ■ fCLKP2 = fCLKB/2 ■ Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) or 1.9V (VRCR:HPM[1:0] = 11B) as described in diagram ■ Main clock = 4MHz external clock ■ Flash memory timing settings: ❐ MTCRA=2128H/2208H (0 Flash wait states, fCLKS1 = 2*fCLKB) ❐ MTCRA=0239H/2129H (1 Flash wait state, fCLKS1 = fCLKB) ❐ MTCRA=4C09H/6B09H (1 Flash wait state, fCLKS1 = 2*fCLKB) ❐ MTCRA=233AH (2 Flash wait states, fCLKS1 = fCLKB) ■ Average Flash access rate (number of read accesses to the Flash per CLKB clock cycle, no buffer hit): ❐ 0 Flash wait states: 0.5 ❐ 1 Flash wait states: 0.33 ❐ 2 Flash wait states: 0.25 Figure 9. CY96F353/F355 PLL Run Mode Currents Document Number: 002-04588 Rev. *C Page 86 of 98 CY96F353/F355 CY96F356 Figure 10. CY96F356 PLL Run Mode Currents Document Number: 002-04588 Rev. *C Page 87 of 98 CY96F353/F355 CY96F356 Package Dimension CY96(F)35x LQFP 64 - LQG064 E1 E 3 % 64 0.50 0.70 ș 0° ' $ ( /  ( + 7  )  23 , 7 1  2' ,$ 7 &( (/ 6 ( + 7 $7 / )0 2 ( 5 +) 7 P 2 7P  <   / 3 3' $1 $ 6  1P 2P , 6  1 (  01 ,( ' ( ( 6: (7 +( % 7       0.30 5 $E1 % 2 0'  $(' '(( &7 ( ;$ +( & 7 2 2  / 7 1  2 +( ,7 % 6  '7 8, 2 5: 7 1 2' 1 5$$ (& 3/   5 5 (($ %+%7 0702  ( $6 $2 '8 ')    ' (  '$P$ & P( 8 / /7  &2 ( 11+  ,/ 1 7  7 /  $5 2$+ 2 1+7  6( 6 6 (58 , 262' ' 0$ 1 5 E