CY96F622ABPMC1-GS-UJERE2

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY96620 Series F2MC-16FX 16-Bit Microcontroller CY96620 series is based on Cypress advanced F2MC-16FX architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established F2MC-16LX family thus allowing for easy migration of F2MC-16LX Software to the new F2MC-16FX products. F2MC-16FX product improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. For high processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed. Features  Technology  DMA 0.18m CMOS Automatic transfer function independent of CPU, can be assigned freely to resources  CPU  F2MC-16FX CPU instruction set for controller applications (bit, byte, word and long-word data types, 23 different addressing modes, barrel shift, variety of pointers)  8-byte instruction queue  Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available  Interrupts  Fast Interrupt processing programmable priority levels  Non-Maskable Interrupt (NMI)  Optimized 8  CAN  Supports CAN protocol version 2.0 part A and B certified  Bit rates up to 1Mbps  32 message objects  Each message object has its own identifier mask  Programmable FIFO mode (concatenation of message objects)  Maskable interrupt  Disabled Automatic Retransmission mode for Time Triggered CAN applications  Programmable loop-back mode for self-test operation  ISO16845  System clock PLL clock multiplier (1 to 8, 1 when PLL stop) to 8MHz crystal oscillator (maximum frequency when using ceramic resonator depends on Q-factor)  Up to 8MHz external clock for devices with fast clock input feature  32.768kHz subsystem quartz clock  100kHz/2MHz internal RC clock for quick and safe startup, clock stop detection function, watchdog  Clock source selectable from mainclock oscillator, subclock oscillator and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals  The subclock oscillator is enabled by the Boot ROM program controlled by a configuration marker after a Power or External reset  Low Power Consumption - 13 operating modes (different Run, Sleep, Timer, Stop modes)  On-chip  4MHz  USART  Full duplex USARTs (SCI/LIN) range of baud rate settings using a dedicated reload timer  Special synchronous options for adapting to different synchronous serial protocols  LIN functionality working either as master or slave LIN device  Extended support for LIN-Protocol to reduce interrupt load  Wide  On-chip voltage regulator Internal voltage regulator supports a wide MCU supply voltage range (Min=2.7V), offering low power consumption  I2 C  Low voltage detection function  Up to 400kbps and Slave functionality, 7-bit and 10-bit addressing  Master Reset is generated when supply voltage falls below programmable reference voltage  Code Security Protects Flash Memory content from unintended read-out Cypress Semiconductor Corporation Document Number: 002-04712 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 20, 2019 CY96620 Series  A/D converter  Real Time Clock  SAR-type  Operational  8/10-bit resolution  Signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger, reload timers and PPGs  Range Comparator Function  Source Clock Timers Three independent clock timers (23-bit RC clock timer, 23bit Main clock timer, 17-bit Sub clock timer)  Hardware Watchdog Timer  Hardware watchdog timer is active after reset function of Watchdog Timer is used to select the lower window limit of the watchdog interval  Window  Reload Timers  16-bit wide  Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency  Event count function  Free-Running Timers  Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4)  Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27, 1/28 of peripheral clock frequency  Input Capture Units  16-bit wide an interrupt upon external event  Rising edge, Falling edge or Both (rising & falling) edges sensitive  Signals  Output Compare Units  16-bit wide an interrupt when a match with Free-running Timer occurs  A pair of compare registers can be used to generate an output signal  Signals  Programmable Pulse Generator  16-bit down counter, cycle and duty setting registers be used as 2 × 8-bit PPG  Interrupt at trigger, counter borrow and/or duty match  PWM operation and one-shot operation  Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock or of selected Reload timer underflow as clock input  Can be triggered by software or reload timer  Can trigger ADC conversion  Timing point capture  Can  Quadrature Position/Revolution Counter (QPRC)  Up/down count mode, Phase difference count mode, Count mode with direction  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers with interrupt  Detection edge of the three external event input pins AIN, BIN and ZIN is configurable Document Number: 002-04712 Rev. *F on main oscillation (4MHz), sub oscillation (32kHz) or RC oscillation (100kHz/2MHz)  Capable to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration)  Read/write accessible second/minute/hour registers  Can signal interrupts every half second/second/minute/hour/day  Internal clock divider and prescaler provide exact 1s clock  External Interrupts  Edge or Level sensitive mask bit per channel  Each available CAN channel RX has an external interrupt for wake-up  Selected USART channels SIN have an external interrupt for wake-up  Interrupt  Non Maskable Interrupt  Disabled after reset, can be enabled by Boot-ROM depending on ROM configuration block  Once enabled, can not be disabled other than by reset  High or Low level sensitive  Pin shared with external interrupt 0  I/O Ports  Most of the external pins can be used as general purpose I/O  All push-pull outputs (except when used as I2C SDA/SCL line)  Bit-wise programmable as input/output or peripheral signal  Bit-wise programmable input enable  One input level per GPIO-pin (either Automotive or CMOS hysteresis)  Bit-wise programmable pull-up resistor  Built-in On Chip Debugger (OCD)  One-wire debug tool interface function: • Hardware break: 6 points (shared with code event) • Software break: 4096 points  Event function • Code event: 6 points (shared with hardware break) • Data event: 6 points • Event sequencer: 2 levels + reset  Execution time measurement function  Trace function: 42 branches  Security function  Break  Flash Memory  Dual operation flash allowing reading of one Flash bank while programming or erasing the other bank  Command sequencer for automatic execution of programming algorithm and for supporting DMA for programming of the Flash Memory  Supports automatic programming, Embedded Algorithm  Write/Erase/Erase-Suspend/Resume commands  A flag indicating completion of the automatic algorithm  Erase can be performed on each sector individually  Sector protection  Flash Security feature to protect the content of the Flash  Low voltage detection during Flash erase or write Page 2 of 69 CY96620 Series Contents 1. Product Lineup .................................................................................................................................................................. 5 2. Block Diagram ................................................................................................................................................................... 6 3. Pin Assignment ................................................................................................................................................................. 7 4. Pin Description .................................................................................................................................................................. 8 5. Pin Circuit Type ............................................................................................................................................................... 10 6. I/O Circuit Type ............................................................................................................................................................... 12 7. Memory Map .................................................................................................................................................................... 17 8. RAMSTART Addresses................................................................................................................................................... 18 9. User ROM Memory Map For Flash Devices .................................................................................................................. 19 10. Serial Programming Communication Interface ............................................................................................................ 20 11. Interrupt Vector Table ..................................................................................................................................................... 21 12. Handling Precautions ..................................................................................................................................................... 25 12.1 Precautions for Product Design ................................................................................................................................... 25 12.2 Precautions for Package Mounting .............................................................................................................................. 26 12.3 Precautions for Use Environment ................................................................................................................................ 27 13. Handling Devices ............................................................................................................................................................ 28 13.1 Latch-Up Prevention .................................................................................................................................................... 28 13.2 Unused Pins Handling ................................................................................................................................................. 28 13.3 External Clock Usage .................................................................................................................................................. 29 13.3.1 Single Phase External Clock for Main Oscillator .......................................................................................................... 29 13.3.2 Single Phase External Clock for Sub Oscillator ........................................................................................................... 29 13.3.3 Opposite Phase External Clock.................................................................................................................................... 29 13.4 Notes on PLL Clock Mode Operation .......................................................................................................................... 29 13.5 Power Supply Pins (Vcc/Vss) ........................................................................................................................................ 29 13.6 Crystal Oscillator and ceramic resonator Circuit .......................................................................................................... 30 13.7 Turn on Sequence of Power Supply to A/D Converter and Analog Inputs................................................................... 30 13.8 Pin Handling when Not Using the A/D Converter ........................................................................................................ 30 13.9 Notes on Power-on ...................................................................................................................................................... 30 13.10 Stabilization of Power Supply Voltage ......................................................................................................................... 30 13.11 Serial Communication ................................................................................................................................................. 30 13.12 Mode Pin (MD) ............................................................................................................................................................ 30 14. Electrical Characteristics ............................................................................................................................................... 31 14.1 Absolute Maximum Ratings ......................................................................................................................................... 31 14.2 Recommended Operating Conditions ......................................................................................................................... 33 14.3 DC Characteristics ...................................................................................................................................................... 34 14.3.1 Current Rating .............................................................................................................................................................. 34 14.3.2 Pin Characteristics ....................................................................................................................................................... 38 14.4 AC Characteristics ....................................................................................................................................................... 40 14.4.1 Main Clock Input Characteristics .................................................................................................................................. 40 14.4.2 Sub Clock Input Characteristics ................................................................................................................................... 41 14.4.3 Built-in RC Oscillation Characteristics .......................................................................................................................... 42 14.4.4 Internal Clock Timing ................................................................................................................................................... 42 14.4.5 Operating Conditions of PLL ........................................................................................................................................ 43 14.4.6 Reset Input ................................................................................................................................................................... 43 14.4.7 Power-on Reset Timing ................................................................................................................................................ 44 14.4.8 USART Timing ............................................................................................................................................................. 45 Document Number: 002-04712 Rev. *F Page 3 of 69 CY96620 Series 14.4.9 External Input Timing ................................................................................................................................................... 47 14.4.10 I2C Timing ................................................................................................................................................................. 48 14.5 A/D Converter .............................................................................................................................................................. 49 14.5.1 Electrical Characteristics for the A/D Converter ........................................................................................................... 49 14.5.2 Accuracy and Setting of the A/D Converter Sampling Time ......................................................................................... 50 14.5.3 Definition of A/D Converter Terms ............................................................................................................................... 51 14.6 Low Voltage Detection Function Characteristics ......................................................................................................... 53 14.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 55 15. Example Characteristics ................................................................................................................................................ 56 16. Ordering Information ...................................................................................................................................................... 59 17. Package Dimension ........................................................................................................................................................ 60 18. Major Changes ................................................................................................................................................................ 62 Document History ................................................................................................................................................................. 68 Sales, Solutions, and Legal Information ............................................................................................................................. 69 Document Number: 002-04712 Rev. *F Page 4 of 69 CY96620 Series 1. Product Lineup Features Product Type Subclock Dual Operation Flash Memory 32.5KB + 32KB 64.5KB + 32KB 128.5KB + 32KB RAM 4KB 10KB 10KB Package DMA USART with automatic LIN-Header transmission/reception with 16 byte RX- and TX-FIFO I2 C CY96620 Flash Memory Product Subclock can be set by software CY96F622R, CY96F622A CY96F623R, CY96F623A CY96F625R, CY96F625A LQFP-64 LQG064/LQD064 2ch 3ch Product Options R: MCU with CAN A: MCU without CAN Yes (only 1ch) LIN-USART 2 1ch 21ch No Yes No No 3ch 16-bit Free-Running Timer (FRT) 4ch 16-bit Output Compare Unit (OCU) 8/16-bit Programmable Pulse Generator (PPG) with Timing point capture with Start delay with Ramp Quadrature Position/Revolution Counter (QPRC) 8ch (2 channels for LIN-USART) 6ch 8ch (16-bit) / 16ch (8-bit) Yes No No 2ch CAN Interface 1ch External Interrupts (INT) Non-Maskable Interrupt (NMI) Real Time Clock (RTC) Clock Calibration Unit (CAL) Clock Output Function 13ch 1ch 1ch 50 (Dual clock mode) 52 (Single clock mode) 1ch 2ch Low Voltage Detection Function Yes Hardware Watchdog Timer On-chip RC-oscillator On-chip Debugger Yes Yes Yes I/O Ports LIN-USART 2/7/8 No 8/10-bit A/D Converter with Data Buffer with Range Comparator with Scan Disable with ADC Pulse Detection 16-bit Reload Timer (RLT) 16-bit Input Capture Unit (ICU) Remark I2 C 0 AN 0 to 14/24/25/28 to 31 RLT 1/3/6 FRT 0 to 3 FRT 2/3 does not have external clock input pin ICU 0/1/4 to 7/9/10 (ICU 9/10 for LIN-USART) OCU 0/1/4 to 7 PPG 0/1/3/4/6/7/12/14 QPRC 0/1 CAN 2 32 Message Buffers INT 0/2/3/4/7 to 15 Low voltage detection function can be disabled by software Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the general I/O port according to your function use. Document Number: 002-04712 Rev. *F Page 5 of 69 CY96620 Series 2. Block Diagram CKOT0_R, CKOT1, CKOT1_R CKOTX1 X0, X1 X0A, X1A RSTX MD NMI_R DEBUG I/F Clock & Mode Controller Flash Memory A Interrupt Controller 16FX CPU OCD 16FX Core Bus (CLKB) SDA0 SCL0 AVcc AVss AVRH AN0 to AN14 AN24, AN25 AN28 to AN31 ADTG_R TIN1, TIN3 TOT1, TOT3 FRCK0 2 IC 1ch 8/10-bit ADC 21ch 16-bit Reload Timer 1/3/6 3ch IN0, IN1 OUT0_R, OUT1_R I/O Timer 0 FRT 0 ICU 0/1 OCU 0/1 FRCK1 IN4 to IN7 OUT4 to OUT7 I/O Timer 1 FRT 1 ICU 4/5/6/7 OCU 4/5/6/7 I/O Timer 2 FRT 2 ICU 9 I/O Timer 3 FRT 3 ICU 10 Document Number: 002-04712 Rev. *F Peripheral Bus Bridge Peripheral Bus 2 (CLKP2) Peripheral Bus Bridge Watchdog Peripheral Bus 1 (CLKP1) DMA Controller RAM Boot ROM Voltage Regulator Vcc Vss C RX2 CAN Interface 1ch USART 3ch PPG 8ch (16-bit) / 16ch (8-bit) Real Time Clock TX2 SIN2, SIN2_R, SIN7_R, SIN8_R SOT2, SOT2_R, SOT7_R, SOT8_R SCK2, SCK2_R, SCK7_R, SCK8_R TTG0, TTG1, TTG4 to TTG6 TTG7, TTG12 to TTG15 PPG0, PPG1, PPG3, PPG4 PPG6, PPG7, PPG12, PPG14 PPG0_B, PPG1_B, PPG3_B, PPG4_B PPG6_B, PPG7_B, PPG12_B, PPG14_B WOT AIN0, AIN1 QPRC 2ch External Interrupt 13ch BIN0, BIN1 ZIN0, ZIN1 INT8 to INT15 INT0_R, INT2_R, INT4_R INT7_R, INT9_R to INT11_R INT3_R1 Page 6 of 69 CY96620 Series 3. Pin Assignment P01_2 / INT11_R P01_1 / TOT1 / CKOTX1 / OUT1_R P01_4 / PPG4_B P01_3 P01_6 / SOT2_R / PPG6_B P01_5 / SIN2_R / INT7_R*1 P02_0 / PPG12 / CKOT1_R P01_7 / SCK2_R / PPG7_B*1 P02_2 / ZIN0 / PPG14 / CKOT0_R P02_1 P02_4 / AIN0 / IN0 / TTG0 P02_3 X1 RSTX Vss X0 (Top view) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 P01_0 / TIN1 / CKOT1 / OUT0_R C 50 31 P00_7 / INT15 P02_5 / BIN0 / IN1 / TTG1 / ADTG_R 51 30 P00_6 / INT14 P04_4 / SDA0 / FRCK0*2 52 29 P00_5 / INT13 / SIN8_R / PPG14_B*1 2 53 28 P00_4 / INT12 / SOT8_R / PPG12_B P03_0 / AIN1 / IN4 / TTG4 / TTG12 / AN24 54 27 P00_3 / INT11 / SCK8_R / PPG3_B*1 P03_1 / BIN1 / IN5 / TTG5 / TTG13 / AN25 55 26 P00_2 / INT10 / SIN7_R*1 1 56 25 P00_1 / INT9 / SOT7_R / PPG1_B P03_3 / TX2 57 24 P00_0 / INT8 / SCK7_R / PPG0_B*1 P03_4 / OUT4 / AN28 58 23 DEBUG I/F P03_5 / OUT5 / AN29 59 22 P17_0 P03_6 / ZIN1 / OUT6 / AN30 60 21 MD P03_7 / OUT7 / AN31 61 20 P04_1 / X1A*3 P06_0 / AN0 / PPG0 62 19 P04_0 / X0A*3 P06_1 / AN1 / PPG1 63 18 Vss P05_6 / AN14 / INT4_R P04_3 / IN7 / TTG7 / TTG15 P04_2 / IN6 / INT9_R / TTG6 / TTG14 P05_4 / AN12 / TOT3 / INT2_R P05_5 / AN13 / INT0_R / NMI_R P05_2 / AN10 / SCK2*1 8 P05_3 / AN11 / TIN3 / WOT 7 P05_1 / AN9 / SOT2 6 17 9 10 11 12 13 14 15 16 P05_0 / AN8 / SIN2 / INT3_R1*1 5 P06_6 / AN6 / PPG6 4 P06_7 / AN7 / PPG7 3 P06_5 / AN5 2 P06_4 / AN4 / PPG4 64 1 AVss AVcc LQFP - 64 P06_2 / AN2 P03_2 / INT10_R / RX2* P06_3 / AN3 / PPG3 P04_5 / SCL0 / FRCK1* AVRH Vcc (LQG064/LQD064) *1: CMOS input level only *2: CMOS input level only for I2C *3: Please set ROM Configuration Block (RCB) to use the subclock. Other than those above, general-purpose pins have only Automotive input level. Document Number: 002-04712 Rev. *F Page 7 of 69 CY96620 Series 4. Pin Description Pin Name Feature Description ADTG_R ADC Relocated A/D converter trigger input pin AINn QPRC Quadrature Position/Revolution Counter Unit n input pin ANn ADC A/D converter channel n input pin AVcc Supply Analog circuits power supply pin AVRH ADC A/D converter high reference voltage input pin AVss Supply Analog circuits power supply pin BINn QPRC Quadrature Position/Revolution Counter Unit n input pin C Voltage regulator Internally regulated power supply stabilization capacitor pin CKOTn Clock Output function Clock Output function n output pin CKOTn_R Clock Output function Relocated Clock Output function n output pin CKOTXn Clock Output function Clock Output function n inverted output pin DEBUG I/F OCD On Chip Debugger input/output pin FRCKn Free-Running Timer Free-Running Timer n input pin INn ICU Input Capture Unit n input pin INTn External Interrupt External Interrupt n input pin INTn_R External Interrupt Relocated External Interrupt n input pin INTn_R1 External Interrupt Relocated External Interrupt n input pin MD Core Input pin for specifying the operating mode NMI_R External Interrupt Relocated Non-Maskable Interrupt input pin OUTn OCU Output Compare Unit n waveform output pin OUTn_R OCU Relocated Output Compare Unit n waveform output pin Pnn_m GPIO General purpose I/O pin PPGn PPG Programmable Pulse Generator n output pin (16bit/8bit) PPGn_B PPG Programmable Pulse Generator n output pin (16bit/8bit) RSTX Core Reset input pin RXn CAN CAN interface n RX input pin SCKn USART USART n serial clock input/output pin SCKn_R USART Relocated USART n serial clock input/output pin SCLn I2 C I2C interface n clock I/O input/output pin SDAn I2 C I2C interface n serial data I/O input/output pin SINn USART USART n serial data input pin SINn_R USART Relocated USART n serial data input pin SOTn USART USART n serial data output pin SOTn_R USART Relocated USART n serial data output pin TINn Reload Timer Reload Timer n event input pin TOTn Reload Timer Reload Timer n output pin TTGn PPG Programmable Pulse Generator n trigger input pin TXn CAN CAN interface n TX output pin Vcc Supply Power supply pin Vss Supply Power supply pin WOT RTC Real Time clock output pin Document Number: 002-04712 Rev. *F Page 8 of 69 CY96620 Series Pin Name Feature Description X0 Clock Oscillator input pin X0A Clock Subclock Oscillator input pin X1 Clock Oscillator output pin X1A Clock Subclock Oscillator output pin ZINn QPRC Quadrature Position/Revolution Counter Unit n input pin Document Number: 002-04712 Rev. *F Page 9 of 69 CY96620 Series 5. Pin Circuit Type Pin No. I/O Circuit Type* Pin Name 1 Supply AVss 2 G AVRH 3 K P06_2 / AN2 4 K P06_3 / AN3 / PPG3 5 K P06_4 / AN4 / PPG4 6 K P06_5 / AN5 7 K P06_6 / AN6 / PPG6 8 K P06_7 / AN7 / PPG7 9 I P05_0 / AN8 / SIN2 / INT3_R1 10 K P05_1 / AN9 / SOT2 11 I P05_2 / AN10 / SCK2 12 K P05_3 / AN11 / TIN3 / WOT 13 K P05_4 / AN12 / TOT3 / INT2_R 14 K P05_5 / AN13 / INT0_R / NMI_R 15 K P05_6 / AN14 / INT4_R 16 H P04_2 / IN6 / INT9_R / TTG6 / TTG14 17 H P04_3 / IN7 / TTG7 / TTG15 18 Supply Vss 19 B P04_0 / X0A 20 B P04_1 / X1A 21 C MD 22 H P17_0 23 O DEBUG I/F 24 M P00_0 / INT8 / SCK7_R / PPG0_B 25 H P00_1 / INT9 / SOT7_R / PPG1_B 26 M P00_2 / INT10 / SIN7_R 27 M P00_3 / INT11 / SCK8_R / PPG3_B 28 H P00_4 / INT12 / SOT8_R / PPG12_B 29 M P00_5 / INT13 / SIN8_R / PPG14_B 30 H P00_6 / INT14 31 H P00_7 / INT15 32 H P01_0 / TIN1 / CKOT1 / OUT0_R Document Number: 002-04712 Rev. *F Page 10 of 69 CY96620 Series Pin No. I/O Circuit Type* Pin Name 33 H P01_1 / TOT1 / CKOTX1 / OUT1_R 34 H P01_2 / INT11_R 35 H P01_3 36 H P01_4 / PPG4_B 37 M P01_5 / SIN2_R / INT7_R 38 H P01_6 / SOT2_R / PPG6_B 39 M P01_7 / SCK2_R / PPG7_B 40 H P02_0 / PPG12 / CKOT1_R 41 H P02_1 42 H P02_2 / ZIN0 / PPG14 / CKOT0_R 43 H P02_3 44 H P02_4 / AIN0 / IN0 / TTG0 45 C RSTX 46 A X1 47 A X0 48 Supply Vss 49 Supply Vcc 50 F C 51 H P02_5 / BIN0 / IN1 / TTG1 / ADTG_R 52 N P04_4 / SDA0 / FRCK0 53 N P04_5 / SCL0 / FRCK1 54 K P03_0 / AIN1 / IN4 / TTG4 / TTG12 / AN24 55 K P03_1 / BIN1 / IN5 / TTG5 / TTG13 / AN25 56 M P03_2 / INT10_R / RX2 57 H P03_3 / TX2 58 K P03_4 / OUT4 / AN28 59 K P03_5 / OUT5 / AN29 60 K P03_6 / ZIN1 / OUT6 / AN30 61 K P03_7 / OUT7 / AN31 62 K P06_0 / AN0 / PPG0 63 K P06_1 / AN1 / PPG1 64 Supply AVcc *: See “I/O Circuit Type” for details on the I/O circuit types. Document Number: 002-04712 Rev. *F Page 11 of 69 CY96620 Series 6. I/O Circuit Type Type A Circuit X1 R 0 1 X out Remarks High-speed oscillation circuit: • Programmable between oscillation mode (external crystal or resonator connected to X0/X1 pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin) • Feedback resistor = approx. 1.0M • The amplitude: 1.8V±0.15V to operate by the internal supply voltage FCI X0 FCI or Osc disable Document Number: 002-04712 Rev. *F Page 12 of 69 CY96620 Series Type B Circuit Pull-up control P-ch Standby control for input shutdown P-ch Pout N-ch Nout Remarks Low-speed oscillation circuit shared with GPIO functionality: • Feedback resistor = approx. 5.0M • GPIO functionality selectable (CMOS level output (IOL = 4mA, IOH = -4mA), Automotive input with input shutdown function and programmable pull-up resistor) R Automotive input X1A R X out 0 1 FCI X0A FCI or Osc disable Pull-up control P-ch Standby control for input shutdown P-ch Pout N-ch Nout R C Document Number: 002-04712 Rev. *F Automotive input CMOS hysteresis input pin Page 13 of 69 CY96620 Series Type F Circuit Remarks Power supply input protection circuit P-ch N-ch G • A/D converter ref+ (AVRH) power supply input pin with protection circuit • Without protection circuit against VCC for pins AVRH P-ch N-ch H Pull-up control P-ch P-ch Pout N-ch Nout • CMOS level output (IOL = 4mA, IOH = -4mA) • Automotive input with input shutdown function • Programmable pull-up resistor R Standby control for input shutdown Automotive input I Pull-up control P-ch P-ch Pout N-ch Nout • CMOS level output (IOL = 4mA, IOH = -4mA) • CMOS hysteresis input with input shutdown function • Programmable pull-up resistor • Analog input R Hysteresis input Standby control for input shutdown Analog input Document Number: 002-04712 Rev. *F Page 14 of 69 CY96620 Series Type K Circuit Remarks Pull-up control P-ch P-ch Pout N-ch Nout • CMOS level output (IOL = 4mA, IOH = -4mA) • Automotive input with input shutdown function • Programmable pull-up resistor • Analog input R Automotive input Standby control for input shutdown Analog input M Pull-up control P-ch P-ch Pout N-ch Nout R • CMOS level output (IOL = 4mA, IOH = -4mA) • CMOS hysteresis input with input shutdown function • Programmable pull-up resistor Hysteresis input Standby control for input shutdown N Pull-up control P-ch R P-ch Pout N-ch Nout* • CMOS level output (IOL = 3mA, IOH = -3mA) • CMOS hysteresis input with input shutdown function • Programmable pull-up resistor *: N-channel transistor has slew rate control according to I2C spec, irrespective of usage. Hysteresis input Standby control for input shutdown Document Number: 002-04712 Rev. *F Page 15 of 69 CY96620 Series Type O Circuit Remarks • Open-drain I/O • Output 25mA, Vcc = 2.7V • TTL input N-ch Nout R Standby control for input shutdown Document Number: 002-04712 Rev. *F TTL input Page 16 of 69 CY96620 Series 7. Memory Map FF:FFFFH USER ROM*1 DE:0000H DD:FFFFH Reserved 10:0000H 0F:C000H Boot-ROM Peripheral 0E:9000H Reserved 01:0000H 00:8000H RAMSTART0*2 ROM/RAM MIRROR Internal RAM bank0 Reserved 00:0C00H 00:0380H Peripheral 00:0180H GPR*3 00:0100H DMA 00:00F0H Reserved 00:0000H Peripheral *1: For details about USER ROM area, see “USER ROM MEMORY MAP FOR FLASH DEVICES” on the following pages. *2: For RAMSTART addresses, see the table on the next page. *3: Unused GPR banks can be used as RAM area. GPR: General-Purpose Register The DMA area is only available if the device contains the corresponding resource. The available RAM and ROM area depends on the device. Document Number: 002-04712 Rev. *F Page 17 of 69 CY96620 Series 8. RAMSTART Addresses Bank 0 RAM Size Devices RAMSTART0 CY96F622 4KB 00:7200H CY96F623 CY96F625 10KB 00:5A00H Document Number: 002-04712 Rev. *F Page 18 of 69 CY96620 Series 9. User ROM Memory Map For Flash Devices *: Physical address area of SAS-512B is from DF:0000H to DF:01FFH. Others (from DF:0200H to DF:1FFFH) is mirror area of SAS-512B. Sector SAS contains the ROM configuration block RCBA at CPU address DF:0000H -DF:01FFH. SAS can not be used for E2PROM emulation. Document Number: 002-04712 Rev. *F Page 19 of 69 CY96620 Series 10. Serial Programming Communication Interface USART pins for Flash serial programming (MD = 0, DEBUG I/F = 0, Serial Communication mode) CY96620 Pin Number USART Number 9 10 Normal Function SIN2 USART2 SOT2 11 SCK2 26 SIN7_R 25 USART7 SOT7_R 24 SCK7_R 29 SIN8_R 28 USART8 27 Document Number: 002-04712 Rev. *F SOT8_R SCK8_R Page 20 of 69 CY96620 Series 11. Interrupt Vector Table Vector Number Offset in Vector Table Index in ICR to Program Cleared by DMA Vector Name Description 0 3FCH CALLV0 No - CALLV instruction 1 3F8H CALLV1 No - CALLV instruction 2 3F4H CALLV2 No - CALLV instruction 3 3F0H CALLV3 No - CALLV instruction 4 3ECH CALLV4 No - CALLV instruction 5 3E8H CALLV5 No - CALLV instruction 6 3E4H CALLV6 No - CALLV instruction 7 3E0H CALLV7 No - CALLV instruction 8 3DCH RESET No - Reset vector 9 3D8H INT9 No - INT9 instruction 10 3D4H EXCEPTION No - Undefined instruction execution 11 3D0H NMI No - Non-Maskable Interrupt 12 3CCH DLY No 12 Delayed Interrupt 13 3C8H RC_TIMER No 13 RC Clock Timer 14 3C4H MC_TIMER No 14 Main Clock Timer 15 3C0H SC_TIMER No 15 Sub Clock Timer 16 3BCH LVDI No 16 Low Voltage Detector 17 3B8H EXTINT0 Yes 17 External Interrupt 0 18 3B4H - - 18 Reserved 19 3B0H EXTINT2 Yes 19 External Interrupt 2 20 3ACH EXTINT3 Yes 20 External Interrupt 3 21 3A8H EXTINT4 Yes 21 External Interrupt 4 22 3A4H - - 22 Reserved 23 3A0H - - 23 Reserved 24 39CH EXTINT7 Yes 24 External Interrupt 7 25 398H EXTINT8 Yes 25 External Interrupt 8 26 394H EXTINT9 Yes 26 External Interrupt 9 27 390H EXTINT10 Yes 27 External Interrupt 10 28 38CH EXTINT11 Yes 28 External Interrupt 11 29 388H EXTINT12 Yes 29 External Interrupt 12 30 384H EXTINT13 Yes 30 External Interrupt 13 31 380H EXTINT14 Yes 31 External Interrupt 14 32 37CH EXTINT15 Yes 32 External Interrupt 15 33 378H - - 33 Reserved 34 374H - - 34 Reserved 35 370H CAN2 No 35 CAN Controller 2 36 36CH - - 36 Reserved 37 368H - - 37 Reserved 38 364H PPG0 Yes 38 Programmable Pulse Generator 0 39 360H PPG1 Yes 39 Programmable Pulse Generator 1 Document Number: 002-04712 Rev. *F Page 21 of 69 CY96620 Series 40 35CH - - Index in ICR to Program 40 41 358H PPG3 Yes 41 Programmable Pulse Generator 3 42 354H PPG4 Yes 42 Programmable Pulse Generator 4 43 350H - - 43 Reserved 44 34CH PPG6 Yes 44 Programmable Pulse Generator 6 45 348H PPG7 Yes 45 Programmable Pulse Generator 7 46 344H - - 46 Reserved 47 340H - - 47 Reserved 48 33CH - - 48 Reserved 49 338H - - 49 Reserved 50 334H PPG12 Yes 50 Programmable Pulse Generator 12 51 330H - - 51 Reserved 52 32CH PPG14 Yes 52 Programmable Pulse Generator 14 53 328H - - 53 Reserved 54 324H - - 54 Reserved 55 320H - - 55 Reserved 56 31CH - - 56 Reserved 57 318H - - 57 Reserved 58 314H - - 58 Reserved 59 310H RLT1 Yes 59 Reload Timer 1 60 30CH - - 60 Reserved 61 308H RLT3 Yes 61 Reload Timer 3 62 304H - - 62 Reserved 63 300H - - 63 Reserved 64 2FCH RLT6 Yes 64 Reload Timer 6 65 2F8H ICU0 Yes 65 Input Capture Unit 0 66 2F4H ICU1 Yes 66 Input Capture Unit 1 67 2F0H - - 67 Reserved 68 2ECH - - 68 Reserved 69 2E8H ICU4 Yes 69 Input Capture Unit 4 70 2E4H ICU5 Yes 70 Input Capture Unit 5 71 2E0H ICU6 Yes 71 Input Capture Unit 6 72 2DCH ICU7 Yes 72 Input Capture Unit 7 73 2D8H - - 73 Reserved 74 2D4H ICU9 Yes 74 Input Capture Unit 9 75 2D0H ICU10 Yes 75 Input Capture Unit 10 76 2CCH - - 76 Reserved 77 2C8H OCU0 Yes 77 Output Compare Unit 0 78 2C4H OCU1 Yes 78 Output Compare Unit 1 79 2C0H - - 79 Reserved 80 2BCH - - 80 Reserved Vector Number Offset in Vector Table Document Number: 002-04712 Rev. *F Cleared by DMA Vector Name Description Reserved Page 22 of 69 CY96620 Series 81 2B8H OCU4 Yes Index in ICR to Program 81 82 2B4H OCU5 Yes 82 Output Compare Unit 5 83 2B0H OCU6 Yes 83 Output Compare Unit 6 84 2ACH OCU7 Yes 84 Output Compare Unit 7 85 2A8H - - 85 Reserved 86 2A4H - - 86 Reserved 87 2A0H - - 87 Reserved 88 29CH - - 88 Reserved 89 298H FRT0 Yes 89 Free-Running Timer 0 90 294H FRT1 Yes 90 Free-Running Timer 1 91 290H FRT2 Yes 91 Free-Running Timer 2 92 28CH FRT3 Yes 92 Free-Running Timer 3 93 288H RTC0 No 93 Real Time Clock 94 284H CAL0 No 94 Clock Calibration Unit 95 280H - - 95 Reserved 96 27CH IIC0 Yes 96 I2C interface 0 97 278H - - 97 Reserved 98 274H ADC0 Yes 98 A/D Converter 0 99 270H - - 99 Reserved 100 26CH - - 100 Reserved 101 268H - - 101 Reserved 102 264H - - 102 Reserved 103 260H - - 103 Reserved 104 25CH - - 104 Reserved 105 258H LINR2 Yes 105 LIN USART 2 RX 106 254H LINT2 Yes 106 LIN USART 2 TX 107 250H - - 107 Reserved 108 24CH - - 108 Reserved 109 248H - - 109 Reserved 110 244H - - 110 Reserved 111 240H - - 111 Reserved 112 23CH - - 112 Reserved 113 238H - - 113 Reserved 114 234H - - 114 Reserved 115 230H LINR7 Yes 115 LIN USART 7 RX 116 22CH LINT7 Yes 116 LIN USART 7 TX 117 228H LINR8 Yes 117 LIN USART 8 RX 118 224H LINT8 Yes 118 LIN USART 8 TX 119 220H - - 119 Reserved 120 21CH - - 120 Reserved 121 218H - - 121 Reserved 122 214H - - 122 Reserved Vector Number Offset in Vector Table Document Number: 002-04712 Rev. *F Cleared by DMA Vector Name Description Output Compare Unit 4 Page 23 of 69 CY96620 Series 123 210H - - Index in ICR to Program 123 124 20CH - - 124 Reserved 125 208H - - 125 Reserved 126 204H - - 126 Reserved 127 200H - - 127 Reserved 128 1FCH - - 128 Reserved 129 1F8H - - 129 Reserved 130 1F4H - - 130 Reserved 131 1F0H - - 131 Reserved 132 1ECH - - 132 Reserved 133 1E8H FLASHA Yes 133 Flash memory A interrupt 134 1E4H - - 134 Reserved 135 1E0H - - 135 Reserved 136 1DCH - - 136 Reserved 137 1D8H QPRC0 Yes 137 Quad Position/Revolution counter 0 138 1D4H QPRC1 Yes 138 139 1D0H ADCRC0 No 139 140 1CCH - - 140 Quad Position/Revolution counter 1 A/D Converter 0 - Range Comparator Reserved 141 1C8H - - 141 Reserved 142 1C4H - - 142 Reserved 143 1C0H - - 143 Reserved Vector Number Offset in Vector Table Document Number: 002-04712 Rev. *F Cleared by DMA Vector Name Description Reserved Page 24 of 69 CY96620 Series 12. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 12.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices.  Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.  Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand.  Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.  Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence.  Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.  Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Document Number: 002-04712 Rev. *F Page 25 of 69 CY96620 Series  Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 12.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative.  Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting.  Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions.  Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use.  Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.  Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Document Number: 002-04712 Rev. *F Page 26 of 69 CY96620 Series  Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 12.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-04712 Rev. *F Page 27 of 69 CY96620 Series 13. Handling Devices Special Care is Required for the Following when Handling the Device: • • • • • • • • • • • • Latch-up prevention Unused pins handling External clock usage Notes on PLL clock mode operation Power supply pins (Vcc/Vss) Crystal oscillator and ceramic resonator circuit Turn on sequence of power supply to A/D converter and analog inputs Pin handling when not using the A/D converter Notes on Power-on Stabilization of power supply voltage Serial communication Mode Pin (MD) 13.1 Latch-Up Prevention CMOS IC chips may suffer latch-up under the following conditions: • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between Vcc pins and Vss pins. • The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current dramatically, causing thermal damages to the device. For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed the digital powersupply voltage. 13.2 Unused Pins Handling Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0). Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. To prevent latch-up, they must therefore be pulled up or pulled down through resistors which should be more than 2k. Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above. Document Number: 002-04712 Rev. *F Page 28 of 69 CY96620 Series 13.3 External Clock Usage The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows: 13.3.1 Single Phase External Clock for Main Oscillator When using a single phase external clock for the Main oscillator, X0 pin must be driven and X1 pin left open. And supply 1.8V power to the external clock. X0 X1 13.3.2 Single Phase External Clock for Sub Oscillator When using a single phase external clock for the Sub oscillator, “External clock mode” must be selected and X0A/P04_0 pin must be driven. X1A/P04_1 pin can be configured as GPIO. 13.3.3 Opposite Phase External Clock When using an opposite phase external clock, X1 (X1A) pins must be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins. Supply level on X0 and X1 pins must be 1.8V. X0 X1 13.4 Notes on PLL Clock Mode Operation If the microcontroller is operated with PLL clock mode and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed. 13.5 Power Supply Pins (Vcc/Vss) It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range. Vcc and Vss pins must be connected to the device from the power supply with lowest possible impedance. The smoothing capacitor at Vcc pin must use the one of a capacity value that is larger than Cs. Besides this, as a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1F between Vcc and Vss pins as close as possible to Vcc and Vss pins. Document Number: 002-04712 Rev. *F Page 29 of 69 CY96620 Series 13.6 Crystal Oscillator and ceramic resonator Circuit Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area for stabilizing the operation. It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially when using low-Q resonators at higher frequencies. 13.7 Turn on Sequence of Power Supply to A/D Converter and Analog Inputs It is required to turn the A/D converter power supply (AVCC, AVRH) and analog inputs (ANn) on after turning the digital power supply (VCC) on. It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, AVRH must not exceed AVCC . Input voltage for ports shared with analog input ports also must not exceed AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable). 13.8 Pin Handling when Not Using the A/D Converter If the A/D converter is not used, the power supply pins for A/D converter should be connected such as AVCC = VCC , AVSS = AVRH = VSS. 13.9 Notes on Power-on To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50s from 0.2V to 2.7V. 13.10 Stabilization of Power Supply Voltage If the power supply voltage varies acutely even within the operation safety range of the VCC power supply voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be stabilized in such a way that VCC ripple fluctuations (peak to peak value) in the commercial frequencies (50Hz to 60Hz) fall within 10% of the standard VCC power supply voltage and the transient fluctuation rate becomes 0.1V/s or less in instantaneous fluctuation for power supply switching. 13.11 Serial Communication There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit the data if an error occurs. 13.12 Mode Pin (MD) Connect the mode pin directly to Vcc or Vss pin. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mode pin to Vcc or Vss pin and provide a low-impedance connection. Document Number: 002-04712 Rev. *F Page 30 of 69 CY96620 Series 14. Electrical Characteristics 14.1 Absolute Maximum Ratings Parameter Power supply voltage*1 Analog power supply voltage*1 Analog reference voltage*1 Input voltage*1 Output voltage*1 Maximum Clamp Current Total Maximum Clamp Current "L" level maximum output current "L" level average output current "L" level maximum overall output current "L" level average overall output current "H" level maximum output current "H" level average output current "H" level maximum overall output current "H" level average overall output current Power consumption*5 Operating ambient temperature Storage temperature Symbol Condition Min Rating Max Unit VCC - VSS - 0.3 VSS + 6.0 V AVCC - VSS - 0.3 VSS + 6.0 V AVRH - VSS - 0.3 VSS + 6.0 V VI VO - VSS - 0.3 VSS - 0.3 VSS + 6.0 VSS + 6.0 V V ICLAMP - -4.0 +4.0 mA Σ|ICLAMP| - - 17 mA IOL - - 15 mA IOLAV - - 4 mA ΣIOL - - 42 mA ΣIOLAV - - 21 mA IOH - - -15 mA IOHAV - - -4 mA ΣIOH - - -42 mA ΣIOHAV - - -21 mA PD TA= +125°C - 352*6 mW TA - -40 +125*7 °C TSTG - -55 +150 °C Remarks VCC = AVCC*2 AVCC ≥ AVRH, AVRH ≥ AVSS VI ≤ VCC + 0.3V*3 VO ≤ VCC + 0.3V*3 Applicable to general purpose I/O pins *4 Applicable to general purpose I/O pins *4 *1: This parameter is based on VSS = AVSS = 0V. *2: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *3: VI and VO should not exceed VCC + 0.3V. VI should also not exceed the specified ratings. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/Output voltages of standard ports depend on VCC. *4: Applicable to all general purpose I/O pins (Pnn_m). • • • • Use within recommended operating conditions. Use at DC voltage (current). The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0V), the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset. Document Number: 002-04712 Rev. *F Page 31 of 69 CY96620 Series • The DEBUG I/F pin has only a protective diode against VSS. Hence it is only permitted to input a negative clamping current (4mA). For protection against positive input voltages, use an external clamping diode which limits the input voltage to maximum 6.0V. • Sample recommended circuits: Protective diode VCC Limiting resistance P-ch +B input (0V to 16V) N-ch R *5: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance of the package on the PCB. The actual power dissipation depends on the customer application and can be calculated as follows: PD = PIO + PINT PIO = Σ (VOL  IOL + VOH  IOH) (I/O load power dissipation, sum is performed on all I/O ports) PINT = VCC  (ICC + IA) (internal power dissipation) ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the selected operation mode and clock frequency and the usage of functions like Flash programming. IA is the analog current consumption into AVCC. *6: Worst case value for a package mounted on single layer PCB at specified TA without air flow. *7: Write/erase to a large sector in flash memory is warranted with TA ≤ + 105°C. WARNING Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-04712 Rev. *F Page 32 of 69 CY96620 Series 14.2 Recommended Operating Conditions (VSS = AVSS = 0V) Parameter Symbol Power supply voltage VCC, AVCC Smoothing capacitor at C pin CS Min 2.7 2.0 0.5 Value Typ Unit - Max 5.5 5.5 V V 1.0 to 3.9 4.7 F Remarks Maintains RAM data in stop mode 1.0F (Allowance within ± 50%) 3.9µF (Allowance within ± 20%) Please use the ceramic capacitor or the capacitor of the frequency response of this level. The smoothing capacitor at VCC must use the one of a capacity value that is larger than CS. WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-04712 Rev. *F Page 33 of 69 CY96620 Series 14.3 DC Characteristics 14.3.1 Current Rating Parameter Symbol Pin Name (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Value Conditions Unit Remarks Min Typ Max - 25 - mA TA = +25°C - - 34 mA TA = +105°C - - 35 mA TA = +125°C Main Run mode with CLKS1/2 = CLKB = CLKP1/2 = 4MHz - 3.5 - mA TA = +25°C Flash 0 wait - - 7.5 mA TA = +105°C - - 8.5 mA TA = +125°C RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = CLKRC = 2MHz - 1.7 - mA TA = +25°C Flash 0 wait - - 5.5 mA TA = +105°C (CLKMC, CLKPLL and CLKSC stopped) - - 6.5 mA TA = +125°C - 0.15 - mA TA = +25°C Flash 0 wait - - 3.2 mA TA = +105°C (CLKMC, CLKPLL and CLKSC stopped) - - 4.2 mA TA = +125°C Sub Run mode with CLKS1/2 = CLKB = CLKP1/2 = 32kHz - 0.1 - mA TA = +25°C Flash 0 wait - - 3 mA TA = +105°C (CLKMC, CLKPLL and CLKRC stopped) - - 4 mA TA = +125°C PLL Run mode with CLKS1/2 = CLKB = CLKP1/2 = 32MHz ICCPLL Flash 0 wait (CLKRC and CLKSC stopped) ICCMAIN (CLKPLL, CLKSC and CLKRC stopped) Power supply current in Run modes*1 ICCRCH Vcc RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = CLKRC = 100kHz ICCRCL ICCSUB Document Number: 002-04712 Rev. *F Page 34 of 69 CY96620 Series Parameter Symbol Pin Name ICCSMAIN ICCSRCH ICCSRCL ICCSSUB Document Number: 002-04712 Rev. *F Vcc Value Typ Min Max Unit Remarks - 6.5 - mA TA = +25°C - - 13 mA TA = +105°C - - 14 mA TA = +125°C Main Sleep mode with CLKS1/2 = CLKP1/2 = 4MHz, SMCR:LPMSS = 0 (CLKPLL, CLKRC and CLKSC stopped) - 0.9 - mA TA = +25°C - - 4 mA TA = +105°C - - 5 mA TA = +125°C RC Sleep mode with CLKS1/2 = CLKP1/2 = CLKRC = 2MHz, SMCR:LPMSS = 0 (CLKMC, CLKPLL and CLKSC stopped) - 0.5 - mA TA = +25°C - - 3.5 mA TA = +105°C - - 4.5 mA TA = +125°C - 0.06 - mA TA = +25°C - - 2.7 mA TA = +105°C - - 3.7 mA TA = +125°C - 0.04 - mA TA = +25°C - - 2.5 mA TA = +105°C - - 3.5 mA TA = +125°C PLL Sleep mode with CLKS1/2 = CLKP1/2 = 32MHz (CLKRC and CLKSC stopped) ICCSPLL Power supply current in Sleep modes*1 Conditions RC Sleep mode with CLKS1/2 = CLKP1/2 = CLKRC = 100kHz (CLKMC, CLKPLL and CLKSC stopped) Sub Sleep mode with CLKS1/2 = CLKP1/2 = 32kHz, (CLKMC, CLKPLL and CLKRC stopped) Page 35 of 69 CY96620 Series Parameter Symbol Pin Name ICCTMAIN ICCTRCH Vcc ICCTRCL ICCTSUB Document Number: 002-04712 Rev. *F Value Typ Min Max Unit Remarks - 1800 2245 A TA = +25°C - - 3165 A TA = +105°C - - 3975 A TA = +125°C Main Timer mode with CLKMC = 4MHz, SMCR:LPMSS = 0 (CLKPLL, CLKRC and CLKSC stopped) - 285 325 A TA = +25°C - - 1085 A TA = +105°C - - 1930 A TA = +125°C RC Timer mode with CLKRC = 2MHz, SMCR:LPMSS = 0 (CLKPLL, CLKMC and CLKSC stopped) - 160 210 A TA = +25°C - - 1025 A TA = +105°C - - 1840 A TA = +125°C - 35 75 A TA = +25°C - - 855 A TA = +105°C - - 1640 A TA = +125°C - 25 65 A TA = +25°C - - 830 A TA = +105°C - - 1620 A TA = +125°C PLL Timer mode with CLKPLL = 32MHz (CLKRC and CLKSC stopped) ICCTPLL Power supply current in Timer modes*2 Conditions RC Timer mode with CLKRC = 100kHz (CLKPLL, CLKMC and CLKSC stopped) Sub Timer mode with CLKSC = 32kHz (CLKMC, CLKPLL and CLKRC stopped) Page 36 of 69 CY96620 Series Parameter Symbol Power supply current in Stop mode*3 ICCH Flash Power Down current ICCFLASHPD - Value Typ 20 Max 55 A TA = +25°C - - 825 A TA = +105°C - - 1615 A TA = +125°C - - 36 70 A Low voltage detector enabled - 5 - A TA = +25°C - - 12.5 A TA = +125°C - 12.5 - mA TA = +25°C - - 20 mA TA = +125°C Pin Name Conditions - Min Vcc Power supply current for active Low Voltage detector*4 ICCLVD Flash Write/ Erase current*5 ICCFLASH - Unit Remarks *1: The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the Hardware Manual for further details about voltage regulator control. Current for "On Chip Debugger" part is not included. Power supply current in Run mode does not include Flash Write / Erase current. *2: The power supply current in Timer mode is the value when Flash is in Power-down / reset mode. When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current. The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. The current for "On Chip Debugger" part is not included. *3: The power supply current in Stop mode is the value when Flash is in Power-down / reset mode. When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current. *4 : When low voltage detector is enabled, ICCLVD must be added to Power supply current. *5: When Flash Write / Erase program is executed, ICCFLASH must be added to Power supply current. Document Number: 002-04712 Rev. *F Page 37 of 69 CY96620 Series 14.3.2 Pin Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Symbol "L" level input voltage Conditions Port inputs Pnn_m - VIHX0S X0 VIHX0AS X0A External clock in "Fast Clock Input mode" External clock in "Oscillation mode" VIHR RSTX - VIHM MD - VIHD DEBUG I/F - VIL Port inputs Pnn_m VIH "H" level input voltage Pin Name - External clock in "Fast Clock Input mode" External clock in "Oscillation mode" VILX0S X0 VILX0AS X0A VILR RSTX - VILM MD - VILD DEBUG I/F - Document Number: 002-04712 Rev. *F Min Value Typ VCC  0.7 VCC  0.8 VD  0.8 VCC  0.8 VCC  0.8 VCC - 0.3 - 2.0 - VSS - 0.3 VSS - 0.3 VSS VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 - - Max VCC + 0.3 VCC + 0.3 VD VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC  0.3 VCC  0.5 VD  0.2 VCC  0.2 VCC  0.2 VSS + 0.3 0.8 Uni t V V V Remarks CMOS Hysteresis input AUTOMOTIVE Hysteresis input VD=1.8V±0.15V V V V CMOS Hysteresis input CMOS Hysteresis input V TTL Input V CMOS Hysteresis input AUTOMOTIVE Hysteresis input V V VD=1.8V±0.15V V V V V CMOS Hysteresis input CMOS Hysteresis input TTL Input Page 38 of 69 CY96620 Series Parameter Symbol Pin Name VOH4 4mA type VOH3 3mA type VOL4 4mA type VOL3 3mA type VOLD DEBUG I/F Input leak current IIL Pnn_m Pull-up resistance value RPU Pnn_m CIN Other than C, Vcc, Vss, AVcc, AVss, AVRH "H" level output voltage "L" level output voltage Input capacitance Document Number: 002-04712 Rev. *F Conditions 4.5V ≤ VCC ≤ 5.5V IOH = -4mA 2.7V ≤ VCC < 4.5V IOH = -1.5mA 4.5V ≤ VCC ≤ 5.5V IOH = -3mA 2.7V ≤ VCC < 4.5V IOH = -1.5mA 4.5V ≤ VCC ≤ 5.5V IOL = +4mA 2.7V ≤ VCC < 4.5V IOL = +1.7mA 2.7V ≤ VCC < 5.5V IOL = +3mA VCC = 2.7V IOL = +25mA VSS < VI < VCC AVSS < VI < AVCC, AVRH Min Value Typ Max Unit VCC - 0.5 - VCC V VCC - 0.5 - VCC V - - 0.4 V - - 0.4 V 0 - 0.25 V -1 - +1 A VCC = 5.0V ±10% 25 50 100 k - - 5 15 pF Remarks Page 39 of 69 CY96620 Series 14.4 AC Characteristics 14.4.1 Main Clock Input Characteristics (VCC = AVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Input frequency Pin Name Symbol fC X0, X1 fFCI Max Unit 4 - 8 MHz - - 8 MHz 4 - 8 MHz Input frequency Value Typ Min - 8 When using a crystal oscillator, PLL off When using an opposite phase external clock, PLL off When using a crystal oscillator or opposite phase external clock, PLL on MHz When using a single phase external clock in “Fast Clock Input mode”, PLL off When using a single phase external clock in “Fast Clock Input mode”, PLL on X0 4 - 8 MHz Input clock cycle tCYLH - 125 - - ns Input clock pulse width PWH, PWL - 55 - - ns Document Number: 002-04712 Rev. *F Remarks Page 40 of 69 CY96620 Series 14.4.2 Sub Clock Input Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Input frequency Pin Name Symbol fCL Value Conditions Min Typ Max Unit - - 32.768 - kHz - - - 100 kHz X0A - - - 50 kHz X0A, X1A Input clock cycle tCYLL - - 10 - - s Input clock pulse width - - PWH/tCYLL, PWL/tCYLL 30 - 70 % Document Number: 002-04712 Rev. *F Remarks When using an oscillation circuit When using an opposite phase external clock When using a single phase external clock Page 41 of 69 CY96620 Series 14.4.3 Built-in RC Oscillation Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Clock frequency RC clock stabilization time 14.4.4 Value Symbol Min Typ Unit Max 50 100 200 kHz 1 2 4 MHz 80 160 320 s 64 128 256 s Remarks When using slow frequency of RC oscillator When using fast frequency of RC oscillator When using slow frequency of RC oscillator (16 RC clock cycles) When using fast frequency of RC oscillator (256 RC clock cycles) fRC tRCSTAB Internal Clock Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Value Symbol Min Max Unit Internal System clock frequency (CLKS1 and CLKS2) fCLKS1, fCLKS2 - 54 MHz Internal CPU clock frequency (CLKB), Internal peripheral clock frequency (CLKP1) fCLKB, fCLKP1 - 32 MHz Internal peripheral clock frequency (CLKP2) fCLKP2 - 32 MHz Document Number: 002-04712 Rev. *F Page 42 of 69 CY96620 Series 14.4.5 Operating Conditions of PLL (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Symbol Value Min Typ Unit Max Remarks PLL oscillation stabilization wait time tLOCK 1 - 4 ms PLL input clock frequency fPLLI 4 - 8 MHz PLL oscillation clock frequency fCLKVCO 56 - 108 MHz Permitted VCO output frequency of PLL (CLKVCO) PLL phase jitter tPSKEW -5 - +5 ns For CLKMC (PLL input clock) ≥ 4MHz 14.4.6 For CLKMC = 4MHz Reset Input (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Reset input time Rejection of reset input time Symbol tRSTL Value Pin Name RSTX Min Unit Max 10 - s 1 - s tRSTL RSTX 0.2VCC Document Number: 002-04712 Rev. *F 0.2VCC Page 43 of 69 CY96620 Series 14.4.7 Power-on Reset Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Power on rise time Power off time Symbol tR tOFF Document Number: 002-04712 Rev. *F Pin Name Vcc Vcc Value Min 0.05 1 Typ - Unit Max 30 - ms ms Page 44 of 69 CY96620 Series 14.4.8 USART Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C, CL=50pF) Serial clock cycle time Symbo l tSCYC SCK   SOT delay time tSLOVI SOT  SCK  delay time tOVSHI SIN  SCK  setup time tIVSHI SCK   SIN hold time tSHIXI Serial clock "L" pulse width tSLSH SCKn Serial clock "H" pulse width tSHSL SCKn SCK   SOT delay time tSLOVE Parameter SIN  SCK  setup time tIVSHE SCK   SIN hold time tSHIXE SCK fall time SCK rise time tF tR Pin Name SCKn SCKn , SOTn SCKn , SOTn SCKn , SINn SCKn , SINn SCKn , SOTn SCKn , SINn SCKn , SINn SCKn SCKn Conditions Internal shift clock mode 4.5V  VCC 5.5V Min Max 4tCLKP1 - 2.7V  VCC  4.5V Min Max 4tCLKP1 - ns - 20 + 20 - 30 + 30 ns NtCLKP1 – 20* - NtCLKP1 – 30* - ns tCLKP1 + 45 - tCLKP1 + 55 - ns 0 - 0 - ns - ns - ns tCLKP1 + 10 tCLKP1 + 10 External shift clock mode - tCLKP1 + 10 tCLKP1 + 10 Unit - 2tCLKP1 + 45 - 2tCLKP1 + 55 ns tCLKP1/2 + 10 - tCLKP1/2 + 10 - ns tCLKP1 + 10 - tCLKP1 + 10 - ns - 20 20 - 20 20 ns ns Notes: • AC characteristic in CLK synchronized mode. • CL is the load capacity value of pins when testing. • Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. These parameters are shown in “CY96600 series HARDWARE MANUAL”. • tCLKP1 indicates the peripheral clock 1 (CLKP1), Unit: ns • These characteristics only guarantee the same relocate port number. For example, the combination of SCKn and SOTn_R is not guaranteed. *: Parameter N depends on tSCYC and can be calculated as follows: • If tSCYC = 2  k  tCLKP1, then N = k, where k is an integer > 2 • If tSCYC = (2  k + 1)  tCLKP1, then N = k + 1, where k is an integer > 1 Examples: tSCYC N 4  tCLKP1 2 5  tCLKP1, 6  tCLKP1 3 7  tCLKP1, 8  tCLKP1 4 … … Document Number: 002-04712 Rev. *F Page 45 of 69 CY96620 Series tSCYC VOH SCK VOL VOL tOVSHI tSLOVI VOH SOT VOL tIVSHI SIN tSHIXI VIH VIH VIL VIL Internal shift clock mode SCK tSHSL tSLSH VIH VIH VIL tF SOT VIL VIH tR tSLOVE VOH VOL SIN tIVSHE VIH VIL tSHIXE VIH VIL External shift clock mode Document Number: 002-04712 Rev. *F Page 46 of 69 CY96620 Series 14.4.9 External Input Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Parameter Input pulse width Symbol tINH, tINL Pin Name Min Value Max Unit Remarks Pnn_m General Purpose I/O ADTG_R A/D Converter trigger input TINn TTGn Reload Timer PPG trigger input Free-Running Timer input clock Input Capture Quadrature Position/Revolution Counter FRCKn INn AINn, BINn, ZINn INTn, INTn_R, INTn_R1 NMI_R 2tCLKP1 +200 (tCLKP1= 1/fCLKP1)* - ns 200 - ns External Interrupt Non-Maskable Interrupt *: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time except stop when in stop mode. tINH External input timing VIH tINL VIH VIL Document Number: 002-04712 Rev. *F VIL Page 47 of 69 CY96620 Series 14.4.10 I2C Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) High-Speed Mode*4 Min Max 0 400 kHz SCL clock frequency (Repeated) START condition hold time SDA   SCL  SCL clock "L" width SCL clock "H" width (Repeated) START condition setup time SCL   SDA  Data hold time SCL   SDA   Data setup time SDA    SCL  STOP condition setup time SCL   SDA  Bus free time between "STOP condition" and "START condition" fSCL Typical Mode Min Max 0 100 tHDSTA 4.0 - 0.6 - s tLOW tHIGH 4.7 4.0 - 1.3 0.6 - s s 4.7 - 0.6 - s 0 3.45*2 0 0.9*3 s tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - s tBUS 4.7 - 1.3 - s Pulse width of spikes which will be suppressed by input noise filter tSP 0 (1-1.5) tCLKP1*5 0 (1-1.5) tCLKP1*5 ns Parameter Symbol Conditions tSUSTA CL = 50pF, R = (Vp/IOL)*1 tHDDAT - *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal. *3: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250ns". *4: For use at over 100kHz, set the peripheral clock1 (CLKP1) to at least 6MHz. *5: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time. Unit SDA tSUDAT tSUSTA tBUS tLOW SCL tHDSTA Document Number: 002-04712 Rev. *F tHDDAT tHIGH tHDSTA tSP tSUSTO Page 48 of 69 CY96620 Series 14.5 A/D Converter 14.5.1 Electrical Characteristics for the A/D Converter Resolution - - - (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Value Unit Remarks Typ Max 10 bit Total error - - - 3.0 - + 3.0 LSB Nonlinearity error - - - 2.5 - + 2.5 LSB Differential Nonlinearity error - - - 1.9 - + 1.9 LSB Zero transition voltage VOT ANn Typ - 20 AVSS + 0.5LSB Typ + 20 mV Full scale transition voltage VFST ANn Typ - 20 Typ + 20 mV Compare time* - - Sampling time* - - 5.0 8.0 3.1 s s s s mA Parameter Power supply current Reference power supply current (between AVRH and AVSS ) Pin Name Symbol IA IAH AVCC IR IRH AN8, 9, 12, 13 AN16 to 23 CVIN Analog impedance RVIN ANn IAIN AN8, 9, 12, 13 AN16 to 23 Analog input voltage Reference voltage range Variation between channels 1.0 2.2 0.5 1.2 - AVRH - 1.5LSB 2.0 - - 3.3 A - 520 810 A A/D Converter active - - 1.0 A A/D Converter not operated - - 15.5 pF Normal outputs - - 17.4 pF High current outputs - - 1450 2700   4.5V ≤ AVCC ≤ 5.5V 2.7V ≤ AVCC < 4.5V - 1.0 - + 1.0 A - 3.0 - + 3.0 A AVRH Analog input capacity Analog port input current (during conversion) Min VAIN ANn AVSS - AVRH V - AVRH AVCC - 0.1 - AVCC V - ANn - - 4.0 LSB 4.5V ≤ ΑVCC ≤ 5.5V 2.7V ≤ ΑVCC  4.5V 4.5V ≤ ΑVCC ≤ 5.5V 2.7V ≤ ΑVCC  4.5V A/D Converter active A/D Converter not operated AVSS VAIN  AVCC, AVRH *: Time for each channel. Document Number: 002-04712 Rev. *F Page 49 of 69 CY96620 Series 14.5.2 Accuracy and Setting of the A/D Converter Sampling Time If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting the A/D conversion precision. To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time (Tsamp) depends on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and the AVCC voltage level. The following replacement model can be used for the calculation: MCU Rext Analog input RVIN Source Comparator Cext CVIN Sampling switch (During sampling:ON) Rext: External driving impedance Cext: Capacitance of PCB at A/D converter input CVIN: Analog input capacity (I/O, analog switch and ADC are contained) RVIN: Analog input impedance (I/O, analog switch and ADC are contained) The following approximation formula for the replacement model above can be used: Tsamp = 7.62 × (Rext × Cext + (Rext + RVIN) × CVIN) • Do not select a sampling time below the absolute minimum permitted value. (0.5s for 4.5V ≤ AVCC ≤ 5.5V, 1.2s for 2.7V ≤ AVCC < 4.5V) • If the sampling time cannot be sufficient, connect a capacitor of about 0.1F to the analog input pin. • A big external driving impedance also adversely affects the A/D conversion precision due to the pin input leakage current IIL (static current before the sampling switch) or the analog input leakage current IAIN (total leakage current of pin input and comparator during sampling). The effect of the pin input leakage current IIL cannot be compensated by an external capacitor. • The accuracy gets worse as |AVRH - AVSS| becomes smaller. Document Number: 002-04712 Rev. *F Page 50 of 69 CY96620 Series 14.5.3 Definition of A/D Converter Terms • Resolution • Nonlinearity error transition point • • • • : Analog variation that is recognized by an A/D converter. : Deviation of the actual conversion characteristics from a straight line that connects the zero (0b0000000000 ←→ 0b0000000001) to the full-scale transition point (0b1111111110 ←→ 0b1111111111). Differential nonlinearity error : Deviation from the ideal value of the input voltage that is required to change the output code by 1LSB. Total error : Difference between the actual value and the theoretical value. The total error includes zero transition error, full-scale transition error and nonlinearity error. Zero transition voltage : Input voltage which results in the minimum conversion value. Full scale transition voltage: Input voltage which results in the maximum conversion value. Nonlinearity error of digital output N = VNT - {1LSB  (N - 1) + VOT} 1LSB Differential nonlinearity error of digital output N = 1LSB = N VOT VFST VNT : : : : V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VOT 1022 A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0x3FE to 0x3FF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. Document Number: 002-04712 Rev. *F Page 51 of 69 CY96620 Series 1LSB (Ideal value) = Total error of digital output N = AVRH - AVSS 1024 [V] VNT - {1LSB  (N - 1) + 0.5LSB} 1LSB N : A/D converter digital output value. VNT : Voltage at which the digital output changes from 0x(N + 1) to 0xN. VOT (Ideal value) = AVSS + 0.5LSB[V] VFST (Ideal value) = AVRH - 1.5LSB[V] Document Number: 002-04712 Rev. *F Page 52 of 69 CY96620 Series 14.6 Low Voltage Detection Function Characteristics Detected voltage*1 VDL0 VDL1 VDL2 VDL3 VDL4 VDL5 VDL6 (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Value Conditions Unit Min Typ Max CILCR:LVL = 0000B 2.70 2.90 3.10 V CILCR:LVL = 0001B 2.79 3.00 3.21 V CILCR:LVL = 0010B 2.98 3.20 3.42 V CILCR:LVL = 0011B 3.26 3.50 3.74 V CILCR:LVL = 0100B 3.45 3.70 3.95 V CILCR:LVL = 0111B 3.73 4.00 4.27 V CILCR:LVL = 1001B 3.91 4.20 4.49 V Power supply voltage change rate*2 dV/dt - - 0.004 - + 0.004 V/s Hysteresis width VHYS CILCR:LVHYS=0 - - 50 mV CILCR:LVHYS=1 80 100 120 mV Stabilization time TLVDSTAB - - - 75 s Detection delay time td - - - 30 s Parameter Symbol *1: If the power supply voltage fluctuates within the time less than the detection delay time (td), there is a possibility that the low voltage detection will occur or stop after the power supply voltage passes the detection range. *2: In order to perform the low voltage detection at the detection voltage (VDLX), be sure to suppress fluctuation of the power supply voltage within the limits of the change ration of power supply voltage. Document Number: 002-04712 Rev. *F Page 53 of 69 CY96620 Series Voltage Vcc dV Detected Voltage dt VDLX max VDLX min Time RCR:LVDE ···Low voltage detection function enable Document Number: 002-04712 Rev. *F Low voltage detection function disable Stabilization time TLVDSTAB Low voltage detection function enable··· Page 54 of 69 CY96620 Series 14.7 Flash Memory Write/Erase Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Value Conditions Unit Remarks Min Typ Max Parameter Sector erase time Word (16-bit) write time Large Sector TA ≤ + 105°C - 1.6 7.5 s Small Sector - - 0.4 2.1 s Security Sector - - 0.31 1.65 s Large Sector TA ≤ + 105°C - 25 400 s Small Sector - - 25 400 s TA ≤ + 105°C - 5.11 25.05 s Chip erase time Includes write time prior to internal erase. Not including system-level overhead time. Includes write time prior to internal erase. Note: While the Flash memory is written or erased, shutdown of the external power (VCC) is prohibited. In the application system where the external power (VCC) might be shut down while writing or erasing, be sure to turn the power off by using a low voltage detection function. To put it concrete, change the external power in the range of change ration of power supply voltage (-0.004V/s to +0.004V/s) after the external power falls below the detection voltage (VDLX)*1. Write/Erase cycles and data hold time Write/Erase Cycles (Cycle) 1,000 10,000 100,000 *1: Data Hold Time (Year) 20 *2 10 *2 5 *2 See "Low Voltage Detection Function Characteristics". *2 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85C). Document Number: 002-04712 Rev. *F Page 55 of 69 CY96620 Series 15. Example Characteristics This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.  CY96F625 Run Mode (VCC = 5.5V) 100.00 PLL clock (32MHz) 10.00 ICC [mA] Main osc. (4MHz) 1.00 RC clock (2MHz) RC clock (100kHz) 0.10 Sub osc. (32kHz) 0.01 -50 0 50 100 150 TA [ºC] Sleep Mode 100.000 PLL clock (32MHz) 10.000 ICC [mA] (VCC = 5.5V) Main osc. (4MHz) 1.000 RC clock (2MHz) 0.100 RC clock (100kHz) 0.010 Sub osc. (32kHz) 0.001 -50 0 50 100 150 TA [ºC] Document Number: 002-04712 Rev. *F Page 56 of 69 CY96620 Series  CY96F625 Timer Mode (VCC = 5.5V) 10.000 PLL clock (32MHz) 1.000 ICC [mA] Main osc. (4MHz) 0.100 RC clock (2MHz) RC clock (100kHz) 0.010 Sub osc. (32kHz) 0.001 -50 0 50 100 150 TA [ºC] Stop Mode (VCC = 5.5V) 1.000 ICC [mA] 0.100 0.010 0.001 -50 0 50 100 150 TA [ºC] Document Number: 002-04712 Rev. *F Page 57 of 69 CY96620 Series  Used setting Selected Source Clock Mode Run mode Sleep mode PLL CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32MHz Main osc. CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4MHz RC clock fast CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2MHz RC clock slow CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100kHz Sub osc. CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32kHz CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32MHz Regulator in High Power Mode, (CLKB is stopped in this mode) CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4MHz Regulator in High Power Mode, (CLKB is stopped in this mode) CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2MHz Regulator in High Power Mode, (CLKB is stopped in this mode) CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100kHz Regulator in Low Power Mode, (CLKB is stopped in this mode) CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32kHz Regulator in Low Power Mode, (CLKB is stopped in this mode) CLKMC = 4MHz, CLKPLL = 32MHz (System clocks are stopped in this mode) Regulator in High Power Mode, FLASH in Power-down / reset mode CLKMC = 4MHz (System clocks are stopped in this mode) Regulator in High Power Mode, FLASH in Power-down / reset mode CLKMC = 2MHz (System clocks are stopped in this mode) Regulator in High Power Mode, FLASH in Power-down / reset mode CLKMC = 100kHz (System clocks are stopped in this mode) Regulator in Low Power Mode, FLASH in Power-down / reset mode CLKMC = 32 kHz (System clocks are stopped in this mode) Regulator in Low Power Mode, FLASH in Power-down / reset mode (All clocks are stopped in this mode) Regulator in Low Power Mode, FLASH in Power-down / reset mode PLL Main osc. RC clock fast RC clock slow Sub osc. Timer mode PLL Main osc. RC clock fast RC clock slow Sub osc. Stop mode Clock/Regulator and FLASH Settings stopped Document Number: 002-04712 Rev. *F Page 58 of 69 CY96620 Series 16. Ordering Information MCU with CAN Controller Part Number CY96F622RBPMC-GS-UJE1 CY96F622RBPMC-GS-UJE2 CY96F622RBPMC1-GS-UJE1 CY96F622RBPMC1-GS-UJE2 CY96F623RBPMC-GS-UJE1 CY96F623RBPMC-GS-UJE2 CY96F623RBPMC1-GS-UJE2 Flash Memory Flash A (64.5KB) Flash A (96.5KB) CY96F625RBPMC-GS-UJE1 CY96F625RBPMC-GS-UJE2 Flash A (160.5KB) CY96F625RBPMC1-GS-UJE1 CY96F625RBPMC1-GS-UJE2 *: For details about package, see "PACKAGE DIMENSION". MCU without CAN Controller Part Number CY96F622ABPMC-GS-UJE1 CY96F622ABPMC-GS-UJE2 CY96F622ABPMC1-GS-UJE1 CY96F622ABPMC1-GS-UJE2 CY96F622ABPMC1-GS-UJERE2 CY96F623ABPMC-GS-UJE1 CY96F623ABPMC-GS-UJE2 CY96F623ABPMC1-GS-UJE1 CY96F623ABPMC1-GS-UJE2 CY96F625ABPMC-GS-UJE2 Flash Memory Flash A (64.5KB) Flash A (96.5KB) Flash A CY96F625ABPMC1-GS-UJE1 (160.5KB) CY96F625ABPMC1-GS-UJE2 *: For details about package, see "PACKAGE DIMENSION". Document Number: 002-04712 Rev. *F Package* 64-pin plastic LQFP (LQG064) 64-pin plastic LQFP (LQD064) 64-pin plastic LQFP (LQG064) 64-pin plastic LQFP (LQD064) 64-pin plastic LQFP (LQG064) 64-pin plastic LQFP (LQD064) Package* 64-pin plastic LQFP (LQG064) 64-pin plastic LQFP (LQD064) 64-pin plastic LQFP (LQG064) 64-pin plastic LQFP (LQD064) 64-pin plastic LQFP (LQG064) 64-pin plastic LQFP (LQD064) Page 59 of 69 CY96620 Series 17. Package Dimension LQG064, 64 Lead Plastic Low Profile Quad Flat Package Package Type Package Code LQFP 64pin LQG064 D D1 48 4 5 7 33 33 32 49 48 32 49 17 64 E1 E 5 7 4 3 17 64 1 16 e 0.20 1 16 2 5 7 3 BOTTOM VIEW 0.10 C A-B D C A-B D b 0.13 C A-B D 8 TOP VIEW 2 A θ A A' 0.10 C SEATI N G PLA N E 0.2 5 L1 L 9 A1 10 c b SECTION A -A' SIDE VIEW SYM BOL DIM ENSION M IN. NOM . M AX. 1.70 A A1 0.00 0.20 b 0.27 c 0.09 0.32 0.37 0.20 D 14.00 BSC D1 12.00 BSC e 0.65 BSC E 14.00 BSC E1 12.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 θ 0° 8° 002-13881 ** PACKAGE OUTLINE, 64 LEAD LQFP 12.0X12.0X1.7 M M LQG064 REV** Document Number: 002-04712 Rev. *F Page 60 of 69 CY96620 Series LQD064, 64 Lead Plastic Low Profile Quad Flat Package Package Type Package Code LQFP 64pin LQD064 4 D D1 48 5 7 33 33 32 49 48 32 49 17 64 5 7 E1 E 4 3 6 17 64 1 16 e 1 16 2 5 7 3 BOTTOM VIEW 0.1 0 C A-B D 0.2 0 C A-B D b 0.0 8 C A-B D 8 TOP VIEW A 2 9 A A' 0.0 8 C SEATING PLAN E L1 0.25 L A1 c b SECTION A-A' 10 SIDE VIEW SYM BOL DIM ENSIONS M IN. NOM . M AX. A A1 1. 70 0.00 0.20 b 0.15 0.2 c 0.09 0.20 D 12.00 BSC. D1 10.00 BSC. e 0.50 BSC E 12.00 BSC. E1 10.00 BSC. L 0.45 0.60 0.75 L1 0.30 0.50 0.70 002-11499 ** PACKAGE OUTLINE, 64 LEAD LQFP 10.0X10.0X1.7 M M LQD064 Rev** Document Number: 002-04712 Rev. *F Page 61 of 69 CY96620 Series 18. Major Changes Spansion Publication Number: MB96620_DS704-00008 Page Section Revision 2.0 Features 4 25 to 28 Handling Precautions Electrical Characteristics 3. Dc Characteristics (1) Current Rating 36 37 38 49 51 4. Ac Characteristics (10) I2c Timing 5. A/D Converter (2) Accuracy And Setting Of The A/D Converter Sampling Time 7. Flash Memory Write/Erase Characteristics 56 Document Number: 002-04712 Rev. *F Change Results Changed the description of “External Interrupts” Interrupt mask and pending bit per channel → Interrupt mask bit per channel Added a section Changed the Conditions for ICCSRCH CLKS1/2 = CLKB = CLKP1/2 = CLKRC = 2MHz, → CLKS1/2 = CLKP1/2 = CLKRC = 2MHz, Changed the Conditions for ICCSRCL CLKS1/2 = CLKB = CLKP1/2 = CLKRC = 100kHz → CLKS1/2 = CLKP1/2 = CLKRC = 100kHz Changed the Conditions for ICCTPLL PLL Timer mode with CLKP1 = 32MHz → PLL Timer mode with CLKPLL = 32MHz Changed the Value of “Power supply current in Timer modes” ICCTPLL Typ: 2480μA → 1800μA (TA = +25°C) Max: 2710μA → 2245μA (TA = +25°C) Max: 3985μA → 3165μA (TA = +105°C) Max: 4830μA → 3975μA (TA = +125°C) Changed the Conditions for ICCTRCL RC Timer mode with CLKRC = 100kHz, SMCR:LPMSS = 0 (CLKPLL, CLKMC and CLKSC stopped) → RC Timer mode with CLKRC = 100kHz (CLKPLL, CLKMC and CLKSC stopped) Changed the annotation *2 Power supply for "On Chip Debugger" part is not included. Power supply current in Run mode does not include Flash Write / Erase current. → The current for "On Chip Debugger" part is not included. Added parameter, “Noise filter” and an annotation *5 for it Added tSP to the figure Deleted the unit “[Min]” from approximation formula of Sampling time Changed the condition (VCC = AVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) → (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 125°C) Page 62 of 69 CY96620 Series Page Section Electrical Characteristics 7. Flash Memory Write/Erase Characteristics 56 Ordering Information 60 Revision 2.1 Rev. *B 1. Product Lineup 5, 7, 59, 3. Pin Assignment 60, 61, 16. Ordering Information 62 17. Package Dimension 59 16. Ordering Information Document Number: 002-04712 Rev. *F Change Results Changed the Note While the Flash memory is written or erased, shutdown of the external power (VCC) is prohibited. In the application system where the external power (VCC) might be shut down while writing, be sure to turn the power off by using an external voltage detector. → While the Flash memory is written or erased, shutdown of the external power (VCC) is prohibited. In the application system where the external power (VCC) might be shut down while writing or erasing, be sure to turn the power off by using a low voltage detection function. Deleted the Part number MCU with CAN controller MB96F622RBPMC-GTE2 MB96F622RBPMC1-GTE2 MB96F623RBPMC-GTE2 MB96F623RBPMC1-GTE2 MB96F625RBPMC-GTE2 MB96F625RBPMC1-GTE2 MCU without CAN controller MB96F622ABPMC-GTE2 MB96F622ABPMC1-GTE2 MB96F623ABPMC-GTE2 MB96F623ABPMC1-GTE2 MB96F625ABPMC-GTE2 MB96F625ABPMC1-GTE2 Company name and layout design change Package description modified to JEDEC description. FPT-64P-M23 → LQG064 FPT-64P-M24 → LQD064 Added the following part number. MB96F622RBPMC-GS-UJE1 MB96F622RBPMC-GS-UJE2 MB96F622RBPMC1-GS-UJE1 MB96F622RBPMC1-GS-UJE2 MB96F623RBPMC-GS-UJE1 MB96F623RBPMC-GS-UJE2 MB96F623RBPMC1-GS-UJE1 MB96F623RBPMC1-GS-UJE2 MB96F625RBPMC-GS-UJE1 MB96F625RBPMC-GS-UJE2 MB96F625RBPMC1-GS-UJE1 MB96F625RBPMC1-GS-UJE2 MB96F622ABPMC-GS-UJE1 MB96F622ABPMC-GS-UJE2 MB96F622ABPMC1-GS-UJE1 MB96F622ABPMC1-GS-UJE2 MB96F623ABPMC-GS-UJE1 MB96F623ABPMC-GS-UJE2 MB96F623ABPMC1-GS-UJE1 MB96F623ABPMC1-GS-UJE2 MB96F625ABPMC-GS-UJE1 MB96F625ABPMC-GS-UJE2 MB96F625ABPMC1-GS-UJE1 MB96F625ABPMC1-GS-UJE2 Page 63 of 69 CY96620 Series Page Rev. *C 11 Section 5. Pin Circuit Type Change Results The shading parts below revised I/O circuit type and Pin name. (Error) 33 I/O Circuit Type* N P04_5 / SCL0 34 O DEBUG I/F 35 H P17_0 36 C MD 37 A X0 38 A X1 39 Supply Vss 40 B P04_0 / X0A 41 B P04_1 / X1A 42 C RSTX 43 J P11_7 / SEG3 / IN0_R 44 J P11_0 / COM0 45 J P11_1 / COM1 / PPG0_R 46 J P11_2 / COM2 / PPG1_R 47 J P11_3 / COM3 / PPG2_R 48 J 49 J 50 J 51 J 52 J 53 J 54 J P12_0 / SEG4 / IN1_R P12_1 / SEG5 / TIN1_R / PPG0_B P12_2 / SEG6 / TOT1_R / PPG1_B P12_4 / SEG8 P12_5 / SEG9 / TIN2_R / PPG2_B P12_6 / SEG10 / TOT2_R / PPG3_B P12_7 / SEG11 / INT1_R 55 J P01_1 / SEG21 / CKOT1 56 J P01_3 / SEG23 57 L P03_0 / SEG36 / V0 58 L P03_1 / SEG37 / V1 59 L P03_2 / SEG38 / V2 60 L P03_3 / SEG39 / V3 61 M P03_4 / RX0 / INT4 62 H P03_5 / TX0 63 H P03_6 / INT0 / NMI 64 Supply Vcc Pin No. Document Number: 002-04712 Rev. *F Pin Name Page 64 of 69 CY96620 Series 11 5. Pin Circuit Type (Correct) Pin No. I/O Circuit Type* Pin Name 33 H P01_1 / TOT1 / CKOTX1 / OUT1_R 34 H P01_2 / INT11_R 35 H P01_3 36 H P01_4 / PPG4_B 37 M P01_5 / SIN2_R / INT7_R 38 H P01_6 / SOT2_R / PPG6_B 39 M P01_7 / SCK2_R / PPG7_B 40 H P02_0 / PPG12 / CKOT1_R 41 H P02_1 42 H P02_2 / ZIN0 / PPG14 / CKOT0_R 43 H P02_3 44 H P02_4 / AIN0 / IN0 / TTG0 45 C RSTX 46 A X1 47 A X0 48 Supply Vss 49 Supply Vcc 50 F C 51 H P02_5 / BIN0 / IN1 / TTG1 / ADTG_R 52 N P04_4 / SDA0 / FRCK0 53 N P04_5 / SCL0 / FRCK1 54 K 55 K 56 M P03_2 / INT10_R / RX2 57 H P03_3 / TX2 58 K P03_4 / OUT4 / AN28 59 K P03_5 / OUT5 / AN29 60 K P03_6 / ZIN1 / OUT6 / AN30 61 K P03_7 / OUT7 / AN31 62 K P06_0 / AN0 / PPG0 63 K P06_1 / AN1 / PPG1 64 Supply AVcc P03_0 / AIN1 / IN4 / TTG4 / TTG12 / AN24 P03_1 / BIN1 / IN5 / TTG5 / TTG13 / AN25 Rev. *D Document Number: 002-04712 Rev. *F Page 65 of 69 CY96620 Series Page P59 Section 16. Ordering Information P60 Change Results Deleted the Part number MCU with CAN controller MB96F623RBPMC1-GS-UJE1 Deleted the Part number MCU without CAN controller MB96F625ABPMC-GS-UJE1 Rev. *E - Marketing Part Numbers changed from an MB prefix to a CY prefix. 59 to 60 16. Ordering Information Revised Marketing Part Numbers as follows: Before) MCU with CAN Controller MB96F622RBPMC-GSE1 MB96F622RBPMC-GS-UJE1 MB96F622RBPMC-GSE2 MB96F622RBPMC-GS-UJE2 MB96F622RBPMC-GTE1 MB96F622RBPMC1-GSE1 MB96F622RBPMC1-GS-UJE1 MB96F622RBPMC1-GSE2 MB96F622RBPMC-1-GS-UJE2 MB96F622RBPMC1-GTE1 MB96F623RBPMC-GSE1 MB96F623RBPMC-GS-UJE1 MB96F623RBPMC-GSE2 MB96F623RBPMC-GS-UJE2 MB96F623RBPMC-GTE1 MB96F623RBPMC1-GSE1 MB96F623RBPMC1-GSE2 MB96F623RBPMC1-GS-UJE2 MB96F623RBPMC1-GTE1 MB96F625RBPMC-GSE1 MB96F625RBPMC-GS-UJE1 MB96F625RBPMC-GSE2 MB96F625RBPMC-GS-UJE2 MB95F625RBPMC-GTE1 MB96F625RBPMC1-GSE1 MB96F625RBPMC1-GS-UJE1 MB96F625RBPMC1-GSE2 MB96F625RBPMC1-GS-UJE2 MB96F625RBPMC1-GTE1 MCU without CAN Controller MB96F622ABPMC-GSE1 MB96F622ABPMC-GS-UJE1 MB96F622ABPMC-GSE2 MB96F622ABPMC-GS-UJE2 MB96F622ABPMC-GTE1 MB96F622ABPMC1-GSE1 MB96F622ABPMC1-GSUJE1 MB96F622ABPMC1-GSE2 MB96F622ABPMC1-GS-UJE2 MB96F622ABPMC1-GTE1 Document Number: 002-04712 Rev. *F Page 66 of 69 CY96620 Series Page Section Change Results 59 to 60 16. Ordering Information MB96F623ABPMC-GSE1 MB96F623ABPMC-GS-UJE1 MB96F623ABPMC-GSE2 MB96F623ABPMC-GS-UJE2 MB96F623ABPMC-GTE1 MB96F623ABPMC1-GSE1 MB96F623ABPMC1-GS-UJE1 MB96F623ABPMC1-GSE2 MB96F623ABPMC1-GS-UJE2 MB96F623ABPMC1-GTE1 MB96F625ABPMC-GSE1 MB96F625ABPMC-GSE2 MB96F625ABPMC-GS-UJE2 59 16. Ordering Information After) MCU with CAN Controller CY96F622RBPMC-GS-UJE1 CY96F622RBPMC-GS-UJE2 CY96F622RBPMC1-GS-UJE1 CY96F622RBPMC1-GS-UJE2 CY96F623RBPMC-GS-UJE1 CY96F623RBPMC-GS-UJE2 CY96F623RBPMC1-GS-UJE2 CY96F625RBPMC-GS-UJE1 CY96F625RBPMC-GS-UJE2 CY96F625RBPMC1-GS-UJE1 CY96F625RBPMC1-GS-UJE2 MCU without CAN Controller CY96F622ABPMC-GS-UJE1 CY96F622ABPMC-GS-UJE2 CY96F622ABPMC1-GS-UJE1 CY96F622ABPMC1-GS-UJE2 CY96F622ABPMC1-GS-UJERE2 CY96F623ABPMC-GS-UJE1 CY96F623ABPMC-GS-UJE2 CY96F623ABPMC1-GS-UJE1 CY96F623ABPMC1-GS-UJE2 CY96F625ABPMC-GS-UJE2 CY96F625ABPMC1-GS-UJE1 CY96F625ABPMC1-GS-UJE2 Document Number: 002-04712 Rev. *F Page 67 of 69 CY96620 Series Document History Document Title: CY96620 Series, F2MC-16FX 16-Bit Microcontroller Document Number: 002-04712 Revision ECN Orig. of Change ** - KSUN Submission Date Description of Change 01/31/2014 Migrated to Cypress and assigned document number 002-04712. No change to document contents or format. *A 5137624 KSUN 02/17/2016 Updated to Cypress template. *B 5735123 KUME 05/15/2017 Updated Ordering Information. Updated Package Dimension. For details, please see 18. Major Changes. *C 5749379 MIYH 05/25/2017 Updated Pin Circuit Type: Updated details in “I/O Circuit Type” and “Pin Name” columns. For details, please see 18. Major Changes. *D 5809040 MIYH 07/11/2017 Updated Ordering Information. For details, please see 18. Major Changes. *E 5978310 MIYH 2 11/30/2017 Updated Document Title to read as “CY96620 Series, F MC-16FX 16-Bit Microcontroller”. Replaced MB96620 Series with CY96620 Series in all instances across the document. Changed the prefix of all MPNs from MB to CY in all instances across the document. Updated Ordering Information. For details, please see 18. Major Changes. *F 6599972 KSUN Document Number: 002-04712 Rev. *F 06/20/2019 Updated to new template. Page 68 of 69 CY96620 Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products ARM® Cortex® Microcontrollers Automotive Clocks & Buffers Interface Internet of Things Memory cypress.com/arm cypress.com/automotive cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Touch Sensing USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic cypress.com/touch cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2014-2019. 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It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device” means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-04712 Rev. *F June 20, 2019 Page 69 of 69