Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY9A130N Series
32-bit ARM® Cortex®-M3 based
FM3 Microcontroller
The CY9A130N Series are highly integrated 32-bit microcontrollers that dedicated for embedded controllers with low-power
consumption mode and competitive cost.
The CY9A130N Series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral
functions such as Motor Control Timers, ADCs, DACs and Communication Interfaces (UART, CSIO, I2C).
The products which are described in this data sheet are placed into TYPE7 product categories in FM3 Family Peripheral Manual .
Features
32-bit ARM Cortex-M3 Core
[I2C]
Processor version: r2p1
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
Up to 20 MHz frequency operation
supported
Integrated Nested Vectored Interrupt Controller (NVIC): 1
channel NMI (non-maskable interrupt) and
32 channels' peripheral interrupts and 8 priority levels
A/D Converter (Max 16 channels)
24-bit System timer (Sys Tick): System timer for OS task
management
[12-bit A/D Converter]
Successive Approximation type
Conversion time: Min 1.0 μs
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16steps, for Priority conversion: 4 steps)
On-chip Memories
[Flash memory]
Up to 128 Kbytes
Read cycle: 0 wait-cycle
D/A Converter (Max 2 channels)
Security function for code protection
R-2R type
[SRAM]
This series contains a total of up to 16 Kbyte on-chip SRAM
10-bit resolution
that is connected to System bus of Cortex-M3 core.
Base Timer (Max 8 channels)
SRAM1: Up to 16 Kbytes
Operation mode is selectable from the followings for each
Multi-function Serial Interface (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
channel.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
UART
16-/32-bit PWC timer
CSIO
I2 C
General-Purpose I/O Port
[UART]
This series can use its pins as general-purpose I/O ports when
Full duplex double buffer
they are not used for peripherals. Moreover, the port relocate
Selection with or without parity supported
function is built in. It can set which I/O port the peripheral
Built-in dedicated baud rate generator
function can be allocated to.
External clock available as a serial clock
Capable of pull-up control per pin
Various error detection functions available (parity errors,
framing errors, and overrun errors)
Capable of reading pin level directly
[CSIO]
Up to 84 high-speed general-purpose I/O Ports@100 pin
Package
Some ports are 5V tolerant I/O
Full duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
Cypress Semiconductor Corporation
Document Number: 002-05644 Rev. *C
•
Built-in the port relocate function
See List of Pin Functions and I/O Circuit Type to confirm the
corresponding pins.
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 17, 2019
CY9A130N Series
Multi-function Timer
External Interrupt Controller Unit
The Multi-function timer is composed of the following blocks.
Up to 16 external interrupt input pins
16-bit free-run timer × 3 ch.
Include one non-maskable interrupt (NMI) input pin
Input capture × 4 ch.
Output compare × 6 ch.
Watchdog Timer (2 channels)
A/D activating compare × 3 ch.
A watchdog timer can generate interrupts or a reset when a
Waveform generator × 3 ch.
time-out value is reached.
16-bit PPG timer × 3 ch.
IGBT mode is contained
This series consists of two different watchdogs, a Hardware
The following function can be used to achieve the motor
The Hardware watchdog timer is clocked by the built-in
control.
Low-speed CR oscillator. Therefore, the Hardware watchdog is
PWM signal output function
active in any low-power consumption mode except RTC, Stop,
DC chopper waveform output function
Deep Standby RTC and Deep Standby Stop modes.
Dead time function
Input capture function
A/D convertor activate function
watchdog and a Software watchdog.
Clock and Reset
[Clocks]
DTIF (Motor emergency stop) interrupt function
Selectable from five clock sources (2 external oscillators, 2
HDMI-CEC/Remote Control Receiver (Up to 2
channels)
Main Clock:
4 MHz to 20 MHz
Sub Clock:
32.768 kHz
HDMI- CEC receiver / Remote control receiver
Operating modes supporting the following standards
can be selected
SIRCS
NEC/Association for Electric Home Appliances
HDMI-CEC
Capable of adjusting detection timings for start bit and
data bit
Equipped with noise filter
Built-in High-speed CR Clock:
4 MHz
Built-in Low-speed CR Clock:
100 kHz
HDMI-CEC transmitter
Header block automatic transmission by judging Signal
free
Generating status interrupt by detecting Arbitration lost
Generating START, EOM, ACK automatically to output
CEC transmission by setting 1 byte data
Generating transmission status interrupt when
transmitting 1 block (1 byte data and EOM/ACK)
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
built-in CR oscillators, and Main PLL).
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
If external clock failure (clock stop) is detected, reset is
asserted.
00 to 99.
If external frequency anomaly is detected, interrupt or reset
is asserted.
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Low-Voltage Detector (LVD)
Timer interrupt function after set time or each set time.
When the voltage falls below the voltage that has been set,
Capable of rewriting the time with continuing the time count.
Low-Voltage Detector generates an interrupt or reset.
Leap year automatic count is available.
LVD1: error reporting via interrupt
This Series includes 2-stage monitoring of voltage on the VCC.
LVD2: auto-reset operation
Document Number: 002-05644 Rev. *C
Page 2 of 95
CY9A130N Series
Low-Power Consumption Mode
Debug
Six low-power consumption modes supported.
Serial Wire JTAG Debug Port (SWJ-DP)
Sleep
Timer
RTC
Power Supply
Wide range voltage: VCC = 1.8 V to 5.5 V
Stop
Deep Standby RTC
Deep Standby Stop
The back up register is 16 bytes.
Document Number: 002-05644 Rev. *C
Page 3 of 95
CY9A130N Series
Table of Contents
1.
Product Lineup ............................................................................................................................................................... 5
2.
Packages......................................................................................................................................................................... 6
3.
Pin Assignment .............................................................................................................................................................. 7
4.
List of Pin Functions .................................................................................................................................................... 10
5.
I/O Circuit Type ............................................................................................................................................................. 30
6.
Handling Precautions .................................................................................................................................................. 35
6.1
Precautions for Product Design ................................................................................................................................... 35
6.2
Precautions for Package Mounting .............................................................................................................................. 36
6.3
Precautions for Use Environment ................................................................................................................................ 37
7.
Handling Devices ......................................................................................................................................................... 38
8.
Block Diagram .............................................................................................................................................................. 40
9.
Memory Size ................................................................................................................................................................. 41
9.1
Memory Map ............................................................................................................................................................... 41
10. Pin Status in Each CPU State ...................................................................................................................................... 45
11. Electrical Characteristics ............................................................................................................................................ 52
11.1 Absolute Maximum Ratings ......................................................................................................................................... 52
11.2 Recommended Operating Conditions ......................................................................................................................... 53
11.3 DC Characteristics ...................................................................................................................................................... 54
11.3.1 Current Rating .............................................................................................................................................................. 54
11.3.2 Pin Characteristics ....................................................................................................................................................... 57
11.4 AC Characteristics ....................................................................................................................................................... 58
11.4.1 Main Clock Input Characteristics .................................................................................................................................. 58
11.4.2 Sub Clock Input Characteristics ................................................................................................................................... 59
11.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 59
11.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL) ...................................... 60
11.4.5 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock
of the Main PLL) ........................................................................................................................................................... 60
11.4.6 Reset Input Characteristics .......................................................................................................................................... 61
11.4.7 Power-on Reset Timing ................................................................................................................................................ 61
11.4.8 Base Timer Input Timing .............................................................................................................................................. 62
11.4.9 CSIO/UART Timing ...................................................................................................................................................... 63
11.4.10 External Input Timing ................................................................................................................................................ 72
11.4.11 I2C Timing ................................................................................................................................................................. 73
11.4.12 JTAG Timing............................................................................................................................................................. 74
11.5 12-bit A/D Converter .................................................................................................................................................... 75
11.6 10-bit D/A Converter .................................................................................................................................................... 78
11.7 Low-Voltage Detection Characteristics ........................................................................................................................ 79
11.7.1 Low-Voltage Detection Reset ....................................................................................................................................... 79
11.7.2 Interrupt of Low-Voltage Detection ............................................................................................................................... 80
11.8 Flash Memory Write/Erase Characteristics ................................................................................................................. 82
11.9 Return Time from Low-Power Consumption Mode ...................................................................................................... 83
11.9.1 Return Factor: Interrupt/WKUP .................................................................................................................................... 83
11.9.2 Return Factor: Reset .................................................................................................................................................... 85
12. Ordering Information ................................................................................................................................................... 87
13. Package Dimensions ................................................................................................................................................... 88
14. Major Changes ............................................................................................................................................................. 92
Document History ................................................................................................................................................................. 94
Sales, Solutions, and Legal Information ............................................................................................................................. 95
Document Number: 002-05644 Rev. *C
Page 4 of 95
CY9A130N Series
1. Product Lineup
Memory Size
Product name
On-chip Flash memory
On-chip SRAM
SRAM1
CY9AF131M/N
CY9AF132M/N
64 Kbytes
128 Kbytes
12 Kbytes
16 Kbytes
Function
CY9AF131M
CY9AF132M
Product name
Pin count
CPU
80
100
Cortex-M3
Freq.
20 MHz
Power supply voltage range
1.8 V to 5.5 V
Multi-function Serial Interface
(UART/CSIO/I2C)
8 ch. (Max)
Base Timer
(PWC/ Reload timer/PWM/PPG)
8 ch. (Max)
MFTimer
CY9AF131N
CY9AF132N
A/D activation compare
3 ch.
Input capture
4 ch.
Free-run timer
3 ch.
Output compare
6 ch.
Waveform generator
3 ch.
PPG
(IGBT mode)
3 ch.
1 unit (Max)
HDMI-CEC/ Remote Control Receiver
2 ch. (Max)
Real-time clock (RTC)
1 unit
Watchdog timer
1 ch. (SW) + 1 ch. (HW)
External Interrupts
11 pins (Max) + NMI × 1
16 pins (Max) + NMI × 1
General-purpose I/O ports
67 pins (Max)
84 pins (Max)
12-bit A/D converter
12 ch. (1 unit)
16 ch. (1 unit)
10-bit D/A converter
2 ch. (Max)
CSV (Clock Super Visor)
Yes
LVD (Low-Voltage Detector)
2 ch.
Built-in CR
High-speed
4 MHz
Low-speed
100 kHz
Debug Function
SWJ-DP
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use
the port relocate function of the I/O port according to your function use.
See 11.Electrical Characteristics 11.4.AC Characteristics 11.4.3.Built-in CR Oscillation Characteristics for accuracy of built-in
CR.
Document Number: 002-05644 Rev. *C
Page 5 of 95
CY9A130N Series
2. Packages
Product name
Package
CY9AF131M
CY9AF132M
CY9AF131N
CY9AF132N
LQFP:
LQH080 (0.5 mm pitch)
-
LQFP:
LQJ080 (0.65 mm pitch)
-
LQFP:
LQI100 (0.5 mm pitch)
-
QFP:
PQH100 (0.65 mm pitch)
-
: Supported
Note:
−
See 13 Package Dimensions for detailed information on each package.
Document Number: 002-05644 Rev. *C
Page 6 of 95
CY9A130N Series
3. Pin Assignment
LQH080/LQJ080
P02 / TDI
P01 / TCK / SWCLK
P00 / TRSTX
63
62
61
P04 / TDO / SWO
P03 / TMS / SWDIO
66
65
64
P0B / SOT4_0 / TIOB6_1
P0A / SIN4_0 / INT00_2
P07 / ADTG_0
68
67
P0D / RTS4_0 / TIOA3_2
P0C / SCK4_0 / TIOA6_1
71
70
69
P63 / INT03_0
P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0
P0E / CTS4_0 / TIOB3_2
73
72
P61 / SOT5_0 / TIOB2_2 / DTTI0X_2
P62 / SCK5_0 / ADTG_3
76
75
74
P81 / SOT7_2
P80 / SIN7_2
P60 / SIN5_0 / TIOA2_2 / INT15_1 / WKUP3 / CEC1
78
77
VSS
P82 / SCK7_2
80
79
(TOP VIEW)
VCC
1
60
P20 / INT05_0 / CROUT_0
P50 / SIN3_1 / INT00_0
2
59
P21 / SIN0_0 / INT06_1 / WKUP2
P51 / SOT3_1 / INT01_0
3
58
P22 / SOT0_0 / TIOB7_1
P52 / SCK3_1 / INT02_0
4
57
P23 / SCK0_0 / TIOA7_1
P53 / SIN6_0 / TIOA1_2 / INT07_2
5
56
P1B / AN11 / SOT4_1 / IC01_1
P54 / SOT6_0 / TIOB1_2
6
55
P1A / AN10 / SIN4_1 / INT05_1 / IC00_1
P55 / SCK6_0 / ADTG_1
7
54
P19 / AN09 / SCK2_2
P56 / INT08_2
8
53
P18 / AN08 / SOT2_2
P30 / TIOB0_1 / INT03_2
9
52
AVSS
P31 / SCK6_1 / TIOB1_1 / INT04_2
10
51
AVRH
P32 / SOT6_1 / TIOB2_1 / INT05_2
11
50
AVCC
P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6
12
49
P17 / AN07 / SIN2_2 / INT04_1
P39 / DTTI0X_0 / ADTG_2
13
48
P16 / AN06 / SCK0_1
P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2
14
47
P15 / AN05 / SOT0_1 / IC03_2
P3B / TIOA1_1 / RTO01_0
15
46
P14 / AN04 / SIN0_1 / INT03_1 / IC02_2
P3C / TIOA2_1 / RTO02_0
16
45
P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1
P3D / TIOA3_1 / RTO03_0
17
44
P12 / AN02 / SOT1_1 / IC00_2
P3E / TIOA4_1 / RTO04_0
18
43
P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1
P3F / TIOA5_1 / RTO05_0
19
42
P10 / AN00
VSS
20
41
VCC
38
39
40
PE2 / X0
PE3 / X1
VSS
35
36
37
MD0
P4D / SOT7_1 / TIOB4_0 / DA0
PE0 / MD1
33
34
P4C / SCK7_1 / TIOB3_0 / CEC0
P4B / TIOB2_0 / IGTRG
P4E / SIN7_1 / TIOB5_0 / INT06_2 / DA1
30
31
32
P4A / SCK3_2 / TIOB1_0
28
29
INITX
P48 / SIN3_2 / INT14_1
P49 / SOT3_2 / TIOB0_0
25
26
27
P46 / X0A
P47 / X1A
23
24
C
VSS
VCC
21
22
P44 / TIOA4_0
P45 / TIOA5_0
LQFP - 80
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05644 Rev. *C
Page 7 of 95
CY9A130N Series
LQI100
P02 / TDI
P01 / TCK / SWCLK
P00 / TRSTX
VCC
79
78
77
76
P05 / SIN4_2 / TIOA5_2 / INT00_1
P04 / TDO / SWO
P03 / TMS / SWDIO
82
81
80
P07 / SCK4_2 / ADTG_0
P06 / SOT4_2 / TIOB5_2 / INT01_1
84
83
P0A / SIN4_0 / INT00_2
P09 / RTS4_2 / TIOB0_2
P08 / CTS4_2 / TIOA0_2
87
86
85
P0D / RTS4_0 / TIOA3_2
P0C / SCK4_0 / TIOA6_1
P0B / SOT4_0 / TIOB6_1
90
89
88
P63 / INT03_0
P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0
P0E / CTS4_0 / TIOB3_2
93
92
91
P60 / SIN5_0 / TIOA2_2 / INT15_1 / WKUP3 / CEC1
P61 / SOT5_0 / TIOB2_2 / DTTI0X_2
P62 / SCK5_0 / ADTG_3
96
95
94
P82 / SCK7_2
P81 / SOT7_2
P80 / SIN7_2
99
98
97
100 VSS
(TOP VIEW)
VCC
1
75
VSS
P50 / SIN3_1 / INT00_0
2
74
P20 / INT05_0 / CROUT_0
P51 / SOT3_1 / INT01_0
3
73
P21 / SIN0_0 / INT06_1 / WKUP2
P52 / SCK3_1 / INT02_0
4
72
P22 / SOT0_0 / TIOB7_1
P53 / SIN6_0 / TIOA1_2 / INT07_2
5
71
P23 / SCK0_0 / TIOA7_1 / RTO00_1
P54 / SOT6_0 / TIOB1_2
6
70
P1F / AN15 / FRCK0_1 / ADTG_5
P55 / SCK6_0 / ADTG_1
7
69
P1E / AN14 / RTS4_1 / DTTI0X_1
P56 / INT08_2
8
68
P1D / AN13 / CTS4_1 / IC03_1
P30 / TIOB0_1 / INT03_2
9
67
P1C / AN12 / SCK4_1 / IC02_1
P31 / SCK6_1 / TIOB1_1 / INT04_2
10
66
P1B / AN11 / SOT4_1 / IC01_1
P32 / SOT6_1 / TIOB2_1 / INT05_2
11
65
P1A / AN10 / SIN4_1 / INT05_1 / IC00_1
P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6
12
64
P19 / AN09 / SCK2_2
LQFP - 100
P34 / TIOB4_1 / FRCK0_0
13
63
P18 / AN08 / SOT2_2
P35 / TIOB5_1 / INT08_1 / IC03_0
14
62
AVSS
P36 / SIN5_2 / INT09_1 / IC02_0
15
61
AVRH
47
48
49
50
MD0
PE2 / X0
VSS
PE0 / MD1
PE3 / X1
44
45
46
P4D / SOT7_1 / TIOB4_0 / DA0
P4E / SIN7_1 / TIOB5_0 / INT06_2 / DA1
42
43
P4B / TIOB2_0 / IGTRG
P4C / SCK7_1 / TIOB3_0 / CEC0
39
40
41
P48 / SIN3_2 / INT14_1
P49 / SOT3_2 / TIOB0_0
P4A / SCK3_2 / TIOB1_0
36
37
VCC
38
51
INITX
25
P46 / X0A
P10 / AN00
VSS
P47 / X1A
52
33
24
34
P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1
P3F / TIOA5_1 / RTO05_0
35
P12 / AN02 / SOT1_1 / IC00_2
53
C
54
23
VSS
22
P3E / TIOA4_1 / RTO04_0
VCC
P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1
P3D / TIOA3_1 / RTO03_0
30
55
31
21
32
P14 / AN04 / SIN0_1 / INT03_1 / IC02_2
P3C / TIOA2_1 / RTO02_0
P44 / TIOA4_0
P15 / AN05 / SOT0_1 / IC03_2
56
P45 / TIOA5_0
57
20
P43 / TIOA3_0 / ADTG_7
19
P3B / TIOA1_1 / RTO01_0
29
P16 / AN06 / SCK0_1
P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2
P42 / TIOA2_0
58
26
18
27
P17 / AN07 / SIN2_2 / INT04_1
P39 / DTTI0X_0 / ADTG_2
28
AVCC
59
VCC
60
17
P40 / TIOA0_0 / INT12_1
16
P41 / TIOA1_0 / INT13_1
P37 / SOT5_2 / INT10_1 / IC01_0
P38 / SCK5_2 / INT11_1 / IC00_0
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Document Number: 002-05644 Rev. *C
Page 8 of 95
CY9A130N Series
PQH100
VCC
VSS
P20 / INT05_0 / CROUT_0
P21 / SIN0_0 / INT06_1 / WKUP2
54
53
52
51
P02 / TDI
P01 / TCK / SWCLK
P00 / TRSTX
57
56
55
P05 / SIN4_2 / TIOA5_2 / INT00_1
P04 / TDO / SWO
P03 / TMS / SWDIO
60
59
58
P08 / CTS4_2 / TIOA0_2
P07 / SCK4_2 / ADTG_0
P06 / SOT4_2 / TIOB5_2 / INT01_1
63
62
61
P0B / SOT4_0 / TIOB6_1
P0A / SIN4_0 / INT00_2
P09 / RTS4_2 / TIOB0_2
66
65
64
P0D / RTS4_0 / TIOA3_2
P0C / SCK4_0 / TIOA6_1
68
67
P63 / INT03_0
P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0
P0E / CTS4_0 / TIOB3_2
71
70
69
P60 / SIN5_0 / TIOA2_2 / INT15_1 / WKUP3 / CEC1
P61 / SOT5_0 / TIOB2_2 / DTTI0X_2
P62 / SCK5_0 / ADTG_3
74
73
72
P82 / SCK7_2
P81 / SOT7_2
P80 / SIN7_2
77
76
75
P50 / SIN3_1 / INT00_0
VCC
VSS
80
79
78
(TOP VIEW)
P51 / SOT3_1 / INT01_0
81
50
P22 / SOT0_0 / TIOB7_1
P52 / SCK3_1 / INT02_0
82
49
P23 / SCK0_0 / TIOA7_1 / RTO00_1
P53 / SIN6_0 / TIOA1_2 / INT07_2
83
48
P1F / AN15 / FRCK0_1 / ADTG_5
P54 / SOT6_0 / TIOB1_2
84
47
P1E / AN14 / RTS4_1 / DTTI0X_1
P55 / SCK6_0 / ADTG_1
85
46
P1D / AN13 / CTS4_1 / IC03_1
P56 / INT08_2
86
45
P1C / AN12 / SCK4_1 / IC02_1
P30 / TIOB0_1 / INT03_2
87
44
P1B / AN11 / SOT4_1 / IC01_1
P31 / SCK6_1 / TIOB1_1 / INT04_2
88
43
P1A / AN10 / SIN4_1 / INT05_1 / IC00_1
P32 / SOT6_1 / TIOB2_1 / INT05_2
89
42
P19 / AN09 / SCK2_2
P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6
90
41
P18 / AN08 / SOT2_2
P34 / TIOB4_1 / FRCK0_0
91
40
AVSS
P35 / TIOB5_1 / INT08_1 / IC03_0
92
39
AVRH
P36 / SIN5_2 / INT09_1 / IC02_0
93
38
AVCC
P37 / SOT5_2 / INT10_1 / IC01_0
94
37
P17 / AN07 / SIN2_2 / INT04_1
P38 / SCK5_2 / INT11_1 / IC00_0
95
36
P16 / AN06 / SCK0_1
P39 / DTTI0X_0 / ADTG_2
96
35
P15 / AN05 / SOT0_1 / IC03_2
P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2
97
34
P14 / AN04 / SIN0_1 / INT03_1 / IC02_2
P3B / TIOA1_1 / RTO01_0
98
33
P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1
P3C / TIOA2_1 / RTO02_0
99
32
P12 / AN02 / SOT1_1 / IC00_2
P3D / TIOA3_1 / RTO03_0 100
31
P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1
27
28
29
30
PE3 / X1
VSS
VCC
P10 / AN00
24
25
26
MD0
PE2 / X0
P4D / SOT7_1 / TIOB4_0 / DA0
PE0 / MD1
21
22
23
P4C / SCK7_1 / TIOB3_0 / CEC0
P4B / TIOB2_0 / IGTRG
P4E / SIN7_1 / TIOB5_0 / INT06_2 / DA1
18
19
20
P49 / SOT3_2 / TIOB0_0
INITX
P4A / SCK3_2 / TIOB1_0
15
16
17
P47 / X1A
P48 / SIN3_2 / INT14_1
13
14
VCC
P46 / X0A
10
11
12
P45 / TIOA5_0
C
P44 / TIOA4_0
VSS
7
8
9
P42 / TIOA2_0
P43 / TIOA3_0 / ADTG_7
4
5
6
VCC
VSS
P40 / TIOA0_0 / INT12_1
P3F / TIOA5_1 / RTO05_0
P41 / TIOA1_0 / INT13_1
1
2
3
P3E / TIOA4_1 / RTO04_0
QFP - 100
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Document Number: 002-05644 Rev. *C
Page 9 of 95
CY9A130N Series
4. List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
Pin name
LQFP-80
1
LQFP-100
1
QFP-100
79
VCC
I/O circuit
type
Pin state
type
-
P50
2
2
80
INT00_0
E
F
E
F
E
F
E
F
E
H
E
H
E
O
E
F
SIN3_1
P51
3
3
81
INT01_0
SOT3_1
(SDA3_1)
P52
4
4
82
INT02_0
SCK3_1
(SCL3_1)
P53
SIN6_0
5
5
83
TIOA1_2
INT07_2
P54
6
6
84
SOT6_0
(SDA6_0)
TIOB1_2
P55
7
7
85
SCK6_0
(SCL6_0)
ADTG_1
P56
8
8
86
INT08_2
P30
9
9
87
TIOB0_1
INT03_2
Document Number: 002-05644 Rev. *C
Page 10 of 95
CY9A130N Series
Pin No
Pin name
LQFP-80
LQFP-100
QFP-100
I/O circuit
type
Pin state
type
P31
TIOB1_1
10
10
88
SCK6_1
(SCL6_1)
E
F
E
F
E
F
E
H
E
F
E
F
E
F
E
F
INT04_2
P32
TIOB2_1
11
11
89
SOT6_1
(SDA6_1)
INT05_2
P33
INT04_0
12
12
90
TIOB3_1
SIN6_1
ADTG_6
P34
-
13
91
FRCK0_0
TIOB4_1
P35
IC03_0
-
14
92
TIOB5_1
INT08_1
P36
IC02_0
-
15
93
SIN5_2
INT09_1
P37
IC01_0
-
16
94
SOT5_2
(SDA5_2)
INT10_1
P38
IC00_0
-
17
95
SCK5_2
(SCL5_2)
INT11_1
Document Number: 002-05644 Rev. *C
Page 11 of 95
CY9A130N Series
Pin No
Pin name
LQFP-80
LQFP-100
QFP-100
I/O circuit
type
Pin state
type
P39
13
18
96
DTTI0X_0
E
H
E
H
E
H
E
H
E
H
E
H
E
H
ADTG_2
P3A
RTO00_0
(PPG00_0)
14
19
97
TIOA0_1
RTCCO_2
SUBOUT_2
P3B
15
20
98
RTO01_0
(PPG00_0)
TIOA1_1
P3C
16
21
99
RTO02_0
(PPG02_0)
TIOA2_1
P3D
17
22
100
RTO03_0
(PPG02_0)
TIOA3_1
P3E
18
23
1
RTO04_0
(PPG04_0)
TIOA4_1
P3F
19
24
2
RTO05_0
(PPG04_0)
TIOA5_1
20
25
3
VSS
-
-
26
4
VCC
-
P40
-
27
5
TIOA0_0
E
F
E
F
INT12_1
P41
-
28
6
TIOA1_0
INT13_1
Document Number: 002-05644 Rev. *C
Page 12 of 95
CY9A130N Series
Pin No
Pin name
LQFP-80
LQFP-100
QFP-100
I/O circuit
type
Pin state
type
P42
-
29
7
E
H
E
H
E
H
E
H
TIOA2_0
P43
-
30
8
TIOA3_0
ADTG_7
P44
21
31
9
TIOA4_0
P45
22
32
10
TIOA5_0
23
33
11
C
-
24
34
12
VSS
-
25
35
13
VCC
-
26
36
14
P46
D
M
D
N
B
C
E
F
E
H
E
H
E
H
G
Q
X0A
P47
27
37
15
X1A
28
38
16
INITX
P48
29
39
17
INT14_1
SIN3_2
P49
30
40
18
TIOB0_0
SOT3_2
(SDA3_2)
P4A
31
41
19
TIOB1_0
SCK3_2
(SCL3_2)
P4B
32
42
20
TIOB2_0
IGTRG
P4C
TIOB3_0
33
43
21
SCK7_1
(SCL7_1)
CEC0
Document Number: 002-05644 Rev. *C
Page 13 of 95
CY9A130N Series
Pin No
Pin name
LQFP-80
LQFP-100
QFP-100
I/O circuit
type
Pin state
type
P4D
TIOB4_0
34
44
22
SOT7_1
(SDA7_1)
J
T
J
S
C
P
H
D
A
A
A
B
DA0
P4E
TIOB5_0
35
45
23
INT06_2
SIN7_1
DA1
PE0
36
46
24
MD1
37
47
25
38
48
26
MD0
PE2
X0
PE3
39
49
27
X1
40
50
28
VSS
-
41
51
29
VCC
-
42
52
30
P10
F
J
F
L
F
J
AN00
P11
AN01
SIN1_1
43
53
31
INT02_1
FRCK0_2
WKUP1
P12
AN02
44
54
32
SOT1_1
(SDA1_1)
IC00_2
Document Number: 002-05644 Rev. *C
Page 14 of 95
CY9A130N Series
Pin No
Pin name
LQFP-80
LQFP-100
QFP-100
I/O circuit
type
Pin state
type
P13
AN03
45
55
33
SCK1_1
(SCL1_1)
F
J
F
K
F
J
F
J
F
K
IC01_2
RTCCO_1
SUBOUT_1
P14
AN04
46
56
34
SIN0_1
INT03_1
IC02_2
P15
AN05
47
57
35
SOT0_1
IC03_2
P16
48
58
36
AN06
SCK0_1
(SCL0_1)
P17
AN07
49
59
37
SIN2_2
INT04_1
50
60
38
AVCC
-
51
61
39
AVRH
-
52
62
40
AVSS
-
P18
53
63
41
AN08
F
J
F
J
SOT2_2
(SDA2_2)
P19
54
64
42
AN09
SCK2_2
(SCL2_2)
Document Number: 002-05644 Rev. *C
Page 15 of 95
CY9A130N Series
Pin No
Pin name
LQFP-80
LQFP-100
QFP-100
I/O circuit
type
Pin state
type
P1A
AN10
55
65
43
SIN4_1
F
K
F
J
F
J
F
J
F
J
F
J
E
H
E
H
INT05_1
IC00_1
P1B
AN11
56
66
44
SOT4_1
(SDA4_1)
IC01_1
P1C
AN12
-
67
45
SCK4_1
(SCL4_1)
IC02_1
P1D
AN13
-
68
46
CTS4_1
IC03_1
P1E
AN14
-
69
47
RTS4_1
DTTI0X_1
P1F
AN15
-
70
48
ADTG_5
FRCK0_1
P23
57
71
49
SCK0_0
(SCL0_0)
TIOA7_1
-
RTO00_1
P22
58
72
50
SOT0_0
(SDA0_0)
TIOB7_1
Document Number: 002-05644 Rev. *C
Page 16 of 95
CY9A130N Series
Pin No
Pin name
LQFP-80
LQFP-100
QFP-100
I/O circuit
type
Pin state
type
P21
SIN0_0
59
73
51
E
G
E
F
INT06_1
WKUP2
P20
60
74
52
INT05_0
CROUT_0
-
75
53
VSS
-
-
76
54
VCC
-
61
77
55
P00
E
E
E
E
E
E
E
E
E
E
E
F
E
F
E
H
E
H
TRSTX
P01
62
78
56
TCK
SWCLK
P02
63
79
57
TDI
P03
64
80
58
TMS
SWDIO
P04
65
81
59
TDO
SWO
P05
TIOA5_2
-
82
60
SIN4_2
INT00_1
P06
TIOB5_2
-
83
61
SOT4_2
(SDA4_2)
INT01_1
P07
66
84
62
ADTG_0
SCK4_2
(SCL4_2)
-
P08
-
85
63
TIOA0_2
CTS4_2
Document Number: 002-05644 Rev. *C
Page 17 of 95
CY9A130N Series
Pin No
Pin name
LQFP-80
LQFP-100
QFP-100
I/O circuit
type
Pin state
type
P09
-
86
64
TIOB0_2
E
H
G
F
G
H
G
H
E
H
E
H
E
I
E
O
E
H
E
H
RTS4_2
P0A
67
87
65
SIN4_0
INT00_2
P0B
68
88
66
SOT4_0
(SDA4_0)
TIOB6_1
P0C
69
89
67
SCK4_0
(SCL4_0)
TIOA6_1
P0D
70
90
68
RTS4_0
TIOA3_2
P0E
71
91
69
CTS4_0
TIOB3_2
P0F
NMIX
CROUT_1
72
92
70
RTCCO_0
SUBOUT_0
WKUP0
P63
73
93
71
INT03_0
P62
74
94
72
SCK5_0
(SCL5_0)
ADTG_3
P61
75
95
73
SOT5_0
(SDA5_0)
TIOB2_2
DTTI0X_2
Document Number: 002-05644 Rev. *C
Page 18 of 95
CY9A130N Series
Pin No
Pin name
LQFP-80
LQFP-100
QFP-100
I/O circuit
type
Pin state
type
P60
SIN5_0
TIOA2_2
76
96
74
G
R
G
H
G
H
G
H
INT15_1
WKUP3
CEC1
P80
77
97
75
SIN7_2
P81
78
98
76
SOT7_2
P82
79
99
77
SCK7_2
80
100
Document Number: 002-05644 Rev. *C
78
VSS
-
Page 19 of 95
CY9A130N Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin function
ADC
Pin name
Function description
LQFP-80
LQFP-100
QFP-100
ADTG_0
66
84
62
ADTG_1
7
7
85
ADTG_2
13
18
96
74
94
72
-
-
-
ADTG_5
-
70
48
ADTG_6
12
12
90
ADTG_7
-
30
8
ADTG_8
-
-
-
AN00
42
52
30
AN01
43
53
31
AN02
44
54
32
AN03
45
55
33
AN04
46
56
34
AN05
47
57
35
AN06
48
58
36
49
59
37
53
63
41
AN09
54
64
42
AN10
55
65
43
AN11
56
66
44
AN12
-
67
45
AN13
-
68
46
AN14
-
69
47
AN15
-
70
48
TIOA0_0
-
27
5
14
19
97
-
85
63
30
40
18
9
9
87
TIOB0_2
-
86
64
TIOA1_0
-
28
6
15
20
98
5
5
83
31
41
19
10
10
88
6
6
84
ADTG_3
ADTG_4
AN07
AN08
Base Timer
0
TIOA0_1
A/D converter external trigger input pin
A/D converter analog input pin.
ANxx describes ADC ch.xx.
Base timer ch.0 TIOA pin
TIOA0_2
TIOB0_0
TIOB0_1
Base Timer
1
Pin No
TIOA1_1
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
TIOA1_2
TIOB1_0
TIOB1_1
Base timer ch.1 TIOB pin
TIOB1_2
Document Number: 002-05644 Rev. *C
Page 20 of 95
CY9A130N Series
Pin function
Base Timer
2
Pin name
Function description
LQFP-100
QFP-100
-
29
7
16
21
99
TIOA2_2
76
96
74
TIOB2_0
32
42
20
11
11
89
75
95
73
-
30
8
17
22
100
TIOA3_2
70
90
68
TIOB3_0
33
43
21
12
12
90
71
91
69
21
31
9
18
23
1
TIOA4_2
-
-
-
TIOB4_0
34
44
22
-
13
91
-
-
-
22
32
10
19
24
2
TIOA5_2
-
82
60
TIOB5_0
35
45
23
-
14
92
-
83
61
TIOA2_0
TIOA2_1
TIOB2_1
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
TIOB2_2
Base Timer
3
TIOA3_0
TIOA3_1
TIOB3_1
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
TIOB3_2
Base Timer
4
TIOA4_0
TIOA4_1
TIOB4_1
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
TIOB4_2
Base Timer
5
TIOA5_0
TIOA5_1
TIOB5_1
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
TIOB5_2
Base Timer
6
Base Timer
7
TIOA6_1
Base timer ch.6 TIOA pin
69
89
67
TIOB6_1
Base timer ch.6 TIOB pin
68
88
66
-
-
-
57
71
49
-
-
-
-
-
-
58
72
50
TIOA7_0
TIOA7_1
Base timer ch.7 TIOA pin
TIOA7_2
TIOB7_0
TIOB7_1
Base timer ch.7 TIOB pin
TIOB7_2
Debugger
Pin No
LQFP-80
-
-
-
SWCLK
Serial wire debug interface clock input pin
62
78
56
SWDIO
Serial wire debug interface data input / output
pin
64
80
58
SWO
Serial wire viewer output pin
65
81
59
TRSTX
JTAG reset input pin
61
77
55
TCK
JTAG test clock input pin
62
78
56
TDI
JTAG test data input pin
63
79
57
TMS
JTAG test mode state input/output pin
64
80
58
TDO
JTAG debug data output pin
65
81
59
Document Number: 002-05644 Rev. *C
Page 21 of 95
CY9A130N Series
Pin function
External
Interrupt
Pin name
Function description
Pin No
LQFP-80
LQFP-100
QFP-100
2
2
80
-
82
60
INT00_2
67
87
65
INT01_0
3
3
81
-
83
61
4
4
82
43
53
31
73
93
71
46
56
34
9
9
87
12
12
90
49
59
37
INT04_2
10
10
88
INT05_0
60
74
52
55
65
43
11
11
89
59
73
51
35
45
23
5
5
83
-
14
92
INT00_0
INT00_1
INT01_1
INT02_0
INT02_1
External interrupt request 00 input pin
External interrupt request 01 input pin
External interrupt request 02 input pin
INT03_0
INT03_1
External interrupt request 03 input pin
INT03_2
INT04_0
INT04_1
INT05_1
External interrupt request 04 input pin
External interrupt request 05 input pin
INT05_2
INT06_1
INT06_2
INT07_2
INT08_1
INT08_2
External interrupt request 06 input pin
External interrupt request 07 input pin
External interrupt request 08 input pin
8
8
86
INT09_1
External interrupt request 09 input pin
-
15
93
INT10_1
External interrupt request 10 input pin
-
16
94
INT11_1
External interrupt request 11 input pin
-
17
95
INT12_1
External interrupt request 12 input pin
-
27
5
INT13_1
External interrupt request 13 input pin
-
28
6
INT14_1
External interrupt request 14 input pin
29
39
17
INT15_1
External interrupt request 15 input pin
76
96
74
NMIX
Non-Maskable Interrupt input pin
72
92
70
Document Number: 002-05644 Rev. *C
Page 22 of 95
CY9A130N Series
Pin function
GPIO
Pin name
Function description
Pin No
LQFP-80
LQFP-100
QFP-100
P00
61
77
55
P01
62
78
56
P02
63
79
57
P03
64
80
58
P04
65
81
59
P05
-
82
60
P06
-
83
61
P07
66
84
62
P08
General-purpose I/O port 0
-
85
63
P09
-
86
64
P0A
67
87
65
P0B
68
88
66
P0C
69
89
67
P0D
70
90
68
P0E
71
91
69
P0F
72
92
70
P10
42
52
30
P11
43
53
31
P12
44
54
32
P13
45
55
33
P14
46
56
34
P15
47
57
35
P16
48
58
36
49
59
37
53
63
41
P19
54
64
42
P1A
55
65
43
P1B
56
66
44
P1C
-
67
45
P1D
-
68
46
P1E
-
69
47
P1F
-
70
48
P20
60
74
52
59
73
51
58
72
50
57
71
49
P17
P18
P21
P22
General-purpose I/O port 1
General-purpose I/O port 2
P23
Document Number: 002-05644 Rev. *C
Page 23 of 95
CY9A130N Series
Pin function
GPIO
Pin name
Function description
Pin No
LQFP-80
LQFP-100
QFP-100
P30
9
9
87
P31
10
10
88
P32
11
11
89
P33
12
12
90
P34
-
13
91
P35
-
14
92
P36
-
15
93
-
16
94
-
17
95
P39
13
18
96
P3A
14
19
97
P3B
15
20
98
P3C
16
21
99
P3D
17
22
100
P3E
18
23
1
P3F
19
24
2
P40
-
27
5
P41
-
28
6
P42
-
29
7
P43
-
30
8
P44
21
31
9
P45
22
32
10
P46
26
36
14
27
37
15
P48
29
39
17
P49
30
40
18
P4A
31
41
19
P4B
32
42
20
P4C
33
43
21
P4D
34
44
22
P4E
35
45
23
P50
2
2
80
P51
3
3
81
4
4
82
5
5
83
P54
6
6
84
P55
7
7
85
P56
8
8
86
P37
P38
P47
General-purpose I/O port 3
General-purpose I/O port 4
P52
P53
General-purpose I/O port 5
Document Number: 002-05644 Rev. *C
Page 24 of 95
CY9A130N Series
Pin function
GPIO
Pin name
Function description
LQFP-100
QFP-100
P60
76
96
74
P61
75
95
73
P62
General-purpose I/O port 6
74
94
72
P63
73
93
71
P80
77
97
75
78
98
76
79
99
77
36
46
24
38
48
26
P81
General-purpose I/O port 8
P82
PE0
PE2
Multifunction Serial
0
39
49
27
SIN0_0
59
73
51
46
56
34
58
72
50
47
57
35
57
71
49
48
58
36
SIN0_1
SOT0_1
(SDA0_1)
Multi-function serial interface ch.0 input pin
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA0 when it is used in an I2C (operation
mode 4).
SCK0_1
(SCL0_1)
Multi-function serial interface ch.0 clock I/O
pin.
This pin operates as SCK0 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL0 when it is used in an I2C (operation
mode 4).
SIN1_1
Multi-function serial interface ch.1 input pin
43
53
31
SOT1_1
(SDA1_1)
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA1 when it is used in an I2C (operation
mode 4).
44
54
32
SCK1_1
(SCL1_1)
Multi-function serial interface ch.1 clock I/O
pin.
This pin operates as SCK1 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL1 when it is used in an I2C (operation
mode 4).
45
55
33
SIN2_2
Multi-function serial interface ch.2 input pin
49
59
37
SOT2_2
(SDA2_2)
Multi-function serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA2 when it is used in an I2C (operation
mode 4).
53
63
41
SCK2_2
(SCL2_2)
Multi-function serial interface ch.2 clock I/O
pin.This pin operates as SCK2 when it is used
in a UART/CSIO (operation modes 0 to 2) and
as SCL2 when it is used in an I2C (operation
mode 4).
54
64
42
SCK0_0
(SCL0_0)
Multifunction Serial
2
General-purpose I/O port E
PE3
SOT0_0
(SDA0_0)
Multifunction Serial
1
Pin No
LQFP-80
Document Number: 002-05644 Rev. *C
Page 25 of 95
CY9A130N Series
Pin function
Multifunction Serial
3
Pin name
Pin No
LQFP-80
LQFP-100
QFP-100
2
2
80
29
39
17
3
3
81
30
40
18
4
4
82
31
41
19
67
87
65
55
65
43
-
82
60
68
88
66
56
66
44
-
83
61
69
89
67
-
67
45
-
84
62
70
90
68
-
69
47
RTS4_2
-
86
64
CTS4_0
71
91
69
-
68
46
-
85
63
SIN3_1
SIN3_2
SOT3_1
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
Multifunction Serial
4
Function description
Multi-function serial interface ch.3 input pin
Multi-function serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA3 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.3 clock I/O
pin.
This pin operates as SCK3 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL3 when it is used in an I2C (operation
mode 4).
SIN4_0
SIN4_1
Multi-function serial interface ch.4 input pin
SIN4_2
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
Multi-function serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA4 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.4 clock I/O
pin.
This pin operates as SCK4 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL4 when it is used in an I2C (operation
mode 4).
RTS4_0
RTS4_1
CTS4_1
Multi-function serial interface ch.4 RTS output
pin
Multi-function serial interface ch.4 CTS input
pin
CTS4_2
Document Number: 002-05644 Rev. *C
Page 26 of 95
CY9A130N Series
Pin function
Multifunction Serial
5
Pin name
SIN5_0
SIN5_2
SOT5_0
(SDA5_0)
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
SCK5_2
(SCL5_2)
Multifunction Serial
6
SIN6_0
SIN6_1
SOT6_0
(SDA6_0)
SOT6_1
(SDA6_1)
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
Multifunction Serial
7
SIN7_1
SIN7_2
SOT7_1
(SDA7_1)
SOT7_2
(SDA7_2)
SCK7_1
(SCL7_1)
SCK7_2
(SCL7_2)
Function description
Multi-function serial interface ch.5 input pin
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA5 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.5 clock I/O
pin.
This pin operates as SCK5 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL5 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.6 input pin
Multi-function serial interface ch.6 output pin.
This pin operates as SOT6 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA6 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.6 clock I/O
pin.
This pin operates as SCK6 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL6 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.7 input pin
Multi-function serial interface ch.7 output pin.
This pin operates as SOT7 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA7 when it is used in an I2C (operation
mode 4).
Multi-function serial interface ch.7 clock I/O
pin.
This pin operates as SCK7 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL7 when it is used in an I2C (operation
mode 4).
Document Number: 002-05644 Rev. *C
Pin No
LQFP-80
LQFP-100
QFP-100
76
96
74
-
15
93
75
95
73
-
16
94
74
94
72
-
17
95
5
5
83
12
12
90
6
6
84
11
11
89
7
7
85
10
10
88
35
45
23
77
97
75
34
44
22
78
98
76
33
43
21
79
99
77
Page 27 of 95
CY9A130N Series
Pin function
Multifunction Timer
0
Pin name
DTTI0X_0
DTTI0X_1
DTTI0X_2
Function description
Input signal of waveform generator to control
outputs RTO00 to RTO05 of Multi-function
timer 0
FRCK0_0
FRCK0_1
16-bit free-run timer ch.0 external clock input
pin
LQFP-100
QFP-100
13
18
96
-
69
47
75
95
73
-
13
91
-
70
48
FRCK0_2
43
53
31
IC00_0
-
17
95
IC00_1
55
65
43
IC00_2
44
54
32
IC01_0
-
16
94
56
66
44
45
55
33
IC01_1
IC01_2
IC02_0
16-bit input capture input pin of Multi-function
timer 0.
ICxx describes a channel number.
-
15
93
IC02_1
-
67
45
IC02_2
46
56
34
IC03_0
-
14
92
IC03_1
-
68
46
IC03_2
47
57
35
14
19
97
-
71
49
RTO00_0
(PPG00_0)
RTO00_1
(PPG00_1)
Real-time
clock
Pin No
LQFP-80
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is used in
PPG0 output mode.
RTO01_0
(PPG00_0)
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is used in
PPG0 output mode.
15
20
98
RTO02_0
(PPG02_0)
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is used in
PPG0 output mode.
16
21
99
RTO03_0
(PPG02_0)
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is used in
PPG0 output mode.
17
22
100
RTO04_0
(PPG04_0)
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is used in
PPG0 output mode.
18
23
1
RTO05_0
(PPG04_0)
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is used in
PPG0 output mode.
19
24
2
IGTRG
PPG IGBT mode external trigger input pin
32
42
20
72
92
70
45
55
33
14
19
97
72
92
70
45
55
33
14
19
97
RTCCO_0
RTCCO_1
Pulse output pin of Real-time clock
RTCCO_2
SUBOUT_0
SUBOUT_1
Sub clock output pin
SUBOUT_2
Document Number: 002-05644 Rev. *C
Page 28 of 95
CY9A130N Series
Pin function
LowPower
Consumption
Mode
DAC
HDMICEC
Reset
Pin name
Function description
LQFP-100
QFP-100
WKUP0
Deep standby mode return signal input pin 0
72
92
70
WKUP1
Deep standby mode return signal input pin 1
43
53
31
WKUP2
Deep standby mode return signal input pin 2
59
73
51
WKUP3
Deep standby mode return signal input pin 3
76
96
74
DA0
D/A converter ch.0 analog output pin
34
44
22
DA1
D/A converter ch.1 analog output pin
35
45
23
CEC0
HDMI-CEC ch.0 pin
33
43
21
CEC1
HDMI-CEC ch.1 pin
76
96
74
INITX
External Reset Input Pin.
A reset is valid when INITX = L.
28
38
16
MD0
Mode 0 pin.
During normal operation, MD0 = L must be
input.
During serial programming to Flash memory,
MD0 = H must be input.
37
47
25
MD1
Mode 1 pin.
During normal operation, input is not needed.
During serial programming to Flash memory,
MD1 = L must be input.
36
46
24
1
1
79
-
26
4
25
35
13
41
51
29
-
76
54
20
25
3
24
34
12
40
50
28
-
75
53
Mode
Power
VCC
Power supply pin
GND
VSS
Clock
Pin No
LQFP-80
GND pin
80
100
78
X0
Main clock (oscillation) input pin
38
48
26
X0A
Sub clock (oscillation) input pin
26
36
14
X1
Main clock (oscillation) I/O pin
39
49
27
X1A
Sub clock (oscillation) I/O pin
27
37
15
60
74
52
CROUT_0
CROUT_1
Built-in High-speed CR-osc clock output port
72
92
70
AVCC
A/D converter and D/A converter
analog power supply pin
50
60
38
AVRH
A/D converter analog reference voltage input
pin
51
61
39
Analog
GND
AVSS
A/D converter and D/A converter
GND pin
52
62
40
C pin
C
Power supply stabilization capacity pin
23
33
11
Analog
Power
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-05644 Rev. *C
Page 29 of 95
CY9A130N Series
5. I/O Circuit Type
Type
Circuit
Remarks
It is possible to select the main
oscillation / GPIO function.
A
Pull-up
resistor
P-ch
P-ch
Digital output
X1
When the main oscillation is
selected.
– Oscillation feedback resistor
: Approximately 1 MΩ
– With standby mode control
When the GPIO is selected.
– CMOS level output.
N-ch
Digital output
– CMOS level hysteresis input
– With pull-up resistor control
R
– With standby mode control
Pull-up resistor control
Digital input
– Pull-up resistor
: Approximately 50 kΩ
– IOH = -4 mA, IOL = 4 mA
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
X0
N-ch
Digital output
Pull-up resistor control
Document Number: 002-05644 Rev. *C
Page 30 of 95
CY9A130N Series
Type
Circuit
Remarks
B
– CMOS level hysteresis input
– Pull-up resistor
: Approximately 50 kΩ
Pull-up resistor
Digital input
C
Digital input
N-ch
Document Number: 002-05644 Rev. *C
– Open drain output
– CMOS level hysteresis input
Digital output
Page 31 of 95
CY9A130N Series
Type
Circuit
Remarks
It is possible to select the sub
oscillation / GPIO function
D
Pull-up
resistor
P-ch
P-ch
Digital output
X1A
N-ch
Digital output
R
Pull-up resistor control
When the sub oscillation is
selected.
– Oscillation feedback resistor
: Approximately 5 MΩ
– With standby mode control
When the GPIO is selected.
– CMOS level output.
– CMOS level hysteresis input
– With pull-up resistor control
– With standby mode control
– Pull-up resistor
: Approximately 50 kΩ
– IOH = -4 mA, IOL = 4 mA
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
Document Number: 002-05644 Rev. *C
Page 32 of 95
CY9A130N Series
Type
Circuit
Remarks
E
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
– IOH = -4 mA, IOL = 4 mA
–
–
–
–
–
P-ch
P-ch
Digital output
When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
F
P-ch
P-ch
N-ch
R
Digital output
Digital output
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
– IOH = -4 mA, IOL = 4 mA
–
–
–
–
–
–
–
When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
Document Number: 002-05644 Rev. *C
Page 33 of 95
CY9A130N Series
Type
Circuit
Remarks
G
P-ch
N-ch
Digital output
Digital output
R
–
–
–
–
–
–
CMOS level output
CMOS level hysteresis input
With standby mode control
5 V tolerant input
IOH = -4 mA, IOL = 4 mA
Available to control PZR
registers.
P0B, P0C, P4C, P60, P81,
P82 only.
When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
Digital input
Standby mode control
H
CMOS level hysteresis input
Mode input
J
P-ch
P-ch
N-ch
R
Digital output
Digital output
CMOS level output
CMOS level hysteresis input
With input control
Analog output
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
– IOH = -4 mA, IOL = 4 mA
–
–
–
–
–
–
–
When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
Pull-up resistor control
Digital input
Standby mode control
Analog output
Document Number: 002-05644 Rev. *C
Page 34 of 95
CY9A130N Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
Precautions for Product Design
6.1
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1.
Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the
device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current
conditions at the design stage.
2.
Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current
flows. Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3.
Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1.
Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to
abnormal noise, surge levels, etc.
2.
Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-05644 Rev. *C
Page 35 of 95
CY9A130N Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1.
Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2.
Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3.
When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4.
Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-05644 Rev. *C
Page 36 of 95
CY9A130N Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1.
Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2.
Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3.
Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4.
Ground all fixtures and instruments, or protect with anti-static measures.
5.
Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use
anti-static measures or processing to prevent discharges.
Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you
use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding
as appropriate.
Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin
to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-05644 Rev. *C
Page 37 of 95
CY9A130N Series
7. Handling Devices
Power Supply Pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and
GND pin, between AVCC pin and AVSS pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal Oscillator Circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator and the bypass capacitor to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Using an External Clock
To use the external clock, set general-purpose I/O ports to input the clock to X0/PE2 and X0A/P46 pin.
Example of Using an External Clock
Device
X0/PE2 (X0A/P46)
Can be used as
general-purpose I/O
ports.
X1/PE3 (X1A/P47)
Set as
general-purpose I/O
ports.
Handling when Using Multi-Function Serial Pin as I2C Pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I 2C bus system with
power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
Document Number: 002-05644 Rev. *C
Page 38 of 95
CY9A130N Series
C
Device
CS
VSS
GND
Mode pins (MD0, MD1)
Connect the MD pin (MD0, MD1) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance
stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on Power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC AVCC AVRH
Turning off : AVRH AVCC VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Differences in Features among the Products with Different Memory Sizes and between Flash Products and
MASK Products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash products and MASK products are different because chip layout and
memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Document Number: 002-05644 Rev. *C
Page 39 of 95
CY9A130N Series
8. Block Diagram
MB9AF131/132
ROM
Table
SWJ-DP
Cortex-M3 Core
@20MHz(Max)
Flash I/F
I
Multi-layer AHB (Max 20MHz)
TRSTX,TCK,
TDI,TMS
TDO
D
Sys
AHB-APB Bridge: APB0
(Max 20MHz)
NVIC
Watchdog Timer
(Software)
Clock Reset
Generator
INITX
Watchdog Timer
(Hardware)
Security
On-Chip
Flash
64/128Kbyte
SRAM1
12/16Kbyte
CSV
CLK
X0
X1
X0A
X1A
Main
Osc
Sub
Osc
PLL
Source Clock
CR
4MHz
CR
100kHz
CROUT
AVCC,
AVSS,AVRH
ANxx
Deep Standby Ctrl
WKUPx
12-bit A/D Converter
Power On
Reset
Unit 0
LVD Ctrl
ADTGx
LVD
Regulator
TIOBx
Base Timer
16-bit 8ch./
32-bit 4ch.
A/D Activation
Compare
1ch.
IC0x
FRCK0
16-bit Input Capture
4ch.
16-bit FreeRun Timer
3ch.
16-bit Output
Compare
6ch.
DTTI0X
RTO0x
IGTRG
AHB-APB Bridge : APB2 (Max 20MHz)
TIOAx
HDMI-CEC/
Remote Receiver
Control
Multi-Function Timer ×1
Document Number: 002-05644 Rev. *C
CECx
RTCCO
SUBOUT
Real Time Clock
External Interrupt
Controller
16-pin + NMI
INTxx
NMIX
MODE-Ctrl
MD1,
MD0
P0x,
P1x,
GPIO
Waveform Generator
3ch.
16-bit PPG
3ch.
C
IRQ-Monitor
10-bit D/A Converter
2ch.
AHB-APB Bridge : APB1 (Max 20MHz)
DAx
PIN-Function-Ctrl
.
.
.
Pxx
Multi-Function
Serial IF
8ch.
HW flow control(ch.4)*
SCKx
SINx
SOTx
CTS4
RTS4
Page 40 of 95
CY9A130N Series
9. Memory Size
See Memory size in product Lineup to confirm the memory size.
9.1
Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
Reserved
Reserved
0x4003_C000
0x4003_B000
0x4003_9000
0x4003_8000
0x4400_0000
0x4200_0000
32Mbytes
Bit band alias
0x4003_6000
0x4003_5000
Peripherals
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
0x4000_0000
Reserved
0x2400_0000
0x2200_0000
32Mbytes
Bit band alias
Reserved
0x2008_0000
0x2000_0000
SRAM1
0x4002_9000
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
Reserved
See " Memory Map (2)"
for the memory size
details.
0x0010_0008
0x0010_0000
Security/CR Trim
MFS
Reserved
LVD/DS mode
HDMI-CEC/
Remote Control Receiver
GPIO
Reserved
Int-Req.Read
EXTI
Reserved
CR Trim
Reserved
D/AC
A/DC
Reserved
Base Timer
PPG
MFT unit0
Reserved
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
0x4000_1000
0x4000_0000
Document Number: 002-05644 Rev. *C
Reserved
Reserved
0x4002_1000
0x4002_0000
Flash
0x0000_0000
RTC
SW WDT
HW WDT
Clock/Reset
Reserved
Flash I/F
Page 41 of 95
CY9A130N Series
Memory Map (2)
See CY9AAA0N/1A0N/A30N/130N/130L Series Flash Programming Manual to confirm the detail of Flash memory.
Document Number: 002-05644 Rev. *C
Page 42 of 95
CY9A130N Series
Peripheral Address Map
Start address
0x4000_0000
End address
Bus
0x4000_0FFF
Peripherals
Flash memory I/F register
AHB
0x4000_1000
0x4000_FFFF
Reserved
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
Software Watchdog timer
APB0
0x4001_3000
0x4001_4FFF
Reserved
0x4001_5000
0x4001_5FFF
Reserved
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function timer unit0
0x4002_1000
0x4002_1FFF
Reserved
0x4002_2000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
Base Timer
0x4002_6000
0x4002_6FFF
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_8FFF
D/A Converter
0x4002_9000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Built-in CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt
0x4003_1000
0x4003_1FFF
Interrupt Source Check Register
0x4003_2000
0x4003_2FFF
Reserved
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
HDMI-CEC/ Remote Control Receiver
0x4003_5000
0x4003_50FF
Low-Voltage Detector
0x4003_5100
0x4003_5FFF
APB1
Reserved
Deep standby mode Controller
APB2
0x4003_6000
0x4003_6FFF
Reserved
0x4003_7000
0x4003_7FFF
Reserved
0x4003_8000
0x4003_8FFF
Multi-function serial
0x4003_9000
0x4003_9FFF
Reserved
0x4003_A000
0x4003_AFFF
Reserved
0x4003_B000
0x4003_BFFF
Real-time clock
0x4003_C000
0x4003_FFFF
Reserved
Document Number: 002-05644 Rev. *C
Page 43 of 95
CY9A130N Series
Start address
End address
Bus
Peripherals
0x4004_0000
0x4004_FFFF
Reserved
0x4005_0000
0x4005_FFFF
Reserved
0x4006_0000
0x4006_0FFF
Reserved
0x4006_1000
0x4006_1FFF
0x4006_2000
0x4006_2FFF
Reserved
0x4006_3000
0x4006_3FFF
Reserved
0x4006_4000
0x41FF_FFFF
Reserved
Document Number: 002-05644 Rev. *C
AHB
Reserved
Page 44 of 95
CY9A130N Series
10. Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the L level.
INITX=1
This is the period when the INITX pin is the H level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
Document Number: 002-05644 Rev. *C
Page 45 of 95
CY9A130N Series
Pin status type
List of Pin Status
Function
group
Main
crystal
oscillator
input pin
A
Power-on
reset or
INITX
low-voltage
input state
detection
state
Power
supply
unstable
Main
crystal
oscillator
output pin
Power supply stable
Run mode
or Sleep
mode state
Timer mode,
RTC mode, or
Stop mode state
Deep standby RTC mode
or Deep Standby Stop
mode state
Return from
Deep
Standby
mode state
Power
supply
stable
Power supply stable
Power supply stable
Power supply
stable
INITX = 1
INITX = 1
INITX = 1
-
INITX = 0
INITX = 1
INITX = 1
-
-
-
-
Input
enabled
External
main clock Setting
input
disabled
selected
GPIO
selected
Device
internal
reset
state
Setting
disabled
Hi-Z /
Internal
input fixed
at 0
Input
enabled
SPL = 1
SPL = 0
SPL = 1
-
Input
enabled
Input enabled
Input enabled
Input enabled
Input
enabled
Setting
disabled
Maintain
previous
state
Maintain
previous state /
When
oscillation
stops*1, output
maintains
previous state /
Internal input
fixed at 0
Hi-Z /
Input enabled /
When
oscillation
stops*1,
Hi-Z /
Internal input
fixed at 0
Output
maintains
previous state
/ Internal input
fixed at 0
Hi-Z /
Internal
GPIO selected
input fixed at
"0"
Setting
disabled
Setting
disabled
Maintain
previous
state
Output
maintains
Hi-Z / Internal
previous state /
input fixed at 0
Internal input
fixed at 0
Output
maintains
previous state
/ Internal input
fixed at 0
Hi-Z /
Internal
Maintain
input fixed at previous state
0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state /
When
Hi-Z /
Internal
oscillation
input fixed stops*1, Hi-Z
output /
at 0
Internal
input fixed
at 0
Maintain
previous state /
When
oscillation
stops*1, Hi-Z
output /
Internal input
fixed at 0
Maintain
previous state /
When
oscillation
stops*1, Hi-Z
output /
Internal input
fixed at 0
Maintain
previous state /
When
oscillation
stops*1, Hi-Z
output /
Internal input
fixed at 0
Maintain
previous
state /
When
oscillation
stops*1, Hi-Z
output /
Internal input
fixed at 0
Maintain
previous state
Output
maintains
Hi-Z / Internal
previous state
input fixed at 0
/ Internal input
fixed at 0
Setting
disabled
B
Input
enabled
SPL = 0
Input enabled
Maintain
previous state /
When
oscillation
stops*1, Hi-Z
output /
Internal input
fixed at 0
Hi-Z /
Internal
Maintain
input fixed at previous state
0
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
C
INITX
input pin
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up / Input
enabled
Pull-up /
Pull-up / Input Pull-up / Input
Input
enabled
enabled
enabled
Pull-up / Input
enabled
D
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input enabled
Input enabled
Input
enabled
Input enabled
JTAG
selected
Hi-Z
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Setting
disabled
Setting
disabled
E
GPIO
selected
Setting
disabled
Document Number: 002-05644 Rev. *C
Maintain
previous
state
Maintain
previous state
Maintain
previous state
Input enabled
Maintain
previous
state
Maintain
Maintain
previous state Hi-Z /
previous state
Hi-Z / Internal
Internal
input fixed at
input fixed at 0
0
Page 46 of 95
Pin status type
CY9A130N Series
Function
group
External
interrupt
enabled
selected
F
Power-on
reset or
INITX
low-voltage
input state
detection
state
Power
supply
unstable
Device
internal
reset
state
Power supply stable
Run mode
or Sleep
mode state
Timer mode,
RTC mode, or
Stop mode state
Deep standby RTC mode
or Deep Standby Stop
mode state
Return from
Deep
Standby
mode state
Power
supply
stable
Power supply stable
Power supply stable
Power supply
stable
INITX = 1
INITX = 1
INITX = 1
-
INITX = 0
INITX = 1
INITX = 1
-
-
-
-
Setting
disabled
Resource
other than
above
selected
Hi-Z
GPIO
selected
Setting
disabled
SPL = 0
Setting
disabled
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous state
Maintain
previous
state
Maintain
previous state
Hi-Z /
Internal input
fixed at 0
WKUP
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z /
Internal input
fixed at 0
External
interrupt
enabled
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous
state
G Resource
other than
above
selected
Hi-Z
GPIO
selected
Hi-Z /
Input
enabled
Maintain
previous state
H
NMIX
selected
Resource
other than
above
selected
Hi-Z /
Input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Hi-Z /
Input
enabled
Document Number: 002-05644 Rev. *C
Output
maintains
previous state
/ Internal input
fixed at 0
WKUP input
enabled
-
GPIO selected
Hi-Z /
Internal
input fixed at
0
Maintain
previous state
Hi-Z /
WKUP input
enabled
GPIO selected
GPIO selected
Internal input
fixed at 0
Hi-Z /
Internal
input fixed at
0
Output
maintains
Maintain
previous state
previous state
/ Internal input
fixed at 0
GPIO selected
Internal input
GPIO selected
fixed at 0
Hi-Z /
Hi-Z / Internal Output
Internal
input fixed at
input fixed at 0 maintains
Maintain
previous state 0
previous state
/ Internal input
fixed at 0
Hi-Z /
Input
enabled
Hi-Z
GPIO selected
Internal input
fixed at 0
SPL = 1
Hi-Z /
Internal input
fixed at 0
Hi-Z
GPIO
selected
SPL = 0
Hi-Z /
Input
enabled
Resource
selected
I
SPL = 1
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous state
Maintain
previous state
Maintain
previous
state
Maintain
previous state
Hi-Z /
Internal input
fixed at 0
WKUP input
enabled
GPIO selected
Hi-Z /
WKUP input
enabled
Maintain
previous state
Page 47 of 95
Pin status type
CY9A130N Series
Function
group
Power-on
reset or
INITX
low-voltage
input state
detection
state
Power
supply
unstable
-
Analog
input
selected
J
Resource
other than
above
selected
Hi-Z
Device
internal
reset
state
Power supply stable
INITX = 0
INITX = 1
-
-
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
K
Timer mode,
RTC mode, or
Stop mode state
Deep standby RTC mode
or Deep Standby Stop
mode state
Return from
Deep
Standby
mode state
Power
supply
stable
Power supply stable
Power supply stable
Power supply
stable
INITX = 1
INITX = 1
INITX = 1
INITX = 1
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
SPL = 0
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
SPL = 0
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
SPL = 1
Hi-Z /
Internal
input fixed at
0/
Analog input
enabled
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous state
Hi-Z /
Internal input
fixed at 0
Hi-Z
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Hi-Z /
Internal input
fixed at "0" /
Analog input
enabled
External
interrupt
enabled
selected
Resource
other than
above
selected
SPL = 1
GPIO selected
Internal input
GPIO selected
fixed at 0
Hi-Z /
Internal
Output
input fixed at
maintains
0
Maintain
previous state
previous state
/ Internal input
fixed at 0
GPIO
selected
Analog
input
selected
Run mode
or Sleep
mode state
Maintain
previous state
Setting
disabled
Setting
disabled
GPIO
selected
Document Number: 002-05644 Rev. *C
Setting
disabled
Maintain
previous
state
Maintain
previous state
Hi-Z /
Internal input
fixed at 0
Hi-Z /
Internal
input fixed at
"0" /
Analog input
enabled
Hi-Z /
Internal input
fixed at "0" /
Analog input
enabled
GPIO selected
Internal input
GPIO selected
fixed at 0
Hi-Z /
Internal
input fixed at
0
Output
maintains
Maintain
previous state
previous state
/ Internal input
fixed at 0
Page 48 of 95
Pin status type
CY9A130N Series
Function
group
Power-on
reset or
INITX
low-voltage
input state
detection
state
Power
supply
unstable
-
Power supply stable
INITX = 0
INITX = 1
-
-
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Run mode
or Sleep
mode state
Timer mode,
RTC mode, or
Stop mode state
Deep standby RTC mode
or Deep Standby Stop
mode state
Return from
Deep
Standby
mode state
Power
supply
stable
Power supply stable
Power supply stable
Power supply
stable
INITX = 1
INITX = 1
INITX = 1
INITX = 1
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Hi-Z /
Internal
input fixed at
0/
Analog input
enabled
WKUP
enabled
Hi-Z /
Internal input
fixed at 0
WKUP input
enabled
Hi-Z /
WKUP input
enabled
External
interrupt
enabled
selected
Maintain
previous state
Analog
input
selected
L
Device
internal
reset
state
Resource
other than
above
selected
Hi-Z
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
Maintain
previous state
Hi-Z /
Internal input
fixed at 0
GPIO
selected
Sub crystal
Input
oscillator
enabled
input pin
External
sub clock
input
M
selected
GPIO
selected
Setting
disabled
Setting
disabled
Input
enabled
Setting
disabled
Setting
disabled
Document Number: 002-05644 Rev. *C
Input
enabled
Hi-Z /
Internal input
fixed at 0 /
Analog input
enabled
GPIO selected
GPIO selected
Internal input
fixed at 0
Hi-Z /
Internal
input fixed at
0
Output
maintains
Maintain
previous state
previous state
/ Internal input
fixed at 0
Input
enabled
Input enabled
Input enabled
Input enabled
Input
enabled
Input enabled
Setting
disabled
Maintain
previous
state
Maintain
previous state /
When
oscillation
stops*2, output
maintains
previous state /
Internal input
fixed at 0
Hi-Z / Input
enabled /
When
oscillation
stops*2,
Hi-Z /
Internal input
fixed at 0
Maintain
previous state
/
When
oscillation
stops*2, output
maintains
previous state
/
Internal input
fixed at 0
Hi-Z / Input
enabled /
When
oscillation
stops*2,
Hi-Z /
Internal
input fixed at
0
Maintain
previous state
/
When Return
from Deep
Standby
STOP mode,
GPIO is
selected
Setting
disabled
Maintain
previous
state
Output
maintains
Hi-Z / Internal
previous state /
input fixed at 0
Internal input
fixed at 0
Output
maintains
previous state
/ Internal input
fixed at 0
Hi-Z /
Internal
Maintain
input fixed at previous state
0
Page 49 of 95
Pin status type
CY9A130N Series
Function
group
Power-on
reset or
INITX
low-voltage
input state
detection
state
Power
supply
unstable
Device
internal
reset
state
Power supply stable
Run mode
or Sleep
mode state
Timer mode,
RTC mode, or
Stop mode state
Deep standby RTC mode
or Deep Standby Stop
mode state
Return from
Deep
Standby
mode state
Power
supply
stable
Power supply stable
Power supply stable
Power supply
stable
INITX = 1
INITX = 1
INITX = 1
-
INITX = 0
INITX = 1
INITX = 1
-
-
-
-
Hi-Z /
Sub crystal
Internal
oscillator
input fixed
output pin
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Maintain
Internal
previous
input fixed
state
at 0
N
Maintain
previous state
/
When
oscillation
stops*2,
Hi-Z / Internal
input fixed at 0
Maintain
previous
state
Maintain
previous state
Input
enabled
Input
enabled
Input enabled
Input enabled
Input enabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous state
Hi-Z / input
enabled
Maintain
Hi-Z / input
previous state enabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous state
Maintain
Maintain
Maintain
previous
previous state previous state
state
Setting
disabled
Setting
disabled
External
interrupt
enabled
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Mode
input pin
Input
enabled
Input
enabled
GPIO
selected
Setting
disabled
CEC
enabled
Setting
disabled
GPIO
selected
SPL = 1
Maintain
previous
Maintain
Maintain
Maintain
previous state previous state state /
previous state /
/
/
When
When
When
When
oscillation
oscillation
oscillation
oscillation
stops*2,
stops*2,
2
2
stops* ,
stops* ,
Hi-Z /
Hi-Z / Internal
Hi-Z / Internal Hi-Z / Internal Internal
input fixed at 0
input fixed at 0 input fixed at 0 input fixed at
0
GPIO selected
/
Maintain
GPIO selected
previous state Internal input
Hi-Z /
fixed at 0
Internal
Output
input fixed at
maintains
0
Hi-Z / Internal
Maintain
previous state
input fixed at 0
previous state
/ Internal input
fixed at 0
Setting
disabled
Hi-Z
SPL = 0
Maintain
previous state
GPIO
selected
Resource
other than
above
Q
selected
SPL = 1
Output
maintains
Hi-Z / Internal
previous state
input fixed at 0
/ Internal input
fixed at 0
O
P
SPL = 0
Hi-Z /
Input
enabled
Document Number: 002-05644 Rev. *C
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous state
Hi-Z /
Internal input
fixed at 0
Hi-Z /
Internal
Maintain
input fixed at previous state
0
Input
enabled
Input enabled
Maintain
previous state
Maintain
previous state
GPIO selected
Internal input
GPIO selected
fixed at 0
Hi-Z /
Internal
Output
input fixed at
maintains
0
Maintain
previous state
previous state
/ Internal input
fixed at 0
Page 50 of 95
Pin status type
CY9A130N Series
Function
group
CEC
enabled
Power-on
reset or
INITX
low-voltage
input state
detection
state
Power
supply
unstable
Device
internal
reset
state
Power supply stable
-
INITX = 0
INITX = 1
-
-
-
Setting
disabled
Setting
disabled
Setting
disabled
Run mode
or Sleep
mode state
Timer mode,
RTC mode, or
Stop mode state
Deep standby RTC mode
or Deep Standby Stop
mode state
Return from
Deep
Standby
mode state
Power
supply
stable
Power supply stable
Power supply stable
Power supply
stable
INITX = 1
INITX = 1
INITX = 1
INITX = 1
Maintain
previous
state
SPL = 0
Maintain
previous state
R
Setting
disabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Analog
output
selected
Setting
disabled
Setting
disabled
Setting
disabled
External
interrupt
enabled
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
GPIO
selected
Analog
output
selected
Setting
disabled
Resource
other than
above
selected
Hi-Z
GPIO
selected
Maintain
previous state
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Setting
disabled
Setting
disabled
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous state
Hi-Z /
Internal input
fixed at 0
*3
Maintain
previous
state
Resource
other than
above
selected
Hi-Z
T
Setting
disabled
Maintain
previous
state
Resource
other than
above
selected
S
Setting
disabled
Maintain
previous state
*3
Maintain
previous
state
Maintain
previous state
SPL = 0
SPL = 1
Maintain
Maintain
Maintain
previous
previous state previous state
state
Hi-Z /
Internal input
fixed at 0
WKUP
enabled
External
interrupt
enabled
selected
SPL = 1
WKUP input
enabled
Maintain
previous state
Hi-Z /
WKUP input
enabled
GPIO selected
GPIO selected
Internal input
fixed at 0
Hi-Z /
Internal
input fixed at
0
Output
maintains
Maintain
previous state
previous state
/ Internal input
fixed at 0
*4
Maintain
GPIO selected
GPIO selected
previous state Internal input
fixed at 0
Hi-Z /
Internal
input fixed at
0
Hi-Z /
Internal input
fixed at 0
Output
maintains
previous state
/ Internal input
fixed at 0
Maintain
previous state
*4
Hi-Z /
Internal input
fixed at 0
GPIO selected
Internal input
GPIO selected
fixed at 0
Hi-Z /
Internal
input fixed at
0
Output
maintains
Maintain
previous state
previous state
/ Internal input
fixed at 0
*1: Oscillation is stopped at Sub Run mode, Low-speed CR Run mode, Sub Sleep mode, Low-speed CR Sleep mode, Sub Timer
mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode.
*2: Oscillation is stopped at Stop mode and Deep Standby Stop mode.
*3: Maintain previous state at Timer mode. GPIO selected Internal input fixed at 0 at RTC mode, Stop mode.
*4: Maintain previous state at Timer mode. Hi-Z/Internal input fixed at 0 at RTC mode, Stop mode.
Document Number: 002-05644 Rev. *C
Page 51 of 95
CY9A130N Series
11. Electrical Characteristics
11.1 Absolute Maximum Ratings
Parameter
Rating
Symbol
Min
Unit
Max
Power supply voltage*1,*2
VCC
VSS - 0.5
VSS + 6.5
V
Analog power supply voltage*1,*3
AVCC
VSS - 0.5
VSS + 6.5
V
AVRH
VSS - 0.5
VSS + 6.5
V
VSS - 0.5
VCC + 0.5
(≤ 6.5 V)
V
VSS - 0.5
VSS + 6.5
V
1, 3
Analog reference voltage* *
Input voltage*1
VI
Analog pin input voltage*1
VIA
VSS - 0.5
AVCC + 0.5
(≤ 6.5 V)
V
Output voltage*1
VO
VSS - 0.5
VCC + 0.5
(≤ 6.5 V)
V
L level maximum output current*4
IOL
-
10
mA
L level average output current*5
IOLAV
-
4
mA
L level total maximum output current
∑IOL
-
100
mA
L level total average output current*6
∑IOLAV
-
50
mA
H level maximum output current*
4
IOH
-
- 10
mA
H level average output current*5
IOHAV
-
-4
mA
H level total maximum output current
∑IOH
-
- 100
mA
H level total average output current*6
∑IOHAV
-
- 50
mA
Power consumption
PD
-
400
mW
Storage temperature
TSTG
- 55
+ 150
C
Remarks
5 V tolerant
*1: These parameters are based on the condition that VSS = AVSS = 0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: Be careful not to exceed VCC + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100
ms period.
*6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms.
WARNING:
−
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Document Number: 002-05644 Rev. *C
Page 52 of 95
CY9A130N Series
11.2 Recommended Operating Conditions
Parameter
Symbol
Value
Conditions
Min
Max
Unit
Power supply voltage
VCC
-
1.8
5.5
V
Analog power supply voltage
AVCC
-
1.8
5.5
V
AVCC
V
2.7
Analog reference voltage
AVRH
-
Smoothing capacitor
CS
-
1
10
μF
TA
-
- 40
+ 85
C
Operating
Temperature
LQH080,
LQJ080,
LQI100,
PQH100
AVCC
Remarks
AVCC = VCC
AVCC ≥ 2.7 V
AVCC < 2.7 V
For built-in Regulator
*
*: See “C Pin” in “Handling Devices” for the smoothing capacitor.
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-05644 Rev. *C
Page 53 of 95
CY9A130N Series
11.3
11.3.1
DC Characteristics
Current Rating
(VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C)
Parameter
Symbol
Value
Pin
name
Conditions
Power
supply
current
VCC
ICCS
Max*4
Unit
Remarks
CPU: 20 MHz,
Peripheral: 20 MHz,
Flash memory 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
19
24
mA
*1, *5
CPU: 20 MHz,
Peripheral: clock stopped,
NOP operation
9.5
12.5
mA
*1, *5
High-speed
CR
Run mode
CPU/Peripheral: 4 MHz*2
Flash memory 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
4.5
5.5
mA
*1
Sub
Run mode
CPU/Peripheral: 32 kHz,
Flash memory 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
0.25
0.55
mA
*1, *6
Low-speed
CR
Run mode
CPU/Peripheral: 100 kHz,
Flash memory 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
0.3
0.95
mA
*1
PLL
Sleep mode
Peripheral: 20 MHz
8
10.5
mA
*1, *5
High-speed
CR
Sleep mode
Peripheral: 4 MHz*2
2
2.5
mA
*1
Sub
Sleep mode
Peripheral: 32 kHz
0.2
0.45
mA
*1, *6
Low-speed
CR
Sleep mode
Peripheral: 100 kHz
0.25
0.65
mA
*1
PLL
Run mode
ICC
Typ*3
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=3.3 V
*4: TA=+85°C, VCC=5.5 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-05644 Rev. *C
Page 54 of 95
CY9A130N Series
Parameter
Symbol
Pin
name
Conditions
Main
Timer mode
ICCT
Sub
Timer mode
ICCR
Power
supply
current
RTC mode
VCC
ICCH
ICCRD
ICCHD
Stop mode
Deep Standby
RTC mode
Deep Standby
Stop mode
Value
Typ*2
Max*3
Unit
Remarks
TA = + 25°C,
When LVD is off
0.9
3.3
mA
*1, *4
TA = + 85°C,
When LVD is off
1.5
3.5
mA
*1, *4
TA = + 25°C,
When LVD is off
7.5
60
μA
*1, *5
TA = + 85°C,
When LVD is off
16
150
μA
*1, *5
TA = + 25C,
When LVD is off
1.5
6.5
μA
*1, *5
TA = + 85C,
When LVD is off
6
89
μA
*1, *5
TA = + 25C,
When LVD is off
0.6
5
μA
*1
TA = + 85C,
When LVD is off
4.2
87
μA
*1
TA = + 25C,
When LVD is off
1.3
4.5
μA
*1, *5
TA = + 85C,
When LVD is off
3
32
μA
*1, *5
TA = + 25C,
When LVD is off
0.4
3
μA
*1
TA = + 85C,
When LVD is off
1.4
30
μA
*1
*1: When all ports are fixed.
*2: VCC=3.3 V
*3: VCC=5.5 V
*4: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*5: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-05644 Rev. *C
Page 55 of 95
CY9A130N Series
Low Voltage Detection Current
(VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40C to + 85C)
Parameter
Low-voltage
detection circuit
(LVD) power
supply current
Symbol
ICCLVD
Pin
name
VCC
Value
Conditions
Typ*
Unit
Max
For occurrence of reset or for
occurrence of interrupt in normal mode
operation
10
For occurrence of reset and for
occurrence of interrupt in normal mode
operation
14
30
μA
For occurrence of interrupt in
low-power mode operation
0.3
2
μA
Remarks
μA
20
When not
detected
When not
detected
*: When VCC=3.3 V
Flash Memory Current
(VCC = 1.8 V to 5.5 V, VSS = 0 V, TA = - 40°C to + 85°C)
Parameter
Flash memory
write/erase
current
Pin
name
Symbol
ICCFLASH
VCC
Value
Conditions
At Write/Erase
Typ
10.8
Max
11.9
Unit
Remarks
mA
A/D Converter Current
(VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C)
Parameter
Power supply
current
Reference power
supply current
Pin
name
Symbol
ICCAD
ICCAVRH
AVCC
AVRH
Value
Conditions
Typ
Max
Unit
At 1unit
operation
1.4
2.5
mA
At stop
0.1
0.35
μA
At 1unit
operation
AVRH=5.5 V
0.5
1.5
mA
At stop
0.1
0.3
μA
Remarks
D/A Converter Current
(VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C)
Parameter
Power supply
current
Pin
name
Symbol
IDDA
AVCC
IDSA
Value
Conditions
Typ
Max
Unit
Remarks
At D/A 1ch.
operation
AVCC=3.3 V
314
440
μA
*1, *2
At D/A 1ch.
operation
AVCC=5.0 V
476
670
μA
*1, *2
At D/A stop
-
1.0
μA
*1
*1: No-load
*2: Generates the max current by the CODE about 0x200
Document Number: 002-05644 Rev. *C
Page 56 of 95
CY9A130N Series
11.3.2
Pin Characteristics
(VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
H level input
voltage
(hysteresis
input)
L level input
voltage
(hysteresis
input)
H level
output voltage
L level
output voltage
VIHS
VILS
VOH
Typ
MD0, MD1,
PE0, PE2,
PE3, P46, P47,
P3A, P3B,
P3C,
P3D, P3E,
P3F,
INITX
-
VCC × 0.8
-
VCC + 0.3
V
P0A, P0B,
P0C, P4C,
P60,
P80, P81, P82
-
VCC × 0.7
-
VSS + 5.5
V
CMOS
hysteresis
input pins other
than the above
-
VCC × 0.7
-
VCC + 0.3
V
MD0, MD1,
PE0, PE2,
PE3,
P46, P47,
INITX
-
VSS - 0.3
-
VCC × 0.2
V
CMOS
hysteresis
input pins other
than the above
-
VSS - 0.3
-
VCC × 0.3
V
VCC - 0.5
-
VCC
V
VSS
-
0.4
V
Pxx
VCC ≥ 4.5 V,
IOH = - 4 mA
5V tolerant
VCC < 4.5 V,
IOH = - 1 mA
VOL
Pxx
VCC ≥ 4.5 V,
IOL = 4 mA
VCC < 4.5 V,
IOL = 2 mA
-
-
-5
-
+5
IIL
CEC0,
CEC1
VCC = AVCC =
AVRH = VSS =
AVSS = 0.0 V
-
-
+ 1.8
Pull-up resistor
value
RPU
Pull-up pin
VCC ≥ 4.5 V
25
50
100
VCC 4.5 V
40
100
400
Input
capacitance
CIN
-
-
5
15
Input leak
current
Remarks
Max
Other than
VCC, VSS,
AVCC, AVSS,
AVRH
Document Number: 002-05644 Rev. *C
μA
kΩ
pF
Page 57 of 95
CY9A130N Series
11.4 AC Characteristics
11.4.1
Main Clock Input Characteristics
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Parameter
Input frequency
Pin
name
Symbol
fCH
X0,
X1
Value
Conditions
Min
Max
Unit
VCC ≥ 2.0 V
4
20
MHz
VCC 2.0 V
4
4
MHz
VCC ≥ 4.5 V
4
20
MHz
VCC 4.5 V
4
16
MHz
VCC ≥ 4.5 V
50
250
ns
VCC 4.5 V
62.5
250
ns
Remarks
When crystal oscillator is
connected
When using external
clock
When using external
clock
Input clock cycle
tCYLH
Input clock pulse width
-
PWH/tCYLH,
PWL/tCYLH
45
55
%
When using external
clock
Input clock rising time
and falling time
tCF,
tCR
-
-
5
ns
When using external
clock
Internal operating
clock*1
frequency
Internal operating
clock*1
cycle time
fCM
-
-
-
20
MHz
Master clock
fCC
-
-
-
20
MHz
Base clock (HCLK/FCLK)
fCP0
-
-
-
20
MHz
APB0 bus clock*2
fCP1
-
-
-
20
MHz
APB1 bus clock*2
fCP2
-
-
-
20
MHz
APB2 bus clock*2
tCYCC
-
-
50
-
ns
Base clock (HCLK/FCLK)
tCYCP0
-
-
50
-
ns
APB0 bus clock*2
tCYCP1
-
-
50
-
ns
APB1 bus clock*2
tCYCP2
-
-
50
-
ns
APB2 bus clock*2
*1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual Main part
(002-05586).
*2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet.
X0
Document Number: 002-05644 Rev. *C
Page 58 of 95
CY9A130N Series
11.4.2
Sub Clock Input Characteristics
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Parameter
Input frequency
Pin
name
Symbol
Value
Conditions
Min
Typ
Max
Unit
Remarks
-
-
32.768
-
kHz
When crystal oscillator
is connected
-
32
-
100
kHz
When using external
clock
-
10
-
31.25
μs
When using external
clock
PWH/tCYLL,
PWL/tCYLL
45
-
55
%
When using external
clock
fCL
Input clock cycle
tCYLL
Input clock pulse
width
-
X0A,
X1A
tCYLL
0.8 × VBAT
0.8 × VBAT
0.2 × VBAT
X0A
PWH
11.4.3
0.8 × VBAT
0.2 × VBAT
PWL
Built-in CR Oscillation Characteristics
Built-in High-speed CR
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Parameter
Symbol
VCC ≥ 2.2 V
Clock frequency
fCRH
VCC < 2.2 V
Frequency
stabilization time
Value
Conditions
tCRWT
Min
Typ
Max
TA = + 25C
3.92
4
4.08
TA = - 40C to +
85C
3.8
4
4.2
TA = - 40C to +
85C
2.3
-
7.03
TA = + 25C
3.4
4
4.6
TA = - 40C to +
85C
3.16
4
4.84
TA = - 40C to +
85C
2.3
-
7.03
-
-
10
-
Unit
MH
z
Remarks
When trimming*1
When not trimming
When trimming*1
MH
z
When not trimming
μs
*2
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value.
This period is able to use High-speed CR clock as source clock.
Built-in Low-speed CR
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Parameter
Clock frequency
Symbo
l
fCRL
Condition
-
Document Number: 002-05644 Rev. *C
Value
Min
50
Typ
100
Max
150
Unit
Remarks
kHz
Page 59 of 95
CY9A130N Series
11.4.4
Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Value
Parameter
Symbol
Unit
Min
Typ
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
200
-
-
μs
PLL input clock frequency
fPLLI
4
-
20
MHz
PLL multiplication rate
-
1
-
5
multiplier
PLL macro oscillation clock frequency
fPLLO
10
-
20
MHz
fCLKPLL
-
-
20
MHz
Main PLL clock frequency*
2
Remarks
Max
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
11.4.5
Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock of the Main
PLL)
(VCC = 2.2V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Value
Parameter
Symbol
Unit
Min
Typ
Remarks
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
200
-
-
μs
PLL input clock frequency
fPLLI
3.8
4
4.2
MHz
PLL multiplication rate
-
3
-
4
multiplier
PLL macro oscillation clock frequency
fPLLO
11.4
-
16.8
MHz
Main PLL clock frequency*2
fCLKPLL
-
-
16.8
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
Note:
−
Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency has been trimmed.
When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the
master clock from exceeding the maximum frequency.
Main PLL connection
Main clock (CLKMO)
High-speed CR clock (CLKHC)
K
divider
PLL input
clock
PLL macro
oscillation clock
Main
PLL
M
divider
Main PLL
clock
(CLKPLL)
N
divider
Document Number: 002-05644 Rev. *C
Page 60 of 95
CY9A130N Series
11.4.6
Reset Input Characteristics
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Parameter
Symbol
Pin name
Value
Conditions
Min
Reset input time
11.4.7
tINITX
INITX
-
Unit
Remarks
Max
500
-
ns
1.5
-
ms
When RTC mode or Stop
mode
1.5
-
ms
When Deep Standby mode
Power-on Reset Timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Value
Parameter
Symbol
Pin name
Unit
Min
Typ
Remarks
Max
Power supply rising time
dV/dt
0.1
-
-
V/ms
Power supply shut down time
tOFF
1
-
-
ms
Reset release voltage
VDETH
1.44
1.60
1.76
V
When voltage rises
1.39
1.55
1.71
V
When voltage drops
VCC
Reset detection voltage
VDETL
Time until releasing
Power-on reset
tPRT
0.46
-
11.4
ms
dV/dt ≥ 0.1 mV/μs
Reset detection delay time
tOFFD
-
-
0.4
ms
dV/dt ≥ -0.04 mV/μs
VDETH
VDETL
VCC
dV
0.2V
dt
0.2V
tOFF
tPRT
Internal reset
CPU Operation
Document Number: 002-05644 Rev. *C
Reset active
tOFFD
Release
Reset active
start
Page 61 of 95
CY9A130N Series
11.4.8
Base Timer Input Timing
Timer input timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Parameter
Input pulse width
Symbol
tTIWH,
tTIWL
Pin name
Conditions
TIOAn/TIOBn
(when using as
ECK, TIN)
-
tTIWH
Value
Min
Max
2tCYCP
-
Unit
Remarks
ns
tTIWL
ECK
VIHS
TIN
VIHS
VILS
VILS
Trigger input timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Parameter
Input pulse width
Symbol
tTRGH,
tTRGL
Pin name
TIOAn/TIOBn
(when using as
TGIN)
-
VIHS
Min
2tCYCP
tTRGH
TGIN
Value
Conditions
Max
-
Unit
Remarks
ns
tTRGL
VIHS
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet.
Document Number: 002-05644 Rev. *C
Page 62 of 95
CY9A130N Series
11.4.9
CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Parameter
Symbol
Pin
name
Conditions
-
-
-
Baud rate
Serial clock cycle
time
tSCYC
SCKx
SCK SOT
delay time
tSLOVI
SCKx,
SOTx
VCC 2.7 V
2.7 V ≤VCC 4.5 V
VCC ≥ 4.5 V
Unit
Min
Max
Min
Max
Min
Max
-
5
-
5
-
5
Mbps
4tCYCP
-
4tCYCP
-
4tCYCP
-
ns
-40
+40
-30
+30
-20
+20
ns
75
-
50
-
30
-
ns
Master mode
SIN SCK setup
time
tIVSHI
SCKx,
SINx
SCK SIN hold
time
tSHIXI
SCKx,
SINx
0
-
0
-
0
-
ns
Serial clock L pulse
width
tSLSH
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock H pulse
width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
tCYCP + 10
-
ns
SCK SOT
delay time
tSLOVE
SCKx,
SOTx
-
75
-
50
-
30
ns
SIN SCK setup
time
tIVSHE
SCKx,
SINx
10
-
10
-
10
-
ns
SCK SIN hold
time
tSHIXE
SCKx,
SINx
20
-
20
-
20
-
ns
SCK falling time
tF
SCKx
-
5
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
-
5
ns
Slave mode
Notes:
−
The above characteristics apply to clock synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 50 pF.
Document Number: 002-05644 Rev. *C
Page 63 of 95
CY9A130N Series
tSCYC
SCK
VOH
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
Master mode
tSHSL
SCK
VIH
VIH
VIL
tR
SOT
tSLSH
tF
VIL
VIL
tSHOVE
VOH
VOL
tIVSLE
SIN
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
Document Number: 002-05644 Rev. *C
Page 64 of 95
CY9A130N Series
CSIO (SPI = 0, SCINV = 1)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Parameter
Symbol
Pin
name
Conditions
-
-
-
Baud rate
VCC 2.7 V
2.7 V ≤VCC 4.5 V
VCC ≥ 4.5 V
Unit
Min
Max
Min
Max
Min
Max
-
5
-
5
-
5
Mbps
4tCYCP
-
4tCYCP
-
4tCYCP
-
ns
-40
+40
-30
+30
-20
+20
ns
75
-
50
-
30
-
ns
Serial clock cycle
time
tSCYC
SCKx
SCK SOT
delay time
tSHOVI
SCKx,
SOTx
SIN SCK setup
time
tIVSLI
SCKx,
SINx
SCK SIN hold
time
tSLIXI
SCKx,
SINx
0
-
0
-
0
-
ns
Serial clock L pulse
width
tSLSH
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock H pulse
width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
tCYCP + 10
-
ns
SCK SOT
delay time
tSHOVE
SCKx,
SOTx
-
75
-
50
-
30
ns
SIN SCK setup
time
tIVSLE
SCKx,
SINx
10
-
10
-
10
-
ns
SCK SIN hold
time
tSLIXE
SCKx,
SINx
20
-
20
-
20
-
ns
SCK falling time
tF
SCKx
-
5
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
-
5
ns
Master
mode
Slave mode
Notes:
−
The above characteristics apply to clock synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 50 pF.
Document Number: 002-05644 Rev. *C
Page 65 of 95
CY9A130N Series
tSCYC
SCK
VOH
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
Master mode
tSHSL
SCK
VIH
VIH
VIL
tR
SOT
tSLSH
tF
VIL
VIL
tSHOVE
VOH
VOL
tIVSLE
SIN
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
Document Number: 002-05644 Rev. *C
Page 66 of 95
CY9A130N Series
CSIO (SPI = 1, SCINV = 0)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Parameter
Symbol
Pin
name
Conditions
-
-
-
Baud rate
VCC 2.7 V
2.7 V ≤VCC 4.5 V
VCC ≥ 4.5 V
Unit
Min
Max
Min
Max
Min
Max
-
5
-
5
-
5
Mbps
Serial clock cycle
time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
4tCYCP
-
ns
SCK SOT
delay time
tSHOVI
SCKx,
SOTx
-40
+40
-30
+30
-20
+20
ns
SIN SCK
setup time
tIVSLI
SCKx,
SINx
75
-
50
-
30
-
ns
SCK SIN
hold time
tSLIXI
SCKx,
SINx
0
-
0
-
0
-
ns
SOT SCK
delay time
tSOVLI
SCKx,
SOTx
2tCYCP - 30
-
2tCYCP - 30
-
2tCYCP - 30
-
ns
Serial clock L
pulse width
tSLSH
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock H
pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
tCYCP + 10
-
ns
SCK SOT
delay time
tSHOVE
SCKx,
SOTx
-
75
-
50
-
30
ns
SIN SCK
setup time
tIVSLE
SCKx,
SINx
10
-
10
-
10
-
ns
SCK SIN
hold time
tSLIXE
SCKx,
SINx
20
-
20
-
20
-
ns
SCK falling time
tF
SCKx
-
5
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
-
5
ns
Master
mode
Slave mode
Notes:
−
The above characteristics apply to clock synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 50 pF.
Document Number: 002-05644 Rev. *C
Page 67 of 95
CY9A130N Series
tSCYC
VOH
SCK
VOL
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
Master mode
tSLSH
SCK
SOT
VIH
VIL
VIL
tF
*
VOH
VOL
tR
tIVSLE
SIN
tSHSL
VIH
VIH
tSHOVE
VOH
VOL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-05644 Rev. *C
Page 68 of 95
CY9A130N Series
CSIO (SPI = 1, SCINV = 1)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Parameter
Symbol
Pin
name
Conditions
-
-
-
Baud rate
VCC 2.7 V
2.7 V ≤VCC 4.5 V
VCC ≥ 4.5 V
Unit
Min
Max
Min
Max
Min
Max
-
5
-
5
-
5
Mbps
Serial clock cycle
time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
4tCYCP
-
ns
SCK SOT
delay time
tSLOVI
SCKx,
SOTx
-40
+40
-30
+30
-20
+20
ns
SIN SCK
setup time
tIVSHI
SCKx,
SINx
75
-
50
-
30
-
ns
SCK SIN
hold time
tSHIXI
SCKx,
SINx
0
-
0
-
0
-
ns
SOT SCK
delay time
tSOVHI
SCKx,
SOTx
2tCYCP - 30
-
2tCYCP - 30
-
2tCYCP - 30
-
ns
Serial clock L
pulse width
tSLSH
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock H
pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
tCYCP + 10
-
ns
SCK SOT
delay time
tSLOVE
SCKx,
SOTx
-
75
-
50
-
30
ns
SIN SCK
setup time
tIVSHE
SCKx,
SINx
10
-
10
-
10
-
ns
SCK SIN
hold time
tSHIXE
SCKx,
SINx
20
-
20
-
20
-
ns
SCK falling time
tF
SCKx
-
5
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
-
5
ns
Master mode
Slave mode
Notes:
−
The above characteristics apply to clock synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance CL = 50 pF.
Document Number: 002-05644 Rev. *C
Page 69 of 95
CY9A130N Series
tSCYC
VOH
SCK
tSOVHI
SOT
tSLOVI
VOH
VOL
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
Master mode
tR
SCK
VIL
tF
tSHSL
VIH
VIH
tSLSH
VIL
VIL
tSLOVE
SOT
VOH
VOL
VOH
VOL
tIVSHE
SIN
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-05644 Rev. *C
Page 70 of 95
CY9A130N Series
UART external clock input (EXT = 1)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Parameter
Symbol
Value
Conditions
Min
Unit
Serial clock L pulse width
tSLSH
tCYCP + 10
-
ns
Serial clock H pulse width
tSHSL
tCYCP + 10
-
ns
SCK falling time
tF
-
5
ns
SCK rising time
tR
-
5
ns
CL = 50 pF
tF
tR
t
t
SHSL
SCK
VIL
Document Number: 002-05644 Rev. *C
Remarks
Max
V
IH
SLSH
V
IH
VI L
VIL
V
IH
Page 71 of 95
CY9A130N Series
11.4.10 External Input Timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Max
Unit
ADTG
FRCKx
A/D converter trigger input
-
2tCYCP*
1
1
-
ns
Waveform generator
-
ns
PPG IGBT mode
-
ns
ICxx
Input pulse width
tINH,
tINL
Remarks
Free-run timer input clock
Input capture
DTTIxX
-
2tCYCP*
IGTRG
-
2tCYCP*1
1
INTxx,
NMIX
*2
2tCYCP + 100*
-
ns
*3
500
-
ns
External interrupt,
NMI
WKUPx
*4
500
-
ns
Deep standby wake up
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, PPG, External interrupt, Deep Standby mode
Controller are connected to, see Block Diagram in this data sheet.
*2: When in Run mode, in Sleep mode.
*3: When in Timer mode, in RTC mode, in Stop mode.
*4: When in Deep Standby RTC mode, in Deep Standby Stop mode.
Document Number: 002-05644 Rev. *C
Page 72 of 95
CY9A130N Series
11.4.11 I2C Timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Parameter
Symbol
Conditions
Standard-mode
Fast-mode
SCL clock frequency
fSCL
(Repeated) START condition hold
time
SDA SCL
tHDSTA
4.0
-
0.6
-
μs
SCL clock L width
tLOW
4.7
-
1.3
-
μs
SCL clock H width
tHIGH
4.0
-
0.6
-
μs
(Repeated) START condition
setup time
SCL SDA
tSUSTA
4.7
-
0.6
-
μs
Data hold time
SCL SDA
tHDDAT
0
3.45*2
0
0.9*3
μs
Data setup time
SDA SCL
tSUDAT
250
-
100
-
ns
STOP condition setup time
SCL SDA
tSUSTO
4.0
-
0.6
-
μs
Bus free time between
STOP condition and
START condition
tBUF
4.7
-
1.3
-
μs
Noise filter
tSP
2tCYCP*4
-
2tCYCP*4
-
ns
CL = 50 pF,
R = (VP/IOL)*1
-
Max
100
Min
0
Max
400
Unit
Min
0
Remarks
kHz
*1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of
tSUDAT ≥ 250 ns.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number which I2C is connected to, see Block Diagram in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
Document Number: 002-05644 Rev. *C
Page 73 of 95
CY9A130N Series
11.4.12 JTAG Timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Parameter
Symbol
Pin name
Conditions
15
-
ns
15
-
ns
VCC ≥ 4.5 V
-
30
2.7 V ≤VCC 4.5 V
-
45
VCC 2.7 V
-
60
TCK,
TMS,TDI
VCC ≥ 4.5 V
TMS,TDI hold time tJTAGH
TCK,
TMS,TDI
VCC ≥ 4.5 V
TDO delay time
TCK,
TDO
tJTAGD
Unit
Max
tJTAGS
TMS,TDI setup
time
Value
Min
VCC 4.5 V
VCC 4.5 V
Remarks
ns
Note:
−
When the external load capacitance CL = 50 pF.
TCK
TMS/TDI
TDO
Document Number: 002-05644 Rev. *C
Page 74 of 95
CY9A130N Series
11.5 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(VCC = AVCC = 2.7V to 3.6V, VSS = AVSS = AVRL = 0V)
Parameter
Pin
name
Symbol
Resolution
-
-
Integral Nonlinearity
INL
-
Differential Nonlinearity
DNL
-
Zero transition voltage
VZT
ANxx
Full-scale transition voltage
VFST
ANxx
Conversion time*1
Sampling time*2
-
tS
-
-
Value
Unit
Remarks
Min
Typ
Max
-
-
12
bit
-
± 2.5
± 3.0
LSB
AVCC ≥ 2.7 V
-
± 3.5
± 4.0
LSB
AVCC < 2.7 V
-
± 1.8
± 1.9
LSB
AVCC ≥ 2.7 V
-
± 2.7
± 2.9
LSB
AVCC < 2.7 V
-
±9
± 20
mV
-
AVRH ± 9
AVRH ± 20
mV
-
-
μs
-
10
μs
-
1000
ns
1
μs
15
pF
1.0
4.0
0.3
1.2
50
Compare clock cycle*3
tCCK
-
Period of operation enable
state transitions
tSTT
-
-
-
Analog input capacity
CAIN
-
-
-
200
RAIN
-
-
-
Interchannel disparity
-
-
-
-
Analog port input leak current
-
ANxx
-
Analog input voltage
-
ANxx
AVSS
Reference voltage
-
AVRH
1.6
kΩ
4.0
2.7
AVCC
AVCC < 2.7 V
AVCC ≥ 2.7 V
AVCC < 2.7 V
AVCC ≥ 2.7 V
AVCC < 2.7 V
AVCC ≥ 4.5 V
0.9
Analog input resistor
AVCC ≥ 2.7 V
2.7 V ≤ AVCC < 4.5 V
AVCC < 2.7 V
4
LSB
-
0.3
μA
-
AVRH
V
-
AVCC
V
AVCC ≥ 2.7 V
AVCC < 2.7 V
*1: The conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is the following.
AVCC ≥ 2.7 V, HCLK=20 MHz
sampling time: 0.3 μs, compare time: 0.7 μs
AVCC < 2.7 V, HCLK=20 MHz
sampling time: 1.2 μs, compare time: 2.8 μs
Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK).
For setting*4 of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual
Analog Macro Part.
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing.
For the number of the APB bus to which the A/D Converter is connected, see Block Diagram.
The Base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: A necessary sampling time changes by external impedance.
Ensure to set the sampling time to satisfy (Equation 1).
*3: The compare time (tC) is the value of (Equation 2).
Document Number: 002-05644 Rev. *C
Page 75 of 95
CY9A130N Series
ANxx
Analog input pin
Analog
signal source
REXT
Comparator
RAIN
CAIN
(Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9
tS:
Sampling time
RAIN:
Input resistor of A/D = 0.9 kΩ at 4.5 V ≤ AVCC ≤ 5.5 V
Input resistor of A/D = 1.6 kΩ at 2.7 V ≤ AVCC < 4.5 V
Input resistor of A/D = 4.0 kΩ at 1.8 V ≤ AVCC < 2.7 V
CAIN:
Input capacity of A/D = 15 pF at 1.8 V ≤ AVCC ≤ 5.5 V
REXT:
Output impedance of external circuit
(Equation 2) tC = tCCK × 14
tC:
Compare time
tCCK:
Compare clock cycle
Document Number: 002-05644 Rev. *C
Page 76 of 95
CY9A130N Series
Definition of 12-bit A/D Converter Terms
Resolution:
Analog variation that is recognized by an A/D converter.
Integral Nonlinearity:
Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.
Differential Nonlinearity:
Deviation from the ideal value of the input voltage that is required to
change the output code by 1 LSB.
Integral Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
Differential Nonlinearity
Actual conversion
characteristics
Ideal characteristics
0x002
0x001
0xN
Actual conversion
characteristics
Ideal characteristics
Actual conversion characteristics
AVRH
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
N:
VZT:
VFST:
VNT:
(Actually-measured
value)
0x(N-2)
AVSS
Analog input
1LSB =
(Actually-measured
value)
VNT
VZT (Actually-measured value)
AVSS
V(N+1)T
0x(N-1)
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-05644 Rev. *C
Page 77 of 95
CY9A130N Series
11.6 10-bit D/A Converter
Electrical Characteristics for the D/A Converter
(VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C)
Parameter
Symbol
Pin name
Value
Unit
Remarks
Min
Typ
Max
-
-
10
bit
tC20
0.37
0.53
0.69
μs
Load 20 pF
tC100
1.87
2.67
3.47
μs
Load 100 pF
Integral Nonlinearity
INL
-4.0
-
+4.0
LSB
*
Differential Nonlinearity
DNL
-0.9
-
+0.9
LSB
*
Output Voltage offset
VOFF
Resolution
Conversion time
-
Analog output impedance
RO
Output undefined period
tR
DAx
-
-
10.0
mV
Code is 0x000
-50.0
-
+5.5
mV
Code is 0x3FF
2.45
3.50
4.55
kΩ
D/A operation
5.0
9.0
-
MΩ
D/A stop
-
-
250
ns
*: No-load
Document Number: 002-05644 Rev. *C
Page 78 of 95
CY9A130N Series
11.7 Low-Voltage Detection Characteristics
11.7.1
Low-Voltage Detection Reset
(TA = - 40C to + 85C)
Parameter
Symbol
Conditions
Value
Unit
Typ
Max
1.43
1.53
1.63
V
When voltage drops
1.53
1.63
1.73
V
When voltage rises
1.80
1.93
2.06
V
When voltage drops
1.90
2.03
2.16
V
When voltage rises
Detected voltage
VDLR
Released voltage
VDHR
Detected voltage
VDLR
Released voltage
VDHR
LVD stabilization wait
time
tLVDRW
-
-
-
633 × tCYCP*
μs
Detection delay time
tLVDRD
dV/dt ≥ -4 mV/μs
-
-
60
μs
SVHR = 0001
SVHR = 0100
Remarks
Min
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05644 Rev. *C
Page 79 of 95
CY9A130N Series
11.7.2
Interrupt of Low-Voltage Detection
Normal Mode
(TA = - 40C to + 85C)
Parameter
Symbol
Conditions
Value
Unit
Typ
Max
1.87
2.00
2.13
V
When voltage drops
1.97
2.10
2.23
V
When voltage rises
1.96
2.10
2.24
V
When voltage drops
2.06
2.20
2.34
V
When voltage rises
2.05
2.20
2.35
V
When voltage drops
2.15
2.30
2.45
V
When voltage rises
2.15
2.30
2.45
V
When voltage drops
2.25
2.40
2.55
V
When voltage rises
2.24
2.40
2.56
V
When voltage drops
2.34
2.50
2.66
V
When voltage rises
2.33
2.50
2.67
V
When voltage drops
2.43
2.60
2.77
V
When voltage rises
2.43
2.60
2.77
V
When voltage drops
2.53
2.70
2.87
V
When voltage rises
2.61
2.80
2.99
V
When voltage drops
2.71
2.90
3.09
V
When voltage rises
2.80
3.00
3.20
V
When voltage drops
2.90
3.10
3.30
V
When voltage rises
2.99
3.20
3.41
V
When voltage drops
3.09
3.30
3.51
V
When voltage rises
3.36
3.60
3.84
V
When voltage drops
3.46
3.70
3.94
V
When voltage rises
3.45
3.70
3.95
V
When voltage drops
3.55
3.80
4.05
V
When voltage rises
3.73
4.00
4.27
V
When voltage drops
3.83
4.10
4.37
V
When voltage rises
3.83
4.10
4.37
V
When voltage drops
3.93
4.20
4.47
V
When voltage rises
3.92
4.20
4.48
V
When voltage drops
4.02
4.30
4.58
V
When voltage rises
Detected voltage
VDLI
Released voltage
VDHI
Detected voltage
VDLI
Released voltage
VDHI
Detected voltage
VDLI
Released voltage
VDHI
Detected voltage
VDLI
Released voltage
VDHI
Detected voltage
VDLI
Released voltage
VDHI
Detected voltage
VDLI
Released voltage
VDHI
Detected voltage
VDLI
Released voltage
VDHI
Detected voltage
VDLI
Released voltage
VDHI
Detected voltage
VDLI
Released voltage
VDHI
Detected voltage
VDLI
Released voltage
VDHI
Detected voltage
VDLI
Released voltage
VDHI
Detected voltage
VDLI
Released voltage
VDHI
Detected voltage
VDLI
Released voltage
VDHI
Detected voltage
VDLI
Released voltage
VDHI
Detected voltage
VDLI
Released voltage
VDHI
LVD stabilization wait
time
tLVDIW
-
-
-
633 × tCYCP*
μs
Detection delay time
tLVDID
dV/dt ≥ 4mV/μs
-
-
60
μs
SVHI = 0000
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0101
SVHI = 0110
SVHI = 0111
SVHI = 1000
SVHI = 1001
SVHI = 1010
SVHI = 1011
SVHI = 1100
SVHI = 1101
SVHI = 1110
Remarks
Min
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05644 Rev. *C
Page 80 of 95
CY9A130N Series
Low power mode
(TA = - 40C to + 85C)
Parameter
Symbol
Conditions
Value
Unit
Remarks
2.20
V
When voltage drops
2.10
2.30
V
When voltage rises
2.10
2.31
V
When voltage drops
1.99
2.20
2.41
V
When voltage rises
1.98
2.20
2.42
V
When voltage drops
2.08
2.30
2.52
V
When voltage rises
2.07
2.30
2.53
V
When voltage drops
2.17
2.40
2.63
V
When voltage rises
2.16
2.40
2.64
V
When voltage drops
2.26
2.50
2.74
V
When voltage rises
2.25
2.50
2.75
V
When voltage drops
2.35
2.60
2.85
V
When voltage rises
2.34
2.60
2.86
V
When voltage drops
2.44
2.70
2.96
V
When voltage rises
2.52
2.80
3.08
V
When voltage drops
2.62
2.90
3.18
V
When voltage rises
2.70
3.00
3.30
V
When voltage drops
2.80
3.10
3.40
V
When voltage rises
2.88
3.20
3.52
V
When voltage drops
2.98
3.30
3.62
V
When voltage rises
3.24
3.60
3.96
V
When voltage drops
3.34
3.70
4.06
V
When voltage rises
3.33
3.70
4.07
V
When voltage drops
3.43
3.80
4.17
V
When voltage rises
3.60
4.00
4.40
V
When voltage drops
3.70
4.10
4.50
V
When voltage rises
3.69
4.10
4.51
V
When voltage drops
3.79
4.20
4.61
V
When voltage rises
3.78
4.20
4.62
V
When voltage drops
3.88
4.30
4.72
V
When voltage rises
Min
Typ
Max
1.80
2.00
1.90
1.89
Detected voltage
VDLIL
Released voltage
VDHIL
Detected voltage
VDLIL
Released voltage
VDHIL
Detected voltage
VDLIL
Released voltage
VDHIL
Detected voltage
VDLIL
Released voltage
VDHIL
Detected voltage
VDLIL
Released voltage
VDHIL
Detected voltage
VDLIL
Released voltage
VDHIL
Detected voltage
VDLIL
Released voltage
VDHIL
Detected voltage
VDLIL
Released voltage
VDHIL
Detected voltage
VDLIL
Released voltage
VDHIL
Detected voltage
VDLIL
Released voltage
VDHIL
Detected voltage
VDLIL
Released voltage
VDHIL
Detected voltage
VDLIL
Released voltage
VDHIL
Detected voltage
VDLIL
Released voltage
VDHIL
Detected voltage
VDLIL
Released voltage
VDHIL
Detected voltage
VDLIL
Released voltage
VDHIL
LVD stabilization wait
time
tLVDILW
-
-
-
8039 × tCYCP*
μs
Detection delay time
tLVDILD
dV/dt ≥ - 0.4 mV/μs
-
-
800
μs
SVHI = 0000
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0101
SVHI = 0110
SVHI = 0111
SVHI = 1000
SVHI = 1001
SVHI = 1010
SVHI = 1011
SVHI = 1100
SVHI = 1101
SVHI = 1110
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05644 Rev. *C
Page 81 of 95
CY9A130N Series
11.8 Flash Memory Write/Erase Characteristics
Write / Erase time
(VCC = 2.0V to 5.5V, TA = - 40C to + 85C)
Parameter
Value
Typ*
Max*
Large Sector
1.6
7.5
Small Sector
0.4
2.1
Half word (16-bit)
write time
25
Chip erase time
4
Sector erase
time
Unit
Remarks
s
Includes write time prior to internal erase
400
μs
Not including system-level overhead time.
19.2
s
Includes write time prior to internal erase
*: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000 cycle of erase/write.
Write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
1,000
20 *
10,000
10 *
100,000
5*
Remarks
*: At average + 85C
Document Number: 002-05644 Rev. *C
Page 82 of 95
CY9A130N Series
11.9 Return Time from Low-Power Consumption Mode
11.9.1 Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
Typ
Sleep mode
Max*
40
80
μs
630
1260
μs
Sub Timer mode
630
1260
μs
RTC mode,
Stop mode
1083
2100
μs
Deep Standby RTC mode
Deep Standby Stop mode
1099
2127
μs
Low-speed CR Timer mode
Remarks
μs
tCYCC
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Unit
tICNT
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*)
External
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-05644 Rev. *C
Page 83 of 95
CY9A130N Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
resource
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
−
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the
Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family
Peripheral Manual.
Document Number: 002-05644 Rev. *C
Page 84 of 95
CY9A130N Series
11.9.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
Unit
Typ
Max*
Sleep mode
359
647
μs
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
359
647
μs
929
1787
μs
Sub Timer mode
929
1787
μs
RTC/Stop mode
1099
2127
μs
Deep Standby RTC mode
Deep Standby Stop mode
1099
2127
μs
Low-speed CR Timer mode
tRCNT
Remarks
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Document Number: 002-05644 Rev. *C
Start
Page 85 of 95
CY9A130N Series
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
−
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the
Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family
Peripheral Manual.
−
The time during the power-on reset/low-voltage detection reset is excluded. See (6) Power-on Reset
Timing in 4. AC Characteristics in Electrical Characteristics for the detail on the time during the power-on
reset/low-voltage detection reset.
−
When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock
or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the Main PLL
clock stabilization wait time.
−
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-05644 Rev. *C
Page 86 of 95
CY9A130N Series
12. Ordering Information
Part number
On-chip
On-chip
Flash memory
SRAM
CY9AF131MPMC-G-SNE2
64 Kbyte
12 Kbyte
CY9AF132MPMC-G-SNE2
128 Kbyte
16 Kbyte
CY9AF131MPMC1-G-SNE2
64 Kbyte
12 Kbyte
CY9AF132MPMC1-G-SNE2
128 Kbyte
16 Kbyte
CY9AF131NPMC-G-SNE2
64 Kbyte
12 Kbyte
CY9AF132NPMC-G-SNE2
128 Kbyte
16 Kbyte
CY9AF131NPF-G-SNE1
64 Kbyte
12 Kbyte
CY9AF132NPF-G-SNE1
128 Kbyte
16 Kbyte
Document Number: 002-05644 Rev. *C
Package
Packing
Plastic LQFP
(0.5 mm pitch), 80-pin
(LQH080)
Plastic LQFP
(0.65 mm pitch), 80-pin
(LQJ080)
Plastic LQFP
(0.5 mm pitch), 100-pin
(LQI100)
Tray
Plastic QFP
(0.65 mm pitch), 100-pin
(PQH100)
Page 87 of 95
CY9A130N Series
13. Package Dimensions
Package Type
LQFP 80 (0.5mm pitch)
4
D
D1
60
Package Code
LQH080
5 7
41
41
40
61
60
40
61
21
80
5
7
E1
E
4
3
6
80
21
1
20
D
e
20
2 5 7
0.10 C A-B D
3
b
0.08
C A-B
1
BOTTOM VIEW
D
0.20 C A-B D
8
TOP VIEW
2
A
A
A'
0.08 C
SIDE VIEW
SYMBOL
SEATIN G
PLAN E
9
L1
L
0.25
A1
10
c
b
SECTION A-A'
DIM ENSIONS
M IN. NOM . M AX.
A
A1
1. 70
0.05
0.15
b
0.15
0.27
c
0.09
0.20
D
14.00 BSC.
D1
12.00 BSC.
e
0.50 BSC
E
14.00 BSC.
E1
12.00 BSC.
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
PACKAGE OUTLINE, 80 LEAD LQFP
12.0X12.0X1.7 M M LQH080 Rev **
Document Number: 002-05644 Rev. *C
002-11501 **
Page 88 of 95
CY9A130N Series
Package Type
LQFP 80 (0.65mm pitch)
Package Code
LQJ080
D
D1
60
4
5 7
41
41
61
40
E1
60
40
61
21
80
E
5
7
4
3
6
80
21
1
20
20
2 5 7
1
0.1 0 C A-B D
3
e
0.2 0 C A-B D
b
dd d
C A-B
D
8
2
A
A
A'
0.1 0 C
SEATING
PLAN E
9
θ
c
L1
0.2 5
A1
10
b
SECTION A-A'
L
SYM BOL
DIM ENSIONS
M IN. NOM . M AX.
1.70
A
A1
0.00
0.20
b
0.16
c
0.09
0.32
0.38
0.20
D
16.00 BSC
D1
14.00 BSC
e
0.65 BSC
E
16.00 BSC
E1
14.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
θ
0°
8°
002-14043 **
PACKAGE OUTLINE, 80 LEAD LQFP
14.0X14.0X1.7 M M LQJ080 REV**
Document Number: 002-05644 Rev. *C
Page 89 of 95
CY9A130N Series
Package Type
LQFP 100
Package Code
LQI100
D
D1
75
4
D
5 7
51
D1
51
50
76
4
5 7
75
50
76
E1 E
5 4
7
E1 E
5 4
7
3
6
26
100
1
26
25
1
25
2 5 7
e
100
BOTTOM VIEW
0.1 0 C A-B D
3
0.2 0 C A-B D
b
TOP VIEW
8
0.0 8
C A-B
D
2
A
9
A
SEATIN G
PLA N E
A'
0.25
L1
0.0 8 C
c
A1
b
10
SECTIO N A-A '
L
SIDE VIEW
SYM BOL
DETAIL A
DIM ENSIONS
M IN.
NOM . M AX.
1.70
A
A1
0.05
b
0.15
0.15
0.27
c
0.09
0.20
D
16.00 BSC
D1
14.00 BSC
e
0.50 BSC
E
16.00 BSC
E1
14.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
NOTES :
1. ALL DIM ENSIONS ARE IN M ILLIM ETERS.
2. DATUM PLANE H IS LOCATED AT THE BOTTOM OF THE M OLD PARTING
LINE COINCIDENT W ITH W HERE THE LEAD EXITS THE BODY.
3. DATUM S A-B AND D TO BE DETERM INED AT DATUM PLANE H.
4. TO BE DETERM INED AT SEATING PLANE C.
5. DIM ENSIONS D1 AND E1 DO NOT INCLUDE M OLD PROTRUSION.
ALLOW ABLEPROTRUSION IS 0.25m m PRE SIDE.
DIM ENSIONS D1 AND E1 INCLUDE M OLD M ISM ATCH AND ARE DETERM INED
AT DATUM PLANE H.
6. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT M UST BE LOCATED
W ITHIN THE ZONE INDICATED.
7. REGARDLESS OF THE RELATIVE SIZE OF THE UPPER AND LOW ER BODY
SECTIONS. DIM ENSIONS D1 AND E1 ARE DETERM INED AT THE LARGEST
FEATURE OF THE BODY EXCLUSIVE OF M OLD FLASH AND GATE BURRS.
BUT INCLUDING ANY M ISM ATCH BETW EEN THE UPPER AND LOW ER
SECTIONS OF THE M OLDER BODY.
8. DIM ENSION b DOES NOT INCLUDE DAM BAR PROTRUSION. THE DAM BAR
PROTRUSION (S) SHALL NOT CAUSE THE LEAD W IDTH TO EXCEED b
M AXIM UM BY M ORE THAN 0.08m m . DAM BAR CANNOT BE LOCATED ON
THE LOW ER RADIUS OR THE LEAD FOOT.
9. THESE DIM ENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETW EEN 0.10m m AND 0.25m m FROM THE LEAD TIP.
10. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO
THE LOW EST POINT OF THE PACKAGE BODY.
002-11500 *A
PACKAGE OUTLINE, 100 LEAD LQFP
14.0X14.0X1.7 M M LQI100 REV*A
Document Number: 002-05644 Rev. *C
Page 90 of 95
CY9A130N Series
Package Type
QFP 100
Package Code
PQH100
D
D1
4
5 7
80
51
81
51
50
80
50
81
31
100
E1 E
5
7
6
3
4
31
100
1
30
e
3
0.40 C A-B D
30
2 5 7
1
0.20 C A-B D
b
0.13
C A-B
D
BOTTOM VIEW
8
TOP VIEW
2
θ
9
A
A'
SEATING
PLANE
L2
c
10
b
0.10 C
SECTION A-A'
D ETAIL A
SID E VIEW
SYM BOL
DIM ENSIONS
M IN.
NOM . M AX.
A1
0.05
0.45
b
0.27
c
0.11
A
3.35
0.32
0.23
D
23.90 BSC
D1
20.00 BSC
e
0.65 BSC
E
17.90 BSC
E1
θ
L
0.37
14.00 BSC
0°
0.73
8°
0.88
L1
1.95 REF
L2
0.2 5 BSC
1.03
002-15156 **
PACKAGE OUTLINE, 100 LEAD QFP
20.00X14.00X3 .35 M M PQH100 REV**
Document Number: 002-05644 Rev. *C
Page 91 of 95
CY9A130N Series
14. Major Changes
Spansion Publication Number: DS706-00042
Page
Section
Change Results
Revision 3.0
LIST OF PIN FUNCTIONS
• List of pin numbers
Revised the Pin state type.
• List of pin functions
Revised the pin name of "External Interrupt".
INIT15_1 → INT15_1
41
BLOCK DIAGRAM
Revised the description of "Multi-Function Serial IF".
52, 53
PIN STATUS IN EACH CPU STATE
• List of pin status
• Added "S" and "T" type to the Pin status type.
• Added the footnote.
15
22
Revision 3.1
-
-
Company name and layout design change
Revision 4.0
2
Features
· On-chip Memories
Changed the description of on-chip SRAM
7 - 29
Packages
Pin Assignment
List of Pin Functions
Deleted BGA package
38
Handling Devices
Added "· Stabilizing power supply voltage"
38
Handling Devices
Crystal oscillator circuit
Added the following description
"Evaluate oscillation of your using crystal oscillator by your mount
board."
40
Block Diagram
Modified the block diagram
42
Memory Map
· Memory map(2)
Added the summary of Flash memory sector and the note
55 - 57
Electrical Characteristics
3. DC Characteristics
(1) Current rating
· Changed the table format
· Added Main Timer mode current
· Added Flash Memory Current
· Moved A/D Converter Current
· Moved D/A Converter Current
58
Electrical Characteristics
3. DC Characteristics
(2) Pin Characteristics
Added the input leak current of CEC port at power off
61
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions of Main PLL
(4-2) Operating Conditions of Main PLL
· Added the figure of Main PLL connection
62
Electrical Characteristics
4. AC Characteristics
(6) Power-on Reset Timing
· Changed the figure of timing
· Changed from Reset release delay time(tOND) to Time until releasing
Power-on reset(tPRT)
64 - 71
Electrical Characteristics
4. AC Characteristics
(8) CSIO/UART Timing
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
75
Electrical Characteristics
5. 12bit A/D Converter
· Added the typical value of Integral Nonlinearity, Differential
Nonlinearity, Zero transition voltage and Full-scale transition voltage
· Added Conversion time at AVCC < 2.7 V
· Changed from Non linearity error to Integral Nonlinearity
· Changed from Differential linearity error to Differential Nonlinearity
78
Electrical Characteristics
6. 10bit D/A Converter
· Changed from Non linearity error to Integral Nonlinearity
· Changed from Differential linearity error to Differential Nonlinearity
Document Number: 002-05644 Rev. *C
Page 92 of 95
CY9A130N Series
Page
Section
Change Results
79
Electrical Characteristics
7. Low-voltage Detection
Characteristics
Deleted the figure
82
Electrical Characteristics
8. Flash Memory Write/Erase
Characteristics
Change to the erase time of include write time prior to internal erase
83 - 86
Electrical Characteristics
9. Return Time from Low-Power
Consumption Mode
Added Return Time from Low-Power Consumption Mode
87
Ordering Information
Changed notation of part number
88
Package Dimensions
Deleted BGA-112P-M04
NOTE: Please see “Document History” about later revised information.
Document Number: 002-05644 Rev. *C
Page 93 of 95
CY9A130N Series
Document History
Document Title: CY9A130N Series 32-bit ARM® Cortex®-M3 based FM3 Microcontroller
Document Number: 002-05644
Revision
ECN
Orig. of
Change
Submission
Date
**
-
AKIH
06/19/2015
Migrated to Cypress and assigned document number 002-05644.
No change to document contents.
*A
5135521
AKIH
03/10/2016
Updated to Cypress template.
*B
5531476
NNAK
06/06/2017
Deleted the following package in Package Dimensions.
LCC-64P-M24
Description of Change
Modified RTC description in “Features, Real-Time Clock(RTC)”.
Changed starting count value from 01 to 00. Deleted “second, or day of
the week” in the Interrupt function.
Changed package code as the following in chapter :
2. Packages
3. Pin Assignment
12. Ordering Information
13. Package Dimensions.
FPT-80P-M37 -> LQH080, FPT-80P-M40 -> LQJ080,
FPT-100P-M23 -> LQI100, FPT-100P-M06 -> PQH100
Replaced “J-TAG” with “JTAG" in 4. List of Pin Functions.
Added Note for JTAG pin in 4. List of Pin Functions.
Added the Baud rate spec in 11.4.9 CSIO/UART Timing.
Updated to new template.
*C
6575932
XITO
Document Number: 002-05644 Rev. *C
05/17/2019
Updated Document Title to read as “CY9A130N Series 32-bit ARM®
Cortex®-M3 based FM3 Microcontroller”.
Replaced “MB9A130N Series” with “CY9A130N Series” in all instances
across the document.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
Completing Sunset Review.
Page 94 of 95
CY9A130N Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the
office closest to you, visit us at Cypress Locations.
Products
ARM®
Cortex®
PSoC® Solutions
Microcontrollers
Automotive
Clocks & Buffers
Interface
Internet of Things
Memory
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
cypress.com/pmic
Touch Sensing
USB Controllers
Wireless/RF
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/touch
cypress.com/usb
cypress.com/wireless
ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries. All other trademarks or registered trademarks referenced herein are the property of their respective
owners.
© Cypress Semiconductor Corporation, 2012-2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and
reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or
compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED
USING CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION
(collectively, “Security Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from
any Security Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the
application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for
reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting
product. “High-Risk Device” means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations,
surgical implants, and other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly,
the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other
liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates,
distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property
damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk
Device except to the limited extent that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has
given you advance written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-05644 Rev. *C
May 17, 2019
Page 95 of 95
工商网监
湘ICP备2023018690号