CY9AF156MBBGL-GE1

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Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY9A150RB Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller The CY9A150RB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the Arm Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, and Communication Interfaces (UART, CSIO, I2C). The products which are described in this data sheet are placed into TYPE8 product categories in FM3 Family Peripheral Manual. Features 32-bit Arm Cortex-M3 Core Multi-function Serial Interface (Max 16 channels) ◼ Processor version: r2p1 ◼ 16 channels with 16 steps×9-bit FIFO ◼ Up to 40 MHz Frequency Operation ◼ Operation mode is selectable from the followings for each channel.  UART  CSIO  I2 C ◼ Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels ◼ 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [UART] ◼ Full-duplex double buffer ◼ Selection with or without parity supported [Flash memory] ◼ Dual operation Flash memory  Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously. ◼ Main area: Up to 512 Kbytes (Up to 496 Kbytes upper bank + 16 Kbytes lower bank) ◼ Work area: 32 Kbytes (lower bank) ◼ Built-in dedicated baud rate generator ◼ External clock available as a serial clock ◼ Hardware Flow control: Automatically control the transmission/reception by CTS/RTS (only ch.4) ◼ Various error detection functions available (parity errors, framing errors, and overrun errors) [CSIO] ◼ Full-duplex double buffer ◼ Read cycle: 0 wait-cycle ◼ Built-in dedicated baud rate generator ◼ Security function for code protection ◼ Overrun error detection function available [SRAM] This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. ◼ SRAM0: Up to 32 Kbytes [I2C] Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported DMA Controller (8channels) The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously. ◼ SRAM1: Up to 32 Kbytes ◼ 8 independently configured and operated channels External Bus Interface ◼ Supports SRAM, NOR NAND Flash memory device ◼ Transfer can be started by software or request from the built-in peripherals ◼ Up to 8 chip selects ◼ Transfer address area: 32-bit (4 Gbytes) ◼ 8-/16-bit Data width ◼ Up to 25-bit Address bit ◼ Transfer mode: Block transfer/Burst transfer/Demand transfer ◼ Maximum area size: Up to 256 Mbytes ◼ Transfer data type: byte/half-word/word ◼ Supports Address/Data multiplex ◼ Transfer block count: 1 to 16 ◼ Supports external RDY function ◼ Number of transfers: 1 to 65536 Cypress Semiconductor Corporation Document Number: 002-05646 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 15, 2021 CY9A150RB Series A/D Converter (Max 24 channels) [12-bit A/D Converter] The following function can be used to achieve the motor ◼ Successive Approximation type ◼ PWM signal output function ◼ Built-in 2 units ◼ DC chopper waveform output function ◼ Conversion time: 2.0 μs @ 2.7 V to 3.6 V ◼ Dead time function ◼ Priority conversion available (priority at 2 levels) ◼ Input capture function ◼ Scanning conversion mode ◼ A/D convertor activate function ◼ Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps) ◼ DTIF (Motor emergency stop) interrupt function Base Timer (Max 16channels) Operation mode is selectable from the followings for each channel. control. Quadrature Position/Revolution Counter (QPRC) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is ◼ 16-bit PWM timer possible to use as the up/down counter. ◼ 16-bit PPG timer ◼ The detection edge of the three external event input pins AIN, BIN and ZIN is configurable. ◼ 16-/32-bit reload timer ◼ 16-/32-bit PWC timer ◼ 16-bit position counter ◼ 16-bit revolution counter General-Purpose I/O Port ◼ Two 16-bit compare registers This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to. HDMI-CEC/Remote Control Reception (Up to 2 channels) ◼ Capable of pull-up control per pin ◼ Capable of reading pin level directly ◼ Built-in the port relocate function ◼ Up to 103 high-speed general-purpose I/O Ports@120 pin Package HDMI-CEC transmission ◼ Header block automatic transmission by judging Signal free ◼ Generating status interrupt by detecting Arbitration lost ◼ Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data ◼ Some ports are 5 V tolerant I/O ◼ Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK) See List of Pin Function and I/O Circuit Type to confirm the corresponding pins. HDMI-CEC reception Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel. ◼ Free-running ◼ Automatic ACK reply function available ◼ Line error detection function available Remote control reception ◼ 4 bytes reception buffer ◼ Repeat code detection function available ◼ Periodic (=Reload) Real-time clock (RTC) ◼ One-shot The Real-time clock can count Multi-function Timer The Multi-function timer is composed of the following blocks. Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99. ◼ Output compare × 6ch. ◼ The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute. ◼ A/D activation compare × 2ch. ◼ Timer interrupt function after set time or each set time. ◼ Waveform generator × 3ch. ◼ Capable of rewriting the time with continuing the time count. ◼ 16-bit PPG timer × 3ch. ◼ Leap year automatic count is available. ◼ 16-bit free-run timer × 3ch. ◼ Input capture × 4ch. Document Number: 002-05646 Rev. *E Page 2 of 149 CY9A150RB Series Watch Counter Clock Super Visor (CSV) The Watch counter is used for wake up from sleep and timer mode. Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks. Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz ◼ If external clock failure (clock stop) is detected, reset is asserted. External Interrupt Controller Unit ◼ If external frequency anomaly is detected, interrupt or reset is asserted. ◼ Up to 24 external interrupt input pins ◼ Include one non-maskable interrupt (NMI) input pin Watchdog Timer (Two channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog. The Hardware watchdog timer is clocked by the built-in Lowspeed CR oscillator. Therefore, the Hardware watchdog is active in any low-power consumption modes except RTC, Stop, Deep Standby RTC and Deep Standby Stop modes. CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. CCITT CRC16 and IEEE-802.3 CRC32 are supported. ◼ CCITT CRC16 Generator Polynomial: 0x1021 ◼ IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 Clock and Reset Low-Voltage Detector (LVD) This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage that has been set, Low-Voltage Detector generates an interrupt or reset. ◼ LVD1: error reporting via interrupt ◼ LVD2: auto-reset operation Low-Power Consumption Mode Six low-power consumption modes supported. ◼ Sleep ◼ Timer ◼ RTC ◼ Stop ◼ Deep Standby RTC (selectable between keeping the value of RAM and not) ◼ Deep Standby Stop (selectable between keeping the value of RAM and not) Debug ◼ Serial Wire JTAG Debug Port (SWJ-DP) ◼ Embedded Trace Macrocells (ETM).* *: CY9AF154MB, F155MB and F156MB support only SWJ-DP. [Clocks] Selectable from five clock sources (2 external oscillators, 2 Unique ID built-in CR oscillators, and Main PLL). Unique value of the device (41-bit) is set. ◼ Main Clock: 4 MHz to 48 MHz Power Supply ◼ Sub Clock: 32.768 kHz ◼ Built-in High-speed CR Clock: 4 MHz Wide range voltage: VCC = 1.65 V to 3.6 V ◼ Built-in Low-speed CR Clock: 100 kHz ◼ Main PLL Clock [Resets] ◼ Reset requests from INITX pin ◼ Power-on reset ◼ Software reset ◼ Watchdog timers reset ◼ Low-voltage detection reset ◼ Clock Super Visor reset Document Number: 002-05646 Rev. *E Page 3 of 149 CY9A150RB Series Contents Features................................................................................................................................................................................... 1 1. Product Lineup .............................................................................................................................................................. 6 1.1 Memory size................................................................................................................................................................... 6 1.2 Function ......................................................................................................................................................................... 6 2. Packages ........................................................................................................................................................................ 8 3. Pin Assignment.............................................................................................................................................................. 9 3.1 LQM120 ......................................................................................................................................................................... 9 3.2 LQI100 ......................................................................................................................................................................... 10 3.3 LQH080........................................................................................................................................................................ 11 3.4 LBC112 ........................................................................................................................................................................ 12 3.5 FDG096 ....................................................................................................................................................................... 13 4. List of Pin Function ..................................................................................................................................................... 14 4.1 List of Pin Numbers ...................................................................................................................................................... 14 4.2 List of Pin Functions ..................................................................................................................................................... 36 5. I/O Circuit Type ............................................................................................................................................................ 60 6. Handling Precautions .................................................................................................................................................. 65 6.1 Precautions for Product Design ................................................................................................................................... 65 6.2 Precautions for Package Mounting .............................................................................................................................. 66 6.3 Precautions for Use Environment ................................................................................................................................ 68 7. Handling Devices ......................................................................................................................................................... 69 7.1 Power Supply Pins ....................................................................................................................................................... 69 7.2 Stabilizing Power Supply Voltage ................................................................................................................................ 69 7.3 Crystal Oscillator Circuit ............................................................................................................................................... 69 7.4 Sub Crystal Oscillator .................................................................................................................................................. 69 7.5 Using an external clock ................................................................................................................................................ 70 7.6 Handling when using Multi-function serial pin as I2C pin .............................................................................................. 70 7.7 C pin ............................................................................................................................................................................ 70 7.8 Mode pins (MD0) ......................................................................................................................................................... 70 7.9 Notes on power-on ....................................................................................................................................................... 71 7.10 Serial Communication .................................................................................................................................................. 71 7.11 Differences in features among the products with different memory sizes and between Flash memory products and MASK products ..................................................................................................................................................... 71 7.12 Pull-Up function of 5 V tolerant I/O ............................................................................................................................... 71 8. Block Diagram.............................................................................................................................................................. 72 9. Memory Size ............................................................................................................................................................... 72 10. Memory Map ................................................................................................................................................................. 73 10.1 Memory Map (1) ........................................................................................................................................................... 73 10.2 Memory Map (2) ........................................................................................................................................................... 74 10.3 Peripheral Address Map .............................................................................................................................................. 75 11. Pin Status in Each CPU State ..................................................................................................................................... 76 11.1 List of Pin Status .......................................................................................................................................................... 77 12. Electrical Characteristics ............................................................................................................................................ 86 12.1 Absolute Maximum Ratings ......................................................................................................................................... 86 12.2 Recommended Operating Conditions .......................................................................................................................... 87 12.3 DC Characteristics ....................................................................................................................................................... 88 12.3.1 Current rating ............................................................................................................................................................... 88 Document Number: 002-05646 Rev. *E Page 4 of 149 CY9A150RB Series 12.3.2 Pin Characteristics ....................................................................................................................................................... 91 12.4 AC Characteristics ....................................................................................................................................................... 92 12.4.1 Main Clock Input Characteristics .................................................................................................................................. 92 12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 93 12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 94 12.4.4 Operating Conditions of Main PLL ............................................................................................................................... 95 12.4.5 Reset Input Characteristics .......................................................................................................................................... 96 12.4.6 Power-on Reset Timing................................................................................................................................................ 96 12.4.7 External Bus Timing ..................................................................................................................................................... 97 12.4.8 Base Timer Input Timing ............................................................................................................................................ 108 12.4.9 CSIO/UART Timing .................................................................................................................................................... 109 12.4.10 External Input Timing ............................................................................................................................................... 117 12.4.11 Quadrature Position/Revolution Counter timing ....................................................................................................... 118 12.4.12 I2C Timing ................................................................................................................................................................ 121 12.4.13 ETM Timing .............................................................................................................................................................. 122 12.4.14 JTAG Timing ............................................................................................................................................................ 123 12.5 12-bit A/D Converter .................................................................................................................................................. 124 12.5.1 Electrical Characteristics for the A/D Converter ......................................................................................................... 124 12.5.2 Definition of 12-bit A/D Converter Terms ................................................................................................................... 126 12.6 Low-Voltage Detection Characteristics ...................................................................................................................... 127 12.6.1 Low-Voltage Detection Reset ..................................................................................................................................... 127 12.6.2 Interrupt of Low-Voltage Detection ............................................................................................................................. 129 12.7 Flash Memory Write/Erase Characteristics ................................................................................................................ 130 12.7.1 Write / Erase time....................................................................................................................................................... 130 12.7.2 Write cycles and data hold time ................................................................................................................................. 130 12.8 Return Time from Low-Power Consumption Mode .................................................................................................... 131 12.8.1 Return Factor: Interrupt/WKUP .................................................................................................................................. 131 12.8.2 Return Factor: Reset .................................................................................................................................................. 133 13. Ordering Information ................................................................................................................................................. 135 14. Package Dimensions ................................................................................................................................................. 136 15. Errata .......................................................................................................................................................................... 141 15.1 Part Numbers Affected ............................................................................................................................................... 141 15.2 Qualification Status .................................................................................................................................................... 141 15.3 Errata Summary ......................................................................................................................................................... 141 16. Major Changes ........................................................................................................................................................... 144 Document History ............................................................................................................................................................... 147 Sales, Solutions, and Legal Information ........................................................................................................................... 149 Document Number: 002-05646 Rev. *E Page 5 of 149 CY9A150RB Series 1. Product Lineup 1.1 Memory size Product name CY9AF154MB/NB/RB CY9AF155MB/NB/RB CY9AF156MB/NB/RB On-chip Main area 256 Kbytes 384 Kbytes 512 Kbytes Flash memory Work area 32 Kbytes 32 Kbytes 32 Kbytes SRAM0 16 Kbytes 24 Kbytes 32 Kbytes SRAM1 16 Kbytes 24 Kbytes 32 Kbytes Total 32 Kbytes 48 Kbytes 64 Kbytes On-chip SRAM 1.2 Function Product name Pin count CY9AF154MB CY9AF154NB CY9AF154RB CY9AF155MB CY9AF155NB CY9AF155RB CY9AF156MB CY9AF156NB CY9AF156RB 80/96 100/112 120 Addr: 21-bit (Max) Addr: 25-bit (Max) Addr: 25-bit (Max) R/W Data: 8-bit (Max) R/W Data: 8-/16-bit (Max) R/W Data: 8-/16-bit (Max) CS: 4 (Max) CS: 8 (Max) CS: 8 (Max) Support: SRAM, NOR Flash Support: SRAM, Support: SRAM, memory NOR Flash memory NOR Flash memory, Cortex-M3 CPU Freq. 40 MHz Power supply voltage range 1.65V to 3.6V DMAC 8ch. External Bus Interface NAND Flash memory 10ch. (Max) Multi-function Serial Interface Enabled channels : 2 (UART/CSIO/I C) ch.0 to ch.7, ch.10, ch.11 Base Timer MF- A/D activation 2ch compare . Timer Free-run timer Output compare Waveform generator PPG 16ch. (Max) Enabled channels : Enabled channels : ch.0 to ch.0 to ch.13 ch.15 16ch. (Max) (PWC/Reload timer/PWM/PPG) Input capture 14ch. (Max) 4ch . 3ch . 6ch 1 unit (Max) . 3ch . 3ch . QPRC 2ch. (Max) Dual Timer 1 unit HDMI-CEC/ Remote Control Reception Document Number: 002-05646 Rev. *E 2ch. (Max) Page 6 of 149 CY9A150RB Series Product name CY9AF154MB CY9AF154NB CY9AF154RB CY9AF155MB CY9AF155NB CY9AF155RB CY9AF156MB CY9AF156NB CY9AF156RB Real-Time Clock 1 unit Watch Counter 1 unit CRC Accelerator Yes Watchdog timer 1ch. (SW) + 1ch. (HW) External Interrupts 23 pins (Max) + NMI × 1 24 pins (Max) + NMI × 1 I/O ports 66 pins (Max) 83 pins (Max) 12-bit A/D converter 17ch. (2 units) 24ch. (2 units) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2ch. High-speed 4 MHz Low-speed 100 kHz 103 pins (Max) Built-in CR Debug Function SWJ-DP Unique ID Yes SWJ-DP/ETM Note: − − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See Electrical Characteristics0 AC Characteristics 12.4.3 Built-in CR Oscillation Characteristics for accuracy of built-in CR. Document Number: 002-05646 Rev. *E Page 7 of 149 CY9A150RB Series 2. Packages CY9AF154MB CY9AF154NB CY9AF154RB CY9AF155MB CY9AF155NB CY9AF155RB CY9AF156MB CY9AF156NB CY9AF156RB LQFP: LQH080 (0.5 mm pitch)  - - BGA: FDG096 (0.5 mm pitch)  - - LQFP: LQI100 (0.5 mm pitch) -  - BGA: LBC112 (0.8 mm pitch) -  - LQFP: LQM120 (0.5 mm pitch) - -  Product name Package : Supported Note: − See Package Dimensions for detailed information on each package. Document Number: 002-05646 Rev. *E Page 8 of 149 CY9A150RB Series 3. Pin Assignment 3.1 LQM120 P02/TDI/SOT8_0/TIOB14_2/MCSX6_0 P01/TCK/SWCLK P00/TRSTX/SCK8_0/TIOA14_2/MCSX7_0 VCC 94 93 92 91 P05/AN20/TRACED0/SIN8_0/SIN4_2/TIOA5_2/INT00_1/MCSX5_0 P04/TDO/SWO P03/TMS/SWDIO 95 98 97 99 96 P08/AN23/TRACED3/CTS4_2/TIOA0_2/INT16_0/MCSX3_0 P07/AN22/ADTG_0/TRACED2/SCK4_2/INT23_1/MCLKOUT_0 P06/AN21/TRACED1/SOT4_2/TIOB5_2/INT01_1/MCSX4_0 100 P0B/SOT4_0/TIOB6_1/INT18_0/CEC0_1/MCSX0_0 P0A/SIN4_0/INT00_2/WKUP5/MCSX1_0 P09/TRACECLK/RTS4_2/TIOB0_2/INT17_0/MCSX2_0 103 102 101 P0E/CTS4_0/TIOB3_2/INT21_0/MDQM1_0 P0D/RTS4_0/TIOA3_2/INT20_0/MDQM0_0 P0C/SCK4_0/TIOA6_1/INT19_0/MALE_0 104 107 106 105 P67/SOT3_0/TIOA7_2/INT22_0 P68/SCK3_0/TIOB7_2/INT12_2 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 109 108 P64/SOT5_1/TIOA7_0/INT10_2 P65/SCK5_1/TIOB7_0/TIOB12_2/INT23_0 P66/SIN3_0/TIOA12_2/INT11_2 112 111 110 P62/ADTG_3/SCK5_0/TIOA15_1/INT07_1/MOEX_0 P63/SIN5_1/TIOB15_1/INT03_0/MWEX_0 114 113 VCC P60/SIN5_0/IGTRG_1/TIOA2_2/INT15_1/WKUP3/CEC1_0/MRDY_0 P61/SOT5_0/TIOB2_2 117 116 115 VSS P81/TIOA15_0/INT17_1 P80/TIOB15_0/INT16_1 120 119 118 (TOP VIEW) VCC 1 90 VSS P50/SIN3_1/AIN0_2/TIOB8_0/INT00_0/MADATA00_0 2 89 P20/AN19/CROUT_0/AIN1_1/TIOA10_2/INT05_0/MAD24_0 P51/SOT3_1/BIN0_2/TIOB9_0/INT01_0/MADATA01_0 3 88 P21/AN18/SIN0_0/BIN1_1/TIOB10_2/INT06_1/WKUP2 P52/SCK3_1/ZIN0_2/TIOB10_0/INT02_0/MADATA02_0 4 87 P22/AN17/SOT0_0/ZIN1_1/TIOB7_1 P53/SIN6_0/TIOB11_0/TIOA1_2/INT07_2/MADATA03_0 5 86 P23/AN16/SCK0_0/RTO00_1/TIOA7_1 P54/SOT6_0/TIOB12_0/TIOB1_2/INT18_1/MADATA04_0 6 85 P24/SIN2_1/RTO01_1/TIOB14_1/INT01_2 P55/ADTG_1/SCK6_0/TIOB13_0/INT19_1/MADATA05_0 7 84 P25/SOT2_1/RTO02_1/TIOA14_1/TIOB11_2 P56/SIN1_0/TIOA8_0/INT08_2/CEC1_1/MADATA06_0 8 83 P26/SCK2_1/RTO03_1/TIOA11_2 P57/SOT1_0/TIOA9_0/MADATA07_0 9 82 P27/SIN15_0/RTO04_1/TIOA6_2/INT02_2 P58/SCK1_0/TIOA10_0/MADATA08_0 10 81 P28/ADTG_4/SOT15_0/RTO05_1/TIOB6_2 P59/SIN7_0/TIOA11_0/INT09_2/MADATA09_0 11 80 P1F/AN15/ADTG_5/SCK15_0/FRCK0_1/TIOB9_2/MAD23_0 P5A/SOT7_0/TIOA12_0/INT16_2/MADATA10_0 12 79 P1E/AN14/RTS4_1/DTTI0X_1/TIOA9_2/INT23_2/MAD22_0 P5B/SCK7_0/TIOA13_0/INT17_2/MADATA11_0 13 78 P1D/AN13/CTS4_1/IC03_1/TIOA13_1/INT22_2/MAD21_0 P30/AIN0_0/TIOB0_1/TIOA13_2/INT03_2/WKUP4/MADATA12_0 14 77 P1C/AN12/SCK4_1/IC02_1/TIOA12_1/INT21_2/MAD20_0 P31/SCK6_1/BIN0_0/TIOB1_1/TIOB13_2/INT04_2/MADATA13_0 15 76 P1B/AN11/SOT4_1/IC01_1/TIOA11_1/INT20_2/MAD19_0 P32/SOT6_1/ZIN0_0/TIOB2_1/INT05_2/MADATA14_0 16 75 P1A/AN10/SIN4_1/IC00_1/TIOA10_1/INT05_1/MAD18_0 P33/ADTG_6/SIN9_0/SIN6_1/TIOB3_1/INT04_0/MADATA15_0 17 74 P19/AN09/SCK2_2/TIOA9_1/MAD17_0 P34/SOT9_0/FRCK0_0/TIOB4_1/TIOA15_2/MNALE_0 18 73 P18/AN08/SOT2_2/TIOA8_1/MAD16_0 P35/SCK9_0/IC03_0/TIOB5_1/TIOB15_2/INT08_1/MNCLE_0 19 72 AVSS LQFP - 120 P36/SIN5_2/IC02_0/TIOB14_0/INT09_1/MNWEX_0 20 71 AVRH P37/SOT5_2/IC01_0/TIOA14_0/INT10_1/MNREX_0 21 70 AVCC P38/SCK5_2/IC00_0/TIOA8_2/INT11_1 22 69 P17/AN07/SIN2_2/INT04_1/MAD15_0 P39/ADTG_2/SIN10_0/DTTI0X_0/TIOB8_2/INT06_0 23 68 P16/AN06/SCK0_1/TIOB13_1/INT15_0/MAD14_0 P3A/SOT10_0/RTO00_0/TIOA0_1/INT07_0/RTCCO_2/SUBOUT_2 24 67 P15/AN05/SOT0_1/IC03_2/TIOB12_1/INT14_0/MAD13_0 P3B/SCK10_0/RTO01_0/TIOA1_1 25 66 P14/AN04/SIN0_1/IC02_2/TIOB11_1/INT03_1/MAD12_0 P3C/SIN11_0/RTO02_0/TIOA2_1/INT18_2 26 65 P13/AN03/SCK1_1/IC01_2/TIOB10_1/RTCCO_1/SUBOUT_1/MAD11_0 57 58 59 60 MD0 VSS PE0/MD1 PE2/X0 56 P74/SCK2_0 PE3/X1 53 54 55 P73/SOT2_0/TIOB6_0/INT15_2 51 52 P70/SOT14_0/TIOA4_2 P72/SIN2_0/TIOA6_0/INT14_2 P71/SCK14_0/TIOB4_2/INT13_2 48 49 50 P4D/SOT7_1/BIN1_2/TIOB4_0/INT13_0/MAD07_0 P4C/SCK7_1/AIN1_2/TIOB3_0/INT12_0/CEC0_0/MAD06_0 P4E/SIN14_0/SIN7_1/ZIN1_2/TIOB5_0/INT06_2/MAD08_0 47 P4B/IGTRG_0/ZIN0_1/TIOB2_0/INT22_1/MAD05_0 44 45 46 P49/SOT3_2/AIN0_1/TIOB0_0/INT20_1/MAD03_0 P4A/SCK3_2/BIN0_1/TIOB1_0/INT21_1/MAD04_0 42 43 INITX P47/X1A P48/SIN3_2/INT14_1/MAD02_0 39 40 41 VSS VCC C P46/X0A 37 38 P45/SCK13_0/TIOA5_0/INT11_0/MAD01_0 P42/SCK12_0/TIOA2_0/INT08_0 34 VCC 35 61 36 30 P43/ADTG_7/SIN13_0/TIOA3_0/INT09_0 P10/AN00 VSS P44/SOT13_0/TIOA4_0/INT10_0/MAD00_0 62 31 29 32 P11/AN01/SIN1_1/FRCK0_2/TIOB8_1/INT02_1/WKUP1/MAD09_0 P3F/RTO05_0/TIOA5_1 33 P12/AN02/SOT1_1/IC00_2/TIOB9_1/MAD10_0 63 VCC 64 28 P40/SIN12_0/TIOA0_0/INT12_1 27 P41/SOT12_0/TIOA1_0/INT13_1 P3D/SOT11_0/RTO03_0/TIOA3_1 P3E/SCK11_0/RTO04_0/TIOA4_1/INT19_2 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05646 Rev. *E Page 9 of 149 CY9A150RB Series 3.2 LQI100 VSS P81/TIOA15_0/INT17_1 P80/TIOB15_0/INT16_1 VCC P60/SIN5_0/IGTRG_1/TIOA2_2/INT15_1/WKUP3/CEC1_0/MRDY_0 P61/SOT5_0/TIOB2_2 P62/ADTG_3/SCK5_0/TIOA15_1/INT07_1/MOEX_0 P63/TIOB15_1/INT03_0/MWEX_0 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P0E/CTS4_0/TIOB3_2/INT21_0/MDQM1_0 P0D/RTS4_0/TIOA3_2/INT20_0/MDQM0_0 P0C/SCK4_0/TIOA6_1/INT19_0/MALE_0 P0B/SOT4_0/TIOB6_1/INT18_0/CEC0_1/MCSX0_0 P0A/SIN4_0/INT00_2/WKUP5/MCSX1_0 P09/TRACECLK/RTS4_2/TIOB0_2/INT17_0/MCSX2_0 P08/AN23/TRACED3/CTS4_2/TIOA0_2/INT16_0/MCSX3_0 P07/AN22/ADTG_0/TRACED2/SCK4_2/INT23_1/MCLKOUT_0 P06/AN21/TRACED1/SOT4_2/TIOB5_2/INT01_1/MCSX4_0 P05/AN20/TRACED0/SIN8_0/SIN4_2/TIOA5_2/INT00_1/MCSX5_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI/SOT8_0/TIOB14_2/MCSX6_0 P01/TCK/SWCLK P00/TRSTX/SCK8_0/TIOA14_2/MCSX7_0 VCC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (TOP VIEW) VCC 1 75 VSS P50/SIN3_1/AIN0_2/TIOB8_0/INT00_0/MADATA00_0 2 74 P20/AN19/CROUT_0/AIN1_1/TIOA10_2/INT05_0/MAD24_0 P51/SOT3_1/BIN0_2/TIOB9_0/INT01_0/MADATA01_0 3 73 P21/AN18/SIN0_0/BIN1_1/TIOB10_2/INT06_1/WKUP2 P52/SCK3_1/ZIN0_2/TIOB10_0/INT02_0/MADATA02_0 4 72 P22/AN17/SOT0_0/ZIN1_1/TIOB7_1 P53/SIN6_0/TIOB11_0/TIOA1_2/INT07_2/MADATA03_0 5 71 P23/AN16/SCK0_0/TIOA7_1 P54/SOT6_0/TIOB12_0/TIOB1_2/INT18_1/MADATA04_0 6 70 P1F/AN15/ADTG_5/FRCK0_1/TIOB9_2/MAD23_0 P55/ADTG_1/SCK6_0/TIOB13_0/INT19_1/MADATA05_0 7 69 P1E/AN14/RTS4_1/DTTI0X_1/TIOA9_2/INT23_2/MAD22_0 P56/INT08_2/CEC1_1/MADATA06_0 8 68 P1D/AN13/CTS4_1/IC03_1/TIOA13_1/INT22_2/MAD21_0 P30/AIN0_0/TIOB0_1/TIOA13_2/INT03_2/WKUP4/MADATA07_0 9 67 P1C/AN12/SCK4_1/IC02_1/TIOA12_1/INT21_2/MAD20_0 P31/SCK6_1/BIN0_0/TIOB1_1/TIOB13_2/INT04_2/MADATA08_0 10 66 P1B/AN11/SOT4_1/IC01_1/TIOA11_1/INT20_2/MAD19_0 P32/SOT6_1/ZIN0_0/TIOB2_1/INT05_2/MADATA09_0 11 65 P1A/AN10/SIN4_1/IC00_1/TIOA10_1/INT05_1/MAD18_0 P33/ADTG_6/SIN9_0/SIN6_1/TIOB3_1/INT04_0/MADATA10_0 12 64 P19/AN09/SCK2_2/TIOA9_1/MAD17_0 LQFP - 100 P34/SOT9_0/FRCK0_0/TIOB4_1/TIOA15_2/MADATA11_0 13 63 P18/AN08/SOT2_2/TIOA8_1/MAD16_0 P35/SCK9_0/IC03_0/TIOB5_1/TIOB15_2/INT08_1/MADATA12_0 14 62 AVSS P36/SIN5_2/IC02_0/TIOB14_0/INT09_1/MADATA13_0 15 61 AVRH P37/SOT5_2/IC01_0/TIOA14_0/INT10_1/MADATA14_0 16 60 AVCC P38/SCK5_2/IC00_0/TIOA8_2/INT11_1/MADATA15_0 17 59 P17/AN07/SIN2_2/INT04_1/MAD15_0 P39/ADTG_2/SIN10_0/DTTI0X_0/TIOB8_2/INT06_0 18 58 P16/AN06/SCK0_1/TIOB13_1/INT15_0/MAD14_0 P3A/SOT10_0/RTO00_0/TIOA0_1/INT07_0/RTCCO_2/SUBOUT_2 19 57 P15/AN05/SOT0_1/IC03_2/TIOB12_1/INT14_0/MAD13_0 48 49 50 PE3/X1 VSS 46 PE0/MD1 47 45 P4E/SIN7_1/ZIN1_2/TIOB5_0/INT06_2/MAD08_0 MD0 44 P4D/SOT7_1/BIN1_2/TIOB4_0/INT13_0/MAD07_0 PE2/X0 43 P4C/SCK7_1/AIN1_2/TIOB3_0/INT12_0/CEC0_0/MAD06_0 39 P48/SIN3_2/INT14_1/MAD02_0 42 38 INITX P4B/IGTRG_0/ZIN0_1/TIOB2_0/INT22_1/MAD05_0 37 P47/X1A 41 36 P46/X0A 40 35 VCC P49/SOT3_2/AIN0_1/TIOB0_0/INT20_1/MAD03_0 34 P4A/SCK3_2/BIN0_1/TIOB1_0/INT21_1/MAD04_0 33 C VSS VCC 32 P10/AN00 51 P45/SCK13_0/TIOA5_0/INT11_0/MAD01_0 52 25 31 24 VSS 30 P11/AN01/SIN1_1/FRCK0_2/TIOB8_1/INT02_1/WKUP1/MAD09_0 P3F/RTO05_0/TIOA5_1 P44/SOT13_0/TIOA4_0/INT10_0/MAD00_0 53 29 23 P42/SCK12_0/TIOA2_0/INT08_0 P12/AN02/SOT1_1/IC00_2/TIOB9_1/MAD10_0 P3E/SCK11_0/RTO04_0/TIOA4_1/INT19_2 P43/ADTG_7/SIN13_0/TIOA3_0/INT09_0 54 28 22 27 P13/AN03/SCK1_1/IC01_2/TIOB10_1/RTCCO_1/SUBOUT_1/MAD11_0 P3D/SOT11_0/RTO03_0/TIOA3_1 26 P14/AN04/SIN0_1/IC02_2/TIOB11_1/INT03_1/MAD12_0 55 VCC 56 21 P40/SIN12_0/TIOA0_0/INT12_1 20 P41/SOT12_0/TIOA1_0/INT13_1 P3B/SCK10_0/RTO01_0/TIOA1_1 P3C/SIN11_0/RTO02_0/TIOA2_1/INT18_2 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05646 Rev. *E Page 10 of 149 CY9A150RB Series 3.3 LQH080 P02/TDI/TIOB14_2/MCSX6_0 P01/TCK/SWCLK P00/TRSTX/TIOA14_2/MCSX7_0 63 62 61 P07/AN22/ADTG_0/INT23_1/MCLKOUT_0 P04/TDO/SWO P03/TMS/SWDIO 66 65 64 P0B/SOT4_0/TIOB6_1/INT18_0/CEC0_1/MCSX0_0 P0A/SIN4_0/INT00_2/WKUP5/MCSX1_0 68 67 P0D/RTS4_0/TIOA3_2/INT20_0/MDQM0_0 P0C/SCK4_0/TIOA6_1/INT19_0/MALE_0 71 70 69 P63/TIOB15_1/INT03_0/MWEX_0 P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0 P0E/CTS4_0/TIOB3_2/INT21_0/MDQM1_0 73 72 P61/SOT5_0/TIOB2_2 P62/ADTG_3/SCK5_0/TIOA15_1/INT07_1/MOEX_0 75 74 VCC P60/SIN5_0/IGTRG_1/TIOA2_2/INT15_1/WKUP3/CEC1_0/MRDY_0 78 77 76 VSS P81/TIOA15_0/INT17_1 P80/TIOB15_0/INT16_1 80 79 (TOP VIEW) VCC 1 60 P20/AN19/CROUT_0/AIN1_1/TIOA10_2/INT05_0/MAD24_0 P50/SIN3_1/AIN0_2/TIOB8_0/INT00_0/MADATA00_0 2 59 P21/AN18/SIN0_0/BIN1_1/TIOB10_2/INT06_1/WKUP2 P51/SOT3_1/BIN0_2/TIOB9_0/INT01_0/MADATA01_0 3 58 P22/AN17/SOT0_0/ZIN1_1/TIOB7_1 P52/SCK3_1/ZIN0_2/TIOB10_0/INT02_0/MADATA02_0 4 57 P23/AN16/SCK0_0/TIOA7_1 P53/SIN6_0/TIOB11_0/TIOA1_2/INT07_2/MADATA03_0 5 56 P1B/AN11/SOT4_1/IC01_1/TIOA11_1/INT20_2/MAD19_0 P54/SOT6_0/TIOB12_0/TIOB1_2/INT18_1/MADATA04_0 6 55 P1A/AN10/SIN4_1/IC00_1/TIOA10_1/INT05_1/MAD18_0 P55/ADTG_1/SCK6_0/TIOB13_0/INT19_1/MADATA05_0 7 54 P19/AN09/SCK2_2/TIOA9_1/MAD17_0 P56/INT08_2/CEC1_1/MADATA06_0 8 53 P18/AN08/SOT2_2/TIOA8_1/MAD16_0 P30/AIN0_0/TIOB0_1/TIOA13_2/INT03_2/WKUP4/MADATA07_0 9 52 AVSS P31/SCK6_1/BIN0_0/TIOB1_1/TIOB13_2/INT04_2/MADATA08_0 10 51 AVRH LQFP - 80 38 39 40 VSS MD0 PE2/X0 PE0/MD1 PE3/X1 35 36 37 P4E/SIN7_1/ZIN1_2/TIOB5_0/INT06_2/MAD08_0 33 34 VCC P4D/SOT7_1/BIN1_2/TIOB4_0/INT13_0/MAD07_0 41 P4C/SCK7_1/AIN1_2/TIOB3_0/INT12_0/CEC0_0/MAD06_0 20 30 P10/AN00 VSS 31 P11/AN01/SIN1_1/FRCK0_2/TIOB8_1/INT02_1/WKUP1/MAD09_0 42 32 43 19 P4A/SCK3_2/BIN0_1/TIOB1_0/INT21_1/MAD04_0 18 P3F/RTO05_0/TIOA5_1 P4B/IGTRG_0/ZIN0_1/TIOB2_0/INT22_1/MAD05_0 P12/AN02/SOT1_1/IC00_2/TIOB9_1/MAD10_0 P3E/SCK11_0/RTO04_0/TIOA4_1/INT19_2 28 44 29 17 INITX P13/AN03/SCK1_1/IC01_2/TIOB10_1/RTCCO_1/SUBOUT_1/MAD11_0 P3D/SOT11_0/RTO03_0/TIOA3_1 P48/SIN3_2/INT14_1/MAD02_0 45 P49/SOT3_2/AIN0_1/TIOB0_0/INT20_1/MAD03_0 16 26 P14/AN04/SIN0_1/IC02_2/TIOB11_1/INT03_1/MAD12_0 P3C/SIN11_0/RTO02_0/TIOA2_1/INT18_2 27 46 P46/X0A 15 P47/X1A P15/AN05/SOT0_1/IC03_2/TIOB12_1/INT14_0/MAD13_0 P3B/SCK10_0/RTO01_0/TIOA1_1 23 47 24 14 25 P16/AN06/SCK0_1/TIOB13_1/INT15_0/MAD14_0 P3A/SOT10_0/RTO00_0/TIOA0_1/INT07_0/RTCCO_2/SUBOUT_2 VSS 48 VCC 13 21 P17/AN07/SIN2_2/INT04_1/MAD15_0 P39/ADTG_2/SIN10_0/DTTI0X_0/INT06_0 22 AVCC 49 C 50 12 P44/TIOA4_0/INT10_0/MAD00_0 11 P45/TIOA5_0/INT11_0/MAD01_0 P32/SOT6_1/ZIN0_0/TIOB2_1/INT05_2/MADATA09_0 P33/ADTG_6/SIN6_1/TIOB3_1/INT04_0/MADATA10_0 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05646 Rev. *E Page 11 of 149 CY9A150RB Series 3.4 LBC112 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A VSS P81 P80 VCC P0E P0B P07 TMS/ SWDIO TRSTX VCC VSS B VCC VSS P52 P61 P0F P0C P08 TDO/ SWO TCK/ SWCLK VSS TDI C P50 P51 VSS P60 P62 P0D P09 P05 VSS P20 P21 D P53 P54 P55 VSS P56 P63 P0A VSS P06 P23 AN15 E P30 P31 P32 P33 Index P22 AN14 AN12 AN11 F P34 P35 P36 P39 AN13 AN10 AN09 AVRH G P37 P38 P3A P3D AN08 AN07 AN06 AVSS H P3B P3C P3E VSS P44 P4C AN05 VSS AN04 AN03 AVCC J VCC P3F VSS P40 P43 P49 P4D AN02 VSS AN01 AN00 K VCC VSS X1A INITX P42 P48 P4B P4E MD1 VSS VCC L VSS C X0A VSS P41 P45 P4A MD0 X0 X1 VSS Note: − PFBGA - 112 The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05646 Rev. *E Page 12 of 149 CY9A150RB Series 3.5 FDG096 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A VSS P81 P80 VCC VSS P0F VSS P07 TMS/ SWDIO TRSTX VSS B VCC VSS P52 P61 P63 P0D P0C TDO/ SWO TCK/ SWCLK VSS TDI C P50 P51 VSS P60 P62 P0E P0B P0A VSS P20 P21 D P53 P54 P55 Index P22 P23 VSS E P56 P30 P31 AN11 AN10 AN09 F VSS VSS VSS AN08 AN07 AVRH G P32 P33 P39 AN06 AN05 AVSS H P3A P3B P3C AN04 AN03 AVCC J P3D P3E VSS P3F P48 P4A P4D AN02 VSS AN01 AN00 K VCC VSS X1A INITX P45 P49 P4C P4E MD1 VSS VCC L VSS C X0A VSS P44 VSS P4B MD0 X0 X1 VSS Note: − PFBGA - 96 The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-05646 Rev. *E Page 13 of 149 CY9A150RB Series 4. List of Pin Function 4.1 List of Pin Numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 1 1 B1 1 B1 I/O Circuit Pin State Type Type VCC - P50 SIN3_1 AIN0_2 2 2 C1 2 C1 E K E K E K E K TIOB8_0 INT00_0 MADATA00_0 P51 SOT3_1 (SDA3_1) 3 3 C2 3 C2 BIN0_2 TIOB9_0 INT01_0 MADATA01_0 P52 SCK3_1 (SCL3_1) 4 4 B3 4 B3 ZIN0_2 TIOB10_0 INT02_0 MADATA02_0 P53 SIN6_0 TIOB11_0 5 5 D1 5 D1 TIOA1_2 INT07_2 MADATA03_0 Document Number: 002-05646 Rev. *E Page 14 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Type Pin State Type P54 SOT6_0 (SDA6_0) 6 6 D2 6 D2 TIOB12_0 E K E K H[1] R H[1] J H[1] J TIOB1_2 INT18_1 MADATA04_0 P55 ADTG_1 SCK6_0 7 7 D3 7 D3 (SCL6_0) TIOB13_0 INT19_1 MADATA05_0 P56 INT08_2 8 D5 8 E1 CEC1_1 8 MADATA06_0 SIN1_0 - - - TIOA8_0 P57 SOT1_0 9 - - - - (SDA1_0) TIOA9_0 MADATA07_0 P58 SCK1_0 10 - - - - (SCL1_0) TIOA10_0 MADATA08_0 Document Number: 002-05646 Rev. *E Page 15 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Type Pin State Type P59 SIN7_0 11 - - - - TIOA11_0 E K E K E K E S E S INT09_2 MADATA09_0 P5A SOT7_0 (SDA7_0) 12 - - - TIOA12_0 INT16_2 MADATA10_0 P5B SCK7_0 (SCL7_0) 13 - - - TIOA13_0 INT17_2 MADATA11_0 P30 AIN0_0 TIOB0_1 14 - - - - TIOA13_2 INT03_2 WKUP4 MADATA12_0 P30 AIN0_0 TIOB0_1 - 9 E1 9 E2 TIOA13_2 INT03_2 WKUP4 MADATA07_0 Document Number: 002-05646 Rev. *E Page 16 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Pin State Type Type E K E K E K E K E K P31 SCK6_1 (SCL6_1) BIN0_0 15 - - - - TIOB1_1 TIOB13_2 INT04_2 MADATA13_0 P31 SCK6_1 (SCL6_1) BIN0_0 - 10 E2 10 E3 TIOB1_1 TIOB13_2 INT04_2 MADATA08_0 P32 SOT6_1 (SDA6_1) 16 - - - - ZIN0_0 TIOB2_1 INT05_2 MADATA14_0 P32 SOT6_1 (SDA6_1) - 11 E3 11 G1 ZIN0_0 TIOB2_1 INT05_2 MADATA09_0 P33 ADTG_6 SIN9_0 17 - - - - SIN6_1 TIOB3_1 INT04_0 MADATA15_0 Document Number: 002-05646 Rev. *E Page 17 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Pin State Type Type E K E J E J E K E K P33 ADTG_6 SIN6_1 12 - 12 G2 E4 TIOB3_1 INT04_0 MADATA10_0 - - SIN9_0 P34 SOT9_0 (SDA9_0) 18 - - - - FRCK0_0 TIOB4_1 TIOA15_2 MNALE_0 P34 SOT9_0 (SDA9_0) - 13 F1 - - FRCK0_0 TIOB4_1 TIOA15_2 MADATA11_0 P35 SCK9_0 (SCL9_0) IC03_0 19 - - - - TIOB5_1 TIOB15_2 INT08_1 MNCLE_0 P35 SCK9_0 (SCL9_0) IC03_0 - 14 F2 - TIOB5_1 TIOB15_2 INT08_1 MADATA12_0 Document Number: 002-05646 Rev. *E Page 18 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Pin State Type Type E K E K P36 SIN5_2 IC02_0 20 - - - TIOB14_0 INT09_1 MNWEX_0 P36 SIN5_2 IC02_0 - 15 F3 - TIOB14_0 INT09_1 MADATA13_0 - - - - F1 VSS - - - - - F2 VSS - - - - - F3 VSS - P37 SOT5_2 (SDA5_2) 21 - - - - IC01_0 E K E K TIOA14_0 INT10_1 MNREX_0 P37 SOT5_2 (SDA5_2) - 16 G1 - - IC01_0 TIOA14_0 INT10_1 MADATA14_0 Document Number: 002-05646 Rev. *E Page 19 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Pin State Type Type E K E K E K E J E K P38 SCK5_2 (SCL5_2) 22 17 G2 - - IC00_0 TIOA08_2 INT11_1 - MADATA15_0 P39 ADTG_2 13 23 18 G3 SIN10_0 F4 DTTI0X_0 INT06_0 - - TIOB8_2 P3A SOT10_0 (SDA10_0) RTO00_0 24 19 G3 14 H1 TIOA0_1 INT07_0 RTCCO_2 SUBOUT_2 P3B SCK10_0 25 20 H1 15 H2 (SCL10_0) RTO01_0 TIOA1_1 P3C SIN11_0 26 21 H2 16 H3 RTO02_0 TIOA2_1 INT18_2 Document Number: 002-05646 Rev. *E Page 20 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Pin State Type Type E J P3D SOT11_0 27 22 G4 17 J1 (SDA11_0) RTO03_0 TIOA3_1 - - B2 - B2 VSS - P3E SCK11_0 (SCL11_0) 28 23 H3 18 J2 E K E J RTO04_0 TIOA4_1 INT19_2 P3F 29 24 J2 19 J4 RTO05_0 TIOA5_1 30 25 L1 20 L1 VSS - 31 26 J1 - - VCC - P40 SIN12_0 32 27 J4 - - E K E K E K TIOA0_0 INT12_1 P41 SOT12_0 33 28 L5 - - (SDA12_0) TIOA1_0 INT13_1 P42 SCK12_0 (SCL12_0) 34 29 K5 - TIOA2_0 INT08_0 Document Number: 002-05646 Rev. *E Page 21 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Pin State Type Type E K E K E K P43 ADTG_7 35 30 J5 - - SIN13_0 TIOA3_0 INT09_0 21 L5 - - P44 SOT13_0 (SDA13_0) 36 31 H5 TIOA4_0 21 L5 INT10_0 MAD00_0 37 32 22 K5 P45 - - SCK13_0 L6 TIOA5_0 22 K5 INT11_0 MAD01_0 - - K2 - K2 VSS - - - J3 - J3 VSS - - - H4 - - VSS - - - - - L6 VSS - 38 33 L2 23 L2 C - 39 34 L4 24 L4 VSS - 40 35 K1 25 K1 VCC - 41 36 L3 26 L3 P46 D F D G B C E K X0A P47 42 37 K3 27 K3 X1A 43 38 K4 28 K4 INITX P48 SIN3_2 44 39 K6 29 J5 INT14_1 MAD02_0 Document Number: 002-05646 Rev. *E Page 22 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Pin State Type Type E K E K E K H[1] R P49 SOT3_2 (SDA3_2) 45 40 J6 30 K6 AIN0_1 TIOB0_0 INT20_1 MAD03_0 P4A SCK3_2 (SCL3_2) 46 41 L7 31 J6 BIN0_1 TIOB1_0 INT21_1 MAD04_0 P4B IGTRG_0 ZIN0_1 47 42 K7 32 L7 TIOB2_0 INT22_1 MAD05_0 P4C SCK7_1 (SCL7_1) AIN1_2 48 43 H6 33 K7 TIOB3_0 INT12_0 CEC0_0 MAD06_0 Document Number: 002-05646 Rev. *E Page 23 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Pin State Type Type H[1] K H[1] K E J E K E K E K P4D SOT7_1 (SDA7_1) 49 44 J7 34 J7 BIN1_2 TIOB4_0 INT13_0 MAD07_0 P4E SIN7_1 ZIN1_2 45 K8 35 K8 50 TIOB5_0 INT06_2 MAD08_0 - - - - SIN14_0 P70 SOT14_0 51 - - - (SDA14_0) TIOA4_2 P71 SCK14_0 52 - - - - (SCL14_0) TIOB4_2 INT13_2 P72 SIN2_0 53 - - - TIOA6_0 INT14_2 P73 SOT2_0 54 - - - - (SDA2_0) TIOB6_0 INT15_2 Document Number: 002-05646 Rev. *E Page 24 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Pin State Type Type E J C E G D A A A B P74 55 - - - - SCK2_0 (SCL2_0) MD1 56 46 K9 36 K9 PE0 57 47 L8 37 L8 58 48 L9 38 L9 MD0 X0 PE2 X1 59 49 L10 39 L10 PE3 60 50 L11 40 L11 VSS - 61 51 K11 41 K11 VCC - 62 52 J11 42 J11 P10 F L F P F L AN00 P11 AN01 SIN1_1 FRCK0_2 63 53 J10 43 J10 TIOB8_1 INT02_1 WKUP1 MAD09_0 P12 AN02 SOT1_1 64 54 J8 44 J8 (SDA1_1) IC00_2 TIOB9_1 MAD10_0 - - K10 - K10 - - J9 - J9 Document Number: 002-05646 Rev. *E VSS VSS - Page 25 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Pin State Type Type F L F M F M P13 AN03 SCK1_1 (SCL1_1) 65 55 H10 45 H10 IC01_2 TIOB10_1 RTCCO_1 SUBOUT_1 MAD11_0 P14 AN04 SIN0_1 66 56 H9 46 H9 IC02_2 TIOB11_1 INT03_1 MAD12_0 P15 AN05 SOT0_1 (SDA0_1) 67 57 H7 47 G10 IC03_2 TIOB12_1 INT14_0 MAD13_0 Document Number: 002-05646 Rev. *E Page 26 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Pin State Type Type F M F M P16 AN06 SCK0_1 68 58 G10 48 G9 (SCL0_1) TIOB13_1 INT15_0 MAD14_0 P17 AN07 69 59 G9 49 F10 SIN2_2 INT04_1 MAD15_0 70 60 H11 50 H11 AVCC - 71 61 F11 51 F11 AVRH - 72 62 G11 52 G11 AVSS - P18 AN08 SOT2_2 73 63 G8 53 F9 F L F L (SDA2_2) TIOA8_1 MAD16_0 P19 AN09 74 64 F10 54 E11 SCK2_2 (SCL2_2) TIOA9_1 MAD17_0 - - H8 - - VSS - P1A AN10 SIN4_1 75 65 F9 55 E10 IC00_1 F M TIOA10_1 INT05_1 MAD18_0 Document Number: 002-05646 Rev. *E Page 27 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Pin State Type Type F M F M F M F M F L P1B AN11 SOT4_1 (SDA4_1) 76 66 E11 56 E9 IC01_1 TIOA11_1 INT20_2 MAD19_0 P1C AN12 SCK4_1 (SCL4_1) 77 67 E10 - - IC02_1 TIOA12_1 INT21_2 MAD20_0 P1D AN13 CTS4_1 78 68 F8 - - IC03_1 TIOA13_1 INT22_2 MAD21_0 P1E AN14 RTS4_1 79 69 E9 - - DTTI0X_1 TIOA9_2 INT23_2 MAD22_0 P1F AN15 ADTG_5 70 D11 - - FRCK0_1 80 TIOB9_2 MAD23_0 SCK15_0 - - - (SCL15_0) - - Document Number: 002-05646 Rev. *E B10 - B10 VSS Page 28 of 149 CY9A150RB Series Pin No Pin Name BGA-96 I/O Circuit Pin State Type Type LQFP-120 LQFP-100 BGA-112 LQFP-80 - - C9 - C9 VSS - - - - - D11 VSS - P28 ADTG_4 SOT15_0 81 - - - - (SDA15_0) E J E K E J E J E K F L RTO05_1 TIOB6_2 P27 SIN15_0 82 - - - - RTO04_1 TIOA6_2 INT02_2 P26 SCK2_1 83 - - - - (SCL2_1) RTO03_1 TIOA11_2 P25 SOT2_1 (SDA2_1) 84 - - - RTO02_1 TIOA14_1 TIOB11_2 P24 SIN2_1 85 - - - - RTO01_1 TIOB14_1 INT01_2 P23 AN16 71 D10 57 D10 SCK0_0 86 (SCL0_0) TIOA7_1 - Document Number: 002-05646 Rev. *E - - - RTO00_1 Page 29 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Pin State Type Type F L F P F M P22 AN17 87 72 E8 58 D9 SOT0_0 (SDA0_0) ZIN1_1 TIOB7_1 P21 AN18 SIN0_0 88 73 C11 59 C11 BIN1_1 TIOB10_2 INT06_1 WKUP2 P20 AN19 CROUT_0 89 74 C10 60 C10 AIN1_1 TIOA10_2 INT05_0 MAD24_0 90 75 A11 - A11 VSS - 91 76 A10 - - VCC - P00 TRSTX 61 A10 TIOA14_2 92 77 A9 E I E I E I MCSX7_0 SCK8_0 - (SCL8_0) P01 93 78 B9 62 B9 TCK SWCLK P02 TDI 63 94 79 B11 TIOB14_2 B11 MCSX6_0 - Document Number: 002-05646 Rev. *E - SOT8_0 Page 30 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Pin State Type Type E I E I F O P03 95 80 A8 64 A9 TMS SWDIO P04 96 81 B8 65 B8 TDO SWO P05 AN20 TRACED0 SIN8_0 97 82 C8 - SIN4_2 TIOA5_2 INT00_1 MCSX5_0 - - D8 - - VSS - P06 AN21 TRACED1 SOT4_2 98 83 D9 - - F O F O (SDA4_2) TIOB5_2 INT01_1 MCSX4_0 P07 AN22 66 A8 ADTG_0 MCLKOUT_0 99 84 A7 INT23_1 TRACED2 - - SCK4_2 (SCL4_2) - - Document Number: 002-05646 Rev. *E - - A7 VSS - Page 31 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Pin State Type Type F O E N H[1] S H[1] R H[1] K P08 AN23 TRACED3 100 85 B7 - - CTS4_2 TIOA0_2 INT16_0 MCSX3_0 P09 TRACECLK RTS4_2 101 86 C7 - TIOB0_2 INT17_0 MCSX2_0 P0A SIN4_0 102 87 D7 67 C8 INT00_2 WKUP5 MCSX1_0 P0B SOT4_0 (SDA4_0) 103 88 A6 68 C7 TIOB6_1 INT18_0 CEC0_1 MCSX0_0 P0C SCK4_0 (SCL4_0) 104 89 B6 69 B7 TIOA6_1 INT19_0 MALE_0 - - Document Number: 002-05646 Rev. *E D4 - - VSS Page 32 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 - - C3 - C3 I/O Circuit Pin State Type Type VSS - P0D RTS4_0 105 90 C6 70 B6 TIOA3_2 E K E K INT20_0 MDQM0_0 P0E CTS4_0 106 91 A5 71 C6 TIOB3_2 INT21_0 MDQM1_0 - - - - A5 VSS - P0F NMIX CROUT_1 107 92 B5 72 A6 E H RTCCO_0 SUBOUT_0 WKUP0 P68 SCK3_0 108 - - - - (SCL3_0) E K TIOB7_2 INT12_2 P67 SOT3_0 109 - - - - (SDA3_0) E K E K TIOA7_2 INT22_0 P66 SIN3_0 110 - - - - TIOA12_2 INT11_2 Document Number: 002-05646 Rev. *E Page 33 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 I/O Circuit Pin State Type Type E K E K E K E K E J H[1] Q P65 SCK5_1 (SCL5_1) 111 - - - TIOB7_0 TIOB12_2 INT23_0 P64 SOT5_1 112 - - - - (SDA5_1) TIOA7_0 INT10_2 P63 TIOB15_1 93 D6 73 B5 113 INT03_0 MWEX_0 - - - - SIN5_1 P62 ADTG_3 SCK5_0 114 94 C5 74 C5 (SCL5_0) TIOA15_1 INT07_1 MOEX_0 P61 SOT5_0 115 95 B4 75 B4 (SDA5_0) TIOB2_2 P60 SIN5_0 IGTRG_1 TIOA2_2 116 96 C4 76 C4 INT15_1 WKUP3 CEC1_0 MRDY_0 Document Number: 002-05646 Rev. *E Page 34 of 149 CY9A150RB Series Pin No Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 117 97 A4 77 A4 I/O Circuit Pin State Type Type VCC - P80 118 98 A3 78 A3 TIOB15_0 E K E K INT16_1 P81 119 99 A2 79 A2 TIOA15_0 INT17_1 120 100 A1 80 A1 VSS - [1]. 5V tolerant I/O Document Number: 002-05646 Rev. *E Page 35 of 149 CY9A150RB Series 4.2 List of Pin Functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin Function Pin Name ADC Pin No Function Description LQFP-120 LQFP-100 BGA-112 LQFP-80 ADTG_0 99 ADTG_1 7 ADTG_2 84 A7 66 A8 7 D3 7 D3 23 18 F4 13 G3 114 94 C5 74 C5 81 - - - - ADTG_5 80 70 D11 - - ADTG_6 17 12 E4 12 G2 ADTG_7 35 30 J5 - - ADTG_3 ADTG_4 A/D converter external trigger input pin BGA-96 ADTG_8 - - - - - AN00 62 52 J11 42 J11 AN01 63 53 J10 43 J10 AN02 64 54 J8 44 J8 AN03 65 55 H10 45 H10 AN04 66 56 H9 46 H9 AN05 67 57 H7 47 G10 AN06 68 58 G10 48 G9 AN07 69 59 G9 49 F10 AN08 73 63 G8 53 F9 AN09 74 64 F10 54 E11 AN10 75 65 F9 55 E10 AN11 A/D converter analog input pin. 76 66 E11 56 E9 AN12 ANxx describes ADC ch.xx. 77 67 E10 - - AN13 78 68 F8 - - AN14 79 69 E9 - - AN15 80 70 D11 - - AN16 86 71 D10 57 D10 AN17 87 72 E8 58 D9 AN18 88 73 C11 59 C11 AN19 89 74 C10 60 C10 AN20 97 82 C8 - - AN21 98 83 D9 - - AN22 99 84 A7 66 A8 AN23 100 85 B7 - - Document Number: 002-05646 Rev. *E Page 36 of 149 CY9A150RB Series Pin Function Base Timer 0 Pin Name LQFP-100 BGA-112 LQFP-80 BGA-96 32 27 J4 - - 24 19 G3 14 H1 TIOA0_2 100 85 B7 - - TIOB0_0 45 40 J6 30 K6 14 9 E1 9 E2 TIOB0_2 101 86 C7 - - TIOA1_0 33 28 L5 - - 25 20 H1 15 H2 TIOA1_2 5 5 D1 5 D1 TIOB1_0 46 41 L7 31 J6 15 10 E2 10 E3 TIOB1_2 6 6 D2 6 D2 TIOA2_0 34 29 K5 - - 26 21 H2 16 H3 TIOA2_2 116 96 C4 76 C4 TIOB2_0 47 42 K7 32 L7 16 11 E3 11 G1 TIOB2_2 115 95 B4 75 B4 TIOA3_0 35 30 J5 - - 27 22 G4 17 J1 TIOA3_2 105 90 C6 70 B6 TIOB3_0 48 43 H6 33 K7 17 12 E4 12 G2 106 91 A5 71 C6 36 31 H5 21 L5 28 23 H3 18 J2 TIOA4_2 51 - - - - TIOB4_0 49 44 J7 34 J7 18 13 F1 - - TIOB4_2 52 - - - - TIOA5_0 37 32 L6 22 K5 29 24 J2 19 J4 TIOA5_2 97 82 C8 - - TIOB5_0 50 45 K8 35 K8 19 14 F2 - - 98 83 D9 - - TIOA0_0 TIOB0_1 TIOA1_1 TIOB1_1 Base Timer 2 TIOA2_1 TIOB2_1 Base Timer 3 TIOA3_1 TIOB3_1 Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin Base timer ch.2 TIOB pin Base timer ch.3 TIOA pin Base timer ch.3 TIOB pin TIOB3_2 Base Timer 4 TIOA4_0 TIOA4_1 TIOB4_1 Base Timer 5 Pin No LQFP-120 TIOA0_1 Base Timer 1 Function Description TIOA5_1 TIOB5_1 Base timer ch.4 TIOA pin Base timer ch.4 TIOB pin Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin TIOB5_2 Document Number: 002-05646 Rev. *E Page 37 of 149 CY9A150RB Series Pin Function Base Timer 6 Pin Name LQFP-120 53 - - - - Base timer ch.6 TIOA pin 104 89 B6 69 B7 TIOA6_2 82 - - - - TIOB6_0 54 - - - - 103 88 A6 68 C7 TIOB6_2 81 - - - - TIOA7_0 112 - - - - 86 71 D10 57 D10 TIOA7_2 109 - - - - TIOB7_0 111 - - - - 87 72 E8 58 D9 TIOB7_2 108 - - - - TIOA8_0 8 8 D5 8 E1 73 63 G8 53 F9 TIOA8_2 22 17 G2 - - TIOB8_0 2 2 C1 2 C1 63 53 J10 43 J10 TIOB8_2 23 18 F4 - - TIOA9_0 9 - - - - 74 64 F10 54 E11 TIOA9_2 79 69 E9 - - TIOB9_0 3 3 C2 3 C2 64 54 J8 44 J8 80 70 D11 - - TIOA6_0 TIOA6_1 TIOB6_1 Base Timer 7 TIOA7_1 TIOB7_1 Base Timer 8 TIOA8_1 TIOB8_1 Base Timer 9 TIOA9_1 TIOB9_1 Base timer ch.6 TIOB pin Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin Base timer ch.8 TIOA pin Base timer ch.8 TIOB pin Base timer ch.9 TIOA pin Base timer ch.9 TIOB pin TIOB9_2 Base Timer 10 TIOA10_0 TIOA10_1 Base timer ch.10 TIOA pin TIOA10_2 TIOB10_0 TIOB10_1 Base timer ch.10 TIOB pin TIOB10_2 Base Timer 11 Pin No Function Description TIOA11_0 TIOA11_1 Base timer ch.11 TIOA pin TIOA11_2 TIOB11_0 TIOB11_1 Base timer ch.11 TIOB TIOB11_2 Document Number: 002-05646 Rev. *E pin LQFP-100 BGA-112 LQFP-80 BGA-96 10 - - - - 75 65 F9 55 E10 89 74 C10 60 C10 4 4 B3 4 B3 65 55 H10 45 H10 88 73 C11 59 C11 11 - - - - 76 66 E11 56 E9 83 - - - - 5 5 D1 5 D1 66 56 H9 46 H9 84 - - - Page 38 of 149 CY9A150RB Series Pin Function Base Timer 12 Pin Name Function Description TIOA12_0 TIOA12_1 Base timer ch.12 TIOA pin TIOA12_2 TIOB12_0 TIOB12_1 Base timer ch.12 TIOB pin TIOB12_2 Base Timer 13 TIOA13_0 TIOA13_1 Base timer ch.13 TIOA pin TIOA13_2 TIOB13_0 TIOB13_1 Base timer ch.13 TIOB pin TIOB13_2 Base Timer 14 TIOA14_0 TIOA14_1 Base timer ch.14 TIOA pin TIOA14_2 TIOB14_0 TIOB14_1 Base timer ch.14 TIOB pin TIOB14_2 Base Timer 15 TIOA15_0 TIOA15_1 Base timer ch.15 TIOA pin TIOA15_2 TIOB15_0 TIOB15_1 Base timer ch.15 TIOB TIOB15_2 Document Number: 002-05646 Rev. *E pin Pin No LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 12 - - - - 77 67 E10 - - 110 - - - - 6 6 D2 6 D2 67 57 H7 47 G10 111 - - - - 13 - - - - 78 68 F8 - - 14 9 E1 9 E2 7 7 D3 7 D3 68 58 G10 48 G9 15 10 E2 10 E3 21 16 G1 - - 84 - - - - 92 77 A9 61 A10 20 15 F3 - - 85 - - - - 94 79 B11 63 B11 119 99 A2 79 A2 114 94 C5 74 C5 18 13 F1 - - 118 98 A3 78 A3 113 93 D6 73 B5 19 14 F2 - - Page 39 of 149 CY9A150RB Series Pin Function Pin Name SWCLK Function Description Serial wire debug interface LQFP-100 BGA-112 LQFP-80 BGA-96 93 78 B9 62 B9 95 80 A8 64 A9 96 81 B8 65 B8 JTAG test clock input pin 93 78 B9 62 B9 JTAG test data input pin 94 79 B11 63 B11 96 81 B8 65 B8 95 80 A8 64 A9 101 86 C7 - - TRACED0 97 82 C8 - - TRACED1 Trace data output pin of 98 83 D9 - - TRACED2 ETM SWDIO clock input pin Serial wire debug interface SWO TCK TDI Debugger Pin No LQFP-120 TDO TMS TRACECLK data input / output pin Serial wire viewer output pin JTAG debug data output pin JTAG test mode state input/output pin Trace CLK output pin of ETM TRACED3 TRSTX JTAG test reset input pin 99 84 A7 - - 100 85 B7 - A10 92 77 A9 61 External MAD00_0 36 31 H5 21 L5 Bus MAD01_0 37 32 L6 22 K5 MAD02_0 44 39 K6 29 J5 MAD03_0 45 40 J6 30 K6 MAD04_0 46 41 L7 31 J6 MAD05_0 47 42 K7 32 L7 MAD06_0 48 43 H6 33 K7 MAD07_0 49 44 J7 34 J7 MAD08_0 50 45 K8 35 K8 MAD09_0 63 53 J10 43 J10 MAD10_0 64 54 J8 44 J8 MAD11_0 65 55 H10 45 H10 H9 46 H9 MAD12_0 External bus interface 66 56 MAD13_0 address bus 67 57 H7 47 G10 MAD14_0 68 58 G10 48 G9 MAD15_0 69 59 G9 49 F10 MAD16_0 73 63 G8 53 F9 MAD17_0 74 64 F10 54 E11 MAD18_0 75 65 F9 55 E10 MAD19_0 76 66 E11 56 E9 MAD20_0 77 67 E10 - - MAD21_0 78 68 F8 - - MAD22_0 79 69 E9 - - MAD23_0 80 70 D11 - - MAD24_0 89 74 C10 60 C10 Document Number: 002-05646 Rev. *E Page 40 of 149 CY9A150RB Series Pin Function Pin Name Function Description Pin No LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 MCSX0_0 103 88 A6 68 C7 MCSX1_0 102 87 D7 67 C8 MCSX2_0 101 86 C7 - - MCSX3_0 External bus interface chip 100 85 B7 - - MCSX4_0 select output pin 98 83 D9 - - MCSX5_0 97 82 C8 - - MCSX6_0 94 79 B11 63 B11 MCSX7_0 92 77 A9 61 A10 MDQM0_0 External bus interface byte 105 90 C6 70 B6 MDQM1_0 mask signal output pin 106 91 A5 71 C6 114 94 C5 74 C5 113 93 D6 73 B5 18 - - - - 19 - - - - 21 - - - - 20 - - - - MADATA00_0 2 2 C1 2 C1 MADATA01_0 3 3 C2 3 C2 MADATA02_0 4 4 B3 4 B3 MADATA03_0 5 5 D1 5 D1 MADATA04_0 6 6 D2 6 D2 MADATA05_0 7 7 D3 7 D3 8 8 D5 8 E1 9 9 E1 9 E2 MADATA08_0 10 10 E2 10 E3 MADATA09_0 11 11 E3 11 G1 MADATA10_0 12 12 E4 12 G2 MADATA11_0 13 13 F1 - - MADATA12_0 14 14 F2 - - MOEX_0 MWEX_0 External bus interface read enable signal for SRAM External bus interface write enable signal for SRAM External bus interface ALE MNALE_0 signal to control NAND Flash memory output pin External bus interface CLE MNCLE_0 External Bus signal to control NAND Flash memory output pin External bus interface read MNREX_0 enable signal to control NAND Flash memory External bus interface write MNWEX_0 enable signal to control NAND Flash memory MADATA06_0 MADATA07_0 Document Number: 002-05646 Rev. *E External bus interface data bus Page 41 of 149 CY9A150RB Series Pin No Pin Function External Bus Pin Name LQFP-100 BGA-112 LQFP-80 BGA-96 15 15 F3 - - MADATA14_0 16 16 G1 - - MADATA15_0 17 17 G2 - - 104 89 B6 69 B7 116 96 C4 76 C4 99 84 A7 66 A8 2 2 C1 2 C1 97 82 C8 - - 102 87 D7 67 C8 MALE_0 MCLKOUT_0 INT00_0 INT00_1 INT00_2 INT01_0 INT01_1 INT01_2 INT02_0 INT02_1 INT02_2 INT03_0 INT03_1 INT03_2 INT04_0 INT04_1 INT04_2 INT05_0 INT05_1 Interrupt LQFP-120 MADATA13_0 MRDY_0 External Function Description INT05_2 INT06_0 INT06_1 INT06_2 INT07_0 INT07_1 INT07_2 INT08_0 INT08_1 INT08_2 Latch enable signal for multiplex External RDY input signal External bus clock output pin External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 04 input pin External interrupt request 05 input pin External interrupt request 06 input pin External interrupt request 07 input pin External interrupt request 08 input pin INT09_0 INT09_1 External interrupt request 09 input pin INT09_2 INT10_0 INT10_1 INT10_2 External interrupt request 10 input pin INT11_0 INT11_1 INT11_2 Document Number: 002-05646 Rev. *E External interrupt request 11 input pin 3 3 C2 3 C2 98 83 D9 - - 85 - - - - 4 4 B3 4 B3 63 53 J10 43 J10 82 - - - - 113 93 D6 73 B5 66 56 H9 46 H9 14 9 E1 9 E2 17 12 E4 12 G2 69 59 G9 49 F10 15 10 E2 10 E3 89 74 C10 60 C10 75 65 F9 55 E10 16 11 E3 11 G1 23 18 F4 13 G3 88 73 C11 59 C11 50 45 K8 35 K8 24 19 G3 14 H1 114 94 C5 74 C5 5 5 D1 5 D1 34 29 K5 - - 19 14 F2 - - 8 8 D5 8 E1 35 30 J5 - - 20 15 F3 - - 11 - - - - 36 31 H5 21 L5 21 16 G1 - - 112 - - - - 37 32 L6 22 K5 22 17 G2 - - 110 - - - - Page 42 of 149 CY9A150RB Series Pin No Pin Function Pin Name Function Description INT12_0 INT12_1 External interrupt request 12 input pin INT12_2 INT13_0 INT13_1 External interrupt request 13 input pin INT13_2 INT14_0 INT14_1 External interrupt request 14 input pin INT14_2 INT15_0 INT15_1 External interrupt request 15 input pin INT15_2 INT16_0 INT16_1 External interrupt request 16 input pin INT16_2 INT17_0 INT17_1 External interrupt request 17 input pin INT17_2 INT18_0 INT18_1 External Interrupt External interrupt request 18 input pin INT18_2 INT19_0 INT19_1 External interrupt request 19 input pin INT19_2 INT20_0 INT20_1 External interrupt request 20 input pin INT20_2 INT21_0 INT21_1 External interrupt request 21 input pin INT21_2 INT22_0 INT22_1 External interrupt request 22 input pin INT22_2 INT23_0 INT23_1 External interrupt request 23 input pin INT23_2 NMIX Document Number: 002-05646 Rev. *E Non-Maskable Interrupt input pin LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 48 43 H6 33 K7 32 27 J4 - - 108 - - - - 49 44 J7 34 J7 33 28 L5 - - 52 - - - - 67 57 H7 47 G10 44 39 K6 29 J5 53 - - - - 68 58 G10 48 G9 116 96 C4 76 C4 54 - - - - 100 85 B7 - - 118 98 A3 78 A3 12 - - - - 101 86 C7 - - 119 99 A2 79 A2 13 - - - - 103 88 A6 68 C7 6 6 D2 6 D2 26 21 H2 16 H3 104 89 B6 69 B7 7 7 D3 7 D3 28 23 H3 18 J2 105 90 C6 70 B6 45 40 J6 30 K6 76 66 E11 56 E9 106 91 A5 71 C6 46 41 L7 31 J6 77 67 E10 - - 109 - - - - 47 42 K7 32 L7 78 68 F8 - - 111 - - - - 99 84 A7 66 A8 79 69 E9 - - 107 92 B5 72 A6 Page 43 of 149 CY9A150RB Series Pin Function Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 P00 92 77 A9 61 P01 93 78 B9 62 B9 P02 94 79 B11 63 B11 P03 95 80 A8 64 A9 P04 96 81 B8 65 B8 P05 97 82 C8 - - P06 98 83 D9 - - P07 99 84 A7 66 A8 - P08 GPIO Pin No Function Description General-purpose I/O port 0 A10 100 85 B7 - P09 101 86 C7 - - P0A 102 87 D7 67 C8 P0B 103 88 A6 68 C7 P0C 104 89 B6 69 B7 P0D 105 90 C6 70 B6 P0E 106 91 A5 71 C6 P0F 107 92 B5 72 A6 P10 62 52 J11 42 J11 P11 63 53 J10 43 J10 P12 64 54 J8 44 J8 P13 65 55 H10 45 H10 P14 66 56 H9 46 H9 P15 67 57 H7 47 G10 P16 68 58 G10 48 G9 P17 69 59 G9 49 F10 P18 General-purpose I/O port 1 73 63 G8 53 F9 P19 74 64 F10 54 E11 P1A 75 65 F9 55 E10 P1B 76 66 E11 56 E9 P1C 77 67 E10 - - P1D 78 68 F8 - - P1E 79 69 E9 - - P1F 80 70 D11 - - P20 89 74 C10 60 C10 P21 88 73 C11 59 C11 P22 87 72 E8 58 D9 P23 86 71 D10 57 D10 85 - - - - P25 84 - - - - P26 83 - - - - P27 82 - - - - P28 81 - - - - P24 General-purpose I/O port 2 Document Number: 002-05646 Rev. *E Page 44 of 149 CY9A150RB Series Pin Function Pin Name LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 P30 14 9 E1 9 P31 15 10 E2 10 E3 P32 16 11 E3 11 G1 P33 17 12 E4 12 G2 P34 18 13 F1 - - P35 19 14 F2 - - P36 20 15 F3 - - P37 21 16 G1 - - P38 GPIO Pin No Function Description General-purpose I/O port 3 E2 22 17 G2 - - P39 23 18 F4 13 G3 P3A 24 19 G3 14 H1 P3B 25 20 H1 15 H2 P3C 26 21 H2 16 H3 P3D 27 22 G4 17 J1 P3E 28 23 H3 18 J2 P3F 29 24 J2 19 J4 P40 32 27 J4 - - P41 33 28 L5 - - P42 34 29 K5 - - P43 35 30 J5 - - P44 36 31 H5 21 L5 P45 37 32 L6 22 K5 41 36 L3 26 L3 42 37 K3 27 K3 P48 44 39 K6 29 J5 P49 45 40 J6 30 K6 P4A 46 41 L7 31 J6 P46 P47 General-purpose I/O port 4 P4B 47 42 K7 32 L7 P4C 48 43 H6 33 K7 P4D 49 44 J7 34 J7 P4E 50 45 K8 35 K8 P50 2 2 C1 2 C1 P51 3 3 C2 3 C2 P52 4 4 B3 4 B3 P53 5 5 D1 5 D1 P54 6 6 D2 6 D2 7 7 D3 7 D3 8 8 D5 8 E1 P57 9 - - - - P58 10 - - - - P59 11 - - - - P5A 12 - - - - P5B 13 - - - - P55 P56 General-purpose I/O port 5 Document Number: 002-05646 Rev. *E Page 45 of 149 CY9A150RB Series Pin Function Pin Name Pin No Function Description LQFP-120 BGA-112 LQFP-80 BGA-96 P60 116 96 C4 76 C4 P61 115 95 B4 75 B4 P62 114 94 C5 74 C5 P63 113 93 D6 73 B5 112 - - - - P65 111 - - - - P66 110 - - - - P67 109 - - - - P68 108 - - - - P70 51 - - - - P71 52 - - - - 53 - - - - P73 54 - - - - P74 55 - - - - 118 98 A3 78 A3 P81 119 99 A2 79 A2 PE0 56 46 K9 36 K9 58 48 L9 38 L9 59 49 L10 39 L10 P64 GPIO LQFP-100 P72 General-purpose I/O port 6 General-purpose I/O port 7 P80 General-purpose I/O port 8 PE2 General-purpose I/O port E PE3 Document Number: 002-05646 Rev. *E Page 46 of 149 CY9A150RB Series Pin Function Pin No Pin Name Function Description SIN0_0 Multi-function serial 88 73 C11 59 C11 SIN0_1 interface ch.0 input pin 66 56 H9 46 H9 SOT0_0 interface ch.0 output pin. (SDA0_0) 87 72 E8 58 D9 This pin operates as SOT0 67 57 H7 47 G10 86 71 D10 57 D10 68 58 G10 48 G9 LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 Multi-function serial when it is used in a UART/CSIO (operation Multi- function SOT0_1 modes 0 to 2) and as (SDA0_1) SDA0 when it is used in an Serial 0 I2C (operation mode 4). Multi-function serial SCK0_0 interface ch.0 clock I/O pin. (SCL0_0) This pin operates as SCK0 when it is used in a UART/CSIO (operation SCK0_1 modes 0 to 2) and as (SCL0_1) SCL0 when it is used in an I2C (operation mode 4). SIN1_0 Multi-function serial 8 - - - - SIN1_1 interface ch.1 input pin 63 53 J10 43 J10 SOT1_0 interface ch.1 output pin. (SDA1_0) 9 - - - - This pin operates as SOT1 64 54 J8 44 J8 10 - - - - 65 55 H10 45 H10 Multi-function serial when it is used in a UART/CSIO (operation Multi- function SOT1_1 modes 0 to 2) and as (SDA1_1) SDA1 when it is used in an Serial 1 I2C (operation mode 4). Multi-function serial SCK1_0 interface ch.1 clock I/O pin. (SCL1_0) This pin operates as SCK1 when it is used in a UART/CSIO (operation SCK1_1 modes 0 to 2) and as (SCL1_1) SCL1 when it is used in an I2C (operation mode 4). Document Number: 002-05646 Rev. *E Page 47 of 149 CY9A150RB Series Pin Function Pin Name Pin No Function Description LQFP-120 SIN2_0 Multi-function serial SIN2_1 interface ch.2 input pin SIN2_2 SOT2_0 Multi-function serial (SDA2_0) interface ch.2 output pin. LQFP-100 BGA-112 LQFP-80 BGA-96 53 - - - 85 - - - - 69 59 G9 49 F10 54 - - - - 84 - - - - 73 63 G8 53 F9 55 - - - - 83 - - - - 74 64 F10 54 E11 This pin operates as SOT2 SOT2_1 when it is used in a (SDA2_1) UART/CSIO (operation Multi- function SOT2_2 Serial 2 (SDA2_2) modes 0 to 2) and as SDA2 when it is used in an I2C (operation mode 4). SCK2_0 Multi-function serial (SCL2_0) interface ch.2 clock I/O pin. This pin operates as SCK2 SCK2_1 when it is used in a (SCL2_1) SCK2_2 (SCL2_2) UART/CSIO (operation modes 0 to 2) and as SCL2 when it is used in an 2 I C (operation mode 4). SIN3_0 Multi-function serial SIN3_1 interface ch.3 input pin SIN3_2 SOT3_0 Multi-function serial (SDA3_0) interface ch.3 output pin. 110 - - - - 2 2 C1 2 C1 44 39 K6 29 J5 109 - - - - 3 3 C2 3 C2 45 40 J6 30 K6 108 - - - - 4 4 B3 4 B3 46 41 L7 31 J6 This pin operates as SOT3 SOT3_1 when it is used in a (SDA3_1) UART/CSIO (operation Multi- function SOT3_2 Serial 3 (SDA3_2) modes 0 to 2) and as SDA3 when it is used in an I2C (operation mode 4). SCK3_0 Multi-function serial (SCL3_0) interface ch.3 clock I/O pin. This pin operates as SCK3 SCK3_1 when it is used in a (SCL3_1) SCK3_2 (SCL3_2) UART/CSIO (operation modes 0 to 2) and as SCL3 when it is used in an Document Number: 002-05646 Rev. *E I2C (operation mode 4). Page 48 of 149 CY9A150RB Series Pin Function Pin Name Pin No Function Description LQFP-120 SIN4_0 Multi-function serial SIN4_1 interface ch.4 input pin SIN4_2 SOT4_0 Multi-function serial (SDA4_0) interface ch.4 output pin. LQFP-100 BGA-112 LQFP-80 BGA-96 102 87 D7 67 C8 75 65 F9 55 E10 97 82 C8 - - 103 88 A6 68 C7 76 66 E11 56 E9 98 83 D9 - - 104 89 B6 69 B7 77 67 E10 - - 99 84 A7 - - This pin operates as SOT4 SOT4_1 when it is used in a (SDA4_1) UART/CSIO (operation SOT4_2 (SDA4_2) Multi- function Serial 4 modes 0 to 2) and as SDA4 when it is used in an I2C (operation mode 4). SCK4_0 Multi-function serial (SCL4_0) interface ch.4 clock I/O pin. This pin operates as SCK4 SCK4_1 when it is used in a (SCL4_1) SCK4_2 (SCL4_2) UART/CSIO (operation modes 0 to 2) and as SCL4 when it is used in an 2 I C (operation mode 4). RTS4_0 Multi-function serial 105 90 C6 70 B6 RTS4_1 interface ch.4 RTS output 79 69 E9 - - RTS4_2 pin 101 86 C7 - - CTS4_0 Multi-function serial 106 91 A5 71 C6 CTS4_1 interface ch.4 CTS input 78 68 F8 - - CTS4_2 pin 100 85 B7 - - 116 96 C4 76 C4 113 - - - - 20 15 F3 - - 115 95 B4 75 B4 112 - - - - 21 16 G1 - - 114 94 C5 74 C5 111 - - - - 22 17 G2 - - SIN5_0 Multi-function serial SIN5_1 interface ch.5 input pin SIN5_2 SOT5_0 Multi-function serial (SDA5_0) interface ch.5 output pin. SOT5_1 This pin operates as SOT5 when it is used in a (SDA5_1) Multi- function Serial 5 UART/CSIO (operation modes 0 to 2) and as SOT5_2 (SDA5_2) SDA5 when it is used in an I2C (operation mode 4). SCK5_0 Multi-function serial (SCL5_0) interface ch.5 clock I/O pin. SCK5_1 This pin operates as SCK5 when it is used in a (SCL5_1) UART/CSIO (operation modes 0 to 2) and as SCK5_2 SCL5 when it is used in an (SCL5_2) Document Number: 002-05646 Rev. *E I2C (operation mode 4). Page 49 of 149 CY9A150RB Series Pin Function Pin Name Pin No Function Description LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 SIN6_0 Multi-function serial 5 5 D1 5 D1 SIN6_1 interface ch.6 input pin 17 12 E4 12 G2 6 6 D2 6 D2 16 11 E3 11 G1 7 7 D3 7 D3 15 10 E2 10 E3 11 - - - - 50 45 K8 35 K8 12 - - - - 49 44 J7 34 J7 13 - - - - 48 43 H6 33 K7 Multi-function serial SOT6_0 interface ch.6 output pin. (SDA6_0) This pin operates as SOT6 when it is used in a UART/CSIO (operation Multi- function SOT6_1 modes 0 to 2) and as (SDA6_1) SDA6 when it is used in an I2C (operation mode 4). Serial 6 Multi-function serial SCK6_0 interface ch.6 clock I/O pin. (SCL6_0) This pin operates as SCK6 when it is used in a UART/CSIO (operation SCK6_1 modes 0 to 2) and as (SCL6_1) SCL6 when it is used in an I2C (operation mode 4). SIN7_0 Multi-function serial SIN7_1 interface ch.7 input pin SOT7_0 Multi-function serial (SDA7_0) interface ch.7 output pin. This pin operates as SOT7 when it is used in a SOT7_1 UART/CSIO (operation (SDA7_1) modes 0 to 2) and as Multi- function SDA7 when it is used in an Serial 7 I2C (operation mode 4). SCK7_0 Multi-function serial (SCL7_0) interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a SCK7_1 UART/CSIO (operation (SCL7_1) modes 0 to 2) and as SCL7 when it is used in an I2C (operation mode 4). Document Number: 002-05646 Rev. *E Page 50 of 149 CY9A150RB Series Pin Function Pin Name Pin No Function Description Multi-function serial SIN8_0 interface ch.8 input pin LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 97 82 C8 - - 94 79 B11 - - 92 77 A9 - - 17 12 E4 - - 18 13 F1 - - 19 14 F2 - - Multi-function serial interface ch.8 output pin. This pin operates as SOT8 SOT8_0 when it is used in a (SDA8_0) UART/CSIO (operation modes 0 to 2) and as Multi- function SDA8 when it is used in an Serial 8 I2C (operation mode 4). Multi-function serial interface ch.8 clock I/O pin. This pin operates as SCK8 SCK8_0 when it is used in a (SCL8_0) UART/CSIO (operation modes 0 to 2) and as SCL8 when it is used in an I2C (operation mode 4). Multi-function serial SIN9_0 interface ch.9 input pin Multi-function serial interface ch.9 output pin. This pin operates as SOT9 SOT9_0 when it is used in a (SDA9_0) UART/CSIO (operation modes 0 to 2) and as Multi- function SDA9 when it is used in an Serial 9 I2C (operation mode 4). Multi-function serial interface ch.9 clock I/O pin. This pin operates as SCK9 SCK9_0 when it is used in a (SCL9_0) UART/CSIO (operation modes 0 to 2) and as SCL9 when it is used in an I2C (operation mode 4). Document Number: 002-05646 Rev. *E Page 51 of 149 CY9A150RB Series Pin No Pin Function Pin Name Function Description Multi-function serial SIN10_0 interface ch.10 input pin LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 23 18 F4 13 G3 24 19 G3 14 H1 25 20 H1 15 H2 26 21 H2 16 H3 27 22 G4 17 J1 28 23 H3 18 J2 Multi-function serial interface ch.10 output pin. This pin operates as SOT10_0 (SDA10_0) SOT10 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA10 when it is used in an I2C (operation mode Multi- function 4). Serial 10 Multi-function serial interface ch.10 clock I/O pin. This pin operates as SCK10_0 SCK10 when it is used in (SCL10_0) a UART/CSIO (operation modes 0 to 2) and as SCL10 when it is used in an I2C (operation mode 4). Multi-function serial SIN11_0 interface ch.11 input pin Multi-function serial interface ch.11 output pin. This pin operates as SOT11_0 (SDA11_0) SOT11 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA11 when it is used in an I2C (operation mode Multi- function 4). Serial 11 Multi-function serial interface ch.11 clock I/O pin. This pin operates as SCK11_0 SCK11 when it is used in (SCL11_0) a UART/CSIO (operation modes 0 to 2) and as SCL11 when it is used in an I2C (operation mode 4). Document Number: 002-05646 Rev. *E Page 52 of 149 CY9A150RB Series Pin No Pin Function Pin Name Function Description Multi-function serial interface ch.12 SIN12_0 input pin LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 32 27 J4 - - 33 28 L5 - - 34 29 K5 - - 35 30 J5 - - 36 31 H5 - - 37 32 L6 - - Multi-function serial interface ch.12 output pin. SOT12_0 (SDA12_0) This pin operates as SOT12 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA12 when it is used in an I2C (operation mode Multi- function Serial 12 4). Multi-function serial interface ch.12 clock I/O pin. SCK12_0 (SCL12_0) This pin operates as SCK12 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL12 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.13 SIN13_0 input pin Multi-function serial interface ch.13 output pin. SOT13_0 (SDA13_0) This pin operates as SOT13 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA13 when Multi- function it is used in an I2C (operation mode Serial 13 4). Multi-function serial interface ch.13 clock I/O pin. SCK13_0 (SCL13_0) This pin operates as SCK13 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL13 when it is used in an I2C (operation mode 4). Document Number: 002-05646 Rev. *E Page 53 of 149 CY9A150RB Series Pin No Pin Function Pin Name SIN14_0 Function Description Multi-function serial interface ch.14 input pin LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 50 - - - - 51 - - - - 52 - - - - 82 - - - 81 - - - 80 - - - Multi-function serial interface ch.14 output pin. This pin operates as SOT14_0 (SDA14_0) SOT14 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA14 when it is used in an I2C (operation mode Multi- function 4). Serial 14 Multi-function serial interface ch.14 clock I/O pin. This pin operates as SCK14_0 SCK14 when it is used in (SCL14_0) a UART/CSIO (operation modes 0 to 2) and as SCL14 when it is used in an I2C (operation mode 4). SIN15_0 Multi-function serial interface ch.15 input pin Multi-function serial interface ch.15 output pin. This pin operates as SOT15_0 (SDA15_0) SOT15 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA15 when it is used in an I2C (operation mode Multi- function 4). Serial 15 Multi-function serial interface ch.15 clock I/O pin. This pin operates as SCK15_0 SCK15 when it is used in (SCL15_0) a UART/CSIO (operation modes 0 to 2) and as SCL15 when it is used in an I2C (operation mode 4). Document Number: 002-05646 Rev. *E Page 54 of 149 CY9A150RB Series Pin No Pin Function Pin Name Function Description DTTI0X_0 Input signal of waveform LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96 23 18 F4 13 G3 79 69 E9 - - 18 13 F1 - - 80 70 D11 - - FRCK0_2 63 53 J10 43 J10 generator to control outputs DTTI0X_1 RTO00 to RTO05 of multifunction timer 0. FRCK0_0 FRCK0_1 16-bit free-run timer ch.0 external clock input pin IC00_0 22 17 G2 - - Multi- function IC00_1 75 65 F9 55 E10 Timer 0 IC00_2 64 54 J8 44 J8 IC01_0 21 16 G1 - - IC01_1 16-bit input capture input pin 76 66 E11 56 E9 IC01_2 of multi-function timer 0. 65 55 H10 45 H10 IC02_0 ICxx describes channel 20 15 F3 - - IC02_1 number. 77 67 E10 - - IC02_2 66 56 H9 46 H9 IC03_0 19 14 F2 - - IC03_1 78 68 F8 - - IC03_2 67 57 H7 47 G10 Document Number: 002-05646 Rev. *E Page 55 of 149 CY9A150RB Series Pin No Pin Function Pin Name Function Description LQFP-120 RTO00_0 Waveform generator output (PPG00_0) pin of multi-function timer 0. LQFP-100 BGA-112 LQFP-80 BGA-96 24 19 G3 14 H1 86 71 D10 57 D10 25 20 H1 15 H2 85 - - - - 26 21 H2 16 H3 84 - - - - 27 22 G4 17 J1 83 - - - - 28 23 H3 18 J2 82 - - - - 29 24 J2 19 J4 81 - - - - This pin operates as PPG00 RTO00_1 (PPG00_1) when it is used in PPG0 output mode. RTO01_0 Waveform generator output (PPG00_0) pin of multi-function timer 0. This pin operates as PPG00 RTO01_1 (PPG00_1) when it is used in PPG0 output mode. RTO02_0 Waveform generator output (PPG02_0) pin of multi-function timer 0. This pin operates as PPG02 RTO02_1 (PPG02_1) Multi- function when it is used in PPG0 output mode. RTO03_0 Waveform generator output (PPG02_0) pin of multi-function timer 0. Timer 0 This pin operates as PPG02 RTO03_1 (PPG02_1) when it is used in PPG0 output mode. RTO04_0 Waveform generator output (PPG04_0) pin of multi-function timer 0. This pin operates as PPG04 RTO04_1 (PPG04_1) when it is used in PPG0 output mode. RTO05_0 Waveform generator output (PPG04_0) pin of multi-function timer 0. This pin operates as PPG04 RTO05_1 when it is used in PPG0 (PPG04_1) output mode. IGTRG_0 PPG IGMT mode external 46 41 L7 31 J6 IGTRG_1 trigger input pin 116 96 C4 76 C4 Document Number: 002-05646 Rev. *E Page 56 of 149 CY9A150RB Series Pin Function Pin Name Quadrature AIN0_0 Position/ AIN0_1 Revolution AIN0_2 Counter 0 BIN0_0 BIN0_1 LQFP-120 QPRC ch.0 AIN input pin QPRC ch.0 BIN input pin BIN0_2 ZIN0_0 ZIN0_1 Pin No Function Description QPRC ch.0 ZIN input pin LQFP-100 BGA-112 LQFP-80 BGA-96 14 9 E1 9 45 40 J6 30 E2 K6 2 2 C1 2 C1 15 10 E2 10 E3 46 41 L7 31 J6 3 3 C2 3 C2 16 11 E3 11 G1 47 42 K7 32 L7 ZIN0_2 4 4 B3 4 B3 Quadrature AIN1_1 89 74 C10 60 C10 Position/ AIN1_2 48 43 H6 33 K7 Revolution BIN1_1 88 73 C11 59 C11 Counter 1 BIN1_2 49 44 J7 34 J7 87 72 E8 58 D9 ZIN1_1 ZIN1_2 Real-time clock RTCCO_0 RTCCO_1 QPRC ch.1 AIN input pin QPRC ch.1 BIN input pin QPRC ch.1 ZIN input pin 0.5 seconds pulse output pin of Real-time clock RTCCO_2 SUBOUT_ 0 SUBOUT_ Sub clock output pin 1 SUBOUT_ 2 Low-Power Consumption Mode WKUP0 WKUP1 WKUP2 WKUP3 WKUP4 WKUP5 HDMI- Deep standby mode return signal input pin 0 Deep standby mode return signal input pin 1 Deep standby mode return signal input pin 2 Deep standby mode return signal input pin 3 Deep standby mode return signal input pin 4 Deep standby mode return signal input pin 5 HDMI-CEC/Remote CEC0_0 CEC/ Remote 50 45 K8 35 K8 107 92 B5 72 A6 65 55 H10 45 H10 24 19 G3 14 H1 107 92 B5 72 A6 65 55 H10 45 H10 24 19 G3 14 H1 107 92 B5 72 A6 63 53 J10 43 J10 88 73 C11 59 C11 116 96 C4 76 C4 14 9 E1 9 E2 102 87 D7 67 C8 48 43 H6 33 K7 Control Reception ch.0 Control CEC0_1 input/output pin 103 88 A6 68 C7 Reception CEC1_0 HDMI-CEC/Remote 116 96 C4 76 C4 8 8 D5 8 E1 Control Reception ch.1 CEC1_1 Document Number: 002-05646 Rev. *E input/output pin Page 57 of 149 CY9A150RB Series Pin function Pin name Pin No Function description LQFP-120 Reset LQFP-100 BGA-112 LQFP-80 BGA-96 External Reset Input pin. INITX A reset is valid when 43 38 K4 28 K4 57 47 L8 37 L8 56 46 K9 36 K9 B1 INITX=L. Mode Mode 0 pin. During normal operation, MD0=L must be input. MD0 During serial programming to Flash memory, MD0=H must be input. Mode 1 pin. During serial MD1 programming to Flash memory, MD1=L must be input. Power GND VCC Power supply pin 1 1 B1 1 VCC Power supply pin 31 26 J1 - - VCC Power supply pin 40 35 K1 25 K1 VCC Power supply pin 61 51 K11 41 K11 VCC Power supply pin 91 76 A10 - - VCC Power supply pin 117 97 A4 77 A4 VSS GND pin - - - - F1 VSS GND pin - - - - F2 VSS GND pin - - - - F3 VSS GND pin - - B2 - B2 VSS GND pin 30 25 L1 20 L1 VSS GND pin - - K2 - K2 VSS GND pin - - J3 - J3 VSS GND pin - - H4 - - VSS GND pin - - - - L6 VSS GND pin 39 34 L4 24 L4 VSS GND pin 60 50 L11 40 L11 VSS GND pin - - K10 - K10 VSS GND pin - - J9 - J9 VSS GND pin - - H8 - - VSS GND pin - - B10 - B10 VSS GND pin - - C9 - C9 VSS GND pin - - - - D11 VSS GND pin 90 75 A11 - A11 VSS GND pin - - D8 - - VSS GND pin - - - - A7 VSS GND pin - - D4 - - VSS GND pin - - C3 - C3 VSS GND pin - - - - A5 VSS GND pin 120 100 A1 80 A1 Document Number: 002-05646 Rev. *E Page 58 of 149 CY9A150RB Series Pin Function Clock Pin Name X0 LQFP-120 Main clock (oscillation) input pin Sub clock (oscillation) X0A X1 X1A ADC Power Pin No Function Description input pin Main clock (oscillation) I/O pin Sub clock (oscillation) I/O pin LQFP-100 BGA-112 LQFP-80 BGA-96 58 48 L9 38 L9 41 36 L3 26 L3 59 49 L10 39 L10 42 37 K3 27 K3 CROUT_0 Built-in High-speed CR- 89 74 C10 60 C10 CROUT_1 osc clock output port 107 92 B5 72 A6 70 60 H11 50 H11 71 61 F11 51 F11 72 62 G11 52 G11 38 33 L2 23 L2 A/D converter analog AVCC power supply pin A/D converter analog AVRH reference voltage input pin ADC AVSS A/D converter GND pin GND C pin C Power stabilization capacity pin Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: 002-05646 Rev. *E Page 59 of 149 CY9A150RB Series 5. I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function When the main oscillation is selected. ◼ Oscillation feedback resistor: Pull-up Approximately 1 MΩ resistor ◼ With standby mode control P-ch P-ch Digital output X1 When the GPIO is selected. ◼ CMOS level output. ◼ CMOS level hysteresis input ◼ With pull-up resistor control N-ch Digital output ◼ With standby mode control ◼ Pull-up resistor: Approximately 33 kΩ R ◼ IOH= -4 mA, IOL= 4 mA Pull-up resistor control Digital input Standby mode control Clock input Feedback resistor Standby mode control Digital input Standby mode control Pull-up resistor R P-ch P-ch Digital output X0 N-ch Digital output Pull-up resistor control Document Number: 002-05646 Rev. *E Page 60 of 149 CY9A150RB Series Type Circuit Remarks B ◼ CMOS level hysteresis input ◼ Pull-up resistor: Approximately 33 kΩ Pull-up resistor Digital input C ◼ Open drain output Digital input ◼ CMOS level hysteresis input Digital output N-ch Document Number: 002-05646 Rev. *E Page 61 of 149 CY9A150RB Series Type Circuit Remarks D It is possible to select the sub oscillation / GPIO function Pull-up When the sub oscillation is selected. resistor ◼ Oscillation feedback resistor : Approximately 5MΩ P-ch P-ch Digital output X1A ◼ With standby mode control When the GPIO is selected. ◼ CMOS level output. ◼ CMOS level hysteresis input N-ch Digital output ◼ With pull-up resistor control ◼ With standby mode control R ◼ Pull-up resistor: Approximately 33 kΩ Pull-up resistor control ◼ IOH= -4 mA, IOL= 4 mA Digital input Standby mode control Clock input Feedback resistor Standby mode control Digital input Standby mode control Pull-up resistor R P-ch P-ch Digital output X0A N-ch Digital output Pull-up resistor control Document Number: 002-05646 Rev. *E Page 62 of 149 CY9A150RB Series Type Circuit Remarks E ◼ CMOS level output ◼ CMOS level hysteresis input ◼ With pull-up resistor control ◼ With standby mode control P-ch P-ch Digital output ◼ Pull-up resistor : Approximately 33 kΩ ◼ IOH= -4 mA, IOL= 4 mA ◼ When this pin is used as an I2C pin, the digital output P-ch transistor is always off N-ch Digital output R Pull-up resistor control Digital input Standby mode control F ◼ CMOS level output ◼ CMOS level hysteresis input ◼ With input control ◼ Analog input P-ch P-ch Digital output ◼ With pull-up resistor control ◼ With standby mode control ◼ Pull-up resistor : Approximately 33 kΩ ◼ IOH= -4 mA, IOL= 4 mA N-ch R Digital output ◼ When this pin is used as an I2C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input Standby mode control Analog input Input control Document Number: 002-05646 Rev. *E Page 63 of 149 CY9A150RB Series Type Circuit Remarks G CMOS level hysteresis input Mode input H ◼ CMOS level output ◼ CMOS level hysteresis input ◼ 5 V tolerant ◼ With pull-up resistor control P-ch P-ch Digital output ◼ With standby mode control ◼ Pull-up resistor: Approximately 33 kΩ ◼ IOH= -4 mA, IOL= 4 mA ◼ Available to control PZR registers. ◼ When this pin is used as an I2C pin, the N-ch Digital output digital output P-ch transistor is always off R Pull-up resistor control Digital input Standby mode control Document Number: 002-05646 Rev. *E Page 64 of 149 CY9A150RB Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. ◼ Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. ◼ Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. ◼ Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. ◼ Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. 2. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. Be sure that abnormal current flows do not occur during the power-on sequence. Document Number: 002-05646 Rev. *E Page 65 of 149 CY9A150RB Series ◼ Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. ◼ Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. ◼ Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales representative. ◼ Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason, it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. ◼ Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Document Number: 002-05646 Rev. *E Page 66 of 149 CY9A150RB Series ◼ Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. ◼ Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. 2. 3. 4. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. ◼ Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h ◼ Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. 2. 3. 4. 5. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. Ground all fixtures and instruments, or protect with anti-static measures. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. Document Number: 002-05646 Rev. *E Page 67 of 149 CY9A150RB Series 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-05646 Rev. *E Page 68 of 149 CY9A150RB Series 7. Handling Devices 7.1 Power Supply Pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin near this device. 7.2 Stabilizing Power Supply Voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. 7.3 Crystal Oscillator Circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. 7.4 Sub Crystal Oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. ◼ Surface mount type Size : More than 3.2 mm × 1.5 mm Load capacitance : Approximately 6 pF to 7 pF ◼ Lead type Load capacitance : Approximately 6 pF to 7 pF Document Number: 002-05646 Rev. *E Page 69 of 149 CY9A150RB Series 7.5 Using an external clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. Example of Using an External Clock Device X0(X0A) Can be used as general-purpose I/O ports. 7.6 Set as External clock input X1(PE3), X1A (P47) Handling when using Multi-function serial pin as I2C pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I 2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. 7.7 C pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μF would be recommended for this series. C Device CS VSS GND 7.8 Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistor stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Document Number: 002-05646 Rev. *E Page 70 of 149 CY9A150RB Series 7.9 Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC = VCC and AVSS = VSS. Turning on : VCC →AVCC → AVRH Turning off : AVRH → AVCC → VCC 7.10 Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. 7.11 Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. 7.12 Pull-Up function of 5 V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O. Document Number: 002-05646 Rev. *E Page 71 of 149 CY9A150RB Series 8. Block Diagram TRSTX,TCK, TDI,TMS TDO SWJ-DP ETM* TRACEDx, TRACECLK TPIU* ROM Table SRAM0 16/24/32 Kbyte D NVIC Sys AHB-APB Bridge: APB0(Max 40 MHz) Dual-Timer WatchDog Timer (Software) Clock Reset Generator INITX WatchDog Timer (Hardware) SRAM1 16/24/32 Kbyte Multi-layer AHB (Max 40 MHz) Cortex-M3　Core I @40 MHz(Max) Flash I/F Security On-Chip Flash 256+32 Kbyte/ 384+32 Kbyte/ 512+32 Kbyte DMAC 8ch. CSV X0 X1 X0A X1A CROUT AVCC, AVSS, AVRH ANxx Main Osc Sub Osc Source Clock PLL CR 4 MHz AHB-AHB Bridge CLK CR 100 kHz MADx External Bus I/F 12-bit A/D Converter Unit 0 Unit 1 Power-On Reset ADTGx LVD Ctrl TIOAx TIOBx MADATAx Base Timer 16-bit 16ch./ 32-bit 8ch. IRQ-Monitor MCSXx,MDQMx, MOEX,MWEX, MALE,MRDY, MNALE,MNCLE, MNWEX,MNREX, MCLKOUT LVD Regulator C QPRC 2ch. A/D Activation Compare 2ch. IC0x FRCK0 16-bit Input Capture 4ch. 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. AHB-APB Bridge : APB2 (Max 40 MHz) AINx BINx ZINx AHB-APB Bridge : APB1 (Max 40 MHz) CRC Accelerator Watch Counter Deep Standby Ctrl WKUPx HDMI-CEC/ Remote Reciver Control CEC0, CEC1 Real-Time Clock RTCCO, SUBOUT External Interrupt Controller 24-pin + NMI INTx NMIX MODE-Ctrl MD0, MD1 DTTI0X RTO0x P0x, P1x, Waveform Generator 3ch. GPIO PIN-Function-Ctrl . . . PEx IGTRG 16-bit PPG 3ch. Multi-function Timer × 1 Multi-Function Serial I/F 16ch. HW flow control(ch.4) SCKx SINx SOTx CTS4 RTS4 *:For the CY9AF154MB, CY9AF155MB, and CY9AF156MB, ETM is not available. 9. Memory Size See Memory size in Product Lineup to confirm the memory size. Document Number: 002-05646 Rev. *E Page 72 of 149 CY9A150RB Series 10. Memory Map 10.1 Memory Map (1) Peripherals Area 0x41FF_FFFF Reserved 0xFFFF_FFFF Reserved 0xE010_0000 0xE000_0000 Cortex-M3 Private Peripherals 0x4006_1000 0x4006_0000 0x4004_0000 0x4003_F000 Reserved 0x4003_C000 0x4003_B000 0x4003_A000 0x7000_0000 0x6000_0000 0x4003_9000 External Device Area 0x4003_8000 0x4003_6000 Reserved 0x4400_0000 0x4200_0000 0x4000_0000 32Mbytes Bit band alias Peripherals 0x4003_5000 0x2400_0000 0x2200_0000 0x4003_3000 0x4003_2000 0x4003_1000 0x2000_0000 0x1FF8_0000 0x0020_8000 0x0020_0000 See "lMemory Map (2)" for the memory size details. 0x0010_4000 0x0010_0000 0x4002_F000 0x4002_E000 32Mbytes Bit band alias 0x4002_8000 Reserved 0x4002_7000 0x4002_6000 0x2008_0000 0x4002_5000 SRAM1 SRAM0 Reserved Flash(Work area) Reserved Security/CR Trim 0x4002_4000 0x4002_0000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 Document Number: 002-05646 Rev. *E Reserved LVD/DS mode GPIO Reserved Int-Req.Read EXTI Reserved CR Trim Reserved A/DC QPRC Base Timer PPG Reserved 0x4001_5000 0x0000_0000 EXT-bus I/F Reserved RTC Watch Counter CRC MFS 0x4002_1000 0x4001_6000 Flash(Main area) Reserved HDMI-CEC/ 0x4003_4000 Remote Control Receiver 0x4003_0000 Reserved DMAC MFT Unit0 Reserved Dual Timer Reserved SW WDT HW WDT Clock/Reset Reserved Flash I/F Page 73 of 149 CY9A150RB Series 10.2 Memory Map (2) For more information about Flash (Main area)/Flash (Work area), see CY9AB40N/A40N/340N/140N/150R, CY9B520M/320M/120M Series Flash Programming Manual. Document Number: 002-05646 Rev. *E Page 74 of 149 CY9A150RB Series 10.3 Peripheral Address Map Start address End address 0x4000_0000 0x4000_0FFF Bus Peripherals Flash memory I/F register AHB 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF Software Watchdog timer APB0 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function timer unit0 0x4002_1000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt 0x4003_1000 0x4003_1FFF Interrupt Source Check Register 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF HDMI-CEC/Remote control Reception 0x4003_5000 0x4003_57FF Low-Voltage Detector 0x4003_5800 0x4003_5FFF APB1 Quadrature Position/Revolution Counter Deep standby mode Controller APB2 0x4003_6000 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_EFFF Reserved 0x4003_F000 0x4003_FFFF External bus interface 0x4004_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF 0x4006_1000 0x41FF_FFFF Document Number: 002-05646 Rev. *E AHB DMAC register Reserved Page 75 of 149 CY9A150RB Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings. ◼ INITX=0 This is the period when the INITX pin is the L level. ◼ INITX=1 This is the period when the INITX pin is the H level. ◼ SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0. ◼ SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1. ◼ Input enabled Indicates that the input function can be used. ◼ Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L. ◼ Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state. ◼ Setting disabled Indicates that the setting is disabled. ◼ Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. ◼ Analog input is enabled Indicates that the analog input is enabled. ◼ Trace output Indicates that the trace function can be used. ◼ GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port. Document Number: 002-05646 Rev. *E Page 76 of 149 CY9A150RB Series 11.1 List of Pin Status Pin status type Power-on Function group reset or low- INITX voltage input detection state state Device internal reset state Power supply Return Run mode or Timer mode, Sleep RTC mode, or mode Stop mode state Deep standby Rtc from mode or Deep Deep standby Stop mode standby state mode state state Power Power supply stable unstable supply Power Power supply stable Power supply stable stable - INITX = 0 INITX = 1 INITX = 1 - - - - supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 INITX = 1 SPL = 1 - GPIO GPIO Setting Setting Setting selected disabled disabled disabled Maintain Maintain previous previous state state Hi-Z / selected Internal input fixed at 0 Internal input Hi-Z / Internal GPIO input selected fixed at 0 fixed at 0 A Main crystal oscillator input pin/ External main clock Input Input Input Input Input Input Input Input Input enabled enabled enabled enabled enabled enabled enabled enabled enabled input selected GPIO Setting Setting Setting selected disabled disabled disabled External main clock Setting Setting Setting input disabled disabled disabled selected B Hi-Z / Main crystal Internal input oscillator fixed at 0/ output pin or Input enable C INITX input pin Maintain Maintain previous previous state state Hi-Z / Internal input fixed at 0 Hi-Z / GPIO selected Internal input fixed at 0 Internal GPIO input selected fixed at 0 Hi-Z / Maintain Maintain previous previous state state Maintain Maintain Maintain Maintain Maintain Maintain previous previous previous previous previous previous state/ state/ state/ state/ state/ state/ Internal input fixed at 0 Maintain Hi-Z / previous state Maintain Internal previous input state fixed at 0 Hi-Z / Hi-Z / When When When When When When Internal Internal oscillation oscillatio oscillatio oscillatio oscillatio oscillatio input input stops[1], n stops[1], n stops[1], n stops[1], n stops[1], n stops[1], fixed at 0 fixed at 0 Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal Internal input fixed input input input input input at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 fixed at 0 Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Input Input Input Input Input Input Input Input Input enabled enabled enabled enabled enabled enabled enabled enabled enabled Document Number: 002-05646 Rev. *E Page 77 of 149 CY9A150RB Series Pin status type Power-on Function group reset or low- INITX voltage input detection state state Device internal reset state Power supply Timer mode, Sleep RTC mode, or mode Stop mode state from mode or Deep Deep standby Stop mode standby state mode state supply state Power Power supply stable Power supply stable supply INITX = 1 INITX = 1 INITX = 1 stable - INITX = 0 INITX = 1 INITX = 1 - - - - stable SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Mode Input Input Input Input Input Input Input Input Input input pin enabled enabled enabled enabled enabled enabled enabled enabled enabled Mode Input Input Input Input Input Input Input Input Input input pin enabled enabled enabled enabled enabled enabled enabled enabled enabled GPIO Setting Setting Setting Maintain Maintain Hi-Z / selected disabled disabled disabled previous previous Input state state enabled Maintain Maintain previous previous state state E F mode or Deep standby Rtc Power Power supply stable unstable D Return Run GPIO Setting Setting Setting selected disabled disabled disabled Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected Internal input fixed at 0 Hi-Z / Input enabled GPIO selected Hi-Z / Internal GPIO input selected fixed at 0 Sub crystal oscillator input pin / Input Input Input Input Input Input Input Input Input External sub enabled enabled enabled enabled enabled enabled enabled enabled enabled clock input selected Document Number: 002-05646 Rev. *E Page 78 of 149 CY9A150RB Series Poweron reset Pin status type or lowvoltage Function group detectio INITX input state Device internal reset state n state Power supply Return Run mode or Timer mode, Deep standby Rtc mode Sleep RTC mode, or or Deep standby Stop mode Stop mode state mode state state Power supply stable supply INITX = 0 INITX = 1 INITX = 1 - - - - mode Power Power supply stable Power supply stable supply INITX = 1 INITX = 1 INITX = 1 stable - standby state Power unstable from Deep stable SPL = 0 SPL = 1 SPL = 0 SPL = 1 - GPIO GPIO Setting Setting Setting selected disabled disabled disabled Maintain Maintain previous previous state state Hi-Z / selected Internal input fixed Internal input fixed at 0 Hi-Z / Internal GPIO input fixed selected at 0 at 0 External G sub clock Setting Setting Setting input disabled disabled disabled selected Maintain Maintain previous previous state state Hi-Z / Internal Sub crystal oscillator input fixed at 0/ output pin Hi-Z / Hi-Z / Internal Internal input input fixed at 0 fixed at 0 Maintain previous state or Input enable NMIX Setting Setting Setting selected disabled disabled disabled Resource H other than above selected Hi-Z Hi-Z / Hi-Z / Input Input enabled enabled GPIO Hi-Z / Internal input fixed at 0 Maintain previous state Maintain Maintain previous previous previous state/ state/ state/When When When oscillation oscillation oscillation [2] Internal input fixed at 0 Maintain [2] Hi-Z/ [2] stops , Hi- stops , stops , Z / Internal Hi-Z / Hi-Z/ input fixed Internal Internal at 0 input fixed input fixed at 0 at 0 Maintain previous state/When oscillation stops[2], Hi-Z/ Internal input fixed at 0 Maintain previous state Maintain previous state/ When oscillation stops[2], Hi-Z/ Internal input fixed at 0 Maintain previous state Maintain Maintain WKUP previous previous Hi-Z / input state state Internal enabled Hi-Z / WKUP GPIO input selected enabled input fixed at 0 selected Document Number: 002-05646 Rev. *E Page 79 of 149 CY9A150RB Series Poweron reset Pin status type or lowvoltage Function group detectio INITX input state Device internal reset state n state Power supply selected I Power supply stable GPIO Timer mode, Deep standby Rtc mode Sleep RTC mode, or or Deep standby Stop mode Stop mode state mode state state supply from Deep standby mode state Power Power supply stable Power supply stable supply INITX = 1 INITX = 1 INITX = 1 stable stable - INITX = 0 INITX = 1 INITX = 1 - - - - Pull-up / Pull-up / Maintain Maintain Maintain Maintain Input Input previous previous previous previous enabled enabled state state state state Hi-Z Resource selected mode or Power unstable JTAG Return Run Setting Setting Setting disabled disabled disabled SPL = 0 Maintain Maintain previous previous state state SPL = 1 SPL = 1 - GPIO Hi-Z / selected Internal input fixed at 0 selected SPL = 0 Internal input fixed Hi-Z / Internal GPIO input fixed selected at 0 at 0 Resource GPIO selected J Hi-Z GPIO Hi-Z / Hi-Z / Maintain Maintain Input Input previous previous enabled enabled state state Hi-Z / input fixed at 0 Internal input fixed Hi-Z / Internal GPIO input fixed selected at 0 at 0 selected External interrupt Setting Setting Setting enabled disabled disabled disabled Maintain previous state selected GPIO Resource K selected Internal other than Maintain Maintain selected above previous previous Internal selected state state Hi-Z Hi-Z / Hi-Z / Input Input enabled enabled GPIO Hi-Z / input fixed Internal at 0 Hi-Z / Internal GPIO input fixed selected at 0 input fixed at 0 selected Document Number: 002-05646 Rev. *E Page 80 of 149 CY9A150RB Series Poweron reset INITX Pin status type or low- internal input voltage Function group Device detectio mode or reset state state Power Deep standby Rtc mode Sleep RTC mode, or or Deep standby Stop mode Stop mode state mode state Power supply stable supply INITX = 0 INITX = 1 INITX = 1 - - - - Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal input input input fixed at 0 fixed at 0 fixed at 0 / / / Analog Analog Analog input input input enabled enabled enabled Analog Hi-Z selected L standby mode Power Power supply stable Power supply stable supply INITX = 1 INITX = 1 INITX = 1 stable - from Deep state Power unstable input Timer mode, state n state supply Return Run stable SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal input fixed input fixed input fixed input fixed input fixed at 0 / at 0 / at 0 / at "0" / at 0 / Analog Analog Analog Analog Analog input input input input input enabled enabled enabled enabled enabled Resource GPIO other than above Setting Setting Setting selected disabled disabled disabled Maintain Maintain previous previous state state GPIO Hi-Z / selected Internal input fixed at 0 Internal input fixed Hi-Z / Internal GPIO input fixed selected at 0 at 0 selected Analog input Hi-Z selected Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal input input input fixed at 0 fixed at 0 fixed at 0 / / / Analog Analog Analog input input input enabled enabled enabled Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal input fixed input fixed input fixed input fixed input fixed at 0 / at 0 / at 0 / at 0 / at 0 / Analog Analog Analog Analog Analog input input input input input enabled enabled enabled enabled enabled External M Maintain interrupt previous enabled state selected Resource Setting Setting Setting other than disabled disabled disabled above GPIO Maintain Maintain selected previous previous Internal state state Hi-Z / Internal selected input fixed GPIO at 0 input fixed Hi-Z / Internal GPIO input fixed selected at 0 at 0 selected Document Number: 002-05646 Rev. *E Page 81 of 149 CY9A150RB Series Poweron reset Pin status type or lowvoltage Function group detectio INITX input state Device internal reset state n state Power supply - Analog input Hi-Z selected N mode or Timer mode, Deep standby Rtc mode Sleep RTC mode, or or Deep standby Stop mode Stop mode state mode state state Power supply stable supply INITX = 1 standby mode Power Power supply stable Power supply stable supply INITX = 1 INITX = 1 INITX = 1 stable INITX = 0 from Deep state Power unstable - Return Run stable INITX = 1 - - - Hi-Z / Hi-Z / Hi-Z / Hi-Z / SPL = 0 Hi-Z / SPL = 1 Hi-Z / Internal Internal Internal Internal Internal Internal input input input input fixed input fixed input fixed fixed at 0 fixed at 0 fixed at 0 at 0 / at 0 at 0 / /Analog /Analog /Analog Analog /Analog Analog input input input input input input enabled enabled enabled enabled enabled enabled Trace Trace selected output SPL = 0 SPL = 1 Hi-Z / Internal input fixed at 0 /Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled GPIO Resource other than Setting Setting Setting above disabled disabled disabled selected Maintain selected Maintain previous previous state state Hi-Z / Internal input fixed Internal input fixed Hi-Z / Internal GPIO input fixed selected at 0 at 0 at 0 GPIO selected Analog input Hi-Z selected O Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal input input input fixed at 0 fixed at 0 fixed at 0 /Analog /Analog /Analog input input input enabled enabled enabled Hi-Z / Internal input fixed at 0 /Analog input enabled Hi-Z / Hi-Z / Internal Internal input fixed input fixed at 0 at 0 /Analog /Analog input input enabled enabled Trace Trace selected output External Hi-Z / Internal input fixed at 0 /Analog input enabled Hi-Z / Internal input fixed at 0 /Analog input enabled Maintain interrupt enabled selected Setting Setting Setting Resource disabled disabled disabled previous GPIO state selected Maintain Maintain previous previous Internal state state input fixed other than Hi-Z / above Internal selected input fixed GPIO at 0 at 0 Hi-Z / Internal GPIO input fixed selected at 0 selected Document Number: 002-05646 Rev. *E Page 82 of 149 CY9A150RB Series Poweron reset INITX Pin status type or low- internal input voltage Function group Device detectio mode or reset state state Power Power supply stable input Hi-Z selected Sleep RTC mode, or or Deep standby Stop mode Stop mode state mode state supply INITX = 0 INITX = 1 - - - Hi-Z / Hi-Z / Internal Internal Internal input input input fixed at 0 fixed at 0 fixed at 0 / / / Analog Analog Analog input input input enabled enabled enabled mode Power supply stable Power supply stable supply INITX = 1 INITX = 1 INITX = 1 stable SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Hi-Z / Hi-Z / Hi-Z / Hi-Z / Hi-Z / Internal Internal Internal Internal Internal input fixed input fixed input fixed input fixed input fixed at 0 / at 0 / at 0 / at 0 / at 0 / Analog Analog Analog Analog Analog input input input input input enabled enabled enabled enabled enabled WKUP WKUP P standby state INITX = 1 Hi-Z / from Deep Power stable - Analog Deep standby Rtc mode Power unstable - Timer mode, state n state supply Return Run input enabled Maintain enabled previous External Hi-Z / WKUP input enabled state interrupt enabled Setting Setting Setting selected disabled disabled disabled Resource Maintain Maintain previous previous GPIO state state selected other than Hi-Z / above Internal selected input fixed GPIO at 0 Internal input fixed at 0 GPIO Hi-Z / selected Internal input fixed at 0 selected Document Number: 002-05646 Rev. *E Page 83 of 149 CY9A150RB Series Poweron reset Pin status type or lowvoltage detectio Function group INITX input state Device internal reset state n state Power supply Return Run mode or Timer mode, Deep standby Rtc mode Sleep RTC mode, or or Deep standby Stop mode Stop mode state mode state state unstable supply INITX = 0 INITX = 1 INITX = 1 - - - - CEC Setting Setting Setting enabled disabled disabled disabled INITX = 1 SPL = 0 SPL = 1 External Setting disabled disabled disabled enabled selected Hi-Z / Hi-Z / Input Input enabled enabled Setting Setting Setting disabled disabled disabled interrupt Setting Setting Setting enabled disabled disabled disabled Hi-Z GPIO SPL = 1 - Maintain Maintain Maintain Maintain Maintain previous previous previous previous previous state state state state state state Maintain enabled Hi-Z / WKUP input enabled previous state Maintain Maintain previous previous GPIO state state selected GPIO Hi-Z / selected Internal Internal other than INITX = 1 previous Resource selected SPL = 0 input interrupt above INITX = 1 WKUP Setting supply Maintain enabled Q Power supply stable stable WKUP Setting mode Power Power supply stable stable - standby state Power Power supply stable from Deep Hi-Z / Internal input fixed input fixed at 0 at 0 input fixed at 0 selected CEC enabled Maintain Maintain Maintain Maintain Maintain Maintain previous previous previous previous previous previous state state state state state state External R Maintain previous state selected Resource other than above selected Hi-Z Hi-Z / Hi-Z / Input Input enabled enabled GPIO GPIO Maintain Maintain selected previous previous Internal state state Hi-Z / Internal input fixed Hi-Z / Internal GPIO input fixed selected at 0 at 0 input fixed at 0 selected Document Number: 002-05646 Rev. *E Page 84 of 149 CY9A150RB Series Poweron reset Pin status type or lowvoltage detectio Function group INITX input state Device internal reset state n state Power supply Return Run mode or Timer mode, Deep standby Rtc mode Sleep RTC mode, or or Deep standby Stop mode Stop mode state mode state state unstable supply INITX = 0 INITX = 1 INITX = 1 - - - - INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 WKUP input enabled External Power supply stable Setting Setting disabled disabled disabled supply stable WKUP Setting mode Power Power supply stable stable - standby state Power Power supply stable from Deep Maintain enabled SPL = 1 INITX = 1 - Hi-Z / WKUP input enabled previous state interrupt enabled S selected Maintain Maintain previous previous GPIO state state selected GPIO selected Internal Resource Internal other than above selected Hi-Z / Hi-Z Hi-Z / Hi-Z / Input Input enabled enabled GPIO Hi-Z / Internal input fixed input fixed at 0 at 0 input fixed at 0 selected [1]. Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. [2]. Oscillation is stopped at Stop mode and Deep Standby Stop mode. Document Number: 002-05646 Rev. *E Page 85 of 149 CY9A150RB Series 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Rating Parameter Symbol Unit Min Max VCC VSS - 0.5 VSS + 4.6 V Analog power supply voltage[1], [3] AVCC VSS - 0.5 VSS + 4.6 V Analog reference voltage[1], [3] AVRH VSS - 0.5 VSS + 4.6 V VSS - 0.5 VCC + 0.5 (≤ 4.6 V) V VSS - 0.5 VSS + 6.5 V VIA VSS - 0.5 AVCC + 0.5 (≤ 4.6 V) V VO VSS - 0.5 VCC + 0.5 (≤ 4.6 V) V IOL - 10 mA IOLAV - 4 mA L level total maximum output current ∑IOL - 100 mA L level total average output current[6] ∑IOLAV - 50 mA IOH - - 10 mA H level average output current[5] IOHAV - -4 mA H level total maximum output current ∑IOH - - 100 mA H level total average output current[6] ∑IOHAV - - 50 mA Power consumption PD - 300 mW Storage temperature TSTG - 55 + 150 °C Power supply voltage[1], [2] Input voltage[1] Analog pin input voltage Remarks VI [1] Output voltage[1] L level maximum output current[4] L level average output current [5] H level maximum output current [4] 5 V tolerant [1]. These parameters are based on the condition that V SS = AVSS = 0.0 V. [2]. VCC must not drop below VSS - 0.5 V. [3]. Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on. [4]. The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. [5]. The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. [6]. The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: 002-05646 Rev. *E Page 86 of 149 CY9A150RB Series 12.2 Recommended Operating Conditions (VSS = AVSS = 0.0V) Value Parameter Symbol Conditions Unit Min Max Remarks VCC - 1.65[2] 3.6 V Analog power supply voltage AVCC - 1.65 3.6 V AVCC = VCC 2.7 AVCC V AVCC ≥ 2.7 V Analog reference voltage AVRH AVCC AVCC V AVCC < 2.7 V Power supply voltage Smoothing capacitor CS - 1 10 μF Operating temperature TA - - 40 + 85 °C For built-in Regulator[1] [1]. See C pin in Handling Devices for the connection of the smoothing capacitor. [2]. In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: 002-05646 Rev. *E Page 87 of 149 CY9A150RB Series 12.3 DC Characteristics 12.3.1 Current rating (VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Pin name Conditions Unit Remarks Typ[3] Max[4] 17.5 23.7 mA [1] [5] 8 11 mA [1] [5] CPU/ Peripheral: 4 MHz[2] 1.9 3.1 mA [1] CPU/ Peripheral: 32 kHz 120 810 μA [1] [6] CPU/ Peripheral: 100 kHz 140 830 μA [1] Peripheral: 40 MHz 11 15 mA [1] [5] Peripheral: 4 MHz[2] 0.82 1.7 mA [1] Peripheral: 32 kHz 105 800 μA [1] [6] Peripheral: 100 kHz 125 810 μA [1] CPU: 40 MHz, Peripheral: 40 MHz PLL CPU: 40 MHz, Run mode Peripheral: the clock stops , , NOP operation ICC High-speed CR Run mode Power supply VCC current Sub Run mode Low-speed CR Run mode PLL Sleep mode High-speed CR Sleep mode ICCS Sub Sleep mode Low-speed CR Sleep mode , , , [1]. When all ports are fixed. [2]. When setting it to 4 MHz by trimming. [3]. TA=+25°C, VCC=3.6 V [4]. TA=+85°C, VCC=3.6 V [5]. When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) [6]. When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) Document Number: 002-05646 Rev. *E Page 88 of 149 CY9A150RB Series Parameter Symbol Value Pin name Conditions TA = + 25°C, Main When LVD is off Timer mode TA = + 85°C, When LVD is off ICCT TA = + 25°C, Sub When LVD is off Timer mode TA = + 85°C, When LVD is off TA = + 25°C, ICCR RTC mode When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, ICCH Stop mode When LVD is off TA = + 85°C, When LVD is off Unit Remarks Typ[2] Max[2] 2.0 2.7 mA [1], [3] - 3.2 mA [1], [3] 15 45 μA [1], [4} - 440 μA [1], [4} 13 40 μA [1], [4] - 380 μA [1], [4] 11 38 μA [1] - 370 μA [1] 2.0 12 μA [1], [4],[5] 9.2 25 μA [1], [4],[5] 125 μA [1], [4],[5] 195 μA [1], [4],[5] 1.4 10 μA [1], [5] 8.6 23 μA [1], [5] 120 μA [1], [5] 190 μA [1], [5] TA = + 25°C, When LVD is off, When RAM is off Power supply TA = + 25°C, VCC current Deep ICCRD Standby RTC mode When LVD is off, When RAM is on TA = + 85°C, When LVD is off, When RAM is off TA = + 85°C, - When LVD is off, When RAM is on TA = + 25°C, When LVD is off, When RAM is off TA = + 25°C, Deep ICCHD Standby Stop mode When LVD is off, When RAM is on TA = + 85°C, When LVD is off, When RAM is off TA = + 85°C, When LVD is off, - When RAM is on [1]. When all ports are fixed. [2]. VCC=3.6 V [3]. When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) [4]. When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) [5]. RAM on/off setting is on-chip SRAM only. Document Number: 002-05646 Rev. *E Page 89 of 149 CY9A150RB Series 12.3.1.1 Low-Voltage Detection Current (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Value Conditions Unit At operation for reset Low-voltage detection circuit (LVD) power VCC = 3.6 V ICCLVD Remarks Typ Max 0.13 0.3 μA At not detect 0.13 0.3 μA At not detect VCC At operation for interrupt supply current VCC = 3.6 V 12.3.1.2 Flash Memory Current (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Flash memory write/erase current Symbol ICCFLASH Pin name VCC Value Conditions At Write/Erase Typ Max 9.5 11.2 Unit Remarks mA [1] Unit Remarks [1]. The current at which to write or erase Flash memory, I CCFLASH is added to ICC. 12.3.1.3 A/D Converter Current (VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to +85°C) Parameter Power supply current Symbol ICCAD Pin name Value Conditions Typ Max At 1unit operation 0.27 0.42 mA At stop 0.03 10 μA 0.72 1.29 mA 0.02 2.6 μA AVCC At 1unit operation Reference power supply current ICCAVRH AVRH AVRH=3.6 V At stop Document Number: 002-05646 Rev. *E Page 90 of 149 CY9A150RB Series 12.3.2 Pin Characteristics (VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Parameter Value Sym bol Pin name Conditions Unit Min CMOS VCC ≥ 2.7 V Voltage (hysteresis input pin, VIHS input) input pin CMOS VCC < 2.7 V VCC × 0.7 VCC ≥ 2.7 V VCC × 0.8 VCC < 2.7 V VCC × 0.7 (hysteresis input pin, VILS input) 5 V tolerant current V - V VCC × 0.3 VCC ≥ 2.7 V VCC × 0.2 VSS - 0.3 - VCC < 2.7 V V VCC × 0.3 VCC - 0.5 4mA type - VCC V VSS - 0.4 V -5 - +5 μA - - +1.8 μA 33 66 VCC < 2.7 V, IOH = - 2 VCC - mA 0.45 VCC ≥ 2.7 V, IOL = 4 mA VOL 4mA type VCC < 2.7 V, IOL = 2 mA - Input leak VSS + 5.5 VCC × 0.2 VSS - 0.3 mA L level output voltage - VCC < 2.7 V VCC ≥ 2.7 V, IOH = - 4 H level VOH V MD0, MD1 input pin output voltage VCC + 0.3 VCC ≥ 2.7 V hysteresis Voltage - Remarks MD0, MD1 5V tolerant L level input Max VCC × 0.8 hysteresis H level input Typ - CEC0_0, IIL CEC0_1, VCC = AVCC = AVRH = CEC1_0, VSS = AVSS = 0.0 V CEC1_1 Pull-up resistor value RPU VCC ≥ 2.7 V 21 VCC < 2.7 V - - 134 - - 5 15 Pull-up pin kΩ Other than Input capacitance VCC, VSS, CIN pF AVCC, AVSS, AVRH Document Number: 002-05646 Rev. *E Page 91 of 149 CY9A150RB Series 12.4 AC Characteristics 12.4.1 Main Clock Input Characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Value Conditions Unit Min Max VCC ≥ 2.7V 4 48 VCC < 2.7V 4 20 - 4 48 MHz Input frequency fCH Remarks When crystal oscillator is connected When using external MHz clock X0, Input clock cycle Input clock pulse width tCYLH X1 When using external - 20.83 250 ns clock PWH/tCYLH, - When using external 45 55 % PWL/tCYLH Input clock rising tCF, time and falling time tCR clock When using external - - 5 ns clock fCM - - - 40 MHz Master clock fCC - - - 40 MHz Base clock (HCLK/FCLK) fCP0 - - - 40 MHz APB0 bus clock[2] fCP1 - - - 40 MHz APB1 bus clock[2] fCP2 - - - 40 MHz APB2 bus clock[2] tCYCC - - 25 - ns Base clock (HCLK/FCLK) Internal operating tCYCP0 - - 25 - ns APB0 bus clock[2] clock[1] cycle time tCYCP1 - - 25 - ns APB1 bus clock[2] tCYCP2 - - 25 - ns APB2 bus clock[2] Internal operating clock[1] frequency [1]. For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual. [2]. For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet. X0 Document Number: 002-05646 Rev. *E Page 92 of 149 CY9A150RB Series 12.4.2 Sub Clock Input Characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Input frequency Symbol Pin name Value Conditions Unit Min Typ - - 32.768 - kHz - 32 - 100 kHz - 10 - 31.25 μs Input clock pulse 45 - 55 % width When crystal oscillator is connected[1] fCL X0A, Input clock cycle Remarks Max tCYLL X1A PWH/tCYLL, PWL/tCYLL When using external clock When using external clock When using external clock [1]. For more information about crystal oscillator, see Sub Crystal Oscillator in Handling Devices. X0A Document Number: 002-05646 Rev. *E Page 93 of 149 CY9A150RB Series 12.4.3 Built-in CR Oscillation Characteristics 12.4.3.1 Built-in High-speed CR (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Value Symbo l Conditions Unit Min TA = + 25°C,VCC ≥ 2.7V TA = - 20°C to + 85°C, VCC ≥ 2.7V TA = - 40°C to + 85°C, Clock frequency fCRH VCC ≥ 2.7V TA = - 40°C to + 85°C VCC < 2.7V TA = - 40°C to + 85°C stabilization time tCRWT Remarks Max 3.94 4 4.06 3.92 4 4.08 3.88 4 4.12 When trimming[1] MHz TA = + 25°C, VCC < 2.7V Frequency Typ - 3.9 4 4.1 3.66 4 4.20 2.8 4 5.2 - - 30 When not trimming μs [2] [1]. In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. [2]. This is the time to stabilize the frequency of High-speed CR clock after setting trimming value. This period is able to use High-speed CR clock as source clock. 12.4.3.2 Built-in Low-speed CR (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Symbol Conditions Unit Min Clock frequency fCRL Document Number: 002-05646 Rev. *E - 50 Typ 100 Remarks Max 150 kHz Page 94 of 149 CY9A150RB Series 12.4.4 Operating Conditions of Main PLL 12.4.4.1 Operating Conditions of Main PLL (In the case of using main clock for input of Main PLL) (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Symbol Unit Min Typ Max tLOCK 100 - - μs PLL input clock frequency fPLLI 4 - 16 MHz PLL multiplication rate - 5 - 37 multiplier fPLLO 75 - 150 MHz fCLKPLL - - 40 MHz PLL oscillation stabilization wait time[1] (LOCK UP time) PLL macro oscillation clock frequency [2] Main PLL clock frequency Remarks [1]. Time from when the PLL starts operating until the oscillation stabilizes. [2]. For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. 12.4.4.2 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for input clock of Main PLL) (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Symbol Unit Min Typ PLL oscillation stabilization wait time[1] tLOCK 100 - - μs PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiplication rate - 19 - 35 multiplier PLL macro oscillation clock frequency fPLLO 72 - 150 MHz Main PLL clock frequency[2] fCLKPLL - - 40 MHz (LOCK UP time) Remarks Max [1]. Time from when the PLL starts operating until the oscillation stabilizes. [2]. For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. Note: ◼ Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency has been trimmed. ◼ When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. Main PLL connection Main PLL Main clock (CLKMO) High-speed CR clock (CLKHC) K divider PLLinput PLL macro clock oscillation clock Main PLL clock M (CLKPLL) divider N divider Document Number: 002-05646 Rev. *E Page 95 of 149 CY9A150RB Series 12.4.5 Reset Input Characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Reset input time tINITX Value Pin name Conditions INITX - Unit Min Max 500 - Remarks ns 12.4.6 Power-on Reset Timing (Vss = 0V, TA = - 40°C to + 85°C) Parameter Symbol Power supply shut down time Power ramp rate Pin name VCC Unit Remarks Min Typ Max - 1 - - ms *1 Vcc:0.2V to 2.70V 0.9 - 1000 mV/us *2 tOFF dV/dt Value Conditions Time until releasing Power-on tPRT 0.446 0.744 ms reset *1: VCC must be held below 0.2V for minimum period of tOFF. Improper initialization may occur if this condition is not met. *2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1ms). Note: − If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 5. 2.7V VCC VDH 0.2V dV/dt 0.2V tPRT Internal RST CPU Operation RST Active 0.2V tOFF release start Glossary VDH: detection voltage of Low Voltage detection reset. See “12.6 Low-Voltage Detection Characteristics” Document Number: 002-05646 Rev. *E Page 96 of 149 CY9A150RB Series 12.4.7 External Bus Timing 12.4.7.1 External bus clock output characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Output frequency Symbol Pin name Conditions Unit Min Max VCC ≥ 2.7 V - 40 MHz VCC < 2.7 V - 20 MHz MCLKOUT[1] tCYCLE The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see Chapter 12: External Bus Interface in FM3 Family Peripheral Manual.. When external bus clock is not output, this characteristic does not give any effect on external bus operation. MCLKOUT 12.4.7.2 External bus signal input/output characteristics (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit 0.8 × VCC V 0.2 × VCC V VOH 0.8 × VCC V VOL 0.2 × VCC V VIH Remarks Signal input characteristics VIL Signal output characteristics Input signal VIH VIL VIH VIL Output signal VOH VOL VOH VOL Document Number: 002-05646 Rev. *E Page 97 of 149 CY9A150RB Series 12.4.7.3 Separate Bus Access Asynchronous SRAM Mode (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter MOEX Min pulse width MCSX ↓ → Address output delay time Symbol tOEW tCSL – AV MOEX ↑ → Address hold time tOEH - AX MCSX ↓ →MOEX ↓ delay time Pin name MOEX VCC ≥ 2.7 V VCC < 2.7 V Unit Min Max MCLK×n-3 - MCSX[7:0], VCC ≥ 2.7 V -9 +9 MAD[24:0] VCC < 2.7 V -12 +12 MOEX, VCC ≥ 2.7 V MAD[24:0] VCC < 2.7 V MCLK×m+9 0 time Data set up → MOEX ↑ time VCC ≥ 2.7 V MCLK×m-9 MCLK×m+9 VCC < 2.7 V MCLK×m-12 MCLK×m+12 ns MOEX, VCC ≥ 2.7 V tOEH - CSH tCSL - RDQML tDS - OE MOEX ↑ →Data hold time tDH - OE MWEX Min pulse width tWEW MWEX ↑ → Address output delay time MCSX ↓ → MWEX ↓ delay time MWEX ↑ → MCSX ↑ delay time MCSX ↓→ MDQM ↓ delay time MCSX ↓→ Data output time MWEX ↑ → Data hold time ns MCLK×m+12 MCLK×m+9 tWEH - AX ns 0 VCC < 2.7 V MCSX ↓ → MDQM ↓ delay MCLK×m+12 MCSX, VCC ≥ 2.7 V MCLK×m-9 MCLK×m+9 MDQM[1:0] VCC < 2.7 V MCLK×m-12 MCLK×m+12 MOEX, VCC ≥ 2.7 V 20 - MADATA[15:0] VCC < 2.7 V 38 - MOEX, VCC ≥ 2.7 V MADATA[15:0] VCC < 2.7 V 0 - ns MCLK×n-3 - ns MWEX ns ns VCC ≥ 2.7 V VCC < 2.7 V MWEX, VCC ≥ 2.7 V MAD[24:0] VCC < 2.7 V MCLK×m+9 ns 0 MCLK×m+12 VCC ≥ 2.7 V MCLK×n-9 MCLK×n+9 MWEX, VCC < 2.7 V MCLK×n-12 MCLK×n+12 MCSX[7:0] VCC ≥ 2.7 V tCSL - WEL ns tWEH - CSH MCLK×m+9 0 VCC < 2.7 V tCSL-WDQML tCSL-DV tWEH - DX ns ns tCSL - OEL MCSX[7:0] MOEX ↑ → MCSX ↑ time Conditions ns MCLK×m+12 MCSX, VCC ≥ 2.7 V MCLK×n-9 MCLK×n+9 MDQM[1:0] VCC < 2.7 V MCLK×n-12 MCLK×n+12 MCSX, VCC ≥ 2.7 V MCLK-9 MCLK+9 MADATA[15:0] VCC < 2.7 V MCLK-12 MCLK+12 MWEX, VCC ≥ 2.7 V MADATA[15:0] VCC < 2.7 V ns ns MCLK×m+9 0 ns MCLK×m+12 Note: When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16). Document Number: 002-05646 Rev. *E Page 98 of 149 CY9A150RB Series MCLK MCSX[7:0] MAD[24:0] MOEX MDQM[1:0] MWEX MADATA[15:0] Document Number: 002-05646 Rev. *E Page 99 of 149 CY9A150RB Series 12.4.7.4 Separate Bus Access Synchronous SRAM Mode (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Symbol Pin name Conditions Unit Min MCLK, Address delay time tAV VCC ≥ 2.7 V 9 1 MAD[24:0] VCC < 2.7 V 9 1 MCLK, VCC < 2.7 V MCSX[7:0] VCC ≥ 2.7 V MCSX delay time tCSH 9 1 9 1 MCLK, VCC < 2.7 V MOEX VCC ≥ 2.7 V MOEX delay time tREH 9 1 VCC ≥ 2.7 V 19 MADATA[15:0] VCC < 2.7 V 37 MCLK, VCC ≥ 2.7 V MADATA[15:0] VCC < 2.7 V 0 VCC ≥ 2.7 V MCLK, VCC < 2.7 V MWEX VCC ≥ 2.7 V tWEH - ns ns 12 9 1 ns 12 VCC ≥ 2.7 V tDQML 9 1 MCLK, VCC < 2.7 V MDQM[1:0] VCC ≥ 2.7 V MDQM[1:0] delay time tDQMH ns 12 9 1 VCC < 2.7 V MCLK, tOD ns 9 VCC < 2.7 V MCLK ↑ → Data hold time - 1 MWEX delay time tODS ns 12 MCLK, tWEL MCLK ↑ → Data output time ns 12 VCC < 2.7 V tDH ns 12 VCC ≥ 2.7 V tREL MCLK ↑ → Data hold time ns 12 VCC < 2.7 V tDS ns 12 VCC ≥ 2.7 V tCSL Data set up →MCLK ↑ time Max ns 12 VCC ≥ 2.7 V MCLK+18 MCLK+1 MADATA[15:0] VCC < 2.7 V MCLK, VCC ≥ 2.7 V ns MCLK+24 18 1 MADATA[15:0] VCC < 2.7 V ns 24 Note: − When the external load capacitance CL = 30 pF. Document Number: 002-05646 Rev. *E Page 100 of 149 CY9A150RB Series tCYCLE MCLK tCSL tCSH MCSX[7:0] tAV MAD[24:0] tAV Address Address tREL tREH tDQML tDQMH MOEX tDQML tDQMH tWEL tWEH MDQM[1:0] MWEX MADATA[15:0] tDS tDH RD tOD WD Invalid tODS Document Number: 002-05646 Rev. *E Page 101 of 149 CY9A150RB Series 12.4.7.5 Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Symbol Pin name Conditions Unit Min Multiplexed address delay time Multiplexed address hold time VCC ≥ 2.7 V Max +10 tALE-CHMADV 0 ns MALE, VCC < 2.7 V +20 MADATA[15:0] VCC ≥ 2.7 V MCLK×n+0 MCLK×n+10 VCC < 2.7 V MCLK×n+0 MCLK×n+20 tCHMADH ns Note: − When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16). MCLK MCSX[7:0] MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] Document Number: 002-05646 Rev. *E Page 102 of 149 CY9A150RB Series 12.4.7.6 Multiplexed Bus Access Synchronous SRAM Mode (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Symbol Pin name Conditions Unit Min VCC ≥ 2.7 V tCHAL 9 ns 12 ns 9 ns 12 ns 1 tOD ns 1 tOD ns 1 VCC < 2.7 V MALE delay time MCLK, ALE VCC ≥ 2.7 V tCHAH 1 VCC < 2.7 V MCLK ↑ → Multiplexed Address delay time Remarks Max VCC ≥ 2.7 V tCHMADV VCC < 2.7 V MCLK, MADATA[15:0] MCLK ↑ → Multiplexed Data output time VCC ≥ 2.7 V tCHMADX VCC < 2.7 V Note: − When the external load capacitance CL = 30 pF. MCLK MCSX[7:0] MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] Document Number: 002-05646 Rev. *E Page 103 of 149 CY9A150RB Series 12.4.7.7 NAND Flash Memory Mode (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Symbol Pin name Conditions Unit Min Max MCLK×n-3 - VCC ≥ 2.7 V MNREX Min pulse width tNREW MNREX ns VCC < 2.7 V Data setup → MNREX↑time MNREX↑→ Data hold time MNALE↑→MNWEX delay time MNALE↓→MNWEX delay time MNCLE↑→MNWEX delay time MNWEX↑→MNCLE delay time tDS – NRE tDH – NRE tALEH - NWEL tALEL - NWEL tCLEH - NWEL tNWEH - CLEL MNREX, VCC ≥ 2.7 V 20 - MADATA[15:0] VCC < 2.7 V 38 - MNREX, VCC ≥ 2.7 V 0 - MADATA[15:0] VCC < 2.7 V MNALE, VCC ≥ 2.7 V MCLK×m-9 MCLK×m+9 MNWEX VCC < 2.7 V MCLK×m-12 MCLK×m+12 MNALE, VCC ≥ 2.7 V MCLK×m-9 MCLK×m+9 MNWEX VCC < 2.7 V MCLK×m-12 MCLK×m+12 MNCLE, VCC ≥ 2.7 V MCLK×m-9 MCLK×m+9 MNWEX VCC < 2.7 V MCLK×m-12 MCLK×m+12 MNCLE, VCC ≥ 2.7 V ns ns ns ns ns MCLK×m+9 0 MNWEX VCC < 2.7 V ns MCLK×m+12 VCC ≥ 2.7 V MNWEX Min pulse width tNWEW MNWEX MCLK×n-3 - ns VCC < 2.7 V MNWEX↓→Data output time MNWEX↑→Data hold time tNWEL – DV tNWEH – DX MNWEX, VCC ≥ 2.7 V -9 +9 MADATA[15:0] VCC < 2.7 V -12 +12 MNWEX, VCC ≥ 2.7 V ns MCLK×m+9 0 MADATA[15:0] VCC < 2.7 V ns MCLK×m+12 Note: − When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16). Document Number: 002-05646 Rev. *E Page 104 of 149 CY9A150RB Series Figure 1. NAND Flash Memory Read MCLK MNREX MADATA[15:0] Read Figure 2. NAND Flash Memory Address Write MCLK MNALE MNCLE MNWEX MADATA[15:0] Document Number: 002-05646 Rev. *E Write Page 105 of 149 CY9A150RB Series Figure 3. NAND Flash Memory Command Write MCLK MNALE MNCLE MNWEX MADATA[15:0] Document Number: 002-05646 Rev. *E Write Page 106 of 149 CY9A150RB Series 12.4.7.8 External Ready Input Timing (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Symbol Pin name Conditions Unit Min MCLK ↑ MRDY input setup time tRDYI MCLK, VCC ≥ 2.7 V 19 MRDY VCC < 2.7 V 37 Remarks Max - ns When RDY is input ··· MCLK Over 2cycles Original MOEX MWEX tRDYI MRDY When RDY is released MCLK ··· ··· 2 cycles Extended MOEX MWEX MRDY Document Number: 002-05646 Rev. *E tRDYI 0.5×VCC Page 107 of 149 CY9A150RB Series 12.4.8 Base Timer Input Timing 12.4.8.1 Timer input timing (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Input pulse width Symbol Pin name Conditions Unit Min Max 2tCYCP - Remarks TIOAn/TIOBn tTIWH, - (when using as tTIWL ns ECK, TIN) tTIWH tTIWL ECK TIN VIHS VIHS VILS VILS 12.4.8.2 Trigger input timing (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Input pulse width Symbol tTRGH, tTRGL Pin name Conditions VIHS Max 2tCYCP - Remarks TIOAn/TIOBn - (when using ns as TGIN) tTRGH TGIN Unit Min tTRGL VIHS VILS VILS Note: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet. Document Number: 002-05646 Rev. *E Page 108 of 149 CY9A150RB Series 12.4.9 CSIO/UART Timing 12.4.9.1 CSIO (SPI = 0, SCINV = 0) (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Baud rate - - Serial clock cycle time tSCYC SCKx SCK ↓ → SOT delay time tSLOVI SIN → SCK ↑ setup time VCC < 2.7 V Conditions - VCC ≥ 2.7 V Unit Min Max Min Max - 8 - 8 Mbps 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns SCKx, SOTx SCKx, tIVSHI Master mode SINx SCKx, SCK ↑ → SIN hold time tSHIXI Serial clock L pulse width tSLSH SCKx 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE - 50 - 30 ns SIN → SCK ↑ setup time tIVSHE 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE 20 - 20 - ns SINx SCKx, SOTx SCKx, Slave mode SINx SCKx, SINx SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-05646 Rev. *E Page 109 of 149 CY9A150RB Series tSCYC VOH SCK VOL VOL tSLOVI VOH SOT VOL tIVSHI SIN tSHIXI VIH VIH VIL VIL Master mode tSLSH SCK tSHSL VIH VIH tF VIL VIL VIH tR tSLOVE SOT VOH VOL tIVSHE SIN VIH VIL tSHIXE VIH VIL Slave mode Document Number: 002-05646 Rev. *E Page 110 of 149 CY9A150RB Series 12.4.9.2 CSIO (SPI = 0, SCINV = 1) (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name VCC ≥ 2.7 V VCC < 2.7 V Conditions - Unit Min Max Min Max - 8 - 8 Mbps 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns Baud rate - - Serial clock cycle time tSCYC SCKx SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓ → SIN hold time tSLIXI Serial clock L pulse width tSLSH SCKx 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns SCKx, SOTx SCKx, Master mode SINx SCKx, SINx SCKx, SOTx SCKx, SIN → SCK ↓ setup time tIVSLE SCK ↓ → SIN hold time tSLIXE SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Slave mode SINx SCKx, SINx Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-05646 Rev. *E Page 111 of 149 CY9A150RB Series tSCYC VOH SCK VOH VOL tSHOVI VOH SOT VOL tIVSLI SIN tSLIXI VIH VIH VIL VIL Master mode tSHSL SCK tSLSH VIH VIH VIL tR tF VIL VIL tSHOVE SOT VOH VOL tIVSLE SIN VIH VIL tSLIXE VIH VIL Slave mode Document Number: 002-05646 Rev. *E Page 112 of 149 CY9A150RB Series 12.4.9.3 CSIO (SPI = 1, SCINV = 0) (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Baud rate - - Serial clock cycle time tSCYC SCKx SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI VCC < 2.7 V Conditions - VCC ≥ 2.7 V Unit Min Max Min Max - 8 - 8 Mbps 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 30 - 2tCYCP - 30 - ns SCKx, SOTx SCKx, SINx Master mode SCKx, SCK ↓→ SIN hold time tSLIXI SOT → SCK ↓ delay time tSOVLI Serial clock L pulse width tSLSH SCKx 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE - 50 - 30 ns SIN → SCK ↓ setup time tIVSLE 10 - 10 - ns SCK ↓→ SIN hold time tSLIXE 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns SINx SCKx, SOTx SCKx, SOTx SCKx, Slave mode SINx SCKx, SINx Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-05646 Rev. *E Page 113 of 149 CY9A150RB Series tSCYC VOH SCK VOL SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL Master mode tSLSH SCK VIH VIL tF * SOT VIL tSHSL tR VOH VOL tIVSLE SIN VIH VIH tSHOVE VOH VOL tSLIXE VIH VIL VIH VIL Slave mode *: Changes when writing to TDR register Document Number: 002-05646 Rev. *E Page 114 of 149 CY9A150RB Series 12.4.9.4 CSIO (SPI = 1, SCINV = 1) (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Baud rate - - Serial clock cycle time tSCYC SCKx SCK ↓ → SOT delay time tSLOVI SIN → SCK ↑ setup time tIVSHI VCC ≥ 2.7 V VCC < 2.7 V Conditions - Unit Min Max Min Max - 8 - 8 Mbps 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 30 - 2tCYCP - 30 - ns SCKx, SOTx SCKx, SINx Master mode SCKx, SCK ↑ → SIN hold time tSHIXI SOT → SCK ↑ delay time tSOVHI Serial clock L pulse width tSLSH SCKx 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE - 50 - 30 ns SIN → SCK ↑ setup time tIVSHE 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns SINx SCKx, SOTx SCKx, SOTx SCKx, Slave mode SINx SCKx, SINx Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF. Document Number: 002-05646 Rev. *E Page 115 of 149 CY9A150RB Series tSCYC VOH SCK VOH VOL tSOVHI tSLOVI VOH VOL SOT VOH VOL tSHIXI tIVSHI VIH VIL SIN VIH VIL Master mode tR tF tSHSL SCK tSLSH VIH VIH VIL VIL VIL tSLOVE VOH VOL SOT VOH VOL tIVSHE tSHIXE VIH VIL SIN VIH VIL Slave mode 12.4.9.5 UART external clock input (EXT = 1) (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Symbol Serial clock L pulse width tSLSH Serial clock H pulse width tSHSL Conditions Unit Min Max tCYCP + 10 - ns tCYCP + 10 - ns Remarks CL = 30 pF SCK falling time tF - 5 ns SCK rising time tR - 5 ns tF tR tSHSL SCK V IL Document Number: 002-05646 Rev. *E V IH tSLSH V IH V IL V IL V IH Page 116 of 149 CY9A150RB Series 12.4.10 External Input Timing (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Symbol Pin name Condition s Min Ma x Unit A/D converter trigger ADTG FRCKx Input pulse width Remarks input Free-run timer input - 2tCYCP[1] - ns clock tINH, ICxx Input capture tINL DTIxX Waveform generator [2] WKUPx 2tCYCP + 100[1] INTxx, NMIX - ns External interrupt, NMI [3] 500 - ns [4] 600 - ns Deep Standby wake up [1]. tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Multi-function Timer is connected to, see Block Diagram in this data sheet. [2]. When in Run mode, in Sleep mode. [3]. When in Stop mode, in Timer mode. [4]. When in Deep Standby RTC mode, in Deep Standby Stop mode. Document Number: 002-05646 Rev. *E Page 117 of 149 CY9A150RB Series 12.4.11 Quadrature Position/Revolution Counter timing (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Symbol Conditions AIN pin H width tAHL - AIN pin L width tALL - BIN pin H width tBHL - BIN pin L width tBLL - BIN rising time from AIN pin H tAUBU PC_Mode2 or PC_Mode3 tBUAD PC_Mode2 or PC_Mode3 tADBD PC_Mode2 or PC_Mode3 tBDAU PC_Mode2 or PC_Mode3 tBUAU PC_Mode2 or PC_Mode3 tAUBD PC_Mode2 or PC_Mode3 tBDAD PC_Mode2 or PC_Mode3 tADBU PC_Mode2 or PC_Mode3 ZIN pin H width tZHL QCR:CGSC=0 ZIN pin L width tZLL QCR:CGSC=0 tZABE QCR:CGSC=1 tABEZ QCR:CGSC=1 level AIN falling time from BIN pin H level BIN falling time from AIN pin L level AIN rising time from AIN rising time from BIN pin H level BIN falling time from AIN pin H level AIN falling time from BIN pin L level BIN rising time from AIN pin L level AIN/BIN rising and falling time from determined ZIN level Determined ZIN level from AIN/BIN rising and falling time Unit Min Max 2tCYCP[1] - ns [1]. tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see Block Diagram in this data sheet. Document Number: 002-05646 Rev. *E Page 118 of 149 CY9A150RB Series tALL tAHL AIN tAUBU tADBD tBUAD tBDAU BIN tBHL tBLL tBLL tBHL BIN tBUAU tBDAD tAUBD tADBU AIN tAHL Document Number: 002-05646 Rev. *E tALL Page 119 of 149 CY9A150RB Series ZIN ZIN AIN/BIN Document Number: 002-05646 Rev. *E Page 120 of 149 CY9A150RB Series 12.4.12 I2C Timing (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Standard-mode Parameter Symbol Fast-mode Conditions Unit Min Max Min Max 0 100 0 400 kHz tHDSTA 4.0 - 0.6 - μs SCL clock L width tLOW 4.7 - 1.3 - μs SCL clock H width tHIGH 4.0 - 0.6 - μs 4.7 - 0.6 - μs 0 3.45[2] 0 0.9[3] μs tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs 2 tCYCP[4] - 2 tCYCP[4] - ns SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ (Repeated) START condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ fSCL tSUSTA CL = 30 pF, tHDDAT R = (VP/IOL)[1] Remarks Data setup time SDA ↓ ↑ → SCL ↑ STOP condition setup time SCL ↑ → SDA ↑ Bus free time between STOP condition and START condition Noise filter tSP - [1]. R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. V P indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. [2]. The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. [3]. A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. [4]. tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see Block Diagram in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL Document Number: 002-05646 Rev. *E Page 121 of 149 CY9A150RB Series 12.4.13 ETM Timing (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Data hold TRACECLK frequency Symbol tETMH Pin name Unit Min Max TRACECLK, VCC ≥ 2.7V 2 11 TRACED[3:0] VCC < 2.7V 2 15 VCC ≥ 2.7V - 40 MHz VCC < 2.7V - 20 MHz VCC ≥ 2.7V 25 - ns VCC < 2.7V 50 - ns Remarks ns 1/ tTRACE TRACECLK TRACECLK clock cycle Conditions tTRACE Note: − When the external load capacitance CL = 30 pF. HCLK TRACECLK TRACED[3:0] Document Number: 002-05646 Rev. *E Page 122 of 149 CY9A150RB Series 12.4.14 JTAG Timing (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter TMS, TDI setup time TMS, TDI hold time TDO delay time Symbol tJTAGS tJTAGH tJTAGD Pin name Conditions Unit Min Max 15 - ns 15 - ns TCK, VCC ≥ 2.7V TMS, TDI VCC < 2.7V TCK, VCC ≥ 2.7V TMS, TDI VCC < 2.7V TCK, VCC ≥ 2.7V - 25 TDO VCC < 2.7V - 45 Remarks ns Note: − When the external load capacitance CL = 30 pF. TCK TMS/TDI TDO Document Number: 002-05646 Rev. *E Page 123 of 149 CY9A150RB Series 12.5 12-bit A/D Converter 12.5.1 Electrical Characteristics for the A/D Converter (VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Value Symbol Pin name Min Resolution - - - - 12 bit Integral Nonlinearity - - - ± 2.4 ± 4.5 LSB Differential Nonlinearity - - - ± 2.3 ± 2.5 LSB Zero transition voltage VZT ANxx - ±7 ± 15 mV VFST ANxx - AVRH ± 7 AVRH ± 15 mV 2.0 - - - - 4.0 - - 10 - - 0.6 - 1.2 - 3.0 - Parameter Full-scale transition voltage Conversion time[1] Sampling time[2] tS - Typ Max Unit AVCC ≥ 2.7 V μs tCCK - 200 AVCC ≥ 2.7 V 10 us operation permission Analog input capacity AVCC ≥ 2.7 V - 1000 ns tSTT - - - 1.0 μs CAIN - - - 9.4 pF RAIN - - AVCC ≥ 2.7 V - 5.5 kΩ 10.5 Interchannel disparity - - - 4 LSB - ANxx - - 5 μA Analog input voltage - ANxx AVSS - AVRH V Reference voltage - AVRH - AVCC V current 2.7 AVCC 1.8 V< AVCC < 2.7 V 1.65 V< AVCC < 1.8 V - Analog port input leak 1.8 V< AVCC < 2.7 V 1.65 V< AVCC < 1.8 V 2.2 Analog input resistor 1.8 V< AVCC < 2.7 V 1.65 V< AVCC < 1.8 V 500 State transition time to 1.8 V< AVCC < 2.7 V 1.65 V< AVCC < 1.8 V 100 Compare clock cycle[3] Remarks AVCC ≥ 2.7 V AVCC < 2.7 V [1]. The conversion time is the value of sampling time (tS) + compare time (tC). The condition of the minimum conversion time is the following. AVCC ≥ 2.7 V, HCLK=40 MHz sampling time: 0.6 μs, compare time: 1.4 μs 1.8 V < AVCC < 2.7 V, HCLK=40 MHz sampling time: 1.2 μs, compare time: 2.8 μs 1.65 V < AVCC < 1.8 V, HCLK=40 MHz sampling time: 3 μs, compare time: 7 μs Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK). For setting of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual. Analog Macro Part. The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing. For the number of the APB bus to which the A/D Converter is connected, see Block Diagram. The base clock (HCLK) is used to generate the sampling time and the compare clock cycle. [2]. A necessary sampling time changes by external impedance. Ensure that it sets the sampling time to satisfy (Equation 1). [3]. The compare time (tC) is the value of (Equation 2). Document Number: 002-05646 Rev. *E Page 124 of 149 CY9A150RB Series Analog signal source REXT ANxx Analog input pin Comparator RAIN CAIN (Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9 tS: Sampling time[ns] RAIN: input resistor of A/D[kΩ] = 2.2 kΩ at 2.7 V < AVCC < 3.6 V input resistor of A/D[kΩ] = 5.5 kΩ at 1.8 V < AVCC < 2.7 V input resistor of A/D[kΩ] = 10.5 kΩ at 1.65 V < AVCC < 1.8 V CAIN: input capacity of A/D[pF] = 9.4 pF at 1.65 V < AVCC < 3.6 V REXT: Output impedance of external circuit[kΩ] (Equation 2) tC = tCCK × 14 tC: Compare time tCCK: Compare clock cycle Document Number: 002-05646 Rev. *E Page 125 of 149 CY9A150RB Series 12.5.2 Definition of 12-bit A/D Converter Terms ◼ Resolution: Analog variation that is recognized by an A/D converter. ◼ Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics. ◼ Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity 0xFFF Actual conversion characteristics 0xFFE 0x(N+1) {1 LSB(N-1) + VZT} VFST VNT 0x004 (Actually-measured value) 0x003 0x002 0x001 (Actuallymeasured value) Digital output Digital output 0xFFD Differential Nonlinearity Actual conversion characteristics Ideal characteristics 0xN Actual conversion characteristics Ideal characteristics VNT Actual conversion characteristics AVRH AVSS AVRH Analog input Integral Nonlinearity of digital output N = Differential Nonlinearity of digital output N = 1LSB = (Actually-measured value) (Actually-measured value) 0x(N-2) VZT (Actually-measured value) AVSS V(N+1)T 0x(N-1) Analog input VNT - {1LSB × (N - 1) + VZT} 1LSB V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN. Document Number: 002-05646 Rev. *E Page 126 of 149 CY9A150RB Series 12.6 Low-Voltage Detection Characteristics 12.6.1 Low-Voltage Detection Reset (TA = - 40°C to + 85°C) Value Parameter Symbol Conditions Min Detected voltage VDL Typ Unit Remarks Max 1.38 1.50 1.60 V When voltage drops 1.43 1.55 1.65 V When voltage rises 1.43 1.55 1.65 V When voltage drops Same as SVHR = 00000 value V When voltage rises 1.47 V When voltage drops Same as SVHR = 00000 value V When voltage rises 1.52 V When voltage drops Same as SVHR = 00000 value V When voltage rises 1.56 V When voltage drops Same as SVHR = 00000 value V When voltage rises 1.61 V When voltage drops Same as SVHR = 00000 value V When voltage rises 1.66 V When voltage drops Same as SVHR = 00000 value V When voltage rises 1.70 V When voltage drops Same as SVHR = 00000 value V When voltage rises 1.75 V When voltage drops Same as SVHR = 00000 value V When voltage rises 1.79 V When voltage drops Same as SVHR = 00000 value V When voltage rises 1.84 V When voltage drops Same as SVHR = 00000 value V When voltage rises 1.89 V When voltage drops Same as SVHR = 00000 value V When voltage rises 2.30 V When voltage drops Same as SVHR = 00000 value V When voltage rises 2.39 V When voltage drops Same as SVHR = 00000 value V When voltage rises 2.48 V When voltage drops Same as SVHR = 00000 value V When voltage rises 2.58 V When voltage drops V When voltage rises SVHR[1] = 00000 Released voltage VDH Detected voltage VDL SVHR[1] = 00001 Released voltage VDH Detected voltage VDL 1.60 1.73 SVHR[1] = 00010 Released voltage VDH Detected voltage VDL 1.65 1.78 SVHR[1] = 00011 Released voltage VDH Detected voltage VDL 1.70 1.84 SVHR[1] = 00100 Released voltage VDH Detected voltage VDL 1.75 1.89 SVHR[1] = 00101 Released voltage VDH Detected voltage VDL 1.80 1.94 SVHR[1] = 00110 Released voltage VDH Detected voltage VDL 1.85 2.00 SVHR[1] = 00111 Released voltage VDH Detected voltage VDL 1.90 2.05 SVHR[1] = 01000 Released voltage VDH Detected voltage VDL 1.95 2.11 SVHR[1] = 01001 Released voltage VDH Detected voltage VDL 2.00 2.16 SVHR[1] = 01010 Released voltage VDH Detected voltage VDL 2.05 2.21 SVHR[1] = 01011 Released voltage VDH Detected voltage VDL 2.50 2.70 SVHR[1] = 01100 Released voltage VDH Detected voltage VDL 2.60 2.81 SVHR[1] = 01101 Released voltage VDH Detected voltage VDL 2.70 2.92 SVHR[1] = 01110 Released voltage VDH Detected voltage VDL 2.80 3.02 SVHR[1] = 01111 Released voltage VDH Document Number: 002-05646 Rev. *E Same as SVHR = 00000 value Page 127 of 149 CY9A150RB Series Value Parameter Symbol Conditions Unit Remarks V When voltage drops Same as SVHR = 00000 value V When voltage rises 2.76 V When voltage drops Same as SVHR = 00000 value V When voltage rises 2.85 V When voltage drops Same as SVHR = 00000 value V When voltage rises 2.94 V When voltage drops V When voltage rises Min Detected voltage VDL 2.67 Typ 2.90 Max 3.13 SVHR[1] = 10000 Released voltage VDH Detected voltage VDL 3.00 3.24 SVHR[1] = 10001 Released voltage VDH Detected voltage VDL 3.10 3.35 SVHR[1] = 10010 Released voltage VDH Detected voltage VDL 3.20 3.46 SVHR[1] = 10011 Released voltage LVD stabilization wait time LVD detection delay time VDH Same as SVHR = 00000 value tLVDW - - - tLVDDL - - - 5200 × tCYCP[2] 200 μs μs [1]. The SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is initialized to 00000 by Low-Voltage Detection Reset. [2]. tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-05646 Rev. *E Page 128 of 149 CY9A150RB Series 12.6.2 Interrupt of Low-Voltage Detection (TA = - 40°C to + 85°C) Parameter Symbol Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH Detected voltage VDL Released voltage VDH LVD stabilization wait time LVD detection delay time Conditions SVHI = 00100 SVHI = 00101 SVHI = 00110 SVHI = 00111 SVHI = 01000 SVHI = 01001 SVHI = 01010 SVHI = 01011 SVHI = 01100 SVHI = 01101 SVHI = 01110 SVHI = 01111 SVHI = 10000 SVHI = 10001 SVHI = 10010 SVHI = 10011 Value Unit Remarks 1.84 V When voltage drops 1.89 V When voltage rises 1.75 1.89 V When voltage drops 1.80 1.94 V When voltage rises 1.66 1.80 1.94 V When voltage drops 1.70 1.85 2.00 V When voltage rises 1.70 1.85 2.00 V When voltage drops 1.75 1.90 2.05 V When voltage rises 1.75 1.90 2.05 V When voltage drops 1.79 1.95 2.11 V When voltage rises 1.79 1.95 2.11 V When voltage drops 1.84 2.00 2.16 V When voltage rises 1.84 2.00 2.16 V When voltage drops 1.89 2.05 2.21 V When voltage rises 1.89 2.05 2.21 V When voltage drops 1.93 2.10 2.27 V When voltage rises 2.30 2.50 2.70 V When voltage drops 2.39 2.60 2.81 V When voltage rises 2.39 2.60 2.81 V When voltage drops 2.48 2.70 2.92 V When voltage rises 2.48 2.70 2.92 V When voltage drops 2.58 2.80 3.02 V When voltage rises 2.58 2.80 3.02 V When voltage drops 2.67 2.90 3.13 V When voltage rises 2.67 2.90 3.13 V When voltage drops 2.76 3.00 3.24 V When voltage rises 2.76 3.00 3.24 V When voltage drops 2.85 3.10 3.35 V When voltage rises 2.85 3.10 3.35 V When voltage drops 2.94 3.20 3.46 V When voltage rises 2.94 3.20 3.46 V When voltage drops 3.04 3.30 3.56 V When voltage rises Min Typ Max 1.56 1.70 1.61 1.75 1.61 1.66 tLVDW - - - 5200 × tCYCP[1] μs tLVDDL - - - 200 μs [1]. tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-05646 Rev. *E Page 129 of 149 CY9A150RB Series 12.7 Flash Memory Write/Erase Characteristics 12.7.1 Write / Erase time (VCC = 1.65V to 3.6V, TA = - 40°C to + 85°C) Value Parameter Typ[1] Max[1] Sector erase Large Sector 1.1 2.7 time Small Sector 0.3 0.9 30 11.2 Unit Remarks s Includes write time prior to internal erase 528 μs Not including system-level overhead time 30.5 s Includes write time prior to internal erase Half word (16-bit) write time Chip erase time [1].The typical value is immediately after shipment, the maximum value is guarantee value under 100,000 cycle of erase/write. 12.7.2 Write cycles and data hold time Erase/write cycles (cycle) Data hold time (year) 1,000 20[1] 10,000 10* Remarks [1]. At average + 85°C Document Number: 002-05646 Rev. *E Page 130 of 149 CY9A150RB Series 12.8 Return Time from Low-Power Consumption Mode 12.8.1 Return Factor: Interrupt/WKUP The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. 12.8.1.1 Return Count Time (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Symbol Max[1] Typ Sleep mode Unit Remarks μs tCYCC High-speed CR Timer mode, 40 80 μs 350 700 μs 690 880 μs RTC mode, Stop mode 278 523 μs Deep Standby RTC mode 318 603 μs When RAM is off Deep Standby Stop mode 278 523 μs When RAM is on Main Timer mode, PLL Timer mode Low-speed CR Timer mode Sub Timer mode tICNT [1]. The maximum value depends on the accuracy of built-in CR. 12.8.1.2 Operation example of return from Low-Power consumption mode (by external interrupt[1]) External interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start [1]. External interrupt is set to detecting fall edge. Document Number: 002-05646 Rev. *E Page 131 of 149 CY9A150RB Series Operation example of return from Low-Power consumption mode (by internal resource interrupt [1]) 12.8.1.3 Internal resource interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start [1]. Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. − When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. Document Number: 002-05646 Rev. *E Page 132 of 149 CY9A150RB Series 12.8.2 Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. 12.8.2.1 Return Count Time (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Value Parameter Symbol Unit Remarks Typ Max[1] 148 263 μs 148 263 μs 258 483 μs 322 516 μs RTC/Stop mode 278 523 μs Deep Standby RTC mode 318 603 μs When RAM is off Deep Standby Stop mode 278 523 μs When RAM is on Sleep mode High-speed CR Timer mode, Main Timer mode, PLL Timer mode Low-speed CR Timer mode Sub Timer mode tRCNT [1]. The maximum value depends on the accuracy of built-in CR. 12.8.2.2 Operation example of return from Low-Power consumption mode (by INITX) INITX Internal reset Reset active Release tRCNT CPU Operation Document Number: 002-05646 Rev. *E Start Page 133 of 149 CY9A150RB Series 12.8.2.3 Operation example of return from low power consumption mode (by internal resource reset[1]) Internal resource reset Internal reset Reset active Release tRCNT CPU Operation Start [1]. Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual − When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual − The time during the power-on reset/low-voltage detection reset is excluded. See 12.4.6 Power-on Reset Timing in 12.4 AC Characteristics in Electrical Characteristics for the detail on the time during the power-on reset/low-voltage detection reset. − When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time. − The internal resource reset means the watchdog reset and the CSV reset. Document Number: 002-05646 Rev. *E Page 134 of 149 CY9A150RB Series 13. Ordering Information Part number CY9AF154MBPMC-G-JNE2 CY9AF155MBPMC-G-JNE2 CY9AF156MBPMC-G-JNE2 CY9AF154MBBGL-GK9E1 CY9AF155MBBGL-GK9E1 CY9AF156MBBGL-GK9E1 CY9AF154NBPMC-G-JNE2 CY9AF155NBPMC-G-JNE2 CY9AF156NBPMC-G-JNE2 CY9AF154NBBGL-GK9E1 CY9AF155NBBGL-GK9E1 CY9AF156NBBGL-GK9E1 CY9AF154RBPMC-G-JNE2 CY9AF155RBPMC-G-JNE2 CY9AF156RBPMC-G-JNE2 Document Number: 002-05646 Rev. *E On-chip Flash memory Main: 256 Kbyte Work: 32 Kbyte Main: 384 Kbyte Work: 32 Kbyte Main: 512 Kbyte Work: 32 Kbyte Main: 256 Kbyte Work: 32 Kbyte Main: 384 Kbyte Work: 32 Kbyte Main: 512 Kbyte Work: 32 Kbyte Main: 256 Kbyte Work: 32 Kbyte Main: 384 Kbyte Work: 32 Kbyte Main: 512 Kbyte Work: 32 Kbyte Main: 256 Kbyte Work: 32 Kbyte Main: 384 Kbyte Work: 32 Kbyte Main: 512 Kbyte Work: 32 Kbyte Main: 256 Kbyte Work: 32 Kbyte Main: 384 Kbyte Work: 32 Kbyte Main: 512 Kbyte Work: 32 Kbyte On-chip Package SRAM Packing 32 Kbyte Plastic  LQFP 80-pin 48 Kbyte (0.5 mm pitch), (LQH080) 64 Kbyte 32 Kbyte Plastic  PFBGA 96-pin 48 Kbyte (0.5 mm pitch), (FDG096) 64 Kbyte 32 Kbyte Plastic  LQFP 100-pin 48 Kbyte Tray (0.5 mm pitch), (LQI100) 64 Kbyte 32 Kbyte Plastic  PFBGA 112-pin 48 Kbyte (0.8 mm pitch), (LBC112) 64 Kbyte 32 Kbyte Plastic  LQFP 120-pin 48 Kbyte (0.5 mm pitch), (LQM120) 64 Kbyte Page 135 of 149 CY9A150RB Series 14. Package Dimensions Package Type Package Code LQFP 120 LQM120 4 D 5 7 D1 90 61 91 61 60 90 91 60 E1 E 4 5 7 3 6 31 120 1 31 30 e b 0.20 C A-B D 30 2 5 7 0.10 3 0.08 1 C A-B D C A-B D BOTTOM VIEW 8 TOP VIEW 2 A 9 c θ A A' 0.08 C SEATI N G PLA N E 0.25 A1 10 b SECTION A -A' L SIDE VIEW SYM BOL DIM ENSIONS M IN. NOM . M AX. 0.05 0.15 A A1 1. 70 b 0.17 c 0.115 0.22 D 18.00 BSC D1 16.00 BSC e 0.50 BSC E 18.00 BSC E1 L θ 0.27 0.195 16.00 BSC 0.45 0° 0.60 0.75 8° 002-16172 ** PACKAGE OUTLINE, 120 LEAD LQFP 18.0X18.0X1.7 M M LQM 120 REV** Document Number: 002-05646 Rev. *E Page 136 of 149 CY9A150RB Series Package Type Package Code LQFP 100 LQI100 D D1 75 4 D 5 7 51 D1 51 50 76 4 5 7 75 50 76 E1 E 5 4 7 E1 E 5 4 7 3 6 26 100 1 26 25 1 25 2 5 7 e 100 BOTTOM VIEW 0.1 0 C A-B D 3 0.2 0 C A-B D b TOP VIEW 8 0.0 8 C A-B D 2 A 9 A SEATIN G PLA N E A' 0.25 L1 0.0 8 C c A1 b 10 SECTIO N A-A ' L SIDE VIEW SYM BOL DETAIL A DIM ENSIONS M IN. NOM . M AX. 1.70 A A1 0.05 b 0.15 0.15 0.27 c 0.09 0.20 D 16.00 BSC D1 14.00 BSC e 0.50 BSC E 16.00 BSC E1 14.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 NOTES : 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. 2. DATUM PLANE H IS LOCATED AT THE BOTTOM OF THE M OLD PARTING LINE COINCIDENT W ITH W HERE THE LEAD EXITS THE BODY. 3. DATUM S A-B AND D TO BE DETERM INED AT DATUM PLANE H. 4. TO BE DETERM INED AT SEATING PLANE C. 5. DIM ENSIONS D1 AND E1 DO NOT INCLUDE M OLD PROTRUSION. ALLOW ABLEPROTRUSION IS 0.25m m PRE SIDE. DIM ENSIONS D1 AND E1 INCLUDE M OLD M ISM ATCH AND ARE DETERM INED AT DATUM PLANE H. 6. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT M UST BE LOCATED W ITHIN THE ZONE INDICATED. 7. REGARDLESS OF THE RELATIVE SIZE OF THE UPPER AND LOW ER BODY SECTIONS. DIM ENSIONS D1 AND E1 ARE DETERM INED AT THE LARGEST FEATURE OF THE BODY EXCLUSIVE OF M OLD FLASH AND GATE BURRS. BUT INCLUDING ANY M ISM ATCH BETW EEN THE UPPER AND LOW ER SECTIONS OF THE M OLDER BODY. 8. DIM ENSION b DOES NOT INCLUDE DAM BAR PROTRUSION. THE DAM BAR PROTRUSION (S) SHALL NOT CAUSE THE LEAD W IDTH TO EXCEED b M AXIM UM BY M ORE THAN 0.08m m . DAM BAR CANNOT BE LOCATED ON THE LOW ER RADIUS OR THE LEAD FOOT. 9. THESE DIM ENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETW EEN 0.10m m AND 0.25m m FROM THE LEAD TIP. 10. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOW EST POINT OF THE PACKAGE BODY. 002-11500 *A PACKAGE OUTLINE, 100 LEAD LQFP 14.0X14.0X1.7 M M LQI100 REV*A Document Number: 002-05646 Rev. *E Page 137 of 149 CY9A150RB Series Package Type Package Code LQFP 80 LQH080 4 D D1 60 5 7 41 41 40 61 60 40 61 21 80 5 7 E1 E 4 3 6 80 21 1 20 D e 20 2 5 7 0.10 C A-B D 3 b 0.08 C A-B 1 BOTTOM VIEW D 0.20 C A-B D 8 TOP VIEW 2 A A A' 0.08 C SIDE VIEW SYMBOL SEATIN G PLAN E 9 L1 L 0.25 A1 10 c b SECTION A-A' DIM ENSIONS M IN. NOM . M AX. A A1 1. 70 0.05 0.15 b 0.15 0.27 c 0.09 0.20 D 14.00 BSC. D1 12.00 BSC. e 0.50 BSC E 14.00 BSC. E1 12.00 BSC. L 0.45 0.60 0.75 L1 0.30 0.50 0.70 002-11501 ** PACKAGE OUTLINE, 80 LEAD LQFP 12.0X12.0X1.7 M M LQH080 Rev ** Document Number: 002-05646 Rev. *E Page 138 of 149 CY9A150RB Series Package Type Package Code BGA 112 LBC112 A 0.20 C 11 2X 10 9 6 8 7 6 5 4 3 2 1 L PIN A1 CORNER IN D EX M A RK K J H G F E D 7 C B A 6 B 0.20 C 2X TOP VIEW BOTTOM VIEW DETAIL A 5 11 2x φb C 0.10 C D ETAIL A 0.08 C A B SID E VIEW NOTES: 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. DIM ENSIONS SYM BOL 2. SOLDER BALL POSITION DESIGNATIO N PER JEP95, SECTION 3, SPP-020. M IN. NOM . M AX. A - - 1.45 3. "e"REPRESENTSTHE SOLDER BALL GRID PITCH. A1 0.25 0.35 0.45 4. SYM BOL "M D"IS THE BALL M ATRIX SIZE IN THE "D"DIRECTION. D 10.00 BSC SYM BOL "M E"IS THE BALL M ATRIX SIZE IN THE "E"DIRECTION. E 10.00 BSC N IS THE NUM BER OF POPULATED SOLDER BALL POSITIONS FOR M ATRIX D1 8.00 BSC E1 8.00 BSC MD 11 ME 11 N 112 b 0.35 0.45 eD 0.80 BSC eE 0.80 BSC SD 0.00 SE 0.00 SIZE M D X M E. 5. DIM ENSION "b"IS M EASURED AT THE MAXIM UM BALL DIAM ETER IN A PLANE PARALLEL TO DATUM C. 6. "SD"AND "SE"ARE M EASURED W ITH RESPECT TO DATUM S A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW . 0.55 W HEN THERE IS AN ODD NUM BEROF SOLDER BALLS IN THE OUTER ROW , "SD"OR "SE"= 0. W HEN THERE IS AN EVEN NUM BEROF SOLDER BALLS IN THE OUTER ROW , "SD" = eD/2 AND "SE"= eE/2. 7. A1 CORNER TO BE IDENTIFIED BY CHAM FER, LASER OR INK M ARK M ETALIZED M ARK, INDENTATION OR OTHER M EANS. 8. "+ " INDICATESTHE THEORETICAL CENTER OF DEPOPULATED SOLDER BALLS. 002-13225 ** PACKAGE OUTLINE, 112 BALL FBGA 10.00X10.00X1.45 M M LBC112 REV** Document Number: 002-05646 Rev. *E Page 139 of 149 CY9A150RB Series Package Type Package Code BGA 96 FDG096 A 0.20 C 11 2X 10 9 6 8 7 6 5 4 3 2 1 L PIN A1 CORNER INDEX M ARK K J H G F E D 7 0.20 C TOP VIEW C B A 6 B 2X BOTTOM VIEW DETAIL A 0.20 C C 0.08 C 96xφb DETAIL A 5 0.05 SIDE VIEW C A B NOTES: 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. DIM ENSIONS SYM BOL M IN. NOM . M AX. 2. SOLDER BALL POSITION DESIGNATIO N PER JEP95, SECTION 3, SPP-020. A - - 1.30 3. "e"REPRESENTSTHE SOLDER BALL GRID PITCH. A1 0.15 0.25 0.35 4. SYM BOL "M D"IS THE BALL M ATRIX SIZE IN THE "D"DIRECTION. D 6.00 BSC SYM BOL "M E"IS THE BALL M ATRIX SIZE IN THE "E"DIRECTION. E 6.00 BSC N IS THE NUM BER OF POPULATED SOLDER BALL POSITIONS FOR M ATRIX D1 5.00 BSC E1 5.00 BSC MD 11 ME 11 N 96 b 0.20 0.30 eD 0.50 BSC eE 0.50 BSC SD 0.00 SE 0.00 SIZE M D X M E. 5. DIM ENSION "b"IS MEASURED AT THE M AXIM UM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 6. "SD"AND "SE"ARE M EASURED W ITH RESPECT TO DATUM S A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW . 0.40 W HEN THERE IS AN ODD NUM BEROF SOLDER BALLS IN THE OUTER ROW , "SD"OR "SE"= 0. W HEN THERE IS AN EVEN NUM BEROF SOLDER BALLS IN THE OUTER ROW , "SD" = eD/2 AND "SE"= eE/2. 7. A1 CORNER TO BE IDENTIFIED BY CHAM FER, LASER OR INK M ARK M ETALIZED M ARK, INDENTATION OR OTHER M EANS. 8. "+ " INDICATESTHE THEORETICAL CENTER OF DEPOPULATED SOLDER BALLS. 002-13224 ** PACKAGE OUTLINE, 96 BALL FBGA 6.0X6.0X1.3 M M FDG096 REV** Document Number: 002-05646 Rev. *E Page 140 of 149 CY9A150RB Series 15. Errata This chapter describes the errata for CY9B150R series. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. 15.1 Part Numbers Affected Part Number Initial Revision CY9AF154RPMC-G-JNE2, CY9AF155RPMC-G-JNE2, CY9AF156RPMC-G-JNE2, CY9AF154NPMC-G-JNE2, CY9AF155NPMC-G-JNE2, CY9AF156NPMC-G-JNE2, CY9AF154NBGL-GE1, CY9AF155NBGL-GE1, CY9AF156NBGL-GE1, CY9AF154NBGL-GK9E1, CY9AF155NBGL-GK9E1, CY9AF156NBGL-GK9E1, CY9AF154MPMC-G-JNE2, CY9AF155MPMC-G-JNE2, CY9AF156MPMC-G-JNE2, CY9AF154MBGL-GE1, CY9AF155MBGL-GE1, CY9AF156MBGL-GE1, CY9AF154MBGL-GK9E1, CY9AF155MBGL-GK9E1, CY9AF156MBGL-GK9E1, MB9AF154RPMC-G-JNE2, MB9AF155RPMC-G-JNE2, MB9AF156RPMC-G-JNE2, MB9AF154NPMC-G-JNE2, MB9AF155NPMC-G-JNE2, MB9AF156NPMC-G-JNE2, MB9AF154NBGL-GE1, MB9AF155NBGL-GE1, MB9AF156NBGL-GE1, MB9AF154MPMC-G-JNE2, MB9AF155MPMC-G-JNE2, MB9AF156MPMC-G-JNE2, MB9AF154MBGL-GE1, MB9AF155MBGL-GE1, MB9AF156MBGL-GE1 Rev. A CY9AF154RAPMC-G-JNE2, CY9AF155RAPMC-G-JNE2, CY9AF156RAPMC-G-JNE2, CY9AF154NAPMC-G-JNE2, CY9AF155NAPMC-G-JNE2, CY9AF156NAPMC-G-JNE2, CY9AF154NABGL-GE1, CY9AF155NABGL-GE1, CY9AF156NABGL-GE1, CY9AF154NABGL-GK9E1, CY9AF155NABGL-GK9E1, CY9AF156NABGL-GK9E1, CY9AF154MAPMC-G-JNE2, CY9AF155MAPMC-G-JNE2, CY9AF156MAPMC-G-JNE2, CY9AF154MABGL-GE1, CY9AF155MABGL-GE1, CY9AF156MABGL-GE1, CY9AF154MABGL-GK9E1, CY9AF155MABGL-GK9E1, CY9AF156MABGL-GK9E1, MB9AF154RAPMC-G-JNE2, MB9AF155RAPMC-G-JNE2, MB9AF156RAPMC-G-JNE2, MB9AF154NAPMC-G-JNE2, MB9AF155NAPMC-G-JNE2, MB9AF156NAPMC-G-JNE2, MB9AF154NABGL-GE1, MB9AF155NABGL-GE1, MB9AF156NABGL-GE1, MB9AF154MAPMC-G-JNE2, MB9AF155MAPMC-G-JNE2, MB9AF156MAPMC-G-JNE2, MB9AF154MABGL-GE1, MB9AF155MABGL-GE1, MB9AF156MABGL-GE1 15.2 Qualification Status Product Status: In Production − Qual. 15.3 Errata Summary This table defines the errata applicability to available devices. Items Part Number Silicon Revision Fix Status [1] HDMI-CEC arbitration lost issue Refer to 15.1 Initial rev. Fixed in Rev. A [2] HDMI-CEC polling message issue Refer to 15.1 Initial rev., Rev. A Fixed in Rev. B Document Number: 002-05646 Rev. *E Page 141 of 149 CY9A150RB Series 1. HDMI-CEC arbitration lost issue ◼ PROBLEM DEFINITION Large external load on CEC bus may cause arbitration lost. ◼ PARAMETERS AFFECTED N/A ◼ TRIGGER CONDITION(S) The arbitration lost detection mechanism samples outputting signals and determines that arbitration lost occurs if sampled signals do not match the outputting signals. The large external load on the CEC bus increases slew rate of the signals. The increased slew rate makes the mismatch between outputting signals and sampled signals and the mismatch misleads MCU that arbitration lost occurs. ◼ SCOPE OF IMPACT Once the arbitration lost is detected, the CEC aborts the transmission. Any transmission cannot be completed. ◼ WORKAROUND This error cannot be avoided by any software. Reduce the external load. ◼ FIX STATUS This issue was fixed in Rev. A. 2. HDMI-CEC polling message issue ◼ PROBLEM DEFINITION Error#1) While MCU sends a Polling Message, it always returns a NACK to a message coming to the MCU from another node. Error#2) MCU always waits for 7-bit signal free on CEC line before it drives the line even when the last line initiator was another node. ◼ PARAMETERS AFFECTED N/A ◼ TRIGGER CONDITION(S) This error always happens. ◼ SCOPE OF IMPACT MCU does not reply properly to another node. ◼ WORKAROUND The software workaround is applied to Error #1. 1. Store 0x0 to SFREE register. 2. Monitor CEC line with GPIO and wait until High on the CEC line lasts for the signal free time. 3. Store frame data to TXDATA register and store 0x0F to RCADR1 or RCADR2 register. It sends a message after 3~4 clocks of 32.768 kHz clock when TXDATA is stored. If the device receives a frame from another node within 2~3 clocks after storing TXDATA, the bus error occurs and if the device receives a frame from another node within 3~4 clocks after storing TXDATA, the arbitration lost occurs. In these cases: 4-A-1. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK 4-A-2. Return back to step 2 above If the device receives a frame from another node within 1~2 clocks after storing TXDATA, take these steps. 4-B-1. Monitor CEC line with GPIO after 50us from storing TXDATA 4-B-2. Set TXEN to 1 -> 0 -> 1 immediately when GPIO finds Low on the CEC line 4-B-3. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK Document Number: 002-05646 Rev. *E Page 142 of 149 CY9A150RB Series 4-B-4. Return back to step 2 above For Error #2, there is no software workaround, but signal free time of fixed 7-bit does not violate HDMI-CEC specification. The specification says signal free time must be more than and equals to 5-bit. ◼ FIX STATUS ◼ This issue was fixed in Rev. B. Document Number: 002-05646 Rev. *E Page 143 of 149 CY9A150RB Series 16. Major Changes Spansion Publication Number: MB9A150RB_DS706-00047 Page Section Change Results Revision 0.1 - - Initial release Revision 1.0 1 7 - Preliminary → Data Sheet Features Corrected the description of "Flash memory". On-chip Memories 1. Product Lineup 7.Handling Devices 71 74 75 78, 79 10.Memory Map 94, 95, Corrected the figure. ◼ TIOA: input → input/output ◼ TIOB: output → input Corrected the value of address of "SRAM0". 10.1 Memory Map (1) 10.2 Memory Map (2) Added the footnote. 11. Pin Status In Each CPU State ◼ Corrected the Return from Deep standby mode state of 11.1 List of Pin Status 13. Electrical Characteristics 77, 78 ◼ Added the description of "Crystal oscillator circuit". ◼ Added the description of "Sub crystal oscillator". 8.Block Diagram 75 Corrected the value of channel number of the "Base Timer". 1.2. Function 13.3. DC Characteristics "Pin status type H". ◼ Corrected the function group of "Pin status type I". ◼ Revised the value of "TBD". ◼ Revised the typical value of "Power supply voltage (ICCH, ICCT, ICCR)". 13.3.1 Current Rating ◼ Added the "Flash Memory Write/Erase current (ICCFLASH)". ◼ Added the footnote. 13.4. AC Characteristics ◼ Added the description of Note of "Input frequency (FCL)". 13.4.2 Sub Clock Input Characteristics ◼ Added the footnote. 13.4.3 Built-in CR Oscillation ◼ Revised the condition. Characteristics ◼ Corrected the value. 13.4.3.1 Built-in high-speed CR ◼ Added the item of "Frequency stabilization time". ◼ Added the footnote. 99 13.4.7. External Bus Timing ◼ Corrected the value. 13.4.7.1. Separate Bus Access ◼ Deleted the "MWEX ↓ → Data output time". Asynchronous SRAM Mode ◼ Added the "MCSX ↓ → Data output time". ◼ Corrected the figure. 101 13.4.7.2 Separate Bus Access ◼ Corrected the "MCLK↑ → Data output time". Synchronous SRAM Mode ◼ Added the "MCLK↑ → Data hold time". ◼ Corrected the figure. 110, 13.4.9. CSIO Timming UART Timming → CSIO Timming 112, Corrected the description of "Note". 114, 116 122 Corrected the description of section title. UART is connected → Multi-function Serial is connected 2 13.4.12 I C Timing Added the footnote. 13.5. 12-bit A/D Converter ◼ Revised the parameter. 125 ◼ Revised the symbol. ◼ Corrected the value. Document Number: 002-05646 Rev. *E Page 144 of 149 CY9A150RB Series Page 127 128, 129 130 Section Change Results 13.5.2 Definition of 12-bit A/D Converter ◼ Revised the parameter. Terms 13.6. Low-Voltage Detection ◼ Revised the symbol. ◼ Corrected "Conditions" and "Value" in the table. Characteristics ◼ Added the Item. 13.6.1 Low-Voltage Detection Reset ◼ Added the footnote. 13.6.2 Interrupt of Low-Voltage Detection Added the Item. Revision 1.1 - - Company name and layout design change Revision 2.0 - - Corrected the Series name. MB9A150R Series → MB9A150RA Series Corrected the Product name as follows. - - MB9AF156MA, MB9AF155MA, MB9AF154MA MB9AF156NA, MB9AF155NA, MB9AF154NA MB9AF156RA, MB9AF155RA, MB9AF154RA Features External Bus Interface Added the Item. ◼ Maximum area size : Up to 256 Mbytes 1 Multi-function Serial Interface Corrected the description of "I2C" 2 Multi-function Timer Corrected the channel count of "A/D activation compare" 1 7 9 1.Product Lineup 1.2 Function 2. Packages Added the footnote Delete the following packages. ◼ FPT-100P-M36 ◼ FPT-80P-M40 11 12 15 – 36 37 - 60 75 3. Pin Assignment 3.2 FPT-100P-M36 3.3 FPT-80P-M37 4. List Of Pin Function 4.1 List of numbers 4.2 List of pin functions 10.Memory Map 10.1 Memory Map (1) Delete the Item Corrected the description of section title. FPT-80P-M37/M40 →FPT-80P-M37 Delete column of terminal number "QFP-100" Delete column of terminal number "QFP-100" Corrected the address "External Device Area" 13.Electrical Characteristics 88 13.2.Recommended Operating Add the footnote Conditions ◼ Corrected the Condition 89 13.3.DC Characteristics ◼ Delete the minmun value 13.3.1 Current rating ◼ Corrected the remarks ◼ Add the footnote 13.9. CSIO Timing 116 13.9.4 Synchronous serial (SPI=1, Corrected the figure of "MS bit=1" SCINV=1) 13.9 CSIO Timing 117 13.4.9.5. External Corrected the figure clock(EXT=1):asyntironous only Document Number: 002-05646 Rev. *E Page 145 of 149 CY9A150RB Series Page 118 Section 13.4.10. External Input Timing Change Results Add the terminal as follows ◼ FRCKx ◼ ICxx ◼ DTTIxX 122 13.4.12. I2C Timing Corrected the description as follows. ◼ Typical mode → Standard-mode ◼ High-speed mode → Fast-mode ◼ Corrected the terminal name 13.5.12-bit A/D Converter 125 AN00 to AN23 → ANxx 13.5.1 Electrical Characteristics for ◼ Corrected the minimum value of "Sampling time" the A/D Converter ◼ Corrected the max and min value of "State transition time to operation permission" ◼ Corrected the footnote 137 14. ORDERING INFORMATON Corrected the "Part number" Revision 3.0 - - Corrected the Series name. MB9A150RA Series → MB9A150RB Series Corrected the Product name as follows. - - MB9AF156MB, MB9AF155MB, MB9AF154MB MB9AF156NB, MB9AF155NB, MB9AF154NB MB9AF156RB, MB9AF155RB, MB9AF154RB 76 89 10.Memory Map 10.2. Memory map(2) Added the summary of Flash memory sector 13. Electrical Characteristics ◼ Changed the table format 13.3. DC Characteristics ◼ Added Main TIMER mode current 13.3.1 Current rating ◼ Moved A/D Converter Current 13. Electrical Characteristics 96 13.4. AC Characteristics 13.4.1 Operating Conditions of Main PLL ◼ Added the figure of Main PLL connection 13.4.2 Operating Conditions of Main PLL 13. Electrical Characteristics 97 13. 4. AC Characteristics 13.4.6. Power-on Reset Timing 110 - 117 125 ◼ Added Time until releasing Power-on reset ◼ Changed the figure of timing 13.Electrical Characteristics ◼ Modified from UART Timing to CSIO/UART Timing 13.4. AC Characteristics ◼ Changed from Internal shift clock operation to Master mode 13.4.9 CSIO/UART Timing ◼ Changed from External shift clock operation to Slave mode ◼ Added the typical value of Integral Nonlinearity, Differential 13. Electrical Characteristics 13.5. 12bit A/D Converter Nonlinearity, Zero transition voltage and Full-scale transition voltage ◼ Added the value of conversion time at AVCC < 2.7 V 13. Electrical Characteristics 132 - 134 13.8. Return Time from Low-Power Added Return Time from Low-Power Consumption Mode Consumption Mode 137 14. Ordering Information Changed notation of part number 137 - 141 15. Package Dimensions Deleted FPT-100P-M36 and FPT-80P-M40 NOTE: Please see “Document History” about later revised information. Document Number: 002-05646 Rev. *E Page 146 of 149 CY9A150RB Series Document History Document Title: CY9A150RB Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller Document Number: 002-05646 Revision ECN Orig. of Change ** − AKIH Submission Date Description of Change 04/28/2015 Migrated to Cypress and assigned document number 002-05646. No change to document contents. *A 5226742 AKIH 04/27/2016 Updated to Cypress template. *B 5535819 YSKA 02/09/2017 Updated “12.4.6 Power-On Reset Timing”. Changed parameter from “Power Supply rise time(Tr)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and added some comments (Page 96) Modified RTC description in “Features, Real-Time Clock(RTC)” as below Changed starting count value from 01 to 00. Deleted “second , or day of the week” in the Interrupt function (Page 3) Added Notes for JTAG (Page 59), Changed “J-TAG” to” JTAG” in “4.2 List of Pin Functions” (Page 40) Updated Package code and dimensions as follows (Page 8-13, 135140) FPT-80P-M37 -> LQH080, BGA-96P-M07 -> FDG096, FPT-100P-M23 -> LQI100, BGA-112P-M04 -> LBC112, FPT-120P-M37 -> LQM120 Added “15.Errta (Page 141)” Deleted the note below from the footer of the first page. "CONFIDENTIAL - RELEASED ONLY UNDER NONDISCLOSURE AGREEMENT (NDA)" (Page 1) Added the Baud rate spec in “12.4.9 CSIO/UART Timing”(Page 109, 111, 113, 115) *C 5774754 YSAT 06/19/2017 Updated Cypress Logo and Copyright. *D 6575922 HUAL 05/17/2019 Updated Document Title to read as “CY9A150RB Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller”. Replaced “MB9A150RB Series” with “CY9A150RB Series” in all instances across the document. Updated Ordering Information: Updated part numbers. Updated to new template. *E 7153046 XITO 06/15/2021 Updated the part numbers in Ordering Information as follows: CY9AF154MBBGL-GE1 to CY9AF154MBBGL-GK9E1 CY9AF155MBBGL-GE1 to CY9AF155MBBGL-GK9E1 CY9AF156MBBGL-GE1 to CY9AF156MBBGL-GK9E1 Document Number: 002-05646 Rev. *E Page 147 of 149 CY9A150RB Series Revision ECN Orig. of Change Submission Date Description of Change CY9AF154NBBGL-GE1 to CY9AF154NBBGL-GK9E1 CY9AF155NBBGL-GE1 to CY9AF155NBBGL-GK9E1 CY9AF156NBBGL-GE1 to CY9AF156NBBGL-GK9E1 Updated Errata: Updated Part Numbers Affected: Updated part numbers in the table. Corrected some typos. Completing Sunset Review. Document Number: 002-05646 Rev. *E Page 148 of 149 CY9A150RB Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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