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name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will
offer these products to new and existing customers with the series name, product name, and
ordering part number with the prefix “CY”.
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About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to www.cypress.com.
MB9B110T Series
32-bit ARM® Cortex®-M3
FM3 Microcontroller
The MB9B110T Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive
cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as Motor
2
Control Timers, ADCs and Communication Interfaces (UART, CSIO, I C, LIN).
The products which are described in this data sheet are placed into TYPE2 product categories in "FM3 Family PERIPHERAL MANUAL".
Features
32-bit ARM Cortex-M3 Core
Multi-function Serial Interface (Max 8 channels)
Processor version: r2p1
4 channels with 16steps×9-bit FIFO (ch.4 to ch.7), 4
channels without FIFO (ch.0 to ch.3)
Up to 144 MHz Frequency Operation
Memory Protection Unit (MPU): improves the reliability of
an embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
2
IC
[UART]
Full-duplex double buffer
On-chip Memories
Selection with or without parity supported
[Flash memory]
Built-in dedicated baud rate generator
Up to 1 Mbyte
External clock available as a serial clock
Built-in Flash memory Accelerator System with 16 Kbyte
trace buffer memory
The read access to Flash memory can be achieved without
wait cycle up to the operation frequency of 72MHz. Even at
the operation frequency more than 72 MHz, an equivalent
access to Flash memory can be obtained by Flash memory
Accelerator System.
Hardware Flow control: Automatically controls the
transmission/reception with CTS/RTS (only for ch.4)
Security function for code protection
Various error detection functions available (parity errors,
framing errors, and overrun errors)
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
[SRAM]
Overrun error detection function available
This Series on-chip SRAM is composed of two independent
SRAMs (SRAM0, SRAM1) . SRAM0 is connected to I-code
bus and D-code bus of Cortex-M3 core. SRAM1 is connected
to System bus.
[LIN]
LIN protocol Rev.2.1 supported
Full-duplex double buffer
SRAM0: Up to 64 Kbytes.
Master/Slave mode supported
SRAM1: Up to 64 Kbytes.
LIN break field generation (can be changed to 13-bit length
to 16-bit)
External Bus Interface
LIN break delimiter generation (can be changed to 1-bit
length to 4-bit)
Supports SRAM, NOR and NAND Flash memory devices
Various error detection functions available (parity errors,
framing errors, and overrun errors)
Up to 8 chips selected
8-/16-bit Data width
2
[I C]
Up to 25-bit Address bit
Maximum area size: Up to 256 Mbytes
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
Supports Address/Data multiplex
supported
Supports external RDY function
Cypress Semiconductor Corporation
Document Number: 002-04683 Rev.*C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 11, 2017
MB9B110T Series
DMA Controller (8 channels)
The DMA Controller has a dedicated bus independent from the
CPU, so CPU and DMA Controller can process
simultaneously.
Multi-function Timer (Max 3 units)
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3 ch./unit
Input capture × 4 ch./unit
8 independently configured and operated channels
Output compare × 6 ch./unit
Transfer can be started by software or request from the
built-in peripherals
A/D activation compare × 3 ch./unit
Transfer address area: 32 bits (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Waveform generator × 3 ch./unit
16-bit PPG timer × 3 ch./unit
Transfer data type: byte/half-word/word
The following function can be used to achieve the motor
control.
Transfer block count: 1 to 16
PWM signal output function
Number of transfers: 1 to 65536
DC chopper waveform output function
A/D Converter (Max 32 channels)
Dead time function
Input capture function
[12-bit A/D Converter]
A/D convertor activate function
Successive Approximation type
DTIF (Motor emergency stop) interrupt function
Built-in 3units
Conversion time: 1.0 μs @ 5 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion: 4 steps)
Base Timer (Max 16 channels)
Operation mode is selectable from the followings for each
channel.
16-bit PWM timer
Quadrature Position/Revolution Counter (QPRC)
(Max 3 channels)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use the counter as the up/down counter.
The detection edge of three external event input pins AIN,
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
16-bit PPG timer
16-/32-bit reload timer
Dual Timer (32-/16-bit Down Counter)
16-/32-bit PWC timer
The Dual Timer consists of two programmable 32-/16-bit down
counters.Operation mode is selectable from the followings for
each channel.
General-Purpose I/O Port
This series can use its pins as I/O ports when they are not
used for an external bus or peripherals. Moreover, the port
relocate function is built in. It can set which I/O port the
peripheral function can be allocated to.
Free-running
Capable of pull-up control per pin
Watch Counter
Capable of reading pin level directly
Built-in port relocate function
The Watch counter is used for wake up from low-power
consumption mode.
Up to 154 fast I/O Ports@ 176 pin Package
Interval timer: up to 64 s(Max)@ Sub Clock: 32.768 kHz
Some ports are 5 V tolerant I/O.
See "Pin Assignment" to confirm the corresponding pins.
Periodic (=Reload)
One-shot
External Interrupt Controller Unit
Up to 32 external interrupt input pins
One non-maskable interrupt (NMI) pin
Document Number: 002-04683 Rev.*C
Page 2 of 132
MB9B110T Series
Watchdog Timer (2 channels)
Voltage Detector generates an interrupt or reset.
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
LVD1: error reporting via interrupt
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
The "Hardware" watchdog timer is operated by the built-in
low-speed CR oscillator. Therefore, the "Hardware" watchdog
is active in any low-power consumption mode except STOP
mode.
LVD2: auto-reset operation
Low-Power Consumption Mode
Three Low-Power Consumption modes supported.
Sleep
Timer
Stop
CRC (Cyclic Redundancy Check) Accelerator
Debug
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
Serial Wire JTAG Debug Port (SWJ-DP)
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
Power Supply
Embedded Trace Macrocells (ETM).
Wide range voltage VCC = 2.7 V to 5.5 V
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
Main Clock: 4 MHz to 48 MHz
Sub Clock: 32.768 kHz
Built-in high-speed CR Clock: 4 MHz
Built-in low-speed CR Clock: 100 kHz
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock supervisor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
When external clock failure (clock stop) is detected, reset is
asserted.
When external frequency anomaly is detected, interrupt or
reset is asserted.
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage set, Low
Document Number: 002-04683 Rev.*C
Page 3 of 132
MB9B110T Series
Contents
Features.......................................................................................................................................................................... 1
1.
Product Lineup ...................................................................................................................................................... 6
2.
Packages................................................................................................................................................................ 7
3.
Pin Assignment ..................................................................................................................................................... 8
4.
List of Pin Functions ........................................................................................................................................... 11
5.
I/O Circuit Type .................................................................................................................................................... 58
6.
Handling Precautions ......................................................................................................................................... 65
6.1
Precautions for Product Design .......................................................................................................................... 65
6.2
Precautions for Package Mounting ..................................................................................................................... 67
6.3
Precautions for Use Environment ....................................................................................................................... 68
7.
Handling Devices ................................................................................................................................................ 69
8.
Block Diagram ..................................................................................................................................................... 72
9.
Memory Size ........................................................................................................................................................ 73
10. Memory Map ........................................................................................................................................................ 73
11. Pin Status in Each CPU State ............................................................................................................................. 76
12. Electrical Characteristics ................................................................................................................................... 80
12.1
Absolute Maximum Ratings ................................................................................................................................ 80
12.2
Recommended Operating Conditions................................................................................................................. 82
12.3
DC Characteristics.............................................................................................................................................. 83
12.3.1 Current Rating ..................................................................................................................................................... 83
12.3.2 Pin Characteristics .............................................................................................................................................. 85
12.4
AC Characteristics .............................................................................................................................................. 87
12.4.1 Main Clock Input Characteristics ......................................................................................................................... 87
12.4.2 Sub Clock Input Characteristics .......................................................................................................................... 88
12.4.3 Internal CR Oscillation Characteristics ................................................................................................................ 88
12.4.4 Operating Conditions of Main and USB PLL ....................................................................................................... 89
12.4.5 Reset Input Characteristics ................................................................................................................................. 90
12.4.6 Power-on Reset Timing....................................................................................................................................... 90
12.4.7 External Bus Timing ............................................................................................................................................ 91
12.4.8 Base Timer Input Timing ................................................................................................................................... 101
12.4.9 CSIO/UART Timing ........................................................................................................................................... 102
12.4.10 External Input Timing ..................................................................................................................................... 110
12.4.11 Quadrature Position/Revolution Counter timing ............................................................................................. 111
2
12.4.12 I C Timing ...................................................................................................................................................... 113
12.4.13 ETM Timing ................................................................................................................................................... 114
12.4.14 JTAG Timing .................................................................................................................................................. 115
12.5
12-bit A/D Converter ......................................................................................................................................... 116
12.6
Low-Voltage Detection Characteristics ............................................................................................................. 119
12.6.1 Low-Voltage Detection Reset ............................................................................................................................ 119
12.6.2 Interrupt of Low-Voltage Detection .................................................................................................................... 119
12.7
Flash Memory Write/Erase Characteristics ...................................................................................................... 120
12.7.1 Write / Erase time.............................................................................................................................................. 120
12.7.2 Write cycles and data hold time ........................................................................................................................ 120
12.8
Return Time from Low-Power Consumption Mode ........................................................................................... 121
12.8.1 Return Factor: Interrupt ..................................................................................................................................... 121
Document Number: 002-04683 Rev.*C
Page 4 of 132
MB9B110T Series
12.8.2 Return Factor: Reset ......................................................................................................................................... 123
13. Ordering Information ........................................................................................................................................ 125
14. Package Dimensions ........................................................................................................................................ 126
15. Major Changes .................................................................................................................................................. 129
Document History ...................................................................................................................................................... 131
Sales, Solutions, and Legal Information .................................................................................................................. 132
Document Number: 002-04683 Rev.*C
Page 5 of 132
MB9B110T Series
1.
Product Lineup
Memory size
Product name
On-chip Flash memory
MB9BF116S/T
512 Kbytes
MB9BF117S/T
768 Kbytes
MB9BF118S/T
1 Mbytes
On-chip SRAM
64 Kbytes
96 Kbytes
128 Kbytes
MB9BF116S
MB9BF117S
MB9BF118S
144
MB9BF116T
MB9BF117T
MB9BF118T
176/192
Function
Product name
Pin count
CPU
Freq.
Cortex-M3
144 MHz
Supply voltage range
2.7 V to 5.5 V
DMAC
8 ch
Addr:19-bit (Max)
R/Wdata:8-/16-bit (Max)
CS: 8 (Max)
Support: SRAM, NOR & NAND
Flash memory
External Bus Interface
Addr:25-bit (Max)
R/Wdata:8-/16-bit (Max)
CS:8 (Max)
Support: SRAM, NOR &
NAND Flash memory
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
8 ch. (Max)
ch.4 to ch.7: FIFO (16steps ×9 bits)
ch.0 to ch.3: No FIFO
Base Timer
(PWC/ Reload timer/PWM/PPG)
16 ch. (Max)
A/D activation compare
MF-Timer
Input capture
Free-run timer
Output compare
Waveform generator
PPG
QPRC
Dual Timer
Watch Counter
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
3 ch.
4 ch.
3 ch.
6 ch.
3 ch.
3 ch.
3 units (Max)
3 ch. (Max)
1 unit
1 unit
Yes
1 ch. (SW) + 1 ch. (HW)
32 pins (Max) + NMI pin× 1
122 pins (Max)
154 pins (Max)
24 ch. (3 units)
32 ch. (3 units)
Yes
2 ch.
High-speed
4 MHz
Low-speed
100 kHz
Built-in CR
Debug Function
SWJ-DP/ETM
Note:
−
All signals of the peripheral function in each product cannot be allocated due to the pin count restriction of a package. It is
necessary to use the port relocate function of the I/O port according to functions use. See "Electrical Characteristics 12.4 AC
Characteristics 12.4.3 Internal CR Oscillation Characteristics" for accuracy of built-in CR.
Document Number: 002-04683 Rev.*C
Page 6 of 132
MB9B110T Series
2.
Packages
Product name
Package
MB9BF116S
MB9BF117S
MB9BF118S
MB9BF116T
MB9BF117T
MB9BF118T
LQFP:
LQS144 (0.5 mm pitch)
-
LQFP:
LQP176 (0.5 mm pitch)
-
BGA:
LBE192 (0.8 mm pitch)
-
: Supported
Note:
−
See "Package Dimensions" for detailed information on each package.
Document Number: 002-04683 Rev.*C
Page 7 of 132
MB9B110T Series
3.
Pin Assignment
LQP176
P00/TRSTX
P01/TCK/SWCLK
P02/TDI
P03/TMS/SWDIO
P04/TDO/SWO
P90/TIOB08_0/RTO20_1/INT30_0/MAD19_0
P91/TIOB09_0/RTO21_1/INT31_0/MAD20_0
P92/TIOB10_0/RTO22_1/SIN5_1/MAD21_0
P93/TIOB11_0/RTO23_1/SOT5_1/MAD22_0
P94/TIOB12_0/RTO24_1/SCK5_1/INT26_0/MAD23_0
P95/TIOB13_0/RTO25_1/INT27_0/MAD24_0
PC0
PC1
PC2
PC3/TIOA06_1
PC4/TIOA08_2
PC5/TIOA10_2
PC6/TIOA14_0
PC7/CROUT_1
PC8
PC9
PCA
VCC
VSS
PCB
PCC
PCD
PCE/RTS4_0/TIOB06_1
PCF/CTS4_0/TIOB08_2
PD0/SCK4_0/TIOB10_2/INT30_1
PD1/SOT4_0/TIOB14_0/INT31_1
PD2/SIN4_0/TIOA03_2/INT00_2
PD3/TIOB03_2
P62/SCK5_0/ADTG_3
P61/SOT5_0/TIOB02_2
P60/SIN5_0/TIOA02_2/INT15_1
PF3/TIOA06_0/SIN6_2/INT06_0/AIN2_1
PF4/TIOB06_0/SOT6_2/INT07_0/BIN2_1
PF5/SCK6_2/INT08_0/ZIN2_1
VCC
P80
P81
VCC
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
VSS
(TOP VIEW)
VCC
1
132
VSS
PA0/RTO20_0/TIOA08_0/FRCK1_0
2
131
P83
PA1/RTO21_0/TIOA09_0/IC10_0
3
130
P82
PA2/RTO22_0/TIOA10_0/IC11_0
4
129
VCC
PA3/RTO23_0/TIOA11_0/IC12_0
5
128
PF6/FRCK2_0/NMIX
PA4/RTO24_0/TIOA12_0/IC13_0/INT03_0
6
127
P20/INT05_0/CROUT_0/AIN1_1/MAD18_0
PA5/RTO25_0/TIOA13_0/INT10_2
7
126
P21/SIN0_0/INT06_1/BIN1_1
P05/TRACED0/TIOA05_2/SIN4_2/INT00_1
8
125
P22/AN31/SOT0_0/TIOB07_1/ZIN1_1
P06/TRACED1/TIOB05_2/SOT4_2/INT01_1
9
124
P23/AN30/SCK0_0/TIOA07_1/RTO00_1
P07/TRACED2/ADTG_0/SCK4_2
10
123
P24/AN29/SIN2_1/INT01_2/RTO01_1/MAD17_0
P08/TRACED3/TIOA00_2/CTS4_2
11
122
P25/AN28/SOT2_1/RTO02_1/MAD16_0
P09/TRACECLK/TIOB00_2/RTS4_2/DTTI2X_0
12
121
P26/AN27/SCK2_1/RTO03_1/MAD15_0
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/IC20_0/MOEX_0
13
120
P27/AN26/INT02_2/RTO04_1/MAD14_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/IC21_0/MWEX_0
14
119
P28/AN25/ADTG_4/INT09_0/RTO05_1/MAD13_0
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/IC22_0/MDQM0_0
15
118
P29/AN24/MAD12_0
P53/SIN6_0/TIOA01_2/INT07_2/RTO13_0/IC23_0/MDQM1_0
16
117
PB7/AN23/TIOB12_1/INT23_0/ZIN2_2
P54/SOT6_0/TIOB01_2/RTO14_0/MALE_0
17
116
PB6/AN22/TIOA12_1/SCK0_2/INT22_0/BIN2_2
P55/SCK6_0/ADTG_1/RTO15_0/MRDY_0
18
115
PB5/AN21/TIOB11_1/SOT0_2/INT21_0/AIN2_2
P56/SIN1_0/INT08_2/TIOA09_2/DTTI1X_0/MNALE_0
19
114
PB4/AN20/TIOA11_1/SIN0_2/INT20_0
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
20
113
PB3/AN19/TIOB10_1/INT19_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
21
112
PB2/AN18/TIOA10_1/SCK7_2/INT18_0
P59/SIN7_0/TIOB11_2/INT09_2/MNREX_0
22
111
PB1/AN17/TIOB09_1/SOT7_2/INT17_0
P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_0
23
110
PB0/AN16/TIOA09_1/SIN7_2/INT16_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
24
109
VSS
P5C/TIOA06_2/INT28_0/IC20_1
25
108
AVSS
P5D/TIOB06_2/INT29_0/DTTI2X_1
26
107
AVRH
VSS
27
106
AVCC
P30/AIN0_0/TIOB00_1/INT03_2
28
105
P1F/AN15/ADTG_5/INT29_1/TIOB15_2/FRCK0_1/MAD11_0
P31/BIN0_0/TIOB01_1/SCK6_1/INT04_2
29
104
P1E/AN14/RTS4_1/INT28_1/TIOA15_2/DTTI0X_1/MAD10_0
P32/ZIN0_0/TIOB02_1/SOT6_1/INT05_2
30
103
P1D/AN13/CTS4_1/INT27_1/TIOB14_2/IC03_1/MAD09_0
P33/INT04_0/TIOB03_1/SIN6_1/ADTG_6
31
102
P1C/AN12/SCK4_1/INT26_1/TIOA14_2/IC02_1/MAD08_0
P34/FRCK0_0/TIOB04_1
32
101
P1B/AN11/SOT4_1/INT25_1/TIOB13_2/IC01_1/MAD07_0
P35/IC03_0/TIOB05_1/INT08_1
33
100
P1A/AN10/SIN4_1/INT05_1/TIOA13_2/IC00_1/MAD06_0
P36/IC02_0/SIN5_2/INT09_1/TIOA12_2/MCSX2_0
34
99
P19/AN09/SCK2_2/INT22_1/MAD05_0
P37/IC01_0/SOT5_2/INT10_1/TIOB12_2/MCSX3_0
35
98
P18/AN08/SOT2_2/INT21_1/MAD04_0
P38/IC00_0/SCK5_2/INT11_1/MCLKOUT_0
36
97
P17/AN07/SIN2_2/INT04_1/MAD03_0
P39/DTTI0X_0/ADTG_2
37
96
P16/AN06/SCK0_1/INT20_1/MAD02_0
P3A/RTO00_0/TIOA00_1
38
95
P15/AN05/SOT0_1/IC03_2/MAD01_0
P3B/RTO01_0/TIOA01_1
39
94
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD00_0
P3C/RTO02_0/TIOA02_1
40
93
P13/AN03/SCK1_1/IC01_2/MCSX4_0
P3D/RTO03_0/TIOA03_1
41
92
P12/AN02/SOT1_1/IC00_2/MCSX5_0
P3E/RTO04_0/TIOA04_1
42
91
P11/AN01/SIN1_1/INT02_1/FRCK0_2/MCSX6_0
P3F/RTO05_0/TIOA05_1
43
90
P10/AN00/MCSX7_0
VSS
44
89
VCC
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VCC
P40/TIOA00_0/RTO10_1/INT12_1
P41/TIOA01_0/RTO11_1/INT13_1
P42/TIOA02_0/RTO12_1
P43/TIOA03_0/RTO13_1/ADTG_7
P44/TIOA04_0/RTO14_1
P45/TIOA05_0/RTO15_1
C
VSS
VCC
P46/X0A
P47/X1A
INITX
P48/DTTI1X_1/INT14_1/SIN3_2
P49/TIOB00_0/IC10_1/AIN0_1/SOT3_2
P4A/TIOB01_0/IC11_1/BIN0_1/SCK3_2/MADATA00_0
P4B/TIOB02_0/IC12_1/ZIN0_1/MADATA01_0
P4C/TIOB03_0/IC13_1/SCK7_1/AIN1_2/MADATA02_0
P4D/TIOB04_0/FRCK1_1/SOT7_1/BIN1_2/MADATA03_0
P4E/TIOB05_0/INT06_2/SIN7_1/ZIN1_2/MADATA04_0
P70/TIOA04_2/MADATA05_0
P71/INT13_2/TIOB04_2/MADATA06_0
P72/SIN2_0/INT14_2/AIN2_0/MADATA07_0
P73/SOT2_0/INT15_2/BIN2_0/MADATA08_0
P74/SCK2_0/ZIN2_0/MADATA09_0
P75/SIN3_0/ADTG_8/INT07_1/MADATA10_0
P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0
P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0
P78/AIN1_0/TIOA15_0/MADATA13_0
P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0
P7A/ZIN1_0/INT24_1/MADATA15_0
P7B/TIOB07_0/INT10_0
P7C/TIOA07_0/INT11_0
P7D/TIOA14_1/FRCK2_1/INT12_0
P7E/TIOB14_1/IC21_1/INT24_0
P7F/TIOA15_1/IC22_1/INT25_0
PF0/TIOB15_1/SIN1_2/INT13_0/IC23_1
PF1/TIOA08_1/SOT1_2/INT14_0
PF2/TIOB08_1/SCK1_2/INT15_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 176
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.TIOA09_0, TIOA09_1, and TIOA09_2 cannot be used as the external startup trigger input
(TGIN signal) at I/O mode 1 (timer full mode) of the Base Timer. See "0 Base Timer" in "Handling Devices" for details.
Document Number: 002-04683 Rev.*C
Page 8 of 132
MB9B110T Series
LQS144
P00/TRSTX
P01/TCK/SWCLK
P02/TDI
P03/TMS/SWDIO
P04/TDO/SWO
PC0
PC1
PC2
PC3/TIOA06_1
PC4/TIOA08_2
PC5/TIOA10_2
PC6/TIOA14_0
PC7/CROUT_1
PC8
PC9
PCA
VCC
VSS
PCB
PCC
PCD
PCE/RTS4_0/TIOB06_1
PCF/CTS4_0/TIOB08_2
PD0/SCK4_0/TIOB10_2/INT30_1
PD1/SOT4_0/TIOB14_0/INT31_1
PD2/SIN4_0/TIOA03_2/INT00_2
PD3/TIOB03_2
P62/SCK5_0/ADTG_3
P61/SOT5_0/TIOB02_2
P60/SIN5_0/TIOA02_2/INT15_1
PF5/SCK6_2/INT08_0/ZIN2_1
VCC
P80
P81
VCC
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VSS
(TOP VIEW)
VCC
1
108
VSS
PA0/RTO20_0/TIOA08_0/FRCK1_0
2
107
P83
PA1/RTO21_0/TIOA09_0/IC10_0
3
106
P82
PA2/RTO22_0/TIOA10_0/IC11_0
4
105
VCC
PA3/RTO23_0/TIOA11_0/IC12_0
5
104
PF6/FRCK2_0/NMIX
PA4/RTO24_0/TIOA12_0/IC13_0/INT03_0
6
103
P20/INT05_0/CROUT_0/AIN1_1/MAD18_0
PA5/RTO25_0/TIOA13_0/INT10_2
7
102
P21/SIN0_0/INT06_1/BIN1_1
P05/TRACED0/TIOA05_2/SIN4_2/INT00_1
8
101
P22/AN31/SOT0_0/TIOB07_1/ZIN1_1
P06/TRACED1/TIOB05_2/SOT4_2/INT01_1
9
100
P23/AN30/SCK0_0/TIOA07_1/RTO00_1
P07/TRACED2/ADTG_0/SCK4_2
10
99
P24/AN29/SIN2_1/INT01_2/RTO01_1/MAD17_0
P08/TRACED3/TIOA00_2/CTS4_2
11
98
P25/AN28/SOT2_1/RTO02_1/MAD16_0
P09/TRACECLK/TIOB00_2/RTS4_2/DTTI2X_0
12
97
P26/AN27/SCK2_1/RTO03_1/MAD15_0
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/IC20_0/MOEX_0
13
96
P27/AN26/INT02_2/RTO04_1/MAD14_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/IC21_0/MWEX_0
14
95
P28/AN25/ADTG_4/INT09_0/RTO05_1/MAD13_0
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/IC22_0/MDQM0_0
15
94
P29/AN24/MAD12_0
P53/SIN6_0/TIOA01_2/INT07_2/RTO13_0/IC23_0/MDQM1_0
16
93
VSS
P54/SOT6_0/TIOB01_2/RTO14_0/MALE_0
17
92
AVSS
P55/SCK6_0/ADTG_1/RTO15_0/MRDY_0
18
91
AVRH
P56/SIN1_0/INT08_2/TIOA09_2/DTTI1X_0/MNALE_0
19
90
AVCC
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
20
89
P1F/AN15/ADTG_5/INT29_1/TIOB15_2/FRCK0_1/MAD11_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
21
88
P1E/AN14/RTS4_1/INT28_1/TIOA15_2/DTTI0X_1/MAD10_0
P59/SIN7_0/TIOB11_2/INT09_2/MNREX_0
22
87
P1D/AN13/CTS4_1/INT27_1/TIOB14_2/IC03_1/MAD09_0
P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_0
23
86
P1C/AN12/SCK4_1/INT26_1/TIOA14_2/IC02_1/MAD08_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
24
85
P1B/AN11/SOT4_1/INT25_1/TIOB13_2/IC01_1/MAD07_0
VSS
25
84
P1A/AN10/SIN4_1/INT05_1/TIOA13_2/IC00_1/MAD06_0
LQFP - 144
71
72
VSS
PE3/X1
69
70
PE2/X0
MD0
68
PE0/MD1
67
P7A/ZIN1_0/INT24_1/MADATA15_0
P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0
P78/AIN1_0/TIOA15_0/MADATA13_0
P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0
P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0
P75/SIN3_0/ADTG_8/INT07_1/MADATA10_0
P74/SCK2_0/ZIN2_0/MADATA09_0
P73/SOT2_0/INT15_2/BIN2_0/MADATA08_0
P71/INT13_2/TIOB04_2/MADATA06_0
P72/SIN2_0/INT14_2/AIN2_0/MADATA07_0
P70/TIOA04_2/MADATA05_0
P4E/TIOB05_0/INT06_2/SIN7_1/ZIN1_2/MADATA04_0
P4D/TIOB04_0/FRCK1_1/SOT7_1/BIN1_2/MADATA03_0
P4B/TIOB02_0/IC12_1/ZIN0_1/MADATA01_0
P4C/TIOB03_0/IC13_1/SCK7_1/AIN1_2/MADATA02_0
P4A/TIOB01_0/IC11_1/BIN0_1/SCK3_2/MADATA00_0
P48/DTTI1X_1/INT14_1/SIN3_2
P49/TIOB00_0/IC10_1/AIN0_1/SOT3_2
INITX
P47/X1A
P46/X0A
VCC
VSS
C
P45/TIOA05_0/RTO15_1
P44/TIOA04_0/RTO14_1
P42/TIOA02_0/RTO12_1
P43/TIOA03_0/RTO13_1/ADTG_7
VCC
P41/TIOA01_0/RTO11_1/INT13_1
P40/TIOA00_0/RTO10_1/INT12_1
66
VCC
65
73
64
36
63
P10/AN00/MCSX7_0
VSS
62
74
61
35
60
P11/AN01/SIN1_1/INT02_1/FRCK0_2/MCSX6_0
P3F/RTO05_0/TIOA05_1
59
75
58
34
57
P12/AN02/SOT1_1/IC00_2/MCSX5_0
P3E/RTO04_0/TIOA04_1
56
76
55
33
54
P13/AN03/SCK1_1/IC01_2/MCSX4_0
P3D/RTO03_0/TIOA03_1
53
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD00_0
77
52
78
32
51
31
P3C/RTO02_0/TIOA02_1
50
P15/AN05/SOT0_1/IC03_2/MAD01_0
P3B/RTO01_0/TIOA01_1
49
79
48
30
47
P16/AN06/SCK0_1/INT20_1/MAD02_0
P3A/RTO00_0/TIOA00_1
46
80
45
29
44
P17/AN07/SIN2_2/INT04_1/MAD03_0
P39/DTTI0X_0/ADTG_2
43
81
42
28
41
P18/AN08/SOT2_2/INT21_1/MAD04_0
P38/IC00_0/SCK5_2/INT11_1/MCLKOUT_0
40
P19/AN09/SCK2_2/INT22_1/MAD05_0
82
39
83
27
38
26
37
P36/IC02_0/SIN5_2/INT09_1/TIOA12_2/MCSX2_0
P37/IC01_0/SOT5_2/INT10_1/TIOB12_2/MCSX3_0
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin. TIOA09_0, TIOA09_1, and TIOA09_2 cannot be used as the external startup trigger input
(TGIN signal) at I/O mode 1 (timer full mode) of the Base Timer. See "0 Base Timer" in "Handling Devices" for details.
Document Number: 002-04683 Rev.*C
Page 9 of 132
MB9B110T Series
LBE192
(TOP VIEW)
1
A
2
3
4
5
6
7
8
9
10
11
12
13
14
P81 P80 VCC VSS PCD PCB VSS VCC PC8 VSS TCK VCC
B
VSS PA0 PF5 PF3 P61 PD1 PCA PC1 P95 P92 TDO TMS
C
VCC PA1 PA2 PF4 P60 PD2 PCC PC5 PC0 P93 P90
D
PA5 PA4 P05 P06 PA3 PD3 PCE PC6 PC2 P94 P91 P21 P20 P82
E
VSS P07 P08 P09 P50 P62 PCF PC7 PC3 P25 P24 P23 P22 VCC
F
P51 P52 P53 P54 P55 P56 PD0 PC9 PC4 P29 P28 P27 P26 VSS
G
VSS P57 P58 P59 P5A P5B VSS VSS PB7 PB6 PB5 PB4 PB3 AVSS
H
P5C P5D P30 P31 P32 P33 VSS VSS P1F P1E PB2 PB1 PB0 AVRH
J
VSS P37 P36 P35 P34 P70 VSS P76 P1D P1C P1B P1A P19 AVCC
K
P38 P39 P3A P3B P4A P4E VSS P74 P7B P7F P18 P16 P15 P17
L
P3C P3D P3E P43 P49 P4D VSS P73 P7A P7E P14 P13 P12 VSS
M
VSS P3F P42 P44 P48 P4C VSS P72 P79 PF0 PF2 P11 P10 VCC
N
VCC P40 P41 P45 INITX P4B VSS P71 P78 P7D PF1 MD0 MD1 VSS
P
C
VSS VCC X0A X1A VSS P75 P77 P7C VSS
TRSTX
VSS
TDI PF6 P83
X0
X1
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin. TIOA09_0, TIOA09_1, and TIOA09_2 cannot be used as the external startup trigger input
(TGIN signal) at I/O mode 1 (timer full mode) of the Base Timer. See "0 Base Timer" in "Handling Devices" for details.
Document Number: 002-04683 Rev.*C
Page 10 of 132
MB9B110T Series
4.
List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, the same function is provided on the same channel. Use the extended port function register (EPFR) to select the pin.
Pin No
Pin Name
LQFP-176
LQFP-144
BGA-192
1
1
C1
I/O circuit
type
VCC
Pin state
type
-
PA0
RTO20_0
2
2
B2
G
I
G
I
G
I
G
I
G
H
G
H
E
F
TIOA08_0
FRCK1_0
PA1
RTO21_0
3
3
C2
TIOA09_0
IC10_0
PA2
RTO22_0
4
4
C3
TIOA10_0
IC11_0
PA3
RTO23_0
5
5
D5
TIOA11_0
IC12_0
PA4
RTO24_0
6
6
D2
TIOA12_0
IC13_0
INT03_0
PA5
RTO25_0
7
7
D1
TIOA13_0
INT10_2
P05
TRACED0
8
8
D3
TIOA05_2
SIN4_2
INT00_1
Document Number: 002-04683 Rev.*C
Page 11 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
E
F
E
G
E
G
E
G
E
H
E
H
P06
TRACED1
9
9
D4
TIOB05_2
SOT4_2
INT01_1
P07
TRACED2
10
10
E2
ADTG_0
SCK4_2
P08
TRACED3
11
11
E3
TIOA00_2
CTS4_2
P09
TRACECLK
12
12
E4
TIOB00_2
RTS4_2
DTTI2X_0
P50
INT00_0
AIN0_2
13
13
E5
SIN3_1
RTO10_0
IC20_0
MOEX_0
P51
INT01_0
BIN0_2
14
14
F1
SOT3_1
RTO11_0
IC21_0
MWEX_0
Document Number: 002-04683 Rev.*C
Page 12 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
E
H
E
H
E
I
E
I
E
H
E
H
P52
INT02_0
ZIN0_2
15
15
F2
SCK3_1
RTO12_0
IC22_0
MDQM0_0
P53
SIN6_0
TIOA01_2
16
16
F3
INT07_2
RTO13_0
IC23_0
MDQM1_0
P54
SOT6_0
17
17
F4
TIOB01_2
RTO14_0
MALE_0
P55
SCK6_0
18
18
F5
ADTG_1
RTO15_0
MRDY_0
P56
SIN1_0
INT08_2
19
19
F6
TIOA09_2
DTTI1X_0
MNALE_0
P57
SOT1_0
20
20
G2
TIOB09_2
INT16_1
MNCLE_0
Document Number: 002-04683 Rev.*C
Page 13 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
E
H
E
H
E
H
E
H
E
H
E
H
P58
SCK1_0
21
21
G3
TIOA11_2
INT17_1
MNWEX_0
P59
SIN7_0
22
22
G4
TIOB11_2
INT09_2
MNREX_0
P5A
SOT7_0
23
23
G5
TIOA13_1
INT18_1
MCSX0_0
P5B
SCK7_0
24
24
G6
TIOB13_1
INT19_1
MCSX1_0
P5C
TIOA06_2
25
-
H1
INT28_0
IC20_1
P5D
TIOB06_2
26
-
H2
INT29_0
DTTI2X_1
27
25
J1
VSS
-
P30
AIN0_0
28
-
H3
E
H
TIOB00_1
INT03_2
Document Number: 002-04683 Rev.*C
Page 14 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
E
H
E
H
E
H
E
I
E
H
E
H
E
H
P31
BIN0_0
29
-
H4
TIOB01_1
SCK6_1
INT04_2
P32
ZIN0_0
30
-
H5
TIOB02_1
SOT6_1
INT05_2
P33
INT04_0
31
-
H6
TIOB03_1
SIN6_1
ADTG_6
P34
32
-
J5
FRCK0_0
TIOB04_1
P35
IC03_0
33
-
J4
TIOB05_1
INT08_1
P36
IC02_0
SIN5_2
34
26
J3
INT09_1
TIOA12_2
MCSX2_0
P37
IC01_0
SOT5_2
35
27
J2
INT10_1
TIOB12_2
MCSX3_0
Document Number: 002-04683 Rev.*C
Page 15 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
E
H
E
I
G
I
G
I
G
I
G
I
G
I
G
I
P38
IC00_0
36
28
K1
SCK5_2
INT11_1
MCLKOUT_0
P39
37
29
K2
DTTI0X_0
ADTG_2
P3A
38
30
K3
RTO00_0
TIOA00_1
P3B
39
31
K4
RTO01_0
TIOA01_1
P3C
40
32
L1
RTO02_0
TIOA02_1
P3D
41
33
L2
RTO03_0
TIOA03_1
P3E
42
34
L3
RTO04_0
TIOA04_1
P3F
43
35
M2
RTO05_0
TIOA05_1
44
36
M1
VSS
-
45
37
N1
VCC
-
P40
TIOA00_0
46
38
N2
G
H
RTO10_1
INT12_1
Document Number: 002-04683 Rev.*C
Page 16 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
G
H
G
I
G
I
G
I
G
I
P41
TIOA01_0
47
39
N3
RTO11_1
INT13_1
P42
48
40
M3
TIOA02_0
RTO12_1
P43
TIOA03_0
49
41
L4
RTO13_1
ADTG_7
P44
50
42
M4
TIOA04_0
RTO14_1
P45
51
43
N4
TIOA05_0
RTO15_1
52
44
P2
C
-
53
45
P3
VSS
-
54
46
P4
VCC
-
55
47
P5
P46
D
M
D
N
B
C
E
H
E
I
X0A
P47
56
48
P6
X1A
57
49
N5
INITX
P48
DTTI1X_1
58
50
M5
INT14_1
SIN3_2
P49
TIOB00_0
59
51
L5
IC10_1
AIN0_1
SOT3_2
Document Number: 002-04683 Rev.*C
Page 17 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
E
I
E
I
E
I
E
I
E
H
E
I
P4A
TIOB01_0
IC11_1
60
52
K5
BIN0_1
SCK3_2
MADATA00_0
P4B
TIOB02_0
61
53
N6
IC12_1
ZIN0_1
MADATA01_0
P4C
TIOB03_0
IC13_1
62
54
M6
SCK7_1
AIN1_2
MADATA02_0
P4D
TIOB04_0
FRCK1_1
63
55
L6
SOT7_1
BIN1_2
MADATA03_0
P4E
TIOB05_0
INT06_2
64
56
K6
SIN7_1
ZIN1_2
MADATA04_0
P70
65
57
J6
TIOA04_2
MADATA05_0
Document Number: 002-04683 Rev.*C
Page 18 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
E
H
E
H
E
H
E
I
E
H
E
H
E
H
P71
INT13_2
66
58
N8
TIOB04_2
MADATA06_0
P72
SIN2_0
67
59
M8
INT14_2
AIN2_0
MADATA07_0
P73
SOT2_0
68
60
L8
INT15_2
BIN2_0
MADATA08_0
P74
SCK2_0
69
61
K8
ZIN2_0
MADATA09_0
P75
SIN3_0
70
62
P8
ADTG_8
INT07_1
MADATA10_0
P76
SOT3_0
71
63
J8
TIOA07_2
INT11_2
MADATA11_0
P77
SCK3_0
72
64
P9
TIOB07_2
INT12_2
MADATA12_0
Document Number: 002-04683 Rev.*C
Page 19 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
E
I
E
H
P78
AIN1_0
73
65
N9
TIOA15_0
MADATA13_0
P79
BIN1_0
74
66
M9
TIOB15_0
INT23_1
MADATA14_0
-
-
E1
VSS
-
-
-
G1
VSS
-
P7A
ZIN1_0
75
67
L9
E
H
E
H
E
H
E
H
E
H
E
H
INT24_1
MADATA15_0
P7B
76
-
K9
TIOB07_0
INT10_0
P7C
77
-
P10
TIOA07_0
INT11_0
P7D
TIOA14_1
78
-
N10
FRCK2_1
INT12_0
P7E
TIOB14_1
79
-
L10
IC21_1
INT24_0
P7F
TIOA15_1
80
-
K10
IC22_1
INT25_0
Document Number: 002-04683 Rev.*C
Page 20 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
PF0
TIOB15_1
81
-
M10
SIN1_2
*1
H
*1
H
*1
H
C
P
J
D
A
A
A
B
I
INT13_0
IC23_1
PF1
TIOA08_1
82
-
N11
SOT1_2
I
INT14_0
PF2
TIOB08_1
83
-
M11
SCK1_2
I
INT15_0
PE0
84
68
N13
MD1
85
69
N12
86
70
P12
MD0
PE2
X0
PE3
87
71
P13
X1
88
72
N14
VSS
-
89
73
M14
VCC
-
-
-
L7
VSS
-
-
-
K7
VSS
-
P10
90
74
M13
AN00
F
K
F
L
MCSX7_0
P11
AN01
SIN1_1
91
75
M12
INT02_1
FRCK0_2
MCSX6_0
Document Number: 002-04683 Rev.*C
Page 21 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
F
K
F
K
F
L
F
K
F
L
F
L
P12
AN02
92
76
L13
SOT1_1
IC00_2
MCSX5_0
P13
AN03
93
77
L12
SCK1_1
IC01_2
MCSX4_0
P14
AN04
SIN0_1
94
78
L11
INT03_1
IC02_2
MAD00_0
P15
AN05
95
79
K13
SOT0_1
IC03_2
MAD01_0
P16
AN06
96
80
K12
SCK0_1
INT20_1
MAD02_0
P17
AN07
97
81
K14
SIN2_2
INT04_1
MAD03_0
-
-
P7
VSS
-
-
-
P11
VSS
-
-
-
L14
VSS
-
Document Number: 002-04683 Rev.*C
Page 22 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
F
L
F
L
F
L
F
L
F
L
P18
AN08
98
82
K11
SOT2_2
INT21_1
MAD04_0
P19
AN09
99
83
J13
SCK2_2
INT22_1
MAD05_0
P1A
AN10
SIN4_1
100
84
J12
INT05_1
TIOA13_2
IC00_1
MAD06_0
P1B
AN11
SOT4_1
101
85
J11
INT25_1
TIOB13_2
IC01_1
MAD07_0
P1C
AN12
SCK4_1
102
86
J10
INT26_1
TIOA14_2
IC02_1
MAD08_0
Document Number: 002-04683 Rev.*C
Page 23 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
F
L
F
L
F
L
P1D
AN13
CTS4_1
103
87
J9
INT27_1
TIOB14_2
IC03_1
MAD09_0
P1E
AN14
RTS4_1
104
88
H10
INT28_1
TIOA15_2
DTTI0X_1
MAD10_0
P1F
AN15
ADTG_5
105
89
H9
INT29_1
TIOB15_2
FRCK0_1
MAD11_0
106
90
J14
AVCC
-
107
91
H14
AVRH
-
108
92
G14
AVSS
-
109
93
F14
VSS
-
PB0
AN16
110
-
H13
TIOA09_1
F
L
F
L
SIN7_2
INT16_0
PB1
AN17
111
-
H12
TIOB09_1
SOT7_2
INT17_0
Document Number: 002-04683 Rev.*C
Page 24 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
F
L
F
L
F
L
F
L
PB2
AN18
112
-
H11
TIOA10_1
SCK7_2
INT18_0
PB3
AN19
113
-
G13
TIOB10_1
INT19_0
PB4
AN20
114
-
G12
TIOA11_1
SIN0_2
INT20_0
PB5
AN21
TIOB11_1
115
-
G11
SOT0_2
INT21_0
AIN2_2
-
-
G7
VSS
-
-
-
J7
VSS
-
PB6
AN22
TIOA12_1
116
-
G10
F
L
F
L
F
K
SCK0_2
INT22_0
BIN2_2
PB7
AN23
117
-
G9
TIOB12_1
INT23_0
ZIN2_2
P29
118
94
F10
AN24
MAD12_0
Document Number: 002-04683 Rev.*C
Page 25 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
F
L
F
L
F
K
F
K
F
L
F
K
P28
AN25
ADTG_4
119
95
F11
INT09_0
RTO05_1
MAD13_0
P27
AN26
120
96
F12
INT02_2
RTO04_1
MAD14_0
P26
AN27
121
97
F13
SCK2_1
RTO03_1
MAD15_0
P25
AN28
122
98
E10
SOT2_1
RTO02_1
MAD16_0
P24
AN29
SIN2_1
123
99
E11
INT01_2
RTO01_1
MAD17_0
P23
AN30
124
100
E12
SCK0_0
TIOA07_1
RTO00_1
Document Number: 002-04683 Rev.*C
Page 26 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
F
K
E
H
E
H
*1
J
P22
AN31
125
101
E13
SOT0_0
TIOB07_1
ZIN1_1
P21
SIN0_0
126
102
D12
INT06_1
BIN1_1
P20
INT05_0
127
103
D13
CROUT_0
AIN1_1
MAD18_0
PF6
128
104
C13
FRCK2_0
I
NMIX
129
105
E14
VCC
-
130
106
D14
P82
H
O
131
107
C14
P83
H
O
132
108
B14
VSS
-
133
109
A13
VCC
-
134
110
B13
P00
E
E
E
E
E
E
E
E
E
E
TRSTX
P01
135
111
A12
TCK
SWCLK
P02
136
112
C12
TDI
P03
137
113
B12
TMS
SWDIO
P04
138
114
B11
TDO
SWO
Document Number: 002-04683 Rev.*C
Page 27 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
E
H
P90
TIOB08_0
139
-
C11
RTO20_1
INT30_0
MAD19_0
-
-
A8
VSS
-
P91
TIOB09_0
140
-
D11
RTO21_1
E
H
E
I
E
I
E
H
E
H
INT31_0
MAD20_0
P92
TIOB10_0
141
-
B10
RTO22_1
SIN5_1
MAD21_0
P93
TIOB11_0
142
-
C10
RTO23_1
SOT5_1
MAD22_0
P94
TIOB12_0
RTO24_1
143
-
D10
SCK5_1
INT26_0
MAD23_0
P95
TIOB13_0
144
-
B9
RTO25_1
INT27_0
MAD24_0
145
115
C9
PC0
K
Q
146
116
B8
PC1
K
Q
147
117
D9
PC2
K
Q
Document Number: 002-04683 Rev.*C
Page 28 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
148
118
E9
Pin Name
I/O circuit
type
Pin state
type
K
Q
K
Q
K
Q
PC3
TIOA06_1
PC4
149
119
F9
TIOA08_2
PC5
150
120
C8
TIOA10_2
-
-
A5
151
121
D8
VSS
-
PC6
K
Q
L
Q
TIOA14_0
PC7
152
122
E8
CROUT_1
153
123
A10
PC8
K
Q
154
124
F8
PC9
K
Q
155
125
B7
PCA
K
Q
156
126
A9
VCC
-
157
127
A11
VSS
-
158
128
A7
PCB
L
Q
159
129
C7
PCC
K
Q
160
130
A6
PCD
K
Q
L
Q
L
Q
L
R
L
R
PCE
161
131
D7
RTS4_0
TIOB06_1
PCF
162
132
E7
CTS4_0
TIOB08_2
PD0
SCK4_0
163
133
F7
TIOB10_2
INT30_1
PD1
SOT4_0
164
134
B6
TIOB14_0
INT31_1
-
-
N7
VSS
-
-
-
G8
VSS
-
-
-
H7
VSS
-
-
-
H8
VSS
-
Document Number: 002-04683 Rev.*C
Page 29 of 132
MB9B110T Series
Pin No
LQFP-176
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
L
R
L
Q
E
Q
E
I
E
H
*1
H
*1
H
*1
H
PD2
SIN4_0
165
135
C6
TIOA03_2
INT00_2
PD3
166
136
D6
TIOB03_2
P62
167
137
E6
SCK5_0
ADTG_3
P61
168
138
B5
SOT5_0
TIOB02_2
P60
SIN5_0
169
139
C5
TIOA02_2
INT15_1
PF3
TIOA06_0
170
-
B4
SIN6_2
I
INT06_0
AIN2_1
PF4
TIOB06_0
171
-
C4
SOT6_2
I
INT07_0
BIN2_1
PF5
SCK6_2
172
140
B3
INT08_0
I
ZIN2_1
Document Number: 002-04683 Rev.*C
Page 30 of 132
MB9B110T Series
Pin No
Pin Name
I/O circuit
type
Pin state
type
LQFP-176
LQFP-144
BGA-192
173
141
A4
VCC
174
142
A3
P80
H
O
175
143
A2
P81
H
O
176
144
B1
VSS
-
-
-
M7
VSS
-
-
*1: 5 V tolerant I/O
Document Number: 002-04683 Rev.*C
Page 31 of 132
MB9B110T Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, the same function is provided on the same channel. Use the extended port function register (EPFR) to select the pin.
Pin No
Module
Pin name
ADC
Function
LQFP-176
LQFP-144
BGA-192
ADTG_0
10
10
E2
ADTG_1
18
18
F5
ADTG_2
37
29
K2
ADTG_3
167
137
E6
119
95
F11
ADTG_5
105
89
H9
ADTG_6
31
-
H6
ADTG_7
49
41
L4
ADTG_8
70
62
P8
ADTG_4
Document Number: 002-04683 Rev.*C
A/D converter external trigger input pin
Page 32 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
AN00
90
74
M13
AN01
91
75
M12
AN02
92
76
L13
AN03
93
77
L12
AN04
94
78
L11
AN05
95
79
K13
AN06
96
80
K12
AN07
97
81
K14
AN08
98
82
K11
AN09
99
83
J13
AN10
100
84
J12
AN11
101
85
J11
AN12
102
86
J10
AN13
103
87
J9
AN14
104
88
H10
AN15
A/D converter analog input pin
105
89
H9
AN16
ANxx describes ADC ch.xx
110
-
H13
AN17
111
-
H12
AN18
112
-
H11
AN19
113
-
G13
AN20
114
-
G12
AN21
115
-
G11
AN22
116
-
G10
AN23
117
-
G9
AN24
118
94
F10
AN25
119
95
F11
AN26
120
96
F12
AN27
121
97
F13
AN28
122
98
E10
AN29
123
99
E11
AN30
124
100
E12
AN31
125
101
E13
ADC
Document Number: 002-04683 Rev.*C
Page 33 of 132
MB9B110T Series
Pin No
Module
Pin name
Base Timer 0
TIOA0_0
LQFP-176
LQFP-144
BGA-192
46
38
N2
38
30
K3
TIOA0_2
11
11
E3
TIOB0_0
59
51
L5
28
-
H3
TIOB0_2
12
12
E4
TIOA1_0
47
39
N3
39
31
K4
TIOA1_2
16
16
F3
TIOB1_0
60
52
K5
29
-
H4
TIOB1_2
17
17
F4
TIOA2_0
48
40
M3
40
32
L1
TIOA2_2
169
139
C5
TIOB2_0
61
53
N6
30
-
H5
TIOB2_2
168
138
B5
TIOA3_0
49
41
L4
41
33
L2
TIOA3_2
165
135
C6
TIOB3_0
62
54
M6
31
-
H6
TIOB3_2
166
136
D6
TIOA4_0
50
42
M4
42
34
L3
TIOA4_2
65
57
J6
TIOB4_0
63
55
L6
32
-
J5
66
58
N8
TIOA0_1
TIOB0_1
Base Timer 1
TIOA1_1
TIOB1_1
Base Timer 2
TIOA2_1
TIOB2_1
Base Timer 3
TIOA3_1
TIOB3_1
Base Timer 4
Function
TIOA4_1
TIOB4_1
TIOB4_2
Document Number: 002-04683 Rev.*C
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Page 34 of 132
MB9B110T Series
Pin No
Module
Pin name
Base Timer 5
TIOA5_0
LQFP-176
LQFP-144
BGA-192
51
43
N4
43
35
M2
TIOA5_2
8
8
D3
TIOB5_0
64
56
K6
33
-
J4
TIOB5_2
9
9
D4
TIOA6_0
170
-
B4
148
118
E9
TIOA6_2
25
-
H1
TIOB6_0
171
-
C4
161
131
D7
TIOB6_2
26
-
H2
TIOA07_0
77
-
P10
124
100
E12
TIOA07_2
71
63
J8
TIOB07_0
76
-
K9
125
101
E13
TIOB07_2
72
64
P9
TIOA08_0
2
2
B2
82
-
N11
TIOA08_2
149
119
F9
TIOB08_0
139
-
C11
83
-
M11
TIOB08_2
162
132
E7
TIOA09_0
3
3
C2
110
-
H13
TIOA09_2
19
19
F6
TIOB09_0
140
-
D11
111
-
H12
20
20
G2
TIOA5_1
TIOB5_1
Base Timer 6
TIOA6_1
TIOB6_1
Base Timer 7
TIOA07_1
TIOB07_1
Base Timer 8
TIOA08_1
TIOB08_1
Base Timer 9
Function
TIOA09_1
TIOB09_1
TIOB09_2
Document Number: 002-04683 Rev.*C
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Base timer ch.8 TIOA pin
Base timer ch.8 TIOB pin
Base timer ch.9 TIOA pin
Base timer ch.9 TIOB pin
Page 35 of 132
MB9B110T Series
Pin No
Module
Pin name
Base Timer
10
TIOA10_0
LQFP-176
LQFP-144
BGA-192
4
4
C3
112
-
H11
TIOA10_2
150
120
C8
TIOB10_0
141
-
B10
113
-
G13
TIOB10_2
163
133
F7
TIOA11_0
5
5
D5
114
-
G12
TIOA11_2
21
21
G3
TIOB11_0
142
-
C10
115
-
G11
TIOB11_2
22
22
G4
TIOA12_0
6
6
D2
116
-
G10
TIOA12_2
34
26
J3
TIOB12_0
143
-
D10
117
-
G9
TIOB12_2
35
27
J2
TIOA13_0
7
7
D1
23
23
G5
TIOA13_2
100
84
J12
TIOB13_0
144
-
B9
24
24
G6
TIOB13_2
101
85
J11
TIOA14_0
151
121
D8
78
-
N10
TIOA14_2
102
86
J10
TIOB14_0
164
134
B6
79
-
L10
103
87
J9
TIOA10_1
TIOB10_1
Base Timer
11
TIOA11_1
TIOB11_1
Base Timer
12
TIOA12_1
TIOB12_1
Base Timer
13
TIOA13_1
TIOB13_1
Base Timer
14
Function
TIOA14_1
TIOB14_1
TIOB14_2
Document Number: 002-04683 Rev.*C
Base timer ch.10 TIOA pin
Base timer ch.10 TIOB pin
Base timer ch.11 TIOA pin
Base timer ch.11 TIOB pin
Base timer ch.12 TIOA pin
Base timer ch.12 TIOB pin
Base timer ch.13 TIOA pin
Base timer ch.13 TIOB pin
Base timer ch.14 TIOA pin
Base timer ch.14 TIOB pin
Page 36 of 132
MB9B110T Series
Pin No
Module
Pin name
Base Timer
15
TIOA15_0
Function
LQFP-176
LQFP-144
BGA-192
73
65
N9
80
-
K10
TIOA15_2
104
88
H10
TIOB15_0
74
66
M9
81
-
M10
105
89
H9
TIOA15_1
Base timer ch.15 TIOA pin
TIOB15_1
Base timer ch.15 TIOB pin
TIOB15_2
Debugger
SWCLK
Serial wire debug interface clock input
135
111
A12
SWDIO
Serial wire debug interface data input / output
137
113
B12
SWO
Serial wire viewer output
138
114
B11
TCK
JTAG test clock input
135
111
A12
TDI
JTAG test data input
136
112
C12
TDO
JTAG debug data output
138
114
B11
TMS
JTAG test mode state input/output
137
113
B12
TRACECLK
Trace CLK output of ETM
12
12
E4
8
8
D3
9
9
D4
TRACED2
10
10
E2
TRACED3
11
11
E3
134
110
B13
TRACED0
TRACED1
Trace data output of ETM
TRSTX
Document Number: 002-04683 Rev.*C
JTAG test reset input
Page 37 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
MAD00_0
94
78
L11
MAD01_0
95
79
K13
MAD02_0
96
80
K12
MAD03_0
97
81
K14
MAD04_0
98
82
K11
MAD05_0
99
83
J13
MAD06_0
100
84
J12
MAD07_0
101
85
J11
MAD08_0
102
86
J10
MAD09_0
103
87
J9
MAD10_0
104
88
H10
MAD11_0
105
89
H9
118
94
F10
MAD13_0
119
95
F11
MAD14_0
120
96
F12
MAD15_0
121
97
F13
MAD16_0
122
98
E10
MAD17_0
123
99
E11
MAD18_0
127
103
D13
MAD19_0
139
-
C11
MAD20_0
140
-
D11
MAD21_0
141
-
B10
MAD22_0
142
-
C10
MAD23_0
143
-
D10
MAD24_0
144
-
B9
MCSX0_0
23
23
G5
MCSX1_0
24
24
G6
MCSX2_0
34
26
J3
35
27
J2
MCSX4_0
93
77
L12
MCSX5_0
92
76
L13
MCSX6_0
91
75
M12
MCSX7_0
90
74
M13
MAD12_0
External
Bus
External bus interface address bus
MCSX3_0
External bus interface chip select output pin
Document Number: 002-04683 Rev.*C
Page 38 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
MDQM0_0
LQFP-176
LQFP-144
BGA-192
15
15
F2
16
16
F3
External bus interface byte mask signal output
MDQM1_0
External
Bus
MOEX_0
External bus interface read enable signal for
SRAM
13
13
E5
MWEX_0
External bus interface write enable signal for
SRAM
14
14
F1
MNALE_0
External bus interface ALE signal to control
NAND Flash memory output pin
19
19
F6
MNCLE_0
External bus interface CLE signal to control
NAND Flash memory output pin
20
20
G2
MNREX_0
External bus interface read enable signal to
control NAND Flash memory
22
22
G4
MNWEX_0
External bus interface write enable signal to
control NAND Flash memory
21
21
G3
MADATA00_0
60
52
K5
MADATA01_0
61
53
N6
MADATA02_0
62
54
M6
MADATA03_0
63
55
L6
MADATA04_0
64
56
K6
MADATA05_0
65
57
J6
MADATA06_0
66
58
N8
MADATA07_0
External bus interface data bus
67
59
M8
MADATA08_0
(Multiplexed bus to address output for
multiplex)
68
60
L8
MADATA09_0
69
61
K8
MADATA10_0
70
62
P8
MADATA11_0
71
63
J8
MADATA12_0
72
64
P9
MADATA13_0
73
65
N9
MADATA14_0
74
66
M9
MADATA15_0
75
67
L9
MALE_0
Address Latch enable signal for multiplex
17
17
F4
MRDY_0
External RDY input signal
18
18
F5
MCLKOUT_0
External bus clock output
36
28
K1
Document Number: 002-04683 Rev.*C
Page 39 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
13
13
E5
8
8
D3
INT00_2
165
135
C6
INT01_0
14
14
F1
9
9
D4
INT01_2
123
99
E11
INT02_0
15
15
F2
91
75
M12
INT02_2
120
96
F12
INT03_0
6
6
D2
94
78
L11
INT03_2
28
-
H3
INT04_0
31
-
H6
97
81
K14
INT04_2
29
-
H4
INT05_0
127
103
D13
100
84
J12
INT05_2
30
-
H5
INT06_0
170
-
B4
126
102
D12
INT06_2
64
56
K6
INT07_0
171
-
C4
70
62
P8
INT07_2
16
16
F3
INT08_0
172
140
B3
33
-
J4
INT08_2
19
19
F6
INT09_0
119
95
F11
34
26
J3
22
22
G4
76
-
K9
35
27
J2
7
7
D1
INT00_0
INT00_1
INT01_1
INT02_1
INT03_1
INT04_1
External
Interrupt
INT05_1
INT06_1
INT07_1
INT08_1
INT09_1
External interrupt request 00 input pin
External interrupt request 01 input pin
External interrupt request 02 input pin
External interrupt request 03 input pin
External interrupt request 04 input pin
External interrupt request 05 input pin
External interrupt request 06 input pin
External interrupt request 07 input pin
External interrupt request 08 input pin
External interrupt request 09 input pin
INT09_2
INT10_0
INT10_1
INT10_2
Document Number: 002-04683 Rev.*C
External interrupt request 10 input pin
Page 40 of 132
MB9B110T Series
Pin No
Module
Pin name
External
INT11_0
Interrupt
INT11_1
Function
LQFP-176
LQFP-144
BGA-192
77
-
P10
36
28
K1
INT11_2
71
63
J8
INT12_0
78
-
N10
46
38
N2
INT12_2
72
64
P9
INT13_0
81
-
M10
47
39
N3
INT13_2
66
58
N8
INT14_0
82
-
N11
58
50
M5
INT14_2
67
59
M8
INT15_0
83
-
M11
169
139
C5
68
60
L8
110
-
H13
20
20
G2
111
-
H12
21
21
G3
112
-
H11
23
23
G5
113
-
G13
24
24
G6
114
-
G12
96
80
K12
115
-
G11
98
82
K11
116
-
G10
99
83
J13
117
-
G9
74
66
M9
79
-
L10
75
67
L9
80
-
K10
101
85
J11
INT12_1
INT13_1
INT14_1
INT15_1
External interrupt request 11 input pin
External interrupt request 12 input pin
External interrupt request 13 input pin
External interrupt request 14 input pin
External interrupt request 15 input pin
INT15_2
INT16_0
External interrupt request 16 input pin
INT16_1
INT17_0
External interrupt request 17 input pin
INT17_1
INT18_0
External interrupt request 18 input pin
INT18_1
INT19_0
External interrupt request 19 input pin
INT19_1
INT20_0
External interrupt request 20 input pin
INT20_1
INT21_0
External interrupt request 21 input pin
INT21_1
INT22_0
External interrupt request 22 input pin
INT22_1
INT23_0
External interrupt request 23 input pin
INT23_1
INT24_0
External interrupt request 24 input pin
INT24_1
INT25_0
External interrupt request 25 input pin
INT25_1
Document Number: 002-04683 Rev.*C
Page 41 of 132
MB9B110T Series
Pin No
Module
Pin name
External
Interrupt
INT26_0
Function
LQFP-176
LQFP-144
BGA-192
143
-
D10
102
86
J10
144
-
B9
103
87
J9
25
-
H1
104
88
H10
26
-
H2
105
89
H9
139
-
C11
163
133
F7
140
-
D11
164
134
B6
128
104
C13
P00
134
110
B13
P01
135
111
A12
P02
136
112
C12
P03
137
113
B12
138
114
B11
P05
8
8
D3
P06
9
9
D4
P07
10
10
E2
P08
11
11
E3
P09
12
12
E4
External interrupt request 26 input pin
INT26_1
INT27_0
External interrupt request 27 input pin
INT27_1
INT28_0
External interrupt request 28 input pin
INT28_1
INT29_0
External interrupt request 29 input pin
INT29_1
INT30_0
External interrupt request 30 input pin
INT30_1
INT31_0
External interrupt request 31 input pin
INT31_1
NMIX
GPIO
Non-Maskable Interrupt input
P04
General-purpose I/O port 0
Document Number: 002-04683 Rev.*C
Page 42 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
P10
90
74
M13
P11
91
75
M12
P12
92
76
L13
P13
93
77
L12
P14
94
78
L11
P15
95
79
K13
P16
96
80
K12
97
81
K14
P18
98
82
K11
P19
99
83
J13
P1A
100
84
J12
P1B
101
85
J11
P1C
102
86
J10
P1D
103
87
J9
P1E
104
88
H10
P1F
105
89
H9
P20
127
103
D13
P21
126
102
D12
P22
125
101
E13
P23
124
100
E12
123
99
E11
P25
122
98
E10
P26
121
97
F13
P27
120
96
F12
P28
119
95
F11
P29
118
94
F10
P17
General-purpose I/O port 1
GPIO
P24
General-purpose I/O port 2
Document Number: 002-04683 Rev.*C
Page 43 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
P30
28
-
H3
P31
29
-
H4
P32
30
-
H5
P33
31
-
H6
P34
32
-
J5
P35
33
-
J4
P36
34
26
J3
35
27
J2
P38
36
28
K1
P39
37
29
K2
P3A
38
30
K3
P3B
39
31
K4
P3C
40
32
L1
P3D
41
33
L2
P3E
42
34
L3
P3F
43
35
M2
P40
46
38
N2
P41
47
39
N3
P42
48
40
M3
P43
49
41
L4
P44
50
42
M4
P45
51
43
N4
P46
55
47
P5
56
48
P6
P48
58
50
M5
P49
59
51
L5
P4A
60
52
K5
P4B
61
53
N6
P4C
62
54
M6
P4D
63
55
L6
P4E
64
56
K6
P37
General-purpose I/O port 3
GPIO
P47
Document Number: 002-04683 Rev.*C
General-purpose I/O port 4
Page 44 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
P50
13
13
E5
P51
14
14
F1
P52
15
15
F2
P53
16
16
F3
P54
17
17
F4
P55
18
18
F5
19
19
F6
P57
20
20
G2
P58
21
21
G3
P59
22
22
G4
P5A
23
23
G5
P5B
24
24
G6
P5C
25
-
H1
P5D
26
-
H2
P60
169
139
C5
168
138
B5
P62
167
137
E6
P70
65
57
J6
P71
66
58
N8
P72
67
59
M8
P73
68
60
L8
P74
69
61
K8
P75
70
62
P8
P76
71
63
J8
72
64
P9
P78
73
65
N9
P79
74
66
M9
P7A
75
67
L9
P7B
76
-
K9
P7C
77
-
P10
P7D
78
-
N10
P7E
79
-
L10
P7F
80
-
K10
P56
General-purpose I/O port 5
P61
GPIO
General-purpose I/O port 6
P77
General-purpose I/O port 7
Document Number: 002-04683 Rev.*C
Page 45 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
174
142
A3
175
143
A2
P82
130
106
D14
P83
131
107
C14
P90
139
-
C11
P91
140
-
D11
141
-
B10
P93
142
-
C10
P94
143
-
D10
P95
144
-
B9
PA0
2
2
B2
PA1
3
3
C2
4
4
C3
PA3
5
5
D5
PA4
6
6
D2
PA5
7
7
D1
PB0
110
-
H13
PB1
111
-
H12
PB2
112
-
H11
113
-
G13
PB4
114
-
G12
PB5
115
-
G11
PB6
116
-
G10
PB7
117
-
G9
P80
P81
General-purpose I/O port 8
P92
General-purpose I/O port 9
GPIO
PA2
General-purpose I/O port A
PB3
General-purpose I/O port B
Document Number: 002-04683 Rev.*C
Page 46 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
PC0
145
115
C9
PC1
146
116
B8
PC2
147
117
D9
PC3
148
118
E9
PC4
149
119
F9
PC5
150
120
C8
PC6
151
121
D8
152
122
E8
PC8
153
123
A10
PC9
154
124
F8
PCA
155
125
B7
PCB
158
128
A7
PCC
159
129
C7
PCD
160
130
A6
PCE
161
131
D7
PCF
162
132
E7
PD0
163
133
F7
164
134
B6
PD2
165
135
C6
PD3
166
136
D6
PE0
84
68
N13
86
70
P12
PE3
87
71
P13
PF0
81
-
M10
PF1
82
-
N11
83
-
M11
170
-
B4
PF4
171
-
C4
PF5
172
140
B3
PF6
128
104
C13
PC7
General-purpose I/O port C
GPIO
PD1
General-purpose I/O port D
PE2
General-purpose I/O port E
PF2
PF3
Document Number: 002-04683 Rev.*C
General-purpose I/O port F
*1
Page 47 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
SIN0_0
SIN0_1
Multi-function serial interface ch.0 input pin
SIN0_2
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
Multi-Function
Serial 0
LQFP-176
LQFP-144
BGA-192
126
102
D12
94
78
L11
114
-
G12
125
101
E13
95
79
K13
115
-
G11
124
100
E12
96
80
K12
116
-
G10
19
19
F6
91
75
M12
81
-
M10
20
20
G2
92
76
L13
82
-
N11
21
21
G3
93
77
L12
83
-
M11
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA0 when it is used in an I2C (operation
mode 4).
SOT0_2
(SDA0_2)
SCK0_0
(SCL0_0)
Multi-function serial interface ch.0 clock
SCK0_1
(SCL0_1)
This pin operates as SCK0 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL0 when it is used in an I2C
SCK0_2
(operation mode 4).
I/O pin.
(SCL0_2)
Multi-Function
Serial 1
SIN1_0
SIN1_1
Multi-function serial interface ch.1 input pin
SIN1_2
SOT1_0
(SDA1_0)
SOT1_1
(SDA1_1)
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA1 when it is used in an I2C
(operation mode 4).
SOT1_2
(SDA1_2)
SCK1_0
(SCL1_0)
SCK1_1
(SCL1_1)
SCK1_2
Multi-function serial interface ch.1 clock
I/O pin.
This pin operates as SCK1 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL1 when it is used in an I2C (operation
mode 4).
(SCL1_2)
Document Number: 002-04683 Rev.*C
Page 48 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
SIN2_0
SIN2_1
Multi-function serial interface ch.2 input pin
SIN2_2
SOT2_0
(SDA2_0)
Multi-function serial interface ch.2 output pin.
SOT2_1
This pin operates as SOT2 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA2 when it is used in an I2C
(operation mode 4).
(SDA2_1)
Multi-Function
Serial 2
SOT2_2
(SDA2_2)
SCK2_0
Multi-function serial interface ch.2 clock
I/O pin.
(SCL2_0)
SCK2_1
(SCL2_1)
SCK2_2
This pin operates as SCK2 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL2 when it is used in an I2C
(operation mode 4).
(SCL2_2)
SIN3_0
SIN3_1
Multi-function serial interface ch.3 input pin
SIN3_2
SOT3_0
Multi-Function
Serial 3
(SDA3_0)
Multi-function serial interface ch.3 output pin.
SOT3_1
This pin operates as SOT3 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA3 when it is used in an I2C
(operation mode 4).
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_0
Multi-function serial interface ch.3 clock
I/O pin.
(SCL3_0)
SCK3_1
(SCL3_1)
This pin operates as SCK3 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL3 when it is used in an I2C
SCK3_2
(SCL3_2)
Document Number: 002-04683 Rev.*C
(operation mode 4).
LQFP-176
LQFP-144
BGA-192
67
59
M8
123
99
E11
97
81
K14
68
60
L8
122
98
E10
98
82
K11
69
61
K8
121
97
F13
99
83
J13
70
62
P8
13
13
E5
58
50
M5
71
63
J8
14
14
F1
59
51
L5
72
64
P9
15
15
F2
60
52
K5
Page 49 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
LQFP-176
LQFP-144
BGA-192
165
135
C6
100
84
J12
8
8
D3
164
134
B6
101
85
J11
9
9
D4
163
133
F7
102
86
J10
10
10
E2
161
131
D7
104
88
H10
12
12
E4
162
132
E7
103
87
J9
CTS4_2
11
11
E3
SIN5_0
169
139
C5
141
-
B10
34
26
J3
168
138
B5
142
-
C10
35
27
J2
167
137
E6
143
-
D10
36
28
K1
SIN4_0
SIN4_1
Multi-function serial interface ch.4 input pin
SIN4_2
SOT4_0
(SDA4_0)
Multi-function serial interface ch.4 output pin.
SOT4_1
(SDA4_1)
This pin operates as SOT4 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA4 when it is used in an I2C
SOT4_2
(operation mode 4).
(SDA4_2)
SCK4_0
Multi-Function
Serial 4
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
Multi-function serial interface ch.4 clock I/O
pin.
This pin operates as SCK4 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL4 when it is used in an I2C
(operation mode 4).
(SCL4_2)
RTS4_0
RTS4_1
Multi-function serial interface ch.4 RTS output
pin
RTS4_2
CTS4_0
CTS4_1
SIN5_1
Multi-function serial interface ch.4 CTS input
pin
Multi-function serial interface ch.5 input pin
SIN5_2
SOT5_0
(SDA5_0)
SOT5_1
(SDA5_1)
Multi-Function
Serial 5
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SDA5 when it is used in an I2C
(operation mode 4).
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
SCK5_1
(SCL5_1)
SCK5_2
(SCL5_2)
Document Number: 002-04683 Rev.*C
Multi-function serial interface ch.5 clock
I/O pin.
This pin operates as SCK5 when it is used in
a UART/CSIO (operation modes 0 to 2) and
as SCL5 when it is used in an I2C
(operation mode 4).
Page 50 of 132
MB9B110T Series
Pin No
Module
Pin name
Function
SIN6_0
SIN6_1
Multi-function serial interface ch.6 input pin
SIN6_2
SOT6_0
(SDA6_0)
Multi-function serial interface ch.6 output pin.
SOT6_1
This pin operates as SOT6 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA6 when it is used in an I2C
(operation mode 4).
(SDA6_1)
Multi-Function
Serial 6
SOT6_2
(SDA6_2)
SCK6_0
(SCL6_0)
Multi-function serial interface ch.6 clock I/O pin.
SCK6_1
(SCL6_1)
This pin operates as SCK6 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL6 when it is used in an I2C
SCK6_2
(operation mode 4).
(SCL6_2)
SIN7_0
SIN7_1
Multi-function serial interface ch.7 input pin
SIN7_2
SOT7_0
(SDA7_0)
LQFP-176 LQFP-144
BGA-192
16
16
F3
31
-
H6
170
-
B4
17
17
F4
30
-
H5
171
-
C4
18
18
F5
29
-
H4
172
140
B3
22
22
G4
64
56
K6
110
-
H13
23
23
G5
63
55
L6
111
-
H12
24
24
G6
62
54
M6
112
-
H11
Multi-function serial interface ch.7 output pin.
SOT7_1
(SDA7_1)
Multi-Function
Serial 7
This pin operates as SOT7 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA7 when it is used in an I2C
(operation mode 4).
SOT7_2
(SDA7_2)
SCK7_0
(SCL7_0)
Multi-function serial interface ch.7 clock I/O pin.
SCK7_1
(SCL7_1)
SCK7_2
(SCL7_2)
Document Number: 002-04683 Rev.*C
This pin operates as SCK7 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL7 when it is used in an I2C
(operation mode 4).
Page 51 of 132
MB9B110T Series
Pin No
Module
Pin name
DTTI0X_0
Function
BGA-192
37
29
K2
104
88
H10
32
-
J5
105
89
H9
FRCK0_2
91
75
M12
IC00_0
36
28
K1
IC00_1
100
84
J12
IC00_2
92
76
L13
IC01_0
35
27
J2
IC01_1
101
85
J11
DTTI0X_1
Input signal of waveform generator to control outputs
RTO00 to RTO05 of multi-function timer 0.
FRCK0_0
FRCK0_1
Multi-Function
Timer 0
LQFP-1
LQFP-144
76
16-bit free-run timer ch.0 external clock input pin
IC01_2
16-bit input capture input pin of multi-function timer 0
93
77
L12
IC02_0
ICxx describes channel number.
34
26
J3
IC02_1
102
86
J10
IC02_2
94
78
L11
IC03_0
33
-
J4
IC03_1
103
87
J9
IC03_2
95
79
K13
RTO00_0 (PPG00_0)
Waveform generator output of multi-function timer 0
38
30
K3
RTO00_1 (PPG00_1)
This pin operates as PPG00 when it is used in PPG0
output modes.
124
100
E12
RTO01_0 (PPG00_0)
Waveform generator output of multi-function timer 0
39
31
K4
RTO01_1 (PPG00_1)
This pin operates as PPG00 when it is used in PPG0
output modes.
123
99
E11
RTO02_0 (PPG02_0)
Waveform generator output of multi-function timer 0
40
32
L1
RTO02_1 (PPG02_1)
This pin operates as PPG02 when it is used in PPG0
output modes.
122
98
E10
RTO03_0 (PPG02_0)
Waveform generator output of multi-function timer 0
41
33
L2
RTO03_1 (PPG02_1)
This pin operates as PPG02 when it is used in PPG0
output modes.
121
97
F13
RTO04_0 (PPG04_0)
Waveform generator output of multi-function timer 0
42
34
L3
RTO04_1 (PPG04_1)
This pin operates as PPG04 when it is used in PPG0
output modes.
120
96
F12
RTO05_0 (PPG04_0)
Waveform generator output of multi-function timer 0
43
35
M2
RTO05_1 (PPG04_1)
This pin operates as PPG04 when it is used in PPG0
output modes.
119
95
F11
Document Number: 002-04683 Rev.*C
Page 52 of 132
MB9B110T Series
Pin No
Module
Multi-Function
Timer 1
Pin name
Function
LQFP-176
LQFP-144
BGA-192
19
19
F6
58
50
M5
2
63
3
59
4
60
5
61
6
62
2
55
3
51
4
52
5
53
6
54
B2
L6
C2
L5
C3
K5
D5
N6
D2
M6
Waveform generator output of multi-function
timer 1.
This pin operates as PPG10 when it is used
in PPG1 output modes.
13
13
E5
46
38
N2
Waveform generator output of multi-function
timer 1.
This pin operates as PPG10 when it is used
in PPG1 output modes.
14
14
F1
47
39
N3
Waveform generator output of multi-function
timer 1.
This pin operates as PPG12 when it is used
in PPG1 output modes.
15
15
F2
48
40
M3
Waveform generator output of multi-function
timer 1.
This pin operates as PPG12 when it is used
in PPG1 output modes.
16
16
F3
49
41
L4
17
17
F4
RTO14_1
(PPG14_1)
Waveform generator output of multi-function
timer 1.
This pin operates as PPG14 when it is used
in PPG1 output modes.
50
42
M4
RTO15_0
(PPG14_0)
RTO15_1
(PPG14_1)
Waveform generator output of multi-function
timer 1.
This pin operates as PPG14 when it is used
in PPG1 output modes.
18
18
F5
51
43
N4
DTTI1X_0
DTTI1X_1
FRCK1_0
FRCK1_1
IC10_0
IC10_1
IC11_0
IC11_1
IC12_0
IC12_1
IC13_0
IC13_1
RTO10_0
(PPG10_0)
RTO10_1
(PPG10_1)
RTO11_0
(PPG10_0)
RTO11_1
(PPG10_1)
RTO12_0
(PPG12_0)
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
RTO13_1
(PPG12_1)
RTO14_0
(PPG14_0)
Document Number: 002-04683 Rev.*C
Input signal of waveform generator to
control outputs RTO10 to RTO15 of
multi-function timer 1.
16-bit free-run timer ch.1 external clock
input pin
16-bit input capture input pin of
multi-function timer 1.
ICxx describes channel number
Page 53 of 132
MB9B110T Series
Pin No
Module
Pin name
Multi-Function
Timer 2
DTTI2X_0
Function
LQFP-176
LQFP-144
BGA-192
12
12
E4
26
-
H2
128
104
C13
78
-
N10
IC20_0
13
13
E5
IC20_1
25
-
H1
DTTI2X_1
FRCK2_0
FRCK2_1
Input signal of waveform generator to
control outputs RTO20 to RTO25 of
multi-function timer 2.
16-bit free-run timer ch.2 external clock
input pin
IC21_0
14
14
F1
IC21_1
16-bit input capture input pin of
multi-function timer 2.
79
-
L10
IC22_0
ICxx describes channel number.
15
15
F2
IC22_1
80
-
K10
IC23_0
16
16
F3
IC23_1
81
-
M10
RTO20_0
(PPG20_0)
Waveform generator output of
multi-function timer 2.
2
2
B2
RTO20_1
This pin operates as PPG20 when it is
used in PPG2 output modes.
139
-
C11
(PPG20_0)
Waveform generator output of
multi-function timer 2.
3
3
C2
RTO21_1
This pin operates as PPG20 when it is
used in PPG2 output modes.
140
-
D11
(PPG22_0)
Waveform generator output of
multi-function timer 2.
4
4
C3
RTO22_1
This pin operates as PPG22 when it is
used in PPG2 output modes.
141
-
B10
(PPG22_0)
Waveform generator output of
multi-function timer 2.
5
5
D5
RTO23_1
This pin operates as PPG22 when it is
used in PPG2 output modes.
142
-
C10
6
6
D2
(PPG20_1)
RTO21_0
(PPG20_1)
RTO22_0
(PPG22_1)
RTO23_0
(PPG22_1)
RTO24_0
(PPG24_0)
Waveform generator output of
multi-function timer 2.
RTO24_1
This pin operates as PPG24 when it is
used in PPG2 output modes.
143
-
D10
(PPG24_0)
Waveform generator output of
multi-function timer 2.
7
7
D1
RTO25_1
This pin operates as PPG24 when it is
used in PPG2 output modes.
144
-
B9
(PPG24_1)
RTO25_0
(PPG24_1)
Document Number: 002-04683 Rev.*C
Page 54 of 132
MB9B110T Series
Pin No
Module
Pin name
Quadrature
Position/
Revolution
Counter
0
AIN0_0
LQFP-176
28
LQFP-144
-
BGA-192
H3
59
51
L5
AIN0_2
13
13
E5
BIN0_0
29
-
H4
60
52
K5
BIN0_2
14
14
F1
ZIN0_0
30
-
H5
61
53
N6
ZIN0_2
15
15
F2
AIN1_0
73
65
N9
127
103
D13
AIN1_2
62
54
M6
BIN1_0
74
66
M9
126
102
D12
BIN1_2
63
55
L6
ZIN1_0
75
67
L9
125
101
E13
ZIN1_2
64
56
K6
AIN2_0
67
59
M8
170
-
B4
AIN2_2
115
-
G11
BIN2_0
68
60
L8
171
-
C4
BIN2_2
116
-
G10
ZIN2_0
69
61
K8
172
140
B3
117
-
G9
AIN0_1
BIN0_1
ZIN0_1
Quadrature
Position/
Revolution
Counter
1
AIN1_1
BIN1_1
ZIN1_1
Quadrature
Position/
Revolution
Counter
2
Function
AIN2_1
BIN2_1
ZIN2_1
QPRC ch.0 AIN input pin
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
QPRC ch.2 AIN input pin
QPRC ch.2 BIN input pin
QPRC ch.2 ZIN input pin
ZIN2_2
Reset
INITX
External Reset Input. A reset is valid when
INITX="L".
57
49
N5
MD0
Mode 0 Pin.
During normal operation, MD0="L" must
be input. During serial programming to
Flash memory, MD0="H" must be input.
85
69
N12
MD1
Mode 1 Pin.
During serial programming to Flash
memory, MD1="L" must be input.
84
68
N13
Mode
Document Number: 002-04683 Rev.*C
Page 55 of 132
MB9B110T Series
Pin No
Module
Power
GND
Clock
Analog
Power
Pin name
Function
VCC
Power supply Pin
VCC
Power supply Pin
VCC
Power supply Pin
54
46
P4
VCC
Power supply Pin
89
73
M14
VCC
Power supply Pin
133
109
A13
VCC
Power supply Pin
173
141
A4
VCC
Power supply Pin
129
105
E14
VCC
Power supply Pin
156
126
A9
VSS
GND Pin
27
25
J1
VSS
GND Pin
44
36
M1
VSS
GND Pin
53
45
P3
VSS
GND Pin
88
72
N14
VSS
GND Pin
109
93
F14
VSS
GND Pin
132
108
B14
VSS
GND Pin
157
127
A11
VSS
GND Pin
176
144
B1
VSS
GND Pin
-
-
E1
VSS
GND Pin
-
-
G1
VSS
GND Pin
-
-
P7
VSS
GND Pin
-
-
P11
VSS
GND Pin
-
-
L14
VSS
GND Pin
-
-
A8
VSS
GND Pin
-
-
A5
VSS
GND Pin
-
-
N7
VSS
GND Pin
-
-
M7
VSS
GND Pin
-
-
L7
VSS
GND Pin
-
-
K7
VSS
GND Pin
-
-
J7
VSS
GND Pin
-
-
G7
VSS
GND Pin
-
-
H7
VSS
GND Pin
-
-
H8
LQFP-176
LQFP-144
BGA-192
1
1
C1
45
37
N1
VSS
GND Pin
-
-
G8
X0
Main clock (oscillation) input pin
86
70
P12
X0A
Sub clock (oscillation) input pin
55
47
P5
X1
Main clock (oscillation) I/O pin
87
71
P13
X1A
Sub clock (oscillation) I/O pin
56
48
P6
CROUT_0
127
103
D13
CROUT_1
Built-in high-speed CR oscillation clock
output port
152
122
E8
AVCC
A/D converter analog power supply pin
106
90
J14
AVRH
A/D converter analog reference voltage
input pin
107
91
H14
Document Number: 002-04683 Rev.*C
Page 56 of 132
MB9B110T Series
Pin No
Module
Analog
GND
C pin
Pin name
Function
AVSS
C
LQFP-176
LQFP-144
BGA-192
A/D converter GND pin
108
92
G14
Power supply stabilization capacity pin
52
44
P2
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant
to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in
other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-04683 Rev.*C
Page 57 of 132
MB9B110T Series
5.
I/O Circuit Type
Type
Circuit
Remarks
Pull-up
It is possible to select the main
oscillation / GPIO function
When the main oscillation is selected.
resistor
−
A
P-ch
P-ch
Digital output
X1
−
Oscillation feedback resistor:
Approximately 1 MΩ
With Standby mode control
When the GPIO is selected.
−
−
N-ch
Digital output
R
−
−
−
−
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
Pull-up resistor
control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode
control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
Document Number: 002-04683 Rev.*C
Page 58 of 132
MB9B110T Series
Type
Circuit
Remarks
−
B
−
CMOS level hysteresis input
Pull-up resistor: Approximately 50 kΩ
Pull-up resistor
Digital input
−
C
Digital input
N-ch
Document Number: 002-04683 Rev.*C
−
Open drain output
CMOS level hysteresis input
Control pin
Page 59 of 132
MB9B110T Series
Type
Circuit
Remarks
Pull-up
It is possible to select the sub
oscillation / GPIO function
When the sub oscillation is selected.
resistor
−
D
P-ch
P-ch
Digital output
X1A
−
Oscillation feedback resistor:
Approximately 5 MΩ
With Standby mode control
When the GPIO is selected.
−
−
N-ch
Digital output
R
−
−
−
−
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
Document Number: 002-04683 Rev.*C
Page 60 of 132
MB9B110T Series
Type
Circuit
Remarks
E
−
−
−
−
−
P-ch
P-ch
Digital output
−
−
−
N-ch
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off
+B input is available
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
F
−
−
−
−
−
P-ch
P-ch
Digital output
−
−
−
−
N-ch
Digital output
−
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH= -4 mA, IOL= 4 mA
When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off
+B input is available
Pull-up resistor control
R
Digital input
Standby mode control
Analog input
Input control
Document Number: 002-04683 Rev.*C
Page 61 of 132
MB9B110T Series
Type
Circuit
Remarks
G
−
−
−
−
−
P-ch
P-ch
Digital output
−
−
N-ch
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor: Approximately 50 kΩ
IOH= -12 mA, IOL= 12 mA
+B input is available
Digital output
R
Pull-up resistor
control
Digital input
Standby mode control
H
−
−
−
−
P-ch
N-ch
CMOS level output
CMOS level hysteresis input
With standby mode control
IOH= -20.5 mA, IOL=18.5 mA
Digital output
Digital output
R
Digital input
Standby mode control
Document Number: 002-04683 Rev.*C
Page 62 of 132
MB9B110T Series
Type
Circuit
Remarks
I
−
−
−
−
−
P-ch
Digital output
−
−
N-ch
CMOS level output
CMOS level hysteresis input
5 V tolerant
With standby mode control
IOH= -4 mA, IOL= 4 mA
Available to control PZR registers.
When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off
Digital output
R
Digital input
Standby mode control
J
CMOS level hysteresis input
Mode input
K
−
−
−
−
−
P-ch
P-ch
N-ch
Digital output
−
CMOS level output
TTL level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor: Approximately 50 kΩ
IOH = -4 mA, IOL= 4 mA
Digital output
R
Pull-up resistor
control
Digital input
Standby mode control
Document Number: 002-04683 Rev.*C
Page 63 of 132
MB9B110T Series
Type
Circuit
Remarks
L
−
−
−
−
−
P-ch
P-ch
Digital output
−
−
−
N-ch
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor: Approximately 50 kΩ
IOH = -8 mA, IOL= 8 mA
When this pin is used as an I2C pin,
the digital output P-ch transistor is
always off
+B input is available
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
Document Number: 002-04683 Rev.*C
Page 64 of 132
MB9B110T Series
6.
Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and
input/output functions.
1.
Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and
in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the
design stage.
2.
Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such
conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3.
Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected
through an appropriate resistance to a power supply pin or ground pin.
Document Number: 002-04683 Rev.*C
Page 65 of 132
MB9B110T Series
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess
of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1.
Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2.
Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
Document Number: 002-04683 Rev.*C
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MB9B110T Series
6.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board,
or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be
subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to
Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily
deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open
connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction
strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption
of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel,
reducing moisture resistance and causing packages to crack. To prevent, do the following:
1.
Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2.
Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3.
When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4.
Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-04683 Rev.*C
Page 67 of 132
MB9B110T Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
1.
Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2.
Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3.
Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4.
Ground all fixtures and instruments, or protect with anti-static measures.
5.
Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1.
Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2.
Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use
anti-static measures or processing to prevent discharges.
3.
Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you
use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4.
Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding
as appropriate.
5.
Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin
to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-04683 Rev.*C
Page 68 of 132
MB9B110T Series
7.
Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 μF be connected as a bypass capacitor between each Power supply pins
and GND pins, between AVCC pin and AVSS pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator and the bypass capacitor to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Using an external clock
When using an external clock, the clock signal should be input to the X0,X0A pin only and the X1 and X1A pins should be kept
open.
Example of Using an External Clock
Device
X0(X0A)
Open
X1(X1A)
2
Handling when using Multi-function serial pin as I C pin
2
2
If it is using the multi-function serial pin as I C pins, P-ch transistor of digital output is always disabled. However, I C pins need to
2
keep the electrical characteristic like other pins and not to connect to the external I C bus system with power OFF.
Document Number: 002-04683 Rev.*C
Page 69 of 132
MB9B110T Series
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
Cs
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance
stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC =VCC and AVSS = VSS.
Turning on: VCC → AVCC → AVRH
Turning off: AVRH → AVCC → VCC
Document Number: 002-04683 Rev.*C
Page 70 of 132
MB9B110T Series
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.Therefore, design a
printed circuit board so as to avoid noise.Consider the case of receiving wrong data due to noise, perform error detection such as
by applying a checksum of data at the end. If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash products and
MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics
among the products with different memory sizes and between Flash products and MASK products are different because chip layout
and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Base Timer
In the case of using ch.8 and ch.9 at I/O mode 1 (timer full mode), the TIOA09 pin cannot be used for external startup trigger input
(TGIN). Be sure to use the pin with making ESG1 and ESG2 bits of the Timer Control Register (Ch.9-TMCR) in the Base Timer to
be "0b00" in order to disable trigger input.
Document Number: 002-04683 Rev.*C
Page 71 of 132
MB9B110T Series
8.
Block Diagram
MB9BF116/117/118
TRACED[3:0],
TRACECLK
SWJ-DP
ETM
TPIU
ROM
Table
Cortex-M3 Core
144MHz(Max)
SRAM0
32/48/64Kbyte
I
Multi-layer AHB (Max 144MHz)
TRSTX,TCK,
TDI,TMS
TDO
D
MPU NVIC
Sys
AHB-APB Bridge:
APB0(Max 72MHz)
Dual-Timer
Watchdog Timer
(Software)
Clock Reset
Generator
INITX
Watchdog Timer
(Hardware)
Flash I/F
Security
On-chip Flash
512Kbyte/
768Kbyte/
1024Kbyte
Trace Buffer
(16Kbyte)
SRAM1
32/48/64Kbyte
CSV
DMAC
8ch.
CLK
X1
X0A
X1A
CROUT
AVCC,
AVSS,AVRH
Main
Osc
Sub
Osc
PLL
Source Clock
CR
4MHz
AHB-AHB
Bridge
(Slave)
X0
CR
100kHz
12-bit A/D Converter
Unit 0
AN[31:00]
Unit 1
ADTG[8:0]
Unit 2
MAD[24:00]
AIN[2:0]
BIN[2:0]
QPRC
3ch.
ZIN[2:0]
A/D Activation
Compare
3ch.
IC0[3:0]
IC1[3:0]
IC2[3:0]
FRCK[2:0]
16-bit Input Capture
4ch.
16-bit Free-run Timer
3ch.
16-bit Output
Compare
6ch.
DTTI[2:0]X
RTO0[5:0]
RTO1[5:0]
RTO2[5:0]
AHB-APB Bridge : APB2 (Max 72MHz)
TIOB[15:00]
External Bus I/F
Base Timer
16-bit 16ch./
32-bit 8ch.
AHB-APB Bridge : APB1 (Max 72MHz)
TIOA[15:00]
MADATA[15:00]
Power On
Reset
LVD Ctrl
IRQ-Monitor
MCSX[7:0],
MOEX,MWEX,
MNALE,
MNCLE,
MNWEX,
MNREX,
MDQM[1:0]
MALE
MRDY
MCLKOUT
LVD
Regulator
C
CRC
Accelerator
Watch Counter
External Interrupt
Controller
32-pin + NMI
Waveform Generator
3ch.
MODE-Ctrl
16-bit PPG
3ch.
GPIO
Multi-function Timer ×3
Multi-Function
Serial I/F 8ch.
(with FIFO ch.4 to ch.7)
HW flow control(ch.4)
INT[31:00]
NMIX
MD[1:0]
PIN-Function-Ctrl
P0x,
P1x,
.
.
.
PFx
SCK[7:0]
SIN[7:0]
SOT[7:0]
CTS4
RTS4
Note:
−
The following items vary depending on the package.
•
•
External bus interface pin numbers
12-bit A/D converter channel numbers
Document Number: 002-04683 Rev.*C
Page 72 of 132
MB9B110T Series
9.
Memory Size
See "Memory size" in "Product Lineup" to confirm the memory size.
10.
Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_1000
0x4006_0000
DMAC
Reserved
Reserved
0x4004_0000
0x4003_F000
0x7000_0000
0x6000_0000
Reserved
External Device
Area
0x4003_B000
Reserved
0x4003_8000
32Mbyte
Bit band alias
0x4003_6000
0x4003_A000
0x4003_9000
0x4400_0000
0x4200_0000
0x4000_0000
Peripherals
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
Reserved
0x2400_0000
0x2200_0000
0x2000_0000
0x1FFF_0000
0x0010_2000
See the next page
“●Memory Map (2)” for
the memory size details.
0x0010_0000
0x4003_1000
0x4003_0000
32Mbyte
Bit band alias
0x4002_F000
0x4002_E000
Reserved
0x4002_8000
0x2008_0000
Reserved
Security/CR Trim
0x4002_6000
0x4002_5000
0x4002_4000
0x4002_3000
0x4002_2000
0x4002_1000
0x4002_0000
On-chip Flash
Watch Counter
CRC
MFS
Reserved
LVD Ctrl
Reserved
GPIO
Reserved
Int-Req.Read
EXTI
Reserved
CR Trim
Reserved
0x4002_7000
SRAM1
SRAM0
EXT-bus I/F
0x4001_6000
0x4001_5000
0x0000_0000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
A/DC
QPRC
Base Timer
PPG
Reserved
MFT unit2
MFT unit1
MFT unit0
Reserved
Dual Timer
Reserved
SW WDT
HW WDT
Clock/Reset
Reserved
0x4000_1000
0x4000_0000
Document Number: 002-04683 Rev.*C
Flash I/F
Page 73 of 132
MB9B110T Series
Memory Map (2)
MB9BF118S/T
MB9BF117S/T
0x2008_0000
MB9BF116S/T
0x2008_0000
0x2008_0000
Reserved
Reserved
0x2001_0000
Reserved
0x2001_C000
SRAM1
64Kbyte
0x2000_8000
SRAM1
48Kbyte
0x2000_0000
SRAM1
32Kbyte
0x2000_0000
0x2000_0000
SRAM0
32Kbyte
SRAM0
48Kbyte
SRAM0
64Kbyte
0x1FFF_8000
0x1FFF_4000
Reserved
0x1FFF_0000
Reserved
Reserved
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
CR trimming
Security
0x0010_1000
0x0010_0000
0x0010_2000
CR trimming
Security
0x0010_1000
0x0010_0000
CR trimming
Security
Reserved
0x000C_0000
Reserved
SA10-19(64KBx10)
0x0000_0000
SA4-7(8KBx4)
0x0008_0000
SA10-15(64KBx6)
SA8-9(48KBx2)
0x0000_0000
SA4-7(8KBx4)
Flash 512Kbyte
SA8-9(48KBx2)
Flash 768Kbyte
Flash 1Mbyte
SA10-23(64KBx14)
SA8-9(48KBx2)
0x0000_0000
SA4-7(8KBx4)
See "MB9BD10T/610T/510T/410T/310T/210T/110T Series Flash programming Manual" for sector structure of Flash.
Document Number: 002-04683 Rev.*C
Page 74 of 132
MB9B110T Series
Peripheral Address Map
Start address
End address
0x4000_0000
0x4000_0FFF
Bus
Peripherals
Flash memory I/F register
AHB
0x4000_1000
0x4000_FFFF
Reserved
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
Software Watchdog timer
APB0
0x4001_3000
0x4001_4FFF
Reserved
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function timer unit0
0x4002_1000
0x4002_1FFF
Multi-function timer unit1
0x4002_2000
0x4002_3FFF
Multi-function timer unit2
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
Base Timer
APB1
0x4002_6000
0x4002_6FFF
Quadrature Position/Revolution Counter (QPRC)
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Built-in CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt
0x4003_1000
0x4003_1FFF
Interrupt Source Check Register
0x4003_2000
0x4003_2FFF
Reserved
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_5FFF
Low-Voltage Detector
APB2
0x4003_6000
0x4003_7FFF
Reserved
0x4003_8000
0x4003_8FFF
Multi-function serial Interface
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_EFFF
Reserved
0x4003_F000
0x4003_FFFF
External bus interface
0x4004_0000
0x4005_FFFF
Reserved
0x4006_0000
0x4006_0FFF
0x4006_1000
0x41FF_FFFF
Document Number: 002-04683 Rev.*C
AHB
DMAC register
Reserved
Page 75 of 132
MB9B110T Series
11.
Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the "L" level.
INITX=1
This is the period when the INITX pin is the "H" level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0".
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.If a built-in peripheral function is operating, the
output follows the peripheral function.If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
Document Number: 002-04683 Rev.*C
Page 76 of 132
MB9B110T Series
List of Pin Status
Pin
status Function group
type
A
B
E
Power supply
unstable
INITX input
state
Device internal
reset state
Power supply stable
Power supply stable
INITX=0
INITX=1
INITX=1
-
-
-
SPL=0
SPL=1
Maintain
previous state
Maintain
previous
state
Hi-Z/ Internal
input fixed at
"0"
Input enabled
Input
enabled
Input enabled
Maintain
previous state
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"
Setting disabled
Main crystal
oscillator input
pin
Input enabled
GPIO selected
Setting disabled
Setting disabled Setting disabled
Input enabled
Input enabled
Setting disabled Setting disabled
INITX=1
Main crystal
Hi-Z/
oscillator output Internal input fixed
pin
at "0"/
or Input enable
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state
INITX input pin
Pull-up/
Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input Pull-up/ Input Pull-up/ Input
enabled
enabled
enabled
Mode input pin
Input enabled
Input enabled
Input enabled
Input enabled
Input
enabled
Input enabled
JTAG
selected
Hi-Z
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Maintain
previous state
Maintain
previous state
GPIO
selected
Setting disabled
Setting disabled Setting disabled
Maintain
previous
state
Trace selected
Setting disabled
Setting disabled Setting disabled
Maintain
previous
state
Trace output
GPIO
Hi-Z
selected, or
resource other
than above
selected
G
Power supply
stable
-
External
interrupt enabled
selected
F
Run mode or
Timer mode or stop mode
sleep mode
state
state
-
GPIO selected
C
D
Power-on reset
or low-voltage
detection state
Trace selected
Setting disabled
GPIO selected,
or resource
other than above
selected
Hi-Z
Document Number: 002-04683 Rev.*C
Maintain
previous state
Maintain
Maintain
previous
previous
state/ Hi-Z at state/ Hi-Z at
oscillation
oscillation
*1
*1
stop /
stop /
Internal input Internal input
fixed at "0"
fixed at "0"
Hi-Z/ Internal
input fixed at
"0"
Maintain
previous state
Hi-Z/
Hi-Z/
Hi-Z/
Input enabled
Input enabled
Internal input
fixed at "0"
Setting disabled Setting disabled
Hi-Z/
Hi-Z/
Input enabled
Input enabled
Maintain
previous state
Maintain
previous
state
Trace output
Hi-Z/
Internal input
fixed at "0"
Page 77 of 132
MB9B110T Series
Pin
status Function group
type
Power-on reset
or low-voltage
detection state
Power supply
unstable
-
External
interrupt enabled
selected
H
I
J
Setting disabled
INITX input
state
Device internal
reset state
Power supply stable
INITX=0
INITX=1
Setting disabled Setting disabled
Run mode or
Timer mode or stop mode
sleep mode
state
state
Power supply
stable
Power supply stable
INITX=1
INITX=1
Maintain
previous state
SPL=0
Maintain
previous
state
SPL=1
Maintain
previous state
GPIO selected,
or resource
other than above
selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
GPIO selected,
resource
selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
NMIX selected
Setting disabled
GPIO selected,
or resource
other than above
selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Analog input
selected
Hi-Z
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
GPIO selected,
or resource
other than above
selected
Setting disabled
External
interrupt enabled
selected
Setting disabled
Analog input
selected
Hi-Z
GPIO selected,
or resource
other than above
selected
Setting disabled
Setting disabled Setting disabled
Maintain
previous state
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"
GPIO selected
Setting disabled
Setting disabled Setting disabled
Maintain
previous state
Maintain
previous
state
Hi-Z/ Internal
input fixed at
"0"
Sub crystal
oscillator input
pin
Input enabled
Input enabled
Input
enabled
Input enabled
K
L
Setting disabled Setting disabled
Setting disabled Setting disabled
Setting disabled Setting disabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state
Maintain
previous
state
Hi-Z/ Internal
input fixed at
"0"
Maintain
previous state
Maintain
previous
state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Hi-Z/
Hi-Z/
Internal input Internal input Internal input
fixed at "0"/
fixed at "0"/
fixed at "0"/
Analog input Analog input Analog input
enabled
enabled
enabled
Maintain
previous state
Maintain
previous
state
Maintain
previous state
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state
Hi-Z/
Hi-Z/
Hi-Z/
Internal input Internal input Internal input
fixed at "0"/
fixed at "0"/
fixed at "0"/
Analog input Analog input Analog input
enabled
enabled
enabled
M
Document Number: 002-04683 Rev.*C
Input enabled
Input enabled
Page 78 of 132
MB9B110T Series
Pin
status Function group
type
Power-on reset
or low-voltage
detection state
Power supply
unstable
-
GPIO selected
N
Setting disabled
Hi-Z/
Sub crystal
oscillator output
Internal input fixed
pin
at "0"/
INITX input
state
Device internal
reset state
Power supply stable
INITX=0
INITX=1
-
-
Setting disabled Setting disabled
Hi-Z/
Hi-Z/
Internal input
fixed at "0"
Internal input
fixed at "0"
Run mode or
Timer mode or stop mode
sleep mode
state
state
Power supply
stable
Power supply stable
INITX=1
INITX=1
-
SPL=0
SPL=1
Maintain
previous state
Maintain
previous
state
Hi-Z/
Maintain
previous state
or Input enable
Internal input
fixed at "0"
Maintain
Maintain
previous
previous
state/ Hi-Z at state/ Hi-Z at
oscillation
oscillation
*2
*2
stop /
stop /
Internal input Internal input
fixed at "0"
fixed at "0"
GPIO selected
Hi-Z
O
Mode input pin
Input
Hi-Z/
Hi-Z/
Input enabled
Input enabled
Maintain
previous state
Maintain
previous
state
Hi-Z/ Internal
input fixed at
"0"
Input enabled
Input enabled
Input enabled
Input
Input
enabled
enabled
Maintain
previous
Input enabled
enabled
P
GPIO selected
Setting disabled
Setting disabled Setting disabled
Maintain
previous state
Hi-Z/
state
Q
R
GPIO selected,
resource
selected
Hi-Z
External
interrupt enabled
selected
Setting disabled
GPIO selected,
or resource
other than above
selected
Hi-Z
Hi-Z/
Hi-Z/
Input enabled
Input enabled
Setting disabled Setting disabled
Maintain
previous state
Maintain
previous state
Maintain
previous
Hi-Z/
state
Internal input
fixed at "0"
Maintain
previous
Maintain
previous
state
state
Hi-Z/
Hi-Z/
Hi-Z/
Input enabled
Input enabled
Internal input
fixed at "0"
*1: Oscillation is stopped at Sub timer mode, Low-speed CR timer mode, and STOP mode.
*2: Oscillation is stopped at STOP mode.
Document Number: 002-04683 Rev.*C
Page 79 of 132
MB9B110T Series
12.
Electrical Characteristics
12.1
Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage
*1, *2
Analog power supply voltage
Analog reference voltage
Input voltage
*1, *3
*1, *3
*1
Rating
Max
Vcc
Vss - 0.5
Vss + 6.5
V
AVcc
Vss - 0.5
Vss + 6.5
V
AVRH
Vss - 0.5
Vss + 6.5
V
VI
Vss - 0.5
Vss - 0.5
*1
VIA
Vss - 0.5
VO
Vss - 0.5
Clamp maximum current
ICLAMP
-2
Clamp total maximum current
Σ[ICLAMP]
Analog pin input voltage
Output voltage
*1
"L" level maximum output current
"L" level average output current
*4
IOL
*5
"L" level total maximum output current
"L" level total average output current
"H" level maximum output current
"H" level average output current
*6
*4
"H" level total maximum output current
"H" level total average output current
-
∑IOL
-
∑IOLAV
-
IOHAV
*6
Vcc + 0.5
(≤ 6.5 V)
Vss + 6.5
AVcc + 0.5
(≤ 6.5 V)
Vcc + 0.5
(≤ 6.5 V)
-
IOLAV
IOH
*5
Unit
Min
-
-
Remarks
V
V
5 V tolerant
V
V
+2
mA
*7
+20
mA
*7
10
mA
4 mA type
20
mA
8 mA type
20
mA
12 mA type
39
mA
P80,P81,P82,P83
4
mA
4 mA type
8
mA
8 mA type
12
mA
12 mA type
18.5
mA
P80,P81,P82,P83
100
mA
50
mA
- 10
mA
- 20
mA
8 mA type
- 20
mA
12 mA type
- 39
mA
P80,P81,P82,P83
-4
mA
4 mA type
-8
mA
8 mA type
4 mA type
- 12
mA
12 mA type
- 20.5
mA
P80,P81,P82,P83
∑IOH
-
- 100
mA
∑IOHAV
-
- 50
mA
Power consumption
PD
-
1000
mW
Storage temperature
TSTG
- 55
+ 150
°C
*1: These parameters are based on the condition that Vss = AVss = 0.0 V.
*2: Vcc must not drop below Vss - 0.5 V.
*3: Ensure that the voltage does not to exceed Vcc + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is the peak value for a single pin.
*5: The average output is the average current for a single pin over a period of 100 ms.
*6: The total average output current is the average current for all pins over a period of 100 ms.
Document Number: 002-04683 Rev.*C
Page 80 of 132
MB9B110T Series
*7:
•
•
•
•
•
•
•
•
See "List of Pin Functions" and "I/O Circuit Type" about +B input available pin.
Use within recommended operating conditions.
Use at DC voltage (current) the +B input.
The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin
does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the device drive current is low, such as in the low-power consumpsion modes, the +B input potential may
pass through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.
Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from
the pins, so that incomplete operation may result.
The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
P-ch
Limiting
resistor
Digital output
+B input (0V to 16V)
N-ch
Digital input
R
AVCC
Analog input
WARNING:
−
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess
of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-04683 Rev.*C
Page 81 of 132
MB9B110T Series
12.2
Recommended Operating Conditions
(Vss = AVss = 0.0V)
Parameter
Power supply voltage
Symbol
Conditions
Vcc
-
Analog power supply voltage
AVcc
-
Analog reference voltage
AVRH
-
Smoothing capacitor
CS
TA
Operating
temperature
LQS144,
LQP176,
LBE192
Value
Min
*2
Max
Unit
5.5
V
2.7
5.5
V
2.7
AVcc
V
-
1
10
μF
When
mounted on
four-layer
- 40
+ 85
°C
2.7
Remarks
AVcc = Vcc
for built-in regulator
*1
PCB
*1: See "0 C Pin" in "Handling Devices" for the connection of the smoothing capacitor.
*2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction
execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is
possible to operate only.
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated within these ranges.Always use
semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely
affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or
combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to
contact their representatives beforehand.
Document Number: 002-04683 Rev.*C
Page 82 of 132
MB9B110T Series
12.3
DC Characteristics
12.3.1
Current Rating
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
PLL
RUN mode
RUN
mode
current
Icc
High-speed
CR
RUN mode
VCC
Sub
RUN mode
Low-speed
CR
RUN mode
SLEEP mode
current
Iccs
Value
Conditions
PLL
SLEEP
mode
High-speed
CR
SLEEP
mode
Sub
SLEEP
mode
Low-speed
CR
SLEEP
mode
Typ
CPU: 144 MHz,
Peripheral: 72 MHz,
Flash 2 Wait,
TraceBuffer: ON,
FRWTR.RWT = 10,
FSYNDN.SD = 000,
FBFCR.BE = 1
CPU: 72 MHz,
Peripheral: 72 MHz,Flash 0
Wait,
TraceBuffer: OFF,
FRWTR.RWT = 00,
FSYNDN.SD = 000,
FBFCR.BE = 0
*3
*4
Max
Unit
Remarks
100
180
mA
*1, *5
65
135
mA
*1, *5
6
57.8
mA
*1
1.3
51.7
mA
*1, *6
1.3
51.7
mA
*1
Peripheral: 72 MHz
30
89
mA
*1, *5
*2
4.5
55.9
mA
*1
Peripheral: 32 kHz
1.2
51.6
mA
*1, *6
Peripheral: 100 kHz
1.2
51.6
mA
*1
CPU/ Peripheral: 4 MHz[2],
Flash 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
CPU/ Peripheral: 32 kHz,
Flash 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
CPU/ Peripheral: 100 kHz,
Flash 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
Peripheral: 4 MHz
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA = + 25°C, VCC = 5.5 V
*4: TA = + 85°C, VCC = 5.5 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-04683 Rev.*C
Page 83 of 132
MB9B110T Series
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
ICCT
VCC
STOP mode
current
Sub TIMER mode
ICCH
Typ
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
Main TIMER mode
TIMER mode
current
Value
Conditions
STOP mode
*2
*2
Max
Unit
Remarks
4
10
mA
*1, *3
-
55
mA
*1, *3
1.1
5
mA
*1, *4
-
50
mA
*1, *4
1
5
mA
*1
-
50
mA
*1
*1: When all ports are fixed.
*2: VCC = 5.5 V
*3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Conditions
Low-voltage
detection circuit
(LVD) power
supply current
ICCLVD
VCC
At operation
for interrupt
Value
Typ
Max
4
7
Unit
Remarks
μA
At not detect
Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Conditions
Flash memory
write/erase
current
ICCFLASH
VCC
At Write/Erase
Value
Typ
Max
12
14
Unit
Remarks
mA
A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 85°C)
Parameter
Power supply
current
Reference power
supply current
Symbol
ICCAD
ICCAVRH
Document Number: 002-04683 Rev.*C
Pin
name
Conditions
Value
Unit
Typ
Max
At 1unit
operation
0.57
0.72
mA
At stop
0.06
35
μA
At 1unit
operation
AVRH=5.5 V
1.1
1.96
mA
At stop
0.06
4
μA
Remarks
AVCC
AVRH
Page 84 of 132
MB9B110T Series
12.3.2
Pin Characteristics
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Value
Conditions
Unit
Remarks
Vcc + 0.3
V
[1]
-
Vss + 5.5
V
2.0
-
Vcc + 0.3
V
-
Vss - 0.3
-
Vcc × 0.2
V
-
Vss - 0.3
-
Vcc × 0.2
V
-
Vss - 0.3
-
0.8
V
Vcc - 0.5
-
Vcc
V
[1]
Vcc - 0.5
-
Vcc
V
[1]
Vcc - 0.5
-
Vcc
V
Vcc - 0.4
-
Vcc
V
Min
Typ
Max
-
Vcc × 0.8
-
-
Vcc × 0.8
-
CMOS
hysteresis input
pin, MD0, MD1
"H" level input
voltage
(hysteresis
VIHS
input)
5 V tolerant
input pin
TTL Schmitt
input pin
CMOS
hysteresis input
pin, MD0, MD1
"L" level input
voltage
(hysteresis
VILS
input)
5 V tolerant
input pin
TTL Schmitt
input pin
[1]
Vcc ≥ 4.5 V,
4 mA type
IOH = - 4 mA
Vcc < 4.5 V,
IOH = - 2 mA
Vcc ≥ 4.5 V,
8 mA type
"H" level
output voltage
IOH = - 8 mA
Vcc < 4.5 V,
IOH = - 4 mA
VOH
Vcc ≥ 4.5 V,
12 mA type
IOH = - 12 mA
Vcc < 4.5 V,
IOH = - 8 mA
Vcc ≥ 4.5 V,
P80, P81,
P82, P83
IOH = - 20.5 mA
Vcc < 4.5 V,
[2]
IOH = - 13.0 mA
Document Number: 002-04683 Rev.*C
Page 85 of 132
MB9B110T Series
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
0.4
V
[1]
-
0.4
V
[1]
Vss
-
0.4
V
Vss
-
0.4
V
-
-5
-
+5
μA
Vcc ≥ 4.5 V
25
50
100
Vcc < 4.5 V
30
80
200
-
-
5
15
Min
Typ
Max
Vss
-
Vss
Vcc ≥ 4.5 V,
4 mA type
IOL = 4 mA
Vcc < 4.5 V,
IOL = 2 mA
Vcc ≥ 4.5 V,
8 mA type
"L" level
output voltage
IOL = 8 mA
Vcc < 4.5 V,
IOL = 4 mA
VOL
Vcc ≥ 4.5 V,
12 mA
type
IOL = 12 mA
Vcc < 4.5 V,
IOL = 8 mA
Vcc ≥ 4.5 V,
P80, P81,
P82, P83
IOL = 18.5 mA
Vcc < 4.5 V,
[2]
IOL = 10.5 mA
Input leak
current
IIL
-
Pull-up
resistance value
RPU
Pull-up pin
kΩ
Other than
VCC,
Input
capacitance
CIN
VSS,
AVCC,
pF
AVSS,
AVRH
Document Number: 002-04683 Rev.*C
Page 86 of 132
MB9B110T Series
12.4
AC Characteristics
12.4.1
Main Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Input frequency
Symbol
Pin name
FCH
X0,
Input clock cycle
Input clock pulse
width
Input clock rise time
and fall time
Internal operating
clock[1] frequency
Internal operating
*1
clock cycle time
tCYLH
X1
Conditions
tCR
Remarks
MHz
When crystal oscillator is
connected
MHz
When using external clock
ns
When using external clock
55
%
When using external clock
-
5
ns
When using external clock
Vcc ≥ 4.5 V
4
48
Vcc < 4.5 V
4
20
Vcc ≥ 4.5 V
4
48
Vcc < 4.5 V
4
20
Vcc ≥ 4.5 V
20.83
250
Vcc < 4.5 V
50
250
45
-
PWL/tCYLH
tCF,
Unit
Max
PWH/tCYLH,
-
Value
Min
FCM
-
-
-
144
MHz
Master clock
FCC
-
-
-
144
MHz
Base clock (HCLK/FCLK)
FCP0
-
-
-
72
MHz
APB0 bus clock
FCP1
-
-
-
72
MHz
APB1 bus clock
FCP2
-
-
-
72
MHz
APB2 bus clock
tCYCC
-
-
6.94
-
ns
tCYCP0
-
-
13.8
-
ns
APB0 bus clock
tCYCP1
-
-
13.8
-
ns
APB1 bus clock
tCYCP2
-
-
13.8
-
ns
APB2 bus clock
*2
*2
*2
Base clock (HCLK/FCLK)
*2
*2
*2
*1: For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL
MANUAL".
*2: For about each APB bus which each peripheral is connected to, see "Block Diagram" in this datasheet.
X0
Document Number: 002-04683 Rev.*C
Page 87 of 132
MB9B110T Series
12.4.2
Sub Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Input frequency
Symbol
Pin
name
Value
Conditions
Unit
Remarks
-
kHz
When crystal oscillator is
connected
-
100
kHz
When using external
clock
10
-
31.25
μs
When using external
clock
45
-
55
%
When using external
clock
Min
Typ
Max
-
-
32.768
-
32
-
1/tCYLL
X0A,
Input clock cycle
tCYLL
Input clock pulse
width
-
X1A
PWH/tCYLL,
PWL/tCYLL
X0A
12.4.3
Internal CR Oscillation Characteristics
High-speed Internal CR
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Value
Min
Typ
Max
TA = + 25°C
3.96
4
4.04
TA = 0°C to + 70°C
3.84
4
4.16
TA = - 40°C to + 85°C
3.8
4
4.2
TA = - 40°C to + 85°C
3
4
5
-
-
-
90
Unit
Remarks
*1
Clock frequency
Frequency stability
time
FCRH
tCRWT
MHz
When trimming
When not trimming
μs
*2
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2: Frequency stable time is time to stable of the frequency of the High-speed CR.clock after the trim value is set. After setting the
trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock.
Low-speed Internal CR
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Clock frequency
FCRL
-
Document Number: 002-04683 Rev.*C
Value
Min
Typ
Max
50
100
150
Unit
Remarks
kHz
Page 88 of 132
MB9B110T Series
12.4.4
Operating Conditions of Main and USB PLL
Operating Conditions of Main PLL (In the case of using main clock for input of PLL)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
PLL oscillation stabilization wait time
(LOCK UP time)
Unit
Min
Typ
Max
tLOCK
100
-
-
μs
FPLLI
FPLLO
4
13
200
-
16
75
300
MHz
multiple
MHz
FCLKPLL
-
-
144
MHz
Remarks
*1
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
*2
Main PLL clock frequency
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL".
Operating Conditions of Main PLL (In the case of using high-speed internal CR)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
PLL oscillation stabilization wait time
(LOCK UP time)
Symbol
Unit
Min
Typ
Max
tLOCK
100
-
-
μs
FPLLI
FPLLO
FCLKPLL
3.8
50
190
-
4
-
4.2
71
300
144
MHz
multiple
MHz
MHz
Remarks
*1
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
*2
Main PLL clock frequency
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL".
Note:
−
Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency has been trimmed.
Main PLL connection
Main clock (CLKMO)
High-speed CR clock (CLKHC)
PLL input
clock
K
divider
Main
PLL
PLL macro
oscillation clock
M
divider
Main PLL
clock
(CLKPLL)
N
divider
Document Number: 002-04683 Rev.*C
Page 89 of 132
MB9B110T Series
12.4.5
Reset Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Reset input time
12.4.6
tINITX
Pin name
Value
Conditions
INITX
-
Unit
Min
Max
500
-
Remarks
ns
Power-on Reset Timing
(Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Power supply shut down time
tOFF
Power ramp rate
dV/dt
Time until releasing Power-on reset
tPRT
Pin name
VCC
Conditions
Unit
Remarks
Min
Typ
Max
-
50
-
-
ms
*1
Vcc:0.2 V to 2.70 V
0.9
-
1000
mV/μs
*2
-
0.46
-
0.76
ms
*1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>50 ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 5.
2.7V
VCC
VDH
0.2V
dV/dt
0.2V
tPRT
Internal RST
CPU Operation
RST Active
0.2V
tOFF
release
start
Glossary
VDH: detection voltage of Low Voltage detection reset. See “12.6 Low-Voltage Detection Characteristics”
Document Number: 002-04683 Rev.*C
Page 90 of 132
MB9B110T Series
12.4.7
External Bus Timing
External bus clock output characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Output frequency
tCYCLE
Pin name
MCLKOUT
Conditions
Vcc ≥ 4.5 V
*1
Vcc < 4.5 V
Value
Min
Max
-
*2
MHz
*3
MHz
50
-
Unit
32
*1: External bus clock (MCLKOUT) is divided clock of HCLK.
For more information about setting of clock divider, see "CHAPTER 12: External Bus Interface" in "FM3 Family PERIPHERAL
MANUAL".
When external bus clock is not output, this characteristic does not give any effect on external bus operation.
*2: When AHB bus clock frequency is more than 100 MHz, the divider setting for MCLKOUT must be more than 4.
*3: When AHB bus clock frequency is more than 64 MHz, the divider setting for MCLKOUT must be more than 4.
MCLKOUT
External bus signal input/output characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Value
Unit
0.8 × VCC
V
0.2 × VCC
V
VOH
0.8 × VCC
V
VOL
0.2 × VCC
V
VIH
Remarks
Signal input characteristics
VIL
Signal output characteristics
Input signal
VIH
VIL
VIH
VIL
Output signal
VOH
VOL
VOH
VOL
Document Number: 002-04683 Rev.*C
Page 91 of 132
MB9B110T Series
Separate Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
MOEX
Min pulse width
Symbol
Pin name
tOEW
MOEX
Conditions
Vcc ≥ 4.5 V
Value
Min
Max
MCLK×n-3
-
Unit
ns
Vcc < 4.5 V
MCSX ↓ → Address
output delay time
tCSL – AV
MOEX ↑ →Address hold
time
tOEH - AX
MCSX ↓ →MOEX ↓ delay
time
tCSL - OEL
MOEX ↑ →MCSX ↑ time
tOEH - CSH
MCSX[7:0],
Vcc ≥ 4.5 V
-9
+9
MAD[24:0]
Vcc < 4.5 V
-12
+12
MOEX,
Vcc ≥ 4.5 V
MAD[24:0]
Vcc < 4.5 V
0
tCSL - RDQML
Data set up → MOEX ↑
time
tDS - OE
MOEX ↑ →Data hold
time
tDH - OE
MWEXMin pulse width
tWEW
ns
MCLK×m+12
Vcc ≥ 4.5 V
MCLK×m-9
MCLK×m+9
MOEX,
Vcc < 4.5 V
MCLK×m-12
MCLK×m+12
MCSX[7:0]
Vcc ≥ 4.5 V
0
Vcc < 4.5 V
MCSX ↓ →MDQM ↓
delay time
MCLK×m+9
ns
MCLK×m+9
ns
ns
MCLK×m+12
MCSX,
Vcc ≥ 4.5 V
MCLK×m-9
MCLK×m+9
MDQM[1:0]
Vcc < 4.5 V
MCLK×m-12
MCLK×m+12
ns
MOEX,
Vcc ≥ 4.5 V
20
-
MADATA[15:0]
Vcc < 4.5 V
38
-
MOEX,
Vcc ≥ 4.5 V
MADATA[15:0]
0
-
ns
Vcc < 4.5 V
MCLK×n-3
-
ns
MWEX
Vcc ≥ 4.5 V
ns
Vcc < 4.5 V
MWEX ↑ → Address
output delay time
tWEH - AX
MCSX ↓ → MWEX ↓
delay time
tCSL - WEL
MWEX ↑ → MCSX ↑
delay time
tWEH - CSH
MCSX ↓ → MDQM ↓
delay time
tCSL-WDQML
MCSX ↓ → Data output
time
tCSL - DV
MWEX ↑ →Data hold
time
tWEH - DX
MWEX,
Vcc ≥ 4.5 V
MAD[24:0]
Vcc < 4.5 V
0
MCLK×m+9
ns
MCLK×m+12
Vcc ≥ 4.5 V
MCLK×n-9
MCLK×n+9
MWEX,
Vcc < 4.5 V
MCLK×n-12
MCLK×n+12
MCSX[7:0]
Vcc ≥ 4.5 V
0
Vcc < 4.5 V
MCLK×m+9
ns
ns
MCLK×m+12
MCSX,
Vcc ≥ 4.5 V
MCLK×n-9
MCLK×n+9
MDQM[1:0]
Vcc < 4.5 V
MCLK×n-12
MCLK×n+12
MCSX,
Vcc ≥ 4.5 V
MCLK-9
MCLK+9
MADATA[15:0]
Vcc < 4.5 V
MCLK-12
MCLK+12
MWEX,
Vcc ≥ 4.5 V
MADATA[15:0]
Vcc < 4.5 V
0
MCLK×m+9
ns
ns
ns
MCLK×m+12
Note:
−
When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
Document Number: 002-04683 Rev.*C
Page 92 of 132
MB9B110T Series
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
MCSX[7:0]
tCSL-AV
MAD[24:0]
tOEH-AX
Address
tWEH-AX
tCSL-AV
Address
tCSL-OEL
MOEX
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
tCSL-WEL
tWEW
MWEX
MADATA[15:0]
tDS-OE
tDH-OE
RD
tWEH-DX
WD
Invalid
tCSL-DV
Document Number: 002-04683 Rev.*C
Page 93 of 132
MB9B110T Series
Separate Bus Access Synchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Address delay time
tAV
Pin name
Conditions
MCLK,
Vcc ≥ 4.5 V
MAD[24:0]
Vcc < 4.5 V
Vcc ≥ 4.5 V
tCSL
MCSX delay time
MCLK,
Vcc < 4.5 V
MCSX[7:0]
Vcc ≥ 4.5 V
tCSH
Value
Min
1
Vcc ≥ 4.5 V
MOEX delay time
MCLK,
Vcc < 4.5 V
MOEX
Vcc ≥ 4.5 V
tREH
1
tDS
MCLK ↑ → Data hold
time
tDH
1
1
1
19
Vcc < 4.5 V
37
MCLK,
Vcc ≥ 4.5 V
MADATA[15:0]
Vcc < 4.5 V
MWEX delay time
Vcc < 4.5 V
MWEX
Vcc ≥ 4.5 V
tWEH
0
1
Vcc ≥ 4.5 V
MDQM[1:0] delay time
MCLK,
Vcc < 4.5 V
MDQM[1:0]
Vcc ≥ 4.5 V
tDQMH
1
tOD
MCLK ↑ → Data hold
time
tOD
MCLK,
Vcc ≥ 4.5 V
MADATA[15:0]
Vcc < 4.5 V
MCLK,
Vcc ≥ 4.5 V
MADATA[15:0]
Vcc < 4.5 V
9
ns
9
ns
-
ns
-
ns
9
ns
9
ns
12
1
9
ns
12
1
Vcc < 4.5 V
MCLK ↑ → Data output
time
ns
12
Vcc < 4.5 V
tDQML
9
12
Vcc ≥ 4.5 V
MCLK,
ns
12
MCLK,
Vcc ≥ 4.5 V
9
12
MADATA[15:0]
tWEL
ns
12
Vcc < 4.5 V
Data set up →MCLK ↑
time
9
Unit
12
Vcc < 4.5 V
tREL
Max
9
ns
12
MCLK+1
MCLK+18
ns
MCLK+24
1
18
ns
24
Note:
−
When the external load capacitance = 30 pF.
Document Number: 002-04683 Rev.*C
Page 94 of 132
MB9B110T Series
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
tAV
MAD[24:0]
tAV
Address
Address
tREL
tREH
tDQML
tDQMH
MOEX
tDQML
tDQMH
tWEL
tWEH
MDQM[1:0]
MWEX
MADATA[15:0]
tDS
tDH
RD
tOD
WD
Invalid
tODS
Document Number: 002-04683 Rev.*C
Page 95 of 132
MB9B110T Series
Multiplexed Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Multiplexed
address delay time
Multiplexed
address hold time
Symbol
Pin name
Vcc ≥ 4.5 V
tALE-CHMADV
tCHMADH
Conditions
Value
Min
0
Max
10
MALE,
Vcc < 4.5 V
MADATA[15:0]
Vcc ≥ 4.5 V
MCLK×n+0
MCLK×n+10
Vcc < 4.5 V
MCLK×n+0
MCLK×n+20
Unit
ns
20
ns
Note:
−
When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-04683 Rev.*C
Page 96 of 132
MB9B110T Series
Multiplexed Bus Access Synchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
tCHAL
MALE delay time
tCHAH
MCLK ↑ → Multiplexed
Address delay time
MCLK ↑ → Multiplexed
Data output time
Pin name
Conditions
MCLK,
Vcc < 4.5 V
Vcc ≥ 4.5 V
ALE
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
tCHMADV
MCLK,
MADATA[15:0]
tCHMADX
Value
Min
1
Max
9
Unit
ns
12
ns
9
ns
12
ns
1
tOD
ns
1
tOD
ns
1
Remarks
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Note:
−
When the external load capacitance = 30 pF.
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-04683 Rev.*C
Page 97 of 132
MB9B110T Series
NAND Flash Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
MNREX Min pulse width
tNREW
MNREX
Data setup → MNREX↑time
tDS – NRE
MNREX↑→ Data hold time
tDH – NRE
MNALE↑→ MNWEX delay
time
tALEH - NWEL
MNALE↓→ MNWEX delay
time
tALEL - NWEL
MNCLE↑→ MNWEX delay
time
tCLEH - NWEL
MNWEX↑→ MNCLE delay
time
tNWEH - CLEL
MNWEX Min pulse width
tNWEW
MNWEX↓→ Data output
time
tNWEL – DV
MNWEX↑→ Data hold time
tNWEH – DX
Conditions
Vcc ≥ 4.5 V
Vcc < 4.5 V
Value
Min
Max
MCLK×n-3
-
MNREX,
Vcc ≥ 4.5 V
20
-
MADATA[15:0]
Vcc < 4.5 V
38
-
0
-
MNREX,
Vcc ≥ 4.5 V
MADATA[15:0]
Vcc < 4.5 V
MNALE,
Vcc ≥ 4.5 V
MCLK×m-9
MCLK×m+9
MNWEX
Vcc < 4.5 V
MCLK×m-12
MCLK×m+12
MNALE,
Vcc ≥ 4.5 V
MCLK×m-9
MCLK×m+9
MNWEX
Vcc < 4.5 V
MCLK×m-12
MCLK×m+12
MNCLE,
Vcc ≥ 4.5 V
MCLK×m-9
MCLK×m+9
MNWEX
Vcc < 4.5 V
MCLK×m-12
MCLK×m+12
MNCLE,
Vcc ≥ 4.5 V
MNWEX
Vcc < 4.5 V
MNWEX
Vcc ≥ 4.5 V
Vcc < 4.5 V
0
MCLK×n-3
MCLK×m+9
MCLK×m+12
-
MNWEX,
Vcc ≥ 4.5 V
-9
+9
MADATA[15:0]
Vcc < 4.5 V
-12
+12
MNWEX,
Vcc ≥ 4.5 V
MADATA[15:0]
Vcc < 4.5 V
0
MCLK×m+9
MCLK×m+12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
−
When the external load capacitance = 30 pF. (m=0 to 15, n=1 to 16)
NAND Flash Read
MCLK
MNREX
MADATA[15:0]
Read
Document Number: 002-04683 Rev.*C
Page 98 of 132
MB9B110T Series
NAND Flash Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
NAND Flash Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Document Number: 002-04683 Rev.*C
Write
Page 99 of 132
MB9B110T Series
External Ready Input Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
MCLK ↑ MRDY input
setup time
Symbol
tRDYI
Value
Pin name
Conditions
MCLK,
Vcc ≥ 4.5 V
19
MRDY
Vcc < 4.5 V
37
Min
Max
-
Unit
Remarks
ns
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
MCLK
··· ···
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
Document Number: 002-04683 Rev.*C
Page 100 of 132
MB9B110T Series
12.4.8
Base Timer Input Timing
Timer input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTIWH,
TIOAn/TIOBn
tTIWL
(when using as CK, TIN)
-
tTIWH
Value
Min
Max
2tCYCP
-
Unit
Remarks
ns
tTIWL
ECK
VIHS
TIN
VIHS
VILS
VILS
Trigger input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTRGH,
TIOAn/TIOBn
tTRGL
(when using as TGIN)
-
tTRGH
TGIN
VIHS
Value
Min
Max
2tCYCP
-
Unit
Remarks
ns
tTRGL
VIHS
VILS
VILS
Note:
−
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Base Timer is connected to, see "Block Diagram" in this data sheet.
Document Number: 002-04683 Rev.*C
Page 101 of 132
MB9B110T Series
12.4.9
CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Baud rate
-
Pin
name
-
Serial clock cycle time
tSCYC
SCKx
Parameter
Symbol
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock "L" pulse width
tSLSH
Serial clock "H" pulse width
tSHSL
Conditions
Vcc ≥ 4.5 V
Vcc < 4.5 V
Unit
Min
Max
Min
Max
4tCYCP
8
-
4tCYCP
8
-
Mbps
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
ns
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
SCKx,
SOTx
SCKx,
Master mode
SINx
SCKx,
SINx
SCKx,
ns
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK fall time
tF
SCKx
-
5
-
5
ns
SCK rise time
tR
SCKx
-
5
-
5
ns
SOTx
SCKx,
SINx
Slave mode
SCKx,
SINx
Notes:
−
−
The above characteristics apply to CLK synchronous mode.
−
These characteristics only guarantee the same relocate port number.For example, the combination of SCKx_0 and SOTx_1
is not guaranteed.
−
When the external load capacitance = 30 pF.
tCYCP indicates the APB bus clock cycle time.About the APB bus number which Multi-function Serial is connected to, see
"Block Diagram" in this data sheet.
Document Number: 002-04683 Rev.*C
Page 102 of 132
MB9B110T Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
VIH
VIL
SIN
tSHIXI
VIH
VIL
Master mode
tSLSH
SCK
VIH
tF
SOT
VIL
tSHSL
VIL
VIH
VIH
tR
tSLOVE
VOH
VOL
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
Document Number: 002-04683 Rev.*C
Page 103 of 132
MB9B110T Series
CSIO (SPI = 0, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Baud rate
-
Pin
name
-
Serial clock cycle time
tSCYC
SCKx
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
Serial clock "L" pulse width
tSLSH
Serial clock "H" pulse width
tSHSL
Conditions
Vcc ≥ 4.5 V
Vcc < 4.5 V
Unit
Min
Max
Min
Max
-
8
-
8
Mbps
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
ns
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
SCKx,
SOTx
SCKx,
Master mode
SINx
SCKx,
SINx
SCKx,
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK fall time
tF
SCKx
-
5
-
5
ns
SCK rise time
tR
SCKx
-
5
-
5
ns
SOTx
SCKx,
SINx
Slave mode
SCKx,
SINx
Notes:
−
−
The above characteristics apply to CLK synchronous mode.
−
These characteristics only guarantee the same relocate port number.For example, the combination of SCKx_0 and SOTx_1
is not guaranteed.
−
When the external load capacitance = 30 pF.
tCYCP indicates the APB bus clock cycle time.About the APB bus number which Multi-function Serial is connected to, see
"Block Diagram" in this data sheet.
Document Number: 002-04683 Rev.*C
Page 104 of 132
MB9B110T Series
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
Master mode
tSHSL
SCK
tSLSH
VIH
VIH
VIL
tR
VIL
tF
tSHOVE
SOT
SIN
VIL
VOH
VOL
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
Document Number: 002-04683 Rev.*C
Page 105 of 132
MB9B110T Series
CSIO (SPI = 1, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Vcc ≥ 4.5 V
Vcc < 4.5 V
Baud rate
-
Pin
name
-
Serial clock cycle time
tSCYC
SCKx
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock "L" pulse width
tSLSH
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
Parameter
Symbol
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
Conditions
-
SCKx,
SOTx
SCKx,
SINx
Master mode
SCKx,
SINx
SCKx,
SOTx
SCKx,
SOTx
SCKx,
SINx
Slave mode
SCKx,
SINx
Unit
Min
Max
Min
Max
4tCYCP
8
-
4tCYCP
8
-
Mbps
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 30
-
2tCYCP - 30
-
ns
ns
SCK fall time
tF
SCKx
-
5
-
5
ns
SCK rise time
tR
SCKx
-
5
-
5
ns
Notes:
−
−
The above characteristics apply to CLK synchronous mode.
−
These characteristics only guarantee the same relocate port number.For example, the combination of SCKx_0 and SOTx_1
is not guaranteed.
−
When the external load capacitance = 30 pF.
tCYCP indicates the APB bus clock cycle time.About the APB bus number which Multi-function Serial is connected to, see
"Block Diagram" in this data sheet.
Document Number: 002-04683 Rev.*C
Page 106 of 132
MB9B110T Series
tSCYC
VOH
VOL
SCK
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
Master mode
tSLSH
SCK
VIH
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
VIH
VIL
tF
*
SOT
VIL
tSHSL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-04683 Rev.*C
Page 107 of 132
MB9B110T Series
CSIO (SPI = 1, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Baud rate
-
Pin
name
-
Serial clock cycle time
tSCYC
SCKx
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
SOT → SCK ↑ delay time
tSOVHI
Parameter
Symbol
Conditions
-
SCKx,
SOTx
SCKx,
SINx
Master mode
SCKx,
SINx
SCKx,
SOTx
Vcc ≥ 4.5 V
Vcc < 4.5 V
Unit
Min
Max
Min
Max
4tCYCP
8
-
4tCYCP
8
-
Mbps
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 30
-
2tCYCP - 30
-
ns
ns
Serial clock "L" pulse width
tSLSH
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK ↓ → SOT delay time
tSLOVE
-
50
-
30
ns
SIN → SCK ↑ setup time
tIVSHE
10
-
10
-
ns
SCK ↑ → SIN hold time
tSHIXE
20
-
20
-
ns
SCKx,
SOTx
SCKx,
SINx
Slave mode
SCKx,
SINx
SCK fall time
tF
SCKx
-
5
-
5
ns
SCK rise time
tR
SCKx
-
5
-
5
ns
Notes:
−
−
The above characteristics apply to CLK synchronous mode.
−
These characteristics only guarantee the same relocate port number.For example, the combination of SCKx_0 and SOTx_1
is not guaranteed.
−
When the external load capacitance = 30 pF.
tCYCP indicates the APB bus clock cycle time.About the APB bus number which Multi-function Serial is connected to, see
"Block Diagram" in this data sheet.
Document Number: 002-04683 Rev.*C
Page 108 of 132
MB9B110T Series
tSCYC
VOH
SCK
VOH
VOL
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VIH
VIL
Master mode
tSHSL
tR
SCK
tSLSH
VIH
VIH
VIL
VIL
tF
VIH
VIL
tSLOVE
VOH
VOL
SOT
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
SIN
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Serial clock "L" pulse width
tSLSH
Serial clock "H" pulse width
tSHSL
SCK fall time
tF
SCK rise time
tR
Min
tCYCP + 10
CL = 30 pF
tR
SCK
VIL
Document Number: 002-04683 Rev.*C
Value
Conditions
-
ns
-
5
ns
-
5
ns
tF
tSLSH
VIH
VIL
Remarks
ns
tCYCP + 10
tSHSL
VIH
Unit
Max
-
VIL
VIH
Page 109 of 132
MB9B110T Series
12.4.10 External Input Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Max
Unit
ADTG
FRCKx
A/D converter trigger input
-
*1
-
2tCYCP
ns
ICxx
Input pulse width
tINH,
DTTIxX
tINL
INTxx,
NMIX
Remarks
Free-run timer input clock
Input capture
*1
-
2tCYCP
Except Timer
mode,
2tCYCP + 100
*1
-
ns
-
ns
-
ns
Stop mode
Timer mode,
Stop mode
Wave form generator
External interrupt
NMI
500
*1: tCYCP indicates the APB bus clock cycle time.About the APB bus number which the A/D converter, Multi-function Timer,
External interrupt are connected to, see "Block Diagram" in this data sheet.
Document Number: 002-04683 Rev.*C
Page 110 of 132
MB9B110T Series
12.4.11 Quadrature Position/Revolution Counter timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
AIN pin "H" width
tAHL
-
AIN pin "L" width
tALL
-
BIN pin "H" width
tBHL
-
BIN pin "L" width
tBLL
-
BIN rise time from AIN pin "H" level
tAUBU
PC_Mode2 or PC_Mode3
AIN fall time from BIN pin "H" level
tBUAD
PC_Mode2 or PC_Mode3
BIN fall time from AIN pin "L" level
tADBD
PC_Mode2 or PC_Mode3
AIN rise time from BIN pin "L" level
tBDAU
PC_Mode2 or PC_Mode3
AIN rise time from BIN pin "H" level
tBUAU
PC_Mode2 or PC_Mode3
BIN fall time from AIN pin "H" level
tAUBD
PC_Mode2 or PC_Mode3
AIN fall time from BIN pin "L" level
tBDAD
PC_Mode2 or PC_Mode3
BIN rise time from AIN pin "L" level
tADBU
PC_Mode2 or PC_Mode3
ZIN pin "H" width
tZHL
QCR:CGSC="0"
ZIN pin "L" width
tZLL
QCR:CGSC="0"
AIN/BIN rise and fall time from
determined ZIN level
tZABE
QCR:CGSC="1"
Determined ZIN level from AIN/BIN
rise and fall time
tABEZ
QCR:CGSC="1"
Value
Min
Max
*1
-
2tCYCP
Unit
ns
*1: tCYCP indicates the APB bus clock cycle time.About the APB bus number which Quadrature Position/Revolution Counter is
connected to, see "Block Diagram" in this data sheet.
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
Document Number: 002-04683 Rev.*C
tBLL
Page 111 of 132
MB9B110T Series
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-04683 Rev.*C
Page 112 of 132
MB9B110T Series
2
12.4.12 I C Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Standard-mode
Fast-mode
SCL clock frequency
FSCL
(Repeated) START condition hold
time SDA ↓ → SCL ↓
tHDSTA
4.0
-
0.6
-
μs
SCLclock "L" width
tLOW
4.7
-
1.3
-
μs
SCLclock "H" width
tHIGH
4.0
-
0.6
-
μs
4.7
-
0.6
-
μs
(Repeated) START setup time
SCL ↑ → SDA ↓
tSUSTA
CL = 30 pF,
Max
100
Min
0
Max
400
Unit Remarks
Min
0
*1
R = (Vp/IOL)
*2
Data hold time SCL ↓ → SDA ↓ ↑
tHDDAT
Data setup time SDA ↓ ↑ → SCL ↑
tSUDAT
250
-
tSUSTO
4.0
tBUF
4.7
STOP condition setup time
SCL ↑ → SDA ↑
Bus free time between "STOP
condition" and "START condition"
Noise filter
kHz
tSP
0
*3
0.9
μs
100
-
ns
-
0.6
-
μs
-
1.3
3.45
0
-
μs
*4
-
ns
[5]
*4
-
ns
[5]
*4
-
ns
[5]
*4
-
2 tCYCP
*4
-
3 tCYCP
*4
-
4 tCYCP
8 MHz ≤ tCYCP ≤ 40 Hz
2 tCYCP
40 MHz < tCYCP ≤ 60 Hz
3 tCYCP
60 MHz < tCYCP ≤ 72 Hz
4 tCYCP
*1:
R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates
the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2:
The maximum tHDDAT must satisfy that it does not extend at least "L" period (t LOW) of device's SCL signal.
*3:
A Fast-mode I C bus device can be used on a Standard-mode I C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250 ns".
*4:
tCYCP is the APB bus clock cycle time. About the APB bus number which I C is connected to, see "Block Diagram" in
this data sheet.
2
2
2
To use Standard-mode, set the APB bus clock at 2 MHz or more.To use Fast-mode, set the APB bus clock at 8
MHz or more.
*5:
The number of steps of the noise filter can be changed with register settings.Change the number of the noise filter
steps according to APB2 bus clock frequency.
SDA
SCL
Document Number: 002-04683 Rev.*C
Page 113 of 132
MB9B110T Series
12.4.13 ETM Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Data hold
tETMH
TRACECLK frequency
Pin name
Conditions
TRACECLK,
TRACED[3:0]
cycle time
Unit
Max
Vcc ≥ 4.5 V
2
9
Vcc < 4.5 V
2
15
Vcc ≥ 4.5 V
-
50
MHz
Vcc < 4.5 V
-
32
MHz
Vcc ≥ 4.5 V
20
-
ns
Vcc < 4.5 V
31.25
-
ns
Remarks
ns
1/ tTRACE
TRACECLK
TRACECLK
Value
Min
tTRACE
Note:
−
When the external load capacitance = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
Document Number: 002-04683 Rev.*C
Page 114 of 132
MB9B110T Series
12.4.14 JTAG Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
TMS, TDI setup time
tJTAGS
TMS, TDI hold time
tJTAGH
TDO delay time
tJTAGD
Pin name
Conditions
TCK,
Vcc ≥ 4.5 V
TMS, TDI
Vcc < 4.5 V
Value
Unit
Min
Max
15
-
ns
15
-
ns
TCK,
Vcc ≥ 4.5 V
TMS, TDI
Vcc < 4.5 V
TCK,
Vcc ≥ 4.5 V
-
25
TDO
Vcc < 4.5 V
-
45
Remarks
ns
Note:
−
When the external load capacitance = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-04683 Rev.*C
Page 115 of 132
MB9B110T Series
12.5
12-bit A/D Converter
Electrical characteristics for the A/D converter
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 85°C)
Value
-
Pin
name
-
Min
-
Parameter
Symbol
Resolution
Typ
-
Max
12
Unit
bit
Integral Nonlinearity
-
-
-
± 4.5
LSB
Differential Nonlinearity
-
-
-
± 2.5
LSB
Zero transition voltage
VZT
ANxx
-
± 15
mV
Full-scale transition
voltage
VFST
ANxx
-
AVRH ± 15
mV
Conversion time
-
-
*1
Sampling time
-
-
1.2
-
-
*2
-
-
*2
-
-
1.0
*1
μs
Ts
-
Compare clock cycle*
Tcck
-
50
-
2000
ns
State transition time to
operation permission
Tstt
-
-
-
1.0
μs
Analog input capacity
CAIN
-
-
-
12.9
pF
Analog input resistance
RAIN
-
-
-
Interchannel disparity
-
-
-
-
4
LSB
Analog port input leak
current
-
ANxx
-
-
5
μA
Analog input voltage
-
ANxx
AVSS
-
AVRH
V
Reference voltage
-
AVRH
2.7
-
AVCC
V
3
2
3.8
Remarks
ns
kΩ
AVRH = 2.7 V to 5.5 V
AVcc ≥ 4.5 V
AVcc < 4.5 V
AVcc ≥ 4.5 V
AVcc < 4.5 V
AVcc ≥ 4.5 V
AVcc < 4.5 V
*1: The Conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is the following.
AVcc ≥ 4.5 V, HCLK=120 MHz
AVcc < 4.5 V, HCLK=120 MHz
sampling time: 300 ns
compare time: 700 ns
sampling time: 500 ns
compare time: 700 ns
Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).
For setting of the sampling time and compare clock cycle, see "CHAPTER 1-1: A/D Converter" in "FM3 Family PERIPHERAL
MANUAL Analog Macro Part".
The registers setting of the A/D Converter are reflected in the operation according to the APB bus clock timing.
The sampling clock and compare clock is generated from the Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see "Block Diagram" in this data sheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3: Compare time (Tc) is the value of (Equation 2).
Document Number: 002-04683 Rev.*C
Page 116 of 132
MB9B110T Series
Rext
ANxx
Analog input pin
Comparator
RAIN
Analog
signal source
CAIN
(Equation 1) Ts ≥ ( RAIN + Rext ) × CAIN × 9
Ts:
Sampling time
RAIN:
Input resistance of A/D = 2 kΩ at 4.5 V ≤ AVCC ≤ 5.5 V
Input resistance of A/D = 3.8 kΩ at 2.7 V ≤ AVCC < 4.5 V
CAIN:
Input capacity of A/D = 12.9 pF at 2.7 V ≤ AVCC ≤ 5.5 V
Rext:
Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc:
Compare time
Tcck:
Compare clock cycle
Document Number: 002-04683 Rev.*C
Page 117 of 132
MB9B110T Series
Definition of 12-bit A/D Converter Terms
Resolution:
Analog variation that is recognized by an A/D converter.
Integral Nonlinearity:
Deviation of the line between the zero-transition point
(0b000000000000←→0b000000000001) and the full-scale transition point
(0b111111111110←→0b111111111111) from the actual conversion characteristics.
Deviation from the ideal value of the input voltage that is required to change the output
code by 1 LSB.
Differential Nonlinearity:
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actually-measured
value)
0x003
0x002
(Actuallymeasured
value)
Digital output
Digital output
0xFFD
0xN
Ideal characteristics
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
VNT
0x(N-2)
0x001
VZT (Actually-measured value)
AVss
AVRH
Differential Nonlinearity of digital output N =
1LSB =
N:
(Actually-measured
value)
Actual conversion characteristics
AVss
Analog input
Integral Nonlinearity of digital output N =
V(N+1)T
0x(N-1)
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
[LSB]
1LSB
V(N + 1) T - VNT
- 1 [LSB]
1LSB
VFST - VZT
4094
A/D converter digital output value.
VZT:
Voltage at which the digital output changes from 0x000 to 0x001.
VFST:
Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT:
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-04683 Rev.*C
Page 118 of 132
MB9B110T Series
12.6
Low-Voltage Detection Characteristics
12.6.1
Low-Voltage Detection Reset
(TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Detected voltage
VDL
Released voltage
VDH
12.6.2
Value
-
Min
2.25
Typ
2.45
Max
2.65
-
2.30
2.50
2.70
Unit
Remarks
V
When voltage drops
V
When voltage rises
Interrupt of Low-Voltage Detection
(TA = - 40°C to + 85°C)
Parameter
Symbol
Detected voltage
Released voltage
Detected voltage
VDL
VDH
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
LVD stabilization wait
time
TLVDW
Conditions
SVHI = 0000
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0111
SVHI = 1000
SVHI = 1001
-
Value
Unit
Remarks
V
V
V
When voltage drops
When voltage rises
When voltage drops
Min
2.58
2.67
2.76
Typ
2.8
2.9
3.0
Max
3.02
3.13
3.24
2.85
3.1
3.34
V
When voltage rises
2.94
3.2
3.45
V
When voltage drops
3.04
3.3
3.56
V
When voltage rises
3.31
3.6
3.88
V
When voltage drops
3.40
3.7
3.99
V
When voltage rises
3.40
3.7
3.99
V
When voltage drops
3.50
3.8
4.10
V
When voltage rises
3.68
4.0
4.32
V
When voltage drops
3.77
4.1
4.42
V
When voltage rises
3.77
4.1
4.42
V
When voltage drops
3.86
4.2
4.53
V
When voltage rises
3.86
4.2
4.53
V
When voltage drops
3.96
4.3
4.64
V
When voltage rises
-
-
*1
4032 × tCYCP
μs
*1: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-04683 Rev.*C
Page 119 of 132
MB9B110T Series
12.7
Flash Memory Write/Erase Characteristics
12.7.1
Write / Erase time
(Vcc = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Parameter
Sector erase
time
Value
Typ
*1
*1
Max
Unit
Remarks
s
Includes write time prior to internal erase
Large Sector
0.7
3.7
Small Sector
0.3
1.1
12
384
μs
Not including system-level overhead time.
13.6
68
s
Includes write time prior to internal erase
Half word (16-bit)
write time
Chip erase time
*1: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000
cycle of erase/write.
12.7.2 Write cycles and data hold time
Erase/write cycles
(cycle)
Data hold time
(year)
Remarks
*1
1,000
20
10,000
10
100,000
5
*1
*1
*1: At average + 85°C
Document Number: 002-04683 Rev.*C
Page 120 of 132
MB9B110T Series
12.8
Return Time from Low-Power Consumption Mode
12.8.1
Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
*1
Max
Typ
SLEEP mode
tCYCC
Unit
Remarks
ns
High-speed CR TIMER mode,
40
80
μs
Low-speed CR TIMER mode
453
737
μs
Sub TIMER mode
453
737
μs
STOP mode
453
737
μs
Main TIMER mode,
PLL TIMER mode
Ticnt
*1: The maximum value depends on the accuracy of built-in CR.
*1
Operation example of return from Low-Power consumption mode (by external interrupt )
Ext.INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*1: External interrupt is set to detecting fall edge.
Document Number: 002-04683 Rev.*C
Page 121 of 132
MB9B110T Series
*1
Operation example of return from Low-Power consumption mode (by internal resource interrupt )
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*1: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes. See "CHAPTER 6: Low Power Consumption Mode"
and "Operations of Standby Modes" in FM3 FAMILY PERIPHERAL MANUAL about the return factor from Low-Power
consumption mode.
−
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3 FAMILY PERIPHERAL MANUAL".
Document Number: 002-04683 Rev.*C
Page 122 of 132
MB9B110T Series
12.8.2
Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
*1
Unit
Typ
321
Max
461
321
461
μs
Low-speed CR TIMER mode
441
701
μs
Sub TIMER mode
441
701
μs
STOP mode
441
701
μs
SLEEP mode
Remarks
μs
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Trcnt
*1: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Document Number: 002-04683 Rev.*C
Start
Page 123 of 132
MB9B110T Series
*1
Operation example of return from low power consumption mode (by internal resource reset )
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*1: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.See "CHAPTER 6: Low Power Consumption Mode" and
"Operations of Standby Modes" in FM3 Family PERIPHERAL MANUAL.
−
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3 Family PERIPHERAL MANUAL".
−
The time during the power-on reset/low-voltage detection reset is excluded. See "12.4.6 Power-on Reset Timing in 12.4 AC
Characteristics in Electrical Characteristics" for the detail on the time during the power-on reset/low -voltage detection reset.
−
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time.
−
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-04683 Rev.*C
Page 124 of 132
MB9B110T Series
13.
Ordering Information
Part number
On-chip
Flash
memory
On-chip
SRAM
MB9BF116SPMC-GK7E1
512 Kbyte
64 Kbyte
MB9BF117SPMC-GK7E1
768 Kbyte
96 Kbyte
Package
Packing
Plastic LQFP 144-pin
(0.5 mm pitch), (LQS144)
MB9BF118SPMC-GK7E1
1 Mbyte
128 Kbyte
MB9BF116TPMC-GK7E1
512 Kbyte
64 Kbyte
MB9BF117TPMC-GK7E1
768 Kbyte
96 Kbyte
Plastic LQFP 176-pin
Tray
(0.5 mm pitch), (LQP176)
MB9BF118TPMC-GK7E1
1 Mbyte
128 Kbyte
MB9BF116TBGL-GK7E1
512 Kbyte
64 Kbyte
MB9BF117TBGL-GK7E1
768 Kbyte
96 Kbyte
Plastic PFBGA 192-pin
(0.8 mm pitch), (LBE192)
MB9BF118TBGL-GK7E1
1 Mbyte
Document Number: 002-04683 Rev.*C
128 Kbyte
Page 125 of 132
MB9B110T Series
14.
Package Dimensions
Package Type
Package Code
LQFP 176
LQP176
D
D1
132
4
5 7
89
133
89
88
132
133
88
E1
E
5
7
4
3
6
176
45
1
176
45
44
44
1
2 5 7
e
3
BOTTOM VIEW
0.10 C A-B D
0.20 C A-B D
b
0.08
C A-B
D
8
TOP VIEW
2
A
9
c
A
A'
0.08 C
SIDE VIEW
SYMBOL
L1
0.25
A1
10
L
b
SECTION A-A'
DIMENSIONS
MIN.
NOM. MAX.
0.05
0.15
1.70
A
A1
SEATING
PLANE
b
0.17
c
0.09
0.22
0.20
D
26.00 BSC
D1
24.00 BSC
e
0.50 BSC
E
26.00 BSC
E1
0.27
24.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
0
8
PACKAGE OUTLINE, 176 LEAD LQFP
24.0X24.0X1.7 MM LQP176 REV**
Document Number: 002-04683 Rev.*C
002-15150 **
Page 126 of 132
MB9B110T Series
Package Type
Package Code
LQFP 144
LQS144
4
D
D1
108
4
5 7
7 5
73
109
73
72
D
D1
108
109
72
E1
E
5
7
E
4
4
E1
5
7
3
3
6
144
37
1
144
37
36
1
36
BOTTOM VIEW
2 5 7
e
3
0.10 C A-B D
0.20 C A-B D
b
0.08
TOP VIEW
C A-B
D
8
2
A
9 c
A
A'
0.08 C
SEATING
PLANE
L1
0.25
L
A1
10
b
SECTION A-A'
SIDE VIEW
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
1.70
A
A1
0.05
0.15
b
0.17
c
0.09
0.22
0.27
0.20
D
22.00 BSC
D1
20.00 BSC
e
0.50 BSC
E
22.00 BSC
20.00 BSC
E1
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
PACKAGE OUTLINE, 144 LEAD LQFP
20.0X20.0X1.7 MM LQS144 REV*A
Document Number: 002-04683 Rev.*C
002-13015 *A
Page 127 of 132
MB9B110T Series
Package Type
Package Code
FBGA 192
LBE192
A
0.20 C
14
2X
13
12
7
11
10
9
8
7
6
5
4
3
2
1
P
PIN A1
CORNER
INDEX MARK
8
N
M
L
K
J
H
G
F
E
B
D
C
B
A
7
0.20 C
192xφ b
0.08
C A B
6
2X
TOP VIEW
BOTTOM VIEW
DETAIL A
0.10 C
C
SIDE VIEW
DETAIL A
NOTES
DIMENSIONS
SYMBOL
MIN.
NOM.
A
A1
0.25
D
0.35
1. ALL DIMENSIONS ARE IN MILLIMETERS.
1.45
2. DIMENSIONS AND TOLERANCES METHODS PER ASME Y14.5-2009.
THIS OUTLINE CONFORMS TO JEP95, SECTION 4.5.
0.45
3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-010.
4. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
12.00 BSC
E
12.00 BSC
D1
10.40 BSC
E1
10.40 BSC
MD
14
ME
14
n
192
b
MAX.
0.35
0.45
eD
0.80 BSC
eE
0.80 BSC
SD / SE
0.40 BSC
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
6. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER
IN A PLANE PARALLEL TO DATUM C.
0.55
7. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" =0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
8. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK.
METALLIZED MARK INDENTATION OR OTHER MEANS.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
PACKAGE OUTLINE, 192 BALL FBGA
12.00X12.00X1.45 MM LBE192 REV**
Document Number: 002-04683 Rev.*C
002-13493 **
Page 128 of 132
MB9B110T Series
15.
Major Changes
Spansion Publication Number: DS706-00016
Page
Section
Change Results
-
Initial release
9 to 11
Pin Assignment
Added the description of "Note".
70, 71
Handling Devices
Revision 1.0
Revision 2.0
Block Diagram
Revised the description of "•C pin".
Added the description of "•Base Timer".
Corrected the figure.
TIOA: input → input/output
72
TIOB: output → input
Electrical Characteristics
82
87
89
12.2. Recommended Operating Conditions
12.4. AC Characteristics
12.4.1.Main Clock Input Characteristics
12.4.4.1 Operating Conditions of Main PLL
(In the case of using main clock for input of
PLL)
Added the "Smoothing capacitor (CS)".
Added the footnote.
Added "Internal operating clock frequency (FCM): Master
Clock".
Added "Main PLL clock frequency (FCLKPLL)".
12.4.4.2 Operating Conditions of Main PLL
(In the case of using built-in high-speed CR
clock for the input clock of the main PLL)
12.5. 12-bit A/D Converter
12.5.1 Electrical Characteristics for the
A/D Converter
• Added the Symbol.
• Deleted the following Pin name.
116
"Sampling time"
"Compare clock cycle"
"State transition time to operation permission"
"Analog input capacity"
"Analog input resistance"
Corrected the value of "Compare clock cycle (Tcck)".
Max: 10000 → 2000
Revision 2.1
-
-
Company name and layout design change
Revision 3.0
1
Features
External Bus Interface
9, 10
Pin Assignment
58 to 64
I/O Circuit Type
Added the description of Maximum area size
Added SWCLK and SWDIO and SWO
Added the description of I2C to the type of E, F, I,
Added about +B input
69
Handling Devices
69
Handling Devices
7.3 Crystal oscillator circuit
70
Handling Devices
7.6 C Pin
72
Block Diagram
73
Memory Map
10.1 Memory map(1)
Modified the area of "Extarnal Device Area"
74
Memory Map
10.2 Memory map(2)
Added the summary of Flash memory sector and the note
Document Number: 002-04683 Rev.*C
Added "7.2 Stabilizing power supply voltage"
Added the following description
"Evaluate oscillation of your using crystal oscillator by your
mount board."
Changed the description
Modified the block diagram
Page 129 of 132
MB9B110T Series
Page
80, 81
Section
Electrical Characteristics
12.1 Absolute Maximum Ratings
Change Results
Added the Clamp maximum current
Added the output current of P80, P81, P82, P83
Added about +B input
Modified the minimum value of Analog reference voltage
82
Electrical Characteristics
12.2. Recommended Operation Conditions
Added Smoothing capacitor
Added the note about less than the minimum power
supply voltage
Changed the table format
83, 48
88
Electrical Characteristics
12.3. DC Characteristics
12.3.1 Current rating
Added Main TIMER mode current
Added Flash Memory Current
Moved A/D Converter Current
Electrical Characteristics
Added Frequency stability time at Built to in high to speed CR
12.4. AC Characteristics
12.4.3 Built to in CR Oscillation Characteristics
90
Electrical Characteristics
12.4. AC Characteristics
12.4.6 Power to on Reset Timing
91
Electrical Characteristics
12.4. AC Characteristics
12.4.7 External Bus Timing
106-109
Electrical Characteristics
12.4. AC Characteristics
12.4.9 CSIO/UART Timing
Added Time until releasing Power to on reset
Changed the figure of timing
Modified Data output time
Modified from UART Timing to CSIO/UART Timing
Changed from Internal shift clock operation to Master
mode
Changed from External shift clock operation to Slave
mode
Added the typical value of Integral Nonlinearity, Differential
116
Electrical Characteristics
12.5. 12bit A/D Converter
Nonlinearity, Zero transition voltage and Full to scale
transition voltage
Added Conversion time at AVcc < 4.5 V
Modified Stage transition time to operation permission
Modified the minimum value of Reference voltage
123 to
124
125
Electrical Characteristics
12.8. Return Time from Low to Power
Consumption Mode
Ordering Information
Added Return Time from Low to Power Consumption Mode
Change to full part number
Note:
−
Please see “Document History” about later revised information.
Document Number: 002-04683 Rev.*C
Page 130 of 132
MB9B110T Series
Document History
Document Title: MB9B110T Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller
Document Number: 002-04683
Revision
ECN
Orig. of
Change
Submission
Date
**
-
TOYO
02/10/2015
*A
5200957
TOYO
04/07/2016
Description of Change
Migrated to Cypress and assigned document number 002-04683.
No change to document contents or format.
Updated to Cypress template
Updated “12.4.6 Power-On Reset Timing”. Changed parameter from “Power Supply
rising time(Tr)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and added some
comments (Page 90)
Added Notes for JTAG (Page 57), Changed “J-TAG” to” JTAG” in “4.2 List of Pin
Functions” (Page 37)
Updated Package code and dimensions as follows (Page 7-10, 82, 126-129)
FPT-144P-M08 -> LQS144, FPT-176P-M07 -> LQP176,
BGA-192P-M06 -> LBE192
Corrected the following statement
Analog port input current Analog port input leak current
in chapter 12.5. 12-bit A/D Converter (Page 117)
*B
5560212
YSKA
03/09/2017
Added the Baud rate spec in “12.4.10 CSIO/UART Timing”.(Page 103, 105, 107,
109)
Deleted MPNs below from “13. Ordering Information” (Page 126)
MB9BF116SPMC-GE1, MB9BF116TBGL-GE1, MB9BF116TPMC-GE1,
MB9BF117SPMC-GE1, MB9BF117TBGL-GE1, MB9BF117TPMC-GE1,
MB9BF118SPMC-GE1, MB9BF118TBGL-GE1, MB9BF118TPMC-GE1
Added MPNs below to “13. Ordering Information” (Page 126)
MB9BF116SPMC-GK7E1, MB9BF116TBGL-GK7E1, MB9BF116TPMC-GK7E1,
MB9BF117SPMC-GK7E1, MB9BF117TBGL-GK7E1, MB9BF117TPMC-GK7E1,
MB9BF118SPMC-GK7E1, MB9BF118TBGL-GK7E1, MB9BF118TPMC-GK7E1
*C
5797545
YSAT
Document Number: 002-04683 Rev.*C
07/11/2017
Adapted new Cypress logo
Page 131 of 132
MB9B110T Series
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where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress
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Document Number: 002-04683 Rev.*C
July 11, 2017
Page 132 of 132
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