CY9BF168RPMC-G-JNERE2

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY9B160R Series 32-bit ARM® Cortex®-M4F FM4 Microcontroller The CY9B160R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the ARM® Cortex®-M4F Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I 2C, LIN). Features [SRAM] 32-bit ARM® Cortex®-M4F Core ◼ Up to 160 MHz Frequency Operation This is composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2). SRAM0 is connected to I-code bus or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of Cortex-M4F core. ◼ FPU built-in ◼ SRAM0: Up to 64 Kbytes ◼ Support DSP instruction ◼ SRAM1: Up to 32 Kbytes ◼ Memory Protection Unit (MPU): improves the reliability of an ◼ SRAM2: Up to 32 Kbytes ◼ Integrated Nested Vectored Interrupt Controller (NVIC): 1 External Bus Interface ◼ Processor version: r0p1 embedded system NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels ◼ 24-bit System timer (Sys Tick): System timer for OS task management ◼ Up to 25-bit Address bit ◼ Maximum Access size: 256M byte [Flash memory] These series are based on two independent on-chip Flash memories. ◼ MainFlash memory  Up to 1024 Kbytes  Built-in Flash Accelerator System with 16 Kbytes trace buffer memory  The read access to Flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System.  Security function for code protection ◼ WorkFlash memory Document Number: 002-04918 Rev. *G ◼ Supports Address/Data multiplex ◼ Supports external RDY function ◼ Supports scramble function ◼ Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4 Mbytes units. ◼ Possible to set two kinds of the scramble key ◼ Note: It is necessary to prepare the dedicated software library to use the scramble function. Multi-function Serial Interface (Max 8 channels) Kbytes  Read cycle: • 6 wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz • 4 wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz • 2 wait-cycle: the operation frequency more than 40 MHz, and up to 72 MHz • 0 wait-cycle: the operation frequency up to 40 MHz  Security function is shared with code protection Cypress Semiconductor Corporation ◼ Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM) ◼ 8-/16-bit Data width On-chip Memories  32 ◼ Supports SRAM, NOR, NAND Flash and SDRAM device ◼ 64 bytes with FIFO (the FIFO step numbers are variable depending on the settings of the communication mode or bit length.) ◼ Operation mode is selectable from the followings for each channel.  UART  CSIO  LIN  I2 C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 21, 2021 CY9B160R Series [UART] ◼ Full-duplex double buffer ◼ Selection with or without parity supported ◼ Built-in dedicated baud rate generator ◼ External clock available as a serial clock ◼ Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4) ◼ Various error detect functions available (parity errors, framing errors, and overrun errors) [CSIO] ◼ Full-duplex double buffer ◼ Built-in dedicated baud rate generator ◼ Overrun error detect function available ◼ Serial chip select function (ch.6 and ch.7 only) ◼ Supports high-speed SPI (ch.4 and ch.6 only) ◼ Data length 5 to 16-bit [LIN] ◼ LIN protocol Rev.2.1 supported ◼ Full-duplex double buffer ◼ Master/Slave mode supported ◼ LIN break field generation (can change to 13 to 16-bit length) ◼ LIN break delimiter generation (can change to 1 to 4-bit length) ◼ Various error detect functions available (parity errors, framing errors, and overrun errors) [I2C] DSTC (Descriptor System Data Transfer Controller) (128 channels) The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the Descriptor system and, following the specified contents of the Descriptor which has already been constructed on the memory, can access directly the memory /peripheral device and performs the data transfer operation. It supports the software activation, the hardware activation and the chain activation functions. A/D Converter (Max 24 channels) [12-bit A/D Converter] ◼ Successive Approximation type ◼ Built-in 3 units ◼ Conversion time: 0.5 μs @ 5 V ◼ Priority conversion available (priority at 2 levels) ◼ Scanning conversion mode ◼ Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps) DA converter (Max 2 channels) ◼ R-2R type ◼ 12-bit resolution Base Timer (Max 8 channels) Operation mode is selectable from the followings for each channel. ◼ 16-bit PWM timer ◼ 16-bit PPG timer ◼ 16-/32-bit reload timer ◼ Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) ◼ 16-/32-bit PWC timer ◼ Fast-mode Plus (Fm+) (Max 1000 kbps, only for ch.3 = ch.A General Purpose I/O Port supported and ch.7 = ch.B) supported DMA Controller (8 channels) DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously. ◼ 8 independently configured and operated channels ◼ Transfer can be started by software or request from the builtin peripherals ◼ Transfer address area: 32-bit (4 Gbytes) ◼ Transfer mode: Block transfer/Burst transfer/Demand transfer ◼ Transfer data type: bytes/half-word/word ◼ Transfer block count: 1 to 16 This series can use its pins as general purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated. ◼ Capable of pull-up control per pin ◼ Capable of reading pin level directly ◼ Built-in the port relocate function ◼ Up to 100 high-speed general-purpose I/O ports @ 120 pin Package ◼ Some pin is 5V tolerant I/O. ◼ See “Pin Description” and “I/O Circuit Type” for the corresponding pins. ◼ Number of transfers: 1 to 65536 Document Number: 002-04918 Rev. *G Page 2 of 160 CY9B160R Series Multi-function Timer (Max 2 units) Dual Timer (32-/16-bit Down Counter) The Multi-function timer is composed of the following blocks. ◼ 16-bit free-run timer × 3 ch./unit The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel. ◼ Input capture × 4 ch./unit ◼ Free-running ◼ Output compare × 6 ch./unit ◼ Periodic ( = Reload) ◼ A/D activation compare × 6 ch./unit ◼ One-shot Minimum resolution: 6.25 ns ◼ Waveform generator × 3 ch./unit ◼ 16-bit PPG timer × 3 ch./unit Watch Counter The following function can be used to achieve the motor control. The Watch counter is used for wake up from the low-power consumption mode. It is possible to select the main clock, sub clock, built-in high-speed CR clock or built-in low-speed CR clock as the clock source. ◼ PWM signal output function Interval timer: up to 64s (Max) @ Sub Clock: 32.768 kHz ◼ DC chopper waveform output function ◼ Dead time function ◼ Input capture function ◼ A/D convertor activate function ◼ DTIF (Motor emergency stop) interrupt function Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99. ◼ Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute. ◼ Timer interrupt function after set time or each set time. External Interrupt Controller Unit ◼ External interrupt input pin: Max 16 pins ◼ Include one non-maskable interrupt (NMI) Watchdog Timer (2 channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a “Hardware” watchdog and a “Software” watchdog. “Hardware” watchdog timer is clocked by low-speed internal CR oscillator. Therefore, “Hardware” watchdog is active in any power saving mode except STOP. CRC (Cyclic Redundancy Check) Accelerator ◼ Capable of rewriting the time with continuing the time count. The CRC accelerator helps a verify data transmission or storage integrity. ◼ Leap year automatic count is available. CCITT CRC16 and IEEE-802.3 CRC32 are supported. Quadrature Position/Revolution Counter (QPRC) (Max 2 channels) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter. ◼ The detection edge of the three external event input pins AIN, BIN and ZIN is configurable. ◼ 16-bit position counter ◼ 16-bit revolution counter ◼ Two 16-bit compare registers Document Number: 002-04918 Rev. *G ◼ CCITT CRC16 Generator Polynomial: 0x1021 ◼ IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 SD Card Interface It is possible to use the SD card that conforms to the following standards. ◼ Part 1 Physical Layer Specification version 3.01 ◼ Part E1 SDIO Specification version 3.00 ◼ Part A2 SD Host Controller Standard Specification version 3.00 ◼ 1-bit or 4-bit data bus Page 3 of 160 CY9B160R Series Clock and Reset Low-power Consumption Mode Six low-power consumption modes are supported. [Clocks] Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically selectable. ◼ SLEEP ◼ TIMER ◼ Main clock: 4 MHz to 48 MHz ◼ RTC ◼ Sub Clock: 32.768 kHz ◼ STOP ◼ High-speed internal CR Clock: 4 MHz ◼ Low-speed internal CR Clock: 100 kHz ◼ Main PLL Clock [Resets] ◼ Reset requests from INITX pin ◼ Power on reset ◼ Software reset ◼ Watchdog timers reset ◼ Low voltage detector reset ◼ Clock supervisor reset Clock Super Visor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks. ◼ External OSC clock failure (clock stop) is detected, reset is asserted. ◼ External OSC frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) ◼ Deep standby RTC (selectable from with/without RAM retention) ◼ Deep standby stop (selectable from with/without RAM retention) VBAT The consumption power during the RTC operation can be reduced by supplying the power supply independent from the RTC (calendar circuit)/32 kHz oscillation circuit. The following circuits can also be used. ◼ RTC ◼ 32 kHz oscillation circuit ◼ Power-on circuit ◼ Back up register: 32 bytes ◼ Port circuit Debug ◼ Serial Wire JTAG Debug Port (SWJ-DP) ◼ Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities. This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage has been set, Low-Voltage Detector generates an interrupt or reset. Unique ID ◼ LVD1: error reporting via interrupt Power Supply ◼ LVD2: auto-reset operation Document Number: 002-04918 Rev. *G Unique value of the device (41-bit) is set. Two Power Supplies ◼ Wide range voltage: VCC = 2.7 V to 5.5 V ◼ Power supply for VBAT: VBAT = 2.7 V to 5.5 V Page 4 of 160 CY9B160R Series Contents 1. Product Lineup .................................................................................................................................................................. 7 2. Packages ........................................................................................................................................................................... 8 3. Pin Assignment ................................................................................................................................................................. 9 4. Pin Description ................................................................................................................................................................ 15 5. I/O Circuit Type................................................................................................................................................................ 43 6. Handling Precautions ..................................................................................................................................................... 50 6.1 Precautions for Product Design ................................................................................................................................... 50 6.2 Precautions for Package Mounting .............................................................................................................................. 51 6.3 Precautions for Use Environment ................................................................................................................................ 52 7. Handling Devices ............................................................................................................................................................ 53 8. Block Diagram ................................................................................................................................................................. 56 9. Memory Size .................................................................................................................................................................... 57 10. Memory Map .................................................................................................................................................................... 57 11. Pin Status in Each CPU State ........................................................................................................................................ 60 12. Electrical Characteristics ............................................................................................................................................... 67 12.1 Absolute Maximum Ratings ......................................................................................................................................... 67 12.2 Recommended Operating Conditions.......................................................................................................................... 68 12.3 DC Characteristics....................................................................................................................................................... 71 12.3.1 Current Rating .............................................................................................................................................................. 71 12.3.2 Pin Characteristics ....................................................................................................................................................... 79 12.4 AC Characteristics ....................................................................................................................................................... 81 12.4.1 Main Clock Input Characteristics .................................................................................................................................. 81 12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 82 12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 82 12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL) ......................................... 83 12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR clock for input clock of main PLL) .... 83 12.4.6 Reset Input Characteristics .......................................................................................................................................... 83 12.4.7 Power-on Reset Timing................................................................................................................................................ 84 12.4.8 GPIO Output Characteristics ........................................................................................................................................ 84 12.4.9 External Bus Timing ..................................................................................................................................................... 85 12.4.10 Base Timer Input Timing........................................................................................................................................... 96 12.4.11 CSIO/UART Timing .................................................................................................................................................. 97 12.4.12 External Input Timing .............................................................................................................................................. 130 12.4.13 Quadrature Position/Revolution Counter Timing .................................................................................................... 131 12.4.14 I2C Timing ............................................................................................................................................................... 133 12.4.15 SD Card Interface Timing ....................................................................................................................................... 135 12.4.16 ETM Timing ............................................................................................................................................................ 137 12.4.17 JTAG Timing ........................................................................................................................................................... 138 12.5 12-bit A/D Converter .................................................................................................................................................. 139 12.6 12-bit D/A Converter .................................................................................................................................................. 142 12.7 Low-Voltage Detection Characteristics ...................................................................................................................... 143 12.7.1 Low-Voltage Detection Reset ..................................................................................................................................... 143 12.7.2 Interrupt of Low-Voltage Detection ............................................................................................................................. 143 12.8 MainFlash Memory Write/Erase Characteristics ........................................................................................................ 144 12.9 WorkFlash Memory Write/Erase Characteristics ....................................................................................................... 144 12.10 Standby Recovery Time ............................................................................................................................................ 145 12.10.1 Recovery cause: Interrupt/WKUP ........................................................................................................................... 145 Document Number: 002-04918 Rev. *G Page 5 of 160 CY9B160R Series 12.10.2 Recovery cause: Reset........................................................................................................................................... 147 13. Ordering Information .................................................................................................................................................... 149 14. Package Dimensions .................................................................................................................................................... 150 15. Major Changes .............................................................................................................................................................. 157 Document History ............................................................................................................................................................... 158 Sales, Solutions, and Legal Information........................................................................................................................... 160 Document Number: 002-04918 Rev. *G Page 6 of 160 CY9B160R Series 1. Product Lineup Memory Size Product name MainFlash memory WorkFlash memory On-chip SRAM SRAM0 SRAM1 SRAM1 MB9BF166M/N/R MB9BF167M/N/R 512 Kbytes 32 Kbytes 64 Kbytes 32 Kbytes 16 Kbytes 16 Kbytes 768 Kbytes 32 Kbytes 96 Kbytes 48 Kbytes 24 Kbytes 24 Kbytes MB9BF168M/N/R 1024 Kbytes 32 Kbytes 128 Kbytes 64 Kbytes 32 Kbytes 32 Kbytes Function Product name Pin count CPU Freq. Power supply voltage range DMAC DSTC External Bus Interface MF Timer Multi-function Serial Interface (UART/CSIO/LIN/I2C) Base Timer (PWC/Reload timer/PWM/PPG) A/D activation compare 6 ch. Input capture 4 ch. Free-run timer 3 ch. Output compare 6 ch. Waveform generator 3 ch. PPG 3 ch. SD Card Interface QPRC Dual Timer Real-Time Clock Watch Counter CRC Accelerator Watchdog Timer External Interrupts I/O Ports MB9BF166M MB9BF167M MB9BF168M MB9BF166N MB9BF167N MB9BF168N 80 100/112 Cortex-M4F, MPU, NVIC 128ch. 160 MHz 2.7 V to 5.5 V 8 ch. 128 ch. Addr:25-bit (Max), Addr:19-bit (Max), R/W data: 8-/16-bit R/W data: 8-bit (Max), (Max), CS:9 (Max), CS:5 (Max), SRAM, SRAM, NOR Flash, NOR Flash SDRAM 8 ch. (Max) MB9BF166R MB9BF167R MB9BF168R 120/144 Addr:25-bit (Max), R/W data: 8-/16-bit (Max), CS:9 (Max), SRAM, NOR Flash, NAND Flash, SDRAM 8 ch. (Max) 2 units (Max) 1 unit 2 ch. (Max) 1 unit 1 unit 1 unit Yes 1 ch. (SW) + 1 ch. (HW) 16 pins (Max) + NMI × 1 63 pins (Max) 80 pins (Max) 12-bit A/D Converter 16 ch. (3 units) 24 ch. (3 units) 12-bit D/A Converter 2 units (Max) CSV (Clock Super Visor) LVD (Low-Voltage Detector) High-speed Built-in CR Low-speed Debug Function Unique ID Yes 2 ch. 4 MHz 100 kHz SWJ-DP/ETM Yes 100 pins (Max) Notes: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. − See “12. Electrical Characteristics 12.4. AC Characteristics 12.4.3. Built-in CR Oscillation Characteristics” for accuracy of built-in CR. Document Number: 002-04918 Rev. *G Page 7 of 160 CY9B160R Series 2. Packages MB9BF166M MB9BF167M MB9BF168M MB9BF166N MB9BF167N MB9BF168N MB9BF166R MB9BF167R MB9BF168R LQFP: LQH080 (0.5 mm pitch)  - - LQFP: LQJ080 (0.65 mm pitch)  - - QFP: PQH100 (0.65 mm pitch) -  - LQFP: LQI100 (0.5 mm pitch) -  - LQFP: LQM120 (0.5 mm pitch) - -  BGA: LDC112 (0.5 mm pitch) -  - BGA: LDC144 (0.5 mm pitch) - -  Package Product name : Supported Note: − See “Package Dimensions” for detailed information on each package. Document Number: 002-04918 Rev. *G Page 8 of 160 CY9B160R Series 3. Pin Assignment LQH080/LQJ080 VSS P81 P80 VCC P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0 P61/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0 P62/ADTG_3/SIN5_0/INT04_1/S_WP_0/MOEX_0 P63/CROUT_1/INT03_0/S_CD_0/MWEX_0 P00/TRSTX/MCSX7_0 P01/TCK/SWCLK P02/TDI/MCSX6_0 P03/TMS/SWDIO P04/TDO/SWO P09/AN19/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0 P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0 P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0 P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0 P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0 P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0 VCC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 (TOP VIEW) VCC 1 60 VSS P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0 2 59 P21/AN17/SIN0_0/INT06_1 P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0 3 58 P22/CROUT_0/AN16/TIOB7_1/SOT0_0 P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0 4 57 P23/AN15/TIOA7_1/SCK0_0/RTO00_1 P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0 5 56 P1B/AN11/SCK4_1/IC02_1/MAD18_0 P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0 6 55 P1A/AN10/SOT4_1/IC01_1/MAD17_0 P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 7 54 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0 P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 8 53 P18/AN08/SCK2_2/MAD15_0 P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0 9 52 AVRH P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0 10 51 AVRL P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0 11 50 AVSS P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0 12 49 AVCC P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2 13 48 P17/AN07/SOT2_2/WKUP3/MAD14_0 P3A/TIOA0_1/AIN0_0/RTO00_0 14 47 P16/AN06/SIN2_2/INT14_1/MAD13_0 P3B/TIOA1_1/BIN0_0/RTO01_0 15 46 P15/AN05/SCK0_1/MAD12_0 P3C/TIOA2_1/ZIN0_0/RTO02_0 16 45 P14/AN04/SOT0_1/IC03_2/MAD11_0 P3D/TIOA3_1/RTO03_0/MAD00_0 17 44 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0 P3E/TIOA4_1/RTO04_0/MAD01_0 18 43 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0 P3F/TIOA5_1/RTO05_0/MAD02_0 19 42 P11/AN01/SOT1_1/IC00_2/MAD08_0 VSS 20 41 P10/AN00/SIN1_1/FRCK0_2/INT02_1/MAD07_0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P44/TIOA4_0/RTO14_1/DA0 P45/TIOB0_0/RTO15_1/DA1 INITX P46/X0A P47/X1A P48/VREGCTL P49/VWAKEUP VBAT C VSS VCC P4B/TIOB1_0/SCS7_1/MAD03_0 P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0 P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0 P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 80 Note: − The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-04918 Rev. *G Page 9 of 160 CY9B160R Series LQI100 P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0 P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0 P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0 VCC 79 78 77 76 P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0 P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0 P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0 82 81 80 P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0 P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0 84 83 P04/TDO/SWO P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0 P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0 87 86 85 P02/TDI/MCSX6_0 P03/TMS/SWDIO 90 89 88 VSS P00/TRSTX/MCSX7_0 P01/TCK/SWCLK 92 91 P61/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0 P62/ADTG_3/SIN5_0/INT04_1/S_WP_0/MOEX_0 P63/CROUT_1/INT03_0/S_CD_0/MWEX_0 95 94 93 VCC P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0 97 99 98 96 VSS P81 P80 100 (TOP VIEW) VCC 1 75 VSS P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0 2 74 P20/AN18/AIN1_1/INT05_0/MAD24_0 P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0 3 73 P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0 P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0 4 72 P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1 P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0 5 71 P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0 P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0 6 70 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0 P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 7 69 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0 P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 8 68 P1C/AN12/CTS4_1/IC03_1/MAD19_0 P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0 9 67 P1B/AN11/SCK4_1/IC02_1/MAD18_0 P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0 10 66 P1A/AN10/SOT4_1/IC01_1/MAD17_0 P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0 11 65 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0 P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0 12 64 P18/AN08/SCK2_2/MAD15_0 P34/TIOB4_1/FRCK0_0/MADATA11_0 13 63 AVRH P35/TIOB5_1/IC03_0/INT08_1/MADATA12_0 14 62 AVRL P36/SIN5_2/IC02_0/INT09_1/MADATA13_0 15 61 AVSS P37/SOT5_2/IC01_0/INT05_2/MADATA14_0 16 60 AVCC LQFP - 100 47 48 49 50 MD0 PE2/X0 VSS PE0/MD1 PE3/X1 44 45 46 P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0 P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0 42 43 P4B/TIOB1_0/SCS7_1/MAD03_0 P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0 39 40 41 C VSS VCC 36 37 38 VCC VBAT 51 P49/VWAKEUP 25 34 P10/AN00/SIN1_1/FRCK0_2/INT02_1/MAD07_0 VSS 35 52 P46/X0A 24 P47/X1A P11/AN01/SOT1_1/IC00_2/MAD08_0 P3F/TIOA5_1/RTO05_0/MAD02_0 P48/VREGCTL 53 31 23 32 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0 P3E/TIOA4_1/RTO04_0/MAD01_0 33 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0 54 INITX 55 22 P44/TIOA4_0/RTO14_1/DA0 21 P3D/TIOA3_1/RTO03_0/MAD00_0 P45/TIOB0_0/RTO15_1/DA1 P14/AN04/SOT0_1/IC03_2/MAD11_0 P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0 29 56 30 20 P42/TIOA2_0/RTO12_1/MSDWEX_0 P15/AN05/SCK0_1/MAD12_0 P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0 P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0 57 26 19 27 P16/AN06/SIN2_2/INT14_1/MAD13_0 P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0 28 P17/AN07/SOT2_2/WKUP3/MAD14_0 58 VCC 59 18 P40/TIOA0_0/RTO10_1/INT12_1 17 P41/TIOA1_0/RTO11_1/INT13_1 P38/SCK5_2/IC00_0/INT06_2/MADATA15_0 P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0 Note: − The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-04918 Rev. *G Page 10 of 160 CY9B160R Series LQM120 P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0 P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0 P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0 P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0 VCC 95 94 93 92 91 P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0 P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0 P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0 98 97 99 96 P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0 P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0 P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0 101 100 P03/TMS/SWDIO P04/TDO/SWO 103 102 P00/TRSTX/MCSX7_0 P01/TCK/SWCLK P02/TDI/MCSX6_0 106 105 104 P67/TIOA7_2/SOT3_0 P68/TIOB7_2/SCK3_0/INT00_2 VSS 109 108 107 P64/TIOA7_0/SOT5_1/INT10_2 P65/TIOB7_0/SCK5_1 P66/ADTG_8/SIN3_0/INT11_2 112 111 110 P61/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0 P62/ADTG_3/SIN5_0/INT04_1/S_WP_0/MOEX_0 P63/CROUT_1/SIN5_1/INT03_0/S_CD_0/MWEX_0 115 114 113 P80 VCC P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0 118 117 116 VSS P81 120 119 (TOP VIEW) VCC 1 90 VSS P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0 2 89 P20/AN18/AIN1_1/INT05_0/MAD24_0 P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0 3 88 P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0 P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0 4 87 P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1 P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0 5 86 P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0 P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0 6 85 P24/SIN2_1/RTO01_1/INT01_2 P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 7 84 P25/TIOA5_0/SOT2_1/RTO02_1 P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 8 83 P26/TIOB5_0/SCK2_1/RTO03_1 P57/SCK6_0/MADATA07_0 9 82 P27/TIOA6_2/RTO04_1/INT02_2 P58/SIN4_2/AIN1_0/INT04_2/MADATA08_0 10 81 P1F/ADTG_4/TIOB6_2/RTO05_1 P59/SOT4_2/BIN1_0/INT07_1/MADATA09_0 11 80 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0 P5A/SCK4_2/ZIN1_0/MADATA10_0 12 79 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0 P5B/CTS4_2/MADATA11_0 13 78 P1C/AN12/CTS4_1/IC03_1/MAD19_0 P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA12_0 14 77 P1B/AN11/SCK4_1/IC02_1/MAD18_0 LQFP - 120 P31/TIOB1_1/SIN3_1/INT09_2/MADATA13_0 15 76 P1A/AN10/SOT4_1/IC01_1/MAD17_0 P32/TIOB2_1/SOT3_1/INT10_1/MADATA14_0 16 75 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0 P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA15_0 17 74 P18/AN08/SCK2_2/MAD15_0 59 60 PE3/X1 VSS 56 57 58 PE0/MD1 MD0 P74/SCK2_0/DTTI1X_1 PE2/X0 53 54 55 P73/TIOB6_0/SOT2_0/IC10_1/INT03_2 P70/TIOA4_2/AIN0_1/IC13_1 P71/TIOB4_2/BIN0_1/IC12_1/INT15_1 P72/TIOA6_0/SIN2_0/ZIN0_1/IC11_1/INT14_2 50 51 52 P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0 48 49 P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0 P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0 45 VSS 46 VCC 47 P10/AN00/SIN1_1/FRCK0_2/INT02_1/MAD07_0 61 VCC 62 30 P4B/TIOB1_0/SCS7_1/MAD03_0 29 VSS 42 P11/AN01/SOT1_1/IC00_2/MAD08_0 P3F/TIOA5_1/RTO05_0/MAD02_0 43 63 44 28 C P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0 P3E/TIOA4_1/RTO04_0/MAD01_0 VBAT P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0 64 P49/VWAKEUP 65 27 39 26 P3D/TIOA3_1/RTO03_0/MAD00_0 40 P14/AN04/SOT0_1/IC03_2/MAD11_0 P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0 41 66 P46/X0A 25 P47/X1A P15/AN05/SCK0_1/MAD12_0 P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0 P48/VREGCTL 67 36 24 37 P16/AN06/SIN2_2/INT14_1/MAD13_0 P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0 38 68 INITX 23 P44/TIOA4_0/RTO14_1/DA0 P17/AN07/SOT2_2/WKUP3/MAD14_0 P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0 P45/TIOB0_0/RTO15_1/DA1 AVCC 69 33 70 22 34 21 P38/SCK5_2/IC00_0/INT06_2 35 AVSS P37/SOT5_2/IC01_0/INT05_2/MNREX_0 P41/TIOA1_0/RTO11_1/INT13_1 71 P42/TIOA2_0/RTO12_1/MSDWEX_0 20 P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0 AVRL P36/SIN5_2/IC02_0/INT09_1/MNWEX_0 31 AVRH 72 32 73 19 VCC 18 P40/TIOA0_0/RTO10_1/INT12_1 P34/TIOB4_1/FRCK0_0/MNALE_0 P35/TIOB5_1/IC03_0/INT08_1/MNCLE_0 Note: − The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-04918 Rev. *G Page 11 of 160 CY9B160R Series PQH100 P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0 P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0 VCC VSS P81 P80 VCC P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0 P61/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0 P62/ADTG_3/SIN5_0/INT04_1/S_WP_0/MOEX_0 P63/CROUT_1/INT03_0/S_CD_0/MWEX_0 VSS P00/TRSTX/MCSX7_0 P01/TCK/SWCLK P02/TDI/MCSX6_0 P03/TMS/SWDIO P04/TDO/SWO P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0 P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0 P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0 P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0 P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0 P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0 P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0 P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0 P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0 P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0 VCC VSS P20/AN18/AIN1_1/INT05_0/MAD24_0 P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 (TOP VIEW) 81 50 P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1 P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0 82 49 P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0 P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0 83 48 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0 P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0 84 47 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0 P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 85 46 P1C/AN12/CTS4_1/IC03_1/MAD19_0 P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 86 45 P1B/AN11/SCK4_1/IC02_1/MAD18_0 P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0 87 44 P1A/AN10/SOT4_1/IC01_1/MAD17_0 P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0 88 43 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0 P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0 89 42 P18/AN08/SCK2_2/MAD15_0 P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0 90 41 AVRH QFP - 100 22 23 24 25 26 27 28 29 30 P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0 P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS VCC P10/AN00/SIN1_1/FRCK0_2/INT02_1/MAD07_0 21 18 VSS P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0 17 C 20 16 VBAT 19 15 P49/VWAKEUP VCC 14 P48/VREGCTL P4B/TIOB1_0/SCS7_1/MAD03_0 13 P47/X1A P11/AN01/SOT1_1/IC00_2/MAD08_0 12 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0 31 11 32 INITX 99 P3D/TIOA3_1/RTO03_0/MAD00_0 100 P46/X0A P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0 P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0 10 33 P45/TIOB0_0/RTO15_1/DA1 98 9 P14/AN04/SOT0_1/IC03_2/MAD11_0 P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0 8 P15/AN05/SCK0_1/MAD12_0 34 P44/TIOA4_0/RTO14_1/DA0 35 97 P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0 96 P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0 7 P16/AN06/SIN2_2/INT14_1/MAD13_0 P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0 P42/TIOA2_0/RTO12_1/MSDWEX_0 36 6 95 5 P17/AN07/SOT2_2/WKUP3/MAD14_0 P38/SCK5_2/IC00_0/INT06_2/MADATA15_0 P41/TIOA1_0/RTO11_1/INT13_1 37 P40/TIOA0_0/RTO10_1/INT12_1 94 4 AVCC P37/SOT5_2/IC01_0/INT05_2/MADATA14_0 3 38 VCC 93 2 AVSS P36/SIN5_2/IC02_0/INT09_1/MADATA13_0 1 AVRL 39 VSS 40 92 P3F/TIOA5_1/RTO05_0/MAD02_0 91 P3E/TIOA4_1/RTO04_0/MAD01_0 P34/TIOB4_1/FRCK0_0/MADATA11_0 P35/TIOB5_1/IC03_0/INT08_1/MADATA12_0 Note: − The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-04918 Rev. *G Page 12 of 160 CY9B160R Series LDC112 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 A VSS P81 P80 VCC VSS TCK/ SWCLK VSS AN21 P0A P0B VSS P0E VSS B VCC VSS P60 P61 P62 TRSTX SWDIO AN22 AN19 P0C P0D VSS VCC C P50 P51 P52 AN23 AN20 VSS AN18 AN17 D P53 P54 AN16 AN15 E P55 P56 P30 AN14 AN13 AVRH F P31 P32 P33 AN12 AN11 AVRL G P34 P35 P36 AN10 AN09 AVSS H VSS P37 P38 AN08 AN07 AVCC J P39 P3A P3B AN06 AN05 AN04 K P3C P3D AN03 AN02 L P3E P3F P43 VSS AN01 AN00 M VCC VSS P42 N VSS P40 P41 P63 TMS/ TDI TDO/ SWO index P45 P48 P4B P4C P4E P44 VSS INITX P49 VCC P4D MD1 MD0 VSS VCC VSS X0A X1A VSS VBAT C VSS X0 X1 VSS Note: − The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-04918 Rev. *G Page 13 of 160 CY9B160R Series LDC144 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 A VSS P81 P80 VCC VSS P66 VSS VSS AN21 VSS P0C VCC VSS B VCC VSS P60 P61 P63 P67 TCK/ SWCLK TDO/ SWO AN20 P0B VSS VSS P0E C P50 P51 VSS P62 P64 P68 TDI AN23 AN19 P0D VSS AN18 VSS D P52 P53 P54 VSS P65 AN22 P0A VSS AN17 AN16 AN15 E P55 P56 P57 P58 index P24 P25 P26 P27 F P59 P5A P5B P30 P1F AN14 AN13 AN12 G P31 P32 P33 P34 AN11 AN10 AN09 AVRH H P35 P36 P37 P38 AN08 AN07 AN06 AVRL J P39 P3A P3B P3C AN05 AN04 AN03 AVSS K VSS P3D P3E VSS P45 P49 P4C P70 P72 VSS AN02 AN01 AVCC L P3F P41 VSS P44 VSS P48 P4B P4E P71 P74 VSS AN00 VSS M VCC VSS P43 VSS X1A VSS VSS P4D VCC P73 MD0 VSS VCC N VSS P40 P42 INITX X0A VSS VBAT C VSS MD1 X0 X1 VSS TMS/ TRSTX SWDIO Note: − The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-04918 Rev. *G Page 14 of 160 CY9B160R Series 4. Pin Description List of pin numbers The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. LQFP120 1 LQFP100 1 Pin No LQFP80 QFP100 1 79 BGA112 B1 Pin Name BGA144 B1 VCC I/O circuit type Pin state type - - E K E K E I E I E K E K P50 CTS4_0 AIN0_2 2 2 2 80 C1 C1 RTO10_0 (PPG10_0) INT00_0 MADATA00_0 P51 RTS4_0 BIN0_2 3 3 3 81 C2 C2 RTO11_0 (PPG10_0) INT01_0 MADATA01_0 P52 SCK4_0 (SCL4_0) 4 4 4 82 C3 D1 ZIN0_2 RTO12_0 (PPG12_0) MADATA02_0 P53 TIOA1_2 5 5 5 83 D1 D2 SOT4_0 (SDA4_0) RTO13_0 (PPG12_0) MADATA03_0 P54 TIOB1_2 SIN4_0 6 6 6 84 D2 D3 RTO14_0 (PPG14_0) INT02_0 MADATA04_0 P55 ADTG_1 SIN6_0 7 7 7 85 E1 E1 RTO15_0 (PPG14_0) INT07_2 MADATA05_0 Document Number: 002-04918 Rev. *G Page 15 of 160 CY9B160R Series LQFP120 Pin No LQFP80 QFP100 LQFP100 BGA112 I/O circuit type Pin Name BGA144 Pin state type P56 8 8 8 86 E2 E2 SOT6_0 (SDA6_0) DTTI1X_0 E K E I E K E K E I E I E Q I K INT08_2 MADATA06_0 P57 9 - - - - E3 SCK6_0 (SCL6_0) MADATA07_0 P58 SIN4_2 10 - - - - E4 AIN1_0 INT04_2 MADATA08_0 P59 11 - - - - F1 SOT4_2 (SDA4_2) BIN1_0 INT07_1 MADATA09_0 P5A 12 - - - - F2 SCK4_2 (SCL4_2) ZIN1_0 MADATA10_0 P5B 13 - - - - F3 CTS4_2 MADATA11_0 P30 TIOB0_1 14 14 15 9 9 87 E3 - - - - 10 10 88 F1 F4 RTS4_2 INT15_2 F4 G1 WKUP1 MADATA07_0 MADATA12_0 P31 TIOB1_1 SIN3_1 INT09_2 15 - - Document Number: 002-04918 Rev. *G - - - MADATA08_0 G1 MADATA13_0 Page 16 of 160 CY9B160R Series LQFP120 Pin No LQFP80 QFP100 LQFP100 BGA112 Pin Name BGA144 I/O circuit type Pin state type P32 TIOB2_1 16 16 11 - 11 - 89 - F2 - G2 G2 SOT3_1 (SDA3_1) N K N K E I E K INT10_1 MADATA09_0 MADATA14_0 P33 ADTG_6 17 17 18 18 19 19 12 12 90 F3 - - - - 13 - 91 G1 - - - - 14 - 92 G2 - - Document Number: 002-04918 Rev. *G - - G3 TIOB3_1 SCK3_1 (SCL3_1) G3 INT04_0 MADATA10_0 MADATA15_0 P34 G4 TIOB4_1 G4 FRCK0_0 MADATA11_0 MNALE_0 P35 H1 H1 TIOB5_1 IC03_0 INT08_1 MADATA12_0 MNCLE_0 Page 17 of 160 CY9B160R Series LQFP120 Pin No LQFP80 QFP100 LQFP100 BGA112 Pin Name BGA144 I/O circuit type Pin state type P36 20 20 21 21 22 15 - 16 - 17 - - - - - 93 - 94 - 95 G3 - H2 - H3 - H2 H2 H3 SIN5_2 IC02_0 INT09_1 MADATA13_0 MNWEX_0 P37 H4 E K E K L I G I G I INT05_2 MADATA14_0 MNREX_0 P38 SCK5_2 (SCL5_2) IC00_0 - K SOT5_2 (SDA5_2) IC01_0 H3 E INT06_2 MADATA15_0 P39 ADTG_2 23 18 13 96 J1 J1 DTTI0X_0 RTCCO_2 SUBOUT_2 - MSDCLK_0 P3A TIOA0_1 24 19 14 97 J2 J2 - AIN0_0 RTO00_0 (PPG00_0) MSDCKE_0 P3B TIOA1_1 25 20 15 - Document Number: 002-04918 Rev. *G 98 J3 J3 BIN0_0 RTO01_0 (PPG00_0) MRASX_0 Page 18 of 160 CY9B160R Series LQFP120 Pin No LQFP80 QFP100 LQFP100 BGA112 I/O circuit type Pin Name BGA144 Pin state type P3C TIOA2_1 26 21 16 99 K1 J4 - ZIN0_0 G I G I G I G I VSS - - VCC P40 - - G K G K G I G I RTO02_0 (PPG02_0) MCASX_0 P3D TIOA3_1 27 22 17 100 K2 K2 RTO03_0 (PPG02_0) MAD00_0 P3E TIOA4_1 28 23 18 1 L1 K3 RTO04_0 (PPG04_0) MAD01_0 P3F TIOA5_1 29 24 19 2 L2 L1 30 25 20 3 N1 N1 31 26 - 4 M1 M1 32 27 - 5 N2 N2 RTO05_0 (PPG04_0) MAD02_0 TIOA0_0 RTO10_1 (PPG10_1) INT12_1 P41 TIOA1_0 33 28 - 6 N3 L2 RTO11_1 (PPG10_1) INT13_1 P42 TIOA2_0 34 29 - 7 M3 N3 RTO12_1 (PPG12_1) MSDWEX_0 P43 ADTG_7 35 30 - 8 L3 M3 TIOA3_0 RTO13_1 (PPG12_1) MCSX8_0 Document Number: 002-04918 Rev. *G Page 19 of 160 CY9B160R Series LQFP120 LQFP100 Pin No LQFP80 QFP100 BGA112 I/O circuit type Pin Name BGA144 Pin state type P44 TIOA4_0 36 31 21 9 M4 L4 RTO14_1 (PPG14_1) R J R J B C P S Q T O U O U DA0 P45 TIOB0_0 37 32 22 10 L5 K5 38 33 23 11 M6 N4 RTO15_1 (PPG14_1) DA1 INITX P46 39 34 24 12 N5 N5 40 35 25 13 N6 M5 41 36 26 14 L6 L6 42 37 27 15 M7 K6 43 38 28 16 N8 N7 VBAT - - 44 39 29 17 N9 N8 C - - 45 40 30 18 N10 N9 VSS - - 46 41 31 19 M8 M9 VCC - - E I N I N K I Q X0A P47 X1A P48 VREGCTL P49 VWAKEUP P4B 47 42 32 20 L7 L7 TIOB1_0 SCS7_1 MAD03_0 P4C TIOB2_0 48 43 33 21 L8 K7 SCK7_1 (SCL7_1) AIN1_2 MAD04_0 P4D TIOB3_0 49 44 34 22 M9 M8 SOT7_1 (SDA7_1) BIN1_2 INT13_2 MAD05_0 P4E TIOB4_0 SIN7_1 50 45 35 23 L9 L8 ZIN1_2 FRCK1_1 INT11_1 WKUP2 MAD06_0 Document Number: 002-04918 Rev. *G Page 20 of 160 CY9B160R Series LQFP120 Pin No LQFP80 QFP100 LQFP100 BGA112 I/O circuit type Pin Name BGA144 Pin state type P70 51 - - - - K8 TIOA4_2 AIN0_1 E I E K E K E K E I C E J D A A A B IC13_1 P71 TIOB4_2 52 - - - - L9 BIN0_1 IC12_1 INT15_1 P72 TIOA6_0 53 - - - - K9 SIN2_0 ZIN0_1 IC11_1 INT14_2 P73 TIOB6_0 54 - - - - M10 SOT2_0 (SDA2_0) IC10_1 INT03_2 P74 55 - - - - L10 SCK2_0 (SCL2_0) DTTI1X_1 PE0 56 46 36 24 M10 N10 57 47 37 25 M11 M11 58 48 38 26 N11 N11 59 49 39 27 N12 N12 60 50 40 28 N13 N13 VSS - - 61 51 - 29 M13 M13 VCC - - F M F L MD1 MD0 PE2 X0 PE3 X1 P10 AN00 62 52 41 30 L13 L12 SIN1_1 FRCK0_2 INT02_1 MAD07_0 P11 AN01 63 53 42 31 L12 K12 SOT1_1 (SDA1_1) IC00_2 MAD08_0 Document Number: 002-04918 Rev. *G Page 21 of 160 CY9B160R Series LQFP120 LQFP100 Pin No LQFP80 QFP100 BGA112 I/O circuit type Pin Name BGA144 Pin state type P12 AN02 64 54 43 32 K13 K11 SCK1_1 (SCL1_1) IC01_2 F L F M F L F L F M F P RTCCO_1 SUBOUT_1 MAD09_0 P13 AN03 65 55 44 33 K12 J12 SIN0_1 IC02_2 INT03_1 MAD10_0 P14 AN04 66 56 45 34 J13 J11 SOT0_1 (SDA0_1) IC03_2 MAD11_0 P15 AN05 67 57 46 35 J12 J10 SCK0_1 (SCL0_1) MAD12_0 P16 AN06 68 58 47 36 J11 H12 SIN2_2 INT14_1 MAD13_0 P17 AN07 69 59 48 37 H12 H11 SOT2_2 (SDA2_2) WKUP3 MAD14_0 70 60 49 38 H13 K13 AVCC - - 71 61 50 39 G13 J13 AVSS - - 72 62 51 40 F13 H13 AVRL - - 73 63 52 41 E13 G13 AVRH - - F L P18 AN08 74 64 53 42 H11 H10 SCK2_2 (SCL2_2) MAD15_0 Document Number: 002-04918 Rev. *G Page 22 of 160 CY9B160R Series LQFP120 Pin No LQFP80 QFP100 LQFP100 BGA112 Pin Name BGA144 I/O circuit type Pin state type P19 AN09 75 65 54 43 G12 G12 SIN4_1 IC00_1 F M M L M L F L F L F L E I E K INT05_1 MAD16_0 P1A AN10 76 66 55 44 G11 G11 SOT4_1 (SDA4_1) IC01_1 MAD17_0 P1B AN11 77 67 56 45 F12 G10 SCK4_1 (SCL4_1) IC02_1 MAD18_0 P1C AN12 78 68 - 46 F11 F13 CTS4_1 IC03_1 MAD19_0 P1D AN13 79 69 - 47 E12 F12 RTS4_1 DTTI0X_1 MAD20_0 P1E AN14 80 70 - 48 E11 F11 ADTG_5 FRCK0_1 MAD21_0 P1F ADTG_4 81 - - - - F10 TIOB6_2 RTO05_1 (PPG04_1) P27 TIOA6_2 82 - - - - E13 RTO04_1 (PPG04_1) INT02_2 Document Number: 002-04918 Rev. *G Page 23 of 160 CY9B160R Series LQFP120 Pin No LQFP80 QFP100 LQFP100 BGA112 I/O circuit type Pin Name BGA144 Pin state type P26 TIOB5_0 83 - - - - E12 SCK2_1 (SCL2_1) E I E I E K F L F L F M F M RTO03_1 (PPG02_1) P25 TIOA5_0 84 - - - - E11 SOT2_1 (SDA2_1) RTO02_1 (PPG02_1) P24 SIN2_1 85 - - - - E10 RTO01_1 (PPG00_1) INT01_2 P23 AN15 TIOA7_1 86 71 57 49 D13 D13 SCK0_0 (SCL0_0) RTO00_1 (PPG00_1) - MAD22_0 P22 CROUT_0 87 72 58 AN16 50 D12 D12 TIOB7_1 SOT0_0 (SDA0_0) - ZIN1_1 P21 59 88 73 - AN17 51 C13 D11 SIN0_0 BIN1_1 59 INT06_1 - MAD23_0 P20 AN18 89 74 - 52 C12 C12 AIN1_1 INT05_0 MAD24_0 90 75 60 53 A13 A13 VSS - - 91 76 61 54 B13 A12 VCC - - Document Number: 002-04918 Rev. *G Page 24 of 160 CY9B160R Series LQFP120 Pin No LQFP80 QFP100 LQFP100 BGA112 Pin Name BGA144 I/O circuit type Pin state type P0E TIOB5_2 92 77 62 55 A12 B13 SCS6_1 IC13_0 L I L I L I L K L K M N F N S_CLK_0 MDQM1_0 P0D TIOA5_2 93 78 63 56 B11 C10 SCK6_1 (SCL6_1) IC12_0 S_CMD_0 MDQM0_0 P0C TIOA6_1 94 79 64 57 B10 A11 SOT6_1 (SDA6_1) IC11_0 S_DATA1_0 MALE_0 P0B TIOB6_1 SIN6_1 95 80 65 58 A10 B10 IC10_0 INT00_1 S_DATA0_0 MCSX0_0 P0A SIN1_0 96 81 66 59 A9 D9 FRCK1_0 INT12_2 S_DATA3_0 MCSX1_0 P09 67 AN19 97 82 TRACED0 60 B9 C9 67 TIOA3_2 SOT1_0 (SDA1_0) S_DATA2_0 MCSX5_0 P08 AN20 TRACED1 98 83 - 61 C9 B9 TIOB3_2 SCK1_0 (SCL1_0) MCSX4_0 Document Number: 002-04918 Rev. *G Page 25 of 160 CY9B160R Series LQFP120 Pin No LQFP80 QFP100 LQFP100 BGA112 I/O circuit type Pin Name BGA144 Pin state type P07 AN21 TRACED2 99 84 - 62 A8 A9 TIOA0_2 F N F N F O E G E G E H E G E H - - E K E I SCK7_0 (SCL7_0) MCLKOUT_0 P06 AN22 TRACED3 100 85 - 63 B8 D8 TIOB0_2 SOT7_0 (SDA7_0) MCSX3_0 P05 AN23 ADTG_0 101 86 - 64 C8 C8 TRACECLK SIN7_0 INT01_1 MCSX2_0 P04 102 87 68 65 C7 B8 TDO SWO P03 103 88 69 66 B7 D7 TMS SWDIO P02 104 89 70 67 C6 C7 TDI MCSX6_0 P01 105 90 71 68 A6 B7 TCK SWCLK P00 106 91 72 69 B6 D6 TRSTX MCSX7_0 107 92 - 70 A5 A7 VSS P68 TIOB7_2 108 - - - - C6 SCK3_0 (SCL3_0) INT00_2 P67 109 - - Document Number: 002-04918 Rev. *G - - B6 TIOA7_2 SOT3_0 (SDA3_0) Page 26 of 160 CY9B160R Series LQFP120 Pin No LQFP80 QFP100 LQFP100 BGA112 I/O circuit type Pin Name BGA144 Pin state type P66 110 - - - - A6 ADTG_8 SIN3_0 E K E I E K E K I K E I I F INT11_2 P65 111 - - - - D5 TIOB7_0 SCK5_1 (SCL5_1) P64 TIOA7_0 112 - - - - C5 SOT5_1 (SDA5_1) INT10_2 113 93 73 71 C5 - - - - 93 73 71 P63 CROUT_1 B5 C5 SIN5_1 INT03_0 S_CD_0 MWEX_0 P62 ADTG_3 114 94 74 72 B5 C4 SIN5_0 INT04_1 S_WP_0 MOEX_0 P61 TIOB2_2 115 95 75 73 B4 B4 SOT5_0 (SDA5_0) RTCCO_0 SUBOUT_0 P60 TIOA2_2 116 96 76 74 B3 B3 SCK5_0 (SCL5_0) NMIX WKUP0 MRDY_0 117 97 77 75 A4 A4 VCC - - 118 98 78 76 A3 A3 P80 H R 119 99 79 77 A2 A2 P81 H R Document Number: 002-04918 Rev. *G Page 27 of 160 CY9B160R Series LQFP120 Pin No LQFP80 QFP100 LQFP100 BGA112 I/O circuit type Pin Name BGA144 Pin state type 120 100 80 78 A1 A1 - - - - - - A7 A5 - - - - - - B2 A8 - - - - - - B12 A10 - - - - - - C11 B2 - - - - - - H1 B11 - - - - - - N4 B12 - - - - - - M5 C3 - - - - - - N7 C11 - - - - - - L11 C13 - - - - - - A11 D4 - - - - - - M12 D10 - - - - - - M2 K1 - - - - - - - K4 - - - - - - - K10 - - - - - - - L3 - - - - - - - L5 - - - - - - - L11 - - - - - - - L13 - - - - - - - M2 - - - - - - - M4 - - - - - - - M6 - - - - - - - M7 - - - - - - - M12 - - - - - - - N6 - - Document Number: 002-04918 Rev. *G VSS Page 28 of 160 CY9B160R Series List of pin functions The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin function ADC Base Timer 0 Base Timer 1 Base Timer 2 Pin name ADTG_0 ADTG_1 ADTG_2 ADTG_3 ADTG_4 ADTG_5 ADTG_6 ADTG_7 ADTG_8 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 TIOA0_0 TIOA0_1 TIOA0_2 TIOB0_0 TIOB0_1 TIOB0_2 TIOA1_0 TIOA1_1 TIOA1_2 TIOB1_0 TIOB1_1 TIOB1_2 TIOA2_0 TIOA2_1 TIOA2_2 TIOB2_0 TIOB2_1 TIOB2_2 Document Number: 002-04918 Rev. *G Function description A/D converter external trigger input pin A/D converter analog input pin. Anxx describes ADC ch.xx. Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin Base timer ch.2 TIOB pin Pin No LQFP LQFP LQFP 120 100 80 QFP 100 101 7 23 114 81 80 17 35 110 62 63 64 65 66 67 68 69 74 75 76 77 78 79 80 86 87 88 89 97 98 99 100 101 32 24 99 37 14 100 33 25 5 47 15 6 34 26 116 48 16 115 64 85 96 72 48 90 8 30 31 32 33 34 35 36 37 42 43 44 45 46 47 48 49 50 51 52 60 61 62 63 64 5 97 62 10 87 63 6 98 83 20 88 84 7 99 74 21 89 73 86 7 18 94 70 12 30 52 53 54 55 56 57 58 59 64 65 66 67 68 69 70 71 72 73 74 82 83 84 85 86 27 19 84 32 9 85 28 20 5 42 10 6 29 21 96 43 11 95 7 13 74 12 41 42 43 44 45 46 47 48 53 54 55 56 57 58 59 67 14 22 9 15 5 32 10 6 16 76 33 11 75 BGA 112 C8 E1 J1 B5 E11 F3 L3 L13 L12 K13 K12 J13 J12 J11 H12 H11 G12 G11 F12 F11 E12 E11 D13 D12 C13 C12 B9 C9 A8 B8 C8 N2 J2 A8 L5 E3 B8 N3 J3 D1 L7 F1 D2 M3 K1 B3 L8 F2 B4 BGA 144 C8 E1 J1 C4 F10 F11 G3 M3 A6 L12 K12 K11 J12 J11 J10 H12 H11 H10 G12 G11 G10 F13 F12 F11 D13 D12 D11 C12 C9 B9 A9 D8 C8 N2 J2 A9 K5 F4 D8 L2 J3 D2 L7 G1 D3 N3 J4 B3 K7 G2 B4 Page 29 of 160 CY9B160R Series Pin function Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 Debugger Pin No Pin name TIOA3_0 TIOA3_1 TIOA3_2 TIOB3_0 TIOB3_1 TIOB3_2 TIOA4_0 TIOA4_1 TIOA4_2 TIOB4_0 TIOB4_1 TIOB4_2 TIOA5_0 TIOA5_1 TIOA5_2 TIOB5_0 TIOB5_1 TIOB5_2 TIOA6_0 TIOA6_1 TIOA6_2 TIOB6_0 TIOB6_1 TIOB6_2 TIOA7_0 TIOA7_1 TIOA7_2 TIOB7_0 TIOB7_1 TIOB7_2 SWCLK SWDIO SWO TCK TDI TDO TMS TRACECLK TRACED0 TRACED1 TRACED2 TRACED3 TRSTX Document Number: 002-04918 Rev. *G Function description Base timer ch.3 TIOA pin Base timer ch.3 TIOB pin Base timer ch.4 TIOA pin Base timer ch.4 TIOB pin Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin Base timer ch.6 TIOA pin Base timer ch.6 TIOB pin Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Serial wire viewer output pin JTAG test clock input pin JTAG test data input pin JTAG debug data output pin JTAG test mode state input/output pin Trace CLK output pin of ETM Trace data output pin of ETM JTAG test reset Input pin LQFP LQFP LQFP 120 100 80 QFP 100 35 27 97 49 17 98 36 28 51 50 18 52 84 29 93 83 19 92 53 94 82 54 95 81 112 86 109 111 87 108 105 103 102 105 104 102 103 101 97 98 99 100 106 8 100 60 22 90 61 9 1 23 91 2 56 92 55 57 58 49 50 68 66 65 68 67 65 66 64 60 61 62 63 69 30 22 82 44 12 83 31 23 45 13 24 78 14 77 79 80 71 72 90 88 87 90 89 87 88 86 82 83 84 85 91 17 67 34 12 21 18 35 19 63 62 64 65 57 58 71 69 68 71 70 68 69 72 BGA 112 L3 K2 B9 M9 F3 C9 M4 L1 L9 G1 L2 B11 G2 A12 B10 A10 D13 D12 A6 B7 C7 A6 C6 C7 B7 C8 B9 C9 A8 B8 B6 BGA 144 M3 K2 C9 M8 G3 B9 L4 K3 K8 L8 G4 L9 E11 L1 C10 E12 H1 B13 K9 A11 E13 M10 B10 F10 C5 D13 B6 D5 D12 C6 B7 D7 B8 B7 C7 B8 D7 C8 C9 B9 A9 D8 D6 Page 30 of 160 CY9B160R Series Pin function External Bus Pin No Pin name MAD00_0 MAD01_0 MAD02_0 MAD03_0 MAD04_0 MAD05_0 MAD06_0 MAD07_0 MAD08_0 MAD09_0 MAD10_0 MAD11_0 MAD12_0 MAD13_0 MAD14_0 MAD15_0 MAD16_0 MAD17_0 MAD18_0 MAD19_0 MAD20_0 MAD21_0 MAD22_0 MAD23_0 MAD24_0 Document Number: 002-04918 Rev. *G Function description External bus interface address bus LQFP LQFP LQFP 120 100 80 QFP 100 27 28 29 47 48 49 50 62 63 64 65 66 67 68 69 74 75 76 77 78 79 80 86 88 89 100 1 2 20 21 22 23 30 31 32 33 34 35 36 37 42 43 44 45 46 47 48 49 51 52 22 23 24 42 43 44 45 52 53 54 55 56 57 58 59 64 65 66 67 68 69 70 71 73 74 17 18 19 32 33 34 35 41 42 43 44 45 46 47 48 53 54 55 56 - BGA 112 K2 L1 L2 L7 L8 M9 L9 L13 L12 K13 K12 J13 J12 J11 H12 H11 G12 G11 F12 F11 E12 E11 D13 C13 C12 BGA 144 K2 K3 L1 L7 K7 M8 L8 L12 K12 K11 J12 J11 J10 H12 H11 H10 G12 G11 G10 F13 F12 F11 D13 D11 C12 Page 31 of 160 CY9B160R Series Pin function External Bus Pin No Pin name MCSX0_0 MCSX1_0 MCSX2_0 MCSX3_0 MCSX4_0 MCSX5_0 MCSX6_0 MCSX7_0 MCSX8_0 MADATA00_0 MADATA01_0 MADATA02_0 MADATA03_0 MADATA04_0 MADATA05_0 MADATA06_0 MADATA07_0 MADATA08_0 MADATA09_0 MADATA10_0 MADATA11_0 MADATA12_0 MADATA13_0 MADATA14_0 MADATA15_0 MDQM0_0 MDQM1_0 MALE_0 MRDY_0 MCLKOUT_0 MNALE_0 MNCLE_0 MNREX_0 MNWEX_0 MOEX_0 MWEX_0 MSDCLK_0 MSDCKE_0 External Bus MRASX_0 MCASX_0 MSDWEX_0 Document Number: 002-04918 Rev. *G Function description External bus interface chip select output pin External bus interface data bus (Address / data multiplex bus) External bus interface byte mask signal output pin External bus interface Address Latch enable output signal for multiplex External bus interface external RDY input signal External bus interface external clock output pin External bus interface ALE signal to control NAND Flash output pin External bus interface CLE signal to control NAND Flash output pin External bus interface read enable signal to control NAND Flash External bus interface write enable signal to control NAND Flash External bus interface read enable signal for SRAM External bus interface write enable signal for SRAM SDRAM interface SDRAM clock output pin SDRAM interface SDRAM clock enable pin SDRAM interface SDRAM row address strobe pin SDRAM interface SDRAM column address strobe pin SDRAM interface SDRAM write enable pin LQFP LQFP LQFP 120 100 80 QFP 100 BGA 112 BGA 144 95 96 101 100 98 97 104 106 35 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 93 92 80 81 86 85 83 82 89 91 30 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 78 77 65 66 67 70 72 2 3 4 5 6 7 8 9 10 11 12 63 62 58 59 64 63 61 60 67 69 8 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 56 55 A10 A9 C8 B8 C9 B9 C6 B6 L3 C1 C2 C3 D1 D2 E1 E2 E3 F1 F2 F3 G1 G2 G3 H2 H3 B11 A12 B10 D9 C8 D8 B9 C9 C7 D6 M3 C1 C2 D1 D2 D3 E1 E2 E3 E4 F1 F2 F3 F4 G1 G2 G3 C10 B13 94 79 64 57 B10 A11 116 99 96 84 76 - 74 62 B3 A8 B3 A9 18 - - - - G4 19 - - - - H1 21 - - - - H3 20 - - - - H2 114 94 74 72 B5 C4 113 93 73 71 C5 B5 23 18 - 96 J1 J1 24 19 - 97 J2 J2 25 20 - 98 J3 J3 26 21 - 99 K1 J4 34 29 - 7 M3 N3 Page 32 of 160 CY9B160R Series Pin function External Interrupt Pin No Pin name INT00_0 INT00_1 INT00_2 INT01_0 INT01_1 INT01_2 INT02_0 INT02_1 INT02_2 INT03_0 INT03_1 INT03_2 INT04_0 INT04_1 INT04_2 INT05_0 INT05_1 INT05_2 INT06_1 INT06_2 INT07_1 INT07_2 INT08_1 INT08_2 INT09_1 INT09_2 INT10_1 INT10_2 INT11_1 INT11_2 INT12_1 INT12_2 INT13_1 INT13_2 INT14_1 INT14_2 INT15_1 INT15_2 NMIX Document Number: 002-04918 Rev. *G Function description External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 04 input pin External interrupt request 05 input pin External interrupt request 06 input pin External interrupt request 07 input pin External interrupt request 08 input pin External interrupt request 09 input pin External interrupt request 10 input pin External interrupt request 11 input pin External interrupt request 12 input pin External interrupt request 13 input pin External interrupt request 14 input pin External interrupt request 15 input pin Non-Maskable Interrupt input pin LQFP LQFP LQFP 120 100 80 QFP 100 2 95 108 3 101 85 6 62 82 113 65 54 17 114 10 89 75 21 88 22 11 7 19 8 20 15 16 112 50 110 32 96 33 49 68 53 52 14 116 80 58 81 64 84 30 71 33 90 72 52 43 94 51 95 85 92 86 93 88 89 23 5 59 6 22 36 87 74 2 80 3 86 6 52 93 55 12 94 74 65 16 73 17 7 14 8 15 10 11 45 27 81 28 44 58 9 96 2 65 3 6 41 73 44 12 74 54 59 7 8 10 11 35 66 34 47 9 76 BGA 112 C1 A10 C2 C8 D2 L13 C5 K12 F3 B5 C12 G12 H2 C13 H3 E1 G2 E2 G3 F1 F2 L9 N2 A9 N3 M9 J11 E3 B3 BGA 144 C1 B10 C6 C2 C8 E10 D3 L12 E13 B5 J12 M10 G3 C4 E4 C12 G12 H3 D11 H4 F1 E1 H1 E2 H2 G1 G2 C5 L8 A6 N2 D9 L2 M8 H12 K9 L9 F4 B3 Page 33 of 160 CY9B160R Series Pin No Pin function GPIO Pin name P00 P01 P02 P03 P04 P05 P06 P07 P08 P09 P0A P0B P0C P0D P0E P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P1A P1B P1C P1D P1E P1F P20 P21 P22 P23 P24 P25 P26 P27 Document Number: 002-04918 Rev. *G Function description General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 LQFP LQFP LQFP 120 100 80 QFP 100 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 62 63 64 65 66 67 68 69 74 75 76 77 78 79 80 81 89 88 87 86 85 84 83 82 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 30 31 32 33 34 35 36 37 42 43 44 45 46 47 48 52 51 50 49 - 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 52 53 54 55 56 57 58 59 64 65 66 67 68 69 70 74 73 72 71 - 72 71 70 69 68 67 66 65 64 63 62 41 42 43 44 45 46 47 48 53 54 55 56 59 58 57 - BGA 112 B6 A6 C6 B7 C7 C8 B8 A8 C9 B9 A9 A10 B10 B11 A12 L13 L12 K13 K12 J13 J12 J11 H12 H11 G12 G11 F12 F11 E12 E11 C12 C13 D12 D13 - BGA 144 D6 B7 C7 D7 B8 C8 D8 A9 B9 C9 D9 B10 A11 C10 B13 L12 K12 K11 J12 J11 J10 H12 H11 H10 G12 G11 G10 F13 F12 F11 F10 C12 D11 D12 D13 E10 E11 E12 E13 Page 34 of 160 CY9B160R Series Pin No Pin function GPIO Pin name P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P3A P3B P3C P3D P3E P3F P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P4B P4C P4D P4E P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P5A P5B Document Number: 002-04918 Rev. *G Function description General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 LQFP LQFP LQFP 120 100 80 QFP 100 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 32 33 34 35 36 37 39 40 41 42 47 48 49 50 2 3 4 5 6 7 8 9 10 11 12 13 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 5 6 7 8 9 10 12 13 14 15 20 21 22 23 80 81 82 83 84 85 86 - 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 28 29 30 31 32 34 35 36 37 42 43 44 45 2 3 4 5 6 7 8 - 9 10 11 12 13 14 15 16 17 18 19 21 22 24 25 26 27 32 33 34 35 2 3 4 5 6 7 8 - BGA 112 E3 F1 F2 F3 G1 G2 G3 H2 H3 J1 J2 J3 K1 K2 L1 L2 N2 N3 M3 L3 M4 L5 N5 N6 L6 M7 L7 L8 M9 L9 C1 C2 C3 D1 D2 E1 E2 - BGA 144 F4 G1 G2 G3 G4 H1 H2 H3 H4 J1 J2 J3 J4 K2 K3 L1 N2 L2 N3 M3 L4 K5 N5 M5 L6 K6 L7 K7 M8 L8 C1 C2 D1 D2 D3 E1 E2 E3 E4 F1 F2 F3 Page 35 of 160 CY9B160R Series Pin function GPIO Pin No Pin name P60 P61 P62 P63 P64 P65 P66 P67 P68 P70 P71 P72 P73 P74 P80 P81 PE0 PE2 PE3 SIN0_0 SIN0_1 SOT0_0 (SDA0_0) SOT0_1 Multi- function (SDA0_1) Serial 0 SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) SIN1_0 SIN1_1 SOT1_0 (SDA1_0) SOT1_1 Multi- function (SDA1_1) Serial 1 SCK1_0 (SCL1_0) SCK1_1 (SCL1_1) Document Number: 002-04918 Rev. *G Function description LQFP LQFP LQFP 120 100 80 QFP 100 116 115 114 113 112 111 110 109 108 51 52 53 54 55 118 119 56 58 59 88 65 96 95 94 93 98 99 46 48 49 73 55 76 75 74 73 78 79 36 38 39 59 44 74 73 72 71 76 77 24 26 27 51 33 B3 B4 B5 C5 A3 A2 M10 N11 N12 C13 K12 B3 B4 C4 B5 C5 D5 A6 B6 C6 K8 L9 K9 M10 L10 A3 A2 N10 N11 N12 D11 J12 Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). 87 72 58 50 D12 D12 66 56 45 34 J13 J11 Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SCL0 when it is used in an I2C (operation mode 4). 86 71 57 49 D13 D13 67 57 46 35 J12 J10 96 62 81 52 66 41 59 30 A9 L13 D9 L12 97 82 67 60 B9 C9 63 53 42 31 L12 K12 98 83 - 61 C9 B9 64 54 43 32 K13 K11 General-purpose I/O port 6 General-purpose I/O port 7 General-purpose I/O port 8 General-purpose I/O port E Multi-function serial interface ch.0 input pin Multi-function serial interface ch.1 input pin Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation modes 4) and as SCL1 when it is used in an I2C (operation mode 4). BGA 112 BGA 144 Page 36 of 160 CY9B160R Series Pin function Pin No Pin name SIN2_0 SIN2_1 SIN2_2 SOT2_0 (SDA2_0) SOT2_1 Multi- function (SDA2_1) Serial SOT2_2 2 (SDA2_2) SCK2_0 (SCL2_0) SCK2_1 (SCL2_1) SCK2_2 (SCL2_2) SIN3_0 SIN3_1 SOT3_0 (SDA3_0) Multi- function SOT3_1 Serial (SDA3_1) 3 SCK3_0 (SCL3_0) SCK3_1 (SCL3_1) SIN4_0 SIN4_1 SIN4_2 SOT4_0 (SDA4_0) SOT4_1 (SDA4_1) SOT4_2 (SDA4_2) Multi- function SCK4_0 (SCL4_0) Serial 4 SCK4_1 (SCL4_1) SCK4_2 (SCL4_2) CTS4_0 CTS4_1 CTS4_2 RTS4_0 RTS4_1 RTS4_2 Document Number: 002-04918 Rev. *G Function description Multi-function serial interface ch.2 input pin Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a CSIO (operation modes 2) and as SCL2 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 input pin Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation modes 2) and as SCL3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 input pin Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a CSIO (operation modes 2) and as SCL4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 CTS input pin Multi-function serial interface ch.4 RTS output pin LQFP LQFP LQFP 120 100 80 QFP 100 BGA 112 BGA 144 53 85 68 58 47 36 J11 K9 E10 H12 54 - - - - M10 84 - - - - E11 69 59 48 37 H12 H11 55 - - - - L10 83 - - - - E12 74 64 53 42 H11 H10 110 15 10 10 88 F1 A6 G1 109 - - - - B6 16 11 11 89 F2 G2 108 - - - - C6 17 12 12 90 F3 G3 6 75 10 6 65 - 6 54 - 84 43 - D2 G12 - D3 G12 E4 5 5 5 83 D1 D2 76 66 55 44 G11 G11 11 - - - - F1 4 4 4 82 C3 D1 77 67 56 45 F12 G10 12 - - - - F2 2 78 13 3 79 14 2 68 3 69 9 2 3 9 80 46 81 47 87 C1 F11 C2 E12 E3 C1 F13 F3 C2 F12 F4 Page 37 of 160 CY9B160R Series Pin function Pin No Pin name SIN5_0 SIN5_1 SIN5_2 SOT5_0 (SDA5_0) SOT5_1 Multi- function (SDA5_1) Serial SOT5_2 5 (SDA5_2) SCK5_0 (SCL5_0) SCK5_1 (SCL5_1) SCK5_2 (SCL5_2) SIN6_0 SIN6_1 SOT6_0 (SDA6_0) SOT6_1 Multi- function (SDA6_1) Serial SCK6_0 6 (SCL6_0) SCK6_1 (SCL6_1) Function description Multi-function serial interface ch.5 input pin Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a CSIO (operation modes 2) and as SCL5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 input pin Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a CSIO (operation modes 2) and as SCL6 when it is used in an I2C (operation mode 4). LQFP LQFP LQFP 120 100 80 QFP 100 BGA 112 BGA 144 114 113 20 94 15 74 - 72 93 B5 G3 C4 B5 H2 115 95 75 73 B4 B4 112 - - - - C5 21 16 - 94 H2 H3 116 96 76 74 B3 B3 111 - - - - D5 22 17 - 95 H3 H4 7 95 7 80 7 65 85 58 E1 A10 E1 B10 8 8 8 86 E2 E2 94 79 64 57 B10 A11 9 - - - - E3 93 78 63 56 B11 C10 SCS6_1 Multi-function serial interface ch.6 serial chip select pin 92 77 62 55 A12 B13 SIN7_0 SIN7_1 Multi-function serial interface ch.7 input pin 101 50 86 45 35 64 23 C8 L9 C8 L8 100 85 - 63 B8 D8 49 44 34 22 M9 M8 99 84 - 62 A8 A9 48 43 33 21 L8 K7 47 42 32 20 L7 L7 SOT7_0 (SDA7_0) SOT7_1 (SDA7_1) Multi- function Serial SCK7_0 7 (SCL7_0) SCK7_1 (SCL7_1) SCS7_1 Document Number: 002-04918 Rev. *G Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a CSIO (operation modes 2) and as SCL7 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 serial chip select pin Page 38 of 160 CY9B160R Series Pin function Pin No Pin name DTTI0X_0 DTTI0X_1 Multifunction Timer 0 FRCK0_0 FRCK0_1 FRCK0_2 IC00_0 IC00_1 IC00_2 IC01_0 IC01_1 IC01_2 IC02_0 IC02_1 IC02_2 IC03_0 IC03_1 IC03_2 RTO00_0 (PPG00_0) RTO00_1 (PPG00_1) RTO01_0 (PPG00_0) RTO01_1 (PPG00_1) RTO02_0 (PPG02_0) RTO02_1 (PPG02_1) RTO03_0 (PPG02_0) RTO03_1 (PPG02_1) RTO04_0 (PPG04_0) RTO04_1 (PPG04_1) RTO05_0 (PPG04_0) RTO05_1 (PPG04_1) Document Number: 002-04918 Rev. *G Function description Input signal controlling wave form generator outputs RTO00 to RTO05 of Multi-function timer 0. 16-bit free-run timer ch.0 external clock input pin 16-bit input capture ch.0 input pin of Multifunction timer 0. Icxx describes channel number. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. LQFP LQFP LQFP 120 100 80 QFP 100 BGA 112 BGA 144 23 18 13 96 J1 J1 79 69 - 47 E12 F12 18 80 62 22 75 63 21 76 64 20 77 65 19 78 66 13 70 52 17 65 53 16 66 54 15 67 55 14 68 56 41 54 42 55 43 56 44 45 91 48 30 95 43 31 94 44 32 93 45 33 92 46 34 G1 E11 L13 H3 G12 L12 H2 G11 K13 G3 F12 K12 G2 F11 J13 G4 F11 L12 H4 G12 K12 H3 G11 K11 H2 G10 J12 H1 F13 J11 24 19 14 97 J2 J2 86 71 57 49 D13 D13 25 20 15 98 J3 J3 85 - - - - E10 26 21 16 99 K1 J4 84 - - - - E11 27 22 17 100 K2 K2 83 - - - - E12 28 23 18 1 L1 K3 82 - - - - E13 29 24 19 2 L2 L1 81 - - - - F10 Page 39 of 160 CY9B160R Series Pin function Pin No Pin name DTTI1X_0 DTTI1X_1 Multifunction Timer 1 Quadrature Position/ Revolution Counter 0 Quadrature Position/ Revolution Counter 1 FRCK1_0 FRCK1_1 IC10_0 IC10_1 IC11_0 IC11_1 IC12_0 IC12_1 IC13_0 IC13_1 RTO10_0 (PPG10_0) RTO10_1 (PPG10_1) RTO11_0 (PPG10_0) RTO11_1 (PPG10_1) RTO12_0 (PPG12_0) RTO12_1 (PPG12_1) RTO13_0 (PPG12_0) RTO13_1 (PPG12_1) RTO14_0 (PPG14_0) RTO14_1 (PPG14_1) RTO15_0 (PPG14_0) RTO15_1 (PPG14_1) AIN0_0 AIN0_1 AIN0_2 BIN0_0 BIN0_1 BIN0_2 ZIN0_0 ZIN0_1 ZIN0_2 AIN1_0 AIN1_1 AIN1_2 BIN1_0 BIN1_1 BIN1_2 ZIN1_0 ZIN1_1 ZIN1_2 Document Number: 002-04918 Rev. *G Function description Input signal controlling wave form generator outputs RTO10 to RTO15 of Multi-function timer 1. 16-bit free-run timer ch.1 external clock input pin 16-bit input capture ch.1 input pin of Multifunction timer 1. Icxx describes channel number. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. QPRC ch.0 AIN input pin QPRC ch.0 BIN input pin QPRC ch.0 ZIN input pin QPRC ch.1 AIN input pin QPRC ch.1 BIN input pin QPRC ch.1 ZIN input pin LQFP LQFP LQFP 120 100 80 QFP 100 BGA 112 BGA 144 8 8 8 86 E2 E2 55 - - - - L10 96 50 95 54 94 53 93 52 92 51 81 45 80 79 78 77 - 66 35 65 64 63 62 - 59 23 58 57 56 55 - A9 L9 A10 B10 B11 A12 - D9 L8 B10 M10 A11 K9 C10 L9 B13 K8 2 2 2 80 C1 C1 32 27 - 5 N2 N2 3 3 3 81 C2 C2 33 28 - 6 N3 L2 4 4 4 82 C3 D1 34 29 - 7 M3 N3 5 5 5 83 D1 D2 35 30 - 8 L3 M3 6 6 6 84 D2 D3 36 31 21 9 M4 L4 7 7 7 85 E1 E1 37 32 22 10 L5 K5 24 51 2 25 52 3 26 53 4 10 89 48 11 88 49 12 87 50 19 2 20 3 21 4 74 43 73 44 72 45 14 2 15 3 16 4 33 34 35 97 80 98 81 99 82 52 21 51 22 50 23 J2 C1 J3 C2 K1 C3 C12 L8 C13 M9 D12 L9 J2 K8 C1 J3 L9 C2 J4 K9 D1 E4 C12 K7 F1 D11 M8 F2 D12 L8 Page 40 of 160 CY9B160R Series Pin No Pin function Pin name RTCCO_0 RTCCO_1 RTCCO_2 Real-time clock SUBOUT_0 SUBOUT_1 SUBOUT_2 WKUP0 Low-Power WKUP1 Consumption WKUP2 Mode WKUP3 DA0 DAC DA1 VREGCTL VBAT VWAKEUP S_CLK_0 S_CMD_0 SD I/F S_DATA1_0 S_DATA0_0 S_DATA3_0 S_DATA2_0 S_CD_0 S_WP_0 Reset INITX MD1 Mode MD0 Power VCC Document Number: 002-04918 Rev. *G Function description 0.5 seconds pulse output pin of Real-time clock Sub clock output pin Deep standby mode return signal input pin 0 Deep standby mode return signal input pin 1 Deep standby mode return signal input pin 2 Deep standby mode return signal input pin 3 D/A converter ch.0 analog output pin D/A converter ch.1 analog output pin On-board regulator control pin The return signal input pin from a hibernation state SD memory card interface SD memory card clock output pin SD memory card interface SD memory card command output SD memory card interface SD memory card data bus SD memory card interface SD memory card detection pin SD memory card interface SD memory card write protection External Reset Input pin. A reset is valid when INITX = “L”. Mode 1 pin. During serial programming to Flash memory, MD1 = “L” must be input. Mode 0 pin. During normal operation, MD0 = “L” must be input. During serial programming to Flash memory, MD0 = “H” must be input. Power supply Pin LQFP LQFP LQFP 120 100 80 QFP 100 BGA 112 BGA 144 115 64 23 115 64 23 116 14 50 69 36 37 41 95 54 18 95 54 18 96 9 45 59 31 32 36 75 43 13 75 43 13 76 9 35 48 21 22 26 73 32 96 73 32 96 74 87 23 37 9 10 14 B4 K13 J1 B4 K13 J1 B3 E3 L9 H12 M4 L5 L6 B4 K11 J1 B4 K11 J1 B3 F4 L8 H11 L4 K5 L6 42 37 27 15 M7 K6 92 77 62 55 A12 B13 93 78 63 56 B11 C10 94 95 96 97 79 80 81 82 64 65 66 67 57 58 59 60 B10 A10 A9 B9 A11 B10 D9 C9 113 93 73 71 C5 B5 114 94 74 72 B5 C4 38 33 23 11 M6 N4 56 46 36 24 M10 N10 57 47 37 25 M11 M11 1 31 46 61 91 117 1 26 41 51 76 97 1 31 61 77 79 4 19 29 54 75 B1 M1 M8 M13 B13 A4 B1 M1 M9 M13 A12 A4 Page 41 of 160 CY9B160R Series Pin No Pin function Pin name Function description GND VSS GND Pin GND VSS GND Pin X0 X1 X0A X1A CROUT_0 CROUT_1 Main clock (oscillation) input pin Main clock (oscillation) I/O pin Sub clock (oscillation) input pin Sub clock (oscillation) I/O pin Clock ADC Power VBAT Power ADC GND C pin AVCC AVRL AVRH VBAT AVSS C Built-in high-speed CR-osc clock output port A/D converter and D/A converter analog power supply pin A/D converter analog reference voltage input pin A/D converter analog reference voltage input pin VBAT power supply pin. Backup power supply (battery etc.) and system power supply. A/D converter and D/A converter GND pin Power supply stabilization capacity pin LQFP LQFP LQFP 120 100 80 QFP 100 BGA 112 BGA 144 107 30 45 60 90 120 58 59 39 40 87 113 92 25 40 50 75 100 48 49 34 35 72 93 20 30 40 60 80 38 39 24 25 58 73 70 3 18 28 53 78 26 27 12 13 50 71 A5 N1 N10 N13 A13 A1 A7 B2 B12 C11 H1 N4 M5 N7 L11 A11 M12 M2 N11 N12 N5 N6 D12 C5 A7 N1 N9 N13 A13 A1 A5 A8 A10 B2 B11 B12 C3 C11 C13 D4 D10 K1 K4 K10 L3 L5 L11 L13 M2 M4 M6 M7 M12 N6 N11 N12 N5 M5 D12 B5 70 60 49 38 H13 K13 72 73 62 63 51 52 40 41 F13 E13 H13 G13 43 38 28 16 N8 N7 71 61 50 39 G13 J13 44 39 29 17 N9 N8 Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: 002-04918 Rev. *G Page 42 of 160 CY9B160R Series 5. I/O Circuit Type Type A Circuit Remarks It is possible to select the main oscillation / GPIO function Pull-up When the main oscillation is selected. resistor P-ch P-ch Digital output X1 • Oscillation feedback resistor : Approximately 1 MΩ • With Standby mode control When the GPIO is selected. N-ch Digital output R Pull-up resistor control Digital input • • • • • CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 Kω • IOH = -4 Ma, IOL = 4 Ma Standby mode control Clock input Feedback resistor Standby mode control Digital input Standby mode control Pull-up resistor R P-ch P-ch Digital output N-ch Digital output X0 Pull-up resistor control B • CMOS level hysteresis input • Pull-up resistor : Approximately 50 Kω Pull-up resistor Digital input Document Number: 002-04918 Rev. *G Page 43 of 160 CY9B160R Series Type C Circuit Digital input Remarks • Open drain output • CMOS level hysteresis input Digital output N-ch E • • • • • P-ch P-ch N-ch Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 Kω • IOH = -4 Ma, IOL = 4 Ma Digital output R Pull-up resistor control Digital input Standby mode control F P-ch P-ch N-ch Digital output • • • • • • • CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 Kω • IOH = -4 Ma, IOL = 4 Ma Digital output Pull-up resistor control R Digital input Standby mode control Analog input Input control Document Number: 002-04918 Rev. *G Page 44 of 160 CY9B160R Series Type G Circuit Remarks CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 Kω • IOH = -12 Ma, IOL = 12 Ma • • • • • P-ch Digital output P-ch N-ch Digital output R Pull-up resistor control Digital input Standby mode control H • • • • P-ch N-ch CMOS level output CMOS level hysteresis input With standby mode control IOH = -20.5 Ma, IOL = 18.5 Ma Digital output Digital output R Digital input Standby mode Control Document Number: 002-04918 Rev. *G Page 45 of 160 CY9B160R Series Type I Circuit Remarks • • • • • P-ch P-ch N-ch Digital output CMOS level output CMOS level hysteresis input 5V tolerant With standby mode control Pull-up resistor : Approximately 50 Kω • IOH = -4 Ma, IOL = 4 Ma • Available to control of PZR registers. Digital output R Pull-up resistor control Digital input Standby mode control J CMOS level hysteresis input Mode input L • • • • • P-ch P-ch N-ch R Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 Kω • IOH = -8 Ma, IOL = 8 Ma Digital output Pull-up resistor control Digital input Standby mode control Document Number: 002-04918 Rev. *G Page 46 of 160 CY9B160R Series Type M Circuit P-ch P-ch N-ch Remarks Digital output • • • • • • • CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 Kω • IOH = -8 Ma, IOL = 8 Ma Digital output Pull-up resistor control Digital input R Standby mode control Analog input Input control N P-ch P-ch N-ch R N-ch Pull-up resistor control Digital output Digital output Fast mode control Digital input ・ CMOS level output ・ CMOS level hysteresis input ・ 5V tolerant ・ Pull-up resistor control ・ Standby mode control ・ Pull-up resistor: approximately 50 Kω ・ IOH = -4 Ma, IOL = 4 Ma (GPIO) ・ IOL = 20 Ma (Fast mode Plus) ・ Available to control of PZR register (pseudo-open drain control) ・ For PZR registers, refer to GPIO in the FM4 Family Peripheral Manual Main Part (002-04856). ・ When this pin is used as an I2C pin, the digital output P-ch transistor is always off. Standby mode control Document Number: 002-04918 Rev. *G Page 47 of 160 CY9B160R Series Type O Circuit P-ch P-ch N-ch Remarks Pull-up resistor control Digital output Digital output R Digital input P P-ch P-ch X0A N-ch Pull-up resistor control Digital output ・ CMOS level output ・ CMOS level hysteresis input ・ 5 V tolerant ・ Pull-up resistor control ・ Pull-up resistor: approximately 50 Kω ・ IOH = -4 Ma, IOL = 4 Ma ・ Available to control of PZR register (pseudo-open drain control) ・ For PZR registers, refer to GPIO in the “FM4 Family Peripheral Manual Main Part (002-04856)”. ・ For I/O setting, refer to VBAT Domain in the FM4 Family Peripheral Manual Main Part (002-04856). • • • • • CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 Kω • IOH = -4 Ma, IOL = 4 Ma • For I/O setting, refer to VBAT Domain in the Peripheral Manual Digital output R Digital input Standby mode control OSC Document Number: 002-04918 Rev. *G Page 48 of 160 CY9B160R Series Type Q Circuit Pull-up resistor control Digital output P-ch X1A Remarks It is possible to select the sub oscillation / GPIO function P-ch When the sub oscillation is selected. • Oscillation feedback resistor : Approximately 10 MΩ • With Standby mode control • When the GPIO is selected. Digital output N-ch • • • • • R Digital input Standby mode control OSC CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 Kω • IOH = -4 Ma, IOL = 4 Ma • For I/O setting, refer to VBAT Domain in the Peripheral Manual RX Standby mode control Clock input R P-ch P-ch N-ch Pull-up resistor control Digital output Digital output • • • • • • CMOS level output CMOS level hysteresis input Analog output With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 Kω • IOH = -12 Ma, IOL = 12 Ma (4.5 V to 5.5 V) • IOH = -8 Ma, IOL = 8 Ma (2.7 V to 4.5 V) R Digital input Standby mode control Analog output Document Number: 002-04918 Rev. *G Page 49 of 160 CY9B160R Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred Ma to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Document Number: 002-04918 Rev. *G Page 50 of 160 CY9B160R Series Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress’ recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Document Number: 002-04918 Rev. *G Page 51 of 160 CY9B160R Series Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of 52tyrofoam or other highly static-prone materials for storage of completed board assemblies. 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-04918 Rev. *G Page 52 of 160 CY9B160R Series 7. Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this device. Power supply pins A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub crystal oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. • Surface mount type Size: Load capacitance: More than 3.2 mm × 1.5 mm Approximately 6 Pf to 7 Pf • Lead type Load capacitance: Approximately 6 Pf to 7 Pf Using an external clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. ⚫ Example of Using an External Clock Device X0(X0A) Can be used as general-purpose I/O ports. Document Number: 002-04918 Rev. *G X1(PE3), X1A (P47) Set as External clock input Page 53 of 160 CY9B160R Series Handling when using Multi-function serial pin as I2C pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 Μf would be recommended for this series. C Device CS VSS GND Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. The device operates normally after all power on. VBAT only Power-on is possible when VBAT and VCC turns Power-on and Hibernation control is setting and then VCC turns Power-off. About Hibernation control, see Chapter 7-2: VBAT Domain(A) in FM4 Family Peripheral Manual Main Part(002-04856). If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS. Turning on : VBAT → VCC VCC → AVCC → AVRH Turning off : AVRH → AVCC → VCC VCC → VBAT Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Document Number: 002-04918 Rev. *G Page 54 of 160 CY9B160R Series Pull-Up function of 5V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O. Adjoining wiring on circuit board If wiring of the crystal oscillation circuit X1A adjoins and also runs in parallel with the wiring of P48/VREGCTL, there is a possibility that the oscillation erroneously counts because X1A has noise with the change of P48/VREGCTL. Keep as much distance as possible between both wirings and insert the ground pattern between them in order to avoid this possibility. Device P46/ X0A P47/ X1A P48/ P49/ VREGCTL VWAKEUP Not allowed to run both wirings in parallel Ground Insert the ground pattern Handling when using debug pins When debug pins(TDO/TMS/TDI/TCK/TRSTX or SWO/SWDIO/SWCLK) are set to GPIO or other peripheral functions, only set them as output, do not set them as input. Document Number: 002-04918 Rev. *G Page 55 of 160 CY9B160R Series 8. Block Diagram MB9BF166M/N/R, F167M/N/R, F168M/N/R TRSTX,TCK, TDI,TMS TDO SWJ-DP ETM* TRACEDx, TRACECLK TPIU* ROM Table SRAM0 32/48/64 Kbytes SRAM1 16/24/32 Kbytes Multi-layer AHB (Max 160 MHz) Cortex-M4　Core I @160 MHz(Max) D FPU MPU NVIC Sys AHB-APB Bridge: APB0(Max 80 MHz) Dual-Timer Watchdog Timer (Software) Clock Reset Generator INITX Watchdog Timer (Hardware) SRAM2 16/24/32 Kbytes MainFlash I/F Trace Buffer (16 Kbytes) Security WorkFlash I/F MainFlash 1 Mbytes/ 768 Kbytes/ 512 Kbytes WorkFlash 32 Kbytes DMAC 8ch. CSV DSTC CLK AHB-AHB Bridge SD-CARD I/F Source Clock X0 X1 X0A X1A Main Osc PLL VBAT Domain Sub Osc CR 100 kHz CR 4 MHz PIN-Function-Ctrl TIOAx TIOBx AINx BINx ZINx 12-bit A/D Converter Unit 0 Unit 2 Base Timer 16-bit 16ch./ 32-bit 8ch. QPRC 2ch. A/D Activation Compare 6ch. IC0x FRCK0 16-bit Input Capture 4ch. LVD Ctrl LVD IRQ-Monitor Regulator MCSXx,MDQMx, MOEX,MWEX, MALE,MRDY, MNALE,MNCLE, MNWEX,MNREX, MCLKOUT,MSDWEX, MSDCLK,MSDCKE, MRASX,MCASX C CRC Accelerator Watch Counter Deep Standby Ctrl WKUPx Peripheral Clock Gating Low-speed CR Prescaler VBAT Domain Real-Time Clock Port Ctrl. VWAKEUP VREGCTL RTCCO, SUBOUT External Interrupt Controller 16pin + NMI INTx NMIX MODE-Ctrl MD0, MD1 Waveform Generator 3ch. Multi-function Serial I/F 8ch. HW flow control(ch.4) SCKx SINx SOTx CTS4 RTS4 16-bit PPG 3ch. 12-bit D/A Converter 2units DAx 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. DTTI0X RTO0x . . . PEx MADATAx Power-On Reset Unit 1 AHB-APB Bridge : APB2 (Max 80 MHz) ADTGx External Bus I/F AHB-APB Bridge : APB1 (Max 160 MHz) ANxx P0x, P1x, MADx CROUT AVCC, AVSS, AVRH GPIO S_CLK,S_CMD S_DATAx S_CD,S_WP Multi-function Timer × 2 *: For the MB9BF166M, MB9BF167M and MB9BF168M, ETM is not available. Document Number: 002-04918 Rev. *G Page 56 of 160 CY9B160R Series 9. Memory Size See “Memory size” in “Product Lineup” to confirm the memory size. 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF Reserved 0x4007_0000 0x4006_F000 0x4006_E000 Reserved 0xFFFF_FFFF Reserved 0xE010_0000 0xE000_0000 GPIO SD-Card I/F Cortex-M4 Private Peripherals 0x4006_2000 0x4006_1000 0x4006_0000 DSTC DMAC Reserved 0x4004_0000 0x4003_F000 External Device Area 0x6000_0000 Reserved 0x4400_0000 0x4200_0000 32 Mbytes Bit band alias Peripherals 0x4000_0000 Reserved 0x2400_0000 0x2200_0000 32 Mbytes Bit band alias Reserved 0x2010_0000 0x200E_0000 0x200C_0000 See "⚫Memory Map (2)" for the memory size details. 0x2004_8000 0x2004_0000 0x2003_8000 0x2000_0000 0x1FFF_0000 0x0050_0000 0x0040_0000 WorkFlash I/F WorkFlash Reserved SRAM2 SRAM1 Reserved SRAM0 Reserved Security/CR Trim MainFlash 0x0000_0000 Reserved 0x4003_C800 0x4003_C100 Peripheral Clock Gating 0x4003_C000 Low Speed CR Prescaler 0x4003_B000 RTC/Port Ctrl 0x4003_A000 Watch Counter 0x4003_9000 CRC 0x4003_8000 MFS Reserved 0x4003_6000 0x4003_5000 LVD/DS mode 0x4003_4000 Reserved 0x4003_3000 D/AC Reserved 0x4003_2000 0x4003_1000 Int-Req.Read 0x4003_0000 EXTI 0x4002_F000 Reserved 0x4002_E000 CR Trim 0x4002_8000 0x4002_7000 0x4002_6000 0x4002_5000 0x4002_4000 0x4002_2000 0x4002_1000 0x4002_0000 0x4001_6000 0x4001_5000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 Document Number: 002-04918 Rev. *G EXT-bus I/F Reserved A/DC QPRC Base Timer PPG Reserved MFT Unit1 MFT Unit0 Reserved Dual Timer Reserved SW WDT HW WDT Clock/Reset Reserved MainFlash I/F Page 57 of 160 CY9B160R Series Memory Map (2) MB9BF168M/N/R 0x2008_0000 MB9BF167M/N/R 0x2008_0000 Reserved 0x200C_8000 0x200C_0000 0x2008_0000 Reserved 0x200C_8000 WorkFlash 32 Kbytes MB9BF166M/N/R 0x200C_0000 Reserved Reserved 0x200C_8000 WorkFlash 32 Kbytes 0x200C_0000 Reserved 0x2004_8000 WorkFlash 32 Kbytes Reserved 0x2004_6000 SRAM2 32 Kbytes 0x2004_0000 0x2004_0000 SRAM1 32 Kbytes 0x2003_A000 SRAM2 24 Kbytes SRAM1 24 Kbytes 0x2004_4000 0x2004_0000 0x2003_C000 SRAM2 16 Kbytes SRAM1 16 Kbytes 0x2003_8000 0x2000_0000 0x2000_0000 SRAM0 64 Kbytes Reserved Reserved Reserved 0x1FFF_4000 0x2000_0000 SRAM0 48 Kbytes 0x1FFF_8000 SRAM0 32 Kbytes 0x1FFF_0000 0x0050_0000 0x0040_2000 0x0040_0000 0x0050_0000 CR trimming Security Reserved Reserved Reserved 0x0040_2000 0x0040_0000 0x0050_0000 CR trimming Security 0x0040_2000 0x0040_0000 CR trimming Security Reserved Reserved 0x0010_0000 Reserved 0x000C_0000 MainFlash 1 Mbytes 0x0000_0000 Document Number: 002-04918 Rev. *G 0x0008_0000 MainFlash 768 Kbytes 0x0000_0000 MainFlash 512 Kbytes 0x0000_0000 Page 58 of 160 CY9B160R Series Peripheral Address Map Start address 0x4000_0000 0x4000_1000 0x4001_0000 0x4001_1000 0x4001_2000 0x4001_3000 0x4001_5000 0x4001_6000 0x4002_0000 0x4002_1000 0x4002_2000 0x4002_4000 0x4002_5000 0x4002_6000 0x4002_7000 0x4002_8000 0x4002_E000 0x4002_F000 0x4003_0000 0x4003_1000 0x4003_2000 0x4003_3000 0x4003_4000 0x4003_5000 0x4003_5800 0x4003_6000 0x4003_8000 0x4003_9000 0x4003_A000 0x4003_B000 0x4003_C000 0x4003_C100 0x4003_C800 0x4003_F000 0x4004_0000 0x4006_0000 0x4006_1000 0x4006_4000 0x4006_E000 0x4006_F000 0x4006_7000 0x200E_0000 End address 0x4000_0FFF 0x4000_FFFF 0x4001_0FFF 0x4001_1FFF 0x4001_2FFF 0x4001_4FFF 0x4001_5FFF 0x4001_FFFF 0x4002_0FFF 0x4002_1FFF 0x4003_FFFF 0x4002_4FFF 0x4002_5FFF 0x4002_6FFF 0x4002_7FFF 0x4002_DFFF 0x4002_EFFF 0x4002_FFFF 0x4003_0FFF 0x4003_1FFF 0x4003_4FFF 0x4003_3FFF 0x4003_4FFF 0x4003_57FF 0x4003_5FFF 0x4003_7FFF 0x4003_8FFF 0x4003_9FFF 0x4003_AFFF 0x4003_BFFF 0x4003_C0FF 0x4003_C7FF 0x4003_EFFF 0x4003_FFFF 0x4005_FFFF 0x4006_0FFF 0x4006_3FFF 0x4006_DFFF 0x4006_EFFF 0x4006_FFFF 0x41FF_FFFF 0x200E_FFFF Document Number: 002-04918 Rev. *G Bus AHB APB0 APB1 APB2 AHB Peripherals MainFlash I/F register Reserved Clock/Reset Control Hardware Watchdog timer Software Watchdog timer Reserved Dual-Timer Reserved Multi-function timer unit0 Multi-function timer unit1 Reserved PPG Base Timer Quadrature Position/Revolution Counter A/D Converter Reserved Internal CR trimming Reserved External Interrupt Controller Interrupt Request Batch-Read Function Reserved D/A Converter Reserved Low Voltage Detector Deep standby mode Controller Reserved Multi-function serial Interface CRC Watch Counter RTC/Port Ctrl Low-speed CR Prescaler Peripheral Clock Gating Reserved External Memory interface Reserved DMAC register DSTC register Reserved SD-Card I/F GPIO Reserved WorkFlash I/F register Page 59 of 160 CY9B160R Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings. ◼ INITX = 0 This is the period when the INITX pin is the “L” level. ◼ INITX = 1 This is the period when the INITX pin is the “H” level. ◼ SPL = 0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to “0”. ◼ SPL = 1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to “1”. ◼ Input enabled Indicates that the input function can be used. ◼ Internal input fixed at “0” This is the status that the input function cannot be used. Internal input is fixed at “L”. ◼ Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state. ◼ Setting disabled Indicates that the setting is disabled. ◼ Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. ◼ Analog input is enabled Indicates that the analog input is enabled. ◼ Trace output Indicates that the trace function can be used. ◼ GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port. ◼ Setting prohibition Prohibition of a setting by specification limitation. Document Number: 002-04918 Rev. *G Page 60 of 160 CY9B160R Series Pin status type List of Pin Status Function group Power-on reset or lowvoltage detection state Power supply unstable ‐ ‐ INITX input state Device internal reset state Power supply stable INITX = 0 INITX = 1 ‐ ‐ Run mode or SLEEP mode state Power supply stable INITX = 1 ‐ TIMER mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 GPIO Hi-Z / selected Internal Internal input fixed input fixed at “0” at “0” Return from Deep standby mode state Power supply stable INITX = 1 - Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at “0” Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at “0” GPIO selected Internal input fixed at “0” Hi-Z / Internal input fixed at “0” GPIO selected External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at “0” Maintain previous state Hi-Z / Internal input fixed at “0” Maintain previous state Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at “0” Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at “0” Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at “0” Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at “0” Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at “0” GPIO selected GPIO selected A Main crystal oscillator input pin/ External main clock input selected B Main crystal oscillator output pin Hi-Z / Internal input fixed at “0”/ or Input enable Hi-Z / Internal input fixed at “0” Hi-Z / Internal input fixed at “0” Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at “0” C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Mode input pin Input enabled Input enabled Input enabled Setting disabled Setting disabled Input enabled Hi-Z / Input enabled Input enabled Hi-Z / Input enabled Input enabled Setting disabled Input enabled Maintain previous state Input enabled GPIO selected Input enabled Maintain previous state E Document Number: 002-04918 Rev. *G GPIO selected GPIO selected Page 61 of 160 Pin status type CY9B160R Series Function group Power supply unstable ‐ ‐ NMIX selected F Power-on reset or lowvoltage detection state Resource other than above selected Setting disabled Device internal reset state Power supply stable INITX = 0 INITX = 1 ‐ ‐ Setting disabled Hi-Z Hi-Z / Input enabled Hi-Z Pull-up / Input enabled Pull-up / Input enabled G GPIO selected Setting disabled Setting disabled Setting disabled JTAG selected Hi-Z Pull-up / Input enabled Pull-up / Input enabled H Resource other than above selected GPIO selected I Resource selected GPIO selected Analog output selected J Setting disabled Setting disabled Setting disabled Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Setting disabled Setting disabled Setting disabled Resource other than above selected Hi-Z GPIO selected Hi-Z / Input enabled Document Number: 002-04918 Rev. *G Run mode or SLEEP mode state Power supply stable INITX = 1 ‐ TIMER mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Maintain previous state Setting disabled Hi-Z / Input enabled GPIO selected JTAG selected INITX input state Hi-Z / Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at “0” GPIO selected Hi-Z / WKUP input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at “0” GPIO selected Internal input fixed at “0” Hi-Z / Internal input fixed at “0” GPIO selected Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at “0” GPIO selected Internal input fixed at “0” Hi-Z / Internal input fixed at “0” GPIO selected GPIO selected Internal input fixed at “0” Hi-Z / Internal input fixed at “0” GPIO selected GPIO selected Internal input fixed at “0” Hi-Z / Internal input fixed at “0” GPIO selected Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at “0” *2 *3 Maintain previous state Power supply stable INITX = 1 - Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Return from Deep standby mode state Hi-Z / Internal input fixed at “0” Page 62 of 160 Pin status type CY9B160R Series Function group Power-on reset or lowvoltage detection state Power supply unstable ‐ ‐ External interrupt enabled selected Setting disabled INITX input state Device internal reset state Power supply stable INITX = 0 INITX = 1 ‐ ‐ Setting disabled Deep standby RTC mode or Deep standby STOP mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at “0” Return from Deep standby mode state Power supply stable INITX = 1 - GPIO selected Internal input fixed at “0” Hi-Z / Internal input fixed at “0” GPIO selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z Hi-Z / Internal input fixedat „0“ / Analog input enabled Hi-Z / Internal input fixedat „0“ / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Maintain previous state Hi-Z / Internal input fixed at “0” GPIO selected Internal input fixed at “0” Hi-Z / Internal input fixed at “0” GPIO selected Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled GPIO selected Internal input fixed at “0” Hi-Z / Internal input fixed at “0” GPIO selected GPIO selected Analog input selected Power supply stable INITX = 1 ‐ TIMER mode, RTC mode, or STOP mode state Setting disabled K Resource other than above selected Run mode or SLEEP mode state L Resource other than above Setting selected disabled GPIO selected Setting disabled Setting disabled Maintain previous state Analog input selected Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z M External interrupt enabled selected Setting Resource other disabled than above selected GPIO selected Setting disabled Document Number: 002-04918 Rev. *G Setting disabled Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at “0” Page 63 of 160 Pin status type CY9B160R Series Function group Power-on reset or lowvoltage detection state Power supply unstable ‐ ‐ Analog input selected Hi-Z N INITX input state Device internal reset state Power supply stable INITX = 0 ‐ Hi-Z / Internal input fixed at”0” / Analog input enabled INITX = 1 ‐ Hi-Z / Internal input fixed at “0” / Analog input enabled Run mode or SLEEP mode state Power supply stable INITX = 1 ‐ Hi-Z / Internal input fixed at “0” / Analog input enabled TIMER mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Hi-Z / Internal input fixed at “0” / Analog input enabled Trace output Trace selected Resource other Setting than above disabled selected GPIO selected Analog input selected O Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z Setting disabled Setting disabled Maintain previous state Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Maintain previous state Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” Hi-Z / Internal input fixed at “0” / Analog input enabled Trace selected Trace output External interrupt enabled selected Maintain previous state Resource other than above selected Setting disabled Setting disabled GPIO selected Document Number: 002-04918 Rev. *G Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at “0” Return from Deep standby mode state Power supply stable INITX = 1 - Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled GPIO selected Internal input fixed at “0” Hi-Z / Internal input fixed at “0” GPIO selected Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled GPIO selected Internal input fixed at “0” Hi-Z / Internal input fixed at “0” GPIO selected Page 64 of 160 Pin status type CY9B160R Series Function group Power supply unstable ‐ ‐ Analog input selected P Power-on reset or lowvoltage detection state Hi-Z INITX input state Device internal reset state Power supply stable INITX = 0 ‐ Hi-Z / Internal input fixedat „0“ / Analog input enabled INITX = 1 ‐ Hi-Z / Internal input fixedat „0“ / Analog input enabled Run mode or SLEEP mode state Power supply stable INITX = 1 ‐ Hi-Z / Internal input fixed at “0” / Analog input enabled TIMER mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Power supply stable Power supply stable INITX = 1 SPL = 0 SPL = 1 INITX = 1 SPL = 0 SPL = 1 Hi-Z / Internal input fixed at “0” / Analog input enabled WKUP enabled Resource other Setting than above disabled selected Setting disabled Setting disabled Maintain previous state Maintain previous state GPIO selected WKUP enabled Q R Setting disabled External interrupt enabled selected Resource other than above selected Hi-Z GPIO selected GPIO selected Hi-Z Setting disabled Setting disabled Maintain previous state Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Hi-Z / Internal input fixed at “0” / Analog input enabled Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled Hi-Z / Internal input fixed at “0” GPIO selected Internal input fixed at “0” Hi-Z / Internal input fixed at “0” WKUP input enabled Hi-Z / WKUP input enabled GPIO selected Internal input fixed at “0” Hi-Z / Internal input fixed at “0” GPIO selected Internal input fixed at “0” Hi-Z / Internal input fixed at “0” Maintain previous state Hi-Z / Internal input fixed at “0” Maintain previous state Maintain previous state Hi-Z / Internal input fixed at “0” Return from Deep standby mode state Power supply stable INITX = 1 Hi-Z / Internal input fixed at “0” / Analog input enabled GPIO selected GPIO selected GPIO selected *1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, STOP mode, Deep standby RTC mode, and Deep standby STOP mode. *2: Maintain previous state at timer mode. GPIO selected Internal input fixed at “0” at RTC mode, STOP mode. *3: Maintain previous state at timer mode. Hi-Z/Internal input fixed at “0” at RTC mode, STOP mode. Document Number: 002-04918 Rev. *G Page 65 of 160 CY9B160R Series VBAT pin status type List of VBAT Domain Pin Status Poweron reset*1 Function group Power supply unstable T Power supply stable Power supply stable ‐ INITX = 0 INITX = 1 INITX = 1 ‐ ‐ ‐ ‐ TIMER mode, RTC mode, or STOP mode state Power supply stable INITX = 1 SPL = 0 SPL = 1 Return from Deep standby RTC mode or Deep Deep standby STOP standby mode state mode state VBAT RTC Return from VBAT RTC mode state mode state Power supply stable Power supply stable Power supply stable Power supply stable INITX = 1 INITX = 1 - - - - - SPL = 0 SPL = 1 Maintain Previous state Maintain Previous state Maintain previous state Maintain previous state Maintain Previous state Maintain Previous state Maintain Previous state Maintain Previous state Setting prohibition Sub crystal oscillator input pin / Input External enabled sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Maintain previous state GPIO selected Setting disabled Maintain Previous state Maintain Previous state Maintain previous state Maintain previous state Maintain Previous state Maintain Previous state Maintain Previous state Maintain Previous state Setting prohibition External sub clock input selected Setting disabled Maintain Previous state Maintain Previous state Maintain previous state Maintain previous state Maintain Previous state Maintain previous state Maintain Previous state Maintain previous state Maintain previous state Maintain previous state Maintain Previous state Maintain previous state Maintain previous state/When oscillation stops, Hi-Z*2 Maintain previous state/When oscillation stops, Hi-Z*2 Maintain previous state/When oscillation stops, Hi-Z*2 Maintain previous Maintain state/When Previous oscillation state stops, Hi-Z*2 Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected S INITX input state Run Device internal mode or SLEEP reset mode state state Setting disabled Hi-Z / Internal Sub crystal Maintain input fixed oscillator Previous at “0”/ output pin state or Input enable Resource selected U Hi-Z GPIO selected Maintain previous state Maintain previous state Maintain previous state *1: When VBAT and VCC power on. *2: When the SOSCNTL bit in the WTOSCCNT register is 0, the sub crystal oscillator output pin is maintained in the previous state. When the SOSCNTL bit in the WTOSCCNT register is 1, oscillation is stopped at Stop mode and Deep Standby Stop Document Number: 002-04918 Rev. *G Page 66 of 160 CY9B160R Series 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter Rating Symbol Min Unit Max Power supply voltage *1, *2 VCC VSS – 0.5 VSS + 6.5 V Power supply voltage (VBAT) *1 ,*3 VBAT VSS – 0.5 VSS + 6.5 V Analog power supply voltage * * AVCC VSS – 0.5 VSS + 6.5 V Analog reference voltage *1 ,*4 AVRH VSS – 0.5 V Input voltage *1 VI VSS + 6.5 VCC + 0.5 (≤ 6.5V) VSS + 6.5 V 1 , 4 VSS – 0.5 VSS – 0.5 Remarks V 5V tolerant “L” level maximum output current * IOL - “L” level average output current *6 IOLAV - ∑IOL - AVCC + 0.5 (≤ 6.5V) VCC + 0.5 (≤ 6.5V) 10 20 20 22.4 4 8 12 20 100 ∑IOLAV - 50 Ma - 10 Ma 4Ma type - 20 Ma 8Ma type Ma Ma Ma Ma Ma 12Ma type 4Ma type 8Ma type 12Ma type Analog pin input voltage * 1 Output voltage *1 5 “L” level total maximum output current “L” level total maximum output current * 7 “H” level maximum output current *5 VIA VSS – 0.5 VO VSS – 0.5 IOH V V Ma Ma Ma Ma Ma Ma Ma Ma Ma “H” level average output current *6 IOHAV - “H” level total maximum output current ∑IOH - - 20 -4 8 - 12 - 100 “H” level total average output current *7 ∑IOHAV - - 50 Ma Storage temperature TSTG - 55 + 150 °C 4Ma type 8Ma type 12Ma type I2C Fm+ 4Ma type 8Ma type 12Ma type I2C Fm+ *1: These parameters are based on the condition that VSS = AVSS = 0.0V. *2: VCC must not drop below VSS – 0.5V. *3: VBAT must not drop below VSS – 0.5V. *4: Ensure that the voltage does not exceed VCC + 0.5V, for example, when the power is turned on. *5: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *6: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100ms period. *7: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100ms. WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: 002-04918 Rev. *G Page 67 of 160 CY9B160R Series 12.2 Recommended Operating Conditions Parameter Symbol Value Conditions Min Max Unit Remarks V V V AVCC = VCC V Tj - 40 + 125 °C temperature Ambient temperature TA - 40 *1 °C *1: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed the junction temperature (Tj). The calculation formula of the ambient temperature (TA) is shown below. TA(Max) = Tj(Max) – Pd(Max) × θja Power supply voltage VCC - 2.7*3 5.5 Power supply voltage (VBAT) Analog power supply voltage Analog reference voltage Junction temperature Operating VBAT AVCC AVRH - 2.7 2.7 *2 5.5 5.5 AVCC Pd: θja: Power dissipation (W) Package thermal resistance (°C/W) Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH)) IOL: “L” level output current IOH: “H” level output current VOL: “L” level output voltage VOH: “H” level output voltage *2: The minimum value of Analog reference voltage depends on the value of compare clock cycle (Tcck). See 12.5. 12-bit A/D Converter” for the details. *3: Between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage, instruction execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is possible to operate. Package thermal resistance and maximum permissible power for each package are shown below. The operation is guaranteed maximum permissible power or less for semiconductor devices. Table for package thermal resistance and maximum permissible power Package LQH080 (0.5mm pitch) LQJ080 (0.65mm pitch) LQI100 (0.5mm pitch) PQH100 (0.65mm pitch) LQM120 (0.5mm pitch) LDC112 (0.5mm pitch) LDC144 (0.5mm pitch) Printed circuit board Single-layered both sides 4 layers Single-layered both sides 4 layers Single-layered both sides 4 layers Single-layered both sides 4 layers Single-layered both sides 4 layers Single-layered both sides 4 layers Single-layered both sides 4 layers Thermal resistance θja (°C/W) 60 39 58 38 57 38 48 34 62 43 60 40 55 40 Maximum permissible power (Mw) TA = +85°C TA = +105°C 667 1026 690 1053 702 1053 833 1177 645 930 667 1000 727 1000 333 513 335 526 351 526 417 588 323 465 333 500 364 500 WARNING: − The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: 002-04918 Rev. *G Page 68 of 160 CY9B160R Series Calculation method of power dissipation (Pd) The power dissipation is shown in the following formula. Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH)) IOL: “L” level output current IOH: “H” level output current VOL: “L” level output voltage VOH: “H” level output voltage ICC is a current consumed in device. It can be analyzed as follows. ICC = ICC(INT) + ΣICC(IO) ICC(INT): Current consumed in internal logic and memory, etc. through regulator ΣICC(IO): Sum of current (I/O switching current) consumed in output pin For ICC (INT), it can be anticipated by 12.3.1 “Current Rating” in 12.3. DC Characteristics” (This rating value does not include ICC (IO) for a value at pin fixed). For Icc (IO), it depends on system used by customers. The calculation formula is shown below. ICC(IO) = (CINT + CEXT) × VCC × fsw CINT: Pin internal load capacitance CEXT: External load capacitance of output pin fSW: Pin switching frequency Parameter Pin internal load capacitance Symbol CINT Conditions Capacitance value 4Ma type 1.93Pf 8Ma type 3.45Pf 12Ma type 3.42Pf Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself. 1. Measure current value ICC (Typ) at normal temperature (+25°C). 2. Add maximum leak current value ICC (leak_max) at operating on a value in (1). ICC(Max) = ICC(Typ) + ICC(leak_max) Parameter Maximum leak current at operating Document Number: 002-04918 Rev. *G Symbol ICC(leak_max) Conditions Current value Tj = +125°C 45.5Ma Tj = +105°C 26.8Ma Tj = +85°C 16.2Ma Page 69 of 160 CY9B160R Series Current explanation diagram Pd = VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH)) ICC = ICC(INT)＋ΣICC(IO) VCC A ICC Chip ICC(INT) ΣICC(IO) A Regulator VOL V A ・・・ V IOL Flash VOH ・・・ Logic IOH RAM ICC(IO) CEXT ・・・ Document Number: 002-04918 Rev. *G Page 70 of 160 CY9B160R Series 12.3 DC Characteristics 12.3.1 Current Rating Table 12-1. Typical and maximum current consumption in Normal operation(PLL), code running from Flash memory (Flash accelerator mode and trace buffer function enabled) Parameter Power supply current Symbol ICC Pin name VCC Conditions Normal operation*5,*6 (PLL) Frequency*4 Value Typ*1 Max*2 160MHz 54 103 144MHz 120MHz 100MHz 80MHz 60MHz 40MHz 20MHz 8MHz 4MHz 160MHz 144MHz 49 41 35 28 22 16 8.9 5.1 3.8 34 31 26 22 18 14 10 6.2 3.8 3.1 98 90 84 77 71 64 58 54 53 83 80 75 71 67 63 59 55 53 52 120MHz 100MHz 80MHz 60MHz 40MHz 20MHz 8MHz 4MHz Unit Remarks Ma *3 When all peripheral clocks are ON Ma *3 When all peripheral clocks are OFF Table 12-2. Typical and maximum current consumption in Normal operation(PLL), code with data accessing running from Flash memory (Flash accelerator mode and trace buffer function disabled) Parameter Power supply current Symbol ICC Pin name VCC Conditions Normal operation*8 (PLL) Frequency*7 Value Typ*1 Max*2 160MHz 74 126 144MHz 120MHz 100MHz 80MHz 60MHz 40MHz 20MHz 8MHz 4MHz 160MHz 144MHz 68 59 52 44 36 27 17 8.3 5.4 51 47 42 37 33 28 21 13 6.9 4.6 120 112 104 97 89 79 67 58 55 103 100 94 90 85 80 73 64 56 54 120MHz 100MHz 80MHz 60MHz 40MHz 20MHz 8MHz 4MHz Unit Remarks Ma *3 When all peripheral clocks are ON Ma *3 When all peripheral clocks are OFF *1: TA = +25°C, VCC = 3.3V *2: Tj = +125°C, VCC = 5.5V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK/2 Document Number: 002-04918 Rev. *G Page 71 of 160 CY9B160R Series *5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1) *6: Data access is nothing to MainFlash memory *7: Frequency is a value of HCLK. PCLK0 = PCLK2 = HCLK/2, PCLK1 = HCLK *8: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0) Table 12-3. Typical and maximum current consumption in Normal operation(PLL), code with data accessing running from Flash memory (flash 0 wait-cycle mode and read access 0 wait) Parameter Power supply current Symbol ICC Pin name VCC Conditions Normal operation*5 (PLL) Frequency*4 (MHz) Value Typ*1 Max*2 72MHz 46 98 60MHz 40 92 48MHz 33 85 36MHz 27 78 24MHz 19 70 12MHz 8MHz 4MHz 72MHz 60MHz 11 8.5 5.5 33 29 25 20 15 61 58 55 85 81 76 71 65 9.2 59 6.9 4.6 56 54 48MHz 36MHz 24MHz 12MHz 8MHz 4MHz Unit Remarks Ma *3 When all peripheral clocks are ON Ma *3 When all peripheral clocks are OFF *1: TA = +25°C, VCC = 3.3V *2: Tj = +125°C, VCC = 5.5V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 00) Document Number: 002-04918 Rev. *G Page 72 of 160 CY9B160R Series Table 12-4. Typical and maximum current consumption in Normal operation(other than PLL), code with data accessing running from Flash memory (flash 0 wait-cycle mode and read access 0 wait Parameter Symbol Pin name Conditions Normal operation*5 (built-in high-speed CR) Power supply current ICC VCC Normal operation*5 (sub oscillation) Normal operation*5 (built-in low-speed CR) Frequency*4 Value Typ*1 Max*2 Unit Remarks *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF 3.3 51 Ma 2.8 51 Ma 0.64 48 Ma *3 When all peripheral clocks are ON 0.56 48 Ma *3 When all peripheral clocks are OFF 0.64 48 Ma *3 When all peripheral clocks are ON 0.58 48 Ma *3 When all peripheral clocks are OFF 4MHz 32kHz 100kHz *1: TA = +25°C, VCC = 3.3V *2: Tj = +125°C, VCC = 5.5V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK/2 *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000) Document Number: 002-04918 Rev. *G Page 73 of 160 CY9B160R Series Table 12-5. Typical and maximum current consumption in Sleep operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Power supply current Symbol ICCS Pin name VCC Conditions Sleep operation (PLL) Frequency*4 Value Typ*1 Max*2 160MHz 35 84 144MHz 120MHz 100MHz 80MHz 60MHz 40MHz 20MHz 8MHz 4MHz 160MHz 144MHz 32 27 23 19 15 11 6.5 4.1 3.3 16 14 12 11 9.0 7.4 5.6 3.9 2.9 2.6 81 76 72 68 64 60 55 53 52 65 63 61 60 58 56 54 53 52 51 120MHz 100MHz 80MHz 60MHz 40MHz 20MHz 8MHz 4MHz Unit Remarks Ma *3 When all peripheral clocks are ON Ma *3 When all peripheral clocks are OFF Table 12-6. Typical and maximum current consumption in Sleep operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK Parameter Power supply current Symbol ICCS Pin name VCC Conditions Sleep operation (PLL) Frequency*5 Value Typ*1 Max*2 72MHz 22 71 60MHz 19 68 48MHz 16 64 36MHz 12 61 24MHz 9.0 58 12MHz 8MHz 4MHz 72MHz 60MHz 5.8 4.6 3.6 9.5 8.3 7.1 5.8 4.6 55 54 52 58 57 56 55 53 3.5 52 3.0 2.7 52 51 48MHz 36MHz 24MHz 12MHz 8MHz 4MHz Unit Remarks Ma *3 When all peripheral clocks are ON Ma *3 When all peripheral clocks are OFF *1: TA = +25°C, VCC = 3.3V *2: Tj = +125°C, VCC = 5.5V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK/2 *5: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK Document Number: 002-04918 Rev. *G Page 74 of 160 CY9B160R Series Table 12-7. Typical and maximum current consumption in Sleep operation(other than PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Power supply current Symbol ICCS Pin name VCC Conditions Frequency*4 Sleep operation (built-in high-speed CR) 4MHz Sleep operation (sub oscillation) 32kHz Sleep operation (built-in low-speed CR) Value Typ*1 Max*2 Unit Remarks *3 When all peripheral clocks are ON 1.5 49 Ma 1.0 49 Ma 0.59 48 Ma 0.51 48 Ma 0.61 48 Ma *3 When all peripheral clocks are ON 0.53 48 Ma *3 When all peripheral clocks are OFF 100kHz *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *1: TA = +25°C, VCC = 3.3V *2: Tj = +125°C, VCC = 5.5V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0 = PCLK1 = PCLK2 = HCLK/2 Document Number: 002-04918 Rev. *G Page 75 of 160 CY9B160R Series Table 12-8. Typical and maximum current consumption in STOP mode, TIMER mode and RTC mode Parameter Pin name Symbol ICCH Conditions STOP mode TIMER mode (built-in high-speed CR) Power supply current ICCT VCC TIMER mode (sub oscillation) TIMER mode (built-in low-speed CR) ICCR RTC mode (sub oscillation) Value Typ*1 Max*2 Frequency - 4MHz 32kHz 100kHz 32kHz Unit Remarks *3, *4 TA = +25°C 0.33 1.8 Ma - 15 Ma - 22 Ma 0.70 2.2 Ma - 16 Ma - 22 Ma 0.33 1.8 Ma *3, *4 TA = +25°C - 15 Ma *3, *4 TA = +85°C - 22 Ma 0.34 1.8 Ma - 15 Ma - 22 Ma 0.33 1.8 Ma - 15 Ma - 22 Ma *3, *4 TA = +85°C *3, *4 TA = +105°C *3, *4 TA = +25°C *3, *4 TA = +85°C *3, *4 TA = +105°C *3, *4 TA = +105°C *3, *4 TA = +25°C *3, *4 TA = +85°C *3, *4 TA = +105°C *3, *4 TA = +25°C *3, *4 TA = +85°C *3, *4 TA = +105°C *1: VCC = 3.3V *2: VCC = 5.5V *3: When all ports are fixed. *4: When LVD is OFF Document Number: 002-04918 Rev. *G Page 76 of 160 CY9B160R Series Table 12-9. Typical and maximum current consumption in Deep Standby STOP mode, Deep Standby RTC mode and VBAT Parameter Symbol Pin name Conditions Deep standby STOP mode (When RAM is OFF) ICCHD Value Typ*1 Max*2 Frequency Unit 29 140 Μa - 644 Μa - 1011 Μa 48 273 Μa - 2676 Μa - 4162 Μa 29 140 Μa - 644 Μa - 1011 Μa 48 273 Μa - 2676 Μa - 4162 Μa 0.015 0.29 Μa - 5.77 Μa - 10.6 Μa 1.53 22.6 Μa - 35.2 Μa - 41.8 Μa Deep standby STOP mode (When RAM is ON) VCC Deep standby RTC mode (When RAM is OFF) Power supply current ICCRD 32kHz Deep standby RTC mode (When RAM is ON) RTC stop*6 ICCVBAT VBAT - RTC operation*6 Remarks 3 * , *4 TA = +25°C *3, *4 TA = +85°C *3, *4 TA = +105°C *3, *4 TA = +25°C *3, *4 TA = +85°C *3, *4 TA = +105°C *3, *4 TA = +25°C *3, *4 TA = +85°C *3, *4 TA = +105°C *3, *4 TA = +25°C *3, *4 TA = +85°C *3, *4 TA = +105°C *3, *4, *5 TA = +25°C *3, *4, *5 TA = +85°C *3, *4, *5 TA = +105°C *3, *4 TA = +25°C *3, *4 TA = +85°C *3, *4 TA = +105°C *1: VCC = 3.3V *2: VCC = 5.5V *3: When all ports are fixed. *4: When LVD is OFF *5: When sub oscillation is OFF *6: In the case of setting RTC after VCC power on Document Number: 002-04918 Rev. *G Page 77 of 160 CY9B160R Series Table 12-10. Typical and maximum current consumption in Low-voltage detection circuit, Main flash memory write/erase Parameter Symbol Low-voltage detection circuit (LVD) power supply current ICCLVD Main flash memory write/erase current ICCFLASH Work flash memory write/erase current ICCWFLASH Pin name VCC Conditions Min Value Typ Max Unit At operation - 4 7 Μa At Write/Erase - 13.4 15.9 Ma At Write/Erase - 11.5 13.6 Ma Remarks For occurrence of interrupt Peripheral current dissipation Clock system HCLK PCLK1 PCLK2 Peripheral Unit 40 Frequency (MHz) 80 160 GPIO All ports 0.22 0.43 0.85 DMAC - 0.74 1.48 2.88 DSTC - 0.32 0.61 1.17 External bus I/F - 0.14 0.27 0.55 SD card I/F - 0.93 1.81 3.63 Base timer 4ch. 0.16 0.34 0.66 Multi-functional timer/PPG 1unit/4ch. 0.55 1.09 2.17 Quadrature position/Revolution counter 1unit 0.04 0.09 0.17 A/DC 1unit 0.20 0.39 0.78 Muli-function serial 1ch. 0.31 0.62 - Document Number: 002-04918 Rev. *G Unit Remarks Ma Ma Ma Page 78 of 160 CY9B160R Series 12.3.2 Pin Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Parameter “H” level input voltage (hysteresis input) “L” level input voltage (hysteresis input) Symbol VIHS VILS Pin name CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin Input pin doubled as I2C Fm+ CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin Input pin doubled as I2C Fm+ 4Ma type VOH 8Ma type “H” level output voltage 12Ma type The pin doubled as I2C Fm+ Document Number: 002-04918 Rev. *G Conditions Min Value Typ Max Unit - VCC×0.8 - VCC + 0.3 V - VCC×0.8 - VSS + 5.5 V - VCC×0.7 - VSS + 5.5 V - VSS – 0.3 - VCC×0.2 V - VSS – 0.3 - VCC×0.2 V - VSS - VCC×0.3 V VCC – 0.5 - VCC V VCC – 0.5 - VCC V VCC – 0.5 - VCC V VCC – 0.5 - VCC V VCC ≥ 4.5 V, IOH = - 4Ma VCC < 4.5 V, IOH = - 2Ma VCC ≥ 4.5 V, IOH = - 8Ma VCC < 4.5 V, IOH = - 4Ma VCC ≥ 4.5 V, IOH = - 12Ma VCC < 4.5 V, IOH = - 8Ma VCC ≥ 4.5 V, IOH = - 4Ma VCC < 4.5 V, IOH = - 3Ma Remarks At GPIO Page 79 of 160 CY9B160R Series Parameter Symbol Pin name 4Ma type 8Ma type “L” level output voltage VOL 12Ma type Value Conditions VCC ≥ 4.5 V, IOL = 4Ma VCC < 4.5 V, IOL = 2Ma VCC ≥ 4.5 V, IOH = 8Ma VCC < 4.5 V, IOH = 4Ma VCC ≥ 4.5 V, IOL = 12Ma VCC < 4.5 V, IOL = 8Ma Min Typ Unit Max VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V VCC ≥ 4.5 V, IOH = 4Ma The pin doubled as I2C Fm+ VCC < 4.5 V, IOH = 3Ma At GPIO VCC ≤ 5.5 V, IOH = 20Ma Input leak current Pull-up resistor value Input capacitance IIL - RPU Pull-up pin CIN Other than VCC, VBAT, VSS, AVCC, AVSS, AVRH Document Number: 002-04918 Rev. *G Remarks At I2C Fm+ - -5 - +5 VCC ≥ 4.5 V 25 50 100 VCC < 4.5 V 30 80 200 - - 5 15 Μa Kω Pf Page 80 of 160 CY9B160R Series 12.4 AC Characteristics 12.4.1 Main Clock Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Input frequency FCH Input clock cycle tCYLH Input clock pulse width - Input clock rising time and falling time tCF, tCR Internal operating clock*1 frequency Internal operating clock*1 cycle time Pin name Symbol X0, X1 Value Conditions Min Max VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V PWH/Tcylh, PWL/Tcylh 4 4 4 4 20.83 50 48 20 48 20 250 250 45 - Unit Remarks MHz When crystal oscillator is connected MHz When using external clock ns When using external clock 55 % When using external clock - 5 ns When using external clock FCC - - - 160 MHz Base clock (HCLK/FCLK) FCP0 FCP1 - - - 80 160 MHz MHz APB0 bus clock*2 APB1 bus clock*2 FCP2 - - - 80 MHz APB2 bus clock*2 tCYCC tCYCP0 tCYCP1 tCYCP2 - - 6.25 - ns Base clock (HCLK/FCLK) - - 12.5 - ns APB0 bus clock*2 - - 6.25 - ns APB1 bus clock*2 - - 12.5 - ns APB2 bus clock*2 *1: For more information about each internal operating clock, see “Chapter: Clock” in “FM4 Family Peripheral Manual”. *2: For about each APB bus which each peripheral is connected to, see “Block Diagram” in this datasheet. X0 Document Number: 002-04918 Rev. *G Page 81 of 160 CY9B160R Series 12.4.2 Sub Clock Input Characteristics (VBAT = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Input frequency Pin name Value Conditions Min Typ Unit Max - - 32.768 - kHz - 32 - 100 kHz - 10 - 31.25 μs 45 - 55 % 1/ tCYLL Input clock cycle tCYLL Input clock pulse width - X0A, X1A PWH/tCYLL, PWL/tCYLL 0.8 × VBAT VBAT X0A Remarks When crystal oscillator is connected When using external clock When using external clock When using external clock VBAT VBAT VBAT 12.4.3 Built-in CR Oscillation Characteristics Built-in High-speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Clock frequency Symbol Value Conditions Min Typ Unit Max Tj = -20°C to + 105°C 3.92 4 4.08 Tj = - 40°C to + 125°C 3.88 4 4.12 Tj = - 40°C to + 125°C 3 4 5 When trimming*1 FCRH Clock frequency FCRH Frequency stabilization time tCRWT Remarks - - - MHz When not trimming 30 *2 μs *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. *2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value. This period is able to use highspeed CR clock as source clock. Built-in Low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Clock frequency Symbol FCRL Document Number: 002-04918 Rev. *G Condition - Value Min 50 Typ 100 Max 150 Unit Remarks kHz Page 82 of 160 CY9B160R Series 12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Value Symbol PLL oscillation stabilization wait time* (LOCK UP time) PLL input clock frequency 1 Min Unit Typ Remarks Max tLOCK 200 - - μs FPLLI 4 - 16 MHz PLL multiplication rate - 13 - 80 multiplier PLL macro oscillation clock frequency FPLLO 200 - 320 MHz Main PLL clock frequency*2 FCLKPLL - - 160 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see “Chapter: Clock” in “FM4 Family Peripheral Manual”. 12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR clock for input clock of main PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Value Symbol PLL oscillation stabilization wait time* (LOCK UP time) PLL input clock frequency 1 Min Unit Typ Remarks Max tLOCK 200 - - μs FPLLI 3.8 4 4.2 MHz PLL multiplication rate - 50 - 75 multiplier PLL macro oscillation clock frequency FPLLO 190 - 320 MHz Main PLL clock frequency*2 FCLKPLL - - 160 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see “Chapter: Clock” in “FM4 Family Peripheral Manual”. Note: − Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency and temperature has been trimmed. 12.4.6 Reset Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Reset input time Symbol tINITX Document Number: 002-04918 Rev. *G Pin name INITX Value Condition - Min 500 Max - Unit Remarks ns Page 83 of 160 CY9B160R Series 12.4.7 Power-on Reset Timing (VSS = 0V, TA = -40°C to +85°C) Parameter Symbol Pin Name Dv/dt Power ramp rate VCC Typ Max - 50 - - VCC: 0.2V to 2.70V 1.3 - 1000 - 0.33 - 0.60 tPRT Time until releasing Power-on reset Unit Min tOFF Power supply shut down time Value Conditions ms Remarks *1 Mv/µs *2 ms *1: VCC must be held below 0.2V for a minimum period of tOFF. Improper initialization may occur if this condition is not met. *2: This Dv/dt characteristic is applied at the power-on of cold start (tOFF>50ms). Note: − If Toff cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 6. 2.7V VCC VDH 0.2V 0.2V dV/dt tPRT Internal RST RST Active CPU Operation 0.2V tOFF release start Glossary:  VDH: detection voltage of Low Voltage detection reset. See “12.7. Low-Voltage Detection Characteristics”. 12.4.8 GPIO Output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Output frequency tPCYCLE Pin name Pxx* Value Conditions Min Max Unit VCC ≥ 4.5 V - 50 MHz VCC < 4.5 V - 32 MHz *: GPIO is a target. Pxx tPCYCLE Document Number: 002-04918 Rev. *G Page 84 of 160 CY9B160R Series 12.4.9 External Bus Timing External bus clock output characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Output frequency Pin name MCLKOUT*1 tCYCLE Value Conditions Min Max Unit VCC ≥ 4.5 V - 50*2 MHz VCC < 4.5 V - 32*3 MHz *1: The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see “Chapter: External Bus Interface” in “FM4 Family Peripheral Manual”. *2: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 100MHz. *3: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 64MHz. 0.8 × Vcc 0.8 × Vcc MCLK tCYCLE External bus signal input/output characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Signal input characteristics Signal output characteristics Signal input Signal output Document Number: 002-04918 Rev. *G Symbol Conditions VIH VIL - VOH VOL VIH VIL VIH VIL VOH VOL VOH VOL Value Unit 0.8 × VCC V 0.2 × VCC V 0.8 × VCC V 0.2 × VCC V Remarks Page 85 of 160 CY9B160R Series Separate Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter MOEX Mininum pulse width MCSX↓→Address output delay time MOEX↑→Address hold time MCSX↓→ MOEX↓ delay time MOEX↑→ MCSX↑ time MCSX↓→MDQM↓ delay time Data set up→MOEX↑ time MOEX↑→ Data hold time MWEX Mininum pulse width MWEX↑→Address output delay time Symbol tOEW tCSL – AV tOEH – AX tCSL – OEL tOEH – CSH tCSL – RDQML tDS – OE tDH – OE MOEX MCSX[7:0], MAD[24:0] MOEX, MAD[24:0] MOEX, MCSX[7:0] MCSX, MDQM[1:0] MOEX, MADATA[15:0] MOEX, MADATA[15:0] tWEW MWEX tWEH – AX MWEX, MAD[24:0] MCSX↓→MWEX↓ delay time tCSL – WEL MWEX↑→MCSX↑ delay time tWEH – CSH MCSX↓→MDQM↓ delay time tCSL-WDQML MCSX↓→ Data output time MWEX↑→ Data hold time Pin name tCSL-DX tWEH – DX MWEX, MCSX[7:0] MCSX, MDQM[1:0] MCSX, MADATA[15:0] MWEX, MADATA[15:0] Value Conditions VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V Min Max Unit MCLK×n-3 - -9 -12 MCLK×m-9 MCLK×m-12 20 38 +9 +12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 - 0 - ns MCLK×n-3 - ns 0 MCLK×m-9 MCLK×m-12 0 0 MCLK×n-9 MCLK×n-12 0 MCLK×n-9 MCLK×n-12 MCLK-9 MCLK-12 0 ns MCLK×m+9 MCLK×m+12 MCLK×n+9 MCLK×n+12 MCLK×m+9 MCLK×m+12 MCLK×n+9 MCLK×n+12 MCLK+9 MCLK+12 MCLK×m+9 MCLK×m+12 ns ns ns ns ns ns ns ns ns ns ns ns Note: − When the external load capacitance CL = 30Pf (m = 0 to 15, n = 1 to 16) Document Number: 002-04918 Rev. *G Page 86 of 160 CY9B160R Series tCYCLE MCLK tOEH-CSH MCSX[7:0] tCSL-AV MAD[24:0] tWEH-CSH tOEH-AX Address tWEH-AX tCSL-AV Address tCSL-OEL tOEW MOEX tCSL-WDQML tCSL-RDQML MDQM[1:0] tCSL-WEL tWEW MWEX MADATA[15:0] tDS-OE tDH-OE RD tWEH-DX WD Invalid tCSL-DX Document Number: 002-04918 Rev. *G Page 87 of 160 CY9B160R Series Separate Bus Access Synchronous SRAM Mode Parameter Address delay time Symbol Pin name Conditions VCC ≥ 4.5V MCLK, MAD[24:0] tAV tCSH VCC ≥ 4.5V VCC ≥ 4.5V MOEX delay time tREH VCC ≥ 4.5V Data set up →MCLK↑ time tDS MCLK, MADATA[15:0] VCC ≥ 4.5V 19 VCC < 4.5V 37 MCLK↑→ Data hold time tDH MCLK, MADATA[15:0] VCC ≥ 4.5V VCC ≥ 4.5V MWEX delay time tWEH MDQM[1:0] delay time VCC ≥ 4.5V tDQMH VCC ≥ 4.5V MCLK, MADATA[15:0] VCC ≥ 4.5V MCLK↑→ Data hold time tOD MCLK, MADATA[15:0] VCC ≥ 4.5V 12 ns ns ns - ns 9 12 9 12 9 12 MCLK+18 MCLK+24 18 1 VCC < 4.5V ns ns 12 MCLK+1 VCC < 4.5V ns - 9 1 VCC < 4.5V tODS 9 1 VCC < 4.5V MCLK↑→ Data output time 12 1 VCC ≥ 4.5V MCLK, MDQM[1:0] 9 1 VCC < 4.5V VCC < 4.5V tDQML 12 0 VCC < 4.5V MCLK, MWEX 9 1 VCC < 4.5V tWEL 12 1 VCC < 4.5V MCLK, MOEX 9 1 VCC < 4.5V tREL 12 1 VCC < 4.5V MCLK, MCSX[7:0] MCSX delay time 9 1 VCC < 4.5V VCC ≥ 4.5V tCSL Min (VCC = 2.7V to 5.5V, VSS = 0V) Value Unit Max 24 ns ns ns ns ns ns Note: − When the external load capacitance CL = 30Pf tCYCLE MCLK tCSL tCSH MCSX[7:0] tAV tAV Address MAD[24:0] Address tREL tREH tDQML tDQMH MOEX MDQM[1:0] MWEX tDS MADATA[15:0] tDQML tDQMH tWEL tWEH tDH RD tOD WD Invalid tODS Document Number: 002-04918 Rev. *G Page 88 of 160 CY9B160R Series Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Multiplexed address delay time tALE-CHMADV Multiplexed address hold time tCHMADH Pin name VCC ≥ 4.5V MALE, MADATA[15:0] Value Conditions VCC < 4.5V Min 0 Max 10 Unit ns 20 VCC ≥ 4.5V MCLK×n+0 MCLK×n+10 VCC < 4.5V MCLK×n+0 MCLK×n+20 ns Note: − When the external load capacitance CL = 30Pf (m = 0 to 15, n = 1 to 16) MCLK MCSX[7:0] MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] Document Number: 002-04918 Rev. *G Page 89 of 160 CY9B160R Series Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol tCHAL MALE delay time tCHAH MCLK↑→ Multiplexed address delay time Pin name Conditions VCC ≥ 4.5V MCLK, ALE Value VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V Min Max Unit 9 ns 12 ns 9 ns 12 ns 1 tOD ns 1 tOD ns 1 1 Remarks VCC ≥ 4.5V tCHMADV MCLK, MADATA[15:0] MCLK↑→ t Multiplexed data output time CHMADX VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V Note: − When the external load capacitance CL = 30Pf MCLK MCSX[7:0] MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] Document Number: 002-04918 Rev. *G Page 90 of 160 CY9B160R Series NAND Flash Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter MNREX Min pulse width Data set up →MNREX↑ time MNREX↑→ Data hold time MNALE↑→ MNWEX delay time MNALE↓→ MNWEX delay time MNCLE↑→ MNWEX delay time MNWEX↑→ MNCLE delay time MNWEX Min pulse width MNWEX↓→ Data output time MNWEX↑→ Data hold time Symbol tNREW tDS – NRE tDH – NRE tALEH – NWEL tALEL – NWEL tCLEH – NWEL tNWEH – CLEL tNWEW tNWEL – DV tNWEH – DX Pin name MNREX MNREX, MADATA[15:0] MNREX, MADATA[15:0] MNALE, MNWEX MNALE, MNWEX MNCLE, MNWEX MNCLE, MNWEX MNWEX MNWEX, MADATA[15:0] MNWEX, MADATA[15:0] Value Conditions VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V VCC ≥ 4.5V VCC < 4.5V Min Max Unit MCLK×n-3 - ns 20 38 - ns 0 - ns MCLK×m-9 MCLK×m-12 MCLK×m-9 MCLK×m-12 MCLK×m-9 MCLK×m-12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 0 MCLK×n-3 - -9 -12 +9 +12 MCLK×m+9 MCLK×m+12 0 ns ns ns ns ns ns ns Note: − When the external load capacitance CL = 30Pf (m = 0 to 15, n = 1 to 16) NAND Flash Read MCLK MNREX MADATA[15:0] Document Number: 002-04918 Rev. *G Read Page 91 of 160 CY9B160R Series NAND Flash Address Write MCLK MNALE MNCLE MNWEX MADATA[15:0] Write NAND Flash Command Write MCLK MNALE MNCLE MNWEX MADATA[15:0] Document Number: 002-04918 Rev. *G Write Page 92 of 160 CY9B160R Series External Ready Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol MCLK↑ MRDY input setup time tRDYI Pin name MCLK, MRDY Value Conditions Min VCC ≥ 4.5V 19 VCC < 4.5V 37 Max - Unit Remarks ns When RDY is input ··· MCLK Over 2cycle Original MOEX MWEX tRDYI MRDY When RDY is released MCLK ··· ··· 2 cycle Extended MOEX MWEX tRDYI 0.5×VCC MRDY Document Number: 002-04918 Rev. *G Page 93 of 160 CY9B160R Series SDRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Value Pin name Min Unit Max Output frequency tCYCSD MSDCLK - 32 MHz Address delay time tAOSD MSDCLK, MAD[15:0] 2 12 ns MSDCLK↑→Data output delay time tDOSD MSDCLK, MADATA[31:0] 2 12 ns MSDCLK↑→Data output Hi-Z time tDOZSD MSDCLK, MADATA[31:0] 2 20 ns MDQM[1:0] delay time tWROSD MSDCLK, MDQM[1:0] 1 12 ns MCSX delay time tMCSSD MSDCLK, MCSX8 2 12 ns MRASX delay time tRASSD MSDCLK, MRASX 2 12 ns MCASX delay time tCASSD MSDCLK, MCASX 2 12 ns MSDWEX delay time tMWESD MSDCLK, MSDWEX 2 12 ns MSDCKE delay time tCKESD MSDCLK, MSDCKE 2 12 ns Data set up time tDSSD MSDCLK, MADATA[31:0] 23 - ns Data hold time tDHSD MSDCLK, MADATA[31:0] 0 - ns Note: − When the external load capacitance CL = 30Pf Document Number: 002-04918 Rev. *G Page 94 of 160 CY9B160R Series SDRAM Access tCYCSD MSDCLK tAOSD MAD[24:0] MDQM[1:0] MCSX MRASX MCASX MSDWEX MSDCKE Address tWROSD tMCSSD tRASSD tCASSD tMWESD tCKESD tDSSD MADATA[15:0] RD tDOSD MADATA[15:0] Document Number: 002-04918 Rev. *G tDHSD tDOZSD WD Page 95 of 160 CY9B160R Series 12.4.10 Base Timer Input Timing Timer input timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Input pulse width Symbol Pin name Conditions TIOAn/TIOBn (when using as ECK, TIN) tTIWH, tTIWL tTIWH - Value Min Max 2tCYCP - Unit Remarks ns tTIWL ECK VIHS TIN VIHS VILS VILS Trigger input timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Input pulse width Symbol tTRGH, tTRGL TGIN VIHS Pin name Conditions TIOAn/TIOBn (when using as TGIN) - tTRGH tTRGL VIHS VILS Value Min 2tCYCP Max - Unit Remarks ns VILS Note: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see “Block Diagram” in this datasheet. Document Number: 002-04918 Rev. *G Page 96 of 160 CY9B160R Series 12.4.11 CSIO/UART Timing Synchronous serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Baud rate - Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI Serial clock “L” pulse width Serial clock “H” pulse width tSLSH tSHSL SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK falling time SCK rising time Tf Tr Pin name Conditions - - SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx Internal shift clock operation External shift clock operation VCC < 4.5V Min Max - VCC ≥ 4.5V Min Max 8 - 8 Unit Mbps 4tCYCP - 4tCYCP - ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP – 10 tCYCP + 10 - 2tCYCP – 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30Pf. Document Number: 002-04918 Rev. *G Page 97 of 160 CY9B160R Series tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI VIH VIL SIN tSHIXI VIH VIL MS bit = 0 tSLSH SCK VIH tF SOT SIN VIL tSHSL VIL VIH VIH tR tSLOVE VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 Document Number: 002-04918 Rev. *G Page 98 of 160 CY9B160R Series Synchronous serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Baud rate Serial clock cycle time tSCYC - SCK↑→SOT delay time tSHOVI SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI Serial clock “L” pulse width Serial clock “H” pulse width tSLSH tSHSL SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK falling time SCK rising time Tf Tr Pin name Conditions SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx VCC < 4.5V Min Max - Internal shift clock operation External shift clock operation 8 VCC ≥ 4.5V Min Max 8 Unit 4tCYCP - 4tCYCP - Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP – 10 tCYCP + 10 - 2tCYCP – 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30Pf. Document Number: 002-04918 Rev. *G Page 99 of 160 CY9B160R Series tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH VIL SIN tSLIXI VIH VIL MS bit = 0 tSHSL SCK tSLSH VIH VIH VIL tR VIL tF tSHOVE SOT SIN VIL VOH VOL tIVSLE VIH VIL tSLIXE VIH VIL MS bit = 1 Document Number: 002-04918 Rev. *G Page 100 of 160 CY9B160R Series Synchronous serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Pin name Symbol Baud rate Serial clock cycle time tSCYC - SCK↑→SOT delay time tSHOVI SIN→SCK↓ setup time tIVSLI SCK↓→SIN hold time tSLIXI SOT→SCK↓ delay time tSOVLI Serial clock “L” pulse width tSLSH Serial clock “H” pulse width tSHSL SCK↑→SOT delay time tSHOVE SIN→SCK↓ setup time tIVSLE SCK↓→SIN hold time tSLIXE SCK falling time SCK rising time Tf Tr VCC < 4.5V Min Max Conditions SCKx - - 4tCYCP - Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP – 30 - - ns SCKx 2tCYCP – 10 - - ns SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx tCYCP + 10 - 2tCYCP – 30 2tCYCP – 10 tCYCP + 10 - ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns SCKx, SINx SCKx, SINx SCKx, SOTx Internal shift clock operation External shift clock operation 8 8 Unit 4tCYCP SCKx, SOTx - VCC ≥ 4.5V Min Max Notes: − The above characteristics apply to CLK synchronous mode. − − − tCYCP indicates the APB bus clock cycle time. − When the external load capacitance CL = 30Pf. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. Document Number: 002-04918 Rev. *G Page 101 of 160 CY9B160R Series tSCYC VOH SCK SOT VOL VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL MS bit = 0 tSLSH SCK VIH VIH VIL tF * SOT VIL tSHSL tR VIH tSHOVE VOH VOL VOH VOL tIVSLE SIN tSLIXE VIH VIL VIH VIL MS bit = 1 *: Changes when writing to TDR register Document Number: 002-04918 Rev. *G Page 102 of 160 CY9B160R Series Synchronous serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Pin name Symbol Baud rate Serial clock cycle time tSCYC - SCK↓→SOT delay time tSLOVI SIN→SCK↑ setup time tIVSHI SCK↑→SIN hold time tSHIXI SOT→SCK↑ delay time tSOVHI Serial clock “L” pulse width tSLSH Serial clock “H” pulse width tSHSL SCK↓→SOT delay time tSLOVE SIN→SCK↑ setup time tIVSHE SCK↑→SIN hold time tSHIXE SCK falling time SCK rising time Tf Tr SCKx SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx VCC < 4.5V Min Max Conditions - 4tCYCP - Mbps ns - 30 + 30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP – 30 - - ns SCKx 2tCYCP – 10 - - ns SCKx tCYCP + 10 - - ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Internal shift clock operation External shift clock operation 8 2tCYCP – 30 2tCYCP – 10 tCYCP + 10 8 Unit 4tCYCP SCKx, SOTx SCKx, SINx SCKx, SINx SCKx SCKx - VCC ≥ 4.5V Min Max Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30Pf. Document Number: 002-04918 Rev. *G Page 103 of 160 CY9B160R Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL MS bit = 0 tSHSL tR SCK VIL VIH tSLSH VIH VIL tF VIL VIH tSLOVE SOT VOH VOL VOH VOL tIVSHE SIN tSHIXE VIH VIL VIH VIL MS bit = 1 Document Number: 002-04918 Rev. *G Page 104 of 160 CY9B160R Series When using synchronous serial chip select (SCINV = 0, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↓setup time tCSSI SCK↑→SCS↑ hold time tCSHI Internal shift clock operation VCC ≥ 4.5V VCC < 4.5V Conditions Min Max Min Max Unit (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns (*3)+50 +5tCYCP (*3)-50 +5tCYCP (*3)+50 +5tCYCP ns SCS deselect time tCSDI (*3)-50 +5tCYCP SCS↓→SCK↓setup time tCSSE 3tCYCP+30 - 3tCYCP+30 - ns SCK↑→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↓→SUT delay time tDSE - 40 - 40 ns SCS↑→SUT delay time tDEE 0 - 0 - ns External shift clock operation (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. − − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”. When the external load capacitance CL = 30Pf. Document Number: 002-04918 Rev. *G Page 105 of 160 CY9B160R Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSSE tCSHE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04918 Rev. *G Page 106 of 160 CY9B160R Series When using synchronous serial chip select (SCINV = 1, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↑setup time tCSSI SCK↓→SCS↑ hold time tCSHI Internal shift clock operation VCC ≥ 4.5V VCC < 4.5V Conditions Min Max Min Max Unit (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns (*3)+50 +5tCYCP (*3)-50 +5tCYCP (*3)+50 +5tCYCP ns SCS deselect time tCSDI (*3)-50 +5tCYCP SCS↓→SCK↑setup time tCSSE 3tCYCP+30 - 3tCYCP+30 - ns SCK↓→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↓→SOT delay time tDSE - 40 - 40 ns SCS↑→SOT delay time tDEE 0 - 0 - ns External shift clock operation (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. − − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”. When the external load capacitance CL = 30Pf. Document Number: 002-04918 Rev. *G Page 107 of 160 CY9B160R Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04918 Rev. *G Page 108 of 160 CY9B160R Series When using synchronous serial chip select (SCINV = 0, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter SCS↑→SCK↓setup time SCK↑→SCS↓ hold time Symbol tCSSI tCSHI Internal shift clock operation VCC ≥ 4.5V VCC < 4.5V Conditions Min Max Min Max Unit (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns (*3)+50 +5tCYCP (*3)-50 +5tCYCP (*3)+50 +5tCYCP ns SCS deselect time tCSDI (*3)-50 +5tCYCP SCS↑→SCK↓setup time tCSSE 3tCYCP+30 - 3tCYCP+30 - ns SCK↑→SCS↓ hold time tCSHE 0 - 0 - ns 3tCYCP+30 - 3tCYCP+30 - ns External shift clock operation SCS deselect time tCSDE SCS↑→SOT delay time tDSE - 40 - 40 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. − − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”. When the external load capacitance CL = 30Pf. Document Number: 002-04918 Rev. *G Page 109 of 160 CY9B160R Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04918 Rev. *G Page 110 of 160 CY9B160R Series When using synchronous serial chip select (SCINV = 1, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter SCS↑→SCK↑setup time SCK↓→SCS↓ hold time Symbol tCSSI tCSHI Internal shift clock operation VCC ≥ 4.5V VCC < 4.5V Conditions Min Max Min Max Unit (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns (*3)+50 +5tCYCP (*3)-50 +5tCYCP (*3)+50 +5tCYCP ns SCS deselect time tCSDI (*3)-50 +5tCYCP SCS↑→SCK↑setup time tCSSE 3tCYCP+30 - 3tCYCP+30 - ns SCK↓→SCS↓ hold time tCSHE 0 - 0 - ns 3tCYCP+30 - 3tCYCP+30 - ns External shift clock operation SCS deselect time tCSDE SCS↑→SOT delay time tDSE - 40 - 40 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. − − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”. When the external load capacitance CL = 30Pf. Document Number: 002-04918 Rev. *G Page 111 of 160 CY9B160R Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04918 Rev. *G Page 112 of 160 CY9B160R Series High-speed synchronous serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name VCC ≥ 4.5V VCC < 4.5V Conditions Min Max Min Max Unit Serial clock cycle time tSCYC SCKx 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx - 12.5 - ns SCK↑→SIN hold time tSHIXI SCKx, SINx 5 - 5 - ns Serial clock “L” pulse width tSLSH SCKx 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock “H” pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 5 - 5 - ns SCK↑→SIN hold time tSHIXE 5 - 5 - ns SCK falling time Tf SCKx - 5 - 5 ns SCK rising time Tr SCKx - 5 - 5 ns Internal shift clock operation 14 12.5* External shift clock operation SCKx, SINx Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. − These characteristics only guarantee the following pins. − − − No chip select: SIN4_1, SOT4_1, SCK4_1 Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 When the external load capacitance CL = 30Pf. (For *, when CL = 10Pf) Document Number: 002-04918 Rev. *G Page 113 of 160 CY9B160R Series tSCYC VOH SCK VOL VOL tSLOVI VOH VOL SOT tIVSHI VIH VIL SIN tSHIXI VIH VIL MS bit = 0 tSLSH SCK VIH tF SOT SIN VIL tSHSL VIL VIH VIH tR tSLOVE VOH VOL tIVSHE VIH VIL tSHIXE VIH VIL MS bit = 1 Document Number: 002-04918 Rev. *G Page 114 of 160 CY9B160R Series High-speed synchronous serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Serial clock cycle time tSCYC SCKx SCK↑→SOT delay time tSHOVI SCKx, SOTx Internal shift clock operation VCC ≥ 4.5V VCC < 4.5V Conditions Min Max Min Max Unit 4tCYCP - 4tCYCP - ns -10 +10 -10 +10 ns - 12.5 - ns 14 SIN→SCK↓ setup time tIVSLI SCKx, SINx SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns Serial clock “L” pulse width tSLSH SCKx 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock “H” pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns 5 - 5 - ns 12.5* External shift clock operation SIN→SCK↓ setup time tIVSLE SCKx, SINx SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns SCK falling time Tf SCKx - 5 - 5 ns SCK rising time Tr SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. − These characteristics only guarantee the following pins. − − − No chip select: SIN4_1, SOT4_1, SCK4_1 Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 When the external load capacitance CL = 30Pf. (For *, when CL = 10Pf) Document Number: 002-04918 Rev. *G Page 115 of 160 CY9B160R Series tSCYC VOH SCK VOH VOL tSHOVI VOH VOL SOT tIVSLI VIH VIL SIN tSLIXI VIH VIL MS bit = 0 tSHSL SCK tSLSH VIH VIH VIL tR VIL tF tSHOVE SOT SIN VIL VOH VOL tIVSLE VIH VIL tSLIXE VIH VIL MS bit = 1 Document Number: 002-04918 Rev. *G Page 116 of 160 CY9B160R Series High-speed synchronous serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name VCC ≥ 4.5V VCC < 4.5V Conditions Min Max Min Max Unit Serial clock cycle time tSCYC SCKx 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx - 12.5 - ns SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns SOT→SCK↓ delay time tSOVLI SCKx, SOTx 2tCYCP – 10 - 2tCYCP – 10 - ns Serial clock “L” pulse width tSLSH SCKx 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock “H” pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns 5 - 5 - ns Internal shift clock operation 14 12.5* External shift clock operation SIN→SCK↓ setup time tIVSLE SCKx, SINx SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns SCK falling time Tf SCKx - 5 - 5 ns SCK rising time Tr SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. − These characteristics only guarantee the following pins. − − − No chip select: SIN4_1, SOT4_1, SCK4_1 Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 When the external load capacitance CL = 30Pf. (For *, when CL = 10Pf) Document Number: 002-04918 Rev. *G Page 117 of 160 CY9B160R Series tSCYC VOH SCK SOT VOL VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL MS bit = 0 tSLSH VIH SCK VIH VIL tF * SOT VIL tSHSL tR VIH tSHOVE VOH VOL VOH VOL tIVSLE SIN tSLIXE VIH VIL VIH VIL MS bit = 1 *: Changes when writing to TDR register Document Number: 002-04918 Rev. *G Page 118 of 160 CY9B160R Series High-speed synchronous serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name VCC ≥ 4.5V VCC < 4.5V Conditions Min Max Min Max Unit Internal shift clock operation tSCYC SCKx 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx - 12.5 - ns SCK↑→SIN hold time tSHIXI SCKx, SINx 5 - 5 - ns SOT→SCK↑ delay time tSOVHI SCKx, SOTx 2tCYCP – 10 - 2tCYCP – 10 - ns Serial clock “L” pulse width tSLSH SCKx 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock “H” pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 15 - 15 ns 5 - 5 - ns Internal shift clock operation 14 12.5* External shift clock operation SIN→SCK↑ setup time tIVSHE SCKx, SINx SCK↑→SIN hold time tSHIXE SCKx, SINx 5 - 5 - ns SCK falling time Tf SCKx - 5 - 5 ns SCK rising time Tr SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. − These characteristics only guarantee the following pins. − − − No chip select: SIN4_1, SOT4_1, SCK4_1 Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 When the external load capacitance CL = 30Pf. (For *, when CL = 10Pf) Document Number: 002-04918 Rev. *G Page 119 of 160 CY9B160R Series tSCYC VOH SCK tSOVHI SOT tSLOVI VOH VOL VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL MS bit = 0 tSHSL tR SCK VIL VIH tSLSH VIH VIL tF VIL VIH tSLOVE SOT VOH VOL VOH VOL tIVSHE SIN tSHIXE VIH VIL VIH VIL MS bit = 1 Document Number: 002-04918 Rev. *G Page 120 of 160 CY9B160R Series When using high-speed synchronous serial chip select (SCINV = 0, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↓setup time tCSSI SCK↑→SCS↑ hold time tCSHI Internal shift clock operation VCC ≥ 4.5V VCC < 4.5V Conditions Min Max Min Max Unit (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns (*3)+20 +5tCYCP (*3)-20 +5tCYCP (*3)+20 +5tCYCP ns SCS deselect time tCSDI (*3)-20 +5tCYCP SCS↓→SCK↓setup time tCSSE 3tCYCP+15 - 3tCYCP+15 - ns SCK↑→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↓→SOT delay time tDSE - 25 - 25 ns SCS↑→SOT delay time tDEE 0 - 0 - ns External shift clock operation (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. − − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”. When the external load capacitance CL = 30Pf. Document Number: 002-04918 Rev. *G Page 121 of 160 CY9B160R Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSSE tCSHE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04918 Rev. *G Page 122 of 160 CY9B160R Series When using high-speed synchronous serial chip select (SCINV = 1, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol SCS↓→SCK↑setup time tCSSI SCK↓→SCS↑ hold time tCSHI Internal shift clock operation VCC ≥ 4.5V VCC < 4.5V Conditions Min Max Min Max Unit (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns (*3)+20 +5tCYCP (*3)-20 +5tCYCP (*3)+20 +5tCYCP ns SCS deselect time tCSDI (*3)-20 +5tCYCP SCS↓→SCK↑setup time tCSSE 3tCYCP+15 - 3tCYCP+15 - ns SCK↓→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↓→SOT delay time tDSE - 25 - 25 ns SCS↑→SOT delay time tDEE 0 - 0 - ns External shift clock operation (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. − − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”. When the external load capacitance CL = 30Pf. Document Number: 002-04918 Rev. *G Page 123 of 160 CY9B160R Series SCS output tCSDI tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tCSDE tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04918 Rev. *G Page 124 of 160 CY9B160R Series When using high-speed synchronous serial chip select (SCINV = 0, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter SCS↑→SCK↓setup time SCK↑→SCS↓ hold time Symbol tCSSI tCSHI Internal shift clock operation VCC ≥ 4.5V VCC < 4.5V Conditions Min Max Min Max Unit (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns (*3)+20 +5tCYCP (*3)-20 +5tCYCP (*3)+20 +5tCYCP ns SCS deselect time tCSDI (*3)-20 +5tCYCP SCS↑→SCK↓setup time tCSSE 3tCYCP+15 - 3tCYCP+15 - ns SCK↑→SCS↓ hold time tCSHE 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns External shift clock operation SCS deselect time tCSDE SCS↑→SOT delay time tDSE - 25 - 25 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. − − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”. When the external load capacitance CL = 30Pf. Document Number: 002-04918 Rev. *G Page 125 of 160 CY9B160R Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04918 Rev. *G Page 126 of 160 CY9B160R Series When using high-speed synchronous serial chip select (SCINV = 1, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter SCS↑→SCK↑setup time SCK↓→SCS↓ hold time Symbol tCSSI tCSHI Internal shift clock operation VCC ≥ 4.5V VCC < 4.5V Conditions Min Max Min Max Unit (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns (*3)+20 +5tCYCP (*3)-20 +5tCYCP (*3)+20 +5tCYCP ns SCS deselect time tCSDI (*3)-20 +5tCYCP SCS↑→SCK↑setup time tCSSE 3tCYCP+15 - 3tCYCP+15 - ns SCK↓→SCS↓ hold time tCSHE 0 - 0 - ns 3tCYCP+15 - 3tCYCP+15 - ns External shift clock operation SCS deselect time tCSDE SCS↑→SOT delay time tDSE - 25 - 25 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. − − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”. When the external load capacitance CL = 30Pf. Document Number: 002-04918 Rev. *G Page 127 of 160 CY9B160R Series tCSDI SCS output tCSHI tCSSI SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tCSDE SCS input tCSHE tCSSE SCK input tDEE SOT (SPI=0) tDSE SOT (SPI=1) MS bit = 1 Document Number: 002-04918 Rev. *G Page 128 of 160 CY9B160R Series External clock (EXT = 1) : when in asynchronous mode only (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Serial clock “L” pulse width Serial clock “H” pulse width tSLSH tSHSL SCK falling time Tf SCK rising time Tr SCK VIL Document Number: 002-04918 Rev. *G Condition CL = 30Pf tR Value Min - ns ns - 5 ns - 5 ns VIL Remarks tF tSLSH VIH Unit tCYCP + 10 tCYCP + 10 tSHSL VIH Max VIL VIH Page 129 of 160 CY9B160R Series 12.4.12 External Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Conditions Value Min Max Unit ADTG Input pulse width tINH, tINL FRCKx Icxx DTTIxX INT00 to INT31, NMIX WKUPx Remarks A/D converter trigger input - 2tCYCP*1 - ns - 2tCYCP*1 2tCYCP + 100*1 500*2 500*3 - ns ns ns ns - Free-run timer input clock Input capture Waveform generator External interrupt, NMI Deep standby wake up *1: tCYCP indicates the APB bus clock cycle time except stop when in STOP mode, in timer mode. About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see “Block Diagram” in this data sheet. *2: When in STOP mode, in timer mode. *3: When in deep standby RTC mode, in deep standby STOP mode. Document Number: 002-04918 Rev. *G Page 130 of 160 CY9B160R Series 12.4.13 Quadrature Position/Revolution Counter Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol AIN pin “H” width AIN pin “L” width BIN pin “H” width BIN pin “L” width BIN rising time from AIN pin “H” level AIN falling time from BIN pin “H” level BIN falling time from AIN pin “L” level AIN rising time from BIN pin “L” level AIN rising time from BIN pin “H” level BIN falling time from AIN pin “H” level AIN falling time from BIN pin “L” level BIN rising time from AIN pin “L” level ZIN pin “H” width ZIN pin „L“ width AIN/BIN rising and falling time from determined ZIN level Determined ZIN level from AIN/BIN rising and falling time Value Conditions tAHL tALL tBHL tBLL - tAUBU PC_Mode2 or PC_Mode3 tBUAD PC_Mode2 or PC_Mode3 tADBD PC_Mode2 or PC_Mode3 tBDAU PC_Mode2 or PC_Mode3 tBUAU PC_Mode2 or PC_Mode3 tAUBD PC_Mode2 or PC_Mode3 tBDAD PC_Mode2 or PC_Mode3 tADBU PC_Mode2 or PC_Mode3 tZHL tZLL QCR:CGSC = “0” QCR:CGSC = “0” tZABE QCR:CGSC = “1” tABEZ QCR:CGSC = “1” Min Unit Max 2tCYCP* - ns *: tCYCP indicates the APB bus clock cycle time except stop when in STOP mode, in timer mode. About the APB bus number which Quadrature Position/Revolution Counter is connected to, see “Block Diagram” in this data sheet. tALL tAHL AIN tAUBU tADBD tBUAD tBDAU BIN tBHL Document Number: 002-04918 Rev. *G tBLL Page 131 of 160 CY9B160R Series tBLL tBHL BIN tBUAU tBDAD tAUBD tADBU AIN tAHL tALL ZIN ZIN AIN/BIN Document Number: 002-04918 Rev. *G Page 132 of 160 CY9B160R Series 12.4.14 I2C Timing Standard-mode, Fast-mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Standard-mode Min Max Conditions Fast-mode Min Max Unit SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ SCL clock “L” width FSCL 0 100 0 400 kHz tHDSTA 4.0 - 0.6 - μs tLOW 4.7 - 1.3 - μs SCL clock “H” width (Repeated) START condition setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ STOP condition setup time SCL ↑ → SDA ↑ Bus free time between “STOP condition” and “START condition” tHIGH 4.0 - 0.6 - μs 4.7 - 0.6 - μs 0 3.45*2 0 0.9*3 μs tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs 2tCYCP*4 - 2tCYCP*4 - ns 4tCYCP*4 - 4tCYCP*4 - ns 6tCYCP*4 - 6tCYCP*4 - ns 8tCYCP*4 - 8tCYCP*4 - ns 10tCYCP*4 - 10tCYCP*4 - ns 12tCYCP*4 - 12tCYCP*4 - ns 14tCYCP*4 - 14tCYCP*4 - ns 16tCYCP*4 - 16tCYCP*4 - ns Noise filter tSUSTA tHDDAT tSP CL = 30Pf, R = (Vp/IOL)*1 2MHz ≤ tCYCP