The following document contains information on Cypress products. The document has the series
name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will
offer these products to new and existing customers with the series name, product name, and
ordering part number with the prefix “CY”.
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For More Information
Please contact your local sales office for additional information about Cypress products and
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About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to www.cypress.com.
MB9B310T Series
32-bit ARM® Cortex®-M3
FM3 Microcontroller
The MB9B310T Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and
competitive cost.
®
®
These series are based on the ARM Cortex -M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions
2
such as Motor Control Timers, ADCs and Communication Interfaces (USB, UART, CSIO, I C, LIN).
The products which are described in this data sheet are placed into TYPE2 product categories in "FM3 Family Peripheral Manual".
Features
®
®
32-bit ARM Cortex -M3 Core
External Bus Interface
Processor version: r2p1
Supports SRAM, NOR and NAND Flash device
Up to 144 MHz Frequency Operation
Up to 8 chip selects
Memory Protection Unit (MPU): improves the reliability of an
8-/16-bit Data width
embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
Up to 25-bit Address bit
Maximum area size: Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY input
USB Interface (Max 2 channels)
On-chip Memories
USB interface is composed of Device and Host.
[Flash memory]
[USB device]
Up to 1 Mbyte
USB2.0 Full-Speed supported
Built-in Flash Accelerator System with 16 Kbyte trace buffer
Max 6 EndPoint supported
memory
EndPoint
The read access to Flash memory can be achieved without
wait cycle up to operation frequency of 72 MHz. Even at the
operation frequency more than 72 MHz, an equivalent
access to Flash memory can be obtained by Flash
Accelerator System.
Security function for code protection
[SRAM]
0 is control transfer
1, 2 can be selected Bulk-transfer,
Interrupt-transfer or Isochronous-transfer
EndPoint 3 to 5 can be selected Bulk-transfer or
Interrupt-transfer
EndPoint 1 to 5 is comprised Double Buffer
• EndPoint 0, 2 to 5:64 bytes
• EndPoint 1: 256 bytes
EndPoint
This Series contain a total of up to 128Kbyte on-chip SRAM
memories. This is composed of two independent SRAM
(SRAM0, SRAM1). SRAM0 is connected to I-code bus and
D-code bus of Cortex-M3 core. SRAM1 is connected to System
bus.
[USB host]
SRAM0: Up to 64 Kbyte.
USB Device connected/dis-connected automatically detect
SRAM1: Up to 64 Kbyte.
IN/OUT token handshake packet automatically
USB2.0 Full/Low speed supported
Bulk-transfer, interrupt-transfer and Isochronous-transfer
support
Max 256-byte packet-length supported
Wake-up function supported
Cypress Semiconductor Corporation
Document Number: 002-04686 Rev.*C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 11, 2017
MB9B310T Series
Multi-function Serial Interface (Max 8 channels)
DMA Controller (8channels)
4 channels with 16steps×9-bit FIFO (ch.4 to ch.7), 4
DMA Controller has an independent bus for CPU, so CPU and
DMA Controller can process simultaneously.
channels without FIFO (ch.0 to ch.3)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
2
I C
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32-bit (4 Gbyte)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
[UART]
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
External clock available as a serial clock
A/D Converter (Max 32 channels)
Hardware Flow control: Automatically control the
[12-bit A/D Converter]
transmission by CTS/RTS (only ch.4)
Various error detect functions available (parity errors, framing
errors, and overrun errors)
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detect function available
[LIN]
Successive Approximation Register type
Built-in 3units
Conversion time: 1.0 μs@ 5 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion:
4 steps)
LIN protocol Rev.2.1 supported
Base Timer (Max 16 channels)
Full-duplex double buffer
Operation mode is selectable from the followings for each
channel.
Master/Slave mode supported
LIN break field generate (can be changed 13 to 16-bit length)
LIN break delimiter generate (can be changed 1 to 4-bit
length)
Various error detect functions available (parity errors, framing
errors, and overrun errors)
2
[I C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
General Purpose I/O Port
This series can use its pins as I/O ports when they are not used
for external bus or peripherals. Moreover, the port relocate
function is built in. It can set which I/O port the peripheral
function can be allocated.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up 154 fast I/O Ports@ 176 pin Package
Some pin is 5 V tolerant I/O.
See "Pin Description" to confirm the corresponding pins.
Document Number: 002-04686 Rev.*C
Page 2 of 128
MB9B310T Series
Multi-function Timer (Max 3 units)
Watch dog Timer (2 channels)
The Multi-function timer is composed of the following blocks.
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
16-bit free-run timer × 3 ch./unit
Input capture × 4 ch./unit
Output compare × 6 ch./unit
A/D activation compare × 3 ch./unit
Waveform generator × 3 ch./unit
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low speed internal
CR oscillator. Therefore, "Hardware" watchdog is active in any
power saving mode except STOP mode.
16-bit PPG timer × 3 ch./unit
CRC (Cyclic Redundancy Check) Accelerator
The following function can be used to achieve the motor
control.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
The CRC accelerator helps a verify data transmission or
storage integrity.
PWM signal output function
CCITT CRC16 Generator Polynomial: 0x1021
DC chopper waveform output function
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Quadrature Position/Revolution Counter (QPRC)
(Max 3 channels)
Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
Main Clock:
4 MHz to 48 MHz
Sub Clock:
32.768 kHz
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
High-speed internal CR Clock: 4 MHz
The detection edge of the three external event input pins AIN,
Main PLL Clock
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Low-speed internal CR Clock: 100 kHz
[Resets]
Reset requests from INITX pin
Power on reset
Software reset
Dual Timer (32-/16-bit Down Counter)
Watchdog timers reset
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
Low-voltage detector reset
Free-running
Clock Super Visor (CSV)
Clock supervisor reset
Periodic (=Reload)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
One-shot
External OSC clock failure (clock stop) is detected, reset is
asserted.
Watch Counter
The Watch counter is used for wake up from power saving
mode.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
Low-Voltage Detector (LVD)
External Interrupt Controller Unit
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
Up to 32 external interrupt input pin
Include one non-maskable interrupt(NMI)
Document Number: 002-04686 Rev.*C
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Page 3 of 128
MB9B310T Series
Low Power Mode
Power Supply
Three power saving modes supported.
Three Power Supplies
SLEEP
Wide range voltage VCC
TIMER
STOP
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM) provide comprehensive
debug and trace facilities.
Document Number: 002-04686 Rev.*C
= 2.7 V to 5.5 V
USBVCC0
= 3.0 V to 3.6 V: for USB ch.0 I/O voltage, when USB ch.0 is
used.
= 2.7 V to 5.5 V: when GPIO is used.
USBVCC1
= 3.0 V to 3.6 V: for USB ch.1 I/O voltage, when USB ch.1 is
used.
= 2.7 V to 5.5 V: when GPIO is used.
Page 4 of 128
MB9B310T Series
Contents
1. Product Lineup .................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment ................................................................................................................................................................. 9
4. List of Pin Functions....................................................................................................................................................... 12
5. I/O Circuit Type................................................................................................................................................................ 51
6. Handling Precautions ..................................................................................................................................................... 58
6.1
Precautions for Product Design ................................................................................................................................... 58
6.2
Precautions for Package Mounting .............................................................................................................................. 59
6.3
Precautions for Use Environment ................................................................................................................................ 60
7. Handling Devices ............................................................................................................................................................ 61
8. Block Diagram ................................................................................................................................................................. 64
9. Memory Size .................................................................................................................................................................... 65
10. Memory Map .................................................................................................................................................................... 65
11. Pin Status in Each CPU State ........................................................................................................................................ 68
12. Electrical Characteristics ............................................................................................................................................... 73
12.1 Absolute Maximum Ratings ......................................................................................................................................... 73
12.2 Recommended Operating Conditions.......................................................................................................................... 75
12.3 DC Characteristics....................................................................................................................................................... 76
12.3.1 Current Rating .............................................................................................................................................................. 76
12.3.2 Pin Characteristics ....................................................................................................................................................... 78
12.4 AC Characteristics ....................................................................................................................................................... 80
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 80
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 81
12.4.3 Internal CR Oscillation Characteristics ......................................................................................................................... 81
12.4.4 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL) ................................... 82
12.4.5 Operating Conditions of Main PLL (In the case of using high-speed internal CR)........................................................ 82
12.4.6 Reset Input Characteristics .......................................................................................................................................... 83
12.4.7 Power-on Reset Timing................................................................................................................................................ 83
12.4.8 External Bus Timing ..................................................................................................................................................... 84
12.4.9 Base Timer Input Timing .............................................................................................................................................. 93
12.4.10 CSIO/UART Timing .................................................................................................................................................. 94
12.4.11 External Input Timing .............................................................................................................................................. 102
12.4.12 Quadrature Position/Revolution Counter timing ...................................................................................................... 103
2
12.4.13 I C Timing ............................................................................................................................................................... 105
12.4.14 ETM Timing ............................................................................................................................................................ 106
12.4.15 JTAG Timing ........................................................................................................................................................... 107
12.5 12-bit A/D Converter .................................................................................................................................................. 108
12.6 USB characteristics ................................................................................................................................................... 111
12.7 Low-Voltage Detection Characteristics ...................................................................................................................... 115
12.7.1 Low-Voltage Detection Reset ..................................................................................................................................... 115
12.7.2 Interrupt of Low-Voltage Detection ............................................................................................................................. 115
12.8 Flash Memory Write/Erase Characteristics ............................................................................................................... 116
12.8.1 Write / Erase time....................................................................................................................................................... 116
12.8.2 Write cycles and data hold time ................................................................................................................................. 116
12.9 Return Time from Low-Power Consumption Mode .................................................................................................... 117
12.9.1 Return Factor: Interrupt .............................................................................................................................................. 117
12.9.2 Return Factor: Reset .................................................................................................................................................. 119
Document Number: 002-04686 Rev.*C
Page 5 of 128
MB9B310T Series
13. Ordering Information .................................................................................................................................................... 121
14. Package Dimensions .................................................................................................................................................... 122
15. Major Changes .............................................................................................................................................................. 125
Document History ............................................................................................................................................................... 127
Sales, Solutions, and Legal Information ........................................................................................................................... 128
Document Number: 002-04686 Rev.*C
Page 6 of 128
MB9B310T Series
1. Product Lineup
Memory Size
Product name
On-chip Flash memory
On-chip RAM
MB9BF316S/T
MB9BF317S/T
MB9BF318S/T
512 Kbyte
64 Kbyte
768 Kbyte
96 Kbyte
1 Mbyte
128 Kbyte
Function
MB9BF316S
MB9BF317S
MB9BF318S
Product name
Pin count
CPU
MB9BF316T
MB9BF317T
MB9BF318T
144
176/192
Cortex-M3
144 MHz
VCC:2.7 V to 5.5 V
( USBVCC0:3.0 V to 3.6 V )
( USBVCC1:3.0 V to 3.6 V )
2 ch. (Max)
8 ch.
Freq.
Power supply voltage range
USB2.0 (Device/Host)
DMAC
Addr:19-bit (Max)
R/Wdata:8-/16-bit (Max)
CS: 8 (Max)
Support: SRAM,
NOR & NAND Flash
External Bus Interface
8ch. (Max)
ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO
MF Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/ Reload timer/PWM/PPG)
A/D activation
compare
Input capture
MFFree-run timer
Timer
Output compare
Waveform generator
PPG
QPRC
Dual Timer
Watch Counter
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
High-speed
Built-in CR
Low-speed
Debug Function
Addr:25-bit (Max)
R/Wdata:8-/16-bit (Max)
CS:8 (Max)
Support: SRAM,
NOR & NAND Flash
16 ch. (Max)
3 ch.
4 ch.
3 ch.
6 ch.
3 ch.
3 ch.
3 units (Max)
3 ch. (Max)
1 unit
1 unit
Yes
1 ch. (SW) + 1 ch. (HW)
32 pins (Max) + NMI × 1
122 pins (Max)
24 ch. (3 units)
154 pins (Max)
32 ch. (3 units)
Yes
2 ch.
4 MHz
100 kHz
SWJ-DP/ETM
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use
the port relocate function of the General I/O port according to your function use.
See “12. Electrical Characteristics 12.4. AC Characteristics 12.4.3. Built-in CR Oscillation Characteristics" for accuracy of
built-in CR.
Document Number: 002-04686 Rev.*C
Page 7 of 128
MB9B310T Series
2. Packages
Product name
Package
MB9BF316S
MB9BF317S
MB9BF318S
MB9BF316T
MB9BF317T
MB9BF318T
LQFP:
LQS144 (0.5 mm pitch)
LQFP:
LQP176 (0.5 mm pitch)
-
BGA:
LBE192 (0.8 mm pitch)
-
-
: Supported
Note:
−
See "14. Package Dimensions" for detailed information on each package.
Document Number: 002-04686 Rev.*C
Page 8 of 128
MB9B310T Series
3. Pin Assignment
LQP176
VCC
P00/TRSTX
134
133
P02/TDI
P01/TCK/SWCLK
P03/TMS/SWDIO
137
136
135
P90/TIOB08_0/RTO20_1/INT30_0/MAD19_0
P04/TDO/SWO
P91/TIOB09_0/RTO21_1/INT31_0/MAD20_0
140
139
138
P93/TIOB11_0/RTO23_1/SOT5_1/MAD22_0
P92/TIOB10_0/RTO22_1/SIN5_1/MAD21_0
P94/TIOB12_0/RTO24_1/SCK5_1/INT26_0/MAD23_0
143
142
141
PC0
P95/TIOB13_0/RTO25_1/INT27_0/MAD24_0
PC1
146
145
144
PC3/TIOA06_1
PC2
PC4/TIOA08_2
149
148
147
PC6/TIOA14_0
PC5/TIOA10_2
PC7/CROUT_1
152
151
150
PC9
PC8
PCA
155
154
153
PCB
VSS
VCC
156
159
158
157
PCD
PCC
PCE/RTS4_0/TIOB06_1
161
160
PD0/SCK4_0/TIOB10_2/INT30_1
PCF/CTS4_0/TIOB08_2
PD1/SOT4_0/TIOB14_0/INT31_1
164
163
162
PD3/TIOB03_2
PD2/SIN4_0/TIOA03_2/INT00_2
P62/SCK5_0/ADTG_3
167
166
165
P60/SIN5_0/TIOA02_2/INT15_1
P61/SOT5_0/TIOB02_2/UHCONX0
PF3/TIOA06_0/SIN6_2/INT06_0/AIN2_1
170
169
168
USBVCC0
PF5/SCK6_2/INT08_0/ZIN2_1
PF4/TIOB06_0/SOT6_2/INT07_0/BIN2_1
171
174
173
172
P81/UDP0
VSS
176
175
P80/UDM0
(TOP VIEW)
VCC
1
132
VSS
PA0/RTO20_0/TIOA08_0/FRCK1_0
2
131
P83/UDP1
PA1/RTO21_0/TIOA09_0/IC10_0
3
130
P82/UDM1
PA2/RTO22_0/TIOA10_0/IC11_0
4
129
USBVCC1
PA3/RTO23_0/TIOA11_0/IC12_0
5
128
PF6/FRCK2_0/NMIX
PA4/RTO24_0/TIOA12_0/IC13_0/INT03_0
6
127
P20/INT05_0/CROUT_0/UHCONX1/AIN1_1/MAD18_0
PA5/RTO25_0/TIOA13_0/INT10_2
7
126
P21/SIN0_0/INT06_1/BIN1_1
P05/TRACED0/TIOA05_2/SIN4_2/INT00_1
8
125
P22/AN31/SOT0_0/TIOB07_1/ZIN1_1
P06/TRACED1/TIOB05_2/SOT4_2/INT01_1
9
124
P23/AN30/SCK0_0/TIOA07_1/RTO00_1
P07/TRACED2/ADTG_0/SCK4_2
10
123
P24/AN29/SIN2_1/INT01_2/RTO01_1/MAD17_0
P08/TRACED3/TIOA00_2/CTS4_2
11
122
P25/AN28/SOT2_1/RTO02_1/MAD16_0
P09/TRACECLK/TIOB00_2/RTS4_2/DTTI2X_0
12
121
P26/AN27/SCK2_1/RTO03_1/MAD15_0
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/IC20_0/MOEX_0
13
120
P27/AN26/INT02_2/RTO04_1/MAD14_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/IC21_0/MWEX_0
14
119
P28/AN25/ADTG_4/INT09_0/RTO05_1/MAD13_0
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/IC22_0/MDQM0_0
15
118
P29/AN24/MAD12_0
P53/SIN6_0/TIOA01_2/INT07_2/RTO13_0/IC23_0/MDQM1_0
16
117
PB7/AN23/TIOB12_1/INT23_0/ZIN2_2
P54/SOT6_0/TIOB01_2/RTO14_0/MALE_0
17
116
PB6/AN22/TIOA12_1/SCK0_2/INT22_0/BIN2_2
P55/SCK6_0/ADTG_1/RTO15_0/MRDY_0
18
115
PB5/AN21/TIOB11_1/SOT0_2/INT21_0/AIN2_2
P56/SIN1_0/INT08_2/TIOA09_2/DTTI1X_0/MNALE_0
19
114
PB4/AN20/TIOA11_1/SIN0_2/INT20_0
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
20
113
PB3/AN19/TIOB10_1/INT19_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
21
112
PB2/AN18/TIOA10_1/SCK7_2/INT18_0
P59/SIN7_0/TIOB11_2/INT09_2/MNREX_0
22
111
PB1/AN17/TIOB09_1/SOT7_2/INT17_0
P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_0
23
110
PB0/AN16/TIOA09_1/SIN7_2/INT16_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
24
109
VSS
P5C/TIOA06_2/INT28_0/IC20_1
25
108
AVSS
P5D/TIOB06_2/INT29_0/DTTI2X_1
26
107
AVRH
VSS
27
106
AVCC
P30/AIN0_0/TIOB00_1/INT03_2
28
105
P1F/AN15/ADTG_5/INT29_1/TIOB15_2/FRCK0_1/MAD11_0
P31/BIN0_0/TIOB01_1/SCK6_1/INT04_2
29
104
P1E/AN14/RTS4_1/INT28_1/TIOA15_2/DTTI0X_1/MAD10_0
P32/ZIN0_0/TIOB02_1/SOT6_1/INT05_2
30
103
P1D/AN13/CTS4_1/INT27_1/TIOB14_2/IC03_1/MAD09_0
P33/INT04_0/TIOB03_1/SIN6_1/ADTG_6
31
102
P1C/AN12/SCK4_1/INT26_1/TIOA14_2/IC02_1/MAD08_0
P34/FRCK0_0/TIOB04_1
32
101
P1B/AN11/SOT4_1/INT25_1/TIOB13_2/IC01_1/MAD07_0
P35/IC03_0/TIOB05_1/INT08_1
33
100
P1A/AN10/SIN4_1/INT05_1/TIOA13_2/IC00_1/MAD06_0
P36/IC02_0/SIN5_2/INT09_1/TIOA12_2/MCSX2_0
34
99
P19/AN09/SCK2_2/INT22_1/MAD05_0
P37/IC01_0/SOT5_2/INT10_1/TIOB12_2/MCSX3_0
35
98
P18/AN08/SOT2_2/INT21_1/MAD04_0
P38/IC00_0/SCK5_2/INT11_1/MCLKOUT_0
36
97
P17/AN07/SIN2_2/INT04_1/MAD03_0
P39/DTTI0X_0/ADTG_2
37
96
P16/AN06/SCK0_1/INT20_1/MAD02_0
P3A/RTO00_0/TIOA00_1
38
95
P15/AN05/SOT0_1/IC03_2/MAD01_0
P3B/RTO01_0/TIOA01_1
39
94
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD00_0
P3C/RTO02_0/TIOA02_1
40
93
P13/AN03/SCK1_1/IC01_2/MCSX4_0
P3D/RTO03_0/TIOA03_1
41
92
P12/AN02/SOT1_1/IC00_2/MCSX5_0
P3E/RTO04_0/TIOA04_1
42
91
P11/AN01/SIN1_1/INT02_1/FRCK0_2/MCSX6_0
P3F/RTO05_0/TIOA05_1
43
90
P10/AN00/MCSX7_0
VSS
44
89
VCC
87
88
PE3/X1
VSS
84
85
86
MD0
PE2/X0
PE0/MD1
81
82
83
PF0/TIOB15_1/SIN1_2/INT13_0/IC23_1
PF1/TIOA08_1/SOT1_2/INT14_0
P7E/TIOB14_1/IC21_1/INT24_0
P7F/TIOA15_1/IC22_1/INT25_0
PF2/TIOB08_1/SCK1_2/INT15_0
78
79
80
P7D/TIOA14_1/FRCK2_1/INT12_0
75
76
77
P7B/TIOB07_0/INT10_0
P7C/TIOA07_0/INT11_0
P78/AIN1_0/TIOA15_0/MADATA13_0
P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0
P7A/ZIN1_0/INT24_1/MADATA15_0
72
73
74
P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0
69
70
71
P74/SCK2_0/ZIN2_0/MADATA09_0
P75/SIN3_0/ADTG_8/INT07_1/MADATA10_0
P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0
66
67
68
P71/INT13_2/TIOB04_2/MADATA06_0
P72/SIN2_0/INT14_2/AIN2_0/MADATA07_0
65
P70/TIOA04_2/MADATA05_0
P73/SOT2_0/INT15_2/BIN2_0/MADATA08_0
62
63
64
P4C/TIOB03_0/IC13_1/SCK7_1/AIN1_2/MADATA02_0
P4E/TIOB05_0/INT06_2/SIN7_1/ZIN1_2/MADATA04_0
P4B/TIOB02_0/IC12_1/ZIN0_1/MADATA01_0
P4D/TIOB04_0/FRCK1_1/SOT7_1/BIN1_2/MADATA03_0
60
61
P4A/TIOB01_0/IC11_1/BIN0_1/SCK3_2/MADATA00_0
57
58
59
INITX
P48/DTTI1X_1/INT14_1/SIN3_2
P49/TIOB00_0/IC10_1/AIN0_1/SOT3_2
54
55
56
VCC
P46/X0A
P47/X1A
51
52
53
C
P44/TIOA04_0/RTO14_1
VSS
50
P42/TIOA02_0/RTO12_1
P45/TIOA05_0/RTO15_1
47
48
49
P41/TIOA01_0/RTO11_1/INT13_1
P43/TIOA03_0/RTO13_1/ADTG_7
45
46
VCC
P40/TIOA00_0/RTO10_1/INT12_1
LQFP - 176
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin. TIOA09_0, TIOA09_1, and TIOA09_2 cannot be used as the external startup trigger input (TGIN
signal) at I/O mode 1 (timer full mode) of the Base Timer. See "Base Timer" in "7. Handling Devices" for details.
Document Number: 002-04686 Rev.*C
Page 9 of 128
MB9B310T Series
LQS144
P00/TRSTX
P01/TCK/SWCLK
P02/TDI
P03/TMS/SWDIO
P04/TDO/SWO
PC0
PC1
PC2
PC3/TIOA06_1
PC4/TIOA08_2
PC5/TIOA10_2
PC6/TIOA14_0
PC7/CROUT_1
PC8
PC9
PCA
VCC
VSS
PCB
PCC
PCD
PCE/RTS4_0/TIOB06_1
PCF/CTS4_0/TIOB08_2
PD0/SCK4_0/TIOB10_2/INT30_1
PD1/SOT4_0/TIOB14_0/INT31_1
PD2/SIN4_0/TIOA03_2/INT00_2
PD3/TIOB03_2
P62/SCK5_0/ADTG_3
P61/SOT5_0/TIOB02_2/UHCONX0
P60/SIN5_0/TIOA02_2/INT15_1
PF5/SCK6_2/INT08_0/ZIN2_1
USBVCC0
P80/UDM0
P81/UDP0
VCC
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VSS
(TOP VIEW)
VCC
1
108
VSS
PA0/RTO20_0/TIOA08_0/FRCK1_0
2
107
P83/UDP1
PA1/RTO21_0/TIOA09_0/IC10_0
3
106
P82/UDM1
PA2/RTO22_0/TIOA10_0/IC11_0
4
105
USBVCC1
PA3/RTO23_0/TIOA11_0/IC12_0
5
104
PF6/FRCK2_0/NMIX
PA4/RTO24_0/TIOA12_0/IC13_0/INT03_0
6
103
P20/INT05_0/CROUT_0/UHCONX1/AIN1_1/MAD18_0
PA5/RTO25_0/TIOA13_0/INT10_2
7
102
P21/SIN0_0/INT06_1/BIN1_1
P05/TRACED0/TIOA05_2/SIN4_2/INT00_1
8
101
P22/AN31/SOT0_0/TIOB07_1/ZIN1_1
P06/TRACED1/TIOB05_2/SOT4_2/INT01_1
9
100
P23/AN30/SCK0_0/TIOA07_1/RTO00_1
P07/TRACED2/ADTG_0/SCK4_2
10
99
P24/AN29/SIN2_1/INT01_2/RTO01_1/MAD17_0
P08/TRACED3/TIOA00_2/CTS4_2
11
98
P25/AN28/SOT2_1/RTO02_1/MAD16_0
P09/TRACECLK/TIOB00_2/RTS4_2/DTTI2X_0
12
97
P26/AN27/SCK2_1/RTO03_1/MAD15_0
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/IC20_0/MOEX_0
13
96
P27/AN26/INT02_2/RTO04_1/MAD14_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/IC21_0/MWEX_0
14
95
P28/AN25/ADTG_4/INT09_0/RTO05_1/MAD13_0
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/IC22_0/MDQM0_0
15
94
P29/AN24/MAD12_0
P53/SIN6_0/TIOA01_2/INT07_2/RTO13_0/IC23_0/MDQM1_0
16
93
VSS
P54/SOT6_0/TIOB01_2/RTO14_0/MALE_0
17
92
AVSS
P55/SCK6_0/ADTG_1/RTO15_0/MRDY_0
18
91
AVRH
P56/SIN1_0/INT08_2/TIOA09_2/DTTI1X_0/MNALE_0
19
90
AVCC
LQFP - 144
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
20
89
P1F/AN15/ADTG_5/INT29_1/TIOB15_2/FRCK0_1/MAD11_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
21
88
P1E/AN14/RTS4_1/INT28_1/TIOA15_2/DTTI0X_1/MAD10_0
P59/SIN7_0/TIOB11_2/INT09_2/MNREX_0
22
87
P1D/AN13/CTS4_1/INT27_1/TIOB14_2/IC03_1/MAD09_0
P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_0
23
86
P1C/AN12/SCK4_1/INT26_1/TIOA14_2/IC02_1/MAD08_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
24
85
P1B/AN11/SOT4_1/INT25_1/TIOB13_2/IC01_1/MAD07_0
71
72
VSS
PE3/X1
69
68
70
PE2/X0
MD0
PE0/MD1
66
67
P7A/ZIN1_0/INT24_1/MADATA15_0
P78/AIN1_0/TIOA15_0/MADATA13_0
P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0
P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0
P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0
P75/SIN3_0/ADTG_8/INT07_1/MADATA10_0
P74/SCK2_0/ZIN2_0/MADATA09_0
P73/SOT2_0/INT15_2/BIN2_0/MADATA08_0
P72/SIN2_0/INT14_2/AIN2_0/MADATA07_0
P70/TIOA04_2/MADATA05_0
P71/INT13_2/TIOB04_2/MADATA06_0
P4E/TIOB05_0/INT06_2/SIN7_1/ZIN1_2/MADATA04_0
P4C/TIOB03_0/IC13_1/SCK7_1/AIN1_2/MADATA02_0
P4D/TIOB04_0/FRCK1_1/SOT7_1/BIN1_2/MADATA03_0
P4B/TIOB02_0/IC12_1/ZIN0_1/MADATA01_0
P49/TIOB00_0/IC10_1/AIN0_1/SOT3_2
P4A/TIOB01_0/IC11_1/BIN0_1/SCK3_2/MADATA00_0
P48/DTTI1X_1/INT14_1/SIN3_2
INITX
P47/X1A
VCC
P46/X0A
VSS
C
P45/TIOA05_0/RTO15_1
P44/TIOA04_0/RTO14_1
P42/TIOA02_0/RTO12_1
P43/TIOA03_0/RTO13_1/ADTG_7
VCC
P41/TIOA01_0/RTO11_1/INT13_1
P40/TIOA00_0/RTO10_1/INT12_1
65
VCC
64
73
63
36
62
P10/AN00/MCSX7_0
VSS
61
P11/AN01/SIN1_1/INT02_1/FRCK0_2/MCSX6_0
74
60
75
35
59
34
P3F/RTO05_0/TIOA05_1
58
P12/AN02/SOT1_1/IC00_2/MCSX5_0
P3E/RTO04_0/TIOA04_1
57
76
56
33
55
P13/AN03/SCK1_1/IC01_2/MCSX4_0
P3D/RTO03_0/TIOA03_1
54
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD00_0
77
53
78
32
52
31
P3C/RTO02_0/TIOA02_1
51
P15/AN05/SOT0_1/IC03_2/MAD01_0
P3B/RTO01_0/TIOA01_1
50
79
49
30
48
P16/AN06/SCK0_1/INT20_1/MAD02_0
P3A/RTO00_0/TIOA00_1
47
P17/AN07/SIN2_2/INT04_1/MAD03_0
80
46
81
29
45
28
P39/DTTI0X_0/ADTG_2
44
P18/AN08/SOT2_2/INT21_1/MAD04_0
P38/IC00_0/SCK5_2/INT11_1/MCLKOUT_0
43
82
42
27
41
P19/AN09/SCK2_2/INT22_1/MAD05_0
P37/IC01_0/SOT5_2/INT10_1/TIOB12_2/MCSX3_0
40
P1A/AN10/SIN4_1/INT05_1/TIOA13_2/IC00_1/MAD06_0
83
39
84
26
38
25
37
VSS
P36/IC02_0/SIN5_2/INT09_1/TIOA12_2/MCSX2_0
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin. TIOA09_0 and TIOA09_2 cannot be used as the external startup trigger input (TGIN signal) at I/O
mode 1 (timer full mode) of the Base Timer. See "Base Timer" in "7. Handling Devices" for details.
Document Number: 002-04686 Rev.*C
Page 10 of 128
MB9B310T Series
LBE192
1
A
2
3
UDP0 UDM0
4
5
(TOP VIEW)
6
7
8
9
10
11
12
13
14
USB
VSS PCD PCB VSS VCC PC8 VSS TCK VCC
VCC0
B
VSS PA0 PF5 PF3 P61 PD1 PCA PC1 P95 P92 TDO TMS
C
VCC PA1 PA2 PF4 P60 PD2 PCC PC5 PC0 P93 P90
D
PA5 PA4 P05 P06 PA3 PD3 PCE PC6 PC2 P94 P91 P21 P20 UDM1
E
VSS P07 P08 P09 P50 P62 PCF PC7 PC3 P25 P24 P23 P22 VCC1
F
P51 P52 P53 P54 P55 P56 PD0 PC9 PC4 P29 P28 P27 P26 VSS
G
VSS P57 P58 P59 P5A P5B VSS VSS PB7 PB6 PB5 PB4 PB3 AVSS
H
P5C P5D P30 P31 P32 P33 VSS VSS P1F P1E PB2 PB1 PB0 AVRH
J
VSS P37 P36 P35 P34 P70 VSS P76 P1D P1C P1B P1A P19 AVCC
K
P38 P39 P3A P3B P4A P4E VSS P74 P7B P7F P18 P16 P15 P17
L
P3C P3D P3E P43 P49 P4D VSS P73 P7A P7E P14 P13 P12 VSS
M
VSS P3F P42 P44 P48 P4C VSS P72 P79 PF0 PF2 P11 P10 VCC
N
VCC P40 P41 P45 INITX P4B VSS P71 P78 P7D PF1 MD0 MD1 VSS
P
TRSTX
VSS
TDI PF6 UDP1
USB
C
VSS VCC X0A X1A VSS P75 P77 P7C VSS
X0
X1
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin. TIOA09_0, TIOA09_1, and TIOA09_2 cannot be used as the external startup trigger input (TGIN
signal) at I/O mode 1 (timer full mode) of the Base Timer. See "Base Timer" in "7. Handling Devices" for details.
Document Number: 002-04686 Rev.*C
Page 11 of 128
MB9B310T Series
4. List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
LQFP-176
Pin No
LQFP-144
BGA-192
1
1
C1
Pin Name
I/O circuit
type
VCC
Pin state
type
-
PA0
2
2
B2
RTO20_0
TIOA08_0
G
I
G
I
G
I
G
I
G
H
G
H
E
F
E
F
FRCK1_0
PA1
3
3
C2
RTO21_0
TIOA09_0
IC10_0
PA2
4
4
C3
RTO22_0
TIOA10_0
IC11_0
PA3
5
5
D5
RTO23_0
TIOA11_0
IC12_0
PA4
RTO24_0
6
6
D2
TIOA12_0
IC13_0
INT03_0
PA5
7
7
D1
RTO25_0
TIOA13_0
INT10_2
P05
TRACED0
8
8
D3
TIOA05_2
SIN4_2
INT00_1
P06
TRACED1
9
9
D4
TIOB05_2
SOT4_2
INT01_1
Document Number: 002-04686 Rev.*C
Page 12 of 128
MB9B310T Series
Pin No
LQFP-144
LQFP-176
Pin Name
BGA-192
I/O circuit
type
Pin state
type
E
G
E
G
E
G
E
H
E
H
E
H
P07
10
10
E2
TRACED2
ADTG_0
SCK4_2
P08
11
11
E3
TRACED3
TIOA00_2
CTS4_2
P09
TRACECLK
12
12
E4
TIOB00_2
RTS4_2
DTTI2X_0
P50
INT00_0
AIN0_2
13
13
E5
SIN3_1
RTO10_0
IC20_0
MOEX_0
P51
INT01_0
BIN0_2
14
14
F1
SOT3_1
RTO11_0
IC21_0
MWEX_0
P52
INT02_0
ZIN0_2
15
15
F2
SCK3_1
RTO12_0
IC22_0
MDQM0_0
Document Number: 002-04686 Rev.*C
Page 13 of 128
MB9B310T Series
LQFP-176
Pin No
LQFP-144
BGA-192
Pin Name
I/O circuit
type
Pin state
type
E
H
E
I
E
I
E
H
E
H
E
H
E
H
P53
SIN6_0
TIOA01_2
16
16
F3
INT07_2
RTO13_0
IC23_0
MDQM1_0
P54
SOT6_0
17
17
F4
TIOB01_2
RTO14_0
MALE_0
P55
SCK6_0
18
18
F5
ADTG_1
RTO15_0
MRDY_0
P56
SIN1_0
19
19
F6
INT08_2
TIOA09_2
DTTI1X_0
MNALE_0
P57
SOT1_0
20
20
G2
TIOB09_2
INT16_1
MNCLE_0
P58
SCK1_0
21
21
G3
TIOA11_2
INT17_1
MNWEX_0
P59
SIN7_0
22
22
G4
TIOB11_2
INT09_2
MNREX_0
Document Number: 002-04686 Rev.*C
Page 14 of 128
MB9B310T Series
LQFP-176
Pin No
LQFP-144
BGA-192
Pin name
I/O circuit
type
Pin state
type
E
H
E
H
E
H
E
H
P5A
SOT7_0
23
23
G5
TIOA13_1
INT18_1
MCSX0_0
P5B
SCK7_0
24
24
G6
TIOB13_1
INT19_1
MCSX1_0
P5C
25
-
H1
TIOA06_2
INT28_0
IC20_1
P5D
26
-
H2
TIOB06_2
INT29_0
DTTI2X_1
27
25
J1
VSS
-
P30
28
-
H3
AIN0_0
TIOB00_1
E
H
E
H
E
H
E
H
INT03_2
P31
BIN0_0
29
-
H4
TIOB01_1
SCK6_1
INT04_2
P32
ZIN0_0
30
-
H5
TIOB02_1
SOT6_1
INT05_2
P33
INT04_0
31
-
H6
TIOB03_1
SIN6_1
ADTG_6
Document Number: 002-04686 Rev.*C
Page 15 of 128
MB9B310T Series
LQFP-176
Pin No
LQFP-144
BGA-192
32
-
J5
Pin name
I/O circuit
type
Pin state
type
E
I
E
H
E
H
E
H
E
H
E
I
G
I
G
I
G
I
P34
FRCK0_0
TIOB04_1
P35
33
-
J4
IC03_0
TIOB05_1
INT08_1
P36
IC02_0
34
26
J3
SIN5_2
INT09_1
TIOA12_2
MCSX2_0
P37
IC01_0
35
27
J2
SOT5_2
INT10_1
TIOB12_2
MCSX3_0
P38
IC00_0
36
28
K1
SCK5_2
INT11_1
MCLKOUT_0
P39
37
29
K2
DTTI0X_0
ADTG_2
P3A
38
30
K3
RTO00_0
TIOA00_1
P3B
39
31
K4
RTO01_0
TIOA01_1
P3C
40
32
L1
RTO02_0
TIOA02_1
Document Number: 002-04686 Rev.*C
Page 16 of 128
MB9B310T Series
LQFP-176
Pin No
LQFP-144
BGA-192
41
33
L2
Pin name
I/O circuit
type
Pin state
type
G
I
G
I
G
I
P3D
RTO03_0
TIOA03_1
P3E
42
34
L3
RTO04_0
TIOA04_1
P3F
43
35
M2
RTO05_0
44
36
M1
VSS
-
45
37
N1
VCC
-
TIOA05_1
P40
46
38
N2
TIOA00_0
RTO10_1
G
H
G
H
G
I
G
I
G
I
G
I
INT12_1
P41
47
39
N3
TIOA01_0
RTO11_1
INT13_1
P42
48
40
M3
TIOA02_0
RTO12_1
P43
49
41
L4
TIOA03_0
RTO13_1
ADTG_7
P44
50
42
M4
TIOA04_0
RTO14_1
P45
51
43
N4
52
44
P2
53
45
54
46
55
47
P5
56
48
P6
57
49
N5
TIOA05_0
RTO15_1
C
-
P3
VSS
-
P4
VCC
-
P46
X0A
P47
X1A
INITX
D
M
D
N
B
C
E
H
P48
58
50
M5
DTTI1X_1
INT14_1
SIN3_2
Document Number: 002-04686 Rev.*C
Page 17 of 128
MB9B310T Series
LQFP-176
Pin No
LQFP-144
BGA-192
Pin name
I/O circuit
type
Pin state
type
E
I
E
I
E
I
E
I
E
I
E
H
E
I
E
H
P49
TIOB00_0
59
51
L5
IC10_1
AIN0_1
SOT3_2
P4A
TIOB01_0
60
52
K5
IC11_1
BIN0_1
SCK3_2
MADATA00_0
P4B
TIOB02_0
61
53
N6
IC12_1
ZIN0_1
MADATA01_0
P4C
TIOB03_0
62
54
M6
IC13_1
SCK7_1
AIN1_2
MADATA02_0
P4D
TIOB04_0
63
55
L6
FRCK1_1
SOT7_1
BIN1_2
MADATA03_0
P4E
TIOB05_0
64
56
K6
INT06_2
SIN7_1
ZIN1_2
MADATA04_0
P70
65
57
J6
TIOA04_2
MADATA05_0
P71
66
58
N8
INT13_2
TIOB04_2
MADATA06_0
Document Number: 002-04686 Rev.*C
Page 18 of 128
MB9B310T Series
LQFP-176
Pin No
LQFP-144
BGA-192
Pin name
I/O circuit
type
Pin state
type
E
H
E
H
E
I
E
H
E
H
E
H
E
I
E
H
P72
SIN2_0
67
59
M8
INT14_2
AIN2_0
MADATA07_0
P73
SOT2_0
68
60
L8
INT15_2
BIN2_0
MADATA08_0
P74
69
61
K8
SCK2_0
ZIN2_0
MADATA09_0
P75
SIN3_0
70
62
P8
ADTG_8
INT07_1
MADATA10_0
P76
SOT3_0
71
63
J8
TIOA07_2
INT11_2
MADATA11_0
P77
SCK3_0
72
64
P9
TIOB07_2
INT12_2
MADATA12_0
P78
73
65
N9
AIN1_0
TIOA15_0
MADATA13_0
P79
BIN1_0
74
66
M9
TIOB15_0
INT23_1
MADATA14_0
-
-
E1
VSS
-
-
-
G1
VSS
-
Document Number: 002-04686 Rev.*C
Page 19 of 128
MB9B310T Series
LQFP-176
Pin No
LQFP-144
BGA-192
Pin name
I/O circuit
type
Pin state
type
E
H
E
H
E
H
E
H
E
H
E
H
I*
H
I*
H
I*
H
C
P
J
D
A
A
A
B
P7A
75
67
L9
ZIN1_0
INT24_1
MADATA15_0
P7B
76
-
K9
TIOB07_0
INT10_0
P7C
77
-
P10
TIOA07_0
INT11_0
P7D
78
-
N10
TIOA14_1
FRCK2_1
INT12_0
P7E
79
-
L10
TIOB14_1
IC21_1
INT24_0
P7F
80
-
K10
TIOA15_1
IC22_1
INT25_0
PF0
TIOB15_1
81
-
M10
SIN1_2
INT13_0
IC23_1
PF1
82
-
N11
TIOA08_1
SOT1_2
INT14_0
PF2
83
-
M11
TIOB08_1
SCK1_2
INT15_0
84
68
N13
85
69
N12
86
70
P12
87
71
P13
88
72
N14
Document Number: 002-04686 Rev.*C
PE0
MD1
MD0
PE2
X0
PE3
X1
VSS
-
Page 20 of 128
MB9B310T Series
LQFP-176
Pin No
LQFP-144
BGA-192
89
73
M14
VCC
-
-
-
L7
VSS
-
-
-
K7
VSS
-
90
74
M13
AN00
Pin name
I/O circuit
type
Pin state
type
P10
F
K
F
L
F
K
F
K
F
L
F
K
F
L
F
L
MCSX7_0
P11
AN01
91
75
M12
SIN1_1
INT02_1
FRCK0_2
MCSX6_0
P12
AN02
92
76
L13
SOT1_1
IC00_2
MCSX5_0
P13
AN03
93
77
L12
SCK1_1
IC01_2
MCSX4_0
P14
AN04
94
78
L11
SIN0_1
INT03_1
IC02_2
MAD00_0
P15
AN05
95
79
K13
SOT0_1
IC03_2
MAD01_0
P16
AN06
96
80
K12
SCK0_1
INT20_1
MAD02_0
P17
AN07
97
81
K14
SIN2_2
INT04_1
MAD03_0
Document Number: 002-04686 Rev.*C
Page 21 of 128
MB9B310T Series
LQFP-176
Pin No
LQFP-144
BGA-192
-
-
P7
VSS
-
-
-
P11
VSS
-
-
-
L14
VSS
-
Pin name
I/O circuit
type
Pin state
type
P18
AN08
98
82
K11
SOT2_2
F
L
F
L
F
L
F
L
F
L
F
L
INT21_1
MAD04_0
P19
AN09
99
83
J13
SCK2_2
INT22_1
MAD05_0
P1A
AN10
SIN4_1
100
84
J12
INT05_1
TIOA13_2
IC00_1
MAD06_0
P1B
AN11
SOT4_1
101
85
J11
INT25_1
TIOB13_2
IC01_1
MAD07_0
P1C
AN12
SCK4_1
102
86
J10
INT26_1
TIOA14_2
IC02_1
MAD08_0
P1D
AN13
CTS4_1
103
87
J9
INT27_1
TIOB14_2
IC03_1
MAD09_0
Document Number: 002-04686 Rev.*C
Page 22 of 128
MB9B310T Series
LQFP-176
Pin No
LQFP-144
BGA-192
Pin name
I/O circuit
type
Pin state
type
F
L
F
L
P1E
AN14
RTS4_1
104
88
H10
INT28_1
TIOA15_2
DTTI0X_1
MAD10_0
P1F
AN15
ADTG_5
105
89
H9
INT29_1
TIOB15_2
FRCK0_1
MAD11_0
106
90
J14
AVCC
-
107
91
H14
AVRH
-
108
92
G14
AVSS
-
109
93
F14
VSS
-
PB0
AN16
110
-
H13
TIOA09_1
F
L
F
L
F
L
F
L
F
L
SIN7_2
INT16_0
PB1
AN17
111
-
H12
TIOB09_1
SOT7_2
INT17_0
PB2
AN18
112
-
H11
TIOA10_1
SCK7_2
INT18_0
PB3
113
-
G13
AN19
TIOB10_1
INT19_0
PB4
AN20
114
-
G12
TIOA11_1
SIN0_2
INT20_0
Document Number: 002-04686 Rev.*C
Page 23 of 128
MB9B310T Series
LQFP-176
Pin No
LQFP-144
BGA-192
Pin name
I/O circuit
type
Pin state
type
F
L
PB5
AN21
115
-
G11
TIOB11_1
SOT0_2
INT21_0
AIN2_2
-
-
G7
VSS
-
-
-
J7
VSS
-
PB6
AN22
116
-
G10
TIOA12_1
SCK0_2
F
L
F
L
F
K
F
L
F
L
F
K
F
K
INT22_0
BIN2_2
PB7
AN23
117
-
G9
TIOB12_1
INT23_0
ZIN2_2
P29
118
94
F10
AN24
MAD12_0
P28
AN25
119
95
F11
ADTG_4
INT09_0
RTO05_1
MAD13_0
P27
AN26
120
96
F12
INT02_2
RTO04_1
MAD14_0
P26
AN27
121
97
F13
SCK2_1
RTO03_1
MAD15_0
P25
AN28
122
98
E10
SOT2_1
RTO02_1
MAD16_0
Document Number: 002-04686 Rev.*C
Page 24 of 128
MB9B310T Series
LQFP-176
Pin No
LQFP-144
BGA-192
Pin name
I/O circuit
type
Pin state
type
F
L
F
K
F
K
E
H
E
H
I*
J
P24
AN29
123
99
E11
SIN2_1
INT01_2
RTO01_1
MAD17_0
P23
AN30
124
100
E12
SCK0_0
TIOA07_1
RTO00_1
P22
AN31
125
101
E13
SOT0_0
TIOB07_1
ZIN1_1
P21
126
102
D12
SIN0_0
INT06_1
BIN1_1
P20
INT05_0
127
103
D13
CROUT_0
UHCONX1
AIN1_1
MAD18_0
PF6
128
104
C13
FRCK2_0
129
105
E14
USBVCC1
130
106
D14
131
107
C14
132
108
B14
VSS
-
133
109
A13
VCC
-
134
110
B13
135
111
A12
136
112
C12
NMIX
P82
UDM1
P83
UDP1
P00
TRSTX
H
O
H
O
E
E
E
E
E
E
P01
Document Number: 002-04686 Rev.*C
TCK
SWCLK
P02
TDI
Page 25 of 128
MB9B310T Series
LQFP-176
Pin No
LQFP-144
BGA-192
137
113
B12
TMS
SWDIO
138
114
B11
TDO
SWO
Pin name
I/O circuit
type
Pin state
type
E
E
E
E
E
H
P03
P04
P90
TIOB08_0
139
-
C11
RTO20_1
INT30_0
MAD19_0
-
-
A8
VSS
-
P91
TIOB09_0
140
-
D11
RTO21_1
E
H
E
I
E
I
E
H
E
H
INT31_0
MAD20_0
P92
TIOB10_0
141
-
B10
RTO22_1
SIN5_1
MAD21_0
P93
TIOB11_0
142
-
C10
RTO23_1
SOT5_1
MAD22_0
P94
TIOB12_0
143
-
D10
RTO24_1
SCK5_1
INT26_0
MAD23_0
P95
TIOB13_0
144
-
B9
RTO25_1
INT27_0
MAD24_0
145
115
C9
PC0
K
Q
146
147
116
B8
PC1
K
Q
117
D9
PC2
K
Q
148
118
E9
K
Q
Document Number: 002-04686 Rev.*C
PC3
TIOA06_1
Page 26 of 128
MB9B310T Series
LQFP-176
Pin No
LQFP-144
BGA-192
149
119
F9
150
120
C8
-
-
A5
151
121
D8
152
122
E8
153
123
A10
154
124
F8
155
125
156
157
158
128
A7
PCB
L
Q
159
129
C7
PCC
K
Q
160
130
A6
PCD
K
Q
L
Q
L
Q
L
R
L
R
Pin name
PC4
TIOA08_2
PC5
TIOA10_2
I/O circuit
type
Pin state
type
K
Q
K
Q
VSS
PC6
K
Q
L
Q
PC8
K
Q
PC9
K
Q
B7
PCA
K
Q
126
A9
VCC
-
127
A11
VSS
-
TIOA14_0
PC7
CROUT_1
PCE
161
131
D7
RTS4_0
TIOB06_1
PCF
162
132
E7
CTS4_0
TIOB08_2
PD0
163
133
F7
SCK4_0
TIOB10_2
INT30_1
PD1
SOT4_0
164
134
B6
-
-
N7
VSS
-
-
-
G8
VSS
-
-
-
H7
VSS
-
-
-
H8
VSS
-
TIOB14_0
INT31_1
Document Number: 002-04686 Rev.*C
Page 27 of 128
MB9B310T Series
Pin No
LQFP-144
LQFP-176
BGA-192
Pin name
I/O circuit
type
Pin state
type
L
R
L
Q
E
Q
E
I
E
H
I*
H
I*
H
I*
H
PD2
165
135
C6
SIN4_0
TIOA03_2
INT00_2
166
136
D6
167
137
E6
PD3
TIOB03_2
P62
SCK5_0
ADTG_3
P61
168
138
B5
SOT5_0
TIOB02_2
UHCONX0
P60
169
139
C5
SIN5_0
TIOA02_2
INT15_1
PF3
TIOA06_0
170
-
B4
SIN6_2
INT06_0
AIN2_1
PF4
TIOB06_0
171
-
C4
SOT6_2
INT07_0
BIN2_1
PF5
172
140
B3
SCK6_2
INT08_0
ZIN2_1
173
141
A4
-
USBVCC0
P80
H
O
H
O
174
142
A3
175
143
A2
176
144
B1
VSS
-
-
-
M7
VSS
-
UDM0
P81
UDP0
*: 5V tolerant I/O
Document Number: 002-04686 Rev.*C
Page 28 of 128
MB9B310T Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Module
Pin name
ADC
Function
Pin No.
LQFP-176
LQFP-144
BGA-192
ADTG_0
10
10
E2
ADTG_1
18
18
F5
K2
ADTG_2
37
29
ADTG_3
167
137
E6
119
95
F11
ADTG_5
105
89
H9
ADTG_6
31
-
H6
ADTG_7
49
41
L4
ADTG_8
70
62
P8
AN00
90
74
M13
AN01
91
75
M12
AN02
92
76
L13
AN03
93
77
L12
AN04
94
78
L11
AN05
95
79
K13
AN06
96
80
K12
AN07
97
81
K14
AN08
98
82
K11
AN09
99
83
J13
AN10
100
84
J12
AN11
101
85
J11
AN12
102
86
J10
AN13
103
87
J9
AN14
104
88
H10
105
89
H9
ADTG_4
AN15
AN16
A/D converter external trigger input pin
A/D converter analog input pin.
ANxx describes ADC ch.xx.
110
-
H13
AN17
111
-
H12
AN18
112
-
H11
AN19
113
-
G13
AN20
114
-
G12
AN21
115
-
G11
AN22
116
-
G10
AN23
117
-
G9
AN24
118
94
F10
AN25
119
95
F11
AN26
120
96
F12
AN27
121
97
F13
AN28
122
98
E10
AN29
123
99
E11
AN30
124
100
E12
AN31
125
101
E13
Document Number: 002-04686 Rev.*C
Page 29 of 128
MB9B310T Series
Module
Pin name
Base Timer
0
TIOA0_0
TIOA0_1
Base timer ch.0 TIOA pin
K3
E3
TIOB0_0
59
51
L5
28
-
H3
TIOB0_2
12
12
E4
TIOA1_0
47
39
N3
TIOA1_1
Base timer ch.0 TIOB pin
39
31
K4
TIOA1_2
16
16
F3
TIOB1_0
60
52
K5
29
-
H4
17
17
F4
Base timer ch.1 TIOA pin
48
40
M3
40
32
L1
169
139
C5
61
53
N6
30
-
H5
168
138
B5
49
41
L4
41
33
L2
165
135
C6
62
54
M6
31
-
H6
TIOB3_2
166
136
D6
TIOA4_0
50
42
M4
42
34
L3
TIOA4_2
65
57
J6
TIOB4_0
63
55
L6
32
-
J5
TIOB4_2
66
58
N8
TIOA5_0
51
43
N4
43
35
M2
Base timer ch.1 TIOB pin
TIOA2_0
TIOA2_1
TIOB2_1
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
TIOB2_2
TIOA3_0
TIOA3_1
Base timer ch.3 TIOA pin
TIOA3_2
TIOB3_0
TIOB3_1
TIOA4_1
TIOB4_1
TIOA5_1
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
TIOA5_2
8
8
D3
TIOB5_0
64
56
K6
33
-
J4
TIOB5_2
9
9
D4
TIOA6_0
170
-
B4
TIOB5_1
Base Timer
6
N2
11
TIOB2_0
Base Timer
5
38
30
TIOA2_2
Base Timer
4
BGA-192
46
11
TIOB1_2
Base Timer
3
LQFP-144
38
TIOB1_1
Base Timer
2
Pin No.
LQFP-176
TIOA0_2
TIOB0_1
Base Timer
1
Function
TIOA6_1
Base timer ch.5 TIOB pin
148
118
E9
TIOA6_2
25
-
H1
TIOB6_0
171
-
C4
161
131
D7
26
-
H2
TIOB6_1
TIOB6_2
Document Number: 002-04686 Rev.*C
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
Page 30 of 128
MB9B310T Series
Module
Pin name
Base Timer
7
TIOA07_0
TIOA07_1
Base timer ch.7 TIOA pin
E12
J8
TIOB07_0
76
-
K9
125
101
E13
TIOB07_2
72
64
P9
TIOA08_0
2
2
B2
TIOA08_1
Base timer ch.7 TIOB pin
82
-
N11
TIOA08_2
149
119
F9
TIOB08_0
139
-
C11
Base timer ch.8 TIOA pin
Base timer ch.8 TIOB pin
TIOA09_0
TIOA09_1
TIOB09_1
Base timer ch.9 TIOA pin
Base timer ch.9 TIOB pin
TIOB09_2
TIOA10_0
83
-
M11
162
132
E7
3
3
C2
110
-
H13
19
19
F6
140
-
D11
111
-
H12
20
20
G2
4
4
C3
112
-
H11
150
120
C8
141
-
B10
113
-
G13
TIOB10_2
163
133
F7
TIOA11_0
5
5
D5
114
-
G12
TIOA11_2
21
21
G3
TIOB11_0
142
-
C10
115
-
G11
TIOB11_2
22
22
G4
TIOA12_0
6
6
D2
116
-
G10
TIOA12_2
34
26
J3
TIOB12_0
143
-
D10
117
-
G9
TIOB12_2
35
27
J2
TIOA13_0
7
7
D1
TIOA10_1
Base timer ch.10 TIOA pin
TIOA10_2
TIOB10_0
TIOB10_1
TIOA11_1
TIOB11_1
TIOA12_1
TIOB12_1
Base Timer
13
P10
63
TIOB09_0
Base Timer
12
100
TIOA09_2
Base Timer
11
BGA-192
77
71
TIOB08_2
Base Timer
10
LQFP-144
124
TIOB08_1
Base Timer
9
Pin No.
LQFP-176
TIOA07_2
TIOB07_1
Base Timer
8
Function
TIOA13_1
Base timer ch.10 TIOB pin
Base timer ch.11 TIOA pin
Base timer ch.11 TIOB pin
Base timer ch.12 TIOA pin
Base timer ch.12 TIOB pin
23
23
G5
TIOA13_2
100
84
J12
TIOB13_0
144
-
B9
24
24
G6
101
85
J11
TIOB13_1
TIOB13_2
Document Number: 002-04686 Rev.*C
Base timer ch.13 TIOA pin
Base timer ch.13 TIOB pin
Page 31 of 128
MB9B310T Series
Module
Pin name
Base Timer
14
TIOA14_0
TIOA14_1
Base timer ch.14 TIOA pin
LQFP-144
BGA-192
151
121
D8
78
-
N10
102
86
J10
TIOB14_0
164
134
B6
79
-
L10
TIOB14_2
103
87
J9
TIOA15_0
73
65
N9
TIOA15_1
Base timer ch.14 TIOB pin
80
-
K10
TIOA15_2
104
88
H10
TIOB15_0
74
66
M9
81
-
M10
105
89
H9
TIOB15_1
Base timer ch.15 TIOA pin
Base timer ch.15 TIOB pin
TIOB15_2
Debugger
Pin No.
LQFP-176
TIOA14_2
TIOB14_1
Base Timer
15
Function
SWCLK
Serial wire debug interface clock input pin
135
111
A12
SWDIO
Serial wire debug interface data input / output pin
137
113
B12
SWO
Serial wire viewer output pin
138
114
B11
TCK
JTAG test clock input pin
135
111
A12
TDI
JTAG test data input pin
136
112
C12
TDO
JTAG debug data output pin
138
114
B11
TMS
JTAG test mode state input/output pin
137
113
B12
Trace CLK output pin of ETM
12
12
E4
8
8
D3
9
9
D4
10
10
E2
TRACECLK
TRACED0
TRACED1
TRACED2
Trace data output pin of ETM
TRACED3
TRSTX
Document Number: 002-04686 Rev.*C
JTAG test reset input pin
11
11
E3
134
110
B13
Page 32 of 128
MB9B310T Series
Module
Pin name
External
Bus
Function
Pin No.
LQFP-176
LQFP-144
BGA-192
MAD00_0
94
78
L11
MAD01_0
95
79
K13
MAD02_0
96
80
K12
MAD03_0
97
81
K14
MAD04_0
98
82
K11
MAD05_0
99
83
J13
MAD06_0
100
84
J12
MAD07_0
101
85
J11
MAD08_0
102
86
J10
MAD09_0
103
87
J9
MAD10_0
104
88
H10
MAD11_0
105
89
H9
MAD12_0
118
94
F10
MAD13_0
119
95
F11
MAD14_0
120
96
F12
MAD15_0
121
97
F13
MAD16_0
122
98
E10
MAD17_0
123
99
E11
MAD18_0
127
103
D13
MAD19_0
139
-
C11
MAD20_0
140
-
D11
MAD21_0
141
-
B10
MAD22_0
142
-
C10
MAD23_0
143
-
D10
MAD24_0
144
-
B9
MCSX0_0
23
23
G5
MCSX1_0
24
24
G6
MCSX2_0
34
26
J3
35
27
J2
MCSX3_0
MCSX4_0
External bus interface address bus
External bus interface chip select output pin
93
77
L12
MCSX5_0
92
76
L13
MCSX6_0
91
75
M12
MCSX7_0
90
74
M13
MDQM0_0
15
15
F2
16
16
F3
13
13
E5
14
14
F1
MDQM1_0
MOEX_0
MWEX_0
Document Number: 002-04686 Rev.*C
External bus interface byte mask signal output pin
External bus interface read enable signal for
SRAM
External bus interface write enable signal for
SRAM
Page 33 of 128
MB9B310T Series
Module
External
Bus
Pin name
Function
Pin No.
LQFP-176
LQFP-144
BGA-192
19
19
F6
20
20
G2
22
22
G4
21
21
G3
MADATA00_0
60
52
K5
MADATA01_0
61
53
N6
MADATA02_0
62
54
M6
MADATA03_0
63
55
L6
MADATA04_0
64
56
K6
MADATA05_0
65
57
J6
MADATA06_0
66
58
N8
MADATA07_0
67
59
M8
MNALE_0
MNCLE_0
MNREX_0
MNWEX_0
MADATA08_0
External bus interface ALE signal to control NAND
Flash output pin
External bus interface CLE signal to control NAND
Flash output pin
External bus interface read enable signal to control
NAND Flash
External bus interface write enable signal to
control NAND Flash
External bus interface data bus
(Address / data multiplex bus)
68
60
L8
MADATA09_0
69
61
K8
MADATA10_0
70
62
P8
MADATA11_0
71
63
J8
MADATA12_0
72
64
P9
MADATA13_0
73
65
N9
MADATA14_0
74
66
M9
MADATA15_0
75
67
L9
MALE_0
External bus interface Address Latch enable
output signal for multiplex
17
17
F4
MRDY_0
External bus interface external RDY input signal
18
18
F5
MCLKOUT_0
External bus interface external clock output pin
36
28
K1
Document Number: 002-04686 Rev.*C
Page 34 of 128
MB9B310T Series
Module
Pin name
External
Interrupt
INT00_0
Function
Pin No.
LQFP-176
LQFP-144
13
13
E5
8
8
D3
INT00_2
165
135
C6
INT01_0
14
14
F1
9
9
D4
INT01_2
123
99
E11
INT02_0
15
15
F2
91
75
M12
INT02_2
120
96
F12
INT03_0
6
6
D2
94
78
L11
INT03_2
28
-
H3
INT04_0
31
-
H6
97
81
K14
INT00_1
INT01_1
INT02_1
INT03_1
INT04_1
External interrupt request 00 input pin
External interrupt request 01 input pin
External interrupt request 02 input pin
External interrupt request 03 input pin
External interrupt request 04 input pin
BGA-192
INT04_2
29
-
H4
INT05_0
127
103
D13
100
84
J12
30
-
H5
INT05_1
External interrupt request 05 input pin
INT05_2
INT06_0
170
-
B4
126
102
D12
64
56
K6
171
-
C4
70
62
P8
16
16
F3
172
140
B3
33
-
J4
19
19
F6
119
95
F11
34
26
J3
22
22
G4
76
-
K9
35
27
J2
INT10_2
7
7
D1
INT11_0
77
-
P10
K1
INT06_1
External interrupt request 06 input pin
INT06_2
INT07_0
INT07_1
External interrupt request 07 input pin
INT07_2
INT08_0
INT08_1
External interrupt request 08 input pin
INT08_2
INT09_0
INT09_1
External interrupt request 09 input pin
INT09_2
INT10_0
INT10_1
INT11_1
External interrupt request 10 input pin
36
28
INT11_2
71
63
J8
INT12_0
78
-
N10
N2
INT12_1
External interrupt request 11 input pin
46
38
INT12_2
72
64
P9
INT13_0
81
-
M10
N3
INT13_1
External interrupt request 12 input pin
47
39
INT13_2
66
58
N8
INT14_0
82
-
N11
58
50
M5
67
59
M8
INT14_1
INT14_2
Document Number: 002-04686 Rev.*C
External interrupt request 13 input pin
External interrupt request 14 input pin
Page 35 of 128
MB9B310T Series
Module
Pin name
External
Interrupt
INT15_0
INT15_1
Function
External interrupt request 15 input pin
INT15_2
INT16_0
INT16_1
INT17_0
INT17_1
INT18_0
INT18_1
INT19_0
INT19_1
INT20_0
INT20_1
INT21_0
INT21_1
INT22_0
INT22_1
INT23_0
INT23_1
INT24_0
INT24_1
INT25_0
INT25_1
INT26_0
INT26_1
INT27_0
INT27_1
INT28_0
INT28_1
INT29_0
INT29_1
INT30_0
INT30_1
INT31_0
INT31_1
NMIX
Document Number: 002-04686 Rev.*C
External interrupt request 16 input pin
External interrupt request 17 input pin
External interrupt request 18 input pin
External interrupt request 19 input pin
External interrupt request 20 input pin
External interrupt request 21 input pin
External interrupt request 22 input pin
External interrupt request 23 input pin
External interrupt request 24 input pin
External interrupt request 25 input pin
External interrupt request 26 input pin
External interrupt request 27 input pin
External interrupt request 28 input pin
External interrupt request 29 input pin
External interrupt request 30 input pin
External interrupt request 31 input pin
Non-Maskable Interrupt input pin
Pin No.
LQFP-176
LQFP-144
BGA-192
83
-
M11
169
139
C5
68
60
L8
110
-
H13
20
20
G2
111
-
H12
21
21
G3
112
-
H11
23
23
G5
113
-
G13
24
24
G6
114
-
G12
96
80
K12
115
-
G11
98
82
K11
116
-
G10
99
83
J13
117
-
G9
74
66
M9
79
-
L10
75
67
L9
80
-
K10
101
85
J11
143
-
D10
102
86
J10
144
-
B9
103
87
J9
25
-
H1
104
88
H10
26
-
H2
105
89
H9
139
-
C11
163
133
F7
140
-
D11
164
134
B6
128
104
C13
Page 36 of 128
MB9B310T Series
Module
Pin name
GPIO
Function
Pin No.
LQFP-176
LQFP-144
BGA-192
P00
134
110
B13
P01
135
111
A12
P02
136
112
C12
P03
137
113
B12
P04
138
114
B11
P05
General-purpose I/O port 0
8
8
D3
P06
9
9
D4
P07
10
10
E2
P08
11
11
E3
P09
12
12
E4
P10
90
74
M13
P11
91
75
M12
P12
92
76
L13
P13
93
77
L12
P14
94
78
L11
P15
95
79
K13
P16
96
80
K12
97
81
K14
98
82
K11
P17
P18
General-purpose I/O port 1
P19
99
83
J13
P1A
100
84
J12
P1B
101
85
J11
P1C
102
86
J10
P1D
103
87
J9
P1E
104
88
H10
P1F
105
89
H9
P20
127
103
D13
P21
126
102
D12
P22
125
101
E13
P23
124
100
E12
123
99
E11
122
98
E10
P26
121
97
F13
P27
120
96
F12
P28
119
95
F11
P29
118
94
F10
P24
P25
Document Number: 002-04686 Rev.*C
General-purpose I/O port 2
Page 37 of 128
MB9B310T Series
Module
Pin name
GPIO
Function
Pin No.
LQFP-176
LQFP-144
BGA-192
P30
28
-
H3
P31
29
-
H4
P32
30
-
H5
P33
31
-
H6
P34
32
-
J5
P35
33
-
J4
P36
34
26
J3
P37
35
27
J2
P38
General-purpose I/O port 3
36
28
K1
P39
37
29
K2
P3A
38
30
K3
P3B
39
31
K4
P3C
40
32
L1
P3D
41
33
L2
P3E
42
34
L3
P3F
43
35
M2
P40
46
38
N2
P41
47
39
N3
P42
48
40
M3
P43
49
41
L4
P44
50
42
M4
P45
51
43
N4
P46
55
47
P5
56
48
P6
P48
58
50
M5
P49
59
51
L5
P4A
60
52
K5
P47
General-purpose I/O port 4
P4B
61
53
N6
P4C
62
54
M6
P4D
63
55
L6
P4E
64
56
K6
P50
13
13
E5
P51
14
14
F1
P52
15
15
F2
P53
16
16
F3
P54
17
17
F4
P55
18
18
F5
P56
19
19
F6
20
20
G2
P58
21
21
G3
P57
General-purpose I/O port 5
P59
22
22
G4
P5A
23
23
G5
P5B
24
24
G6
P5C
25
-
H1
P5D
26
-
H2
Document Number: 002-04686 Rev.*C
Page 38 of 128
MB9B310T Series
Module
Pin name
GPIO
P60
P61
Function
LQFP-144
BGA-192
169
139
C5
168
138
B5
P62
167
137
E6
P70
65
57
J6
P71
66
58
N8
P72
67
59
M8
P73
68
60
L8
P74
69
61
K8
P75
70
62
P8
P76
71
63
J8
P77
72
64
P9
P78
General-purpose I/O port 6
Pin No.
LQFP-176
General-purpose I/O port 7
73
65
N9
P79
74
66
M9
P7A
75
67
L9
P7B
76
-
K9
P7C
77
-
P10
P7D
78
-
N10
P7E
79
-
L10
P7F
80
-
K10
P80
174
142
A3
P81
175
143
A2
P82
General-purpose I/O port 8
130
106
D14
P83
131
107
C14
P90
139
-
C11
P91
140
-
D11
141
-
B10
P92
P93
General-purpose I/O port 9
142
-
C10
P94
143
-
D10
P95
144
-
B9
PA0
2
2
B2
PA1
3
3
C2
PA2
4
4
C3
5
5
D5
6
6
D2
PA5
7
7
D1
PB0
110
-
H13
PB1
111
-
H12
PB2
112
-
H11
113
-
G13
114
-
G12
PB5
115
-
G11
PB6
116
-
G10
PB7
117
-
G9
PA3
General-purpose I/O port A
PA4
PB3
PB4
Document Number: 002-04686 Rev.*C
General-purpose I/O port B
Page 39 of 128
MB9B310T Series
Module
Pin name
GPIO
Function
Pin No.
LQFP-176
LQFP-144
BGA-192
PC0
145
115
C9
PC1
146
116
B8
PC2
147
117
D9
PC3
148
118
E9
PC4
149
119
F9
PC5
150
120
C8
PC6
151
121
D8
152
122
E8
153
123
A10
PC7
PC8
General-purpose I/O port C
PC9
154
124
F8
PCA
155
125
B7
PCB
158
128
A7
PCC
159
129
C7
PCD
160
130
A6
PCE
161
131
D7
PCF
162
132
E7
PD0
163
133
F7
164
134
B6
165
135
C6
PD3
166
136
D6
PE0
84
68
N13
PD1
PD2
PE2
General-purpose I/O port D
86
70
P12
PE3
87
71
P13
PF0
81
-
M10
PF1
82
-
N11
PF2
83
-
M11
PF3
General-purpose I/O port E
170
-
B4
PF4
171
-
C4
PF5
172
140
B3
PF6
128
104
C13
Document Number: 002-04686 Rev.*C
General-purpose I/O port F*
Page 40 of 128
MB9B310T Series
Module
Pin name
Multifunction Serial
0
SIN0_0
SIN0_1
Function
Multi-function serial interface ch.0 input pin
LQFP-144
BGA-192
126
102
D12
94
78
L11
114
-
G12
125
101
E13
95
79
K13
115
-
G11
124
100
E12
96
80
K12
SCK0_2
(SCL0_2)
116
-
G10
SIN1_0
19
19
F6
91
75
M12
81
-
M10
20
20
G2
92
76
L13
82
-
N11
21
21
G3
93
77
L12
83
-
M11
SIN0_2
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA0 when it is used in an I2C (operation mode 4).
SOT0_2
(SDA0_2)
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
Multifunction Serial
1
Pin No.
LQFP-176
SIN1_1
Multi-function serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a
CSIO (operation mode 2) and as SCL0 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.1 input pin
SIN1_2
SOT1_0
(SDA1_0)
SOT1_1
(SDA1_1)
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA1 when it is used in an I2C (operation mode 4).
SOT1_2
(SDA1_2)
SCK1_0
(SCL1_0)
SCK1_1
(SCL1_1)
SCK1_2
(SCL1_2)
Document Number: 002-04686 Rev.*C
Multi-function serial interface ch.1 clock I/O pin.
This pin operates as SCK1 when it is used in a
CSIO (operation mode 2) and as SCL1 when it is
used in an I2C (operation mode 4).
Page 41 of 128
MB9B310T Series
Module
Pin name
Multifunction Serial
2
SIN2_0
SIN2_1
Function
BGA-192
67
59
M8
123
99
E11
97
81
K14
SOT2_0
(SDA2_0)
68
60
L8
122
98
E10
98
82
K11
69
61
K8
121
97
F13
SCK2_2
(SCL2_2)
99
83
J13
SIN3_0
70
62
P8
13
13
E5
58
50
M5
71
63
J8
14
14
F1
59
51
L5
72
64
P9
15
15
F2
60
52
K5
Multi-function serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA2 when it is used in an I2C (operation mode 4).
SOT2_2
(SDA2_2)
SCK2_0
(SCL2_0)
SCK2_1
(SCL2_1)
Multifunction Serial
3
LQFP-144
SIN2_2
SOT2_1
(SDA2_1)
Multi-function serial interface ch.2 input pin
Pin No.
LQFP-176
SIN3_1
Multi-function serial interface ch.2 clock I/O pin.
This pin operates as SCK2 when it is used in a
CSIO (operation mode 2) and as SCL2 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.3 input pin
SIN3_2
SOT3_0
(SDA3_0)
SOT3_1
(SDA3_1)
Multi-function serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA3 when it is used in an I2C (operation mode 4).
SOT3_2
(SDA3_2)
SCK3_0
(SCL3_0)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
Document Number: 002-04686 Rev.*C
Multi-function serial interface ch.3 clock I/O pin.
This pin operates as SCK3 when it is used in a
CSIO (operation mode 2) and as SCL3 when it is
used in an I2C (operation mode 4).
Page 42 of 128
MB9B310T Series
Module
Pin name
Multifunction Serial
4
SIN4_0
SIN4_1
Function
Multi-function serial interface ch.4 input pin
SIN4_2
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
Multi-function serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA4 when it is used in an I2C (operation mode 4).
SOT4_2
(SDA4_2)
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
Multi-function serial interface ch.4 clock I/O pin.
This pin operates as SCK4 when it is used in a
CSIO (operation mode 2) and as SCL4 when it is
used in an I2C (operation mode 4).
SCK4_2
(SCL4_2)
RTS4_0
RTS4_1
LQFP-144
BGA-192
165
135
C6
100
84
J12
8
8
D3
164
134
B6
101
85
J11
9
9
D4
163
133
F7
102
86
J10
10
10
E2
161
131
D7
104
88
H10
RTS4_2
12
12
E4
CTS4_0
162
132
E7
103
87
J9
CTS4_1
Multifunction Serial
5
Multi-function serial interface ch.4 RTS output pin
Pin No.
LQFP-176
Multi-function serial interface ch.4 CTS input pin
CTS4_2
11
11
E3
SIN5_0
169
139
C5
SIN5_1
141
-
B10
SIN5_2
34
26
J3
SOT5_0
(SDA5_0)
168
138
B5
142
-
C10
35
27
J2
167
137
E6
143
-
D10
36
28
K1
SOT5_1
(SDA5_1)
Multi-function serial interface ch.5 input pin
Multi-function serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA5 when it is used in an I2C (operation mode 4).
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
SCK5_1
(SCL5_1)
SCK5_2
(SCL5_2)
Document Number: 002-04686 Rev.*C
Multi-function serial interface ch.5 clock I/O pin.
This pin operates as SCK5 when it is used in a
CSIO (operation mode 2) and as SCL5 when it is
used in an I2C (operation mode 4).
Page 43 of 128
MB9B310T Series
Module
Pin name
Multifunction Serial
6
SIN6_0
SIN6_1
Function
BGA-192
16
16
F3
31
-
H6
170
-
B4
SOT6_0
(SDA6_0)
17
17
F4
30
-
H5
171
-
C4
18
18
F5
29
-
H4
SCK6_2
(SCL6_2)
172
140
B3
SIN7_0
22
22
G4
Multi-function serial interface ch.6 output pin.
This pin operates as SOT6 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA6 when it is used in an I2C (operation mode 4).
SOT6_2
(SDA6_2)
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
Multifunction Serial
7
LQFP-144
SIN6_2
SOT6_1
(SDA6_1)
Multi-function serial interface ch.6 input pin
Pin No.
LQFP-176
SIN7_1
Multi-function serial interface ch.6 clock I/O pin.
This pin operates as SCK6 when it is used in a
CSIO (operation mode 2) and as SCL6 when it is
used in an I2C (operation mode 4).
Multi-function serial interface ch.7 input pin
64
56
K6
110
-
H13
23
23
G5
63
55
L6
SOT7_2
(SDA7_2)
111
-
H12
SCK7_0
(SCL7_0)
24
24
G6
62
54
M6
112
-
H11
SIN7_2
SOT7_0
(SDA7_0)
SOT7_1
(SDA7_1)
SCK7_1
(SCL7_1)
SCK7_2
(SCL7_2)
Document Number: 002-04686 Rev.*C
Multi-function serial interface ch.7 output pin.
This pin operates as SOT7 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as
SDA7 when it is used in an I2C (operation mode 4).
Multi-function serial interface ch.7 clock I/O pin.
This pin operates as SCK7 when it is used in a
CSIO (operation mode 2) and as SCL7 when it is
used in an I2C (operation mode 4).
Page 44 of 128
MB9B310T Series
Pin No.
Module
Multifunction Timer
0
Pin name
DTTI0X_0
DTTI0X_1
Function
Input signal controlling wave form generator
outputs RTO00 to RTO05 of Multi-function timer 0.
FRCK0_0
LQFP-176
LQFP-144
BGA-192
37
29
K2
104
88
H10
32
-
J5
105
89
H9
FRCK0_2
91
75
M12
IC00_0
36
28
K1
IC00_1
100
84
J12
IC00_2
92
76
L13
IC01_0
35
27
J2
IC01_1
101
85
J11
93
77
L12
34
26
J3
IC02_1
102
86
J10
IC02_2
94
78
L11
FRCK0_1
IC01_2
IC02_0
16-bit free-run timer ch.0 external clock input pin
16-bit input capture ch.0 input pin of Multi-function
timer 0.
ICxx describes channel number.
IC03_0
33
-
J4
IC03_1
103
87
J9
IC03_2
95
79
K13
38
30
K3
124
100
E12
39
31
K4
123
99
E11
40
32
L1
122
98
E10
41
33
L2
121
97
F13
42
34
L3
120
96
F12
43
35
M2
119
95
F11
RTO00_0
(PPG00_0)
RTO00_1
(PPG00_1)
RTO01_0
(PPG00_0)
RTO01_1
(PPG00_1)
RTO02_0
(PPG02_0)
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
RTO03_1
(PPG02_1)
RTO04_0
(PPG04_0)
RTO04_1
(PPG04_1)
RTO05_0
(PPG04_0)
RTO05_1
(PPG04_1)
Document Number: 002-04686 Rev.*C
Wave form generator output of Multi-function timer
0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
Wave form generator output of Multi-function timer
0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
Wave form generator output of Multi-function timer
0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
Wave form generator output of Multi-function timer
0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
Wave form generator output of Multi-function timer
0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
Wave form generator output of Multi-function timer
0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
Page 45 of 128
MB9B310T Series
Pin No.
Module
Multifunction Timer
1
Pin name
DTTI1X_0
DTTI1X_1
FRCK1_0
FRCK1_1
Function
Input signal controlling wave form generator outputs
RTO10 to RTO15 of Multi-function timer 1
16-bit free-run timer ch.1 external clock input pin
LQFP-176
LQFP-144
BGA-192
19
19
F6
58
50
M5
2
2
B2
63
55
L6
IC10_0
3
3
C2
IC10_1
59
51
L5
IC11_0
4
4
C3
60
52
K5
5
5
D5
IC12_1
61
53
N6
IC13_0
6
6
D2
IC13_1
62
54
M6
Wave form generator output of Multi-function timer 1.
This pin operates as PPG10 when it is used in PPG1
output modes.
13
13
E5
46
38
N2
Wave form generator output of Multi-function timer 1.
This pin operates as PPG10 when it is used in PPG1
output modes.
14
14
F1
47
39
N3
Wave form generator output of Multi-function timer 1.
This pin operates as PPG12 when it is used in PPG1
output modes.
15
15
F2
48
40
M3
Wave form generator output of Multi-function timer 1.
This pin operates as PPG12 when it is used in PPG1
output modes.
16
16
F3
49
41
L4
Wave form generator output of Multi-function timer 1.
This pin operates as PPG14 when it is used in PPG1
output modes.
17
17
F4
50
42
M4
Wave form generator output of Multi-function timer 1.
This pin operates as PPG14 when it is used in PPG1
output modes.
18
18
F5
51
43
N4
IC11_1
IC12_0
RTO10_0
(PPG10_0)
RTO10_1
(PPG10_1)
RTO11_0
(PPG10_0)
RTO11_1
(PPG10_1)
RTO12_0
(PPG12_0)
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
RTO13_1
(PPG12_1)
RTO14_0
(PPG14_0)
RTO14_1
(PPG14_1)
RTO15_0
(PPG14_0)
RTO15_1
(PPG14_1)
Document Number: 002-04686 Rev.*C
16-bit input capture ch.1 input pin of Multi-function
timer 1.
ICxx describes channel number
Page 46 of 128
MB9B310T Series
Pin No.
Module
Multifunction Timer
2
Pin name
DTTI2X_0
DTTI2X_1
FRCK2_0
FRCK2_1
Function
Input signal controlling wave form generator
outputs RTO20 to RTO25 of Multi-function timer 2
16-bit free-run timer ch.2 external clock input pin
LQFP-176
LQFP-144
BGA-192
12
12
E4
26
-
H2
128
104
C13
78
-
N10
IC20_0
13
13
E5
IC20_1
25
-
H1
IC21_0
14
14
F1
79
-
L10
IC21_1
IC22_0
16-bit input capture ch.2 input pin of Multi-function
timer 2.
ICxx describes channel number.
15
15
F2
IC22_1
80
-
K10
IC23_0
16
16
F3
IC23_1
81
-
M10
2
2
B2
139
-
C11
3
3
C2
140
-
D11
4
4
C3
141
-
B10
5
5
D5
142
-
C10
6
6
D2
143
-
D10
7
7
D1
144
-
B9
RTO20_0
(PPG20_0)
RTO20_1
(PPG20_1)
RTO21_0
(PPG20_0)
RTO21_1
(PPG20_1)
RTO22_0
(PPG22_0)
RTO22_1
(PPG22_1)
RTO23_0
(PPG22_0)
RTO23_1
(PPG22_1)
RTO24_0
(PPG24_0)
RTO24_1
(PPG24_1)
RTO25_0
(PPG24_0)
RTO25_1
(PPG24_1)
Document Number: 002-04686 Rev.*C
Wave form generator output of Multi-function timer
2.
This pin operates as PPG20 when it is used in
PPG2 output modes.
Wave form generator output of Multi-function timer
2.
This pin operates as PPG20 when it is used in
PPG2 output modes.
Wave form generator output of Multi-function timer
2.
This pin operates as PPG22 when it is used in
PPG2 output modes.
Wave form generator output of Multi-function timer
2.
This pin operates as PPG22 when it is used in
PPG2 output modes.
Wave form generator output of Multi-function timer
2.
This pin operates as PPG24 when it is used in
PPG2 output modes.
Wave form generator output of Multi-function timer
2.
This pin operates as PPG24 when it is used in
PPG2 output modes.
Page 47 of 128
MB9B310T Series
Module
Pin name
Quadrature
Position/
Revolution
Counter
0
AIN0_0
LQFP-144
BGA-192
28
-
H3
59
51
L5
13
13
E5
29
-
H4
60
52
K5
BIN0_2
14
14
F1
ZIN0_0
30
-
H5
N6
AIN0_1
QPRC ch.0 AIN input pin
AIN0_2
BIN0_0
ZIN0_1
QPRC ch.0 BIN input pin
61
53
ZIN0_2
15
15
F2
AIN1_0
73
65
N9
127
103
D13
AIN1_2
62
54
M6
BIN1_0
74
66
M9
126
102
D12
63
55
L6
AIN1_1
BIN1_1
QPRC ch.0 ZIN input pin
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
BIN1_2
ZIN1_0
75
67
L9
125
101
E13
ZIN1_2
64
56
K6
AIN2_0
67
59
M8
ZIN1_1
Quadrature
Position/
Revolution
Counter
2
AIN2_1
QPRC ch.1 ZIN input pin
170
-
B4
AIN2_2
115
-
G11
BIN2_0
68
60
L8
171
-
C4
116
-
G10
BIN2_1
QPRC ch.2 AIN input pin
QPRC ch.2 BIN input pin
BIN2_2
ZIN2_0
69
61
K8
QPRC ch.2 ZIN input pin
172
140
B3
117
-
G9
UDM0
USB ch.0 device/host D – pin
174
142
A3
UDP0
USB ch.0 device/host D + pin
175
143
A2
USB ch.0
USB external pull-up control pin
168
138
B5
UDM1
USB ch.1 device/host D – pin
130
106
D14
UDP1
USB ch.1 device/host D + pin
131
107
C14
USB ch.1
USB external pull-up control pin
127
103
D13
ZIN2_1
ZIN2_2
USB0
UHCONX0
USB1
Pin No.
LQFP-176
BIN0_1
Quadrature
Position/
Revolution
Counter
1
Function
UHCONX1
Document Number: 002-04686 Rev.*C
Page 48 of 128
MB9B310T Series
Pin No.
Module
Reset
Pin name
VCC
VCC
VCC
VCC
External Reset Input Pin.
A reset is valid when INITX="L".
Mode 0 pin.
During normal operation, MD0="L" must be input.
During serial programming to Flash memory,
MD0="H" must be input.
Mode 1 pin.
During serial programming to Flash memory,
MD1="L" must be input.
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
VCC
Power supply Pin
INITX
Mode
MD0
MD1
Power
Function
USBVCC0
LQFP-176
LQFP-144
BGA-192
57
49
N5
85
69
N12
84
68
N13
1
45
54
89
1
37
46
73
C1
N1
P4
M14
133
109
A13
173
141
A4
129
105
E14
3.3V Power supply port for USB I/O
USBVCC1
GND
VCC
Power supply Pin
156
126
A9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
27
44
53
88
109
132
157
176
-
25
36
45
72
93
108
127
144
-
J1
M1
P3
N14
F14
B14
A11
B1
E1
G1
P7
P11
L14
A8
A5
N7
M7
L7
K7
J7
G7
H7
H8
G8
Document Number: 002-04686 Rev.*C
Page 49 of 128
MB9B310T Series
Pin No.
Module
Pin name
Clock
X0
X0A
X1
X1A
CROUT_0
CROUT_1
AVCC
AVRH
Analog
Power
Analog
GND
C pin
AVSS
C
Function
LQFP-176
LQFP-144
BGA-192
A/D converter analog power pin
A/D converter analog reference voltage input pin
86
55
87
56
127
152
106
107
70
47
71
48
103
122
90
91
P12
P5
P13
P6
D13
E8
J14
H14
A/D converter GND pin
108
92
G14
Power stabilization capacity pin
52
44
P2
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
Built-in high-speed CR-osc clock output port
*: 5 V tolerant I/O
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-04686 Rev.*C
Page 50 of 128
MB9B310T Series
5. I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
Pull-up
When the main oscillation is selected.
−
Oscillation feedback resistor
resistor
P-ch
P-ch
: Approximately 1 MΩ
Digital output
X1
−
With Standby mode control
When the GPIO is selected.
−
CMOS level output.
N-ch
Digital output
R
Pull-up resistor control
Digital input
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
: Approximately 50 kΩ
−
IOH= -4 mA, IOL= 4 mA
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
Document Number: 002-04686 Rev.*C
Page 51 of 128
MB9B310T Series
Type
Circuit
Remarks
B
−
CMOS level hysteresis input
−
Pull-up resistor
: Approximately 50 kΩ
Pull-up resistor
Digital input
C
Digital input
N-ch
Document Number: 002-04686 Rev.*C
−
Open drain output
−
CMOS level hysteresis input
Control pin
Page 52 of 128
MB9B310T Series
Type
Circuit
Remarks
D
It is possible to select the sub oscillation
/ GPIO function
Pull-up
When the sub oscillation is selected.
−
Oscillation feedback resistor
resistor
P-ch
P-ch
: Approximately 5 MΩ
Digital output
X1A
−
With Standby mode control
When the GPIO is selected.
−
CMOS level output.
N-ch
Digital output
R
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Pull-up resistor control
Digital input
: Approximately 50 kΩ
−
IOH= -4 mA, IOL= 4 mA
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
Document Number: 002-04686 Rev.*C
Page 53 of 128
MB9B310T Series
Type
Circuit
Remarks
E
P-ch
P-ch
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Digital output
: Approximately 50 kΩ
−
IOH= -4 mA, IOL= 4 mA
−
When this pin is used as an I2C
pin, the digital output P-ch
N-ch
transistor is always off
Digital output
R
−
+B input is available
−
CMOS level output
−
CMOS level hysteresis input
−
With input control
−
Analog input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Pull-up resistor control
Digital input
Standby mode control
F
P-ch
P-ch
Digital output
: Approximately 50 kΩ
N-ch
Digital output
−
IOH= -4 mA, IOL= 4 mA
−
When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
−
R
+B input is available
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
Document Number: 002-04686 Rev.*C
Page 54 of 128
MB9B310T Series
Type
Circuit
Remarks
G
P-ch
P-ch
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Digital output
N-ch
: Approximately 50 kΩ
−
IOH= -12 mA, IOL= 12 mA
−
+B input is available
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
H
GPIO Digital output
It is possible to select the USB I/O / GPIO
function.
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
UDP (+) output
EBP
USB Full-speed/Low-speed control
UDP (+) input
Differential
EBM
Differential input
When the USB I/O is selected.
−
Full-speed, Low-speed control
When the GPIO is selected.
−
CMOS level output
−
CMOS level hysteresis input
−
With standby mode control
−
IOH= -20.5 mA,
IOL= 18.5 mA
USB/GPIO select
UDM (-) input
UDM (-) output
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
Document Number: 002-04686 Rev.*C
Page 55 of 128
MB9B310T Series
Type
Circuit
Remarks
I
P-ch
Digital output
−
CMOS level output
−
CMOS level hysteresis input
−
5 V tolerant
−
With standby mode control
−
IOH= -4 mA, IOL= 4 mA
−
Available to control of PZR
registers.
−
When this pin is used as an I2C
pin, the digital output P-ch
N-ch
transistor is always off
Digital output
R
Digital input
Standby mode control
J
CMOS level hysteresis input
Mode input
Document Number: 002-04686 Rev.*C
Page 56 of 128
MB9B310T Series
Type
Circuit
Remarks
K
P-ch
P-ch
N-ch
−
CMOS level output
−
TTL level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Digital output
: Approximately 50 kΩ
−
IOH= -4 mA, IOL= 4 mA
−
CMOS level output
−
CMOS level hysteresis input
−
With pull-up resistor control
−
With standby mode control
−
Pull-up resistor
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
L
P-ch
P-ch
Digital output
: Approximately 50 kΩ
−
IOH= -8 mA, IOL= 8 mA
−
When this pin is used as an I2C pin,
the digital output P-ch transistor is
N-ch
always off
Digital output
−
R
+B input is available
Pull-up resistor control
Digital input
Standby mode control
Document Number: 002-04686 Rev.*C
Page 57 of 128
MB9B310T Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-04686 Rev.*C
Page 58 of 128
MB9B310T Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations
where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
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Page 59 of 128
MB9B310T Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of
1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use
anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you
use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-04686 Rev.*C
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MB9B310T Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pins
and GND pins, between AVCC pin and AVSS pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device
as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Using an external clock
When using an external clock, the clock signal should be input to the X0, X0A pin only and the X1,X1A pin should be kept open.
Example of Using an External Clock
Device
X0(X0A)
Open
X1(X1A)
2
Handling when using Multi function serial pin as I C pin
2
2
If it is using multi-function serial pin as I C pins, P-ch transistor of digital output is always disable. However, I C pins need to keep
2
the electrical characteristic like other pins and not to connect to external I C bus system with power OFF.
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MB9B310T Series
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between
the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing
capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation
(F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to
use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
Cs
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance
stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC =VCC and AVSS = VSS.
Turning on:
VCC USBVCC0
VCC USBVCC1
VCC AVCC AVRH
Turning off:
AVRH AVCC VCC
USBVCC1 VCC
USBVCC0 VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the
end. If an error is detected, retransmit the data.
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MB9B310T Series
Differences in features among the products with different memory sizes and between Flash products and
MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics
among the products with different memory sizes and between Flash products and MASK products are different because chip
layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Base Timer
In the case of using ch.8 and ch.9 at I/O mode 1 (timer full mode), the TIOA09 pin cannot be used for external startup trigger input
(TGIN).
Be sure to use the pin with making ESG1 and ESG2 bits of the Timer Control Register (Ch.9-TMCR) in the Base Timer to be
"0b00" in order to disable trigger input.
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MB9B310T Series
8. Block Diagram
MB9BF316/317/318
TRSTX,TCK,
TDI,TMS
TDO
TRACED[3:0],
TRACECLK
SWJ-DP
ETM
TPIU
ROM
Table
SRAM0
32/48/64Kbyte
MPU NVIC
Multi-layer AHB (Max 144MHz)
Cortex-M3 Core I
144MHz(Max)
D
Sys
AHB-APB Bridge:
APB0(Max 72MHz)
Dual-Timer
Watchdog Timer
(Software)
Clock Reset
Generator
INITX
Watchdog Timer
(Hardware)
On-chip Flash
512Kbyte/
768Kbyte/
1024Kbyte
Flash I/F
Security
Trace Buffer
(16Kbyte)
SRAM1
32/48/64Kbyte
USBVCC0
USB 2.0
(Host/
Func)
PHY
USB 2.0
(Host/
Func)
PHY
UDP0,UDM0
UHCONX0
USBVCC1
UDP1,UDM1
UHCONX1
CSV
DMAC
8ch.
CLK
X1
X0A
X1A
CROUT
AVCC,
AVSS,AVRH
Main
Osc
Sub
Osc
PLL
Source Clock
CR
4MHz
AHB-AHB
Bridge
(Slave)
X0
CR
100kHz
12-bit A/D Converter
Unit 0
AN[31:00]
Unit 1
ADTG[8:0]
Unit 2
MAD[24:00]
AIN[2:0]
BIN[2:0]
QPRC
3ch.
ZIN[2:0]
A/D Activation
Compare
3ch.
IC0[3:0]
IC1[3:0]
IC2[3:0]
FRCK[2:0]
16-bit Input Capture
4ch.
16-bit Free-run Timer
3ch.
16-bit Output
Compare
6ch.
DTTI[2:0]X
RTO0[5:0]
RTO1[5:0]
RTO2[5:0]
USB Clk Ctrl
AHB-APB Bridge : APB2 (Max 72MHz)
TIOB[15:00]
External Bus I/F
Base Timer
16-bit 16ch./
32-bit 8ch.
AHB-APB Bridge : APB1 (Max 72MHz)
TIOA[15:00]
MADATA[15:00]
PLL
Power On
Reset
LVD Ctrl
IRQ-Monitor
MCSX[7:0],
MOEX,MWEX,
MNALE,
MNCLE,
MNWEX,
MNREX,
MDQM[1:0]
MALE
MRDY
MCLKOUT
LVD
Regulator
C
CRC
Accelerator
Watch Counter
External Interrupt
Controller
32-pin + NMI
Waveform Generator
3ch.
MODE-Ctrl
16-bit PPG
3ch.
GPIO
Multi-function Timer ×3
Multi-Function
Serial I/F 8ch.
(with FIFO ch.4 to ch.7)
HW flow control(ch.4)
INT[31:00]
NMIX
MD[1:0]
PIN-Function-Ctrl
P0x,
P1x,
.
.
.
PFx
SCK[7:0]
SIN[7:0]
SOT[7:0]
CTS4
RTS4
Note:
−
The following items vary depending on the package.
• External bus address
• 12-bit A/D converter channel
Document Number: 002-04686 Rev.*C
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MB9B310T Series
9. Memory Size
See "Memory size" in "1. Product Lineup" to confirm the memory size.
10. Memory Map
Memory Map(1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_1000
0x4006_0000
DMAC
USB ch.1
0x4005_0000
Reserved
USB ch.0
0x4004_0000
0x4003_F000
0x7000_0000
0x6000_0000
0x4200_0000
0x4000_0000
Reserved
External Device
Area
0x4003_B000
Reserved
0x4003_8000
0x4003_7000
32Mbyte
Bit band alias
0x4003_6000
0x4003_5000
0x4400_0000
Peripherals
0x4003_A000
0x4003_9000
0x4003_4000
0x4003_3000
0x4003_2000
Reserved
0x4003_1000
0x4003_0000
32Mbyte
Bit band alias
0x4002_F000
0x4002_E000
Reserved
0x4002_8000
0x2400_0000
0x2200_0000
0x2008_0000
0x2000_0000
0x1FFF_0000
0x0010_2000
See the next page
“●Memory Map (2)” for
the memory size details.
0x0010_0000
SRAM1
SRAM0
Reserved
Security/CR Trim
Watch Counter
CRC
MFS
Reserved
USB Clk Ctrl
LVD Ctrl
Reserved
GPIO
Reserved
Int-Req.Read
EXTI
Reserved
CR Trim
Reserved
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
0x4002_3000
0x4002_2000
0x4002_1000
0x4002_0000
On-chip Flash
EXT-bus I/F
0x4001_6000
0x4001_5000
0x0000_0000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
A/DC
QPRC
Base Timer
PPG
Reserved
MFT unit2
MFT unit1
MFT unit0
Reserved
Dual Timer
Reserved
SW WDT
HW WDT
Clock/Reset
Reserved
0x4000_1000
0x4000_0000
Document Number: 002-04686 Rev.*C
Flash I/F
Page 65 of 128
MB9B310T Series
Memory Map(2)
MB9BF318S/T
MB9BF317S/T
0x2008_0000
MB9BF316S/T
0x2008_0000
0x2008_0000
Reserved
Reserved
0x2001_0000
Reserved
0x2001_C000
SRAM1
64Kbyte
0x2000_8000
SRAM1
48Kbyte
0x2000_0000
SRAM1
32Kbyte
0x2000_0000
0x2000_0000
SRAM0
32Kbyte
SRAM0
48Kbyte
SRAM0
64Kbyte
0x1FFF_8000
0x1FFF_4000
Reserved
0x1FFF_0000
Reserved
Reserved
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
CR trimming
Security
0x0010_1000
0x0010_0000
0x0010_2000
CR trimming
Security
0x0010_1000
0x0010_0000
CR trimming
Security
Reserved
0x000C_0000
Reserved
SA10-19(64KBx10)
0x0000_0000
SA4-7(8KBx4)
0x0008_0000
SA10-15(64KBx6)
SA8-9(48KBx2)
0x0000_0000
SA4-7(8KBx4)
Flash 512Kbyte
SA8-9(48KBx2)
Flash 768Kbyte
Flash 1Mbyte
SA10-23(64KBx14)
SA8-9(48KBx2)
0x0000_0000
SA4-7(8KBx4)
See "MB9BD10T/610T/510T/410T/310T/210T/110T Series Flash programming Manual" for sector structure of Flash.
Document Number: 002-04686 Rev.*C
Page 66 of 128
MB9B310T Series
Peripheral Address Map
Start address
End address
Bus
Peripherals
0x4000_0000
0x4000_0FFF
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function timer unit0
0x4002_1000
0x4002_1FFF
Multi-function timer unit1
0x4002_2000
0x4002_3FFF
Multi-function timer unit2
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
0x4002_6000
0x4002_6FFF
AHB
APB0
APB1
Flash memory I/F register
Reserved
Software Watchdog timer
Reserved
Base Timer
Quadrature Position/Revolution Counter
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Internal CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt Controller
0x4003_1000
0x4003_1FFF
Interrupt Request Batch-Read Function
0x4003_2000
0x4003_2FFF
Reserved
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_5FFF
Low-Voltage Detector
0x4003_6000
0x4003_6FFF
0x4003_7000
0x4003_7FFF
Reserved
0x4003_8000
0x4003_8FFF
Multi-function serial Interface
APB2
USB clock generator
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_EFFF
Reserved
0x4003_F000
0x4003_FFFF
External Memory interface
0x4004_0000
0x4004_FFFF
USB ch.0
0x4005_0000
0x4005_FFFF
0x4006_0000
0x4006_0FFF
0x4006_1000
0x41FF_FFFF
Document Number: 002-04686 Rev.*C
AHB
USB ch.1
DMAC register
Reserved
Page 67 of 128
MB9B310T Series
11. Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the "L" level.
INITX=1
This is the period when the INITX pin is the "H" level.
SPL=0
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "0".
SPL=1
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
Document Number: 002-04686 Rev.*C
Page 68 of 128
MB9B310T Series
List of Pin Status
Pin
status
type
Function group
Power-on
reset or low
voltage
detection
state
INITX input
state
Device
internal
reset state
Run mode
or sleep
mode state
Timer mode or sleep mode
state
-
INITX=0
-
INITX=1
-
Power
supply
stable
INITX=1
-
GPIO selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Main crystal
oscillator input pin
GPIO selected
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Main crystal
oscillator output pin
Hi-Z/
Internal input
fixed at "0"/
or Input enable
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state
INITX input pin
Pull-up/
Input
enabled
Input enabled
Hi-Z
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Maintain
previous state/
Hi-Z at
oscillation
stop*1
Internal input
fixed at "0"
Pull-up/ Input
enabled
Maintain
previous state/
Hi-Z at
oscillation
stop*1
Internal input
fixed at "0"
Pull-up/ Input
enabled
Input enabled
Pull-up/ Input
enabled
Setting
disabled
Input enabled
Pull-up/ Input
enabled
Setting
disabled
Input enabled
Maintain
previous state
Input enabled
Maintain
previous state
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Input enabled
Maintain
previous state
Hi-Z/ Internal
input fixed at
"0"
Trace output
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Power supply
unstable
Power supply stable
Power supply stable
INITX=1
SPL=0
SPL=1
Hi-Z/ Internal
input fixed at
"0"
Input enabled
A
B
C
D
E
F
Mode input pin
JTAG
selected
GPIO
selected
Trace selected
External interrupt
enabled selected
GPIO
selected, or other
than above resource
selected
Setting disabled
Document Number: 002-04686 Rev.*C
Page 69 of 128
MB9B310T Series
Pin
status
type
G
H
I
J
Function
group
Power-on
reset or low
voltage
detection
state
Power supply
unstable
INITX input
state
Device
internal
reset state
Power supply stable
Run mode or
sleep mode
state
Timer mode or sleep mode
state
Power
supply
stable
INITX=1
-
SPL=0
SPL=1
Maintain
previous state
Trace output
Power supply stable
-
INITX=0
-
INITX=1
-
Trace selected
Setting disabled
Hi-Z
Setting
disabled
Hi-Z/
Input enabled
Maintain
previous state
GPIO selected, or
other than above
resource selected
External interrupt
enabled selected
GPIO selected, or
other than above
resource selected
GPIO selected,
resource selected
Setting
disabled
Hi-Z/
Input enabled
Setting
disabled
Hi-Z/
Input enabled
Setting
disabled
Hi-Z/
Input enabled
Maintain
previous state
Maintain
previous state
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Maintain
previous state
Maintain
previous state
NMIX selected
Setting disabled
Maintain
previous state
Hi-Z
Setting
disabled
Hi-Z/
Input enabled
Maintain
previous state
GPIO selected, or
other than above
resource selected
Setting
disabled
Hi-Z/
Input enabled
Setting disabled
Hi-Z
Document Number: 002-04686 Rev.*C
INITX=1
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Hi-Z/ Internal
input fixed at
"0"
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Page 70 of 128
MB9B310T Series
Pin
status
type
Function
group
Power-on
reset or low
voltage
detection
state
INITX input
state
Device
internal
reset state
Run mode or
sleep mode
state
Timer mode or sleep mode
state
-
INITX=0
-
INITX=1
-
Power
supply
stable
INITX=1
-
Analog input
selected
Hi-Z
GPIO selected, or
other than above
resource selected
External interrupt
enabled selected
Analog input
selected
Setting disabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Setting
disabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Setting
disabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Maintain
previous state
GPIO selected, or
other than above
resource selected
GPIO selected
Setting disabled
Setting
disabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Setting
disabled
Setting
disabled
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Setting
disabled
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Maintain
previous state
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Sub crystal
oscillator input pin
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Power supply
unstable
K
Setting disabled
Hi-Z
L
Power supply stable
Power supply stable
INITX=1
SPL=0
SPL=1
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"/
Analog input
enabled
Hi-Z/
Internal input
fixed at "0"
Hi-Z/ Internal
input fixed at
"0"
M
Document Number: 002-04686 Rev.*C
Input enabled
Page 71 of 128
MB9B310T Series
Pin
status
type
N
Function
group
Power-on
reset or low
voltage
detection
state
Power supply
unstable
INITX input
state
Device
internal
reset state
Power supply stable
-
INITX=0
-
INITX=1
-
GPIO selected
Setting disabled
Setting
disabled
Setting
disabled
Sub crystal
oscillator output
pin
Hi-Z/
Internal input
fixed at "0"/
or Input enable
Hi-Z/
Internal input
fixed at "0"
GPIO selected
Hi-Z
USB I/O pin
Setting disabled
Mode input pin
Power supply stable
INITX=1
SPL=1
Maintain
previous
state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Internal input
fixed at "0"
Maintain
previous
state
Maintain
previous state/
Hi-Z at
oscillation stop*2/
Internal input
fixed at "0"
Maintain
previous state/
Hi-Z at
oscillation stop*2/
Internal input
fixed at "0"
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Maintain
previous
state
Maintain
previous state
Hi-Z/ Internal
input fixed at "0"
Setting
disabled
Setting
disabled
Maintain
previous
state
Hi-Z at
transmission/
Input enabled/
Internal input
fixed at "0" at
reception
Hi-Z at
transmission/
Input enabled/
Internal input
fixed at "0" at
reception
Input
enabled
Input enabled
Input enabled
Input
enabled
Input
enabled
Input
enabled
GPIO selected
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z/
Input enabled
GPIO selected,
resource selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Maintain
previous
state
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"
External interrupt
enabled selected
Setting disabled
Setting
disabled
Setting
disabled
GPIO selected, or
other than above
resource selected
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
P
R
Power
supply
stable
INITX=1
-
Timer mode or sleep mode
state
SPL=0
O
Q
Run mode
or sleep
mode
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"
*1: Oscillation is stopped at Sub timer mode, Low speed CR timer mode, and STOP mode.
*2: Oscillation is stopped at STOP mode.
Document Number: 002-04686 Rev.*C
Page 72 of 128
MB9B310T Series
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Symbol
1, 2
Power supply voltage* *
Power supply voltage (for USB ch.0)*1,*3
Power supply voltage (for USB ch.1)*1,*3
Analog power supply voltage*1,*4
Analog reference voltage*1,*4
Rating
Max
Vcc
USBVcc0
Vss - 0.5
Vss - 0.5
Vss + 6.5
Vss + 6.5
V
V
USBVcc1
AVcc
AVRH
Vss - 0.5
Vss - 0.5
Vss - 0.5
Vss + 6.5
Vss + 6.5
Vss + 6.5
Vcc + 0.5
(≤ 6.5 V)
USBVcc0 + 0.5
V
V
V
Vss - 0.5
Input voltage*1
VI
Vss - 0.5
Vss - 0.5
Vss - 0.5
Analog pin input voltage*
1
Output voltage*1
Clamp maximum current
Clamp total maximum current
"L" level maximum output current*5
VIA
Vss - 0.5
VO
Vss - 0.5
ICLAMP
Σ[ICLAMP]
-2
IOL
IOLAV
-
"L" level total maximum output current
∑IOL
∑IOLAV
-
"H" level maximum output current*
5
IOH
-
"H" level average output current*6
IOHAV
-
"H" level total maximum output current
∑IOH
∑IOHAV
PD
TSTG
- 55
"H" level total average output current*7
Power consumption
Storage temperature
Remarks
V
Except for USB pin
V
USB ch.0 pin
(≤ 6.5 V)
V
USB ch.1 pin
Vss + 6.5
AVcc + 0.5
V
5 V tolerant
(≤ 6.5 V)
USBVcc1 + 0.5
(≤ 6.5 V)
Vcc + 0.5
V
(≤ 6.5 V)
V
-
"L" level average output current*6
"L" level total average output current*7
Unit
Min
+2
mA
*8
+20
mA
*8
10
mA
4 mA type
20
mA
8 mA type
20
39
4
8
12
18.5
100
50
mA
mA
mA
mA
mA
mA
mA
mA
12 mA type
P80,P81,P82,P83
4 mA type
8 mA type
12 mA type
P80,P81,P82,P83
- 10
mA
4 mA type
- 20
- 20
- 39
-4
-8
- 12
- 20.5
- 100
- 50
1000
+ 150
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
8 mA type
12 mA type
P80,P81,P82,P83
4 mA type
8 mA type
12 mA type
P80,P81,P82,P83
°C
*1: These parameters are based on the condition that Vss = AVss = 0.0 V.
*2: Vcc must not drop below Vss - 0.5 V.
*3: USBVcc0 and USBVcc1 must not drop below Vss - 0.5 V.
*4: Ensure that the voltage does not to exceed Vcc + 0.5 V, for example, when the power is turned on.
*5: The maximum output current is the peak value for a single pin.
*6: The average output is the average current for a single pin over a period of 100 ms.
*7: The total average output current is the average current for all pins over a period of 100 ms.
Document Number: 002-04686 Rev.*C
Page 73 of 128
MB9B310T Series
*8:
•
•
•
•
•
See "4. List of Pin Functions" and "5. I/O Circuit Type" about +B input available pin.
Use within recommended operating conditions.
Use at DC voltage (current) the +B input.
The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does
not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass
through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.
• Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the
pins, so that incomplete operation may result.
• The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
P-ch
Limiting
+B input (0V to 16V)
Digital output
N-ch
Digital input
R
AVCC
Analog input
WARNING:
−
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-04686 Rev.*C
Page 74 of 128
MB9B310T Series
12.2 Recommended Operating Conditions
(Vss = AVss = 0.0V)
Parameter
Power supply voltage
Power supply voltage
(3V power supply) for
USB ch.0
Power supply voltage
(3V power supply) for
USB ch.1
Analog power supply voltage
Analog reference voltage
Smoothing capacitor
LQS144,
Operating
LQP176,
temperature
LBE192
Symbol
Conditions
Vcc
-
Value
Min
6
2.7 *
3.0
USBVcc0
USBVcc1
AVcc
AVRH
CS
TA
-
5.5
Unit
(≤ Vcc)
5.5
(≤ Vcc)
3.0
(≤ Vcc)
*1
V
*2
3.6
5.5
Remarks
V
3.6
2.7
When mounted
on four-layer
PCB
Max
*3
V
2.7
(≤ Vcc)
*4
2.7
2.7
1
5.5
AVcc
10
V
V
μF
- 40
+ 85
°C
AVcc = Vcc
5
for built-in regulator *
*1: When P81/UDP0 and P80/UDM0 pin are used as USB (UDP0, UDM0).
*2: When P81/UDP0 and P80/UDM0 pin are used as GPIO (P81, P80).
*3: When P83/UDP1 and P82/UDM1 pin are used as USB (UDP1, UDM1).
*4: When P83/UDP1 and P82/UDM1 pin are used as GPIO (P83, P82).
*5: See "C pin" in "7. Handling Devices" for the connection of the smoothing capacitor.
*6: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction
execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is
possible to operate only.
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or
combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to
contact their representatives beforehand.
Document Number: 002-04686 Rev.*C
Page 75 of 128
MB9B310T Series
12.3 DC Characteristics
12.3.1 Current Rating
(Vcc = AVcc = USBVcc0 = USBVcc1 = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Conditions
PLL
RUN mode
RUN
mode
current
Icc
High-speed
CR
RUN mode
VCC
Sub
RUN mode
Low-speed
CR
RUN mode
SLEEP
mode
current
Iccs
PLL
SLEEP mode
High-speed
CR
SLEEP mode
Sub
SLEEP mode
Low-speed
CR
SLEEP mode
CPU: 144 MHz,
Peripheral: 72 MHz,
Flash 2 Wait,
TraceBuffer: ON,
FRWTR.RWT = 10,
FSYNDN.SD = 000,
FBFCR.BE = 1
CPU: 72 MHz,
Peripheral: 72 MHz,
Flash 0 Wait,
TraceBuffer: OFF,
FRWTR.RWT = 00,
FSYNDN.SD = 000,
FBFCR.BE = 0
Value
4
Max*
3
Typ*
Unit
Remarks
100
180
mA
*1, *5
65
135
mA
*1, *5
6
57.8
mA
*1
1.3
51.7
mA
*1, *6
1.3
51.7
mA
*1
Peripheral: 72 MHz
30
89
mA
*1, *5
Peripheral: 4 MHz*2
4.5
55.9
mA
*1
Peripheral: 32 kHz
1.2
51.6
mA
*1, *6
Peripheral: 100 kHz
1.2
51.6
mA
*1
CPU/ Peripheral: 4 MHz*2,
Flash 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
CPU/ Peripheral: 32 kHz,
Flash 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
CPU/ Peripheral: 100 kHz,
Flash 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA = +25°C, VCC = 5.5 V
*4: TA = +85°C, VCC = 5.5 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-04686 Rev.*C
Page 76 of 128
MB9B310T Series
(Vcc = AVcc = USBVcc0 = USBVcc1 = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 85°C)
Parameter
TIMER
mode
current
Pin
name
Symbol
Conditions
Main
TIMER
mode
ICCT
Sub
TIMER
mode
VCC
STOP
mode
current
ICCH
STOP mode
Value
2
Max*
2
Typ*
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
Unit
Remarks
4
10
mA
*1, *3
-
55
mA
*1, *3
1.1
5
mA
*1, *4
-
50
mA
*1, *4
1
5
mA
*1
-
50
mA
*1
*1: When all ports are fixed.
*2: VCC = 5.5 V
*3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Conditions
Low-voltage detection
circuit (LVD) power
supply current
ICCLVD
VCC
At operation
for interrupt
Value
Typ
Max
4
7
Unit
μA
Remarks
At not detect
Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Conditions
Value
Typ
Max
Flash memory
write/erase
current
ICCFLASH
VCC
At Write/Erase
12
14
Unit
Remarks
mA
A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 85°C)
Parameter
Power supply current
Reference power
supply current
Symbol
Pin
name
ICCAD
AVCC
ICCAVRH
Document Number: 002-04686 Rev.*C
AVRH
Conditions
Value
Unit
Typ
Max
At 1unit operation
0.57
0.72
mA
At stop
0.06
35
μA
At 1unit operation
AVRH=5.5 V
1.1
1.96
mA
At stop
0.06
4
μA
Remarks
Page 77 of 128
MB9B310T Series
12.3.2 Pin Characteristics
(Vcc = USBVcc0 = USBVcc1 = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 85°C)
Parameter
"H" level input
voltage
(hysteresis
input)
"L" level input
voltage
(hysteresis
input)
Symbol
VIHS
VILS
Pin name
Conditions
CMOS
hysteresis
input pin,
MD0, MD1
5 V tolerant
input pin
TTL Schmitt
input pin
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
TTL Schmitt
input pin
Min
Value
Typ
Max
Unit
-
Vcc × 0.8
-
Vcc + 0.3
V
-
Vcc × 0.8
-
Vss + 5.5
V
-
2.0
-
Vcc + 0.3
V
-
Vss - 0.3
-
Vcc × 0.2
V
-
Vss - 0.3
-
Vcc × 0.2
V
-
Vss - 0.3
-
0.8
V
Vcc - 0.5
-
Vcc
V
Vcc - 0.5
-
Vcc
V
Vcc - 0.5
-
Vcc
V
USBVcc 0.4
-
USBVcc
V
Remarks
Vcc ≥ 4.5 V,
4 mA type
IOH = - 4 mA
Vcc
< 4.5 V,
IOH = - 2 mA
Vcc ≥ 4.5 V,
8 mA type
"H" level
output voltage
IOH = - 8 mA
Vcc < 4.5 V,
IOH = - 4 mA
VOH
Vcc ≥ 4.5 V,
12 mA type
IOH = - 12 mA
Vcc < 4.5 V,
IOH = - 8 mA
USBVcc ≥ 4.5 V,
P80, P81,
P82, P83
IOH = - 20.5 mA
USBVcc < 4.5 V,
*
IOH = - 13.0 mA
Document Number: 002-04686 Rev.*C
Page 78 of 128
MB9B310T Series
Value
Parameter
Symbol
Pin name
Conditions
Vcc ≥ 4.5 V,
IOL = 4 mA
4 mA type
8 mA type
"L" level
output voltage
VOL
12 mA type
P80, P81,
P82, P83
Input leak current
Pull-up resistance
value
Input capacitance
IIL
RPU
CIN
-
Vcc < 4.5 V,
IOL = 2 mA
Vcc ≥ 4.5 V,
IOL = 8 mA
Vcc < 4.5 V,
IOL = 4 mA
Vcc ≥ 4.5 V,
IOL = 12 mA
Vcc < 4.5 V,
IOL = 8 mA
USBVcc ≥ 4.5 V,
IOL = 18.5 mA
USBVcc < 4.5 V,
IOL = 10.5 mA
-
Pull-up pin
Other than
VCC,
USBVCC0,
USBVCC1,
VSS,
AVCC,
AVSS, AVRH
Unit
Min
Typ
Max
Vss
-
0.4
V
Vss
-
0.4
V
Vss
-
0.4
V
Vss
-
0.4
V
μA
-5
-
+5
Vcc ≥ 4.5 V
25
50
100
Vcc < 4.5 V
30
80
200
-
-
5
15
Remarks
*
kΩ
pF
*: USBVcc0 and USBVcc1 are described as USBVcc.
Document Number: 002-04686 Rev.*C
Page 79 of 128
MB9B310T Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Input frequency
Input clock cycle
Input clock pulse width
Input clock rise time and
fall time
Internal operating
clock*1 frequency
Internal operating
1
clock* cycle time
Symbol
Pin
name
FCH
tCYLH
X0,
X1
-
Conditions
Value
Unit
Min
Max
4
50
4
20
4
50
4
20
20
250
50
250
45
55
%
-
-
5
ns
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
PWH/tCYLH,
PWL/tCYLH
Remarks
MHz
When crystal oscillator is
connected
MHz
When using external
clock
ns
When using external
clock
When using external
clock
When using external
clock
tCF,
tCR
FCM
-
-
-
144
MHz
Master clock
FCC
-
-
-
144
MHz
Base clock (HCLK/FCLK)
FCP0
FCP1
FCP2
-
-
-
72
MHz
-
-
-
72
MHz
-
-
-
72
MHz
APB0 bus clock*
2
APB1 bus clock*
2
APB2 bus clock*
tCYCC
tCYCP0
tCYCP1
tCYCP2
-
-
6.94
-
ns
Base clock (HCLK/FCLK)
-
-
13.8
-
ns
-
-
13.8
-
ns
-
-
13.8
-
ns
APB0 bus clock*
2
APB1 bus clock*
2
APB2 bus clock*
2
2
*1: For more information about each internal operating clock, see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
*2: For about each APB bus which each peripheral is connected to, see "8. Block Diagram" in this data sheet.
X0
Document Number: 002-04686 Rev.*C
Page 80 of 128
MB9B310T Series
12.4.2 Sub Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Input frequency
1/tCYLL
Input clock cycle
tCYLL
Input clock pulse width
Pin
name
Value
Conditions
Remarks
Typ
Max
-
-
32.768
-
kHz
-
32
-
100
kHz
When crystal oscillator is
connected
When using external clock
-
10
-
31.25
μs
When using external clock
PWH/tCYLL,
PWL/tCYLL
45
-
55
%
When using external clock
X0A,
X1A
-
Unit
Min
X0A
12.4.3 Internal CR Oscillation Characteristics
High-speed Internal CR
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Value
Min
Typ
Max
TA = + 25°C
3.96
4
4.04
TA =0°C to + 70°C
3.84
4
4.16
TA =- 40°C to + 85°C
3.8
4
4.2
TA =- 40°C to + 85°C
3
4
5
-
-
-
90
Unit
Remarks
*1
FCRH
Clock frequency
tCRWT
Frequency stability time
When trimming
MHz
When not trimming
μs
*2
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2: Frequency stable time is time to stable of the frequency of the High-speed CR.
Clock after the trim value is set. After setting the trim value, the period when the frequency stability
Time passes can use the High-speed CR clock as a source clock.
Low-speed Internal CR
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Clock frequency
Symbol
Conditions
FCRL
-
Document Number: 002-04686 Rev.*C
Value
Min
Typ
Max
50
100
150
Unit
Remarks
kHz
Page 81 of 128
MB9B310T Series
12.4.4 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Value
Symbol
PLL oscillation stabilization wait time
(LOCK UP time)
Unit
Min
Typ
Max
tLOCK
100
-
-
μs
FPLLI
4
13
200
-
-
16
75
300
144
48
MHz
multiple
MHz
MHz
MHz
Remarks
*1
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
-
FPLLO
FCLKPLL
FCLKSPLL
2
Main PLL clock frequency*
3
USB clock frequency*
After the M frequency division
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
*3: For more information about USB clock, see "Chapter 2-2: USB clock Generation" in "FM3 Family Peripheral Manual
Communication Macro Part".
12.4.5 Operating Conditions of Main PLL (In the case of using high-speed internal CR)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Value
Symbol
PLL oscillation stabilization wait time
(LOCK UP time)
Unit
Min
Typ
Max
tLOCK
100
-
-
μs
FPLLI
3.8
50
190
-
4
-
4.2
71
300
144
MHz
multiple
MHz
MHz
Remarks
*1
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
-
FPLLO
FCLKPLL
2
Main PLL clock frequency*
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
Note:
−
Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency has been trimmed.
Main PLL connection
Main clock (CLKMO)
High-speed CR clock (CLKHC)
K
divider
PLL input
clock
PLL macro
oscillation clock
Main
PLL
M
divider
Main PLL
clock
(CLKPLL)
N
divider
USB PLL connection
Main clock (CLKMO)
PLL input
clock
K
divider
USB
PLL
PLL macro
oscillation clock
M
divider
USB
clock
N
divider
Document Number: 002-04686 Rev.*C
Page 82 of 128
MB9B310T Series
12.4.6 Reset Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
tINITX
INITX
-
Reset input time
Value
Min
Max
500
-
Unit
Remarks
ns
12.4.7 Power-on Reset Timing
(Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Power supply shut down time
tOFF
Power ramp rate
dV/dt
Time until releasing Power-on reset
tPRT
Pin name
VCC
Value
Conditions
Unit
Remarks
Min
Typ
Max
-
50
-
-
ms
*1
Vcc:0.2 V to 2.70 V
0.9
-
1000
mV/μs
*2
-
0.46
-
0.76
ms
*1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>50ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 6.
2.7V
VCC
VDH
0.2V
dV/dt
0.2V
tPRT
Internal RST
CPU Operation
RST Active
0.2V
tOFF
release
start
Glossary
VDH: detection voltage of Low Voltage detection reset. See “12.7 Low-Voltage Detection Characteristics”
Document Number: 002-04686 Rev.*C
Page 83 of 128
MB9B310T Series
12.4.8 External Bus Timing
External bus clock output characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Output frequency
Symbol
Pin name
Conditions
tCYCLE
MCLKOUT*
1
Value
Min
Max
Vcc ≥ 4.5 V
-
Vcc < 4.5 V
-
50*
3
32*
2
Unit
MHz
MHz
*1: External bus clock (MCLKOUT) is divided clock of HCLK.
For more information about setting of clock divider, see "Chapter 12: External Bus Interface" in "FM3 Family Peripheral Manual".
When external bus clock is not output, this characteristic does not give any effect on external bus operation.
*2: When AHB bus clock frequency is more than 100MHz, the divider setting for MCLKOUT must be more than 4.
*3: When AHB bus clock frequency is more than 64MHz, the divider setting for MCLKOUT must be more than 4.
MCLKOUT
External bus signal input/output characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Value
Unit
0.8 × VCC
V
0.2 × VCC
V
VOH
0.8 × VCC
V
VOL
0.2 × VCC
V
VIH
Remarks
Signal input characteristics
VIL
Signal output characteristics
Input signal
VIH
VIL
VIH
VIL
Output signal
VOH
VOL
VOH
VOL
Document Number: 002-04686 Rev.*C
Page 84 of 128
MB9B310T Series
Separate Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
tOEW
MOEX
MCSX ↓ → Address
output delay time
tCSL – AV
MCSX[7:0],
MAD[24:0]
MOEX ↑ →
Address hold time
tOEH - AX
MOEX,
MAD[24:0]
MCSX ↓ →
MOEX ↓ delay time
tCSL - OEL
MOEX ↑ →
MCSX ↑ time
tOEH - CSH
MOEX
Min pulse width
MCSX ↓ →
MDQM ↓ delay time
MOEX,
MCSX[7:0]
tCSL - RDQML
MCSX,
MDQM[1:0]
Data set up →
MOEX ↑ time
tDS - OE
MOEX,
MADATA[15:0]
MOEX ↑ →
Data hold time
tDH - OE
MOEX,
MADATA[15:0]
MWEX
Min pulse width
tWEW
MWEX
MWEX ↑ → Address
output delay time
tWEH - AX
MWEX,
MAD[24:0]
MCSX ↓ →
MWEX ↓ delay time
tCSL - WEL
MWEX ↑ →
MCSX ↑ delay time
tWEH - CSH
MCSX ↓ →
MDQM ↓ delay time
tCSL-WDQML
MCSX,
MDQM[1:0]
MCSX ↓ →
Data output time
tCSL - DV
MCSX,
MADATA[15:0]
MWEX ↑ →
Data hold time
tWEH - DX
MWEX,
MADATA[15:0]
MWEX,
MCSX[7:0]
Conditions
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Value
Unit
Min
Max
MCLK×n-3
-
-9
-12
MCLK×m-9
MCLK×m-12
20
38
+9
+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
0
-
ns
MCLK×n-3
-
ns
0
MCLK×m-9
MCLK×m-12
0
0
MCLK×n-9
MCLK×n-12
0
MCLK×n-9
MCLK×n-12
MCLK-9
MCLK-12
0
ns
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MCLK+12
MCLK×m+9
MCLK×m+12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
−
When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
Document Number: 002-04686 Rev.*C
Page 85 of 128
MB9B310T Series
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
MCSX[7:0]
tCSL-AV
MAD[24:0]
tOEH-AX
Address
tWEH-AX
tCSL-AV
Address
tCSL-OEL
MOEX
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
tCSL-WEL
tWEW
MWEX
MADATA[15:0]
tDS-OE
tDH-OE
RD
tWEH-DX
WD
Invalid
tCSL-DV
Document Number: 002-04686 Rev.*C
Page 86 of 128
MB9B310T Series
Separate Bus Access Synchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
tAV
MCLK,
MAD[24:0]
Address delay time
tCSL
tCSH
tREL
MCLK,
MOEX
MOEX delay time
tREH
Data set up →
MCLK ↑ time
tDS
MCLK,
MADATA[15:0]
MCLK ↑ →
Data hold time
tDH
MCLK,
MADATA[15:0]
tWEL
MCLK,
MWEX
MWEX delay time
tWEH
MDQM[1:0]
delay time
tDQML
MCLK,
MDQM[1:0]
tDQMH
MCLK ↑ →
Data output time
tOD
MCLK,
MADATA[15:0]
MCLK ↑ →
Data hold time
tOD
MCLK,
MADATA[15:0]
Min
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
MCLK,
MCSX[7:0]
MCSX delay time
Value
Conditions
Unit
Max
9
1
ns
12
9
1
ns
12
9
1
ns
12
9
1
ns
12
9
1
ns
12
19
37
0
-
ns
-
ns
9
1
ns
12
9
1
ns
12
9
1
ns
12
9
1
ns
12
MCLK+18
MCLK+1
MCLK+24
18
1
24
ns
ns
Note:
−
When the external load capacitance = 30 pF.
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
tAV
tAV
Address
MAD[24:0]
Address
tREL
tREH
tDQML
tDQMH
MOEX
tDQML
tDQMH
tWEL
tWEH
MDQM[1:0]
MWEX
MADATA[15:0]
tDS
tDH
RD
tOD
WD
Invalid
tODS
Document Number: 002-04686 Rev.*C
Page 87 of 128
MB9B310T Series
Multiplexed Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Multiplexed
address delay time
tALE-CHMADV
Multiplexed
address hold time
tCHMADH
Pin name
Conditions
MALE,
MADATA[15:0]
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Value
Min
0
Max
10
Unit
ns
20
MCLK×n+0
MCLK×n+10
MCLK×n+0
MCLK×n+20
ns
Note:
−
When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-04686 Rev.*C
Page 88 of 128
MB9B310T Series
Multiplexed Bus Access Synchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
MCLK,
ALE
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
tCHAL
MALE delay time
tCHAH
MCLK ↑ →
Multiplexed
Address delay time
tCHMADV
MCLK ↑ →
Multiplexed
Data output time
tCHMADX
Vcc ≥ 4.5 V
MCLK,
MADATA[15:0]
Value
Min
Max
Unit
9
12
9
12
ns
ns
ns
ns
1
tOD
ns
1
tOD
ns
1
1
Remarks
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Note:
−
When the external load capacitance = 30 pF.
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-04686 Rev.*C
Page 89 of 128
MB9B310T Series
NAND Flash Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
tNREW
MNREX
tDS – NRE
MNREX,
MADATA[15:0]
tDH – NRE
MNREX,
MADATA[15:0]
tALEH - NWEL
MNALE,
MNWEX
tALEL - NWEL
MNALE,
MNWEX
tCLEH - NWEL
MNCLE,
MNWEX
tNWEH - CLEL
MNCLE,
MNWEX
tNWEW
MNWEX
tNWEL – DV
MNWEX,
MADATA[15:0]
tNWEH – DX
MNWEX,
MADATA[15:0]
MNREX
Min pulse width
Data setup →
MNREX↑time
MNREX↑→
Data hold time
MNALE↑→
MNWEX delay time
MNALE↓→
MNWEX delay time
MNCLE↑→
MNWEX delay time
MNWEX↑→
MNCLE delay time
MNWEX
Min pulse width
MNWEX↓→
Data output time
MNWEX↑→
Data hold time
Conditions
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Value
Unit
Min
Max
MCLK×n-3
-
ns
20
38
-
ns
0
-
ns
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
0
MCLK×n-3
-
-9
-12
+9
+12
MCLK×m+9
MCLK×m+12
0
ns
ns
ns
ns
ns
ns
ns
Note:
−
When the external load capacitance = 30 pF. (m=0 to 15, n=1 to 16)
NAND Flash Read
MCLK
MNREX
MADATA[15:0]
Read
Document Number: 002-04686 Rev.*C
Page 90 of 128
MB9B310T Series
NAND Flash Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
NAND Flash Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
Document Number: 002-04686 Rev.*C
Page 91 of 128
MB9B310T Series
External Ready Input Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
MCLK ↑
MRDY input
setup time
Value
Symbol
Pin name
Conditions
tRDYI
MCLK,
MRDY
Vcc ≥ 4.5 V
19
Vcc < 4.5 V
37
Min
Unit
Max
-
Remarks
ns
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
MCLK
··· ···
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
Document Number: 002-04686 Rev.*C
Page 92 of 128
MB9B310T Series
12.4.9 Base Timer Input Timing
Timer input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTIWH,
tTIWL
TIOAn/TIOBn
(when using as ECK,
TIN)
-
tTIWH
Value
Min
Max
2tCYCP
-
Unit
Remarks
ns
tTIWL
ECK
VIHS
TIN
VIHS
VILS
VILS
Trigger input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
tTRGH,
tTRGL
TIOAn/TIOBn
(when using as
TGIN)
-
Input pulse width
tTRGH
TGIN
VIHS
Value
Min
Max
2tCYCP
-
Unit
Remarks
ns
tTRGL
VIHS
VILS
VILS
Notes:
−
tCYCP indicates the APB bus clock cycle time.
−
About the APB bus number which Base Timer is connected to, see "8. Block Diagram" in this data sheet.
Document Number: 002-04686 Rev.*C
Page 93 of 128
MB9B310T Series
12.4.10 CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Baud rate
-
-
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK fall time
SCK rise time
Pin
name
Symbol
tF
tR
Unit
Min
Max
Min
Max
-
8
-
8
Mbps
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Vcc ≥ 4.5 V
Vcc < 4.5 V
Conditions
Master mode
Slave mode
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram" in this data sheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance = 30 pF.
Document Number: 002-04686 Rev.*C
Page 94 of 128
MB9B310T Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
VIH
VIL
SIN
tSHIXI
VIH
VIL
Master mode
tSLSH
SCK
VIH
tF
VIL
tSHSL
VIH
VIL
tR
tSLOVE
SOT
SIN
VIH
VOH
VOL
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
Document Number: 002-04686 Rev.*C
Page 95 of 128
MB9B310T Series
CSIO (SPI = 0, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Pin
name
Symbol
Vcc ≥ 4.5 V
Vcc < 4.5 V
Conditions
Min
Max
Min
Max
Unit
-
8
-
8
Mbps
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK ↑ → SOT delay time
tSHOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN → SCK ↓ setup time
tIVSLI
50
-
30
-
ns
SCK ↓ → SIN hold time
tSLIXI
0
-
0
-
ns
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
SCK ↑ → SOT delay time
tSHOVE
-
50
-
30
ns
SIN → SCK ↓ setup time
tIVSLE
10
-
10
-
ns
SCK ↓ → SIN hold time
tSLIXE
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Baud rate
Serial clock cycle time
SCK fall time
SCK rise time
-
-
tF
tR
-
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Master mode
Slave mode
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram" in this data sheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance = 30 pF.
Document Number: 002-04686 Rev.*C
Page 96 of 128
MB9B310T Series
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
Master mode
tSHSL
SCK
tSLSH
VIH
VIH
VIL
tR
VIL
tF
tSHOVE
SOT
SIN
VIL
VOH
VOL
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
Document Number: 002-04686 Rev.*C
Page 97 of 128
MB9B310T Series
CSIO (SPI = 1, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Pin
name
Symbol
Vcc ≥ 4.5 V
Vcc < 4.5 V
Conditions
Min
Max
Min
Max
Unit
-
8
-
8
Mbps
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK ↑ → SOT delay time
tSHOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN → SCK ↓ setup time
tIVSLI
50
-
30
-
ns
SCK ↓ → SIN hold time
tSLIXI
0
-
0
-
ns
SOT → SCK ↓ delay time
tSOVLI
2tCYCP - 30
-
2tCYCP - 30
-
ns
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
SCK ↑ → SOT delay time
tSHOVE
-
50
-
30
ns
SIN → SCK ↓ setup time
tIVSLE
10
-
10
-
ns
SCK ↓ → SIN hold time
tSLIXE
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Baud rate
Serial clock cycle time
SCK fall time
SCK rise time
-
-
tF
tR
-
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Master mode
Slave mode
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram" in this data sheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance = 30 pF.
Document Number: 002-04686 Rev.*C
Page 98 of 128
MB9B310T Series
tSCYC
VOH
VOL
SCK
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
Master mode
tSLSH
SCK
VIH
VIH
VIL
tF
*
SOT
VIL
tSHSL
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-04686 Rev.*C
Page 99 of 128
MB9B310T Series
CSIO (SPI = 1, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Pin
name
Symbol
Vcc ≥ 4.5 V
Vcc < 4.5 V
Conditions
Min
Max
Min
Max
Unit
-
8
-
8
Mbps
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK ↓ → SOT delay time
tSLOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN → SCK ↑ setup time
tIVSHI
50
-
30
-
ns
SCK ↑ → SIN hold time
tSHIXI
0
-
0
-
ns
SOT → SCK ↑ delay time
tSOVHI
2tCYCP - 30
-
2tCYCP - 30
-
ns
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
2tCYCP - 10
tCYCP + 10
-
ns
ns
SCK ↓ → SOT delay time
tSLOVE
-
50
-
30
ns
SIN → SCK ↑ setup time
tIVSHE
10
-
10
-
ns
SCK ↑ → SIN hold time
tSHIXE
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Baud rate
SCK fall time
SCK rise time
-
-
tF
tR
-
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Master mode
Slave mode
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram" in this data sheet.
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
−
When the external load capacitance = 30 pF.
Document Number: 002-04686 Rev.*C
Page 100 of 128
MB9B310T Series
tSCYC
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
Master mode
tSHSL
tR
SCK
tSLSH
VIH
VIH
VIL
VIL
tF
VIH
VIL
tSLOVE
VOH
VOL
SOT
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
SIN
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
tSLSH
tSHSL
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK fall time
SCK rise time
tF
tR
VIL
Document Number: 002-04686 Rev.*C
Min
tCYCP + 10
tCYCP + 10
CL = 30 pF
tR
SCK
Value
Conditions
VIH
5
5
-
tSHSL
VIL
Remarks
ns
ns
ns
ns
tF
tSLSH
VIH
Unit
Max
VIL
VIH
Page 101 of 128
MB9B310T Series
12.4.11 External Input Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Max
Unit
ADTG
Input pulse width
tINH,
tINL
FRCKx
ICxx
DTTIxX
INTxx,
NMIX
Remarks
A/D converter trigger input
-
2tCYCP*
-
ns
Except
Timer mode,
Stop mode
Timer mode,
Stop mode
2tCYCP*
-
ns
2tCYCP + 100*
-
ns
500
-
ns
Free-run timer input clock
Input capture
Wave form generator
External interrupt
NMI
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to,
see "8. Block Diagram" in this data sheet.
Document Number: 002-04686 Rev.*C
Page 102 of 128
MB9B310T Series
12.4.12 Quadrature Position/Revolution Counter timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
AIN pin "H" width
AIN pin "L" width
BIN pin "H" width
BIN pin "L" width
BIN rise time from
AIN pin "H" level
AIN fall time from
BIN pin "H" level
BIN fall time from
AIN pin "L" level
AIN rise time from
BIN pin "L" level
AIN rise time from
BIN pin "H" level
BIN fall time from
AIN pin "H" level
AIN fall time from
BIN pin "L" level
BIN rise time from
AIN pin "L" level
ZIN pin "H" width
ZIN pin "L" width
AIN/BIN rise and fall time from
determined ZIN level
Determined ZIN level from AIN/BIN
rise and fall time
Symbol
Conditions
tAHL
tALL
tBHL
tBLL
-
tAUBU
PC_Mode2 or PC_Mode3
tBUAD
PC_Mode2 or PC_Mode3
tADBD
PC_Mode2 or PC_Mode3
tBDAU
PC_Mode2 or PC_Mode3
tBUAU
PC_Mode2 or PC_Mode3
tAUBD
PC_Mode2 or PC_Mode3
tBDAD
PC_Mode2 or PC_Mode3
tADBU
PC_Mode2 or PC_Mode3
tZHL
tZLL
QCR:CGSC="0"
QCR:CGSC="0"
tZABE
QCR:CGSC="1"
tABEZ
QCR:CGSC="1"
Value
Min
Max
2tCYCP*
-
Unit
ns
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see "8. Block Diagram" in this
data sheet.
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
Document Number: 002-04686 Rev.*C
tBLL
Page 103 of 128
MB9B310T Series
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-04686 Rev.*C
Page 104 of 128
MB9B310T Series
2
12.4.13 I C Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Standard-mode
Min
Max
Fast-mode
Min
Max
Unit
Remarks
SCL clock frequency
FSCL
0
100
0
400
kHz
(Repeated) START condition hold
time
SDA ↓ → SCL ↓
tHDSTA
4.0
-
0.6
-
μs
tLOW
tHIGH
4.7
4.0
-
1.3
0.6
-
μs
μs
4.7
-
0.6
-
μs
0
3.45*2
0
0.9*3
μs
tSUDAT
250
-
100
-
ns
tSUSTO
4.0
-
0.6
-
μs
tBUF
4.7
-
1.3
-
μs
2 tCYCP*4
-
2 tCYCP*4
-
ns
*5
3 tCYCP*4
-
3 tCYCP*4
-
ns
*5
4 tCYCP*4
-
4 tCYCP*4
-
ns
*5
SCLclock "L" width
SCLclock "H" width
(Repeated) START setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
Bus free time between
"STOP condition" and
"START condition"
Noise filter
*1:
*2:
*3:
*4:
*5:
tSUSTA
tHDDAT
tSP
CL = 30 pF,
R = (Vp/IOL)*1
8 MHz ≤
tCYCP ≤ 40 MHz
40 MHz <
tCYCP ≤ 60 MHz
60 MHz <
tCYCP ≤ 72 MHz
R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement
of "tSUDAT ≥ 250 ns".
tCYCP is the APB bus clock cycle time.
About the APB bus number which I2C is connected to, see "8. Block Diagram" in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
The number of steps of the noise filter can be changed with register settings.
Change the number of the noise filter steps according to APB2 bus clock frequency.
SDA
SCL
Document Number: 002-04686 Rev.*C
Page 105 of 128
MB9B310T Series
12.4.14 ETM Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Data hold
TRACECLK
frequency
Symbol
Pin name
tETMH
TRACECLK,
TRACED[3:0]
Value
Unit
Min
Max
Vcc ≥ 4.5V
2
9
Vcc < 4.5V
2
15
Vcc ≥ 4.5V
-
50
MHz
Vcc < 4.5V
-
32
MHz
Vcc ≥ 4.5V
20
-
ns
Vcc < 4.5V
31.25
-
ns
Remarks
ns
1/ tTRACE
TRACECLK
TRACECLK
cycle time
Conditions
tTRACE
Note:
−
When the external load capacitance = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
Document Number: 002-04686 Rev.*C
Page 106 of 128
MB9B310T Series
12.4.15 JTAG Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
TMS, TDI setup time
tJTAGS
TCK,
TMS, TDI
Vcc < 4.5 V
TMS, TDI hold time
tJTAGH
TCK,
TMS, TDI
Vcc < 4.5 V
TDO delay time
tJTAGD
TCK,
TDO
Value
Unit
Min
Max
15
-
ns
15
-
ns
Vcc ≥ 4.5 V
-
25
Vcc < 4.5 V
-
45
Vcc ≥ 4.5 V
Vcc ≥ 4.5 V
Remarks
ns
Note:
−
When the external load capacitance = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-04686 Rev.*C
Page 107 of 128
MB9B310T Series
12.5 12-bit A/D Converter
Electrical characteristics for the A/D converter
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 85°C)
Parameter
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition voltage
Conversion time
Sampling time
Value
Pin
name
Min
Typ
Max
-
-
VZT
VFST
ANxx
ANxx
12
± 4.5
± 2.5
± 15
AVRH ± 15
bit
LSB
LSB
mV
mV
-
-
1.0*1
1.2*1
-
-
-
-
μs
*2
-
-
*2
-
-
Symbol
-
Unit
Ts
-
Compare clock cycle*3
Tcck
-
50
-
2000
ns
State transition time to
operation permission
Tstt
-
-
-
1.0
μs
Analog input capacity
CAIN
-
-
-
12.9
pF
Analog input resistance
RAIN
-
-
-
Interchannel disparity
Analog port input leak current
-
ANxx
-
Analog input voltage
-
ANxx
Reference voltage
-
AVRH
2
ns
kΩ
-
3.8
4
5
LSB
μA
AVSS
-
AVRH
V
2.7
-
AVCC
V
Remarks
AVRH = 2.7 V to 5.5 V
AVcc ≥ 4.5 V
AVcc < 4.5 V
AVcc ≥ 4.5 V
AVcc < 4.5 V
AVcc ≥ 4.5 V
AVcc < 4.5 V
*1: The Conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is the following.
AVcc ≥ 4.5 V, HCLK=120 MHz
sampling time: 300 ns
compare time: 700 ns
AVcc < 4.5 V, HCLK=120 MHz
sampling time: 500 ns
compare time: 700 ns
Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).
For setting of the sampling time and compare clock cycle, see "Chapter 1-1: A/D Converter" in
"FM3 Family Peripheral Manual Analog Macro Part".
The registers setting of the A/D Converter are reflected in the operation according to the APB bus clock timing.
The sampling clock and compare clock is generated from the Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see "8. Block Diagram" in this data sheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3: Compare time (Tc) is the value of (Equation 2).
Document Number: 002-04686 Rev.*C
Page 108 of 128
MB9B310T Series
Rext
ANxx
Analog input pin
Comparator
RAIN
Analog signal
source
CAIN
(Equation 1) Ts ≥ ( RAIN + Rext ) × CAIN × 9
Ts:
RAIN:
Sampling time
Input resistance of A/D = 2 kΩ at 4.5 V ≤ AVCC ≤ 5.5 V
Input resistance of A/D = 3.8 kΩ at 2.7 V ≤ AVCC < 4.5 V
CAIN:
Input capacity of A/D = 12.9 pF at 2.7 V ≤ AVCC ≤ 5.5 V
Rext:
Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc:
Compare time
Tcck:
Compare clock cycle
Document Number: 002-04686 Rev.*C
Page 109 of 128
MB9B310T Series
Definition of 12-bit A/D Converter Terms
Resolution
:
Analog variation that is recognized by an A/D converter.
Integral Nonlinearity
:
Deviation of the line between the zero-transition point
(0b000000000000←→0b000000000001) and the full-scale transition point
(0b111111111110←→0b111111111111) from the actual conversion characteristics.
Differential Nonlinearity
:
Deviation from the ideal value of the input voltage that is required to change the output code by 1
LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
0xN
Ideal characteristics
V(N+1)T
0x(N-1)
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
0x002
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZT (Actually-measured value)
AVss
Actual conversion characteristics
AVRH
AVss
AVRH
Analog input
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
N:
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VZT
4094
A/D converter digital output value.
VZT:
Voltage at which the digital output changes from 0x000 to 0x001.
VFST:
Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT:
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-04686 Rev.*C
Page 110 of 128
MB9B310T Series
12.6 USB characteristics
The USB characteristics of ch.0 and those of ch.1 are the same.
USBVcc0 and USBVcc1 are described as USBVcc below.
(Vcc = 2.7V to 5.5V, USBVcc = 3.0V to 3.6V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Value
Conditions
Unit
Min
Max
Remarks
VIH
-
2.0
USBVcc + 0.3
V
*1
VIL
-
Vss - 0.3
0.8
V
*1
VDI
-
0.2
-
V
*2
Different common mode range
VCM
-
0.8
2.5
V
*2
Output "H" level voltage
VOH
2.8
3.6
V
*3
Output "L" level voltage
VOL
0.0
0.3
V
*3
Output
charact-eris Crossover voltage
Rise time
tics
Fall time
Rise/ fall time matching
Output impedance
Rise time
Fall time
Rise/ fall time matching
VCRS
tFR
tFF
tFRFM
ZDRV
tLR
tLF
tLRFM
1.3
4
4
90
28
75
75
80
2.0
20
20
111.11
44
300
300
125
V
ns
ns
%
Ω
ns
ns
%
*4
*5
*5
*5
*6
*7
*7
*7
Input "H" level voltage
Input
Input "L" level voltage
charact-eris
Differential input sensitivity
tics
UDP0,
UDM0
External
pull-down
resistance =
15 kΩ
External pull-up
resistance =
1.5 kΩ
Full-Speed
Full-Speed
Full-Speed
Full-Speed
Low-Speed
Low-Speed
Low-Speed
Minimum differential input
sensitivity [V]
*1: The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V, VIH (Min) = 2.0 V
(TTL input standard).
There are some hysteresis to lower noise sensitivity.
*2: Use differential-Receiver to receive USB differential data signal.
Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the
local ground reference level.
Above voltage range is the common mode input voltage range .
Common mode input voltage [V]
Document Number: 002-04686 Rev.*C
Page 111 of 128
MB9B310T Series
*3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to
ground and 1.5 kΩ load) at High-State (VOH).
*4: The cross voltage of the external differential output signal (D + /D − ) of USB I/O buffer is within 1.3 V to 2.0 V.
VCRS specified range
*5: They indicate rise time (Trise) and fall time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission.
Rising time
Document Number: 002-04686 Rev.*C
Falling time
Page 112 of 128
MB9B310T Series
*6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic impedance (Differential
Mode).
USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series resistor
(Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistance.
Rs series resistor 25Ω to 30Ω
Series resistor of 27Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence".
*7: They indicate rise time (Trise) and fall time (Tfall) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
Rising time
Falling time
See Figure "Low-Speed Load (Compliance Load)" for conditions of external load.
Document Number: 002-04686 Rev.*C
Page 113 of 128
MB9B310T Series
Low-Speed Load (Upstream Port Load) - Reference 1
CL = 50pF to 150pF
CL = 50pF to 150pF
Low-Speed Load (Downstream Port Load) - Reference 2
CL =200pF to
600pF
CL =200pF to
600pF
Low-Speed Load (Compliance Load)
CL = 200pF to 450pF
CL = 200pF to 450pF
Document Number: 002-04686 Rev.*C
Page 114 of 128
MB9B310T Series
12.7 Low-Voltage Detection Characteristics
12.7.1 Low-Voltage Detection Reset
(TA = - 40°C to + 85°C)
Parameter
Detected voltage
Released voltage
Symbol
Conditions
VDL
VDH
-
Min
Value
Typ
Max
2.25
2.30
2.45
2.50
2.65
2.70
Unit
V
V
Remarks
When voltage drops
When voltage rises
12.7.2 Interrupt of Low-Voltage Detection
(TA = - 40°C to + 85°C)
Parameter
Symbol
Detected voltage
Released voltage
Detected voltage
VDL
VDH
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
Detected voltage
VDL
Released voltage
VDH
LVD stabilization wait time
TLVDW
Conditions
SVHI = 0000
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0111
SVHI = 1000
SVHI = 1001
-
Min
Value
Typ
Max
2.58
2.67
2.76
2.8
2.9
3.0
3.02
3.13
3.24
V
V
V
When voltage drops
When voltage rises
When voltage drops
2.85
3.1
3.34
V
When voltage rises
2.94
3.2
3.45
V
When voltage drops
3.04
3.3
3.56
V
When voltage rises
3.31
3.6
3.88
V
When voltage drops
3.40
3.7
3.99
V
When voltage rises
3.40
3.7
3.99
V
When voltage drops
3.50
3.8
4.10
V
When voltage rises
3.68
4.0
4.32
V
When voltage drops
3.77
4.1
4.42
V
When voltage rises
3.77
4.1
4.42
V
When voltage drops
3.86
4.2
4.53
V
When voltage rises
3.86
4.2
4.53
V
When voltage drops
3.96
4.3
4.64
V
When voltage rises
-
-
4032 × tCYCP*
μs
Unit
Remarks
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-04686 Rev.*C
Page 115 of 128
MB9B310T Series
12.8 Flash Memory Write/Erase Characteristics
12.8.1 Write / Erase time
(Vcc = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Parameter
Value
Typ*
Max*
Large Sector
0.7
3.7
Small Sector
0.3
1.1
12
13.6
Sector erase time
Half word (16-bit)
write time
Chip erase time
Unit
Remarks
s
Includes write time prior to internal erase
384
μs
Not including system-level overhead time.
68
s
Includes write time prior to internal erase
*: The typical value is immediately after shipment, the maximum value is guarantee value under 100,000 cycle of erase/write.
12.8.2 Write cycles and data hold time
Erase/write cycles
(cycle)
Data hold time
(year)
1,000
20*
10,000
10*
100,000
5*
Remarks
*: At average + 85°C
Document Number: 002-04686 Rev.*C
Page 116 of 128
MB9B310T Series
12.9 Return Time from Low-Power Consumption Mode
12.9.1 Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
Typ
Max*
tCYCC
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Unit
ns
40
80
μs
453
737
μs
Sub TIMER mode
453
737
μs
STOP mode
453
737
μs
Low-speed CR TIMER mode
Ticnt
Remarks
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*)
Ext.INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-04686 Rev.*C
Page 117 of 128
MB9B310T Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family Peripheral Manual about
the return factor from Low-Power consumption mode.
−
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "Chapter 6: Low Power Consumption Mode" in "FM3 Family Peripheral Manual".
Document Number: 002-04686 Rev.*C
Page 118 of 128
MB9B310T Series
12.9.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Parameter
Value
Symbol
Unit
Typ
Max*
321
461
μs
321
461
μs
441
701
μs
Sub TIMER mode
441
701
μs
STOP mode
441
701
μs
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Low-speed CR TIMER mode
Trcnt
Remarks
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Document Number: 002-04686 Rev.*C
Start
Page 119 of 128
MB9B310T Series
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family Peripheral Manual.
−
When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption
mode transition. See "Chapter 6: Low Power Consumption Mode" in "FM3 Family Peripheral Manual".
−
The time during the power-on reset/low-voltage detection reset is excluded. See "12.4.7. Power-on Reset Timing in
12.4. AC Characteristics in Electrical Characteristics" for the detail on the time during the power-on reset/low -voltage detection
reset.
−
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time.
−
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-04686 Rev.*C
Page 120 of 128
MB9B310T Series
13. Ordering Information
On-chip
Flash
memory
On-chip
SRAM
MB9BF316SPMC-GK7E1
512 Kbyte
64 Kbyte
MB9BF317SPMC-GK7E1
768 Kbyte
96 Kbyte
MB9BF318SPMC-GK7E1
1 Mbyte
128 Kbyte
MB9BF316TPMC-GK7E1
512 Kbyte
64 Kbyte
MB9BF317TPMC-GK7E1
768 Kbyte
96 Kbyte
MB9BF318TPMC-GK7E1
1 Mbyte
128 Kbyte
MB9BF316TBGL-GK7E1
512 Kbyte
64 Kbyte
MB9BF317TBGL-GK7E1
768 Kbyte
96 Kbyte
MB9BF318TBGL-GK7E1
1 Mbyte
128 Kbyte
Part number
Document Number: 002-04686 Rev.*C
Package
Packing
144-pin plastic LQFP
(0.5 mm pitch), (LQS144)
176-pin plastic LQFP
(0.5 mm pitch), (LQP176)
Tray
192-ball plastic FBGA
(0.8 mm pitch), (LBE192)
Page 121 of 128
MB9B310T Series
14. Package Dimensions
Package Type
Package Code
LQFP 176
LQP176
D
D1
132
4
5 7
89
133
89
88
132
133
88
E1
E
5
7
4
3
6
176
45
1
176
45
44
44
1
2 5 7
e
3
BOTTOM VIEW
0.10 C A-B D
0.20 C A-B D
b
0.08
C A-B
D
8
TOP VIEW
2
A
9
c
A
A'
0.08 C
SIDE VIEW
SYMBOL
L1
0.25
A1
10
L
b
SECTION A-A'
DIMENSIONS
MIN.
NOM. MAX.
0.05
0.15
1.70
A
A1
SEATING
PLANE
b
0.17
c
0.09
0.22
0.20
D
26.00 BSC
D1
24.00 BSC
e
0.50 BSC
E
26.00 BSC
E1
0.27
24.00 BSC
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
0
8
PACKAGE OUTLINE, 176 LEAD LQFP
24.0X24.0X1.7 MM LQP176 REV**
Document Number: 002-04686 Rev.*C
002-15150 **
Page 122 of 128
MB9B310T Series
Package Type
Package Code
LQFP 144
LQS144
4
D
D1
108
4
5 7
7 5
73
109
73
72
D
D1
108
109
72
E1
E
5
7
E
4
4
E1
5
7
3
3
6
144
37
1
144
37
36
1
36
BOTTOM VIEW
2 5 7
e
3
0.10 C A-B D
0.20 C A-B D
b
0.08
TOP VIEW
C A-B
D
8
2
A
9 c
A
A'
0.08 C
SEATING
PLANE
L1
0.25
L
A1
10
b
SECTION A-A'
SIDE VIEW
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
1.70
A
A1
0.05
0.15
b
0.17
c
0.09
0.22
0.27
0.20
D
22.00 BSC
D1
20.00 BSC
e
0.50 BSC
E
22.00 BSC
20.00 BSC
E1
L
0.45
0.60
0.75
L1
0.30
0.50
0.70
PACKAGE OUTLINE, 144 LEAD LQFP
20.0X20.0X1.7 MM LQS144 REV*A
Document Number: 002-04686 Rev.*C
002-13015 *A
Page 123 of 128
MB9B310T Series
Package Type
Package Code
FBGA 192
LBE192
A
0.20 C
14
2X
13
12
7
11
10
9
8
7
6
5
4
3
2
1
P
PIN A1
CORNER
INDEX MARK
8
N
M
L
K
J
H
G
F
E
B
D
C
B
A
7
0.20 C
192xφ b
0.08
C A B
6
2X
TOP VIEW
BOTTOM VIEW
DETAIL A
0.10 C
C
SIDE VIEW
DETAIL A
NOTES
DIMENSIONS
SYMBOL
MIN.
NOM.
A
A1
0.25
D
0.35
1. ALL DIMENSIONS ARE IN MILLIMETERS.
1.45
2. DIMENSIONS AND TOLERANCES METHODS PER ASME Y14.5-2009.
THIS OUTLINE CONFORMS TO JEP95, SECTION 4.5.
0.45
3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-010.
4. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
12.00 BSC
E
12.00 BSC
D1
10.40 BSC
E1
10.40 BSC
MD
14
ME
14
n
192
b
MAX.
0.35
0.45
eD
0.80 BSC
eE
0.80 BSC
SD / SE
0.40 BSC
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
6. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER
IN A PLANE PARALLEL TO DATUM C.
0.55
7. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" =0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
8. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK.
METALLIZED MARK INDENTATION OR OTHER MEANS.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
PACKAGE OUTLINE, 192 BALL FBGA
12.00X12.00X1.45 MM LBE192 REV**
Document Number: 002-04686 Rev.*C
002-13493 **
Page 124 of 128
MB9B310T Series
15. Major Changes
Spansion Publication Number: DS706-00017
Page
Revision 1.0
Revision 2.0
9 to 11
62, 63
Section
-
Initial release
Pin Assignment
Added the description of "Note".
• Revised the description of "•C pin".
• Added the description of "•Base Timer".
Corrected the figure.
- TIOA: input → input/output
- TIOB: output → input
• Added the "Smoothing capacitor (CS)".
• Added the footnote.
Added "Internal operating clock frequency (FCM):
Master clock".
• Added "Main PLL clock frequency (FCLKPLL)".
• Added "USB clock frequency (FCLKSPLL)".
Handling Devices
Block Diagram
64
75
80
82
Electrical Characteristics
2. Recommended Operating Conditions
4. AC Characteristics
(1) Main Clock Input Characteristics
(4-1) Operating Conditions of Main and USB PLL (In
the case of using main clock for input of PLL)
(4-2) Operating Conditions of Main PLL (In the case of
using high-speed internal CR)
5. 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
109
Revision 2.1
Revision 3.0
-
9, 10
Features
External Bus Interface
Features
USB Interface
Ethernet-MAC
Features
USB Interface
Pin Assignment
51 to 56
I/O Circuit Type
61
Handling Devices
61
Handling Devices
Crystal oscillator circuit
2
2
2
62
64
66
67
Change Results
Handling Devices
C Pin
Block Diagram
Memory Map
Memory map(1)
Memory Map
Memory map(2)
74, 75
Electrical Characteristics
1. Absolute Maximum Ratings
76
Electrical Characteristics
2. Recommended Operation Conditions
Document Number: 002-04686 Rev.*C
• Added the Symbol.
• Deleted the following Pin name.
- "Sampling time"
- "Compare clock cycle"
- "State transition time to operation permission"
- "Analog input capacity"
- "Analog input resistance"
• Corrected the value of "Compare clock cycle (Tcck)".
Max: 10000 → 2000
Company name and layout design change
Added the description of Maximum area size
Added the description of PLL for USB and Ethernet
Added the size of each EndPoint
Added SWCLK and SWDIO and SWO
· Added the description of I2C to the type of E, F, I, L
· Added about +B input
Added "Stabilizing power supply voltage"
Added the following description
"Evaluate oscillation of your using crystal oscillator by your mount
board."
Changed the description
Modified the block diagram
Modified the area of "External Device Area"
Added the summary of Flash memory sector and the note
· Added the Clamp maximum current
· Added the output current of P80, P81, P82, P83
· Added about +B input
· Modified the minimum value of Analog reference voltage
· Added Smoothing capacitor
· Added the note about less than the minimum power supply voltage
Page 125 of 128
MB9B310T Series
Page
77, 88
82
84
86 to 88
95 to 102
109
118 to 121
122
Section
Electrical Characteristics
3. DC Characteristics
(1) Current rating
Electrical Characteristics
4. AC Characteristics
(3) Built-in CR Oscillation Characteristics
Electrical Characteristics
4. AC Characteristics
(6) Power-on Reset Timing
Electrical Characteristics
4. AC Characteristics
(7) External Bus Timing
Electrical Characteristics
4. AC Characteristics
(9) CSIO/UART Timing
Electrical Characteristics
5. 12bit A/D Converter
Electrical Characteristics
9. Return Time from Low-Power Consumption Mode
Ordering Information
Change Results
· Changed the table format
· Added Main TIMER mode current
· Added Flash Memory Current
· Moved A/D Converter Current
Added Frequency stability time at Built-in high-speed CR
· Added Time until releasing Power-on reset
· Changed the figure of timing
Modified Data output time
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
· Added the typical value of Integral Nonlinearity, Differential
Nonlinearity, Zero transition voltage and Full-scale transition voltage
· Added Conversion time at AVcc < 4.5 V
· Modified Stage transition time to operation permission
· Modified the minimum value of Reference voltage
Added Return Time from Low-Power Consumption Mode
Change to full part number
Note:
−
Please see “Document History” about later revised information.
Document Number: 002-04686 Rev.*C
Page 126 of 128
MB9B310T Series
Document History
Document Title: MB9B310T Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller
Document Number: 002-04686
Revision
ECN
**
–
Orig. of
Submission
Change
Date
TOYO
02/10/2015
Description of Change
Migrated to Cypress and assigned document number 002-04686.
No change to document contents or format.
*A
5198810
TOYO
03/31/2016
Updated to Cypress format.
Updated “12.4.7 Power-On Reset Timing”. Changed parameter from “Power Supply
rising time(Tr)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and added some comments
(Page 83)
Added Notes for JTAG (Page 50), Changed “J-TAG” to” JTAG” in “4 List of Pin
Functions” (Page 32)
Updated Package code and dimensions as follows (Page 8-11, 75, 122-125)
FPT-144P-M08 -> LQS144,
FPT-176P-M07
-> LQP176,
BGA-192P-M06 -> LBE192
Change the name from “USB Function” to “USB Device” (Page 1, 7, 48)
*B
5560212
YSKA
03/09/2017
Corrected the following statement
Analog port input current Analog port input leak current
in chapter 12.5. 12-bit A/D Converter (Page 109)
Added the Baud rate spec in “12.4.10 CSIO/UART Timing”.(Page 95, 97, 99, 101)
Deleted MPNs below from “13. Ordering Information” (Page 122)
MB9BF316SPMC-GE1, MB9BF316TBGL-GE1, MB9BF316TPMC-GE1,
MB9BF317SPMC-GE1, MB9BF317TBGL-GE1, MB9BF317TPMC-GE1,
MB9BF318SPMC-GE1, MB9BF318TBGL-GE1, MB9BF318TPMC-GE1
Added MPNs below to “13. Ordering Information” (Page 122)
MB9BF316SPMC-GK7E1, MB9BF316TBGL-GK7E1, MB9BF316TPMC-GK7E1,
MB9BF317SPMC-GK7E1, MB9BF317TBGL-GK7E1, MB9BF317TPMC-GK7E1,
MB9BF318SPMC-GK7E1, MB9BF318TBGL-GK7E1, MB9BF318TPMC-GK7E1
*C
5797539
YSAT
Document Number: 002-04686 Rev.*C
07/11/2017
Adapted new Cypress logo
Page 127 of 128
MB9B310T Series
Sales, Solutions, and Legal Information
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office closest to you, visit us at Cypress Locations.
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ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
All other trademarks or registered trademarks referenced herein are the property of their respective owners.
© Cypress Semiconductor Corporation, 2011-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or
other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software,
then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source
code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form
externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are
infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction,
modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It
is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress
products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support
devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the
failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform
can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress
from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs,
damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-04686 Rev.*C
July 11, 2017
Page 128 of 128
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