CY9BF515RPMC-G-JNE2

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY9B510R Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller The CY9B510R Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the Arm Cortex-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, CAN, UART, CSIO, I2C, LIN). The products which are described in this data sheet are placed into TYPE4 product categories in FM3 Family Peripheral Manual. Features External Bus Interface 32-bit Arm Cortex-M3 Core ◼ Processor version: r2p1 ◼ Up to 144 MHz Frequency Operation ◼ Memory Protection Unit (MPU): improves the reliability of an ◼ Supports SRAM, NOR and NAND Flash device ◼ Integrated Nested Vectored Interrupt Controller (NVIC): 1 ◼ Maximum area size: Up to 256 Mbytes embedded system NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels ◼ 24-bit System timer (Sys Tick): System timer for OS task ◼ Up to 8 chip selects ◼ 8-/16-bit Data width ◼ Up to 25-bit Address bit ◼ Supports Address/Data multiplex ◼ Supports external RDY input management USB Interface On-chip Memories [Flash memory] These series are based on two independent on-chip Flash memories. ◼ MainFlash  Up to 512 Kbyte Flash Accelerator System with 16 Kbyte trace buffer memory  The read access to Flash memory can be achieved without wait cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System.  Security function for code protection  Built-in ◼ WorkFlash  32 Kbyte cycle  4wait-cycle: the operation frequency more than 72 MHz  2wait-cycle: the operation frequency more than 40 MHz, and to 72 MHz  0wait-cycle: the operation frequency to 40 MHz  Security function is shared with code protection  Read [SRAM] This Series contain a total of up to 64 Kbyte on-chip SRAM. This is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. ◼ SRAM0: Up to 32 Kbyte USB interface is composed of Device and Host. PLL for USB is built-in, USB clock can be generated by multiplication of Main clock. ◼ USB device  USB2.0 Full-Speed supported 6 EndPoint supported • EndPoint 0 is control transfer • EndPoint 1, 2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer • EndPoint 3 to 5 can be selected Bulk-transfer or Interrupt-transfer • EndPoint 1 to 5 is comprised Double Buffer • The size of each EndPoint is as follows. • EndPoint 0, 2 to 5: 64 bytes • EndPoint 1: 256 bytes ◼ USB host  USB2.0 Full/Low-speed supported  Bulk-transfer, interrupt-transfer and Isochronous-transfer support  USB Device connected/dis-connected automatically detect  IN/OUT token handshake packet automatically  Max 256-byte packet-length supported  Wake-up function supported  Max CAN Interface (Max two channels) ◼ Compatible with CAN Specification 2.0A/B ◼ Maximum transfer rate: 1 Mbps ◼ Built-in 32 message buffer ◼ SRAM1: Up to 32 Kbyte Cypress Semiconductor Corporation Document Number: 002-08541 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 September 11, 2020 CY9B510R Series Multi-function Serial Interface (Max eight channels) A/D Converter (Max 16 channels) ◼ 4 channels with 16 steps×9-bit FIFO (ch.4 to ch.7), 4 ◼ 12-bit A/D Converter channels without FIFO (ch.0 to ch.3) ◼ Operation mode is selectable from the followings for each channel.  UART  CSIO  LIN  I2 C ◼ UART  Successive Approximation Register type 3 unit  Conversion time: 1.0 μs @ 5 V  Priority conversion available (priority at 2 levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps)  Built-in  Full-duplex Base Timer (Max eight channels)  Selection Operation mode is selectable from the followings for each channel. double buffer with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)  Various error detect functions available (parity errors, framing errors, and overrun errors) ◼ CSIO double buffer dedicated baud rate generator  Overrun error detect function available ◼ 16-bit PWM timer ◼ 16-bit PPG timer ◼ 16-/32-bit reload timer ◼ 16-/32-bit PWC timer  Full-duplex  Built-in ◼ LIN  LIN protocol Rev.2.1 supported double buffer  Master/Slave mode supported  LIN break field generate (can be changed 13 to 16-bit length)  LIN break delimiter generate (can be changed 1 to 4-bit length)  Various error detect functions available (parity errors, framing errors, and overrun errors)  Full-duplex ◼ I2 C  Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported DMA Controller (Eight channels) DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously. ◼ 8 independently configured and operated channels ◼ Transfer can be started by software or request from the built-in peripherals ◼ Transfer address area: 32-bit (4 Gbyte) ◼ Transfer mode: Block transfer/Burst transfer/Demand transfer ◼ Transfer data type: byte/half-word/word ◼ Transfer block count: 1 to 16 ◼ Number of transfers: 1 to 65536 Document Number: 002-08541 Rev. *D General Purpose I/O Port This series can use its pins as general purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated. ◼ Capable of pull-up control per pin ◼ Capable of reading pin level directly ◼ Built-in the port relocate function ◼ Up 103 fast general purpose I/O Ports @ 120 pin Package ◼ Some pin is 5 V tolerant I/O. See "4 List of Pin Functions" to confirm the corresponding pins. Multi-function Timer (Max three units) The Multi-function timer is composed of the following blocks. ◼ 16-bit free-run timer × 3 ch./unit ◼ Input capture × 4 ch./unit ◼ Output compare × 6 ch./unit ◼ A/D activating compare × 3 ch./unit ◼ Waveform generator × 3 ch./unit ◼ 16-bit PPG timer × 3 ch./unit The following function can be used to achieve the motor control. ◼ PWM signal output function ◼ DC chopper waveform output function ◼ Dead time function ◼ Input capture function ◼ A/D convertor activate function ◼ DTIF (Motor emergency stop) interrupt function Page 2 of 117 CY9B510R Series Real-time clock (RTC) Watchdog Timer (Two channels) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99. A watchdog timer can generate interrupts or a reset when a time-out value is reached. ◼ Interrupt function with specifying date and time This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog. ◼ Timer interrupt function after set time or each set time. "Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, "Hardware" watchdog is active in any power consumption mode except Stop mode. (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute. ◼ Capable of rewriting the time with continuing the time count. ◼ Leap year automatic count is available. CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator helps a verify data transmission or storage integrity. Quadrature Position/Revolution Counter (QPRC) (Max three channels) CCITT CRC16 and IEEE-802.3 CRC32 are supported. The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter. ◼ CCITT CRC16 Generator Polynomial: 0x1021 ◼ IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 ◼ The detection edge of the three external event input pins AIN, Clock and Reset BIN and ZIN is configurable. ◼ 16-bit position counter ◼ 16-bit revolution counter ◼ Two 16-bit compare registers ◼ Clocks Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically selectable.  Main Clock: 4 MHz to 48 MHz Clock: 32.768 kHz  High-speed internal CR Clock: 4 MHz  Low-speed internal CR Clock: 100 kHz  Sub Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel. ◼ Free-running ◼ Periodic (=Reload) ◼ One-shot Watch Counter ◼ Resets  Reset requests from INITX pin on reset  Software reset  Watchdog timers reset  Low-voltage detector reset  Clock supervisor reset  Power Clock Super Visor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks. The Watch counter is used for wake up from power consumption mode. ◼ External OSC clock failure (clock stop) is detected, reset is ◼ Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz ◼ External OSC frequency anomaly is detected, interrupt or External Interrupt Controller Unit ◼ Up to 16 external interrupt input pin ◼ Include one non-maskable interrupt (NMI) asserted. reset is asserted. Low-Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage has been set, Low-Voltage Detector generates an interrupt or reset. ◼ LVD1: error reporting via interrupt ◼ LVD2: auto-reset operation Document Number: 002-08541 Rev. *D Page 3 of 117 CY9B510R Series Low-Power Consumption Mode Power Supply Three power consumption modes supported. Two Power Supplies ◼ Sleep ◼ Wide range voltage: ◼ Timer ◼ Stop VCC = 2.7 V to 5.5 V ◼ USB for USB I/O voltage: USBVCC = 3.0 V to 3.6 V (when USB is used) = 2.7 V to 5.5 V (when GPIO is used) Debug ◼ Serial Wire JTAG Debug Port (SWJ-DP) ◼ Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities. Document Number: 002-08541 Rev. *D Page 4 of 117 CY9B510R Series Contents 1. Product Lineup ............................................................................................................................................................ 7 2. Packages ...................................................................................................................................................................... 9 3. Pin Assignments ....................................................................................................................................................... 10 4. List of Pin Functions ................................................................................................................................................. 14 5. I/O Circuit Type .......................................................................................................................................................... 41 6. Handling Precautions................................................................................................................................................ 46 6.1 Precautions for Product Design ................................................................................................................................ 46 6.2 Precautions for Package Mounting ........................................................................................................................... 47 6.3 Precautions for Use Environment ............................................................................................................................. 49 7. Handling Devices ...................................................................................................................................................... 50 8. Block Diagram ........................................................................................................................................................... 52 9. Memory Size .............................................................................................................................................................. 52 10. Memory Map .............................................................................................................................................................. 53 11. Pin Status in Each CPU State ................................................................................................................................... 57 12. Electrical Characteristics.......................................................................................................................................... 61 12.1 Absolute Maximum Ratings ...................................................................................................................................... 61 12.2 Recommended Operating Conditions ....................................................................................................................... 63 12.3 DC Characteristics .................................................................................................................................................... 64 12.3.1 Current Rating ....................................................................................................................................................... 64 12.3.2 Pin Characteristics ................................................................................................................................................. 66 12.4 AC Characteristics .................................................................................................................................................... 68 12.4.1 Main Clock Input Characteristics ........................................................................................................................... 68 12.4.2 Sub Clock Input Characteristics ............................................................................................................................. 69 12.4.3 Internal CR Oscillation Characteristics................................................................................................................... 69 12.4.4 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL) ............................ 70 12.4.5 Operating Conditions of Main PLL (In the case of using high-speed internal CR) ................................................. 70 12.4.6 Reset Input Characteristics .................................................................................................................................... 71 12.4.7 Power-on Reset Timing ......................................................................................................................................... 71 12.4.8 External Bus Timing ............................................................................................................................................... 72 12.4.9 Base Timer Input Timing ........................................................................................................................................ 81 12.4.10 CSIO/UART Timing................................................................................................................................................ 82 12.4.11 External Input Timing ............................................................................................................................................. 90 12.4.12 Quadrature Position/Revolution Counter timing ..................................................................................................... 91 12.4.13 I2C Timing .............................................................................................................................................................. 93 12.4.14 ETM Timing ........................................................................................................................................................... 94 12.4.15 JTAG Timing .......................................................................................................................................................... 95 12.5 12-bit A/D Converter ................................................................................................................................................. 96 12.6 USB Characteristics ................................................................................................................................................. 99 12.7 Low-Voltage Detection Characteristics ................................................................................................................... 103 12.7.1 Low-Voltage Detection Reset .............................................................................................................................. 103 12.7.2 Interrupt of Low-Voltage Detection ...................................................................................................................... 103 12.8 MainFlash Memory Write/Erase Characteristics ..................................................................................................... 104 12.8.1 Write / Erase time ................................................................................................................................................ 104 12.8.2 Erase/write cycles and data hold time.................................................................................................................. 104 12.9 WorkFlash Memory Write/Erase Characteristics .................................................................................................... 104 12.9.1 Write / Erase time ................................................................................................................................................ 104 Document Number: 002-08541 Rev. *D Page 5 of 117 CY9B510R Series 12.9.2 Erase/write cycles and data hold time.................................................................................................................. 104 12.10 Return Time from Low-Power Consumption Mode ................................................................................................. 105 12.10.1 Return Factor: Interrupt........................................................................................................................................ 105 12.10.2 Return Factor: Reset............................................................................................................................................ 107 13. Ordering Information............................................................................................................................................... 109 14. Package Dimensions............................................................................................................................................... 110 15. Major Changes ......................................................................................................................................................... 114 Document History ............................................................................................................................................................... 116 Worldwide Sales and Design Support .................................................................................................................................. 117 Products ............................................................................................................................................................................... 117 PSoC® Solutions ................................................................................................................................................................... 117 Cypress Developer Community ............................................................................................................................................ 117 Technical Support ................................................................................................................................................................. 117 Document Number: 002-08541 Rev. *D Page 6 of 117 CY9B510R Series 1. Product Lineup Memory Size Product name MainFlash WorkFlash On-chip RAM SRAM0 SRAM1 CY9BF512N/R 128 Kbyte 32 Kbyte 16 Kbyte 8 Kbyte 8 Kbyte CY9BF514N/R 256 Kbyte 32 Kbyte 32 Kbyte 16 Kbyte 16 Kbyte CY9BF515N/R 384 Kbyte 32 Kbyte 48 Kbyte 24 Kbyte 24 Kbyte CY9BF516R 512 Kbyte 32 Kbyte 64 Kbyte 32 Kbyte 32 Kbyte Function Product name Pin count CPU CY9BF512N CY9BF514N CY9BF515N CY9BF516N CY9BF512R CY9BF514R CY9BF515R CY9BF516R 100/112 120 Cortex-M3 Freq. Power supply voltage range 144 MHz VCC: 2.7 V to 5.5 V (USBVCC: 3.0 V to 3.6 V) USB2.0 (Device/Host) CAN 1 ch. 2 ch. (Max) DMAC External Bus Interface MF Serial Interface (UART/CSIO/LIN/I2C) Base Timer (PWC/Reload timer/PWM/PPG) A/D activation 3 ch. compare Input 4 ch. capture Free-run MF3 ch. timer Timer Output 6 ch. compare Waveform 3 ch. generator PPG 3 ch. QPRC Dual Timer Real-Time Clock Watch Counter CRC Accelerator Watchdog timer External Interrupts I/O ports 12-bit A/D converter Document Number: 002-08541 Rev. *D 8 ch. Addr: 25-bit (Max) R/Wdata: 8-/16-bit (Max) CS: 8 (Max) Support: SRAM, NOR & NAND Flash 8 ch. (Max) ch.4 to ch.7: FIFO (16steps × 9-bit) ch.0 to ch.3: No FIFO Addr: 25-bit (Max) R/Wdata: 8-/16-bit (Max) CS: 8 (Max) Support: SRAM, NOR Flash 8ch. (Max) 3 units (Max) 3 ch. (Max) 1 unit 1 unit 1 unit Yes 1 ch. (SW) + 1 ch. (HW) 16 pins (Max) + NMI × 1 83 pins (Max) 103 pins (Max) 16 ch. (3 units) Page 7 of 117 CY9B510R Series Product name CSV (Clock Super Visor) LVD (Low-Voltage Detector) High-speed Internal OSC Low-speed Debug Function CY9BF512N CY9BF514N CY9BF515N CY9BF516N CY9BF512R CY9BF514R CY9BF515R CY9BF516R Yes 2 ch. 4 MHz 100 kHz SWJ-DP/ETM Note: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the General I/O port according to your function use. See "12 Electrical Characteristics 12.4 AC Characteristics 12.4.3 Internal CR Oscillation Characteristics" for accuracy of built-in CR. Document Number: 002-08541 Rev. *D Page 8 of 117 CY9B510R Series 2. Packages Product name Package QFP: PQH100 (0.65 mm pitch) LQFP: LQI100 (0.5 mm pitch) LQFP: LQM120 (0.5 mm pitch) FBGA: LBC112 (0.8 mm pitch) : Supported CY9BF512N CY9BF514N CY9BF515N CY9BF516N CY9BF512R CY9BF514R CY9BF515R CY9BF516R     - Note: − See "14. Package Dimensions" for detailed information on each package. Document Number: 002-08541 Rev. *D Page 9 of 117 CY9B510R Series 3. Pin Assignments LQI100 P01/TCK/SWCLK P00/TRSTX/MCSX7_0 VCC 78 77 76 P04/TDO/SWO P03/TMS/SWDIO P02/TDI/MCSX6_0 81 80 79 P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/AIN2_1/MCSX4_0 P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_0 83 82 P09/TRACECLK/TIOB0_2/RTS4_2/RTO20_1/MCSX2_0 P08/TRACED3/TIOA0_2/CTS4_2/ZIN2_1/MCSX3_0 P07/TRACED2/ADTG_0/SCK4_2/BIN2_1/MCLKOUT_0 86 85 84 P0B/SOT4_0/TIOB6_1/IC10_0/IC20_0/RTO22_1/MCSX0_0 P0A/SIN4_0/INT00_2/FRCK1_0/FRCK2_0/RTO21_1/MCSX1_0 88 87 P0E/CTS4_0/TIOB3_2/IC13_0/IC23_0/RTO25_1/MDQM1_0 P0D/RTS4_0/TIOA3_2/IC12_0/IC22_0/RTO24_1/MDQM0_0 P0C/SCK4_0/TIOA6_1/IC11_0/IC21_0/RTO23_1/MALE_0 91 90 89 P62/SCK5_0/ADTG_3/TX0_2/MOEX_0 P63/INT03_0/SIN5_1/RX0_2/MWEX_0 P0F/NMIX/CROUT_1/RTCCO_0/DTTI2X_0/DTTI2X_1/SUBOUT_0 94 93 92 USBVCC P60/SIN5_0/TIOA2_2/INT15_1/MRDY_0 P61/SOT5_0/TIOB2_2/UHCONX 97 96 99 98 95 VSS P81/UDP0 P80/UDM0 100 (Top View) VCC 1 75 VSS P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_0 2 74 P20/INT05_0/CROUT_0/AIN1_1/MAD24_0 P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_0 3 73 P21/SIN0_0/INT06_1/BIN1_1 P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_0 4 72 P22/SOT0_0/TIOB7_1/ZIN1_1 P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_0 5 71 P23/SCK0_0/TIOA7_1 P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_0 6 70 P1F/AN15/ADTG_5/FRCK0_1/MAD23_0 P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_0 7 69 P1E/AN14/RTS4_1/DTTI0X_1/MAD22_0 P56/INT08_2/DTTI1X_0/MADATA06_0 8 68 P1D/AN13/CTS4_1/IC03_1/MAD21_0 P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_0 9 67 P1C/AN12/SCK4_1/IC02_1/MAD20_0 P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_0 10 66 P1B/AN11/SOT4_1/IC01_1/MAD19_0 P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_0 11 65 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_0 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_0 12 64 P19/AN09/SCK2_2/MAD17_0 P34/FRCK0_0/TIOB4_1/TX0_1/MADATA11_0 13 63 P18/AN08/SOT2_2/MAD16_0 P35/IC03_0/TIOB5_1/RX0_1/INT08_1/MADATA12_0 14 62 AVSS LQFP - 100 P36/IC02_0/SIN5_2/INT09_1/MADATA13_0 15 61 AVRH P37/IC01_0/SOT5_2/INT10_1/MADATA14_0 16 60 AVCC P38/IC00_0/SCK5_2/INT11_1/MADATA15_0 17 59 P17/AN07/SIN2_2/INT04_1/MAD15_0 48 49 50 VSS MD0 PE2/X0 PE0/MD1 PE3/X1 45 46 47 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_0 43 44 P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_0 P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_0 P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_0 40 41 42 P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_0 P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_0 38 39 INITX P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_0 35 36 P42/TIOA2_0/RTO12_1 37 VCC VCC 51 P46/X0A 25 P47/X1A P10/AN00 VSS 32 P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/MAD09_0 52 33 53 24 34 23 P3F/RTO05_0/TIOA5_1 C P12/AN02/SOT1_1/TX1_2/IC00_2/MAD10_0 P3E/RTO04_0/TIOA4_1 VSS 54 P45/TIOA5_0/RTO15_1/MAD01_0 22 29 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/IC01_2/MAD11_0 P3D/RTO03_0/TIOA3_1 30 55 31 21 P43/TIOA3_0/RTO13_1/ADTG_7 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_0 P3C/RTO02_0/TIOA2_1 P44/TIOA4_0/RTO14_1/MAD00_0 56 26 20 27 P15/AN05/SOT0_1/IC03_2/MAD13_0 P3B/RTO01_0/TIOA1_1 28 P16/AN06/SCK0_1/MAD14_0 57 VCC 58 19 P40/TIOA0_0/RTO10_1/INT12_1 18 P41/TIOA1_0/RTO11_1/INT13_1 P39/DTTI0X_0/ADTG_2 P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-08541 Rev. *D Page 10 of 117 CY9B510R Series LQM120 P02/TDI/MCSX6_0 P01/TCK/SWCLK P00/TRSTX/MCSX7_0 VCC 94 93 92 91 P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_0 P04/TDO/SWO P03/TMS/SWDIO 97 96 99 98 95 P08/TRACED3/TIOA0_2/CTS4_2/ZIN2_1/MCSX3_0 P07/TRACED2/ADTG_0/SCK4_2/BIN2_1/MCLKOUT_0 P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/AIN2_1/MCSX4_0 100 P0B/SOT4_0/TIOB6_1/IC10_0/IC20_0/RTO22_1/MCSX0_0 P0A/SIN4_0/INT00_2/FRCK1_0/FRCK2_0/RTO21_1/MCSX1_0 P09/TRACECLK/TIOB0_2/RTS4_2/RTO20_1/MCSX2_0 103 102 101 P0E/CTS4_0/TIOB3_2/IC13_0/IC23_0/RTO25_1/MDQM1_0 P0D/RTS4_0/TIOA3_2/IC12_0/IC22_0/RTO24_1/MDQM0_0 P0C/SCK4_0/TIOA6_1/IC11_0/IC21_0/RTO23_1/MALE_0 106 105 104 P67/SOT3_0/TIOA7_2/IC21_1/RTO24_0 P68/SCK3_0/TIOB7_2/INT12_2/IC20_1/RTO25_0 P0F/NMIX/CROUT_1/RTCCO_0/DTTI2X_0/DTTI2X_1/SUBOUT_0 109 108 107 P64/TIOA7_0/SOT5_1/INT10_2/FRCK2_1/RTO21_0 P65/TIOB7_0/SCK5_1/IC23_1/RTO22_0 P66/SIN3_0/ADTG_8/INT11_2/IC22_1/RTO23_0 112 111 110 P62/SCK5_0/ADTG_3/TX0_2/MOEX_0 P63/INT03_0/SIN5_1/RX0_2/RTO20_0/MWEX_0 114 113 USBVCC P60/SIN5_0/TIOA2_2/INT15_1/MRDY_0 P61/SOT5_0/TIOB2_2/UHCONX 115 118 117 116 VSS P81/UDP0 P80/UDM0 120 119 (Top View) VCC 1 90 VSS P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_0 2 89 P20/INT05_0/CROUT_0/AIN1_1/MAD24_0 P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_0 3 88 P21/SIN0_0/INT06_1/BIN1_1 P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_0 4 87 P22/SOT0_0/TIOB7_1/ZIN1_1 P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_0 5 86 P23/SCK0_0/TIOA7_1/RTO00_1 P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_0 6 85 P24/RX1_0/SIN2_1/INT01_2/RTO01_1 P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_0 7 84 P25/TX1_0/SOT2_1/RTO02_1 P56/SIN1_0/INT08_2/DTTI1X_0/MADATA06_0 8 83 P26/SCK2_1/RTO03_1 P57/SOT1_0/MADATA07_0 9 82 P27/TIOA6_2/INT02_2/RTO04_1 P58/SCK1_0/AIN2_0/MADATA08_0 10 81 P28/TIOB6_2/ADTG_4/RTO05_1 P59/SIN7_0/RX1_1/INT09_2/BIN2_0/MADATA09_0 11 80 P1F/AN15/ADTG_5/FRCK0_1/MAD23_0 P5A/SOT7_0/TX1_1/ZIN2_0/MADATA10_0 12 79 P1E/AN14/RTS4_1/DTTI0X_1/MAD22_0 P5B/SCK7_0/MADATA11_0 13 78 P1D/AN13/CTS4_1/IC03_1/MAD21_0 P30/AIN0_0/TIOB0_1/INT03_2/MADATA12_0 14 77 P1C/AN12/SCK4_1/IC02_1/MAD20_0 P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA13_0 15 76 P1B/AN11/SOT4_1/IC01_1/MAD19_0 P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA14_0 16 75 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_0 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA15_0 17 74 P19/AN09/SCK2_2/MAD17_0 P34/FRCK0_0/TIOB4_1/TX0_1/MNALE_0 18 73 P18/AN08/SOT2_2/MAD16_0 P35/IC03_0/TIOB5_1/RX0_1/INT08_1/MNCLE_0 19 72 AVSS P36/IC02_0/SIN5_2/INT09_1/MNWEX_0 20 71 AVRH P37/IC01_0/SOT5_2/INT10_1/MNREX_0 21 70 AVCC P38/IC00_0/SCK5_2/INT11_1 22 69 P17/AN07/SIN2_2/INT04_1/MAD15_0 P39/DTTI0X_0/ADTG_2 23 68 P16/AN06/SCK0_1/MAD14_0 P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2 24 67 P15/AN05/SOT0_1/IC03_2/MAD13_0 P3B/RTO01_0/TIOA1_1 25 66 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_0 P3C/RTO02_0/TIOA2_1 26 65 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/IC01_2/MAD11_0 P3D/RTO03_0/TIOA3_1 27 64 P12/AN02/SOT1_1/TX1_2/IC00_2/MAD10_0 P3E/RTO04_0/TIOA4_1 28 63 P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/MAD09_0 P3F/RTO05_0/TIOA5_1 29 62 P10/AN00 VSS 30 61 VCC 57 58 59 60 MD0 VSS PE0/MD1 PE2/X0 P74/SCK2_0 PE3/X1 54 55 56 P73/SOT2_0/INT15_2/TIOB6_0 51 52 53 P70/TX0_0/TIOA4_2 P71/RX0_0/INT13_2/TIOB4_2 P72/SIN2_0/INT14_2/TIOA6_0 48 49 50 P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_0 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_0 P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_0 P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_0 45 46 47 P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_0 P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_0 42 43 44 INITX P47/X1A P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_0 39 40 41 VSS C VCC 37 38 P45/TIOA5_0/RTO15_1/MAD01_0 P46/X0A 36 P44/TIOA4_0/RTO14_1/MAD00_0 33 34 35 P42/TIOA2_0/RTO12_1 P43/TIOA3_0/RTO13_1/ADTG_7 31 32 VCC P40/TIOA0_0/RTO10_1/INT12_1 P41/TIOA1_0/RTO11_1/INT13_1 LQFP - 120 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-08541 Rev. *D Page 11 of 117 CY9B510R Series PQH100 VCC VSS P20/INT05_0/CROUT_0/AIN1_1/MAD24_0 P21/SIN0_0/INT06_1/BIN1_1 54 53 52 51 P02/TDI/MCSX6_0 P01/TCK/SWCLK P00/TRSTX/MCSX7_0 57 56 55 P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_0 P04/TDO/SWO P03/TMS/SWDIO 60 59 58 P08/TRACED3/TIOA0_2/CTS4_2/ZIN2_1/MCSX3_0 P07/TRACED2/ADTG_0/SCK4_2/BIN2_1/MCLKOUT_0 P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/AIN2_1/MCSX4_0 63 62 61 P0B/SOT4_0/TIOB6_1/IC10_0/IC20_0/RTO22_1/MCSX0_0 P0A/SIN4_0/INT00_2/FRCK1_0/FRCK2_0/RTO21_1/MCSX1_0 P09/TRACECLK/TIOB0_2/RTS4_2/RTO20_1/MCSX2_0 66 65 64 P0E/CTS4_0/TIOB3_2/IC13_0/IC23_0/RTO25_1/MDQM1_0 P0D/RTS4_0/TIOA3_2/IC12_0/IC22_0/RTO24_1/MDQM0_0 P0C/SCK4_0/TIOA6_1/IC11_0/IC21_0/RTO23_1/MALE_0 69 68 67 P62/SCK5_0/ADTG_3/TX0_2/MOEX_0 P63/INT03_0/SIN5_1/RX0_2/MWEX_0 P0F/NMIX/CROUT_1/RTCCO_0/DTTI2X_0/DTTI2X_1/SUBOUT_0 72 71 70 P60/SIN5_0/TIOA2_2/INT15_1/MRDY_0 P61/SOT5_0/TIOB2_2/UHCONX 74 73 P81/UDP0 P80/UDM0 USBVCC 75 78 77 76 P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_0 VCC VSS 80 79 (Top View) P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_0 81 50 P22/SOT0_0/TIOB7_1/ZIN1_1 P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_0 82 49 P23/SCK0_0/TIOA7_1 P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_0 83 48 P1F/AN15/ADTG_5/FRCK0_1/MAD23_0 P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_0 84 47 P1E/AN14/RTS4_1/DTTI0X_1/MAD22_0 P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_0 85 46 P1D/AN13/CTS4_1/IC03_1/MAD21_0 P56/INT08_2/DTTI1X_0/MADATA06_0 86 45 P1C/AN12/SCK4_1/IC02_1/MAD20_0 P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_0 87 44 P1B/AN11/SOT4_1/IC01_1/MAD19_0 P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_0 88 43 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_0 P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_0 89 42 P19/AN09/SCK2_2/MAD17_0 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_0 90 41 P18/AN08/SOT2_2/MAD16_0 P34/FRCK0_0/TIOB4_1/TX0_1/MADATA11_0 91 40 AVSS P35/IC03_0/TIOB5_1/RX0_1/INT08_1/MADATA12_0 92 39 AVRH P36/IC02_0/SIN5_2/INT09_1/MADATA13_0 93 38 AVCC P37/IC01_0/SOT5_2/INT10_1/MADATA14_0 94 37 P17/AN07/SIN2_2/INT04_1/MAD15_0 P38/IC00_0/SCK5_2/INT11_1/MADATA15_0 95 36 P16/AN06/SCK0_1/MAD14_0 P39/DTTI0X_0/ADTG_2 96 35 P15/AN05/SOT0_1/IC03_2/MAD13_0 P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2 97 34 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_0 P3B/RTO01_0/TIOA1_1 98 33 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/IC01_2/MAD11_0 P3C/RTO02_0/TIOA2_1 99 32 P12/AN02/SOT1_1/TX1_2/IC00_2/MAD10_0 P3D/RTO03_0/TIOA3_1 100 31 P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/MAD09_0 27 28 29 30 PE3/X1 VSS VCC P10/AN00 24 25 26 MD0 PE0/MD1 PE2/X0 21 22 23 P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_0 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_0 P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_0 P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_0 18 19 20 P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_0 P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_0 15 16 17 INITX P47/X1A P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_0 12 13 14 VSS VCC C P46/X0A 9 10 11 P44/TIOA4_0/RTO14_1/MAD00_0 P45/TIOA5_0/RTO15_1/MAD01_0 7 8 P42/TIOA2_0/RTO12_1 6 P41/TIOA1_0/RTO11_1/INT13_1 P43/TIOA3_0/RTO13_1/ADTG_7 3 4 5 VCC P40/TIOA0_0/RTO10_1/INT12_1 1 2 P3F/RTO05_0/TIOA5_1 VSS P3E/RTO04_0/TIOA4_1 QFP - 100 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-08541 Rev. *D Page 12 of 117 CY9B510R Series LBC112 (TOP VIEW) 1 2 3 A VSS UDP0 B VCC VSS P52 C P50 P51 D P53 E 4 5 6 7 10 11 P0E P0B P07 VCC VSS P61 P0F P0C P08 TDO/ SWO TCK/ SWCLK VSS TDI VSS P60 P62 P0D P09 P05 VSS P20 P21 P54 P55 VSS P56 P63 P0A VSS P06 P23 AN15 P30 P31 P32 P33 Index P22 AN14 AN12 AN11 F P34 P35 P36 P39 AN13 AN10 AN09 AVRH G P37 P38 P3A P3D AN08 AN07 AN06 AVSS H P3B P3C P3E VSS P44 P4C AN05 VSS AN04 AN03 AVCC J VCC P3F VSS P40 P43 P49 P4D AN02 VSS AN01 AN00 K VCC VSS X1A INITX P42 P48 P4B P4E MD1 VSS VCC L VSS C X0A VSS P41 P45 P4A MD0 X0 X1 VSS UDM0 USBVCC 8 9 TMS/ TRSTX SWDIO PFBGA - 112 Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: 002-08541 Rev. *D Page 13 of 117 CY9B510R Series 4. List of Pin Functions List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. LQFP-100 Pin No FBGA-112 LQFP-120 QFP-100 1 B1 1 79 2 C1 2 80 3 C2 3 81 4 B3 4 82 5 D1 5 83 6 D2 6 84 7 D3 7 85 Document Number: 002-08541 Rev. *D Pin Name VCC P50 INT00_0 AIN0_2 SIN3_1 RTO10_0 (PPG10_0) MADATA00_0 P51 INT01_0 BIN0_2 SOT3_1 (SDA3_1) RTO11_0 (PPG10_0) MADATA01_0 P52 INT02_0 ZIN0_2 SCK3_1 (SCL3_1) RTO12_0 (PPG12_0) MADATA02_0 P53 SIN6_0 TIOA1_2 INT07_2 RTO13_0 (PPG12_0) MADATA03_0 P54 SOT6_0 (SDA6_0) TIOB1_2 RTO14_0 (PPG14_0) MADATA04_0 P55 SCK6_0 (SCL6_0) ADTG_1 RTO15_0 (PPG14_0) MADATA05_0 I/O circuit type Pin state type - E H E H E H E H E I E I Page 14 of 117 CY9B510R Series LQFP-100 8 Pin No FBGA-112 LQFP-120 D5 QFP-100 86 8 - - - - - 9 - - - 10 - - - 11 - - - 12 - - - 13 - 9 E1 14 87 - - 10 E2 14 - 15 88 - - Document Number: 002-08541 Rev. *D 15 - Pin Name P56 INT08_2 DTTI1X_0 MADATA06_0 SIN1_0 (120pin only) P57 SOT1_0 (SDA1_0) MADATA07_0 P58 SCK1_0 (SCL1_0) AIN2_0 MADATA08_0 P59 SIN7_0 RX1_1 INT09_2 BIN2_0 MADATA09_0 P5A SOT7_0 (SDA7_0) TX1_1 ZIN2_0 MADATA10_0 P5B SCK7_0 (SCL7_0) MADATA11_0 P30 AIN0_0 TIOB0_1 INT03_2 MADATA07_0 (100pin only) MADATA12_0 (120pin only) P31 BIN0_0 TIOB1_1 SCK6_1 (SCL6_1) INT04_2 MADATA08_0 (100pin only) MADATA13_0 (120pin only) I/O circuit type Pin state type E H E I E I E H E I E I E H E H Page 15 of 117 CY9B510R Series LQFP-100 Pin No FBGA-112 LQFP-120 QFP-100 16 11 E3 89 - - 12 E4 16 - 17 90 - - 13 F1 17 - 18 91 - - 14 F2 18 - 19 92 - - 15 F3 19 - 20 93 - - 16 G1 20 - 21 94 - - Document Number: 002-08541 Rev. *D 21 - Pin Name P32 ZIN0_0 TIOB2_1 SOT6_1 (SDA6_1) INT05_2 MADATA09_0 (100pin only) MADATA14_0 (120pin only) P33 INT04_0 TIOB3_1 SIN6_1 ADTG_6 MADATA10_0 (100pin only) MADATA15_0 (120pin only) P34 FRCK0_0 TIOB4_1 TX0_1 MADATA11_0 (100pin only) MNALE_0 (120pin only) P35 IC03_0 TIOB5_1 RX0_1 INT08_1 MADATA12_0 (100pin only) MNCLE_0 (120pin only) P36 IC02_0 SIN5_2 INT09_1 MADATA13_0 (100pin only) MNWEX_0 (120pin only) P37 IC01_0 SOT5_2 (SDA5_2) INT10_1 MADATA14_0 (100pin only) MNREX_0 (120pin only) I/O circuit type Pin state type E H E H E I E H E H E H Page 16 of 117 CY9B510R Series LQFP-100 Pin No FBGA-112 LQFP-120 QFP-100 22 17 G2 95 - 18 F4 23 96 19 G3 24 97 - B2 - - 20 H1 25 98 21 H2 26 99 22 G4 27 100 23 H3 28 1 24 J2 29 2 25 26 L1 J1 30 31 3 4 27 J4 32 5 28 L5 33 6 29 K5 34 7 30 J5 35 8 Document Number: 002-08541 Rev. *D Pin Name P38 IC00_0 SCK5_2 (SCL5_2) INT11_1 MADATA15_0 (100pin only) P39 DTTI0X_0 ADTG_2 P3A RTO00_0 (PPG00_0) TIOA0_1 RTCCO_2 SUBOUT_2 VSS P3B RTO01_0 (PPG00_0) TIOA1_1 P3C RTO02_0 (PPG02_0) TIOA2_1 P3D RTO03_0 (PPG02_0) TIOA3_1 P3E RTO04_0 (PPG04_0) TIOA4_1 P3F RTO05_0 (PPG04_0) TIOA5_1 VSS VCC P40 TIOA0_0 RTO10_1 (PPG10_1) INT12_1 P41 TIOA1_0 RTO11_1 (PPG10_1) INT13_1 P42 TIOA2_0 RTO12_1 (PPG12_1) P43 TIOA3_0 RTO13_1 (PPG12_1) I/O circuit type Pin state type E H E I G I G I G I G I G I G I - G H G H G I G I Page 17 of 117 CY9B510R Series LQFP-100 Pin No FBGA-112 LQFP-120 QFP-100 - K2 J3 H4 - - 31 H5 36 9 32 L6 37 10 33 34 35 L2 L4 K1 38 39 40 11 12 13 36 L3 41 14 37 K3 42 15 38 K4 43 16 39 K6 44 17 40 J6 45 18 41 L7 46 19 42 K7 47 20 43 H6 48 21 Document Number: 002-08541 Rev. *D Pin Name ADTG_7 VSS VSS VSS P44 TIOA4_0 RTO14_1 (PPG14_1) MAD00_0 P45 TIOA5_0 RTO15_1 (PPG14_1) MAD01_0 C VSS VCC P46 X0A P47 X1A INITX P48 DTTI1X_1 INT14_1 SIN3_2 MAD02_0 P49 TIOB0_0 IC10_1 AIN0_1 SOT3_2 (SDA3_2) MAD03_0 P4A TIOB1_0 IC11_1 BIN0_1 SCK3_2 (SCL3_2) MAD04_0 P4B TIOB2_0 IC12_1 ZIN0_1 MAD05_0 P4C TIOB3_0 IC13_1 SCK7_1 (SCL7_1) AIN1_2 MAD06_0 I/O circuit type Pin state type - G I G I D M D N B C E H E I E I E I I* I Page 18 of 117 CY9B510R Series LQFP-100 Pin No FBGA-112 LQFP-120 QFP-100 44 J7 49 22 45 K8 50 23 - - 51 - - - 52 - - - 53 - - - 54 - - - 55 - 46 K9 56 24 47 L8 57 25 48 L9 58 26 49 L10 59 27 50 51 L11 K11 60 61 28 29 52 J11 62 30 53 J10 63 31 - K10 J9 - - Document Number: 002-08541 Rev. *D Pin Name P4D TIOB4_0 FRCK1_1 SOT7_1 (SDA7_1) BIN1_2 MAD07_0 P4E TIOB5_0 INT06_2 SIN7_1 ZIN1_2 MAD08_0 P70 TX0_0 TIOA4_2 P71 RX0_0 INT13_2 TIOB4_2 P72 SIN2_0 INT14_2 TIOA6_0 P73 SOT2_0 (SDA2_0) INT15_2 TIOB6_0 P74 SCK2_0 (SCL2_0) PE0 MD1 MD0 PE2 X0 PE3 X1 VSS VCC P10 AN00 P11 AN01 SIN1_1 INT02_1 RX1_2 FRCK0_2 MAD09_0 VSS VSS I/O circuit type Pin state type I* I I* H E I E H E H E H E I C P J D A A A B - F K F L - Page 19 of 117 CY9B510R Series LQFP-100 Pin No FBGA-112 LQFP-120 QFP-100 54 J8 64 32 55 H10 65 33 56 H9 66 34 57 H7 67 35 58 G10 68 36 59 G9 69 37 60 61 62 H11 F11 G11 70 71 72 38 39 40 63 G8 73 41 64 F10 74 42 65 F9 75 43 - H8 - - Document Number: 002-08541 Rev. *D Pin Name P12 AN02 SOT1_1 (SDA1_1) TX1_2 IC00_2 MAD10_0 P13 AN03 SCK1_1 (SCL1_1) RTCCO_1 SUBOUT_1 IC01_2 MAD11_0 P14 AN04 SIN0_1 INT03_1 IC02_2 MAD12_0 P15 AN05 SOT0_1 (SDA0_1) IC03_2 MAD13_0 P16 AN06 SCK0_1 (SCL0_1) MAD14_0 P17 AN07 SIN2_2 INT04_1 MAD15_0 AVCC AVRH AVSS P18 AN08 SOT2_2 (SDA2_2) MAD16_0 P19 AN09 SCK2_2 (SCL2_2) MAD17_0 P1A AN10 SIN4_1 INT05_1 IC00_1 MAD18_0 VSS I/O circuit type Pin state type F K F K F L F K F K F L F K F K F L - Page 20 of 117 CY9B510R Series LQFP-100 Pin No FBGA-112 LQFP-120 QFP-100 66 E11 76 44 67 E10 77 45 68 F8 78 46 69 E9 79 47 70 D11 80 48 - - 81 - - - 82 - - - 83 - - - 84 - - B10 C9 - - - - 85 - Document Number: 002-08541 Rev. *D Pin Name P1B AN11 SOT4_1 (SDA4_1) IC01_1 MAD19_0 P1C AN12 SCK4_1 (SCL4_1) IC02_1 MAD20_0 P1D AN13 CTS4_1 IC03_1 MAD21_0 P1E AN14 RTS4_1 DTTI0X_1 MAD22_0 P1F AN15 ADTG_5 FRCK0_1 MAD23_0 P28 TIOB6_2 ADTG_4 RTO05_1 (PPG04_1) P27 TIOA6_2 INT02_2 RTO04_1 (PPG04_1) P26 SCK2_1 (SCL2_1) RTO03_1 (PPG02_1) P25 TX1_0 SOT2_1 (SDA2_1) RTO02_1 (PPG02_1) VSS VSS P24 RX1_0 SIN2_1 INT01_2 RTO01_1 (PPG00_1) I/O circuit type Pin state type F K F K F K F K F K E I E H E I E I - E H Page 21 of 117 CY9B510R Series LQFP-100 71 Pin No FBGA-112 LQFP-120 D10 QFP-100 49 86 - - 72 E8 87 50 73 C11 88 51 74 C10 89 52 75 76 A11 A10 90 91 53 54 77 A9 92 55 78 B9 93 56 79 B11 94 57 80 A8 95 58 81 B8 96 59 82 C8 97 60 - D8 - - 83 D9 98 61 Document Number: 002-08541 Rev. *D - Pin Name P23 SCK0_0 (SCL0_0) TIOA7_1 RTO00_1 (PPG00_1) P22 SOT0_0 (SDA0_0) TIOB7_1 ZIN1_1 P21 SIN0_0 INT06_1 BIN1_1 P20 INT05_0 CROUT_0 AIN1_1 MAD24_0 VSS VCC P00 TRSTX MCSX7_0 P01 TCK SWCLK P02 TDI MCSX6_0 P03 TMS SWDIO P04 TDO SWO P05 TRACED0 TIOA5_2 SIN4_2 INT00_1 MCSX5_0 VSS P06 TRACED1 TIOB5_2 SOT4_2 (SDA4_2) INT01_1 AIN2_1 MCSX4_0 I/O circuit type Pin state type E I E I E H E H E E E E E E E E E E E F - E F Page 22 of 117 CY9B510R Series LQFP-100 Pin No FBGA-112 LQFP-120 QFP-100 84 A7 99 62 85 B7 100 63 86 C7 101 64 87 D7 102 65 88 A6 103 66 89 B6 104 67 90 C6 105 68 Document Number: 002-08541 Rev. *D Pin Name P07 TRACED2 ADTG_0 SCK4_2 (SCL4_2) BIN2_1 MCLKOUT_0 P08 TRACED3 TIOA0_2 CTS4_2 ZIN2_1 MCSX3_0 P09 TRACECLK TIOB0_2 RTS4_2 RTO20_1 (PPG20_1) MCSX2_0 P0A SIN4_0 INT00_2 FRCK1_0 FRCK2_0 RTO21_1 (PPG20_1) MCSX1_0 P0B SOT4_0 (SDA4_0) TIOB6_1 IC10_0 IC20_0 RTO22_1 (PPG22_1) MCSX0_0 P0C SCK4_0 (SCL4_0) TIOA6_1 IC11_0 IC21_0 RTO23_1 MALE_0 P0D RTS4_0 TIOA3_2 IC12_0 IC22_0 RTO24_1 (PPG24_1) MDQM0_0 I/O circuit type Pin state type E G E G E G I* H I* I I* I E I Page 23 of 117 CY9B510R Series LQFP-100 Pin No FBGA-112 LQFP-120 QFP-100 91 A5 106 69 - D4 C3 - - 92 B5 107 70 - - 108 - - - 109 - - - 110 - - - 111 - - - 112 - Document Number: 002-08541 Rev. *D Pin Name P0E CTS4_0 TIOB3_2 IC13_0 IC23_0 RTO25_1 (PPG24_1) MDQM1_0 VSS VSS P0F NMIX CROUT_1 RTCCO_0 SUBOUT_0 DTTI2X_0 DTTI2X_1 P68 SCK3_0 (SCL3_0) TIOB7_2 INT12_2 IC20_1 RTO25_0 (PPG24_0) P67 SOT3_0 (SDA3_0) TIOA7_2 IC21_1 RTO24_0 (PPG24_0) P66 SIN3_0 ADTG_8 INT11_2 IC22_1 RTO23_0 (PPG22_0) P65 TIOB7_0 SCK5_1 (SCL5_1) IC23_1 RTO22_0 (PPG22_0) P64 TIOA7_0 SOT5_1 (SDA5_1) INT10_2 FRCK2_1 RTO21_0 (PPG20_0) I/O circuit type Pin state type E I - E J G H G I G H G I G H Page 24 of 117 CY9B510R Series LQFP-100 93 Pin No FBGA-112 LQFP-120 D6 QFP-100 71 113 - - 94 C5 114 72 95 B4 115 73 96 C4 116 74 97 A4 117 75 98 A3 118 76 99 A2 119 77 100 *: 5 V tolerant I/O A1 120 78 Document Number: 002-08541 Rev. *D - Pin Name P63 INT03_0 SIN5_1 RX0_2 MWEX_0 RTO20_0 (PPG20_0) P62 SCK5_0 (SCL5_0) ADTG_3 TX0_2 MOEX_0 P61 SOT5_0 (SDA5_0) TIOB2_2 UHCONX P60 SIN5_0 TIOA2_2 INT15_1 MRDY_0 USBVCC P80 UDM0 P81 UDP0 VSS I/O circuit type Pin state type G H E I E I I* H H O H O - Page 25 of 117 CY9B510R Series List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Module ADC Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Pin name ADTG_0 ADTG_1 ADTG_2 ADTG_3 ADTG_4 ADTG_5 ADTG_6 ADTG_7 ADTG_8 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 TIOA0_0 TIOA0_1 TIOA0_2 TIOB0_0 TIOB0_1 TIOB0_2 TIOA1_0 TIOA1_1 TIOA1_2 TIOB1_0 TIOB1_1 TIOB1_2 TIOA2_0 TIOA2_1 TIOA2_2 TIOB2_0 TIOB2_1 TIOB2_2 TIOA3_0 TIOA3_1 TIOA3_2 TIOB3_0 TIOB3_1 TIOB3_2 Document Number: 002-08541 Rev. *D Function A/D converter external trigger input pin A/D converter analog input pin. ANxx describes ADC ch.xx. Base timer ch.0 TIOA pin Base timer ch.0 TIOB pin Base timer ch.1 TIOA pin Base timer ch.1 TIOB pin Base timer ch.2 TIOA pin Base timer ch.2 TIOB pin Base timer ch.3 TIOA pin Base timer ch.3 TIOB pin LQFP100 84 7 18 94 70 12 30 52 53 54 55 56 57 58 59 63 64 65 66 67 68 69 70 27 19 85 40 9 86 28 20 5 41 10 6 29 21 96 42 11 95 30 22 90 43 12 91 Pin No FBGA112 A7 D3 F4 C5 D11 E4 J5 J11 J10 J8 H10 H9 H7 G10 G9 G8 F10 F9 E11 E10 F8 E9 D11 J4 G3 B7 J6 E1 C7 L5 H1 D1 L7 E2 D2 K5 H2 C4 K7 E3 B4 J5 G4 C6 H6 E4 A5 LQFP120 99 7 23 114 81 80 17 35 110 62 63 64 65 66 67 68 69 73 74 75 76 77 78 79 80 32 24 100 45 14 101 33 25 5 46 15 6 34 26 116 47 16 115 35 27 105 48 17 106 QFP100 62 85 96 72 48 90 8 30 31 32 33 34 35 36 37 41 42 43 44 45 46 47 48 5 97 63 18 87 64 6 98 83 19 88 84 7 99 74 20 89 73 8 100 68 21 90 69 Page 26 of 117 CY9B510R Series Module Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 CAN 0 CAN 1 Pin name TIOA4_0 TIOA4_1 TIOA4_2 TIOB4_0 TIOB4_1 TIOB4_2 TIOA5_0 TIOA5_1 TIOA5_2 TIOB5_0 TIOB5_1 TIOB5_2 TIOA6_0 TIOA6_1 TIOA6_2 TIOB6_0 TIOB6_1 TIOB6_2 TIOA7_0 TIOA7_1 TIOA7_2 TIOB7_0 TIOB7_1 TIOB7_2 TX0_0 TX0_1 TX0_2 RX0_0 RX0_1 RX0_2 TX1_0 TX1_1 TX1_2 RX1_0 RX1_1 RX1_2 SWCLK SWDIO Debugger SWO TCK TDI TDO TMS TRACECLK TRACED0 TRACED1 TRACED2 TRACED3 TRSTX Document Number: 002-08541 Rev. *D Function Base timer ch.4 TIOA pin Base timer ch.4 TIOB pin Base timer ch.5 TIOA pin Base timer ch.5 TIOB pin Base timer ch.6 TIOA pin Base timer ch.6 TIOB pin Base timer ch.7 TIOA pin Base timer ch.7 TIOB pin CAN interface ch.0 TX output pin CAN interface ch.0 RX output pin CAN interface ch.1 TX output pin CAN interface ch.1 RX output pin Serial wire debug interface clock input pin Serial wire debug interface data input / output pin Serial wire viewer output pin JTAG test clock input pin JTAG test data input pin JTAG debug data output pin JTAG test mode state input/output pin Trace CLK output pin of ETM Trace data output pin of ETM JTAG test reset Input pin Pin No LQFP100 31 23 44 13 32 24 82 45 14 83 89 88 71 72 13 94 14 93 54 53 78 FBGA112 H5 H3 J7 F1 L6 J2 C8 K8 F2 D9 B6 A6 D10 E8 F1 C5 F2 D6 J8 J10 B9 LQFP120 36 28 51 49 18 52 37 29 97 50 19 98 53 104 82 54 103 81 112 86 109 111 87 108 51 18 114 52 19 113 84 12 64 85 11 63 93 QFP100 9 1 22 91 10 2 60 23 92 61 67 66 49 50 91 72 92 71 32 31 56 80 A8 95 58 81 78 79 81 80 86 82 83 84 85 77 B8 B9 B11 B8 A8 C7 C8 D9 A7 B7 A9 96 93 94 96 95 101 97 98 99 100 92 59 56 57 59 58 64 60 61 62 63 55 Page 27 of 117 CY9B510R Series Module Pin name External Bus MAD00_0 MAD01_0 MAD02_0 MAD03_0 MAD04_0 MAD05_0 MAD06_0 MAD07_0 MAD08_0 MAD09_0 MAD10_0 MAD11_0 MAD12_0 MAD13_0 MAD14_0 MAD15_0 MAD16_0 MAD17_0 MAD18_0 MAD19_0 MAD20_0 MAD21_0 MAD22_0 MAD23_0 MAD24_0 MCSX0_0 MCSX1_0 MCSX2_0 MCSX3_0 MCSX4_0 MCSX5_0 MCSX6_0 MCSX7_0 Document Number: 002-08541 Rev. *D Function External bus interface address bus External bus interface chip select output pin LQFP100 31 32 39 40 41 42 43 44 45 53 54 55 56 57 58 59 63 64 65 66 67 68 69 70 74 88 87 86 85 83 82 79 77 Pin No FBGA112 H5 L6 K6 J6 L7 K7 H6 J7 K8 J10 J8 H10 H9 H7 G10 G9 G8 F10 F9 E11 E10 F8 E9 D11 C10 A6 D7 C7 B7 D9 C8 B11 A9 LQFP120 36 37 44 45 46 47 48 49 50 63 64 65 66 67 68 69 73 74 75 76 77 78 79 80 89 103 102 101 100 98 97 94 92 QFP100 9 10 17 18 19 20 21 22 23 31 32 33 34 35 36 37 41 42 43 44 45 46 47 48 52 66 65 64 63 61 60 57 55 Page 28 of 117 CY9B510R Series Module External Bus Pin name MADATA0_0 MADATA1_0 MADATA2_0 MADATA3_0 MADATA4_0 MADATA5_0 MADATA6_0 MADATA7_0 MADATA8_0 MADATA9_0 MADATA10_0 MADATA11_0 MADATA12_0 MADATA13_0 MADATA14_0 MADATA15_0 MDQM0_0 MDQM1_0 MALE_0 MRDY_0 MCLKOUT_0 MNALE_0 MNCLE_0 MNREX_0 MNWEX_0 MOEX_0 MWEX_0 Document Number: 002-08541 Rev. *D Function External bus interface data bus (Address / data multiplex bus) External bus interface byte mask signal output pin External bus interface Address Latch enable output signal for multiplex External bus interface external RDY input signal External bus interface external clock output pin External bus interface ALE signal to control NAND Flash output pin External bus interface CLE signal to control NAND Flash output pin External bus interface read enable signal to control NAND Flash External bus interface write enable signal to control NAND Flash External bus interface read enable signal for SRAM External bus interface write enable signal for SRAM Pin No LQFP100 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 90 91 FBGA112 C1 C2 B3 D1 D2 D3 D5 E1 E2 E3 E4 F1 F2 F3 G1 G2 C6 A5 LQFP120 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 105 106 QFP100 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 68 69 89 B6 104 67 96 C4 116 74 84 A7 99 62 - - 18 - - - 19 - - - 21 - - - 20 - 94 C5 114 72 93 D6 113 71 Page 29 of 117 CY9B510R Series Module Pin name External Interrupt INT00_0 INT00_1 INT00_2 INT01_0 INT01_1 INT01_2 INT02_0 INT02_1 INT02_2 INT03_0 INT03_1 INT03_2 INT04_0 INT04_1 INT04_2 INT05_0 INT05_1 INT05_2 INT06_1 INT06_2 INT07_2 INT08_1 INT08_2 INT09_1 INT09_2 INT10_1 INT10_2 INT11_1 INT11_2 INT12_1 INT12_2 INT13_1 INT13_2 INT14_1 INT14_2 INT15_1 INT15_2 NMIX Document Number: 002-08541 Rev. *D Function External interrupt request 00 input pin External interrupt request 01 input pin External interrupt request 02 input pin External interrupt request 03 input pin External interrupt request 04 input pin External interrupt request 05 input pin External interrupt request 06 input pin External interrupt request 07 input pin External interrupt request 08 input pin External interrupt request 09 input pin External interrupt request 10 input pin External interrupt request 11 input pin External interrupt request 12 input pin External interrupt request 13 input pin External interrupt request 14 input pin External interrupt request 15 input pin Non-Maskable Interrupt input pin LQFP100 2 82 87 3 83 4 53 93 56 9 12 59 10 74 65 11 73 45 5 14 8 15 16 17 27 28 39 96 92 Pin No FBGA112 C1 C8 D7 C2 D9 B3 J10 D6 H9 E1 E4 G9 E2 C10 F9 E3 C11 K8 D1 F2 D5 F3 G1 G2 J4 L5 K6 C4 B5 LQFP120 2 97 102 3 98 85 4 63 82 113 66 14 17 69 15 89 75 16 88 50 5 19 8 20 11 21 112 22 110 32 108 33 52 44 53 116 54 107 QFP100 80 60 65 81 61 82 31 71 34 87 90 37 88 52 43 89 51 23 83 92 86 93 94 95 5 6 17 74 70 Page 30 of 117 CY9B510R Series Module Pin name GPIO P00 P01 P02 P03 P04 P05 P06 P07 P08 P09 P0A P0B P0C P0D P0E P0F P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P1A P1B P1C P1D P1E P1F P20 P21 P22 P23 P24 P25 P26 P27 P28 Document Number: 002-08541 Rev. *D Function General-purpose I/O port 0 General-purpose I/O port 1 General-purpose I/O port 2 LQFP100 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 52 53 54 55 56 57 58 59 63 64 65 66 67 68 69 70 74 73 72 71 - Pin No FBGA112 A9 B9 B11 A8 B8 C8 D9 A7 B7 C7 D7 A6 B6 C6 A5 B5 J11 J10 J8 H10 H9 H7 G10 G9 G8 F10 F9 E11 E10 F8 E9 D11 C10 C11 E8 D10 - LQFP120 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 62 63 64 65 66 67 68 69 73 74 75 76 77 78 79 80 89 88 87 86 85 84 83 82 81 QFP100 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 30 31 32 33 34 35 36 37 41 42 43 44 45 46 47 48 52 51 50 49 - Page 31 of 117 CY9B510R Series Module Pin name GPIO P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P3A P3B P3C P3D P3E P3F P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P4A P4B P4C P4D P4E P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P5A P5B Document Number: 002-08541 Rev. *D Function General-purpose I/O port 3 General-purpose I/O port 4 General-purpose I/O port 5 LQFP100 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 28 29 30 31 32 36 37 39 40 41 42 43 44 45 2 3 4 5 6 7 8 - Pin No FBGA112 E1 E2 E3 E4 F1 F2 F3 G1 G2 F4 G3 H1 H2 G4 H3 J2 J4 L5 K5 J5 H5 L6 L3 K3 K6 J6 L7 K7 H6 J7 K8 C1 C2 B3 D1 D2 D3 D5 - LQFP120 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 32 33 34 35 36 37 41 42 44 45 46 47 48 49 50 2 3 4 5 6 7 8 9 10 11 12 13 QFP100 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 5 6 7 8 9 10 14 15 17 18 19 20 21 22 23 80 81 82 83 84 85 86 - Page 32 of 117 CY9B510R Series Module GPIO Pin name P60 P61 P62 P63 P64 P65 P66 P67 P68 P70 P71 P72 P73 P74 P80 P81 PE0 PE2 PE3 SIN0_0 SIN0_1 SOT0_0 (SDA0_0) Multifunction Serial 0 SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) SIN1_0 SIN1_1 SOT1_0 (SDA1_0) Multifunction Serial 1 SOT1_1 (SDA1_1) SCK1_0 (SCL1_0) SCK1_1 (SCL1_1) Document Number: 002-08541 Rev. *D Function General-purpose I/O port 6 General-purpose I/O port 7 General-purpose I/O port 8 General-purpose I/O port E Multi-function serial interface ch.0 input pin Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SCL0 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 input pin Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation modes 4) and as SCL1 when it is used in an I2C (operation mode 4). Pin No LQFP100 96 95 94 93 98 99 46 48 49 73 56 FBGA112 C4 B4 C5 D6 A3 A2 K9 L9 L10 C11 H9 LQFP120 116 115 114 113 112 111 110 109 108 51 52 53 54 55 118 119 56 58 59 88 66 QFP100 74 73 72 71 76 77 24 26 27 51 34 72 E8 87 50 57 H7 67 35 71 D10 86 49 58 G10 68 36 53 J10 8 63 31 - - 9 - 54 J8 64 32 - - 10 - 55 H10 65 33 Page 33 of 117 CY9B510R Series Module Multifunction Serial 2 Multifunction Serial 3 Multifunction Serial 4 Pin name SIN2_0 SIN2_1 SIN2_2 SOT2_0 (SDA2_0) SOT2_1 (SDA2_1) SOT2_2 (SDA2_2) SCK2_0 (SCL2_0) SCK2_1 (SCL2_1) SCK2_2 (SCL2_2) SIN3_0 SIN3_1 SIN3_2 SOT3_0 (SDA3_0) SOT3_1 (SDA3_1) SOT3_2 (SDA3_2) SCK3_0 (SCL3_0) SCK3_1 (SCL3_1) SCK3_2 (SCL3_2) SIN4_0 SIN4_1 SIN4_2 SOT4_0 (SDA4_0) SOT4_1 (SDA4_1) SOT4_2 (SDA4_2) SCK4_0 (SCL4_0) SCK4_1 (SCL4_1) SCK4_2 (SCL4_2) RTS4_0 RTS4_1 RTS4_2 CTS4_0 CTS4_1 CTS4_2 Document Number: 002-08541 Rev. *D Function Multi-function serial interface ch.2 input pin Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a CSIO (operation modes 2) and as SCL2 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 input pin Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation modes 2) and as SCL3 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 input pin Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a CSIO (operation modes 2) and as SCL4 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.4 RTS output pin Multi-function serial interface ch.4 CTS input pin Pin No LQFP100 59 FBGA112 G9 LQFP120 53 85 69 QFP100 37 - - 54 - - - 84 - 63 G8 73 41 - - 55 - - - 83 - 64 F10 74 42 2 39 C1 K6 110 2 44 80 17 - - 109 - 3 C2 3 81 40 J6 45 18 - - 108 - 4 B3 4 82 41 L7 46 19 87 65 82 D7 F9 C8 102 75 97 65 43 60 88 A6 103 66 66 E11 76 44 83 D9 98 61 89 B6 104 67 67 E10 77 45 84 A7 99 62 90 69 86 91 68 85 C6 E9 C7 A5 F8 B7 105 79 101 106 78 100 68 47 64 69 46 63 Page 34 of 117 CY9B510R Series Module Multifunction Serial 5 Multifunction Serial 6 Pin name SIN5_0 SIN5_1 SIN5_2 SOT5_0 (SDA5_0) SOT5_1 (SDA5_1) SOT5_2 (SDA5_2) SCK5_0 (SCL5_0) SCK5_1 (SCL5_1) SCK5_2 (SCL5_2) SIN6_0 SIN6_1 SOT6_0 (SDA6_0) SOT6_1 (SDA6_1) SCK6_0 (SCL6_0) SCK6_1 (SCL6_1) SIN7_0 SIN7_1 SOT7_0 (SDA7_0) Multifunction Serial 7 SOT7_1 (SDA7_1) SCK7_0 (SCL7_0) SCK7_1 (SCL7_1) Document Number: 002-08541 Rev. *D Function Multi-function serial interface ch.5 input pin Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a CSIO (operation modes 2) and as SCL5 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 input pin Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a CSIO (operation modes 2) and as SCL6 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 input pin Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I2C (operation mode 4). Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a CSIO (operation modes 2) and as SCL7 when it is used in an I2C (operation mode 4). Pin No LQFP100 96 93 15 FBGA112 C4 D6 F3 LQFP120 116 113 20 QFP100 74 93 93 95 B4 115 73 - - 112 - 16 G1 21 94 94 C5 114 72 - - 111 - 17 G2 22 95 5 12 D1 E4 5 17 83 90 6 D2 6 84 11 E3 16 89 7 D3 7 85 10 E2 15 88 45 K8 11 50 23 - - 12 - 44 J7 49 22 - - 13 - 43 H6 48 21 Page 35 of 117 CY9B510R Series Module Pin name Function DTTI0X_0 Input signal controlling wave form generator outputs RTO00 to RTO05 of Multi-function timer 0. DTTI0X_1 Multifunction Timer 0 FRCK0_0 FRCK0_1 FRCK0_2 IC00_0 IC00_1 IC00_2 IC01_0 IC01_1 IC01_2 IC02_0 IC02_1 IC02_2 IC03_0 IC03_1 IC03_2 RTO00_0 (PPG00_0) RTO00_1 (PPG00_1) RTO01_0 (PPG00_0) RTO01_1 (PPG00_1) RTO02_0 (PPG02_0) RTO02_1 (PPG02_1) RTO03_0 (PPG02_0) RTO03_1 (PPG02_1) RTO04_0 (PPG04_0) RTO04_1 (PPG04_1) RTO05_0 (PPG04_0) RTO05_1 (PPG04_1) Document Number: 002-08541 Rev. *D 16-bit free-run timer ch.0 external clock input pin 16-bit input capture ch.0 input pin of Multi-function timer 0. ICxx describes channel number. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. Pin No LQFP100 18 FBGA112 F4 LQFP120 23 QFP100 96 69 E9 79 47 13 70 53 17 65 54 16 66 55 15 67 56 14 68 57 F1 D11 J10 G2 F9 J8 G1 E11 H10 F3 E10 H9 F2 F8 H7 18 80 63 22 75 64 21 76 65 20 77 66 19 78 67 91 48 31 95 43 32 94 44 33 93 45 34 92 46 35 19 G3 24 97 - - 86 - 20 H1 25 98 - - 85 - 21 H2 26 99 - - 84 - 22 G4 27 100 - - 83 - 23 H3 28 1 - - 82 - 24 J2 29 2 - - 81 - Page 36 of 117 CY9B510R Series Module Pin name Function DTTI1X_0 Input signal controlling wave form generator outputs RTO10 to RTO15 of Multi-function timer 1. 16-bit free-run timer ch.1 external clock input pin DTTI1X_1 Multifunction Timer 1 FRCK1_0 FRCK1_1 IC10_0 IC10_1 IC11_0 IC11_1 IC12_0 IC12_1 IC13_0 IC13_1 RTO10_0 (PPG10_0) RTO10_1 (PPG10_1) RTO11_0 (PPG10_0) RTO11_1 (PPG10_1) RTO12_0 (PPG12_0) RTO12_1 (PPG12_1) RTO13_0 (PPG12_0) RTO13_1 (PPG12_1) RTO14_0 (PPG14_0) 16-bit input capture ch.1 input pin of Multi-function timer 1. ICxx describes channel number. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. RTO14_1 (PPG14_1) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. RTO15_0 (PPG14_0) RTO15_1 (PPG14_1) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. Document Number: 002-08541 Rev. *D Pin No LQFP100 8 FBGA112 D5 LQFP120 8 QFP100 86 39 K6 44 17 87 44 88 40 89 41 90 42 91 43 D7 J7 A6 J6 B6 L7 C6 K7 A5 H6 102 49 103 45 104 46 105 47 106 48 65 22 66 18 67 19 68 20 69 21 2 C1 2 80 27 J4 32 5 3 C2 3 81 28 L5 33 6 4 B3 4 82 29 K5 34 7 5 D1 5 83 30 J5 35 8 6 D2 6 84 31 H5 36 9 7 D3 7 85 32 L6 37 10 Page 37 of 117 CY9B510R Series Module Pin name Function DTTI2X_0 Input signal controlling wave form generator outputs RTO20 to RTO25 of Multi-function timer 2. 16-bit free-run timer ch.2 external clock input pin DTTI2X_1 Multifunction Timer 2 FRCK2_0 FRCK2_1 IC20_0 IC20_1 IC21_0 IC21_1 IC22_0 IC22_1 IC23_0 IC23_1 RTO20_0 (PPG20_0) RTO20_1 (PPG20_1) RTO21_0 (PPG20_0) RTO21_1 (PPG20_1) RTO22_0 (PPG22_0) RTO22_1 (PPG22_1) RTO23_0 (PPG22_0) RTO23_1 (PPG22_1) RTO24_0 (PPG24_0) RTO24_1 (PPG24_1) Quadrature Position/ Revolution Counter 0 Quadrature Position/ Revolution Counter 1 RTO25_0 (PPG24_0) RTO25_1 (PPG24_1) AIN0_0 AIN0_1 AIN0_2 BIN0_0 BIN0_1 BIN0_2 ZIN0_0 ZIN0_1 ZIN0_2 AIN1_1 AIN1_2 BIN1_1 BIN1_2 ZIN1_1 ZIN1_2 Document Number: 002-08541 Rev. *D 16-bit input capture ch.2 input pin of Multi-function timer 2. ICxx describes channel number. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG20 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG20 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG22 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG22 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG24 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG24 when it is used in PPG2 output modes. QPRC ch.0 AIN input pin QPRC ch.0 BIN input pin QPRC ch.0 ZIN input pin QPRC ch.1 AIN input pin QPRC ch.1 BIN input pin QPRC ch.1 ZIN input pin Pin No LQFP100 92 FBGA112 B5 LQFP120 107 QFP100 70 92 B5 107 70 87 88 89 90 91 - D7 A6 B6 C6 A5 - 102 112 103 108 104 109 105 110 106 111 65 66 67 68 69 - - - 113 - 86 C7 101 64 - - 112 - 87 D7 102 65 - - 111 - 88 A6 103 66 - - 110 - 89 B6 104 67 - - 109 - 90 C6 105 68 - - 108 - 91 A5 106 69 9 40 2 10 41 3 11 42 4 74 43 73 44 72 45 E1 J6 C1 E2 L7 C2 E3 K7 B3 C10 H6 C11 J7 E8 K8 14 45 2 15 46 3 16 47 4 89 48 88 49 87 50 87 18 80 88 19 81 89 20 82 52 21 51 22 50 23 Page 38 of 117 CY9B510R Series Module Quadrature Position/ Revolution Counter 2 Real-time clock USB Reset Pin name AIN2_0 AIN2_1 BIN2_0 BIN2_1 ZIN2_0 ZIN2_1 RTCCO_0 RTCCO_1 RTCCO_2 SUBOUT_0 SUBOUT_1 SUBOUT_2 UDM0 UDP0 UHCONX QPRC ch.2 BIN input pin QPRC ch.2 ZIN input pin 0.5 seconds pulse output pin of Real-time clock Sub clock output pin FBGA112 D9 A7 B7 B5 H10 G3 B5 H10 G3 A3 A2 B4 LQFP120 10 98 11 99 12 100 107 65 24 107 65 24 118 119 115 QFP100 61 62 63 70 33 97 70 33 97 76 77 73 38 K4 43 16 47 L8 57 25 46 K9 56 24 1 26 35 51 B1 J1 K1 K11 1 31 40 61 79 4 13 29 VCC VCC VCC VCC VCC Power supply Pin 76 A10 91 54 3.3V Power supply port for USB I/O GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin GND Pin 97 25 34 50 75 100 A4 B2 L1 K2 J3 H4 L4 L11 K10 J9 H8 B10 C9 A11 D8 D4 C3 A1 117 30 39 60 90 120 75 INITX Mode MD1 GND QPRC ch.2 AIN input pin Pin No LQFP100 83 84 85 92 55 19 92 55 19 98 99 95 USB device/host D – pin USB device/host D + pin USB external pull-up control pin External Reset Input pin. A reset is valid when INITX="L". Mode 0 pin. During normal operation, MD0="L" must be input. During serial programming to Flash memory, MD0="H" must be input. Mode 1 pin. During serial programming to Flash memory, MD1="L" must be input. Power supply Pin Power supply Pin Power supply Pin Power supply Pin MD0 Power Function USBVCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Document Number: 002-08541 Rev. *D 3 12 28 53 78 Page 39 of 117 CY9B510R Series Module Clock Analog Power Pin name X0 X0A X1 X1A CROUT_0 CROUT_1 AVCC AVRH Function Main clock (oscillation) input pin Sub clock (oscillation) input pin Main clock (oscillation) I/O pin Sub clock (oscillation) I/O pin Built-in high-speed CR-osc clock output port A/D converter analog power pin A/D converter analog reference voltage input pin Pin No LQFP100 48 36 49 37 74 92 60 FBGA112 L9 L3 L10 K3 C10 B5 H11 LQFP120 58 41 59 42 89 107 70 QFP100 26 14 27 15 52 70 38 61 F11 71 39 Analog AVSS A/D converter GND pin 62 G11 72 40 GND C pin C Power stabilization capacity pin 33 L2 38 11 Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: 002-08541 Rev. *D Page 40 of 117 CY9B510R Series 5. I/O Circuit Type Type A Circuit Remarks It is possible to select the main oscillation / GPIO function Pull-up When the main oscillation is selected. resistor P P − Oscillation feedback resistor: − With Standby mode control Digital output X1 Approximately 1 MΩ When the GPIO is selected. N Digital output R Pull-up resistor control Digital input − CMOS level output. − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor: − IOH = -4 mA, IOL = 4 mA − CMOS level hysteresis input − Pull-up resistor: Approximately 50 kΩ Standby mode Control Clock input Feedback resistor Standby mode Control Digital input Standby mode Control Pull-up resistor R P P Digital output N Digital output X0 Pull-up resistor control B Approximately 50 kΩ Pull-up resistor Digital input Document Number: 002-08541 Rev. *D Page 41 of 117 CY9B510R Series Type C Circuit Remarks Digital input − Open drain output − CMOS level hysteresis input Digital output N-ch It is possible to select the sub oscillation / GPIO function D Pull-up When the sub oscillation is selected. resistor − P P Digital output X1A Oscillation feedback resistor: Approximately 5 MΩ − With Standby mode control When the GPIO is selected. N Digital output R Pull-up resistor control Digital input − CMOS level output. − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor: − IOH = -4 mA, IOL= 4 mA Approximately 50 kΩ Standby mode Control Clock input Feedback resistor Standby mode Control Digital input Standby mode Control Pull-up resistor R P P Digital output N Digital output X0A Pull-up resistor control Document Number: 002-08541 Rev. *D Page 42 of 117 CY9B510R Series Type E Circuit P-ch Remarks P-ch − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor: Digital output Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − When this pin is used as an I2C pin, the digital output N-ch Digital output R − P-ch transistor is always off − +B input is available − CMOS level output − CMOS level hysteresis input − With input control − Analog input − With pull-up resistor control − With standby mode control − Pull-up resistor: − IOH = -4 mA, IOL = 4 mA − When this pin is used as an Pull-up resistor control Digital input Standby mode Control F P-ch P-ch Digital output Approximately 50 kΩ N-ch R Digital output I2C pin, the digital output − P-ch transistor is always off − +B input is available Pull-up resistor control Digital input Standby mode Control Analog input Input control Document Number: 002-08541 Rev. *D Page 43 of 117 CY9B510R Series Type G Circuit P-ch Remarks − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor: − IOH= -12 mA, IOL= 12 mA − +B input is available Approximately 50 kΩ P-ch Digital output N-ch Digital output R Pull-up resistor control Digital input Standby mode Control H It is possible to select the GPIO Digital output USB I/O / GPIO function. GPIO Digital input/output direction When the USB I/O is selected GPIO Digital input − GPIO Digital input circuit control UDP/Pxx Differential UDM/Pxx Full-speed, Low-speed control UDP output When the GPIO is selected. USB Full-speed/Low-speed control − CMOS level output UDP input − CMOS level hysteresis input − With standby mode control − IOH= -20.5 mA, Differential input USB/GPIO select IOL= 18.5 mA UDM input UDM output USB Digital input/output direction GPIO Digital input GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control Document Number: 002-08541 Rev. *D Page 44 of 117 CY9B510R Series Type I Circuit P-ch Remarks P-ch Digital output − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − 5 V tolerant − With standby mode control − IOH = -4 mA, IOL = 4 mA − Available to control of PZR registers. − N-ch Digital output R When this pin is used as an I2C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input Standby mode Control CMOS level hysteresis input J Mode input Document Number: 002-08541 Rev. *D Page 45 of 117 CY9B510R Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Document Number: 002-08541 Rev. *D Page 46 of 117 CY9B510R Series Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (FBGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Document Number: 002-08541 Rev. *D Page 47 of 117 CY9B510R Series Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. Document Number: 002-08541 Rev. *D Page 48 of 117 CY9B510R Series 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: 002-08541 Rev. *D Page 49 of 117 CY9B510R Series 7. Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin near this device. Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Using an external clock When using an external clock, the clock signal should be input to the X0, X0A pin only and the X1, X1A pin should be kept open.  Example of Using an External Clock Device X0(X0A) Open X1(X1A) Handling when using Multi function serial pin as I2C pin If it is using multi function serial pin as I2C pins, P-ch transistor of digital output is always disable. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to external I2C bus system with power OFF. Document Number: 002-08541 Rev. *D Page 50 of 117 CY9B510R Series C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μF would be recommended for this series. C Device CS VSS GND Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC = VCC and AVSS = VSS. Turning on: Turning off: VCC → USBVCC VCC → AVCC → AVRH AVRH → AVCC → VCC USBVCC → VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up function of 5 V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O. Document Number: 002-08541 Rev. *D Page 51 of 117 CY9B510R Series 8. Block Diagram MB9BF512N/R, MB9BF514N/R, MB9BF515N/R, MB9BF516N/R TRACED[3:0], TRACECLK SWJ-DP ETM TPIU ROM Table SRAM0 8/16/24/32Kbyte Cortex-M3 Core 144MHz(Max) I Multi-layer AHB (Max 144MHz) TRSTX,TCK, TDI,TMS TDO D MPU NVIC Sys AHB-APB Bridge: APB0(Max 72MHz) Dual-Timer Watchdog Timer (Software) Clock Reset Generator INITX Watchdog Timer (Hardware) SRAM1 8/16/24/32Kbyte MainFlash 128Kbyte/ 256Kbyte/ 384Kbyte/ 512Kbyte MainFlash I/F Trace Buffer (16Kbyte) Security WorkFlash 32Kbyte WorkFlash I/F USB 2.0 (Host/ Device) USBVCC PHY UDP0,UDM0 UHCONX DMAC 8ch. CSV CLK X0 X1 X0A X1A CROUT AVCC, AVSS, AVRH Main Osc Sub Osc PLL Source Clock CR 4MHz AHB-AHB Bridge CR 100kHz CAN TX0, RX0 CAN TX1, RX1 12-bit A/D Converter × 3 MAD[24:00] MADATA[15:00] Unit 0 External Bus I/F AN[15:00] MRDY Unit 1 ADTG[8:0] Unit 2 AIN[2:0] BIN[2:0] QPRC 3ch. ZIN[2:0] A/D Activation Compare 3ch. IC0[3:0] IC1[3:0] IC2[3:0] 16-bit Input Capture 4ch. FRCK[2:0] 16-bit Free-run Timer 3ch. USB Clock Ctrl AHB-APB Bridge : APB2 (Max 72MHz) TIOB[7:0] Base Timer 16-bit 8ch./ 32-bit 4ch. AHB-APB Bridge : APB1 (Max 72MHz) TIOA[7:0] CAN Prescaler 16-bit Output Compare 6ch. DTTI[2:0]X RTO0[5:0] RTO1[5:0] RTO2[5:0] LVD Ctrl IRQ-Monitor Multi-function Timer x 3 Power On Reset LVD Regulator C CRC Accelerator RTCCO SUBOUT Real-Time Clock Watch Counter External Interrupt Controller 16-pin + NMI INT[15:00] NMIX MODE-Ctrl GPIO Waveform Generator 3ch. 16-bit PPG 3ch. PLL MCSX[7:0], MALE, MOEX,MWEX, MNALE, MNCLE, MNWEX, MNREX, MDQM[1:0] MD[1:0] PIN-Function-Ctrl P0[F:0], P1[F:0], . . . Px[x:0] Multi-function Serial I/F 8ch. (with FIFO ch.4-ch.7) HW flow control(ch.4) SCK[7:0] SIN[7:0] SOT[7:0] CTS4 RTS4 9. Memory Size See "1 Product Lineup" of "Memory size" to confirm the memory size. Document Number: 002-08541 Rev. *D Page 52 of 117 CY9B510R Series 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF Reserved 0x4006_4000 0xFFFF_FFFF Reserved 0xE010_0000 0xE000_0000 Cortex-M3 Private Peripherals Reserved 0x7000_0000 External Device 0x6000_0000 Area Reserved 0x4400_0000 0x4200_0000 0x4000_0000 32Mbyte Bit band alias Peripherals Reserved 0x2400_0000 0x2200_0000 32Mbyte Bit band alias 0x4006_3000 CAN ch.1 0x4006_2000 CAN ch.0 0x4006_1000 Reserved 0x4006_0000 DMAC 0x4005_0000 Reserved 0x4004_0000 USB ch.0 0x4003_F000 EXT-bus I/F 0x4003_C000 Reserved 0x4003_B000 RTC 0x4003_A000 Watch Counter 0x4003_9000 CRC 0x4003_8000 MFS 0x4003_7000 CAN Prescaler 0x4003_6000 USB Clock Ctrl 0x4003_5000 LVD Ctrl 0x4003_4000 Reserved 0x4003_3000 GPIO 0x4003_2000 Reserved 0x4003_1000 Int-Req. Read 0x4003_0000 EXTI 0x4002_F000 Reserved 0x4002_E000 CR Trim 0x4002_8000 Reserved 0x4002_7000 A/DC 0x4002_6000 QPRC Base Timer 0x200E_1000 Reserved 0x4002_5000 0x200E_0000 WorkFlash I/F 0x4002_4000 PPG 0x200C_0000 WorkFlash 0x4002_3000 Reserved 0x2008_0000 Reserved 0x4002_2000 MFT unit2 0x2000_0000 SRAM1 0x4002_1000 MFT unit1 SRAM0 0x4002_0000 MFT unit0 0x4001_6000 Reserved 0x4001_5000 Dual Timer 0x4001_3000 Reserved See the next page "Memory Map (2), (3)" 0x1FFF_0000 for the memory size 0x0010_2000 details. 0x0010_0000 Reserved Security/CR Trim MainFlash 0x0000_0000 Document Number: 002-08541 Rev. *D 0x4001_2000 SW WDT 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_1000 Reserved 0x4000_0000 MainFlash I/F Page 53 of 117 CY9B510R Series Memory Map (2) CY9BF516N/R CY9BF515N/R 0x200E_0000 0x200E_0000 384Kbyte SA0-3 (8KBx4) MainFlash 0x200C_8000 32Kbyte 0x2000_8000 Reserved WorkFlash 0x200C_0000 32Kbyte 0x200C_8000 WorkFlash Reserved SA0-3 (8KBx4) 0x200C_0000 Reserved Reserved 0x2000_6000 SRAM1 32Kbyte SRAM1 24Kbyte 0x2000_0000 0x2000_0000 SRAM0 SRAM0 24Kbyte 32Kbyte 0x1FFF_A000 0x1FFF_8000 Reserved Reserved 0x0010_2000 0x0010_2000 0x0010_1000 CR trimming 0x0010_1000 CR trimming 0x0010_0000 Security 0x0010_0000 Security Reserved 0x0008_0000 Reserved 0x0006_0000 SA10-15 (64KBx6) 512Kbyte MainFlash SA10-13 (64KBx4) SA8-9 (48KBx2) SA8-9 (48KBx2) 0x0000_0000 SA4-7 (8KBx4) 0x0000_0000 SA4-7 (8KBx4) See "CY9B510R/410R/310R/110R Series Flash programming Manual" for sector structure of Flash. Document Number: 002-08541 Rev. *D Page 54 of 117 CY9B510R Series Memory Map (3) CY9BF514N/R CY9BF512N/R 0x200E_0000 0x200E_0000 128Kbyte MainFlash 0x200C_8000 32Kbyte Reserved WorkFlash 32Kbyte 0x200C_8000 WorkFlash Reserved SA0-3 (8KBx4) SA0-3 (8KBx4) 0x200C_0000 0x200C_0000 Reserved Reserved 0x2000_4000 0x2000_0000 0x1FFF_C000 0x2000_2000 SRAM1 16Kbyte 0x2000_0000 SRAM0 16Kbyte 0x1FFF_E000 SRAM1 8Kbyte SRAM0 8Kbyte Reserved Reserved 0x0010_2000 0x0010_2000 0x0010_1000 CR trimming 0x0010_1000 CR trimming 0x0010_0000 Security 0x0010_0000 Security Reserved Reserved 0x0004_0000 SA10-11 (64KBx2) SA4-7 (8KBx4) 256Kbyte 0x0000_0000 MainFlash SA8-9 (48KBx2) 0x0002_0000 SA8-9 (48KBx2) 0x0000_0000 SA4-7 (8KBx4) See "CY9B510R/410R/310R/110R Series Flash programming Manual" for sector structure of Flash. Document Number: 002-08541 Rev. *D Page 55 of 117 CY9B510R Series Peripheral Address Map Start address End address 0x4000_0000 0x4000_1000 0x4001_0000 0x4001_1000 0x4001_2000 0x4001_3000 0x4001_5000 0x4001_6000 0x4002_0000 0x4002_1000 0x4002_2000 0x4002_4000 0x4002_5000 0x4002_6000 0x4002_7000 0x4002_8000 0x4002_E000 0x4002_F000 0x4003_0000 0x4003_1000 0x4003_2000 0x4003_3000 0x4003_4000 0x4003_5000 0x4003_6000 0x4003_7000 0x4003_8000 0x4003_9000 0x4003_A000 0x4003_B000 0x4003_C000 0x4003_F000 0x4004_0000 0x4005_0000 0x4006_0000 0x4006_1000 0x4006_2000 0x4006_3000 0x4006_4000 0x200E_0000 0x4000_0FFF 0x4000_FFFF 0x4001_0FFF 0x4001_1FFF 0x4001_2FFF 0x4001_4FFF 0x4001_5FFF 0x4001_FFFF 0x4002_0FFF 0x4002_1FFF 0x4002_3FFF 0x4002_4FFF 0x4002_5FFF 0x4002_6FFF 0x4002_7FFF 0x4002_DFFF 0x4002_EFFF 0x4002_FFFF 0x4003_0FFF 0x4003_1FFF 0x4003_2FFF 0x4003_3FFF 0x4003_4FFF 0x4003_5FFF 0x4003_6FFF 0x4003_7FFF 0x4003_8FFF 0x4003_9FFF 0x4003_AFFF 0x4003_BFFF 0x4003_EFFF 0x4003_FFFF 0x4004_FFFF 0x4005_FFFF 0x4006_0FFF 0x4006_1FFF 0x4006_2FFF 0x4006_3FFF 0x41FF_FFFF 0x200E_FFFF Document Number: 002-08541 Rev. *D Bus AHB APB0 APB1 APB2 AHB Peripherals MainFlash I/F register Reserved Clock/Reset Control Hardware Watchdog timer Software Watchdog timer Reserved Dual-Timer Reserved Multi-function timer unit0 Multi-function timer unit1 Multi-function timer unit2 PPG Base Timer Quadrature Position/Revolution Counter A/D Converter Reserved Internal CR trimming Reserved External Interrupt Controller Interrupt Request Batch-Read Function Reserved GPIO Reserved Low-Voltage Detector USB clock generator CAN prescaler Multi-function serial Interface CRC Watch Counter Real-time clock Reserved External Memory interface USB ch.0 Reserved DMAC register Reserved CAN ch.0 CAN ch.1 Reserved WorkFlash I/F register Page 56 of 117 CY9B510R Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings. ◼ INITX=0 This is the period when the INITX pin is the "L" level. ◼ INITX=1 This is the period when the INITX pin is the "H" level. ◼ SPL=0 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "0". ◼ SPL=1 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "1". ◼ Input enabled Indicates that the input function can be used. ◼ Internal input fixed at "0" This is the status that the input function cannot be used. Internal input is fixed at "L". ◼ Hi-Z Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state. ◼ Setting disabled Indicates that the setting is disabled. ◼ Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. ◼ Analog input is enabled Indicates that the analog input is enabled. ◼ Trace output Indicates that the trace function can be used. Document Number: 002-08541 Rev. *D Page 57 of 117 CY9B510R Series List of Pin Status Pin status type A Function group Power supply stable INITX=0 - INITX=1 - Setting disabled Setting disabled Main crystal oscillator input pin Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled C INITX input pin D Mode input pin G Device internal reset state Setting disabled Main crystal oscillator output pin F INITX input state GPIO selected B E Power-on reset or low-voltage detection state Power supply unstable - JTAG selected GPIO selected Trace selected External interrupt enabled selected GPIO selected, or other than above resource selected Trace selected GPIO selected, or other than above resource selected Hi-Z/ Internal input fixed at "0"/ or Input enable Pull-up/ Input enabled Input enabled Hi-Z Setting disabled Run mode or sleep mode state Power supply stable INITX=1 Maintain previous state Timer mode or sleep mode state Power supply stable SPL=0 INITX=1 SPL=1 Maintain previous state Hi-Z/ Internal input fixed at "0" Input enabled Input enabled Input enabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Hi-Z/ Internal input fixed at "0" Hi-Z/ Internal input fixed at "0" Maintain previous state Maintain previous state/ Hi-Z at oscillation stop*1/ Internal input fixed at "0" Maintain previous state/ Hi-Z at oscillation stop*1/ Internal input fixed at "0" Pull-up/ Input enabled Input enabled Pull-up/ Input enabled Setting disabled Pull-up/ Input enabled Input enabled Pull-up/ Input enabled Setting disabled Pull-up/ Input enabled Pull-up/ Input enabled Input enabled Input enabled Pull-up/ Input enabled Input enabled Maintain previous state Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Trace output Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Hi-Z/ Internal input fixed at "0" Setting disabled Setting disabled Setting disabled Trace output Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Document Number: 002-08541 Rev. *D Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Page 58 of 117 CY9B510R Series Pin status type H I J Function group External interrupt enabled selected GPIO selected, or other than above resource selected GPIO selected, resource selected NMIX selected GPIO selected, or other than above resource selected Power-on reset or low-voltage detection state Power supply unstable Setting disabled Device internal reset state Power supply stable INITX=0 - INITX=1 - Setting disabled Setting disabled Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Setting disabled Setting disabled Setting disabled Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Hi-Z Hi-Z/ Internal input fixed at "0"/ Analog input enabled Setting disabled Run mode or sleep mode state Power supply stable INITX=1 - Timer mode or sleep mode state Power supply stable SPL=0 INITX=1 SPL=1 Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Hi-Z/ Internal input fixed at "0" Maintain previous state Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Analog input selected Hi-Z Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled Hi-Z/ Internal input fixed at "0"/ Analog input enabled GPIO selected, or other than above resource selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Analog input selected K GPIO selected, or other than above resource selected External interrupt enabled selected L INITX input state Document Number: 002-08541 Rev. *D Hi-Z/ Internal input fixed at "0" Page 59 of 117 CY9B510R Series Pin status type Function group Power-on reset or low-voltage detection state Power supply unstable - INITX input state Device internal reset state Power supply stable INITX=0 - INITX=1 - Power supply stable INITX=1 - Timer mode or sleep mode state Power supply stable SPL=0 INITX=1 SPL=1 GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Sub crystal oscillator input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Sub crystal oscillator output pin Hi-Z/ Internal input fixed at "0"/ or Input enable Hi-Z/ Internal input fixed at "0" Hi-Z/ Internal input fixed at "0" Maintain previous state Maintain previous state/ Hi-Z at oscillation stop*2/ Internal input fixed at "0" Maintain previous state/ Hi-Z at oscillation stop*2/ Internal input fixed at "0" GPIO selected Hi-Z Hi-Z/ Input enabled Hi-Z/ Input enabled Maintain previous state Maintain previous state Hi-Z/ Internal input fixed at "0" Hi-Z at transmission/ Input enabled/ Internal input fixed at "0" at reception Hi-Z at transmission/ Input enabled/ Internal input fixed at "0" at reception M N Run mode or sleep mode state O USB I/O pin Setting disabled Setting disabled Setting disabled Maintain previous state Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z/ Input enabled P *1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, and Stop mode. *2: Oscillation is stopped at Stop mode. Document Number: 002-08541 Rev. *D Page 60 of 117 CY9B510R Series 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter Symbol voltage*1, *2 Power supply Power supply voltage (for USB)*1, * 3 Analog power supply voltage*1, *4 Analog reference voltage*1, *4 VCC USBVCC AVCC AVRH Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 Rating VSS - 0.5 Input voltage*1 VI VSS - 0.5 VSS - 0.5 Analog pin input voltage*1 VIA VSS - 0.5 Output voltage*1 VO VSS - 0.5 ICLAMP Σ[ICLAMP] -2 IOL - IOLAV - ∑IOL ∑IOLAV - IOH - IOHAV - ∑IOH ∑IOHAV PD TSTG - 55 Clamp maximum current Clamp total maximum current L level maximum output current*5 L level average output current*6 L level total maximum output current L level total average output current*7 H level maximum output current*5 H level average output current*6 H level total maximum output current H level total average output current*7 Power consumption Storage temperature Max VSS + 6.5 VSS + 6.5 VSS + 6.5 VSS + 6.5 VCC + 0.5 (≤ 6.5 V) USBVCC + 0.5 (≤ 6.5 V) VSS + 6.5 AVCC + 0.5 (≤ 6.5 V) VCC + 0.5 (≤ 6.5 V) +2 +20 10 20 39 4 12 18.5 100 50 - 10 - 20 - 39 -4 - 12 - 20.5 - 100 - 50 1000 + 150 Unit Remarks V V V V V Except for USB pin V USB pin V 5 V tolerant V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW °C *8 *8 4 mA type 12 mA type P80, P81 4 mA type 12 mA type P80, P81 4 mA type 12 mA type P80, P81 4 mA type 12 mA type P80, P81 *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: VCC must not drop below VSS - 0.5 V. *3: USBVCC must not drop below VSS - 0.5 V. *4: Ensure that the voltage does not to exceed VCC + 0.5 V, for example, when the power is turned on. *5: The maximum output current is the peak value for a single pin. *6: The average output is the average current for a single pin over a period of 100 ms. *7: The total average output current is the average current for all pins over a period of 100 ms. Document Number: 002-08541 Rev. *D Page 61 of 117 CY9B510R Series *8: • • • • • See "List of Pin Functions" and "I/O Circuit Type" about +B input available pin. Use within recommended operating conditions. Use at DC voltage (current) the +B input. The +B signal should always be applied a limiting resistance placed between the +B signal and the device. The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices. • Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. • The following is a recommended circuit example (I/O equivalent circuit). Protection Diode VCC VCC Limiting resistor P-ch Digital output +B input (0V to 16V) N-ch Digital input R AVCC Analog input WARNING: − Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-08541 Rev. *D Page 62 of 117 CY9B510R Series 12.2 Recommended Operating Conditions (VSS = AVSS = 0.0V) Parameter Conditions VCC - USBVCC - Unit AVCC AVRH - 2.7 2.7 CS - 1 10 μF LQI100 LQM120 TA When mounted on four-layer PCB - 40 + 85 °C PQH100 LBC112 TA - - 40 + 85 °C Power supply voltage for USB ch.0 Analog power supply voltage Analog reference voltage Smoothing capacitor Min 2.7 Value Max 5.5 3.6 (≤ VCC) 5.5 (≤ VCC) 5.5 AVCC Power supply voltage Operating temperature Symbol 3.0 2.7 Remarks V *1 V *2 V V AVCC = VCC For built-in 1.2 V regulator*3 *1: When P81/UDP0 and P80/UDM0 pin are used as USB (UDP0, UDM0). *2: When P81/UDP0 and P80/UDM0 pin are used as GPIO (P81, P80). *3: See "C Pin" in "7 Handling Devices" for the connection of the smoothing capacitor. *4: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. WARNING: − The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. − Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-08541 Rev. *D Page 63 of 117 CY9B510R Series 12.3 DC Characteristics 12.3.1 Current Rating (VCC = AVCC = USBVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions PLL Run mode Run mode current ICC High-speed CR Run mode VCC Sub Run mode Low-speed CR Run mode Sleep mode current ICCS PLL Sleep mode High-speed CR Sleep mode Sub Sleep mode Low-speed CR Sleep mode CPU: 144 MHz, Peripheral: 72 MHz, Main Flash 2 Wait TraceBuffer: ON FRWTR.RWT = 10 FSYNDN.SD = 000 FBFCR.BE = 1 CPU: 72 MHz, Peripheral: 72 MHz, Main Flash 0 Wait TraceBuffer: OFF FRWTR.RWT = 00 FSYNDN.SD = 000 FBFCR.BE = 0 Value Typ*3 Max*4 Unit Remarks 85 117 mA *1, *5 52 70 mA *1, *5 5 17 mA *1 1.3 14 mA *1, *6 1.3 14 mA *1 Peripheral: 72 MHz 28 43 mA *1, *5 Peripheral: 4 MHz*2 3 16 mA *1 Peripheral: 32 kHz 1 14 mA *1, *6 Peripheral: 100 kHz 1 14 mA *1 CPU/ Peripheral: 4 MHz*2 Main Flash 0 Wait FRWTR.RWT = 00 FSYNDN.SD = 000 CPU/ Peripheral: 32 kHz Main Flash 0 Wait FRWTR.RWT = 00 FSYNDN.SD = 000 CPU/ Peripheral: 100 kHz Main Flash 0 Wait FRWTR.RWT = 00 FSYNDN.SD = 000 *1: When all ports are fixed. *2: When setting it to 4 MHz by trimming. *3: TA=+25°C, VCC=5.5 V *4: TA=+85°C, VCC=5.5 V *5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) Document Number: 002-08541 Rev. *D Page 64 of 117 CY9B510R Series Parameter Symbol Pin name Main Timer mode Timer mode current ICCT Sub Timer mode VCC Stop mode current Value Typ*2 Max*2 Conditions ICCH Stop mode TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off TA = + 25°C, When LVD is off TA = + 85°C, When LVD is off Unit Remarks 3.2 6 mA *1, *3 - 15 mA *1, *3 0.9 3 mA *1, *4 - 12 mA *1, *4 0.8 3 mA *1 - 12 mA *1 *1: When all ports are fixed. *2: VCC=5.5 V *3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit) Low-Voltage Detection Current (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Low voltage detection circuit (LVD) power supply current ICCLVD VCC At operation for interrupt VCC = 5.5 V Typ Value 4 Max 7 Unit Remarks μA At not detect Flash Memory Current (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Typ Value Max MainFlash 11.4 13.1 At Write/Erase ICCFLASH VCC WorkFlash 11.4 13.1 At Write/Erase *: The current at which to write or erase Flash memory, ICCFLASH is added to ICC. Flash memory write/erase current Unit Remarks mA * mA A/D Converter Current (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 85°C) Parameter Power supply current Reference power supply current Symbol ICCAD ICCAVRH Document Number: 002-08541 Rev. *D Pin name AVCC AVRH Conditions Typ Value Max Unit At 1unit operation 0.47 0.62 mA At stop 0.06 25 μA At 1unit operation AVRH=5.5 V 1.1 1.96 mA At stop 0.06 4 μA Remarks Page 65 of 117 CY9B510R Series 12.3.2 Pin Characteristics (VCC = USBVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol H level input voltage (hysteresis input) VIHS L level input voltage (hysteresis input) VILS Pin name CMOS hysteresis input pin, MD0, MD1 5 V tolerant input pin CMOS hysteresis input pin, MD0, MD1 5 V tolerant input pin 4 mA type H level output voltage VOH 12 mA type P80, P81 Document Number: 002-08541 Rev. *D Conditions Min Value Typ Max Unit - VCC × 0.8 - VCC + 0.3 V - VCC × 0.8 - VSS + 5.5 V - VSS - 0.3 - VCC × 0.2 V - VSS - 0.3 - VCC × 0.2 V VCC - 0.5 - VCC V VCC - 0.5 - VCC V USBVCC - 0.4 - USBVCC V VCC ≥ 4.5 V IOH = - 4 mA VCC < 4.5 V IOH = - 2 mA VCC ≥ 4.5 V IOH = - 12 mA VCC < 4.5 V IOH = - 8 mA USBVCC ≥ 4.5 V IOH = - 20.5 mA USBVCC < 4.5 V IOH = - 13.0 mA Remarks Page 66 of 117 CY9B510R Series Parameter Symbol Pin name 4 mA type L level output voltage VOL 12 mA type P80, P81 Input leak current Pull-up resistance value Input capacitance IIL - RPU Pull-up pin CIN Other than VCC, USBVCC, VSS, AVCC, AVSS, AVRH Document Number: 002-08541 Rev. *D Conditions Value Unit Min Typ Max VSS - 0.4 V VSS - 0.4 V VSS - 0.4 V - -5 - +5 μA VCC ≥ 4.5 V 25 50 100 VCC < 4.5 V 30 80 200 - - 5 15 VCC ≥ 4.5 V IOL = 4 mA VCC < 4.5 V IOL = 2 mA VCC ≥ 4.5 V IOL = 12 mA VCC < 4.5 V IOL = 8 mA USBVCC ≥ 4.5 V IOL = 18.5 mA USBVCC < 4.5 V IOL = 10.5 mA Remarks kΩ pF Page 67 of 117 CY9B510R Series 12.4 AC Characteristics 12.4.1 Main Clock Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Input frequency Input clock cycle Input clock pulse width Input clock rise time and fall time Internal operating clock*1 frequency Internal operating clock*1 cycle time Symbol Pin name fCH tCYLH X0 X1 Conditions Value Unit Min Max VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V PWH/tCYLH PWL/tCYLH 4 4 4 4 20.83 50 48 20 48 20 250 250 45 55 % - - 5 ns MHz MHz ns Remarks When crystal oscillator is connected When using external clock When using external clock tCF, tCR fCM - - - 144 MHz When using external clock When using external clock Master clock fCC fCP0 fCP1 fCP2 - - - 144 72 72 72 MHz MHz MHz MHz Base clock (HCLK/FCLK) APB0 bus clock*2 APB1 bus clock*2 APB2 bus clock*2 tCYCC tCYCP0 tCYCP1 tCYCP2 - - 6.94 13.8 13.8 13.8 - ns ns ns ns Base clock (HCLK/FCLK) APB0 bus clock*2 APB1 bus clock*2 APB2 bus clock*2 - *1: For more information about each internal operating clock, see CHAPTER 2-1: Clock in FM3 Family PERIPHERAL MANUAL. *2: For about each APB bus which each peripheral is connected to, see 8 Block Diagram in this data sheet. X0 Document Number: 002-08541 Rev. *D Page 68 of 117 CY9B510R Series 12.4.2 Sub Clock Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Input frequency 1/ tCYLL Input clock cycle Input clock pulse width tCYLL Pin name X0A X1A - Conditions Value Unit Remarks 100 kHz kHz When crystal oscillator is connected When using external clock - 31.25 μs When using external clock - 55 % When using external clock Min Typ Max - 32 32.768 - PWH/tCYLL PWL/tCYLL 10 45 X0A 12.4.3 Internal CR Oscillation Characteristics High-speed Internal CR Parameter Clock frequency Frequency stability time Symbol fCRH Conditions Min (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Value Unit Remarks Typ Max TA = + 25°C 3.96 4 4.04 TA = 0°C to + 70°C 3.84 4 4.16 TA = - 40°C to + 85°C TA = - 40°C to + 85°C 3.8 3 4 4 4.2 5 - - - 90 tCRWT MHz When trimming*1 When not trimming μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming. *2: Frequency stable time is time to stable of the frequency of the High-speed CR clock after the trim value is set. After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock. Low-speed Internal CR (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions Clock frequency fCRL - Document Number: 002-08541 Rev. *D Value Min Typ Max 50 100 150 Unit Remarks kHz Page 69 of 117 CY9B510R Series 12.4.4 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Value Symbol Min Typ Max PLL oscillation stabilization wait time*1 tLOCK 100 (LOCK UP time) PLL input clock frequency fPLLI 4 16 PLL multiple rate 13 75 PLL macro oscillation clock frequency fPLLO 200 300 Main PLL clock frequency*2 fCLKPLL 144 USB clock frequency*3 fCLKSPLL 48 *1: Time from when the PLL starts operating until the oscillation stabilizes. Unit Remarks μs MHz multiple MHz MHz MHz After the M frequency division *2: For more information about Main PLL clock (CLKPLL), see CHAPTER 2-1: Clock in FM3 Family PERIPHERAL MANUAL. *3: For more information about USB clock, see CHAPTER 2-2: USB Clock Generation in FM3 Family PERIPHERAL MANUAL Communication Macro Part. 12.4.5 Operating Conditions of Main PLL (In the case of using high-speed internal CR) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Value Symbol Min Typ Max PLL oscillation stabilization wait time*1 tLOCK 100 (LOCK UP time) PLL input clock frequency fPLLI 3.8 4 4.2 PLL multiple rate 50 71 PLL macro oscillation clock frequency fPLLO 190 300 Main PLL clock frequency*2 fCLKPLL 144 *1: Time from when the PLL starts operating until the oscillation stabilizes. Unit Remarks μs MHz multiple MHz MHz *2: For more information about Main PLL clock (CLKPLL), see CHAPTER 2-1: Clock in FM3 Family PERIPHERAL MANUAL. When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. Main PLL connection Main clock (CLKMO) High-speed CR clock (CLKHC) K divider PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider USB PLL connection Main clock (CLKMO) K divider PLL input clock PLL macro oscillation clock USB PLL M divider USB clock N divider Document Number: 002-08541 Rev. *D Page 70 of 117 CY9B510R Series 12.4.6 Reset Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Reset input time tINITX INITX - 12.4.7 Value Min Max 500 - Unit Remarks ns Power-on Reset Timing (VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Power supply shut down time tOFF Pin name Value Conditions - Min Typ Max 50 - - Unit ms Remarks *1 Power ramp rate dV/dt Vcc: 0.2 V to 2.70 V 0.8 1000 mV/μs *2 VCC Time until releasing tPRT 0.57 0.76 ms Power-on reset *1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met. *2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>50 ms). Note: − If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per “12. 4. 6.Reset Input Characteristics”. 2.7V VCC VDH 0.2V dV/dt 0.2V tPRT Internal RST CPU Operation RST Active 0.2V tOFF release start Glossary VDH: detection voltage of Low Voltage detection reset. See “12.7. Low-voltage Detection Characteristics” Document Number: 002-08541 Rev. *D Page 71 of 117 CY9B510R Series 12.4.8 External Bus Timing External bus clock output characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Output frequency tCYCLE MCLKOUT*1 VCC ≥ 4.5 V VCC < 4.5 V Value Min Max - 50*2 32*3 Unit MHz MHz *1: External bus clock (MCLKOUT) is divided clock of HCLK. For more information about setting of clock divider, see CHPATER 12: External Bus Interface in FM3 Family PERIPHERAL MANUAL. When external bus clock is not output, this characteristic does not give any effect on external bus operation. *2: When AHB bus clock frequency is more than 100MHz, the divider setting for MCLKOUT must be more than 4. *3: When AHB bus clock frequency is more than 64MHz, the divider setting for MCLKOUT must be more than 4. MCLKOUT External bus signal input/output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Signal input characteristics Signal output characteristics Symbol Conditions VIH VIL - VOH VOL Input signal VIH VIL VIH VIL Output signal VOH VOL VOH VOL Document Number: 002-08541 Rev. *D Value Unit 0.8 × VCC V 0.2 × VCC V 0.8 × VCC V 0.2 × VCC V Remarks Page 72 of 117 CY9B510R Series Separate Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter MOEX Min pulse width MCSX ↓ → Address output delay time MOEX ↑ → Address hold time MCSX ↓ → MOEX ↓ delay time MOEX ↑ → MCSX ↑ time MCSX ↓ → MDQM ↓ delay time Data set up → MOEX ↑ time MOEX ↑ → Data hold time MWEX Min pulse width MWEX ↑ → Address output delay time MCSX ↓ → MWEX ↓ delay time MWEX ↑ → MCSX ↑ delay time MCSX ↓→ MDQM ↓ delay time MCSX ↓→ Data output time MWEX ↑ → Data hold time Symbol Pin name tOEW MOEX tCSL – AV tOEH - AX tCSL - OEL tOEH - CSH tCSL - RDQML tDS - OE tDH - OE MCSX[7:0] MAD[24:0] MOEX MAD[24:0] MOEX MCSX[7:0] MCSX MDQM[1:0] MOEX MADATA[15:0] MOEX MADATA[15:0] tWEW MWEX tWEH - AX MWEX MAD[24:0] tCSL - WEL tWEH - CSH tCSL-WDQML tCSL - DV tWEH - DX MWEX MCSX[7:0] MCSX MDQM[1:0] MCSX MADATA[15:0] MWEX MADATA[15:0] Conditions VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V Min Value Max Unit MCLK×n-3 - -9 -12 MCLK×m-9 MCLK×m-12 20 38 +9 +12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 - 0 - ns MCLK×n-3 - ns 0 MCLK×m-9 MCLK×m-12 0 0 MCLK×n-9 MCLK×n-12 0 MCLK×n-9 MCLK×n-12 MCLK-9 MCLK-12 0 MCLK×m+9 MCLK×m+12 MCLK×n+9 MCLK×n+12 MCLK×m+9 MCLK×m+12 MCLK×n+9 MCLK×n+12 MCLK+9 MCLK+12 MCLK×m+9 MCLK×m+12 ns ns ns ns ns ns ns ns ns ns ns ns ns Note: − When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16) Document Number: 002-08541 Rev. *D Page 73 of 117 CY9B510R Series tCYCLE MCLK tOEH-CSH tWEH-CSH MCSX[7:0] tCSL-AV MAD[24:0] tOEH-AX Address tWEH-AX tCSL-AV Address tCSL-OEL MOEX tOEW tCSL-WDQML tCSL-RDQML MDQM[1:0] tCSL-WEL tWEW MWEX MADATA[15:0] tDS-OE tDH-OE RD tWEH-DX WD Invalid tCSL-DV Document Number: 002-08541 Rev. *D Page 74 of 117 CY9B510R Series Separate Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Address delay time tAV MCLK MAD[24:0] VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V tCSL MCLK MCSX[7:0] MCSX delay time tCSH tREL MCLK MOEX MOEX delay time tREH Data set up → MCLK ↑ time MCLK ↑ → Data hold time MCLK MADATA[15:0] MCLK MADATA[15:0] tDS tDH tWEL MCLK MWEX MWEX delay time tWEH MDQM[1:0] delay time MCLK ↑ → Data output time MCLK ↑ → Data hold time tDQML MCLK MDQM[1:0] tDQMH MCLK, MADATA[15:0] MCLK MADATA[15:0] tODS tOD Min Value Max 9 12 9 12 9 12 9 12 9 12 1 1 1 1 1 Unit ns ns ns ns ns 19 37 - ns 0 - ns 1 1 1 1 MCLK+1 1 9 12 9 12 9 12 9 12 MCLK+18 MCLK+24 18 24 ns ns ns ns ns ns Note: − When the external load capacitance = 30 pF. tCYCLE MCLK tCSL tCSH MCSX[7:0] tAV tAV Address MAD[24:0] Address tREL tREH tDQML tDQMH MOEX tDQML tDQMH tWEL tWEH MDQM[1:0] MWEX MADATA[15:0] tDS tDH RD tOD WD Invalid tODS Document Number: 002-08541 Rev. *D Page 75 of 117 CY9B510R Series Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Multiplexed address delay time Multiplexed address hold time Symbol tALE-CHMADV tCHMADH Pin name Conditions MALE MADATA[15:0] VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V Min 0 MCLK×n+0 MCLK×n+0 Value Max 10 20 MCLK×n+10 MCLK×n+20 Unit ns ns Note: − When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16) MCLK MCSX[7:0] MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] Document Number: 002-08541 Rev. *D Page 76 of 117 CY9B510R Series Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol tCHAL MALE delay time tCHAH MCLK ↑ → Multiplexed Address delay time tCHMADV MCLK ↑ → Multiplexed Data output time tCHMADX Pin name Conditions MCLK ALE VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V MCLK MADATA[15:0] VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V Min 1 1 Value Max 9 12 9 12 Unit Remarks ns ns ns ns 1 tOD ns 1 tOD ns Note: − When the external load capacitance = 30 pF. MCLK MCSX[7:0] MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] Document Number: 002-08541 Rev. *D Page 77 of 117 CY9B510R Series NAND Flash Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = -40°C to +85°C) Parameter MNREX Min pulse width Data setup → MNREX ↑ time MNREX ↑ → Data hold time MNALE ↑ → MNWEX delay time MNALE ↓ → MNWEX delay time MNCLE ↑ → MNWEX delay time MNWEX ↑ → MNCLE delay time MNWEX Min pulse width MNWEX ↓ → Data delay time MNWEX ↑ → Data hold time Symbol Pin name tNREW MNREX tDS – NRE tDH – NRE tALEH - NWEL tALEL - NWEL tCLEH - NWEL tNWEH - CLEL tNWEW tNWEL – DV tNWEH – DX MNREX MADATA[15:0] MNREX MADATA[15:0] MNALE MNWEX MNALE MNWEX MNCLE MNWEX MNCLE MNWEX MNWEX MNWEX MADATA[15:0] MNWEX MADATA[15:0] Conditions VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V Value Unit Min Max MCLK×n-3 - ns 20 38 - ns 0 - ns MCLK×m-9 MCLK×m-12 MCLK×m-9 MCLK×m-12 MCLK×m-9 MCLK×m-12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 MCLK×m+9 MCLK×m+12 0 MCLK×n-3 - -9 -12 +9 +12 MCLK×m+9 MCLK×m+12 0 ns ns ns ns ns ns ns Note: − When the external load capacitance = 30 pF. (m=0 to 15, n=1 to 16) NAND Flash Read MCL K MNREX MADATA[15:0] Document Number: 002-08541 Rev. *D Read Page 78 of 117 CY9B510R Series NAND Flash Address Write MCL K MNA L E MNC L E MNW E X MADATA[15:0] Write NAND Flash Command Write MCLK MNALE MNCLE MNWEX MADATA[15:0] Document Number: 002-08541 Rev. *D Write Page 79 of 117 CY9B510R Series External Ready Input Timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions MCLK ↑ MRDY input setup time tRDYI MCLK MRDY VCC ≥ 4.5 V 19 VCC < 4.5 V 37 Min Value Max - Unit Remarks ns When RDY is input ··· MCLK Over 2cycle Original MOEX MWEX tRDYI MRDY When RDY is released MCLK ··· ··· 2 cycle Extended MOEX MWEX MRDY Document Number: 002-08541 Rev. *D tRDYI 0.5×VCC Page 80 of 117 CY9B510R Series 12.4.9 Base Timer Input Timing Timer input timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Input pulse width tTIWH tTIWL TIOAn/TIOBn (when using as ECK, TIN) - tTIWH Value Min 2tCYCP Max - Unit Remarks ns tTIWL ECK VIHS TIN VIHS VILS VILS Trigger input timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Input pulse width tTRGH tTRGL TIOAn/TIOBn (when using as TGIN) - tTRGH TGIN VIHS Min Value 2tCYCP Max - Unit Remarks ns tTRGL VIHS VILS VILS Note: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Base Timer is connected to, see 8 Block Diagram in this data sheet. Document Number: 002-08541 Rev. *D Page 81 of 117 CY9B510R Series 12.4.10 CSIO/UART Timing CSIO (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Baud rate - - - Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOVI SIN → SCK ↑ setup time tIVSHI SCK ↑ → SIN hold time tSHIXI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK ↓ → SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCK fall time SCK rise time tF tR SCKx SCKx SOTx SCKx SINx SCKx SINx SCKx SCKx SCKx SOTx SCKx SINx SCKx SINx SCKx SCKx VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max - 8 - 8 Mbps 4tCYCP - 4tCYCP - ns -30 +30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns Master mode Slave mode Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see 8 Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance = 30 pF. Document Number: 002-08541 Rev. *D Page 82 of 117 CY9B510R Series tSCYC VOH SCK VOL VOL tSLOVI VOH SOT VOL tIVSHI SIN tSHIXI VIH VIH VIL VIL Master mode tSLSH SCK tSHSL VIH VIH tF VIL VIL VIH tR tSLOVE SOT VOH VOL tIVSHE SIN VIH VIL tSHIXE VIH VIL Slave mode Document Number: 002-08541 Rev. *D Page 83 of 117 CY9B510R Series CSIO (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Baud rate - - - Serial clock cycle time tSCYC SCKx SCK ↑ → SOT delay time tSHOVI SCKx SOTx SCKx SINx SCKx SINx VCC < 4.5 V Master mode VCC ≥ 4.5 V Unit Min Max Min Max - 8 - 8 Mbps 4tCYCP - 4tCYCP - ns -30 +30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns SIN → SCK ↓ setup time tIVSLI SCK ↓ → SIN hold time tSLIXI Serial clock L pulse width tSLSH SCKx 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE - 50 - 30 ns SIN → SCK ↓ setup time tIVSLE 10 - 10 - ns SCK ↓ → SIN hold time tSLIXE 20 - 20 - ns SCK fall time tF SCKx SCKx SOTx SCKx SINx SCKx SINx SCKx - 5 - 5 ns SCK rise time tR SCKx - 5 - 5 ns Slave mode Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see 8 Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance = 30 pF. Document Number: 002-08541 Rev. *D Page 84 of 117 CY9B510R Series tSCYC SCK VOH VOH VOL tSHOVI VOH SOT VOL tIVSLI SIN tSLIXI VIH VIH VIL VIL Master mode tSHSL SCK tSLSH VIH VIH VIL tR tF VIL VIL tSHOVE SOT VOH VOL tIVSLE SIN VIH VIL tSLIXE VIH VIL Slave mode Document Number: 002-08541 Rev. *D Page 85 of 117 CY9B510R Series CSIO (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Baud rate - - - Serial clock cycle time tSCYC SCK ↑ → SOT delay time tSHOVI SIN → SCK ↓ setup time tIVSLI SCK ↓→ SIN hold time tSLIXI SOT → SCK ↓ delay time tSOVLI Serial clock L pulse width tSLSH SCKx SCKx SOTx SCKx SINx SCKx SINx SCKx SOTx SCKx Serial clock H pulse width tSHSL SCK ↑ → SOT delay time tSHOVE SIN → SCK ↓ setup time tIVSLE SCK ↓→ SIN hold time tSLIXE SCK fall time tF SCKx SCKx SOTx SCKx SINx SCKx SINx SCKx SCK rise time tR SCKx VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max - 8 - 8 Mbps 4tCYCP - 4tCYCP - ns -30 +30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 30 - 2tCYCP - 30 - ns 2tCYCP - 10 - 2tCYCP - 10 - ns tCYCP + 10 - tCYCP + 10 - ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 - 5 ns - 5 - 5 ns Master mode Slave mode Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see 8 Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance = 30 pF. Document Number: 002-08541 Rev. *D Page 86 of 117 CY9B510R Series tSCYC VOH SCK VOL SOT VOH VOL VOH VOL tIVSLI tSLIXI VIH VIL SIN VOL tSHOVI tSOVLI VIH VIL Master mode tSLSH SCK VIH VIL tF * SOT VIL tSHSL tR VOH VOL tIVSLE SIN VIH VIH tSHOVE VOH VOL tSLIXE VIH VIL VIH VIL Slave mode *: Changes when writing to TDR register Document Number: 002-08541 Rev. *D Page 87 of 117 CY9B510R Series CSIO (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Baud rate - - - Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOVI SIN → SCK ↑ setup time tIVSHI SCK ↑ → SIN hold time tSHIXI SOT → SCK ↑ delay time tSOVHI Serial clock L pulse width Serial clock H pulse width tSLSH tSHSL SCK ↓ → SOT delay time tSLOVE SIN → SCK ↑ setup time tIVSHE SCK ↑ → SIN hold time tSHIXE SCK fall time SCK rise time tF tR VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max - 8 - 8 Mbps SCKx 4tCYCP - 4tCYCP - ns SCKx SOTx -30 +30 - 20 + 20 ns 50 - 30 - ns 0 - 0 - ns 2tCYCP - 30 - 2tCYCP - 30 - ns 2tCYCP - 10 tCYCP + 10 - 2tCYCP - 10 tCYCP + 10 - ns ns - 50 - 30 ns 10 - 10 - ns 20 - 20 - ns - 5 5 - 5 5 ns ns SCKx SINx SCKx SINx SCKx SOTx SCKx SCKx SCKx SOTx SCKx SINx SCKx SINx SCKx SCKx Master mode Slave mode Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see 8 Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance = 30 pF. Document Number: 002-08541 Rev. *D Page 88 of 117 CY9B510R Series tSCYC VOH SCK tSOVHI tSLOVI VOH VOL SOT VOH VOL tSHIXI tIVSHI VIH VIL SIN VOH VOL VIH VIL Master mode tR tF tSHSL SCK VIH VIH VIL tSLSH VIL VIL tSLOVE VOH VOL SOT VOH VOL tIVSHE tSHIXE VIH VIL SIN VIH VIL Slave mode UART external clock input (EXT = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Serial clock L pulse width Serial clock H pulse width SCK fall time SCK rise time tSLSH tSHSL tF tR Conditions Min Max Unit CL = 30 pF tCYCP + 10 tCYCP + 10 - 5 5 ns ns ns ns tR tF tSHSL SCK Document Number: 002-08541 Rev. *D VIL Remarks VIH tSLSH VIH VIL VIL Page 89 of 117 CY9B510R Series 12.4.11 External Input Timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Min Value Max Unit A/D converter trigger input ADTG FRCKx - 2tCYCP* - ns ICxx Input pulse width tINH, tINL Remarks Free-run timer input clock Input capture DTTIxX - INTxx, NMIX Except Timer mode, Stop mode Timer mode, Stop mode 2tCYCP* - ns 2tCYCP + 100* - ns 500*2 - ns Wave form generator External interrupt NMI *: tCYCP indicates the APB bus clock cycle time. About the APB bus number which A/D converter, Multi-function Timer, External interrupt is connected to, see 8 Block Diagram in this data sheet. Document Number: 002-08541 Rev. *D Page 90 of 117 CY9B510R Series 12.4.12 Quadrature Position/Revolution Counter timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions AIN pin H width tAHL AIN pin L width tALL BIN pin H width tBHL BIN pin L width tBLL BIN rise time from tAUBU AIN pin H level AIN fall time from tBUAD BIN pin H level BIN fall time from tADBD AIN pin L level AIN rise time from tBDAU BIN pin L level AIN rise time from tBUAU BIN pin H level BIN fall time from tAUBD AIN pin H level AIN fall time from tBDAD BIN pin L level BIN rise time from tADBU AIN pin L level ZIN pin H width tZHL ZIN pin L width tZLL AIN/BIN rise and fall time tZABE from determined ZIN level Determined ZIN level from tABEZ AIN/BIN rise and fall time *: tCYCP indicates the APB bus clock cycle time. Min PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 PC_Mode2 or PC_Mode3 QCR:CGSC=0 QCR:CGSC=0 Value Max 2tCYCP* - Unit ns QCR:CGSC=1 QCR:CGSC=1 About the APB bus number which Quadrature Position/Revolution Counter is connected to, see 8 Block Diagram in this data sheet. tALL tAHL AIN tAUBU tADBD tBUAD tBDAU BIN tBHL Document Number: 002-08541 Rev. *D tBLL Page 91 of 117 CY9B510R Series tBLL tBHL BIN tBUAU tBDAD tAUBD tADBU AIN tAHL tALL ZIN ZIN AIN/BIN Document Number: 002-08541 Rev. *D Page 92 of 117 CY9B510R Series 12.4.13 I2C Timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol SCL clock frequency (Repeated) START condition hold time SDA ↓ → SCL ↓ SCLclock L width SCLclock H width (Repeated) START setup time SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data setup time SDA ↓ ↑ → SCL ↑ STOP condition setup time SCL ↑ → SDA ↑ Bus free time between STOP condition and START condition Conditions Standard-mode Fast-mode Unit Min Max Min Max FSCL 0 100 0 400 kHz tHDSTA 4.0 - 0.6 - μs tLOW tHIGH 4.7 4.0 - 1.3 0.6 - μs μs 4.7 - 0.6 - μs 0 3.45*2 0 0.9*3 μs tSUDAT 250 - 100 - ns tSUSTO 4.0 - 0.6 - μs tBUF 4.7 - 1.3 - μs tSUSTA tHDDAT CL = 30 pF, R = (Vp/IOL)*1 8 MHz ≤ 2 tCYCP*4 2 tCYCP*4 tCYCP ≤ 40 MHz 40 MHz < Noise filter tSP 3 tCYCP*4 3 tCYCP*4 tCYCP ≤ 60 MHz 60 MHz < 4 tCYCP*4 4 tCYCP*4 tCYCP ≤ 72 MHz *1: R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Remarks ns *5 ns *5 ns *5 Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it doesn't extend at least L period (tLOW) of device's SCL signal. *3: Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see 8 Block Diagram in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. *5: The number of the steps of the noise filter can be changed by register settings. Change the number of the noise filter steps according to APB2 bus clock frequency. SDA SCL Document Number: 002-08541 Rev. *D Page 93 of 117 CY9B510R Series 12.4.14 ETM Timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Data hold tETMH TRACECLK TRACED[3:0] TRACECLK frequency 1/ tTRACE TRACECLK TRACECLK cycle time tTRACE Value Unit Min Max VCC ≥ 4.5 V 2 9 VCC < 4.5 V 2 15 VCC ≥ 4.5 V - 50 MHz VCC < 4.5 V - 32 MHz VCC ≥ 4.5 V 20 - ns VCC < 4.5 V 31.25 - ns Remarks ns Note: − When the external load capacitance = 30 pF. HCLK TRACECLK TRACED[3:0] Document Number: 002-08541 Rev. *D Page 94 of 117 CY9B510R Series 12.4.15 JTAG Timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name TMS, TDI setup time tJTAGS TCK, TMS, TDI TMS, TDI hold time tJTAGH TCK, TMS, TDI TDO delay time tJTAGD TCK, TDO Conditions VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V VCC ≥ 4.5 V VCC < 4.5 V Value Unit Min Max 15 - ns 15 - ns - 25 - 45 Remarks ns Note: − When the external load capacitance = 30 pF. TCK TMS/TDI TDO Document Number: 002-08541 Rev. *D Page 95 of 117 CY9B510R Series 12.5 12-bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Value Typ - Max 12 Unit Resolution - - Min - Integral Nonlinearity - - - ± 4.0 ± 4.5 LSB Differential Nonlinearity - - - ± 2.3 ± 2.5 LSB Zero transition voltage Full-scale transition voltage VZT ANxx - ± 10 ± 15 mV VFST ANxx - AVRH ± 10 AVRH ± 15 mV Conversion time - - 1.0*1 - - 1.2*1 - - Sampling time tS - *2 - - *2 - - Compare clock cycle*3 tCCK - 50 - 2000 ns State transition time to operation permission tSTT - - - 1.0 μs Analog input capacity CAIN - - - 12.9 pF Analog input resistance RAIN - - - Interchannel disparity Analog port input leak current Analog input voltage - - - - 4 LSB - ANxx - - 5 μA - ANxx AVSS - AVRH V Reference voltage - AVRH 2.7 - AVCC V 2 3.8 Remarks bit μs ns kΩ AVRH = 2.7 V to 5.5 V AVCC ≥ 4.5 V AVCC < 4.5 V AVCC ≥ 4.5 V AVCC < 4.5 V AVCC ≥ 4.5 V AVCC < 4.5 V AVCC ≥ 4.5 V AVCC < 4.5 V *1: Conversion time is the value of sampling time (tS) + compare time (tC). The condition of the minimum conversion time is the following. AVCC ≥ 4.5 V, HCLK=120 Hz sampling time: 300 ns, compare time: 700 ns AVCC < 4.5 V, HCLK=120 Hz sampling time: 500 ns, compare time: 700 ns Ensure that it satisfies the value of sampling time (tS) and compare clock cycle (tCCK). For setting*4 of sampling time and compare clock cycle, see CHAPTER 1-1: 12-bit A/D Converter in FM3 Family PERIPHERAL MANUAL Analog Macro Part. A/D Converter register is set at APB bus clock timing. Sampling and compare clock is set at Base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see 8 Block Diagram in this data sheet. *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1). *3: Compare time (tC) is the value of (Equation 2). Document Number: 002-08541 Rev. *D Page 96 of 117 CY9B510R Series ANxx Analog input pin Analog signal source REXT Comparator RAIN CAIN (Equation 1) tS ≥ (RAIN + REXT ) × CAIN × 9 tS: Sampling time RAIN: Input resistance of A/D = 2 kΩ at 4.5 V < AVCC < 5.5 V Input resistance of A/D = 3.8 kΩ at 2.7 V < AVCC < 4.5 V CAIN: Input capacity of A/D = 12.9 pF at 2.7 V < AVCC < 5.5 V REXT: Output impedance of external circuit (Equation 2) tC = tCCK × 14 tC: Compare time tCCK: Compare clock cycle Document Number: 002-08541 Rev. *D Page 97 of 117 CY9B510R Series Definition of 12-bit A/D Converter Terms ◼ Resolution: Analog variation that is recognized by an A/D converter. ◼ Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics. ◼ Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity 0xFFF Actual conversion characteristics 0xFFE 0x(N+1) {1 LSB(N-1) + VZT} VFST VNT 0x004 (Actuallymeasured value) (Actually-measured value) 0x003 Digital output Digital output 0xFFD Differential Nonlinearity Actual conversion characteristics Ideal characteristics 0x002 0x001 0xN Actual conversion characteristics Ideal characteristics VNT Actual conversion characteristics AVRH AVSS AVRH Analog input Integral Nonlinearity of digital output N = Differential Nonlinearity of digital output N = 1LSB = (Actually-measured value) (Actually-measured value) 0x(N-2) VZT (Actually-measured value) AVSS V(N+1)T 0x(N-1) Analog input VNT - {1LSB × (N - 1) + VZT} 1LSB V(N + 1) T - VNT 1LSB [LSB] - 1 [LSB] VFST - VZT 4094 N: VZT: VFST: VNT: A/D converter digital output value. Voltage at which the digital output changes from 0x000 to 0x001. Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N − 1) to 0xN. Document Number: 002-08541 Rev. *D Page 98 of 117 CY9B510R Series 12.6 USB Characteristics (VCC = 2.7V to 5.5V, USBVCC = 3.0V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Input characte ristics Symbol Pin name Conditions Value Max USBVCC + 0.3 Unit Remarks V *1 Input H level voltage VIH - Min 2.0 Input L level voltage Differential input sensitivity Different common mode input voltage VIL - VSS - 0.3 0.8 V *1 VDI - 0.2 - V *2 VCM - 0.8 2.5 V *2 External pull-down Output H level voltage VOH 2.8 3.6 V *3 resistance = 15 kΩ UDP0, UDM0 External pull-up Output L level voltage VOL resistance = 0.0 0.3 V *3 1.5 kΩ Output Crossover voltage VCRS 1.3 2.0 V *4 characte Rise time tFR Full-Speed 4 20 ns *5 ristics Fall time tFF Full-Speed 4 20 ns *5 Rise/ fall time matching tFRFM Full-Speed 90 111.11 % *5 Output impedance ZDRV Full-Speed 28 44 Ω *6 Rise time tLR Low-Speed 75 300 ns *7 Fall time tLF Low-Speed 75 300 ns *7 Rise/ fall time matching tLRFM Low-Speed 80 125 % *7 *1: The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V, VIH (Min) = 2.0 V (TTL input standard). There are some hystereses to lower noise sensitivity. *2: Use differential-Receiver to receive USB differential data signal. Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the local ground reference level. Minimum differential input sensitivity [V] Above voltage range is the common mode input voltage range. Common mode input voltage [V] Document Number: 002-08541 Rev. *D Page 99 of 117 CY9B510R Series *3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to the VSS and 1.5 kΩ load) at High-State (VOH). *4: The cross voltage of the external differential output signal (D + /D −he of USB I/O buffer is within 1.3 V to 2.0 V. VCRS specified range *5: They indicate rise time (Trise) and fall time (Tfall) of the full-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission. Rising time Document Number: 002-08541 Rev. *D Falling time Page 100 of 117 CY9B510R Series *6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic impedance (Differential Mode). USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance. When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) Series resistor Rs. 28Ω to 44Ω Equiv. Imped. 28Ω to 44Ω Equiv. Imped. Mount it as external resistance. Rs series resistor 25Ω to 30Ω Series resistor of 27Ω (recommendation value) must be added. And, use resistance with an uncertainty of 5% by E24 sequence. *7: They indicate rise time (Trise) and fall time (Tfall) of the low-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. Rising time Falling time See Figure  Low-Speed Load (Compliance Load) for conditions of external load. Document Number: 002-08541 Rev. *D Page 101 of 117 CY9B510R Series Low-Speed Load (Upstream Port Load) - Reference 1 CL = 50pF to 150pF CL = 50pF to 150pF Low-Speed Load (Downstream Port Load) - Reference 2 CL =200pF to 600pF CL =200pF to 600pF Low-Speed Load (Compliance Load) CL = 200pF to 450pF CL = 200pF to 450pF Document Number: 002-08541 Rev. *D Page 102 of 117 CY9B510R Series 12.7 Low-Voltage Detection Characteristics 12.7.1 Low-Voltage Detection Reset (TA = - 40°C to + 85°C) Parameter Symbol Conditions Detected voltage Released voltage VDL VDH - 12.7.2 Min 2.25 2.30 Value Typ 2.45 2.50 Max 2.65 2.70 Unit Remarks V V When voltage drops When voltage rises Interrupt of Low-Voltage Detection (TA = - 40°C to + 85°C) Parameter Symbol Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage Detected voltage Released voltage VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH VDL VDH LVD stabilization wait time tLVDW Conditions SVHI = 0000 SVHI = 0001 SVHI = 0010 SVHI = 0011 SVHI = 0100 SVHI = 0111 SVHI = 1000 SVHI = 1001 - Min 2.58 2.67 2.76 2.85 2.94 3.04 3.31 3.40 3.40 3.50 3.68 3.77 3.77 3.86 3.86 3.96 - Value Typ 2.8 2.9 3.0 3.1 3.2 3.3 3.6 3.7 3.7 3.8 4.0 4.1 4.1 4.2 4.2 4.3 - Max 3.02 3.13 3.24 3.34 3.45 3.56 3.88 3.99 3.99 4.10 4.32 4.42 4.42 4.53 4.53 4.64 4032 × tCYCP* Unit Remarks V V V V V V V V V V V V V V V V When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises When voltage drops When voltage rises μs *: tCYCP indicates the APB2 bus clock cycle time. Document Number: 002-08541 Rev. *D Page 103 of 117 CY9B510R Series 12.8 MainFlash Memory Write/Erase Characteristics 12.8.1 Write / Erase time (VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C) Parameter Value Unit Remarks s Includes write time prior to internal erase 384 μs Not including system-level overhead time 38.4 s Includes write time prior to internal erase Typ* Max* Large Sector 0.7 3.7 Small Sector 0.3 1.1 Half word (16-bit) write time 12 Chip erase time 8 Sector erase time *: The typical value is immediately after shipment, the maximum value is guarantee value under 100,000 cycle of erase/write. 12.8.2 Erase/write cycles and data hold time Erase/write cycles (cycle) Data hold time (year) 1,000 20* 10,000 10* 100,000 5* Remarks *: At average + 85C 12.9 WorkFlash Memory Write/Erase Characteristics 12.9.1 Write / Erase time (VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C) Parameter Value Unit Remarks 1.5 s Includes write time prior to internal erase 20 384 μs Not including system-level overhead time 1.2 6 s Includes write time prior to internal erase Typ* Max* Sector erase time 0.3 Half word (16-bit) write time Chip erase time *: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write. 12.9.2 Erase/write cycles and data hold time Erase/write cycles (cycle) Data hold time (year) 1,000 20* 10,000 10* Remarks *: At average + 85C Document Number: 002-08541 Rev. *D Page 104 of 117 CY9B510R Series 12.10 Return Time from Low-Power Consumption Mode 12.10.1 Return Factor: Interrupt The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. Return Count Time (VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C) Parameter Symbol Sleep mode High-speed CR Timer mode, Main Timer mode, PLL Timer mode Value Typ Max* tCYCC Unit ns 40 80 μs 453 737 μs Sub Timer mode 453 737 μs Stop mode 453 737 μs Low-speed CR Timer mode tICNT Remarks *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by external interrupt*) External interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: External interrupt is set to detecting fall edge. Document Number: 002-08541 Rev. *D Page 105 of 117 CY9B510R Series Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal resource interrupt Interrupt factor accept Active tICNT CPU Operation Interrupt factor clear by CPU Start *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See "CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes" in "FM3 Family PERIPHERAL MANUAL" about the return factor from Low-Power consumption mode. − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3 Family PERIPHERAL MANUAL". Document Number: 002-08541 Rev. *D Page 106 of 117 CY9B510R Series 12.10.2 Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. Return Count Time (VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C) Parameter Symbol Value Unit Typ Max* 321 461 μs 321 461 μs 441 701 μs Sub Timer mode 441 701 μs Stop mode 441 701 μs Sleep mode High-speed CR Timer mode, Main Timer mode, PLL Timer mode Low-speed CR Timer mode tRCNT Remarks *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by INITX) INITX Internal reset Reset active Release tRCNT CPU Operation Document Number: 002-08541 Rev. *D Start Page 107 of 117 CY9B510R Series Operation example of return from low power consumption mode (by internal resource reset*) Internal resource reset Internal reset Reset active Release tRCNT CPU Operation Start *: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See "CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes" in "FM3 Family PERIPHERAL MANUAL." − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3 Family PERIPHERAL MANUAL". − The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on Reset Timing" in "4. AC Characteristics" in "12 Electrical Characteristics" for the detail on the time during the power-on reset/low -voltage detection reset. − When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time. − The internal resource reset means the watchdog reset and the CSV reset. Document Number: 002-08541 Rev. *D Page 108 of 117 CY9B510R Series 13. Ordering Information Part number On-chip Flash memory On-chip SRAM CY9BF512NPQC-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte CY9BF514NPQC-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte CY9BF515NPQC-G-JNE2 Main: 384 Kbyte Work: 32 Kbyte 48 Kbyte CY9BF516NPQC-G-JNE2 Main: 512 Kbyte Work: 32 Kbyte 64 Kbyte CY9BF512NPMC-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte CY9BF514NPMC-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte CY9BF515NPMC-G-JNE2 Main: 384 Kbyte Work: 32 Kbyte 48 Kbyte CY9BF516NPMC-G-JNE2 Main: 512 Kbyte Work: 32 Kbyte 64 Kbyte CY9BF512RPMC-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte CY9BF514RPMC-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte CY9BF515RPMC-G-JNE2 Main: 384 Kbyte Work: 32 Kbyte 48 Kbyte CY9BF516RPMC-G-JNE2 Main: 512 Kbyte Work: 32 Kbyte 64 Kbyte CY9BF512NBGL-GE1 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte CY9BF514NBGL-GE1 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte CY9BF515NBGL-GE1 Main: 384 Kbyte Work: 32 Kbyte 48 Kbyte CY9BF516NBGL-GE1 Main: 512 Kbyte Work: 32 Kbyte 64 Kbyte Document Number: 002-08541 Rev. *D Package Packing Plastic  QFP 100-pin (0.65 mm pitch), (PQH100) Plastic  LQFP 100-pin (0.5 mm pitch), (LQI100) Tray Plastic  LQFP 120-pin (0.5 mm pitch), (LQM120) Plastic  FBGA 112-pin (0.8 mm pitch), (LBC112) Page 109 of 117 CY9B510R Series 14. Package Dimensions Package Type Package Code LQFP 100 LQI100 D D1 75 4 D 5 7 51 D1 51 50 76 4 5 7 75 50 76 E1 E 5 4 7 E1 E 5 4 7 3 6 26 100 1 26 25 1 25 2 5 7 e 100 BOTTOM VIEW 0.1 0 C A-B D 3 0.2 0 C A-B D b TOP VIEW 8 0.0 8 C A-B D 2 A 9 A SEATIN G PLA N E A' 0.25 L1 0.0 8 C c A1 b 10 SECTIO N A-A ' L SIDE VIEW SYM BOL DETAIL A DIM ENSIONS M IN. NOM . M AX. 1.70 A A1 0.05 b 0.15 0.15 0.27 c 0.09 0.20 D 16.00 BSC D1 14.00 BSC e 0.50 BSC E 16.00 BSC E1 14.00 BSC L 0.45 0.60 0.75 L1 0.30 0.50 0.70 NOTES : 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. 2. DATUM PLANE H IS LOCATED AT THE BOTTOM OF THE M OLD PARTING LINE COINCIDENT W ITH W HERE THE LEAD EXITS THE BODY. 3. DATUM S A-B AND D TO BE DETERM INED AT DATUM PLANE H. 4. TO BE DETERM INED AT SEATING PLANE C. 5. DIM ENSIONS D1 AND E1 DO NOT INCLUDE M OLD PROTRUSION. ALLOW ABLEPROTRUSION IS 0.25m m PRE SIDE. DIM ENSIONS D1 AND E1 INCLUDE M OLD M ISM ATCH AND ARE DETERM INED AT DATUM PLANE H. 6. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT M UST BE LOCATED W ITHIN THE ZONE INDICATED. 7. REGARDLESS OF THE RELATIVE SIZE OF THE UPPER AND LOW ER BODY SECTIONS. DIM ENSIONS D1 AND E1 ARE DETERM INED AT THE LARGEST FEATURE OF THE BODY EXCLUSIVE OF M OLD FLASH AND GATE BURRS. BUT INCLUDING ANY M ISM ATCH BETW EEN THE UPPER AND LOW ER SECTIONS OF THE M OLDER BODY. 8. DIM ENSION b DOES NOT INCLUDE DAM BAR PROTRUSION. THE DAM BAR PROTRUSION (S) SHALL NOT CAUSE THE LEAD W IDTH TO EXCEED b M AXIM UM BY M ORE THAN 0.08m m . DAM BAR CANNOT BE LOCATED ON THE LOW ER RADIUS OR THE LEAD FOOT. 9. THESE DIM ENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETW EEN 0.10m m AND 0.25m m FROM THE LEAD TIP. 10. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOW EST POINT OF THE PACKAGE BODY. PACKAGE OUTLINE, 100 LEAD LQFP 14.0X14.0X1.7 M M LQI100 REV*A Document Number: 002-08541 Rev. *D 002-11500 *A Page 110 of 117 CY9B510R Series Package Type Package Code LQFP 120 LQM120 4 D 5 7 D1 90 61 91 61 60 90 91 60 E1 E 4 5 7 3 6 31 120 1 31 30 e 3 b 0.20 C A-B D 30 2 5 7 0.10 0.08 1 C A-B D C A-B D BOTTOM VIEW 8 TOP VIEW 2 A 9 c θ A A' 0.08 C SEATI N G PLA N E 0.25 A1 10 b SECTION A -A' L SIDE VIEW SYM BOL DIM ENSIONS M IN. NOM . M AX. 0.05 0.15 A A1 1. 70 b 0.17 c 0.115 0.22 D 18.00 BSC D1 16.00 BSC e 0.50 BSC E 18.00 BSC E1 L θ 0.27 0.195 16.00 BSC 0.45 0° 0.60 0.75 8° PACKAGE OUTLINE, 120 LEAD LQFP 18.0X18.0X1.7 M M LQM 120 REV** Document Number: 002-08541 Rev. *D 002-16172 ** Page 111 of 117 CY9B510R Series Package Type Package Code QFP 100 PQH100 D D1 4 5 7 80 51 81 51 50 80 50 81 31 100 E1 E 5 7 6 3 4 31 100 1 30 e 3 0.40 C A-B D 30 2 5 7 1 0.20 C A-B D b 0.13 C A-B D BOTTOM VIEW 8 TOP VIEW 2 θ 9 A A' SEATING PLANE L2 c 10 b 0.10 C SECTION A-A' D ETAIL A SID E VIEW SYM BOL DIM ENSIONS M IN. NOM . M AX. A1 0.05 0.45 b 0.27 c 0.11 A 3.35 0.32 0.23 D 23.90 BSC D1 20.00 BSC e 0.65 BSC E 17.90 BSC E1 θ L 0.37 14.00 BSC 0° 0.73 8° 0.88 L1 1.95 REF L2 0.2 5 BSC 1.03 PACKAGE OUTLINE, 100 LEAD QFP 20.00X14.00X3 .35 M M PQH100 REV** Document Number: 002-08541 Rev. *D 002-15156 ** Page 112 of 117 CY9B510R Series Package Type Package Code FBGA 112 LBC112 A 0.20 C 11 2X 10 9 6 8 7 6 5 4 3 2 1 L PIN A1 CORNER IN D EX M A RK K J H G F E D 7 C B A 6 B 0.20 C 2X TOP VIEW BOTTOM VIEW DETAIL A 5 11 2x φb C 0.10 C D ETAIL A 0.08 C A B SID E VIEW NOTES: 1. ALL DIM ENSIONS ARE IN M ILLIM ETERS. DIM ENSIONS SYM BOL M IN. NOM . M AX. 2. SOLDER BALL POSITION DESIGNATIO N PER JEP95, SECTION 3, SPP-020. A - - 1.45 3. "e"REPRESENTSTHE SOLDER BALL GRID PITCH. A1 0.25 0.35 0.45 4. SYM BOL "M D"IS THE BALL M ATRIX SIZE IN THE "D"DIRECTION. D 10.00 BSC SYM BOL "M E"IS THE BALL M ATRIX SIZE IN THE "E"DIRECTION. E 10.00 BSC N IS THE NUM BER OF POPULATED SOLDER BALL POSITIONS FOR M ATRIX D1 8.00 BSC E1 8.00 BSC MD 11 ME 11 N 112 b 0.35 0.45 eD 0.80 BSC eE 0.80 BSC SD 0.00 SE 0.00 SIZE M D X M E. 5. DIM ENSION "b"IS M EASURED AT THE MAXIM UM BALL DIAM ETER IN A PLANE PARALLEL TO DATUM C. 6. "SD"AND "SE"ARE M EASURED W ITH RESPECT TO DATUM S A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW . 0.55 W HEN THERE IS AN ODD NUM BEROF SOLDER BALLS IN THE OUTER ROW , "SD"OR "SE"= 0. W HEN THERE IS AN EVEN NUM BEROF SOLDER BALLS IN THE OUTER ROW , "SD" = eD/2 AND "SE"= eE/2. 7. A1 CORNER TO BE IDENTIFIED BY CHAM FER, LASER OR INK M ARK M ETALIZED M ARK, INDENTATION OR OTHER M EANS. 8. "+ " INDICATESTHE THEORETICAL CENTER OF DEPOPULATED SOLDER BALLS. PACKAGE OUTLINE, 112 BALL FBGA 10.00X10.00X1.45 M M LBC112 REV** Document Number: 002-08541 Rev. *D 002-13225 ** Page 113 of 117 CY9B510R Series 15. Major Changes Spansion Publication Number: DS706-00025 Page Section Revision 1.0 Revision 2.0 6 ◼ FEATURES  External Interrupt Controller Unit ◼ ELECTRICAL CHARACTERISTICS 102 5. 12-bit A/D Converter  Electrical Characteristics for the A/D Converter ◼ ORDERING INFORMATION 111 Revision 2.1 Revision 3.0 ◼Features 2 ⚫External Bus Interface ◼Features 3 ⚫USB Interface 10 ◼Packages ◼List of Pin Functions 28, 29 · List of pin numbers 48, 50 ◼I/O Circuit Type 48, 49 ◼I/O Circuit Type 55 ◼Handling Devices ◼Handling Devices 55 ⚫Crystal oscillator circuit ◼Handling Devices 56 ⚫C Pin 57 ◼Block Diagram ◼Memory Map 58 · Memory map(1) ◼Memory Map 59, 60 · Memory map(2)(3) 67, 68 ◼Electrical Characteristics 1. Absolute Maximum Ratings 69 ◼Electrical Characteristics 2. Recommended Operation Conditions 70, 71 ◼Electrical Characteristics 3. DC Characteristics (1) Current rating 74 75 ◼Electrical Characteristics 4. AC Characteristics (1) Main Clock Input Characteristics ◼Electrical Characteristics 4. AC Characteristics (3) Built-in CR Oscillation Characteristics Document Number: 002-08541 Rev. *D Change Results Initial release Corrected the external interrupt input pin. Corrected the value of "Compare clock cycle". Max: 10000 → 2000 Corrected the part number. Company name and layout design change Added the description of Maximum area size Added the description of PLL for USB Deleted the description of ES Modified I/O circuit type of P63 to P68 Added the description of I2C to the type of E, F and I Added about +B input Added "Stabilizing power supply voltage" Added the following description "Evaluate oscillation of your using crystal oscillator by your mount board." Changed the description Modified the block diagram Modified the area of "External Device Area" Added the summary of Flash memory sector and the note · Added the Clamp maximum current · Added the output current of P80 and P81 · Added about +B input · Modified the minimum value of Analog reference voltage · Added Smoothing capacitor · Added the note about less than the minimum power supply voltage · Changed the table format · Added Main TIMER mode current · Added Flash Memory Current · Moved A/D Converter Current · Modified the unit of low voltage detection circuit (LVD) power supply current Added Master clock at Internal operating clock frequency Added Frequency stability time at Built-in high-speed CR Page 114 of 117 CY9B510R Series Page 76 77 79-81 89-96 103 110 111 112-11 5 Section ◼Electrical Characteristics 4. AC Characteristics (4-1) Operating Conditions of Main and USB PLL (4-2) Operating Conditions of Main PLL ◼Electrical Characteristics 4. AC Characteristics (6) Power-on Reset Timing ◼Electrical Characteristics 4. AC Characteristics (7) External Bus Timing ◼Electrical Characteristics 4. AC Characteristics (8) CSIO/UART Timing ◼Electrical Characteristics 5. 12bit A/D Converter ◼Electrical Characteristics 7. Low-voltage Detection Characteristics (2) Interrupt of Low-voltage Detection ◼Electrical Characteristics 9. WorkFlash Memory Write/Erase Characteristics (1) Write / Erase time ◼Electrical Characteristics 9. Return Time from Low-Power Consumption Mode ◼Ordering Information Change Results · Added Main PLL clock frequency · Added USB clock frequency · Added the figure of Main PLL connection and USB PLL connection · Added Time until releasing Power-on reset · Changed the figure of timing Modified Data output time · Modified from UART Timing to CSIO/UART Timing · Changed from Internal shift clock operation to Master mode · Changed from External shift clock operation to Slave mode · Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage · Modified Stage transition time to operation permission · Modified the minimum value of Reference voltage Modified LVD stabilization wait time · Modified sector erase time · Modified half word(16-bit) write time Added Return Time from Low-Power Consumption Mode 116 Change to full part number 117-12 ◼Package Dimensions Deleted FPT-100P-M20 and FPT-120P-M21 0 NOTE: Please see “Document History” about later revised information. Document Number: 002-08541 Rev. *D Page 115 of 117 CY9B510R Series Document History Document Title: CY9B510R Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller Document Number: 002-08541 Revision ECN ** - Submission Description of Change Date Migrated to Cypress and assigned document number 002-08541. 03/31/2015 No change to document contents or format. Changed package code as below. FPT-100P-M23 to LQI100-02 FPT-120P-M37 to LQM120-02 FPT-100P-M36 to PQH100 BGA-112P-M04 to LBC112 *A 5175344 03/17/2016 Modified from USB function to USB device. P.19 Modified I/O circuit type of MD0 P.40 Added the note of JTAG pins. P.52 Modified X1A of block diagram. P.70 Modified max value of PLL macro oscillation clock frequency to 144MHz. P.110-113 Changed package Dimensions. *B 5314949 06/16/2016 P.109 Modified part number. “Modified RTC description in “Features, Real-Time Clock(RTC)” Changed starting count value from 01 to 00. Deleted “second , or day of the week” in the Interrupt function (Page 3) Updated “12.4.7 Power-On Reset Timing”. Changed parameter from “Power Supply rising time(tVCCR)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and added some comments (Page 71) *C 5666809 03/21/2017 Updated Package code as follows (Page 9-13, 63, 109) LQI100-02 -> LQI100, LQM120-02 -> LQM120 Updated “14. Package dimensions” (Page 110-113) Modified typo in “13. Ordering Information” (Page 109) Added the Baud rate spec in “12.4.10 CSIO/UART Timing”.(Page 82, 84, 86, 88) *D 6963793 09/11/2020 Document Number: 002-08541 Rev. *D Updated Ordering Information; Changed MB into CY globally. Page 116 of 117 CY9B510R Series Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Arm® Cortex® Microcontrollers cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU Automotive cypress.com/automotive Cypress Developer Community Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Community | Code Examples | Projects | Videos | Blogs | Training | Components Internet of Things cypress.com/iot Technical Support Memory cypress.com/memory cypress.com/support Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless All other trademarks or registered trademarks referenced herein are the property of their respective owners. Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 © Cypress Semiconductor Corporation, 2012-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device” means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-08541 Rev. *D Page 117 of 117