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CYBL10563-68FLXIT

CYBL10563-68FLXIT

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    68-XFBGA,WLCSP

  • 描述:

    ICRFTXRXBLUETOOTH68WLCSP

  • 数据手册
  • 价格&库存
CYBL10563-68FLXIT 数据手册
CYBL10X6X Family Datasheet Programmable Radio-on-Chip With Bluetooth Low Energy (PRoC BLE) ns General Description es ig PRoC BLE is a 32-bit, 48-MHz ARM® Cortex®-M0 BLE solution with CapSense®, 12-bit ADC, four timer, counter, pulse-width modulators (TCPWM), thirty-six GPIOs, two serial communication blocks (SCBs), LCD, and I2S. PRoC BLE includes a royalty-free BLE stack compatible with Bluetooth® 4.1 and provides a complete, programmable, and flexible solution for HID, remote controls, toys, beacons, and wireless chargers. In addition to these applications, PRoC BLE provides a simple, low-cost way to add BLE connectivity to any system. Features ■ ■ Clock, Reset, and Supply ■ fo r 32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit multiply, operating at up to 48 MHz ■ 128-KB flash memory ■ 16-KB SRAM memory ■ Emulated EEPROM using flash memory ■ Watchdog timer with dedicated internal low-speed oscillator (ILO) ■ Programmable GPIOs en de d ■ ■ ■ 36 GPIOs configurable as open drain high/low, pull-up/pull-down, HI-Z, or strong output Any GPIO pin can be CapSense, LCD, or analog, with flexible pin routing Programming and Debug Ultra-Low-Power 1.3-µA Deep-Sleep mode with watch crystal oscillator (WCO) on ■ 150-nA Hibernate mode current with SRAM retention ■ 60-nA Stop mode current with GPIO wakeup ■ CapSense® ■ om m ■ Touch Sensing with Two-Finger Gestures Up to 36 capacitive sensors for buttons, sliders, and touchpads ■ Two-finger gestures: scroll, inertial scroll, pinch, stretch, and edge-swipe ■ Cypress Capacitive Sigma-Delta (CSD) provides best-in-class SNR (> 5:1) and liquid tolerance ■ Automatic hardware-tuning algorithm (SmartSense™) R ec ■ Wide supply-voltage range: 1.9 V to 5.5 V 3-MHz to 48-MHz internal main oscillator (IMO) with 2% accuracy 24-MHz external clock oscillator (ECO) without load capacitance 32-kHz WCO N ■ ■ ARM Cortex-M0 CPU Core Four dedicated 16-bit TCPWMs ❐ Additional four 8-bit or two 16-bit PWMs Programmable LVD from 1.8 V to 4.5 V I2S Master interface D ■ Bluetooth 4.1 single-mode device ■ 2.4-GHz BLE radio and baseband with integrated balun ■ TX output power: –18 dBm to +3 dBm ■ Received signal strength indicator (RSSI) with 1-dB resolution ■ RX sensitivity: –89 dBm ■ TX current: 15.6 mA at 0 dBm ■ RX current: 16.4 mA ■ ew Bluetooth® Smart Connectivity Peripherals ■ Temperature and Packaging ■ ■ ■ ot N • Easy-to-use IDE to configure, develop, program, and test a BLE application Option to export the design to Keil, IAR, or Eclipse Bluetooth Low Energy Protocol Stack ■ Cypress Semiconductor Corporation Document Number: 001-90478 Rev. *L Operating temperature range: –40 °C to +105 °C Available in 56-pin QFN (7 mm × 7 mm) and 68-ball WLCSP (3.52 mm × 3.91 mm) packages PSoC® Creator™ Design Environment ■ 12-bit, 1-Msps SAR ADC with internal reference, sample-and-hold (S/H), and channel sequencer ■ Ultra-low-power LCD segment drive for 128 segments with operation in Deep-Sleep mode 2 ■ Two serial communication blocks (SCBs) supporting I C (Master/Slave), SPI (Master/Slave), or UART 2-pin SWD In-system flash programming support ■ 198 Champion Court Bluetooth Low Energy protocol stack supporting generic access profile (GAP) Central, Peripheral, Observer, or Broadcaster roles ❐ Switches between Central and Peripheral roles on-the-go Standard Bluetooth Low Energy profiles and services for interoperability ❐ Custom profile and service for specific use cases • San Jose, CA 95134-1709 • 408-943-2600 Revised March 23, 2017 PRoC BLE: CYBL10X6X Family Datasheet Contents 26 29 29 33 34 35 38 40 40 41 42 42 42 42 42 42 N ew D es ig ns Digital Peripherals ..................................................... Memory ..................................................................... System Resources .................................................... Ordering Information...................................................... Part Numbering Conventions .................................... Packaging........................................................................ Acronyms ........................................................................ Document Conventions ................................................. Units of Measure ....................................................... Revision History ............................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC® Solutions ...................................................... Cypress Developer Community................................. Technical Support ..................................................... N ot R ec om m en de d fo r Blocks and Functionality ................................................. 3 CPU Subsystem .......................................................... 4 BLE Subsystem........................................................... 4 System Resources Subsystem ................................... 4 Peripheral Blocks ........................................................ 6 Pinouts .............................................................................. 8 Power............................................................................... 13 Low-Power Modes..................................................... 13 Development Support .................................................... 15 Documentation .......................................................... 15 Online ........................................................................ 15 Tools.......................................................................... 15 Kits ............................................................................ 15 Electrical Specifications ................................................ 16 Absolute Maximum Ratings ...................................... 16 BLE Subsystem......................................................... 16 Device-Level Specifications ...................................... 19 Analog Peripherals .................................................... 24 Document Number: 001-90478 Rev. *L Page 2 of 42 PRoC BLE: CYBL10X6X Family Datasheet Blocks and Functionality The CYBL10X6X block diagram is shown in Figure 1. There are five major subsystems: CPU subsystem, BLE subsystem, system resources, peripheral blocks, and I/O subsystem. ns Figure 1. Block Diagram P0.6 P0.7 es ig CPU Subsystem ARM Cortex-M0 SWD FLASH 128 kB SRAM 16 kB CONFIG 512 B ROM 8 kB System Resources BLE Subsystem Clock Control N System Interconnect ew D NVIC XRES BOD ILO WDT WCO ECO fo r LVD IMO XRES Link Layer Engine RF PHY XTAL32I/P6.1 XTAL32O/P6.0 XTAL24I XTAL24O ANT R ec GPIOs 4x TCPWM I2S SCB0 I2C/UART/SPI GPIOs SCB1 I2C/UART/SPI GPIOs 4x PWM LCD GPIOs GPIOs High Speed I/O Matrix The PSoC Creator IDE provides fully integrated programming and debug support for PRoC BLE devices. The SWD interface is fully compatible with industry-standard third-party tools. PRoC BLE also supports disabling the SWD interface and has a robust flash-protection feature. N ot The PRoC BLE family includes extensive support for programming, testing, debugging, and tracing both hardware and firmware. The complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. Peripheral Interconnect CSD om GPIOs 12-Bit SAR ADC m GPIOs en de d Peripherals GPIOs Document Number: 001-90478 Rev. *L Page 3 of 42 PRoC BLE: CYBL10X6X Family Datasheet The CYBL10X6X device is based on an energy-efficient ARM Cortex-M0 32-bit processor, offering low power consumption, high performance, and reduced code size using 16-bit thumb instructions. The Cortex-M0’s ability to perform single-cycle 32-bit arithmetic and logic operations, including single-cycle 32-bit multiplication, helps in better performance. The inclusion of the tightly-integrated Nested Vectored Interrupt Controller (NVIC) with 32 interrupt lines enables the Cortex-M0 to achieve a low latency and a deterministic interrupt response. The CPU also includes a 2-pin interface, the serial wire debug (SWD), which is a 2-wire form of JTAG. The debug circuits are enabled by default and can only be disabled in firmware. If disabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with the new firmware that enables debugging. In addition, it is possible to use the debug pins as GPIO too. The device has four breakpoints and two watchpoints for effective debugging. ns CPU The physical layer consists of a modem and an RF transceiver that transmits and receives BLE packets at the rate of 1 Mbps over the 2.4-GHz ISM band. In the transmit direction, this block performs GFSK modulation and then converts the digital baseband signal of these BLE packets into radio frequency before transmitting them to air through an antenna. In the receive direction, this block converts an RF signal from the antenna to a digital bit stream after performing GFSK demodulation. es ig CPU Subsystem The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50-Ω antenna terminal through a pi-matching network. The output power is programmable from –18 dBm to +3 dBm to optimize the current consumption for different applications. BLE Subsystem System Resources Subsystem ew en de d fo r The device has a 128-KB flash memory with a flash accelerator, tightly coupled to the CPU to improve average access times from flash. The flash is designed to deliver 1-wait-state (WS) access time at 48 MHz and with 0-WS access time at 24 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average. Part of the flash can be used to emulate EEPROM operation, if required. N Flash D The 8-KB supervisory ROM contains a library of executable functions for flash programming. These functions are accessed through supervisory calls (SVC) and enable in-system programming of the flash memory. The Bluetooth Low Energy protocol stack uses the BLE subsystem and provides the following features: ■ Link Layer (LL) ❐ Master and Slave roles ❐ 128-bit AES engine ❐ Encryption ❐ Low-duty-cycle advertising (Bluetooth 4.1 feature) ❐ LE ping (Bluetooth 4.1 feature) ■ Bluetooth Low Energy 4.1 single-mode protocol stack with logical link control and adaptation protocol (L2CAP), attribute (ATT), and security manager (SM) protocols ■ Master and slave roles ■ API access to generic attribute profile (GATT), generic access profile (GAP), and L2CAP ■ L2CAP connection-oriented channel (Bluetooth 4.1 feature) ■ GAP features ❐ Broadcaster, Observer, Peripheral, and Central roles ❐ Security mode 1: Level 1, 2, and 3 ❐ Security mode 2: Level 1 and 2 ❐ User-defined advertising data ❐ Multiple-bond support ■ GATT features ❐ GATT client and server ❐ Supports GATT subprocedures ❐ 32-bit universally unique identifiers (UUID) (Bluetooth 4.1 feature) ■ Security Manager (SM) ❐ Pairing methods: Just Works, Passkey Entry, and Out of Band ❐ Authenticated man-in-the-middle (MITM) protection and data signing ■ Supports all SIG-adopted BLE profiles m During flash erase and programming operations (the maximum erase and program time is 20 ms per row), the IMO will be set to 48 MHz for the duration of the operation. This also applies to the emulated EEPROM. System design must take this into account because peripherals operating from different IMO frequencies will be affected. If it is critical that peripherals continue to operate with no change during flash programming, always set the IMO to 48 MHz and derive the peripheral clocks by dividing down from this frequency. om SRAM ot ROM R ec The low-power 16-KB SRAM memory retains its contents even in Hibernate mode. N The BLE subsystem consists of the link layer engine and physical layer. The link layer engine supports both master and slave roles. The link layer engine implements time-critical functions such as encryption in the hardware to reduce the power consumption, and provides minimal processor intervention and a high performance. The key protocol elements, such as host control interface (HCI) and link control, are implemented in firmware. The direct test mode (DTM) is included to test the radio performance using a standard Bluetooth tester. Document Number: 001-90478 Rev. *L Power The power block includes internal LDOs that supply required voltage levels for different blocks. The power system also includes POR, BOD, and LVD circuits. The POR circuit holds the device in the reset state until the power supplies have stabilized at appropriate levels and the clock is ready. The BOD circuit resets the device when the supply voltage is too low for proper device operation. The LVD circuit generates an interrupt if the supply voltage drops below a user-selectable level. Page 4 of 42 PRoC BLE: CYBL10X6X Family Datasheet peripherals. The system clock (SYSCLK) driving buses, registers, and the processor must be higher than all the other clocks in the system that are divided off HFCLK. The ECO and WCO are present in the BLE subsystem and the clock outputs are routed to the system resources. Clock Control Internal Main Oscillator (IMO) The PRoC BLE clock control is responsible for providing clocks to all subsystems and also for switching between different clock sources without glitching. The clock control for PRoC BLE consists of the IMO and the internal low-speed oscillator (ILO). It uses the 24-MHz external crystal oscillator (ECO) and the 32-kHz WCO. In addition, an external clock may be supplied from a pin. The IMO is the primary system clock source, which can be adjusted in the range of 3 MHz to 48 MHz in steps of 1 MHz. The IMO accuracy is ±2%. es ig Internal Low-Speed Oscillator (ILO) D The ILO is a very-low-power 32-kHz oscillator, which is primarily used to generate clocks for peripheral operations in Deep-Sleep mode. The ILO-driven counters can be calibrated to the IMO to improve accuracy. Cypress provides a software component, which does the calibration. fo r BLE Subsystem N Figure 2. Clock Control ew The device has 12 dividers with 16 divider outputs. Two dividers have additional fractional division capability. The HFCLK signal is divided down, as shown in Figure 2, to generate the system clock (SYSCLK) and peripheral clock (PERx_CLK) for different ECO Prescaler ` Divider 0 (/16) en de d Divider /2n (n=0..3) ns An external active-LOW reset pin (XRES) can be used to reset the device. The XRES pin has an internal pull-up resistor and, in most applications, does not require any additional pull-up resistors. The power system is described in detail in the “Power” section on page 13. HFCLK SYSCLK PER0_CLK IMO m EXTCLK om WCO Divider 9 (/16) Fractional Divider 0 (/16.5) Fractional Divider 1 (/16.5) LFCLK ILO R ec PER15_CLK   Voltage Reference The ECO is used as the active clock for the BLE subsystem to meet the ±50-ppm clock accuracy requirement of the Bluetooth 4.1 specification. The ECO includes a tunable load capacitor to tune the crystal clock frequency by measuring the actual clock frequency. The high-accuracy ECO clock can also be used as a system clock. The internal bandgap reference circuit with 1% accuracy provides the voltage reference for the 12-bit SAR ADC. To enable better SNRs and absolute accuracy, it will be possible to bypass the internal bandgap reference using a REF pin and to use an external reference for the SAR. N ot External Crystal Oscillator (ECO) Watch Crystal Oscillator (WCO) The WCO is used as the sleep clock for the BLE subsystem to meet the ±500-ppm clock accuracy requirement of the Bluetooth 4.1 specification. The sleep clock provides accurate sleep timing and enables wakeup at specified advertisement and connection intervals. With the WCO and firmware, an accurate real-time clock (within the bounds of the 32.768-kHz crystal accuracy) can be realized. Document Number: 001-90478 Rev. *L Watchdog Timer (WDT) A watchdog timer is implemented in the system resources subsystem running from the ILO; this allows watchdog operations during Deep-Sleep mode and generates a watchdog reset if not serviced before the timeout occurs. The watchdog reset is recorded in the ‘Reset Cause’ register. Page 5 of 42 PRoC BLE: CYBL10X6X Family Datasheet Peripheral Blocks Serial Communication Block (SCB0/SCB1) Control Configure Registers AHB, DSI VPLUS SARMUX SARADC Data Sequencer fo r VMINUS When SCB0 is used, Serial Data (SDA) and Serial Clock (SCL) of I2C can be connected to P0.4 and P0.5, or P1.4 and P1.5, or P3.0 and P3.1. SARREF Vrefs When SCB1 is used, SDA and SCL can be connected to P0.0 and P0.1, or P3.4 and P3.5, or P5.0 and P5.1. Ref-bypass en de d Analog Mux Bus A/B The hardware I2C block implements a full multimaster and slave interface (it is capable of multimaster arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast-Mode Plus) and has flexible buffering options to reduce the interrupt overhead and latency for the CPU. The I2C function is implemented using the Cypress-provided software Component (EzI2C) that creates a mailbox address range in the memory of PRoC BLE and effectively reduces the I2C communication to reading from and writing to an array in memory. In addition, the block supports an 8-byte FIFO for receive and transmit, which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused by the CPU not having read the data on time. N P3.0 - P3.7 SARSEQ I2C mode: The I2C peripheral is compatible with the I2C Standard-mode, Fast-mode, and Fast-Mode-Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIOs in open-drain modes. ew Figure 3. SAR ADC System Diagram ns Preceding the SAR ADC is the SARMUX, which can route external pins and internal signals (analog mux bus and temperature sensor output) to the eight internal channels of the SAR ADC. The sequencer controller (SARSEQ) is used to control the SARMUX and SAR ADC to do an automatic scan on all enabled channels without CPU intervention and for preprocessing tasks such as averaging the output data. A Cypress-supplied software driver (Component) is used to control the ADC peripheral. es ig The ADC is a 12-bit, 1-Msps SAR ADC with a built-in sample-and-hold (S/H) circuit. The ADC can operate with either an internal voltage reference or an external voltage reference. The SCB can be configured as an I2C, UART, or SPI interface. It supports an 8-byte FIFO for receive and transmit buffers to reduce CPU intervention. A maximum of two SCBs (SCB0, SCB1) are available. D 12-Bit SAR ADC   m A diode based, on-chip temperature sensor is used to measure the die temperature. The temperature sensor is connected to the ADC, which digitizes the reading and produces a temperature value using the Cypress-supplied software that includes calibration and linearization. om 4x Timer Counter PWM (TCPWM) R ec The 16-bit TCPWM module can be used to generate the PWM output or to capture the timing of edges of input signals or to provide a timer functionality. TCPWM can also be used as a 16-bit counter that supports up, down, and up/down counting modes. ot Rising edge, falling edge, combined rising/falling edge detection, or pass-through on all hardware input signals can be used to derive counter events. Three routed output signals are available to indicate underflow, overflow, and counter/compare match events. A maximum of four TCPWMs are available. 4x PWM N These PWMs are in addition to the TCPWMs. The PWM peripheral can be configured as 8-bit or 16-bit resolution. The PWM provides compare outputs to generate single or continuous timing and control signals in hardware. It also provides an easy method of generating complex real-time events accurately with minimal CPU intervention. A maximum of four 8-bit PWMs or two 16-bit PWMs are available. Document Number: 001-90478 Rev. *L Configurations for I2C are as follows: ■ SCB1 is fully compliant with the Standard-mode (100 kHz), Fast-mode (400 kHz), and Fast-Mode-Plus (1 MHz) I2C signaling specifications when routed to GPIO pins P5.0 and P5.1, except for hot-swap capability during I2C active communication. ■ SCB1 is compliant only with Standard mode (100 kHz) when not used with P5.0 and P5.1. ■ SCB0 is compliant with Standard mode (100 kHz) only. UART mode: This is a full-feature UART operating up to 1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols. In addition, it supports the 9-bit multiprocessor mode, which allows addressing of peripherals connected over common RX and TX lines. The UART hardware flow control is supported to allow slow and fast devices to communicate with each other over UART without the risk of losing data. Refer to Table 4 on page 11 for possible UART connections to the GPIOs. SPI Mode: The SPI mode supports full Motorola® SPI, Texas Instruments® Secure Simple Pairing (SSP) (essentially adds a start pulse used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). This block supports an 8-byte FIFO for receive and transmit. Refer to Table 4 on page 11 for the possible SPI connections to the GPIOs. Inter-IC Sound Bus (I2S) Inter-IC Sound Bus (I2S) is a serial bus interface standard used for connecting digital audio devices. The specification is from Philips® Semiconductor (I2S bus specification; February 1986, revised June 5, 1996). Page 6 of 42 PRoC BLE: CYBL10X6X Family Datasheet The PWM method drives the panel with PWM signals to effectively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher power consumption but provides better results in driving TN displays. ns The I/O subsystem, which comprises the GPIO block, implements the following: ■ Eight drive-strength modes: ❐ Analog input mode (input and output buffers disabled) ❐ Input only ❐ Weak pull-up with strong pull-down ❐ Weak pull-up with weak pull-down ❐ Strong pull-up with weak pull-down ❐ Strong pull-up with strong pull-down ❐ Open drain with strong pull-down ❐ Open drain with strong pull-up ■ Port pins: 36 ■ Input threshold select (CMOS or LVTTL) ■ Individual control of input and output buffers (enabling/disabling) in addition to drive-strength modes ■ Hold mode for latching the previous state (used for retaining the I/O state in Deep Sleep and Hibernate modes) ■ Selectable slew rates for dV/dt to improve EMI ■ The GPIO pins P5.0 and P5.1 are overvoltage-tolerant ■ The GPIO cells, including P5.0 and P5.1, cannot be hot-swapped or powered up independent of the rest of the system. fo r LCD operation is supported during Deep-Sleep mode by refreshing a small display buffer (four bits; one 32-bit register per port). I/O Subsystem es ig The digital correlation method modulates the frequency and signal levels of the commons and segments to generate the highest RMS voltage across a segment to light it up or to maintain the RMS signal as zero. This method is good for STN displays but may result in reduced contrast in TN (cheaper) displays. D The LCD controller can drive up to four commons and up to 32 segments. It uses full digital methods to drive the LCD segments providing ultra-low power consumption. The two methods used are referred to as digital correlation and PWM. The CapSense trackpad/touchpad with gestures has the following features: ■ Supports 1-finger and 2-finger touch applications ■ Supports up to 35 X/Y sensor inputs ■ Includes a gesture-detection library: ❐ 1-finger touch: tracing, pan, click, double-click ❐ 2-finger touch: pan, click, zoom ew LCD in phase with the sense electrode keeps the shield capacitance from attenuating the sensed input. N I2S operates only in the Master mode, supporting the transmitter (TX) and the receiver (RX), which have independent data byte streams. These byte streams are packed with the most significant byte first. The number of bytes used for each sample (a sample for the left or right channel) is the minimum number of bytes to hold a sample. CapSense N ot R ec om m en de d CapSense is supported on all GPIOs through a Capacitive Sigma-Delta (CSD) block, which can be connected to any GPIO through an analog mux bus. Any GPIO pin can be connected to the analog mux bus via an analog switch. The CapSense function can thus be provided on any pin or group of pins in a system under software control. A software Component in PSoC Creator is provided for the CapSense block to make it easy for the user. The shield voltage can be driven on another mux bus to provide liquid-tolerance capability. Driving the shield electrode Document Number: 001-90478 Rev. *L Page 7 of 42 PRoC BLE: CYBL10X6X Family Datasheet Pinouts Table 1 shows the pin list for the CYBL10X6X device. 1 VDDD POWER 1.71-V to 5.5-V digital supply 2 XTAL32O/P6.0 CLOCK 32.768-kHz crystal 3 XTAL32I/P6.1 CLOCK 32.768-kHz crystal or external clock input 4 XRES RESET Reset, active LOW 5 P4.0 GPIO Port 4 Pin 0, analog/digital/lcd/csd 6 P4.1 GPIO Port 4 Pin 1, analog/digital/lcd/csd 7 P5.0 GPIO Port 5 Pin 0, analog/digital/lcd/csd 8 P5.1 GPIO Port 5 Pin 1, analog/digital/lcd/csd 9 VSSD GROUND 10 VDDR POWER 1.9-V to 5.5-V radio supply Digital ground GANT1 GROUND Antenna shielding ground ANT ANTENNA Antenna pin 13 GANT2 GROUND Antenna shielding ground 14 VDDR POWER 1.9-V to 5.5-V radio supply 15 VDDR POWER 1.9-V to 5.5-V radio supply 16 XTAL24I CLOCK 24-MHz crystal or external clock input 17 XTAL24O 18 VDDR 19 P0.0 20 P0.1 21 P0.2 22 P0.3 23 VDDD 24 P0.4 25 P0.5 fo r N 11 12 24-MHz crystal 1.9-V to 5.5-V radio supply en de d CLOCK POWER GPIO Port 0 Pin 0, analog/digital/lcd/csd GPIO Port 0 Pin 1, analog/digital/lcd/csd GPIO Port 0 Pin 2, analog/digital/lcd/csd GPIO Port 0 Pin 3, analog/digital/lcd/csd m POWER 1.71-V to 5.5-V digital supply GPIO Port 0 Pin 4, analog/digital/lcd/csd Port 0 Pin 5, analog/digital/lcd/csd GPIO Port 0 Pin 6, analog/digital/lcd/csd P0.7 GPIO Port 0 Pin 7, analog/digital/lcd/csd P1.0 GPIO Port 1 Pin 0, analog/digital/lcd/csd 29 P1.1 GPIO Port 1 Pin 1, analog/digital/lcd/csd 30 P1.2 GPIO Port 1 Pin 2, analog/digital/lcd/csd 31 P1.3 GPIO Port 1 Pin 3, analog/digital/lcd/csd 32 P1.4 GPIO Port 1 Pin 4, analog/digital/lcd/csd 33 P1.5 GPIO Port 1 Pin 5, analog/digital/lcd/csd 34 P1.6 GPIO Port 1 Pin 6, analog/digital/lcd/csd 27 ot R ec 28 om GPIO P0.6 26 N Description es ig Type D Name ew Pin ns Table 1. CYBL10X6X Pin List (QFN Package) 35 P1.7 GPIO 36 VDDA POWER 37 P2.0 GPIO Port 2 Pin 0, analog/digital/lcd/csd 38 P2.1 GPIO Port 2 Pin 1, analog/digital/lcd/csd 39 P2.2 GPIO Port 2 Pin 2, analog/digital/lcd/csd 40 P2.3 GPIO Port 2 Pin 3, analog/digital/lcd/csd Document Number: 001-90478 Rev. *L Port 1 Pin 7, analog/digital/lcd/csd 1.71-V to 5.5-V analog supply Page 8 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 1. CYBL10X6X Pin List (QFN Package) (continued) Type 41 P2.4 GPIO Port 2 Pin 4, analog/digital/lcd/csd 42 P2.5 GPIO Port 2 Pin 5, analog/digital/lcd/csd 43 P2.6 GPIO Port 2 Pin 6, analog/digital/lcd/csd 44 P2.7 GPIO Port 2 Pin 7, analog/digital/lcd/csd VREF REF 46 VDDA POWER 1.024-V reference 1.71-V to 5.5-V analog supply P3.0 GPIO Port 3 Pin 0, analog/digital/lcd/csd P3.1 GPIO Port 3 Pin 1, analog/digital/lcd/csd 49 P3.2 GPIO Port 3 Pin 2, analog/digital/lcd/csd 50 P3.3 GPIO Port 3 Pin 3, analog/digital/lcd/csd 51 P3.4 GPIO Port 3 Pin 4, analog/digital/lcd/csd 52 P3.5 GPIO Port 3 Pin 5, analog/digital/lcd/csd 53 P3.6 GPIO Port 3 Pin 6, analog/digital/lcd/csd 54 P3.7 GPIO Port 3 Pin 7, analog/digital/lcd/csd 55 VSSA GROUND 56 VCCD POWER 57 EPAD GROUND Analog ground N ew 47 48 D 45 Description ns Name es ig Pin fo r Regulated 1.8-V supply; connect to 1-µF capacitor Ground paddle for the QFN package en de d Table 2 shows the pin list for the CYBL10X6X device (WLCSP package). Table 2. CYBL10X6X Pin List (WLCSP Package) Name A1 VREF A2 VSSA A3 P3.3 P3.7 A5 VSSD A6 VSSA A7 REF GROUND GPIO GPIO om A4 Type m Pin Analog ground Port 3 Pin 3, analog/digital/lcd/csd Port 3 Pin 7, analog/digital/lcd/csd GROUND Digital ground GROUND Analog ground VCCD POWER Regulated 1.8-V supply, connect to 1-μF capacitor VDDD POWER 1.71-V to 5.5-V digital supply P2.3 GPIO B2 VSSA GROUND B3 P2.7 GPIO Port 2 Pin 7, analog/digital/lcd/csd B4 P3.4 GPIO Port 3 Pin 4, analog/digital/lcd/csd B5 P3.5 GPIO Port 3 Pin 5, analog/digital/lcd/csd B6 P3.6 GPIO Port 3 Pin 6, analog/digital/lcd/csd B7 XTAL32I/P6.1 CLOCK A8 ot R ec B1 N Description 1.024-V reference Port 2 Pin 3, analog/digital/lcd/csd Analog ground 32.768-kHz crystal or external clock input B8 XTAL32O/P6.0 CLOCK C1 VSSA GROUND C2 P2.2 GPIO Port 2 Pin 2, analog/digital/lcd/csd C3 P2.6 GPIO Port 2 Pin 6, analog/digital/lcd/csd C4 P3.0 GPIO Port 3 Pin 0, analog/digital/lcd/csd Document Number: 001-90478 Rev. *L 32.768-kHz crystal Analog ground Page 9 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 2. CYBL10X6X Pin List (WLCSP Package) (continued) Pin Name Type Description C5 P3.1 GPIO Port 3 Pin 1, analog/digital/lcd/csd Port 3 Pin 2, analog/digital/lcd/csd P3.2 GPIO C7 XRES RESET C8 P4.0 GPIO Port 4 Pin 0, analog/digital/lcd/csd D1 P1.7 GPIO Port 1 Pin 7, analog/digital/lcd/csd D2 VDDA POWER D3 P2.0 GPIO Port 2 Pin 0, analog/digital/lcd/csd D4 P2.1 GPIO Port 2 Pin 1, analog/digital/lcd/csd D5 P2.5 GPIO Port 2 Pin 5, analog/digital/lcd/csd D6 VSSD GROUND D7 P4.1 GPIO Port 4 Pin 1, analog/digital/lcd/csd D8 P5.0 GPIO Port 5 Pin 0, analog/digital/lcd/csd, overvoltage-tolerant E1 P1.2 GPIO Port 1 Pin 2, analog/digital/lcd/csd E2 P1.3 GPIO Port 1 Pin 3, analog/digital/lcd/csd E3 P1.4 GPIO Port 1 Pin 4, analog/digital/lcd/csd E4 P1.5 GPIO Port 1 Pin 5, analog/digital/lcd/csd E5 P1.6 GPIO Port 1 Pin 6, analog/digital/lcd/csd E8 VSSD F1 VSSD F2 P0.7 F3 P0.3 F4 P1.0 F5 P1.1 F6 VSSR Port 2 Pin 4, analog/digital/lcd/csd Port 5 Pin 1, analog/digital/lcd/csd, overvoltage-tolerant GROUND Digital ground GROUND Digital ground GPIO Port 0 Pin 7, analog/digital/lcd/csd GPIO Port 0 Pin 3, analog/digital/lcd/csd GPIO Port 1 Pin 0, analog/digital/lcd/csd GPIO Port 1 Pin 1, analog/digital/lcd/csd Radio ground GROUND Radio ground VDDR POWER P0.6 GPIO G2 VDDD POWER G3 P0.2 GPIO G4 VSSD GROUND Digital ground G5 VSSR GROUND Radio ground N ot G1 om GROUND F8 es ig GPIO GPIO VSSR F7 ew fo r N Digital ground D 1.71-V to 5.5-V analog supply en de d P5.1 m P2.4 E7 Reset, active LOW R ec E6 ns C6 1.9-V to 5.5-V radio supply Port 0 Pin 6, analog/digital/lcd/csd 1.71-V to 5.5-V digital supply Port 0 Pin 2, analog/digital/lcd/csd G6 VSSR GROUND Radio ground G7 GANT GROUND Antenna shielding ground G8 VSSR GROUND Radio ground H1 P0.5 GPIO Port 0 Pin 5, analog/digital/lcd/csd Port 0 Pin 1, analog/digital/lcd/csd H2 P0.1 GPIO H3 XTAL24O CLOCK 24-MHz crystal H4 XTAL24I CLOCK 24-MHz crystal or external clock input Document Number: 001-90478 Rev. *L Page 10 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 2. CYBL10X6X Pin List (WLCSP Package) (continued) Pin Name Type Description H5 VSSR GROUND H6 VSSR GROUND Radio ground H7 ANT ANTENNA Antenna pin J1 P0.4 GPIO Port 0 Pin 4, analog/digital/lcd/csd J2 P0.0 GPIO Port 0 Pin 0, analog/digital/lcd/csd J3 VDDR POWER 1.9-V to 5.5-V radio supply J6 VDDR POWER 1.9-V to 5.5-V radio supply J7 NO CONNECT - D es ig ns Radio ground ew The I/O subsystem consists of a high-speed I/O matrix (HSIOM), which is a group of high-speed switches that routes GPIOs to the resources inside the device. These resources include CapSense, TCPWMs, I2C, SPI, UART, and LCD. HSIOM_PORT_SELx are 32-bit-wide registers that control the routing of GPIOs. Each register controls one port; four dedicated bits are assigned to each GPIO in the port. This provides up to 16 different options for GPIO routing as shown in Table 3. Value N Table 3. HSIOM Port Settings Description Firmware-controlled GPIO 1 Reserved 2 Reserved 3 Reserved 4 Pin is a CSD sense pin 5 Pin is a CSD shield pin 6 Pin is connected to AMUXA 7 Pin is connected to AMUXB 8 Pin-specific Active function #0 9 Pin-specific Active function #1 10 Pin-specific Active function #2 11 Reserved 12 Pin is an LCD common pin 13 Pin is an LCD segment pin 14 Pin-specific Deep-Sleep function #0 15 Pin-specific Deep-Sleep function #1 R ec om m en de d fo r 0 The selection of peripheral functions for different GPIO pins is given in Table 4. Table 4. Port Pin Connections[1] ot Name Analog Digital (HSIOM_PORT_SELx.SELy) ('x' denotes port number and 'y' denotes pin number) 0 8 9 10 Active #2 14 15 Active #0 Active #1 Deep Sleep #0 Deep Sleep #1 GPIO TCPWM0_P[3] SCB1_UART_RX[1] SCB1_I2C_SDA[1] SCB1_SPI_MOSI[1] P0.1 GPIO TCPWM0_N[3] SCB1_UART_TX[1] SCB1_I2C_SCL[1] SCB1_SPI_MISO[1] P0.2 GPIO TCPWM1_P[3] SCB1_UART_RTS[1] 'SCB1_SPI_SS0[1]' P0.3 GPIO TCPWM1_N[3] SCB1_UART_CTS[1] SCB1_SPI_SCLK[1] N GPIO P0.0 Note 1. For devices with only 1 SCB, use pins corresponding to SCB1. Document Number: 001-90478 Rev. *L Page 11 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 4. Port Pin Connections[1] (continued) Digital (HSIOM_PORT_SELx.SELy) ('x' denotes port number and 'y' denotes pin number) Analog 0 8 9 10 14 15 ns Name GPIO Active #0 Active #1 Active #2 Deep Sleep #0 P0.4 GPIO TCPWM1_P[0] SCB0_UART_RX[1] EXT_CLK[0]/ ECO_OUT[0] SCB0_I2C_SDA[1] P0.5 GPIO TCPWM1_N[0] SCB0_UART_TX[1] SCB0_I2C_SCL[1] SCB0_SPI_MISO[1] P0.6 GPIO TCPWM2_P[0] SCB0_UART_RTS[1] SWDIO[0] SCB0_SPI_SS0[1] P0.7 GPIO TCPWM2_N[0] SCB0_UART_CTS[1] SWDCLK[0] SCB0_SPI_SCLK[1] P1.0 GPIO TCPWM0_P[1] P1.1 GPIO TCPWM0_N[1] P1.2 GPIO TCPWM1_P[1] P1.3 GPIO TCPWM1_N[1] P1.4 GPIO TCPWM2_P[1] SCB0_UART_RX[0] P1.5 GPIO TCPWM2_N[1] SCB0_UART_TX[0] P1.6 GPIO TCPWM3_P[1] SCB0_UART_RTS[0] P1.7 GPIO TCPWM3_N[1] SCB0_UART_CTS[0] P2.0 GPIO P2.1 GPIO P2.2 GPIO P2.3 GPIO P2.4 GPIO P2.5 GPIO P2.6 GPIO P2.7 GPIO P3.0 SARMUX_0 GPIO P3.1 SARMUX_1 GPIO P3.2 es ig D ew N SCB1_SPI_SS1 SCB1_SPI_SS2 SCB1_SPI_SS3 SCB0_I2C_SDA[0] SCB0_SPI_MOSI[1] SCB0_I2C_SCL[0] SCB0_SPI_MISO[1] SCB0_SPI_SS0[1] SCB0_SPI_SCLK[1] fo r en de d m WCO_OUT[2] SCB0_SPI_SS1 SCB0_SPI_SS2 WAKEUP SCB0_SPI_SS3 WCO_OUT[1] EXT_CLK[1]/ ECO_OUT[1] SCB0_I2C_SDA[2] TCPWM0_N[2] SCB0_UART_TX[2] SCB0_I2C_SCL[2] SARMUX_2 GPIO TCPWM1_P[2] SCB0_UART_RTS[2] P3.3 SARMUX_3 GPIO TCPWM1_N[2] SCB0_UART_CTS[2] P3.4 SARMUX_4 GPIO TCPWM2_P[2] SCB1_UART_RX[2] SCB1_I2C_SDA[2] P3.5 SARMUX_5 GPIO TCPWM2_N[2] SCB1_UART_TX[2] SCB1_I2C_SCL[2] P3.6 SARMUX_6 GPIO TCPWM3_P[2] SCB1_UART_RTS[2] P3.7 SARMUX_7 GPIO TCPWM3_N[2] SCB1_UART_CTS[2] WCO_OUT[0] R ec om SCB0_UART_RX[2] ot TCPWM0_P[2] Deep Sleep #1 SCB0_SPI_MOSI[1] CMOD GPIO TCPWM0_P[0] SCB1_UART_RTS[0] SCB1_SPI_MOSI[0] P4.1 CTANK GPIO TCPWM0_N[0] SCB1_UART_CTS[0] SCB1_SPI_MISO[0] P5.0 GPIO TCPWM3_P[0] SCB1_UART_RX[0] EXTPA_EN SCB1_I2C_SDA[0] SCB1_SPI_SS0[0] P5.1 GPIO TCPWM3_N[0] SCB1_UART_TX[0] EXT_CLK[2]/ ECO_OUT[2] SCB1_I2C_SCL[0] SCB1_SPI_SCLK[0] P6.0_XTAL32O GPIO P6.1_XTAL32I GPIO N P4.0 Document Number: 001-90478 Rev. *L Page 12 of 42 PRoC BLE: CYBL10X6X Family Datasheet Power Power Supply Table 5. Power Modes System Status 850 µA + 260 µA per MHz[2] Sleep 1.1 mA at 3 MHz 0.1-µF ceramic at each pin plus bulk capacitor 1 µF to 10 µF VDDR 0.1-µF ceramic at each pin plus bulk capacitor 1 µF to 10 µF VCCD 1-µF ceramic capacitor at the VCCD pin VREF (optional) The internal bandgap may be bypassed with a 1-µF to 10-µF capacitor Low-Power Modes es ig ns VDDA N ew PRoC BLE supports five power modes. Refer to Table 5 for more details on the system status. The PRoC BLE device consumes the lowest current in Stop mode; the device wakeup from stop mode is with a system reset through the XRES or WAKEUP pin. It can retain the SRAM data in Hibernate mode and is capable of retaining the complete system status in Deep-Sleep mode. Table 5 shows the different power modes and the peripherals that are active. Code Execution Digital Peripherals Available Analog Peripherals Available Clock Sources Available Wake Up Sources Wake-Up Time Yes All All All – – No All All All Any interrupt source 0 No WDT, LCD, I2C/SPI, Link-Layer POR, BOD WCO, ILO GPIO, WDT, I2C/SPI Link Layer 25 μs 1.3 μA Hibernate 150 nA No No POR, BOD No GPIO 2 ms 60 nA No No No No Wake-Up pin, XRES 2 ms N ot R ec Stop om Deep Sleep m Active 0.1-µF ceramic at each pin plus bulk capacitor 1 µF to 10 µF en de d Current Consumption Power Mode VDDD fo r Bypass capacitors must be used from VDDx (x = A, D, or R) to ground. The typical practice for systems in this frequency range is to use a capacitor in the 1-µF range in parallel with a smaller capacitor (for example, 0.1 µF). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to design to obtain optimal bypassing. Bypass Capacitors D PRoC BLE can be supplied from batteries with a voltage range of 1.9 V to 5.5 V by directly connecting to the digital supply (VDDD), analog supply (VDDA), and radio supply (VDDR) pins. The internal LDOs in the device regulate the supply voltage to required levels for different blocks. The device has one regulator for the digital circuitry and separate regulators for radio circuitry for noise isolation. The analog circuits run directly from the analog supply (VDDA) input. The device uses separate regulators for Deep Sleep and Hibernate modes to minimize the power consumption. The radio stops working below 1.9 V, but the rest of the system continues to function down to 1.71 V without RF. Note that VDDR must be supplied whenever VDDD is supplied. Note 2. For CPU subsystem. Document Number: 001-90478 Rev. *L Page 13 of 42 PRoC BLE: CYBL10X6X Family Datasheet A typical system application connection diagram for the 56-QFN package is shown in Figure 4. VDDA C1 1.0 uF U1 VDDD 1 2 L1 VDDR 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDA 15 16 17 18 19 20 21 22 23 24 25 26 27 28 C5 PRoC BLE 56-QFN N VDDR C6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 VDDA P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 fo r 1 2 ANTENNA VDDD XTAL32O/P6.0 XTAL32I/P6.1 XRES P4.0 P4.1 P5.0 P5.1 VSS VDDR GANT1 ANT GANT2 VDDR VDDR XTAL24I XTAL24O VDDR P0.0 P0.1 P0.2 P0.3 VDDD P0.4 P0.5 P0.6 P0.7 P1.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32.768KHz D 1 ew 2 EPAD VCCD VSSA P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 VDDA VREF P2.7 P2.6 Y2 es ig C4 18 pF 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 C3 36 pF C2 1.0 uF ns Figure 4. PRoC BLE Applications Diagram VDDD SWDIO SWDCLK 2 N ot R ec om m 3 Y1 24MHz 4 1 en de d VDDR Document Number: 001-90478 Rev. *L Page 14 of 42 PRoC BLE: CYBL10X6X Family Datasheet Component Datasheets: PSoC Creator Components provide hardware abstraction using APIs to configure and control peripheral activity. The Component datasheet covers Component features, its usage and operation details, API description, and electrical specifications. This is the primary documentation used during development. These Components can represent peripherals on the device (such as a timer, I2C, or UART) or high-level system functions (such as the BLE Component). ns Tools With industry-standard cores, programming, and debugging interfaces, the CYBL10X6X family is part of a development tool ecosystem. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy-to-use PSoC Creator IDE, supported third-party compilers, programmers, and debuggers. Kits Cypress provides a portfolio of kits to accelerate time-to-market. Visit us at www.cypress.com/procble. N ot R ec om m en de d fo r Application Notes: Application notes help you to understand how to use various device features. They also provide guidance on how to solve a variety of system design challenges. es ig A suite of documentation supports the CYBL10X6X family to ensure that you find answers to your questions quickly. This section contains a list of some of the key documents. In addition to the print documentation, Cypress forums connect you with fellow users and experts from around the world, 24 hours a day, 7 days a week. D Documentation Online ew The CYBL10X6X family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit www.cypress.com/procble to find out more. Technical Reference Manual (TRM): The TRM describes all peripheral functionality in detail, with register-level descriptions. This document is divided into two parts: the Architecture TRM and the Register TRM. N Development Support Document Number: 001-90478 Rev. *L Page 15 of 42 PRoC BLE: CYBL10X6X Family Datasheet Exposure to absolute maximum conditions for extended periods of time may affect device reliability. This section provides detailed electrical characteristics. Absolute maximum rating for the CYBL10X6X devices is listed in the following table. Usage above the absolute maximum conditions may cause permanent damage to the device. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions, but above normal operating conditions, the device may not operate to the specification. Absolute Maximum Ratings Table 6. Absolute Maximum Ratings Parameter Description Min Typ Max – 6 VDDD_ABS Analog, digital, or radio supply relative to VSS (VSSD = VSSA) –0.5 SID2 VCCD_ABS Direct digital core voltage input relative to VSSD –0.5 SID3 VGPIO_ABS GPIO voltage –0.5 SID4 IGPIO_ABS Maximum current per GPIO –25 – SID5 IGPIO_injection GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS –0.5 – BID57 ESD_HBM Electrostatic discharge human body model 2200[3] BID58 ESD_CDM Electrostatic discharge charged device model BID61 LU Pin current for latch up Parameter RF Receiver Specifications SID340 RXS, IDLE RXS, IDLE R ec SID340A Absolute max V Absolute max – VDD +0.5 V Absolute max 25 mA Absolute max 0.5 mA Absolute max, current injected per pin – – V 500 – – V –200 – 200 mA N 1.95 Details/ Conditions Typ Max Units RX sensitivity with idle transmitter – –89 – dBm RX sensitivity with idle transmitter excluding balun loss – –91 – dBm Guaranteed by design simulation RX sensitivity with dirty transmitter – –87 – dBm RF-PHY Specification (RCV-LE/CA/01/C) – –91 – dBm –10 –1 – dBm RF-PHY Specification (RCV-LE/CA/06/C) – 9 21 dB RF-PHY Specification (RCV-LE/CA/03/C) RXS, DIRTY SID342 RXS, HIGHGAIN RX sensitivity in high-gain mode with idle transmitter SID343 PRXMAX Maximum input power SID344 CI1 Co-channel interference, Wanted signal at –67 dBm and Interferer at FRX ot V Min SID341 N Details/ Conditions – fo r Description om Spec ID# en de d Table 7. BLE Subsystem m BLE Subsystem ew SID1 Units D Spec ID# es ig ns Electrical Specifications Note 3. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM. Document Number: 001-90478 Rev. *L Page 16 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 7. BLE Subsystem (continued) Parameter Description Min Typ Max Units Details/ Conditions CI2 Adjacent channel interference Wanted signal at –67 dBm and Interferer at FRX ±1 MHz – 3 15 dB RF-PHY Specification (RCV-LE/CA/03/C) SID346 CI3 Adjacent channel interference Wanted signal at –67 dBm and Interferer at FRX ±2 MHz – –29 – dB RF-PHY Specification (RCV-LE/CA/03/C) SID347 CI4 Adjacent channel interference Wanted signal at –67 dBm and Interferer at ≥FRX ±3 MHz – –39 – dB RF-PHY Specification (RCV-LE/CA/03/C) SID348 CI5 Adjacent channel interference Wanted Signal at –67 dBm and Interferer at Image frequency (FIMAGE) – –20 – SID349 CI3 Adjacent channel interference Wanted signal at –67 dBm and Interferer at Image frequency (FIMAGE ± 1 MHz) – SID350 OBB1 Out-of-band blocking, Wanted signal at –67 dBm and Interferer at F = 30–2000 MHz –30 SID351 OBB2 Out-of-band blocking, Wanted signal at –67 dBm and Interferer at F = 2,003–2,399 MHz SID352 OBB3 SID353 OBB4 SID354 IMD SID355 RXSE1 D es ig ns SID345 ew Spec ID# dB RF-PHY Specification (RCV-LE/CA/03/C) – dB RF-PHY Specification (RCV-LE/CA/03/C) –27 – dBm RF-PHY Specification (RCV-LE/CA/04/C) –35 –27 – dBm RF-PHY Specification (RCV-LE/CA/04/C) Out-of-band blocking, Wanted signal at –67 dBm and Interferer at F = 2,484–2,997 MHz –35 –27 – dBm RF-PHY Specification (RCV-LE/CA/04/C) Out-of-band blocking, Wanted signal a –67 dBm and Interferer at F = 3,000–12,750 MHz –30 –27 – dBm RF-PHY Specification (RCV-LE/CA/04/C) Intermodulation performance Wanted signal at –64 dBm and 1-Mbps BLE, third, fourth, and fifth offset channel –50 – – dBm RF-PHY Specification (RCV-LE/CA/05/C) Receiver spurious emission 30 MHz to 1.0 GHz – – –57 dBm 100-kHz measurement bandwidth ETSI EN300 328 V1.8.1 Receiver spurious emission 1.0 GHz to 12.75 GHz – – –47 dBm 1-MHz measurement bandwidth ETSI EN300 328 V1.8.1 RF Transmitter Specifications SID357 TXP, ACC RF power accuracy – ±1 – dB SID358 TXP, RANGE RF power control range – 20 – dB SID359 TXP, 0 dBm Output power, 0-dB gain setting (PA7) – 0 – dBm N fo r en de d m om R ec RXSE2 N ot SID356 –30 Document Number: 001-90478 Rev. *L Page 17 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 7. BLE Subsystem (continued) Parameter Description Min Typ Max Units TXP, MAX Output power, maximum power setting (PA10) – 3 – dBm SID361 TXP, MIN Output power, minimum power setting (PA1) – –18 – dBm SID362 F2AVG Average frequency deviation for 10101010 pattern 185 – – SID363 F1AVG Average frequency deviation for 11110000 pattern 225 250 275 SID364 EO Eye opening = ∆F2AVG/∆F1AVG 0.8 – – SID365 FTX, ACC Frequency accuracy –150 – 150 SID366 FTX, MAXDR Maximum frequency drift –50 SID367 FTX, INITDR Initial frequency drift –20 SID368 FTX,DR Maximum drift rate –20 SID369 IBSE1 In-band spurious emission at 2-MHz offset SID370 IBSE2 In-band spurious emission at ≥3-MHz offset SID371 TXSE1 SID372 TXSE2 RF-PHY Specification (TRM-LE/CA/05/C) kHz RF-PHY Specification (TRM-LE/CA/05/C) ew D kHz kHz RF-PHY Specification (TRM-LE/CA/06/C) 50 kHz RF-PHY Specification (TRM-LE/CA/06/C) – 20 kHz RF-PHY Specification (TRM-LE/CA/06/C) – 20 kHz/ 50 µs RF-PHY Specification (TRM-LE/CA/06/C) fo r N – – –20 dBm RF-PHY Specification (TRM-LE/CA/03/C) – – –30 dBm RF-PHY Specification (TRM-LE/CA/03/C) Transmitter spurious emissions (average), 1.0 GHz – – –41.5 dBm FCC-15.247 Receive current in normal mode – 18.7 – mA Receive current in normal mode – 16.4 – mA Receive current in high-gain mode – 21.5 – mA IRX SID373A IRX_RF SID374 IRX, HIGHGAIN SID375 ITX, 3 dBm TX current at 3-dBm setting (PA10) – 20 – mA SID376 ITX, 0 dBm TX current at 0-dBm setting (PA7) – 16.5 – mA om m SID373 R ec RF-PHY Specification (TRM-LE/CA/05/C) – en de d RF Current Specification es ig SID360 Details/ Conditions ns Spec ID# Measured at VDDR ITX_RF, 0 dBm TX current at 0-dBm setting (PA7) – 15.6 – mA Measured at VDDR SID376B ITX_RF, 0 dBm TX current at 0 dBm excluding Balun loss – 14.2 – mA Guaranteed by design simulation SID377 ITX, -3 dBm TX current at –3-dBm setting (PA4) – 15.5 – mA SID378 ITX, -6 dBm TX current at –6-dBm setting (PA3) – 14.5 – mA SID379 ITX, -12 dBm TX current at –12-dBm setting (PA2) – 13.2 – mA SID380 ITX, -18 dBm TX current at –18-dBm setting (PA1) – 12.5 – mA SID380A Iavg_1sec, 0dBm Average current at 1-second BLE connection interval – 18.9 – µA N ot SID376A Document Number: 001-90478 Rev. *L TXP: 0 dBm; ±20-ppm master and slave clock accuracy. For empty PDU exchange Page 18 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 7. BLE Subsystem (continued) Min Typ Max Units Details/ Conditions – 6.25 – µA TXP: 0 dBm; ±20-ppm master and slave clock accuracy. For empty PDU exchange 2400 – 2482 Description Iavg_4sec, 0dBm Average current at 4-second BLE connection interval SID381 FREQ RF operating frequency SID382 CHBW Channel spacing – 2 – SID383 DR On-air data rate – 1000 – SID384 IDLE2TX BLE Radio Idle to BLE Radio TX transition time – 120 140 SID385 IDLE2RX BLE Radio Idle to BLE Radio RX transition time – ew General RF Specification MHz D MHz kbps µs 120 µs RSSI, ACC RSSI accuracy – ±5 – dB SID387 RSSI, RES RSSI resolution – 1 – dB SID388 RSSI, PER RSSI sample period – 6 – µs en de d Device-Level Specifications fo r SID386 N RSSI Specification 75 ns SID380B Parameter es ig Spec ID# All specifications are valid for –40 °C  TA  105 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Table 8. DC Specifications SID6 VDD SID7 VDD SID8 VDDR SID8A VDDR SID10 Min Typ Max Units Power supply input voltage (VDDA = VDDD = VDD) 1.8 – 5.5 V Power supply input voltage unregulated (VDDA = VDDD = VDD) 1.71 1.8 1.89 V Radio supply voltage (Radio on) 1.9 – 5.5 V Radio supply voltage (Radio off) 1.71 – 5.5 V Details/ Conditions With regulator enabled Internally unregulated supply VCCD Digital regulator output voltage (for core logic) – 1.8 – V CVCCD Digital regulator output bypass capacitor 1 1.3 1.6 µF Execute from flash; CPU at 3 MHz – 1.7 – mA T = 25 °C, VDD = 3.3 V R ec SID9 Description m Parameter om Spec ID# X5R ceramic or better Active Mode, VDD = 1.71 V to 5.5 V IDD3 SID14 IDD4 Execute from flash; CPU at 3 MHz – – – mA T = –40 °C to 105 °C SID15 IDD5 Execute from flash; CPU at 6 MHz – 2.5 – mA T = 25 °C, VDD = 3.3 V N ot SID13 SID16 IDD6 Execute from flash; CPU at 6 MHz – – – mA T = –40 °C to 105 °C SID17 IDD7 Execute from flash; CPU at 12 MHz – 4 – mA T = 25 °C, VDD = 3.3 V SID18 IDD8 Execute from flash; CPU at 12 MHz – – – mA T = –40 °C to 105 °C Document Number: 001-90478 Rev. *L Page 19 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 8. DC Specifications (continued) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions IDD9 Execute from flash; CPU at 24 MHz – 7.1 – mA T = 25 °C, VDD = 3.3 V SID20 IDD10 Execute from flash; CPU at 24 MHz – – – mA T = –40 °C to 105 °C SID21 IDD11 Execute from flash; CPU at 48 MHz – 13.4 – mA T = 25 °C, VDD = 3.3 V SID22 IDD12 Execute from flash; CPU at 48 MHz – – – mA T = –40 °C to 105 °C – – – mA T = 25 °C, VDD = 3.3 V, SYSCLK = 3 MHz – mA T = 25 °C, VDD = 3.3 V, SYSCLK = 3 MHz SID24 IDD14 ECO on – Deep-Sleep Mode, VDD = 1.8 V to 3.6 V es ig ew Sleep Mode, VDD and VDDR = 1.9 V to 5.5 V – N IMO on IDD13 D Sleep Mode, VDD = 1.8 V to 5.5 V SID23 ns SID19 IDD15 WDT with WCO on – 1.3 – µA T = 25 °C, VDD = 3.3 V SID26 IDD16 WDT with WCO on fo r SID25 – SID27 IDD17 WDT with WCO on – – – µA T = 25 °C, VDD = 5 V SID28 IDD18 WDT with WCO on – – – µA T = –40 °C to 105 °C en de d Deep-Sleep Mode, VDD = 3.6 V to 5.5 V – – µA T = –40 °C to 105 °C Deep-Sleep Mode, VDD = 1.71 V to 1.89 V (Regulator Bypassed) SID29 IDD19 WDT with WCO on – – – µA T = 25 °C SID30 IDD20 WDT with WCO on – – – µA T = –40 °C to 105 °C GPIO and reset active – 150 – nA T = 25 °C, VDD = 3.3 V GPIO and reset active – – – nA T = –40 °C to 105 °C GPIO and reset active – – – nA T = 25 °C, VDD = 5 V GPIO and reset active – – – nA T = –40 °C to 105 °C IDD27 SID38 IDD28 om SID37 m Hibernate Mode, VDD = 1.8 V to 3.6 V Hibernate Mode, VDD = 3.6 V to 5.5 V IDD29 R ec SID39 SID40 IDD30 Hibernate Mode, VDD = 1.71 V to 1.89 V (Regulator Bypassed) IDD31 GPIO and reset active – – – nA T = 25 °C SID42 IDD32 GPIO and reset active – – – nA T = –40 °C to 105 °C ot SID41 Stop Mode, VDD = 1.8 V to 3.6 V IDD33 Stop-mode current (VDD) – 20 – nA T = 25 °C, VDD = 3.3 V SID44 IDD34 Stop-mode current (VDDR) – 40 –- nA T = 25 °C, VDDR = 3.3 V SID45 IDD35 Stop-mode current (VDD) – – – nA T = –40 °C to 105 °C SID46 IDD36 Stop-mode current (VDDR) – – – nA T = –40 °C to 105 °C, VDDR = 1.9 V to 3.6 V N SID43 Document Number: 001-90478 Rev. *L Page 20 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 8. DC Specifications (continued) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions ns Stop Mode, VDD = 3.6 V to 5.5 V IDD37 Stop-mode current (VDD) – – – nA T = 25 °C, VDD = 5 V SID48 IDD38 Stop-mode current (VDDR) – – – nA T = 25 °C, VDDR = 5 V SID49 IDD39 Stop-mode current (VDD) – – – nA T = –40 °C to 105 °C SID50 IDD40 Stop-mode current (VDDR) – – – nA T = –40 °C to 105 °C D Stop Mode, VDD = 1.71 V to 1.89 V (Regulator Bypassed) es ig SID47 IDD41 Stop-mode current (VDD) – – – nA T = 25 °C SID52 IDD42 Stop-mode current (VDD) – – – nA T = –40 °C to 105 °C Table 9. AC Specifications Parameter Description Min Details/ Conditions Typ Max Units DC – 48 MHz – 0 – µs Guaranteed by characterization – – 25 µs 24-MHz IMO. Guaranteed by characterization N Spec ID# ew SID51 1.71 V VDD 5.5 V FCPU CPU frequency SID54 TSLEEP Wakeup from Sleep mode SID55 TDEEPSLEEP Wakeup from Deep-Sleep mode SID56 THIBERNATE Wakeup from Hibernate mode – – 2 ms Guaranteed by characterization SID57 TSTOP Wakeup from Stop mode – – 2 ms Guaranteed by characterization Min Typ Max Units Input voltage HIGH threshold 0.7 × VDD – – V CMOS input Input voltage LOW threshold – – 0.3 × VDD V CMOS input SID58 VIH SID59 VIL SID60 m Parameter VIH Description om Spec ID# en de d GPIO Table 10. GPIO DC Specifications fo r SID53 0.7 × VDD – - V SID61 VIL LVTTL input, VDD < 2.7 V – – 0.3× VDD V SID62 VIH LVTTL input, VDD ≥ 2.7 V 2.0 – - V SID63 VIL LVTTL input, VDD ≥ 2.7 V – – 0.8 V SID64 VOH Output voltage HIGH level VDD –0.6 – – V IOH = 4 mA at 3.3-V VDD ot R ec LVTTL input, VDD < 2.7 V Details/ Conditions VOH Output voltage HIGH level VDD –0.5 – – V IOH = 1 mA at 1.8-V VDD SID66 VOL Output voltage LOW level – – 0.6 V IOL = 8 mA at 3.3-V VDD SID67 VOL Output voltage LOW level – – 0.6 V IOL = 4 mA at 1.8-V VDD N SID65 Note 4. VIH must not exceed VDD + 0.2 V. Document Number: 001-90478 Rev. *L Page 21 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 10. GPIO DC Specifications (continued) SID68 Parameter Description VOL Output voltage LOW level Min Typ Max Units – – 0.4 V RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ RPULLDOWN Pull-down resistor 3.5 5.6 8.5 kΩ SID71 IIL Input leakage current (absolute value) – – 2 IIL_CTBM Input leakage on CTBm input pins – – 4 CIN Input capacitance – – 7 SID74 VHYSTTL Input hysteresis LVTTL 25 40 SID75 VHYSCMOS Input hysteresis CMOS 0.05 × VDD – SID76 IDIODE Current through protection diode to VDD/VSS – SID77 ITOT_GPIO Maximum total source or sink chip current – Parameter Description en de d Spec ID# 25 °C, VDD = 3.3 V nA pF mV – ew N – fo r Table 11. GPIO AC Specifications – nA D SID72 SID73 IOL = 3 mA at 3.3-V VDD es ig SID69 SID70 Details/ Conditions ns Spec ID# VDD > 2.7 V mV 100 µA 200 mA Min Typ Max Units Except for overvoltage-tolerant pins (P5.0 and P5.1) Details/ Conditions TRISEF Rise time in Fast-Strong mode 2 – 12 ns 3.3-V VDDD, CLOAD = 25 pF SID79 TFALLF Fall time in Fast-Strong mode 2 – 12 ns 3.3-V VDDD, CLOAD = 25 pF SID80 TRISES Rise time in Slow-Strong mode 10 – 60 ns 3.3-V VDDD, CLOAD = 25 pF SID81 TFALLS Fall time in Slow-Strong mode 10 – 60 ns 3.3-V VDDD, CLOAD = 25 pF SID82 FGPIOUT1 GPIO Fout; 3.3 V  VDD 5.5 V. Fast-Strong mode – – 33 MHz 90/10%, 25-pF load, 60/40 duty cycle SID83 FGPIOUT2 GPIO Fout; 1.7 VVDD 3.3 V. Fast-Strong mode – – 16.7 MHz 90/10%, 25-pF load, 60/40 duty cycle SID84 FGPIOUT3 GPIO Fout; 3.3 V VDD 5.5 V. Slow-Strong mode – – 7 MHz 90/10%, 25-pF load, 60/40 duty cycle SID85 FGPIOUT4 GPIO Fout; 1.7 V VDD 3.3 V. Slow-Strong mode – – 3.5 MHz 90/10%, 25-pF load, 60/40 duty cycle SID86 FGPIOIN GPIO input operating frequency. 1.71 V VDD 5.5 V – – 48 MHz 90/10% VIO Min Typ Max Units Details/ Conditions 10 µA 25°C, VDD = 0 V, VIH = 3.0 V 0.4 V IOL = 20 mA, VDD > 2.9 V ot R ec om m SID78 N Table 12. OVT GPIO DC Specifications (P5_0 and P5_1 Only) Spec ID# Parameter Description SID71A IIL Input leakage (absolute value). VIH > VDD SID66A VOL Output voltage LOW level Document Number: 001-90478 Rev. *L – – Page 22 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 13. OVT GPIO AC Specifications (P5_0 and P5_1 Only) Parameter Description Min Typ Max Units Details/ Conditions TRISE_OVFS Output rise time in Fast-Strong mode 1.5 – 12 ns 25-pF load, 10%–90%, VDD=3.3 V SID79A TFALL_OVFS Output fall time in Fast-Strong mode 1.5 – 12 ns 25-pF load, 10%–90%, VDD=3.3 V SID80A TRISESS Output rise time in Slow-Strong mode 10 – 60 ns 25-pF load, 10%-90%, VDD = 3.3 V SID81A TFALLSS Output fall time in Slow-Strong mode 10 – 25-pF load, 10%-90%, VDD = 3.3 V SID82A FGPIOUT1 GPIO FOUT; 3.3 V ≤ VDD ≤ 5.5 V Fast-Strong mode – SID83A FGPIOUT2 GPIO FOUT; 1.71 V ≤ VDD ≤ 3.3 V Fast-Strong mode – Table 14. XRES DC Specifications Description en de d SID87 Parameter es ig ew 60 ns 24 MHz 90/10%, 25-pF load, 60/40 duty cycle – 16 MHz 90/10%, 25-pF load, 60/40 duty cycle N – fo r XRES Spec ID# ns SID78A D Spec ID# VIH Input voltage HIGH threshold SID88 VIL Input voltage LOW threshold SID89 RPULLUP Pull-up resistor Typ Max Units 0.7 × VDDD – – V CMOS input – – 0.3 × VDDD V CMOS input 3.5 5.6 8.5 kΩ CIN Input capacitance – 3 – pF VHYSXRES Input voltage hysteresis – 100 – mV SID92 IDIODE Current through protection diode to VDD/VSS – – 100 µA m SID90 SID91 om Details/ Conditions Min Table 15. XRES AC Specifications Parameter R ec Spec ID# TRESETWIDTH Reset pulse width Min Typ Max Units 1 – – µs Details/ Conditions N ot SID93 Description Document Number: 001-90478 Rev. *L Page 23 of 42 PRoC BLE: CYBL10X6X Family Datasheet Analog Peripherals Temperature Sensor Parameter TSENSACC Description Temperature sensor accuracy Min Typ Max Units Details/Conditions –5 ±1 5 °C –40 to +85 °C SAR ADC Table 17. SAR ADC DC Specifications Parameter Description Min Typ Max Units D Spec ID# es ig Spec ID# SID155 A_RES Resolution – – 12 SID157 A_CHNIS_S Number of channels – single-ended – – 8 SID158 A-CHNKS_D Number of channels – differential – SID159 A-MONO Monotonicity – SID160 A_GAINERR Gain error – – ±0.1 % SID161 A_OFFSET Input offset voltage – – 2 mV 4 Differential inputs use neighboring I/O – – Yes N Input voltage range – single-ended SID164 A_VIND Input voltage range – differential SID165 A_INRES Input resistance SID166 A_INCAP SID312 VREFSAR 8 full-speed – fo r Current consumption A_VINS – – 1 mA VSS – VDDA V VSS – VDDA V – – 2.2 kΩ Input capacitance – – 10 pF Trimmed internal reference to SAR –1 – 1 % Min Typ Max Units 70 – – dB – dB With external reference Measured with 1-V VREF Percentage of Vbg (1.024 V) m en de d A_ISAR SID163 Details/Conditions bits ew SID156 SID162 ns Table 16. Temperature Sensor Specifications Spec ID# Parameter A_PSRR Description Power supply rejection ratio R ec SID167 om Table 18. SAR ADC AC Specifications Measured at 1-V reference A_CMRR Common-mode rejection ratio 66 – SID169 A_SAMP Sample rate – – 1 Msps SID313 Fsarintref SAR operating speed without external reference bypass – – 100 Ksps SID170 A_SNR Signal-to-noise ratio (SNR) 65 – – dB SID171 A_BW Input bandwidth without aliasing – – A_SAMP/ 2 kHz SID172 A_INL Integral nonlinearity (INL). VDD = 1.71 V to 5.5 V, 1 Msps –1.7 – 2 LSB VREF = 1 V to VDD SID173 A_INL Integral nonlinearity. VDDD = 1.71 V to 3.6 V, 1 Msps –1.5 – 1.7 LSB VREF = 1.71 V to VDD SID174 A_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps –1.5 – 1.7 LSB VREF = 1 V to VDD N ot SID168 Details/ Conditions Document Number: 001-90478 Rev. *L 12-bit resolution FIN = 10 kHz Page 24 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 18. SAR ADC AC Specifications (continued) Spec ID# Parameter Description Min Typ Max Units Details/ Conditions A_DNL Differential nonlinearity (DNL). VDD = 1.71 V to 5.5 V, 1 Msps –1 – 2.2 LSB VREF = 1 V to VDD SID176 A_DNL Differential nonlinearity. VDD = 1.71 V to 3.6 V, 1 Msps –1 – 2 LSB VREF = 1.71 V to VDD SID177 A_DNL Differential nonlinearity. VDD = 1.71 V to 5.5 V, 500 Ksps –1 – 2.2 SID178 A_THD Total harmonic distortion – – –65 Description Min Typ Max Units VCSD Voltage range of operation 1.71 – 5.5 V IDAC1 DNL for 8-bit resolution –1 – 1 LSB SID181 IDAC1 INL for 8-bit resolution –3 – 3 LSB SID182 IDAC2 DNL for 7-bit resolution –1 – 1 LSB SID183 IDAC2 INL for 7-bit resolution –3 – 3 LSB SID184 SNR Ratio of counts of finger to noise 5 – – Ratio SID185 IDAC1_CRT1 Output current of IDAC1 (8 bits) in HIGH range – 612 – µA SID186 IDAC1_CRT2 Output current of IDAC1 (8 bits) in LOW range – 306 – µA SID187 IDAC2_CRT1 Output current of IDAC2 (7 bits) in HIGH range – 305 – µA SID188 IDAC2_CRT2 Output current of IDAC2 (7 bits) in LOW range – 153 – µA es ig dB VREF = 1 V to VDD FIN = 10 kHz N fo r en de d m Details/ Conditions Capacitance range of 9 pF to 35 pF; 0.1-pF sensitivity. Radio is not operating during the scan N ot R ec SID180 om SID179 Parameter ew Table 19. CSD Block Specifications Spec ID# LSB D CSD ns SID175 Document Number: 001-90478 Rev. *L Page 25 of 42 PRoC BLE: CYBL10X6X Family Datasheet Digital Peripherals 4x TCPWM Table 20. Timer DC Specifications Description Block current consumption at 3 MHz SID189A SID190 ITIM2 Block current consumption at 12 MHz ITIM3 Block current consumption at 48 MHz SID190A SID191 Typ – Max 42 Units µA Details/Conditions 16-bit timer, 85 °C – – 46 µA 16-bit timer, 105 °C – – 130 µA 16-bit timer, 85 °C – – 137 µA 16-bit timer, 105 °C – – 535 µA 16-bit timer, 85 °C – – 560 µA 16-bit timer, 105 °C Min FCLK Typ – Max 48 Units MHz – – ns D SID191A Min – Spec ID SID192 Parameter TTIMFREQ Description Operating frequency SID193 TCAPWINT Capture pulse width (internal) 2 × TCLK SID194 TCAPWEXT Capture pulse width (external) 2 × TCLK SID195 TTIMRES Timer resolution SID196 TTENWIDINT Enable pulse width (internal) SID197 TTENWIDEXT Enable pulse width (external) SID198 TTIMRESWINT Reset pulse width (internal) SID199 TTIMRESEXT Reset pulse width (external) ew Table 21. Timer AC Specifications – ns – – ns 2 × TCLK – – ns fo r N – TCLK Details/Conditions 2 × TCLK – – ns 2 × TCLK – – ns 2 × TCLK – – ns Min – Typ – Max 42 – – 46 µA 16-bit timer, 105 °C – – 130 µA 16-bit timer, 85 °C – – 137 µA 16-bit timer, 105 °C – – 535 µA 16-bit timer, 85 °C – – 560 µA 16-bit timer, 105 °C Min FCLK Typ – Max 48 Units MHz en de d Counter ns Parameter ITIM1 es ig Spec ID SID189 Table 22. Counter DC Specifications Spec ID SID200 Parameter ICTR1 Description Block current consumption at 3 MHz SID200A ICTR2 Block current consumption at 12 MHz ICTR3 Block current consumption at 48 MHz m SID201 SID202 SID202A om SID201A Units Details/Conditions µA 16-bit timer, 85 °C R ec Table 23. Counter AC Specifications Parameter TCTRFREQ Description Operating frequency SID204 TCTRPWINT Capture pulse width (internal) 2 × TCLK – – ns SID205 TCTRPWEXT Capture pulse width (external) 2 × TCLK – – ns SID206 TCTRES Counter resolution TCLK – – ns ot Spec ID SID203 TCENWIDINT Enable pulse width (internal) 2 × TCLK – – ns SID208 TCENWIDEXT Enable pulse width (external) 2 × TCLK – – ns N SID207 SID209 TCTRRESWINT Reset pulse width (internal) 2 × TCLK – – ns SID210 TCTRRESWEXT Reset pulse width (external) 2 × TCLK – – ns Document Number: 001-90478 Rev. *L Details/Conditions Page 26 of 42 PRoC BLE: CYBL10X6X Family Datasheet Pulse Width Modulation (PWM) Table 24. PWM DC Specifications Block current consumption at 3 MHz SID211A SID212 IPWM2 Block current consumption at 12 MHz SID212A SID213 IPWM3 Block current consumption at 48 MHz SID213A Min Typ Max – – 42 µA 16-bit timer, 85 °C – – 46 µA 16-bit timer, 105 °C Parameter Description µA 16-bit timer, 85 °C 16-bit timer, 105 °C µA 16-bit timer, 85 °C µA 16-bit timer, 105 °C – 130 – 137 – – 535 – – 560 Min Typ Max Units – 48 MHz – – ns – – ns – – ns TPWMFREQ Operating frequency FCLK TPWMPWINT Pulse width (internal) 2 × TCLK SID216 TPWMEXT Pulse width (external) 2 × TCLK SID217 TPWMKILLINT Kill pulse width (internal) 2 × TCLK SID218 TPWMKILLEXT Kill pulse width (external) 2 × TCLK – – ns SID219 TPWMEINT Enable pulse width (internal) 2 × TCLK – – ns SID220 TPWMENEXT Enable pulse width (external) SID221 TPWMRESWINT Reset pulse width (internal) SID222 TPWMRESWEXT Reset pulse width (external) Spec ID Parameter N fo r 2 × TCLK – – ns 2 × TCLK – – ns 2 × TCLK – – ns Min Typ Max Units en de d Table 26. I2C DC Specifications ew SID214 SID215 I2C Description II2C1 Block current consumption at 100 kHz – – 50 µA II2C2 Block current consumption at 400 kHz – – 155 µA SID225 II2C3 Block current consumption at 1 Mbps – – 390 µA SID226 II2C4 I2C enabled in Deep-Sleep mode – – 1.4 µA Min – Typ – Max 1 Units Mbps Min – Typ 17.5 Max – LCD capacitance per segment/common driver Long-term segment offset – 500 5000 – 20 – mV LCD system operating current. Vbias = 5 V LCD system operating current. Vbias = 3.3 V – 2 – mA – 2 – mA m SID223 SID224 om Details/Conditions µA – – Table 25. PWM AC Specifications Spec ID Units ns IPWM1 Description es ig SID211 Parameter D Spec ID Details/Conditions Details/Conditions Table 27. Fixed I2C AC Specifications Parameter FI2C1 Description Bit rate R ec Spec ID SID227 Details/Conditions LCD Direct Drive Table 28. LCD Direct Drive DC Specifications Parameter ILCDLOW SID229 CLCDCAP N ot Spec ID SID228 SID230 LCDOFFSET SID231 ILCDOP1 SID232 ILCDOP2 Description Operating current in low-power mode Document Number: 001-90478 Rev. *L Units Details/Conditions µA 16 × 4 small-segment display at 50 Hz pF 32 × 4 segments. 50 Hz. 25 °C 32 × 4 segments. 50 Hz. 25 °C Page 27 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 29. LCD Direct Drive AC Specifications Parameter FLCD Description LCD frame rate Min 10 Typ 50 Max 150 Units Hz Details/Conditions ns Spec ID SID233 Table 30. Fixed UART DC Specifications Parameter Description Min Typ Max Units µA SID234 IUART1 Block current consumption at 100 kbps – – 55 SID235 IUART2 Block current consumption at 1000 kbps – – 312 Min Typ Max Units – – 1 Mbps Parameter FUART Description Bit rate Min Typ Max Units – – 360 fo r Spec ID Parameter Description N SPI Specifications Table 32. Fixed SPI DC Specifications Details/Conditions ew Spec ID SID236 µA D Table 31. Fixed UART AC Specifications Details/Conditions es ig Spec ID µA – 560 µA – 600 µA Min Typ Max Units – – 8 MHz Min Typ Max Units MOSI valid after SCLK driving edge – – 18 ns MISO valid before SCLK capturing edge. Full clock, late MISO sampling used 20 – – ns Full clock, late MISO sampling Previous MOSI data hold time 0 – – ns Referred to Slave capturing edge ISPI1 Block current consumption at 1 Mbps SID238 ISPI2 Block current consumption at 4 Mbps – SID239 ISPI3 Block current consumption at 8 Mbps – en de d SID237 Details/Conditions Table 33. Fixed SPI AC Specifications Spec ID SID240 Parameter FSPI Description SPI operating frequency (master; 6x oversampling) Details/Conditions Table 34. Fixed SPI Master Mode AC Specifications TDMO SID242 TDSI SID243 THMO R ec SID241 Description m Parameter om Spec ID Details/Conditions Table 35. Fixed SPI Slave Mode AC Specifications Spec ID Parameter TDMI ot SID244 Min Typ Max Units MOSI valid before SCLK capturing edge Description 40 – – ns TDSO MISO valid after SCLK driving edge – – 42 + 3 × TSCB ns SID246 TDSO_ext MISO Valid after SCLK driving edge in external clock mode. VDD < 3.0 V – – 50 ns SID247 THSO Previous MISO data hold time 0 – – ns SID248 TSSELSCK SSEL valid to first SCK valid edge 100 – – ns N SID245 Document Number: 001-90478 Rev. *L Page 28 of 42 PRoC BLE: CYBL10X6X Family Datasheet Memory Table 36. Flash DC Specifications Description Min Typ Max Units 1.71 – 5.5 V Number of Wait states at 32–48 MHz 2 – – TWS32 Number of Wait states at 16–32 MHz 1 – – TWS16 Number of Wait states for 0–16 MHz 0 – – SID309 TWS48 SID310 SID311 CPU execution from flash CPU execution from flash CPU execution from flash Min Typ Max Units Details/Conditions TROWWRITE[5] Row (block) write time (erase and program) – – 20 ms Row (block) = 128 bytes SID251 TROWERASE[5] Row erase time – – 13 ms SID252 Row program time after erase – – 7 ms Bulk erase time (128 KB) – – 35 ms SID254 TROWPROGRAM[5] TBULKERASE[5] TDEVPROG[5] SID255 FEND Flash endurance SID256 FRET SID257 SID257A fo r – – 25 seconds 100 K – – cycles Flash retention. TA  55 °C, 100-K P/E cycles 20 – – years FRET2 Flash retention. TA  85 °C, 10-K P/E cycles 10 – – years FRET3 Flash retention. TA  105 °C, 10-K P/E cycles 3 – – years en de d Total device program time N Description SID250 SID253 Parameter ew Table 37. Flash AC Specifications Spec ID Details/Conditions D Erase and program voltage ns Parameter VPE es ig Spec ID SID249 Power-on-Reset (POR) m System Resources For TA ≥ 85 °C Spec ID om Table 38. POR DC Specifications Parameter Description Min Typ Max Units VRISEIPOR Rising trip voltage 0.80 – 1.45 V SID259 VFALLIPOR Falling trip voltage 0.75 – 1.40 V SID260 VIPORHYST Hysteresis 15 – 200 mV Description Min Typ Max Units Precision power-on reset (PPOR) response time in Active and Sleep modes – – 1 µs R ec SID258 Details/Conditions Table 39. POR AC Specifications Spec ID Parameter TPPOR_TR Details/Conditions N ot SID264 Note 5. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Document Number: 001-90478 Rev. *L Page 29 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 40. Brown-Out Detect Parameter Description Min Typ Max Units VFALLPPOR BOD trip voltage in Active and Sleep modes 1.64 – – V SID262 VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 – – V Min Typ Max Units 1.1 – – V SID263 Parameter VHBRTRIP Description BOD trip voltage in Hibernate ew Spec ID# Voltage Monitors (LVD) Parameter N Table 42. Voltage Monitor DC Specifications Spec ID D Table 41. Hibernate Reset es ig SID261 Description Min Typ Max Units 1.71 VLVI1 LVI_A/D_SEL[3:0] = 0000b SID266 VLVI2 LVI_A/D_SEL[3:0] = 0001b SID267 VLVI3 LVI_A/D_SEL[3:0] = 0010b SID268 VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V SID269 VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V SID270 VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V SID271 VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V SID272 VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V SID273 VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V SID274 VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V SID275 VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V SID276 VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V SID277 VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V SID278 VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V SID279 VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V SID280 VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V – – 100 µA Min Typ Max Units – – 1 µs en de d m om R ec LVI_IDD Block current 1.75 1.79 V 1.76 1.80 1.85 V 1.85 1.90 1.95 V fo r SID265 SID281 Details/ Conditions ns Spec ID# Details/ Conditions Details/ Conditions Table 43. Voltage Monitor AC Specifications Spec ID TMONTRIP Description Voltage monitor trip time Details/ Conditions N ot SID282 Parameter Document Number: 001-90478 Rev. *L Page 30 of 42 PRoC BLE: CYBL10X6X Family Datasheet SWD Interface Table 44. SWD Interface Specifications Spec ID Parameter Description Min Typ Max Units Details/Conditions F_SWDCLK1 3.3 V  VDD  5.5 V – – 14 MHz SWDCLK ≤ 1/3 CPU clock frequency SID284 F_SWDCLK2 1.71 V  VDD  3.3 V – – 7 MHz SWDCLK ≤ 1/3 CPU clock frequency SID285 T_SWDI_SETUP T = 1/f SWDCLK 0.25 × T – – SID286 T_SWDI_HOLD 0.25 × T – – SID287 T_SWDO_VALID T = 1/f SWDCLK – – 0.5 × T SID288 T_SWDO_HOLD T = 1/f SWDCLK 1 – – Table 45. IMO DC Specifications es ig Min Typ Max Units IMO operating current at 48 MHz – – 1000 µA SID290 IIMO2 IMO operating current at 24 MHz – SID291 IIMO3 IMO operating current at 12 MHz – SID292 IIMO4 IMO operating current at 6 MHz SID293 IIMO5 IMO operating current at 3 MHz Table 46. IMO AC Specifications Spec ID Parameter N Description ns IIMO1 – 325 µA – 225 µA – – 180 µA – – 150 µA fo r Parameter ns SID289 en de d Spec ID ns ew Internal Main Oscillator ns D T = 1/f SWDCLK Description ns SID283 Min Typ Max Units Details/Conditions Details/Conditions SID296 FIMOTOL3 Frequency variation from 3 to 48 MHz – – ±2 % SID297 FIMOTOL3 IMO startup time – 12 – µs Min Typ Max Units Details/Conditions – 0.3 1.05 µA Guaranteed by design m Internal Low-Speed Oscillator With API-called calibration Table 47. ILO DC Specifications SID298 Parameter IILO2 om Spec ID Description ILO operating current at 32 kHz R ec Table 48. ILO AC Specifications Min Typ Max Units SID299 Spec ID TSTARTILO1 Parameter ILO startup time Description – – 2 ms Details/Conditions SID300 FILOTRIM1 32-kHz trimmed frequency 15 32 50 kHz Min Typ Max Units Details/Conditions ot Table 49. External Clock Specifications Spec ID Parameter Description ExtClkFreq External clock input frequency 0 – 48 MHz CMOS input level only. TTL input is not supported SID302 ExtClkDuty Duty cycle; measured at VDD/2 45 – 55 % CMOS input level only. TTL input is not supported N SID301 Document Number: 001-90478 Rev. *L Page 31 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 50. ECO Specifications Parameter Description – 24 – MHz –50 – 50 ppm SID391 ESR Equivalent series resistance – – 60 SID392 PD Drive level – – 100 SID393 TSTART1 Startup time (Fast Charge on) – – 850 SID394 TSTART2 Startup time (Fast Charge off) – – 3 SID395 CL Load capacitance – 8 – SID396 C0 Shunt capacitance – 1.1 – pF SID397 IECO Operating current – 1400 – µA Ω µW µs ms pF Parameter Description Typ Max Units – 32.768 – kHz – 50 – ppm fo r Min en de d Table 51. WCO Specifications Spec ID# Details/ Conditions es ig Frequency tolerance Units D Crystal frequency FTOL Max ew FECO SID390 Typ Includes LDO+BG current N SID389 Min ns Spec ID# Details/ Conditions FWCO Crystal frequency SID399 FTOL Frequency tolerance SID400 ESR Equivalent series resistance – 50 – kΩ SID401 PD Drive level – – 1 µW SID402 TSTART Startup time – – 500 ms SID403 CL Crystal load capacitance 6 – 12.5 pF SID404 C0 Crystal shunt capacitance – 1.35 – pF SID405 IWCO1 Operating current (high-power mode) – – 8 µA SID406 IWCO2 Operating current (low-power mode) – – 1 µA 85 °C – – 2.6 µA 105 °C om N ot R ec SID406A m SID398 Document Number: 001-90478 Rev. *L Page 32 of 42 PRoC BLE: CYBL10X6X Family Datasheet Ordering Information The CYBL10X6X part numbers and features are listed in the following table. Flash Size (KB) CapSense SCB TCPWM 12-Bit SAR ADC I2S PWM LCD Package CYBL10161-56LQXI 48 128 No 1 2 1 Msps No No No 56-QFN CYBL10162-56LQXI 48 128 No 2 4 1 Msps No CYBL10163-56LQXI 48 128 No 2 4 1 Msps Yes CYBL10461-56LQXI 48 128 Yes 2 4 1 Msps No CYBL10462-56LQXI 48 128 Yes 2 4 1 Msps Yes CYBL10463-56LQXI 48 128 Yes 2 4 1 Msps CYBL10561-56LQXI 48 128 Yes (Gestures) 2 4 1 Msps CYBL10562-56LQXI 48 128 Yes (Gestures) 2 4 1 Msps CYBL10563-56LQXI 48 128 Yes (Gestures) 2 4 CYBL10563-68FNXIT 48 128 Yes (Gestures) 2 CYBL10563-56LQXQ[6] 48 128 Yes (Gestures) 2 CYBL10563-68FLXIT[7] 48 128 56-QFN No 56-QFN No No 56-QFN No D No 56-QFN No No Yes 56-QFN No No No 56-QFN Yes 1 No 56-QFN 1 Msps Yes 1 Yes 56-QFN 4 1 Msps Yes 1 Yes 68-WLCSP 4 1 Msps Yes 1 Yes 56-QFN 4 1 Msps Yes 1 Yes 68-Thin WLCSP N fo r en de d 2 es ig No ew 4 No Contact Sales N ot R ec om m CYBL10999-56LQXI Yes (Gestures) ns CPU Speed (MHz) Part Number Note 6. This part is available as Engineering Sample. 7. This part is available as Engineering Sample (CYBL10563-68FLXIEST). Document Number: 001-90478 Rev. *L Page 33 of 42 PRoC BLE: CYBL10X6X Family Datasheet Part Numbering Conventions The part numbers are of the form CYBL10ABC-DEFGHIT where the fields are defined as follows. CY BL 10 A B C - DE FG H I T CYBL: PRoC- Smart Family ns Example 10 : CYBL10 XXX es ig Cypress Prefix Sub - family 1: Embedded only 4: CapSense 5: Touch D Product Type Flash Capacity 6: 128 KB 3: Part Identifier LQ: QFN FN : WLCSP FL : Thin WLCSP Package Code Pb X : Pb - free I: Industrial Q: Extended Industrial Temperature Range N Package Pins fo r 56/ 70: Number of Pins ew Feature Set Tape and Reel en de d T: Tape and Reel Blank : Tray / Tube Description Values Cypress PRoC BLE Family CYBL 10 Subfamily 10 CYBL10X6X 1 Embedded Only A Product Type 4 CapSense om Field CYBL m The Field Values are listed in the following table: B Flash Capacity Package Pins FG Package code ot DE N H I 5 Touch 6 128 KB Feature set R ec C Meaning Pb Temperature Range Document Number: 001-90478 Rev. *L 56 68 LQ QFN FN WLCSP FL Thin WLCSP X Pb-free C Commercial 0 °C to 70 °C X Absent (with Pb) I Industrial –40 °C to 85 °C Q Extended Industrial –40 °C to 105 °C Page 34 of 42 PRoC BLE: CYBL10X6X Family Datasheet Packaging Table 52. Package Characteristics Conditions Operating ambient temperature TJ Operating junction temperature TJA Package JA (56-pin QFN) Min Typ Industrial –40 25 Extended industrial –40 25 Industrial –40 – Extended industrial –40 – TJC Package JC (56-pin QFN) – TJA Package JA (68-ball WLCSP) – TJC Package JC (68-ball WLCSP) TJA Package JA (68-ball Thin WLCSP) TJC Package JC (68-ball Thin WLCSP) 56-pin QFN 260 °C 260 °C 260 °C °C 100 °C – 125 °C 16.9 – °C/watt – °C/watt – °C/watt – 0.19 – °C/watt – 16.6 – °C/watt 0.19 – °C/watt ew D 9.7 Maximum Time at Peak Temperature 30 seconds 30 seconds 30 seconds en de d 68-ball WLCSP 68-ball Thin WLCSP 105 N Maximum Peak Temperature °C fo r Package Units 85 16.6 – Table 53. Solder Reflow Peak Temperature Max ns TA Description es ig Parameter Table 54. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package MSL 56-pin QFN MSL 3 68-ball WLCSP MSL 1 MSL 1 m 68-ball Thin WLCSP Spec ID om Table 55. Package Details 001-58740 Rev. *C Description 7 mm × 7 mm × 0.6 mm 68-ball WLCSP 3.52 mm × 3.91 mm × 0.55 mm R ec 001-92343 Rev. *A Package 56-pin QFN 68-ball Thin WLCSP 3.52 mm X 3.91 mm X 0.4 mm N ot 001-99408 Rev ** Document Number: 001-90478 Rev. *L Page 35 of 42 PRoC BLE: CYBL10X6X Family Datasheet Figure 5. 56-Pin QFN 7 mm × 7 mm × 0.6 mm TOP VIEW SIDE VIEW NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED PAD 2. BASED ON REF JEDEC # MO-248 fo r N ew D es ig ns BOTTOM VIEW 001-58740 *C en de d 3. ALL DIMENSIONS ARE IN MILLIMETERS The center pad on the QFN package must be connected to ground (VSS) for the proper operation of the device. N ot R ec om m Figure 6. 68-Ball WLCSP Package Outline Document Number: 001-90478 Rev. *L 001-92343 *A Page 36 of 42 PRoC BLE: CYBL10X6X Family Datasheet Figure 7. 68-Ball Thin WLCSP SIDE VIEW 1 2 3 4 5 6 7 BOTTOM VIEW 8 8 7 6 5 4 3 2 ns TOP VIEW 1 A A B es ig B C C D D E E F F G G H D H J NOTES: 1. REFERENCE JEDEC PUBLICATION 95, DESIGN GUIDE 4.18 001-99408 ** N ot R ec om m en de d 2. ALL DIMENSIONS ARE IN MILLIMETERS fo r N ew J Document Number: 001-90478 Rev. *L Page 37 of 42 PRoC BLE: CYBL10X6X Family Datasheet Acronyms Description ABUS analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus Acronym Description ns Acronym Table 56. Acronyms Used in This Document (continued) ETM embedded trace macrocell FET field-effect transistor FIR finite impulse response, see also IIR FPB flash patch and breakpoint es ig Table 56. Acronyms Used in This Document FS full-speed GPIO general-purpose input/output, applies to a PSoC pin arithmetic logic unit AMUXBUS analog multiplexer bus HCI host controller interface API application programming interface HVI high-voltage interrupt, see also LVI, LVD APSR application program status register IC ARM® advanced RISC machine, a CPU architecture IDAC ATM automatic thump mode IDE ew D ALU integrated circuit current DAC, see also DAC, VDAC N BW bandwidth CAN Controller Area Network, a communications protocol integrated development environment Inter-Integrated Circuit, a communications protocol fo r I2C, or IIC I2S Inter-IC Sound IIR infinite impulse response, see also FIR ILO internal low-speed oscillator, see also IMO internal main oscillator, see also ILO common-mode rejection ratio CPU central processing unit CRC cyclic redundancy check, an error-checking protocol IMO INL integral nonlinearity, see also DNL DAC digital-to-analog converter, see also IDAC, VDAC I/O input/output, see also GPIO, DIO, SIO, USBIO DFB digital filter block IPOR initial power-on reset DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. IPSR interrupt program status register DMIPS Dhrystone million instructions per second DMA direct memory access, see also TD DNL differential nonlinearity, see also INL DNU do not use DR DWT ECC instrumentation trace macrocell LCD liquid crystal display LIN Local Interconnect Network, a communications protocol. port write data registers LR link register digital system interconnect LUT lookup table data watchpoint and trace LVD low-voltage detect, see also LVI error correcting code LVI low-voltage interrupt, see also HVI om m interrupt request ITM external crystal oscillator LVTTL low-voltage transistor-transistor logic EEPROM electrically erasable programmable read-only memory MAC multiply-accumulate EMI electromagnetic interference MCU microcontroller unit EMIF external memory interface MISO master-in slave-out EOC end of conversion NC no connect EOF end of frame NMI nonmaskable interrupt EPSR execution program status register ESD electrostatic discharge N ot ECO IRQ R ec DSI en de d CMRR Document Number: 001-90478 Rev. *L NRZ non-return-to-zero NVIC nested vectored interrupt controller Page 38 of 42 PRoC BLE: CYBL10X6X Family Datasheet Table 56. Acronyms Used in This Document (continued) Acronym Description Table 56. Acronyms Used in This Document (continued) Acronym Description nonvolatile latch, see also WOL SRAM static random access memory Opamp operational amplifier SRES software reset PAL programmable array logic, see also PLD STN super twisted nematic PC program counter SWD serial wire debug, a test protocol PCB printed circuit board SWV single-wire viewer PGA programmable gain amplifier TD transaction descriptor, see also DMA PHUB peripheral hub THD total harmonic distortion PHY physical layer TIA transimpedance amplifier PICU port interrupt control unit TN twisted nematic PLA programmable logic array TRM technical reference manual PLD programmable logic device, see also PAL TTL PLL phase-locked loop TX PMDD package material declaration data sheet UART POR power-on reset PRES precise power-on reset port read data register PSoC® Programmable System-on-Chip™ PSRR power supply rejection ratio PWM pulse-width modulator RAM random-access memory RISC reduced-instruction-set computing RMS root-mean-square real-time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register es ig D ew N VDAC voltage DAC, see also DAC, IDAC WDT watchdog timer WOL write once latch, see also NVL WRES watchdog timer reset XRES external reset I/O pin XTAL crystal om switched capacitor/continuous time SCL I2C serial clock S/H USB input/output, PSoC pins used to connect to a USB port R ec SC/CT SDA Universal Serial Bus USBIO m RTC transmit Universal Asynchronous Transmitter Receiver, a communications protocol fo r pseudo random sequence PS transistor-transistor logic USB en de d PRS ns NVL I2C serial data sample and hold signal to noise and distortion ratio SIO special input/output, GPIO with advanced features. See GPIO. N ot SINAD SOC start of conversion SOF start of frame SPI Serial Peripheral Interface, a communications protocol SR slew rate Document Number: 001-90478 Rev. *L Page 39 of 42 PRoC BLE: CYBL10X6X Family Datasheet Document Conventions Units of Measure Table 57. Units of Measure (continued) Unit of Measure Unit of Measure µH microhenry microsecond degrees Celsius dB decibel µV microvolt dBm decibel-milliwatts µW microwatt fF femtofarads mA milliampere Hz hertz ms millisecond KB 1024 bytes mV millivolt kbps kilobits per second nA nanoampere Khr kilohour ns nanosecond kHz kilohertz nV k kilo ohm  ksps kilosamples per second pF LSB least significant bit ppm ew D °C µs ns Symbol Symbol es ig Table 57. Units of Measure nanovolt N ohm picofarad picosecond s second sps samples per second en de d fo r parts per million ps megabits per second MHz megahertz M mega-ohm Msps megasamples per second sqrtHz square root of hertz µA microampere V volt µF microfarad W watt N ot R ec om m Mbps Document Number: 001-90478 Rev. *L Page 40 of 42 PRoC BLE: CYBL10X6X Family Datasheet Revision History es ig ns Description Title: CYBL10X6X Family Datasheet Programmable Radio-on-Chip With Bluetooth Low Energy (PRoC BLE) Document Number: 001-90478 Orig. of Submission Revision ECN Description of Change Change Date *F 4567076 CSAI 11/11/2014 Initial release *G 4600081 SKAR 12/19/2014 Revision to 16-bit Timer Counter PWM, block current consumption at 3, 12, and 48 MHz to align with CHAR data Revision of I2C/ UART block current consumption to align with CHAR data D Revision of LCD Direct Drive - operating current in low-power mode to align with CHAR data ew Revision of BLE RF Average Current Spec for 4-sec BLE connection interval to 6.25 µA to align with CHAR data N Revision of RXS with idle transmitter, with balun loss and in high-gain mode to align with CHAR data fo r Clarified the IECO operating current to reflect crystal current - LDO and Bandgap current as well Corrected Typo for SID#245 (CPU -> SCB) Corrected Typo for SID#275 4651104 CSAI Removed errata 02/11/2015 Updated Figure 5 en de d *H Updated CapSense column for CYBL10563-56LQXI and CYBL10563-68FNXIT parts to "Yes (Gestures)" in Ordering Information table and updated part number 4779453 HXR *J 4810822 GCG *K 4865942 om ot R ec SASD/ SDUR/ UTSV N *L Updated Part Numbering Conventions 05/28/2015 Removed min and max values for SID359 and SID360. Removed max value and added typ value for SID357. 06/29/2015 Updated Figure 1 for clarity Updated Figure 2 and Figure 3 for uniformity Updated Figure 4 with a higher resolution image Removed EZSPI reference. Updated 56-pin QFN package diagram to correct the orientation of text. 08/19/2015 Changed temperature range from –40 °C to 85 °C to –40 °C to 105 °C. Added ‘overvoltage-tolerant’ description to pins P5.0 and P5.1 in CYBL10X6X Pin List (WLCSP Package). Added clarifying note on overvoltage-tolerant pins for SID76. Updated max values in Timer, Counter, and PWM DC specifications for 105 °C. Added SID257A in Flash AC Specifications. Added Guaranteed by Design note to SID 298. Added SID406A for 105 °C. Added extended industrial temperature range in the Field Values table. Added TA and TJ for extended industrial in Package Characteristics. Added extended industrial temperature parts in Ordering Information. Added thin WLCSP (CYBL10563-68FLXIT) details in Ordering Information and Packaging sections. 03/23/2017 Updated the template. Added NRND watermark. m *I 5669710 DEJO Document Number: 001-90478 Rev. *L Page 41 of 42 PRoC BLE: CYBL10X6X Family Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support PSoC® Solutions cypress.com/arm cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Internet of Things cypress.com/iot Memory cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic cypress.com/touch USB Controllers N Touch Sensing cypress.com/usb cypress.com/wireless om m en de d fo r Wireless Connectivity es ig Automotive D ARM® Cortex® Microcontrollers ew Products ns Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. R ec © Cypress Semiconductor Corporation, 2013-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. N ot TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-90478 Rev. *L Revised March 23, 2017 Page 42 of 42
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