CYBLE-416045-02

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CYBLE-416045-02 EZ-BLE™ Creator Module Low-Power 1.71 V to 3.6 V Operation EZ-BLE™ Creator™ Module General Description The Cypress CYBLE-416045-02 is a fully certified and qualified module supporting Bluetooth Low Energy (BLE) wireless communication. The CYBLE-416045-02 is a turnkey solution and includes onboard crystal oscillators, trace antenna, passive components, and the Cypress PSoC® 63 BLE silicon device. Refer to the PSoC 63 BLE datasheet for additional details on the capabilities of the PSoC 63 BLE device used on this module. The EZ-BLE™ Creator module is a scalable and reconfigurable platform architecture. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The CYBLE-416045-02 also includes digital programmable logic, high-performance analog-to-digital conversion (ADC), low-power comparators, and standard communication and timing peripherals. The CYBLE-416045-02 includes a royalty-free BLE stack compatible with Bluetooth 5.0 and provides up to 36 GPIOs in a 14 × 18.5 × 2.00 mm package. The CYBLE-416045-02 is a complete solution and an ideal fit for applications seeking a high-performance BLE wireless solution. Module Description ■ Active, Low-power Active, Sleep, Low-power Sleep, Deep Sleep, and Hibernate modes for fine-grained power management ■ Deep Sleep mode current with 64K SRAM retention is 7 µA with 3.3-V external supply and internal buck ■ On-chip Single-In Multiple Out (SIMO) DC-DC Buck converter, less than 1 µA quiescent current ■ Backup domain with 64 bytes of memory and Real-Time-Clock (RTC) programmable analog Serial Communication ■ Five independent runtime reconfigurable serial communication blocks (SCBs), each is software configurable as I2C, SPI, or UART Timing and Pulse-Width Modulation (TCPWM) ■ Thirty-two TCPWM blocks ■ Center-aligned, Edge, and Pseudo-random modes ■ Comparator-based triggering of Kill signals ■ Module size: 14.0 mm × 18.5 mm × 2.00 mm (with shield) Up to 36 Programmable GPIOs ■ 1 MB Application Flash with 32-KB EEPROM area and 32-KB Secure Flash ■ ■ 288-KB SRAM with Selectable Retention Granularity ■ Up to 36 GPIOs with programmable drive modes, strengths, and slew rates ■ Bluetooth 5.0 qualified single-mode module ❐ QDID: D040144 ❐ Declaration ID:112778 Audio Subsystem ■ ■ ■ Certified to FCC, CE, MIC, and ISED regulations ■ ■ Industrial temperature range: –40 °C to +85 °C ■ Cortex®-M4F CPU with single-cycle multiply (Floating Point Unit (FPU) and Memory Protection Unit (MPU)) ■ 100-MHz Cortex-M0+ CPU with single-cycle multiply and MPU ■ OTP eFuse memory for validation and security Power Consumption ■ ■ TX output power: –20 dbm to +4 dbm ■ Received signal strength indication (RSSI) with 4-dB resolution ■ TX current consumption of 5.7 mA (radio only, 0 dbm) ■ RX current consumption of 6.7 mA (radio only) ■ ■ ■ • 12-bit 1 Msps SAR ADC with differential and single-ended modes and Sequencer with signal averaging One 12-bit voltage mode DAC with less than 5 µs settling time Two opamps with low-power operation modes Two low-power comparators that operate in Deep Sleep and Hibernate modes Built-in temperature sensor connected to ADC Programmable Digital ■ ■ Cypress Semiconductor Corporation Document Number: 002-24085 Rev. *A I2S interface; up to 192 kilosamples (ksps) word clock Two pulse-density modulation (PDM) channels for stereo digital microphones Programmable Analog ■ ® ■ 150-MHz Arm Any GPIO pin can be CapSense®, analog/digital 198 Champion Court 12 programmable logic blocks, each with eight macrocells and an 8-bit data path (called universal digital blocks or UDBs) Usable as drag-and-drop Boolean primitives (gates, registers), or as Verilog programmable blocks Cypress-provided peripheral component library using UDBs to implement functions such as communication peripherals (for example, LIN, UART, SPI, I2C, S/PDIF and other protocols), waveform generators, pseudo-random sequence (PRS) generation, and other functions. Smart I/O (Programmable I/O) blocks enable Boolean operations on signals coming from, and going to, GPIO pins • San Jose, CA 95134-1709 • 408-943-2600 Revised February 21, 2019 CYBLE-416045-02 ■ Two ports with Smart I/O block capability are provided and are available during Deep Sleep Capacitive Sensing ■ ■ ■ ■ ■ Cypress Capacitive Sigma-Delta (CSD) provides best-in-class SNR, liquid tolerance, and proximity sensing Mutual capacitance sensing (Cypress CSX) with dynamic usage of both self and mutual sensing Wake-on-Touch (WOT) with very low current Cypress-supplied software component makes capacitive sensing design fast and easy Automatic hardware tuning (SmartSense) Energy Profiler ■ ■ ■ Authentication during boot using hardware hashing ■ Step-wise authentication of execution images ■ Secure execution of code in execute only mode for protected routines ■ All debug and test ingress paths can be disabled Cryptography Accelerators ■ Hardware acceleration for Symmetric and Asymmetric Cryptographic methods (AES, 3DES, RSA, and ECC) and Hash functions (SHA-512, SHA-256) ■ True Random Number Generator (TRNG) function Block that provides history of time spent in different power modes Software energy profiling to observe and optimize energy consumption Security Built into Platform Architecture ■ Multi-faceted secure architecture based on ROM-based root of trust ■ Secure boot uninterruptible until system protection attributes are established Document Number: 002-24085 Rev. *A Page 2 of 59 CYBLE-416045-02 More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design. ■ ■ ■ ■ Overview: Module Roadmap PSoC 63 BLE Silicon Datasheet Application Notes: ❐ AN96841 - Getting Started with EZ-BLE Module ❐ AN210781 - Getting Started with PSoC 6 MCU BLE ❐ AN215656 - PSoC 6 MCU Dual-CPU System Design ❐ AN91162 - Creating a BLE Custom Profile ❐ AN217666 - PSoC 6 MCU Interrupts ❐ AN91445 - Antenna Design and RF Layout Guidelines ❐ AN213924 - PSoC 6 MCU Bootloader Guide ❐ AN219528 - PSoC 6 MCU Power Reduction Techniques Technical Reference Manual (TRM): ❐ PSoC 63 with BLE Architecture Technical Reference Manual ❐ PSoC 63 with BLE Registers Technical Reference Manual ■ Knowledge Base Articles ❐ KBA97095 - EZ-BLE™ Module Placement ❐ KBA213976 - FAQ for BLE and Regulatory Certifications with EZ-BLE modules ❐ KBA210802 - Queries on BLE Qualification and Declaration Processes ■ Development Kits: ❐ CYBLE-416045-EVAL, CYBLE-416045-02 Evaluation Board ❐ CY8CKIT-062-BLE, PSoC 63 BLE Pioneer Kit ■ Test and Debug Tools: ❐ CYSmart, Bluetooth LE Test and Debug Tool (Windows) ❐ CYSmart Mobile, Bluetooth LE Test and Debug Tool (Android/iOS Mobile App) PSoC Creator™ Integrated Design Environment (IDE) PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables you to design hardware and firmware systems concurrently, based on PSoC 6 MCU. As shown below, with PSoC Creator, you can: 1. Explore the library of 200+ Components in PSoC Creator 4. Co-design your application firmware and hardware in the PSoC Creator IDE or build project for 3rd party IDE 2. Drag and drop Component icons to complete your hardware system design in the main design workspace 5. Prototype your solution with the CYBLE-416045-02 Evaluation Kit. If a design change is needed, PSoC Creator and 3. Configure Components using the Component Configuration Components enable you to make changes on the fly without Tools and the Component Datasheets the need for hardware revisions Figure 1. PSoC Creator Schematic Entry and Components Document Number: 002-24085 Rev. *A Page 3 of 59 CYBLE-416045-02 Contents Functional Definition ........................................................ 5 CPU and Memory Subsystem ..................................... 5 System Resources ...................................................... 5 BLE Radio and Subsystem ......................................... 6 Analog Blocks .............................................................. 6 Programmable Digital .................................................. 7 Fixed-Function Digital .................................................. 7 GPIO ........................................................................... 8 Special-Function Peripherals ...................................... 8 Module Overview .............................................................. 9 Module Description ...................................................... 9 Pad Connection Interface .............................................. 11 Recommended Host PCB Layout ................................. 12 Digital and Analog Capabilities and Connections ....... 14 Power ............................................................................... 18 32-kHz Crystal Oscillator ........................................... 19 Critical Components List ........................................... 21 Antenna Design ......................................................... 21 Electrical Specification .................................................. 22 Device-Level Specifications ...................................... 22 Analog Peripherals .................................................... 28 Digital Peripherals ..................................................... 37 Memory ..................................................................... 39 System Resources .................................................... 40 Document Number: 002-24085 Rev. *A Environmental Specifications ....................................... 48 Environmental Compliance ....................................... 48 RF Certification .......................................................... 48 Environmental Conditions ......................................... 48 ESD and EMI Protection ........................................... 48 Regulatory Information .................................................. 49 FCC ........................................................................... 49 ISED .......................................................................... 50 European Declaration of Conformity ......................... 51 MIC Japan ................................................................. 51 Packaging ........................................................................ 52 Ordering Information ...................................................... 54 Part Numbering Convention ...................................... 54 Acronyms ........................................................................ 55 Document Conventions ................................................. 57 Unit of Measure ......................................................... 57 Document History Page ................................................. 58 Sales, Solutions, and Legal Information ...................... 59 Worldwide Sales and Design Support ....................... 59 Products .................................................................... 59 PSoC® Solutions ...................................................... 59 Cypress Developer Community ................................. 59 Technical Support ..................................................... 59 Page 4 of 59 CYBLE-416045-02 Functional Definition System Resources CPU and Memory Subsystem Power System CPU The power system provides assurance that voltage levels are as required for each respective mode and will either delay mode entry (for example, on power-on reset (POR)) until voltage levels are as required for proper function or generate resets (brownout detect (BOD)) when the power supply drops below specified levels. The design will guarantee safe chip operation between power supply voltage dropping below specified levels (for example, below 1.71 V) and the reset occurring. There are no voltage sequencing requirements. The VDD core logic supply (1.71 to 3.6 V) will feed an on-chip buck, which will produce the core logic supply of either 1.1 V or 0.9 V selectable. Depending on the frequency of operation, the buck converter will have a quiescent current of