CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
FLEx36™ 3.3V 32K/64K/128K/256K/512 x 36
Synchronous Dual-Port RAM
Features
Functional Description
■
True dual-ported memory cells that enable simultaneous
access of the same memory location
■
Synchronous pipelined operation
■
Family of 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit and 18-Mbit devices
■
Pipelined output mode allows fast operation
■
0.18 micron CMOS for optimum speed and power
■
High speed clock to data access
■
3.3V low power
❐ Active as low as 225 mA (typ.)
❐ Standby as low as 55 mA (typ.)
■
Mailbox function for message passing
■
Global master reset
■
Separate byte enables on both ports
■
Commercial and industrial temperature ranges
■
IEEE 1149.1-compatible JTAG boundary scan
■
256 Ball FBGA (1-mm pitch)
■
Counter wrap around control
❐ Internal mask register controls counter wrap-around
❐ Counter-interrupt flags to indicate wrap-around
❐ Memory block retransmit operation
■
Counter readback on address lines
■
Mask register readback on address lines
■
Dual Chip Enables on both ports for easy depth expansion
■
Seamless migration to next-generation dual-port family
The FLEx36™ family includes 1-Mbit, 2-Mbit, 4-Mbit, 9-Mbit, and
18-Mbit pipelined, synchronous, true dual-port static RAMs that
are high speed, low power 3.3V CMOS. Two ports are provided,
permitting independent, simultaneous access to any location in
memory. A particular port can write to a certain location while
another port is reading that location. The result of writing to the
same location by more than one port at the same time is
undefined. Registers on control, address, and data lines allow for
minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CYD18S36V devices in this family has limited features.
Please see Address Counter and Mask Register Operations[19]
on page 5 for details.
Seamless Migration to Next-Generation Dual-Port
Family
Cypress offers a migration path for all devices in this family to the
next-generation devices in the Dual-Port family with a compatible
footprint. Please contact Cypress Sales for more details.
Table 1. Product Selection Guide
1 Mbit
(32K x 36)
2 Mbit
(64K x 36)
4 Mbit
(128K x 36)
9 Mbit
(256K x 36)
18 Mbit
(512K x 36)
CYD01S36V
CYD02S36V/36VA
CYD04S36V
CYD09S36V
CYD18S36V
Max. Speed (MHz)
167
167
167
167
133
Max. Access Time – Clock to Data
(ns)
4.0
4.4
4.0
4.0
5.0
Typical Operating Current (mA)
225
225
225
270
315
Density
Part Number
Package
256 FBGA
256 FBGA
256 FBGA
256 FBGA
256 FBGA
(17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (23 mm x 23 mm)
Cypress Semiconductor Corporation
Document Number: 38-06076 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised Decenber 09, 2008
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CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Logic Block Diagram[1]
FTSELL
FTSELR
CONFIG Block
CONFIG Block
PORTSTD[1:0]R
PORTSTD[1:0]L
DQ [35:0]L
BE [3:0]L
CE0L
CE1L
OEL
IO
Control
IO
Control
DQ [35:0]R
BE [3:0]R
CE0R
CE1R
OER
R/WR
R/WL
Dual Ported Array
BUSYL
A [18:0]L
CNT/MSKL
ADSL
CNTENL
CNTRSTL
RETL
CNTINTL
CL
Arbitration Logic
Address &
Counter Logic
BUSYR
Address &
Counter Logic
WRPL
A [18:0]R
CNT/MSKR
ADSR
CNTENR
CNTRSTR
RETR
CNTINTR
CR
WRPR
JTAG
TRST
TMS
TDI
TDO
TCK
RESET
LOGIC
MRST
READYR
LowSPDR
Mailboxes
INTL
INTR
READYL
LowSPDL
Note
1. 18-Mbit device has 19 address bits, 9-Mbit device has 18 address bits, 4-Mbit device has 17 address bits, 2-Mbit device has 16 address bits, and 1-Mbit device has
15 address bits.
Document Number: 38-06076 Rev. *G
Page 2 of 28
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CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Pin Configurations
Figure 1. Pin Diagram - 256-Ball FBGA (Top View)
CYD01S36V/CYD02S36V/36VA/CYD04S36V/CYD09S36V/CYD18S36V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
DQ32L
DQ30L
DQ28L
DQ26L
DQ24L
DQ22L
DQ20L
DQ18L
DQ18R
DQ20R
DQ22R
DQ24R
DQ26R
DQ28R
DQ30R
DQ32R
B
DQ33L
DQ31L
DQ29L
DQ27L
DQ25L
DQ23L
DQ21L
DQ19L
DQ19R
DQ21R
DQ23R
DQ25R
DQ27R
DQ29R
DQ31R
DQ33R
C
DQ34L
DQ35L
RETL
[2,3]
INTL
NC
[2,5]
NC
[2,5]
REVL
[2,4]
TRST
[2,5]
MRST
NC
[2,5]
NC
[2,5]
NC
[2,5]
INTR
RETR
[2,3]
DQ35R
DQ34R
D
A0L
A1L
WRPL
[2,3]
VSS
VTTL
VTTL
VSS
LOWSP FTSEL VREFL
[2,4]
DR [2,4] R [2,3]
WRPR
[2,3]
A1R
A0R
E
A2L
A3L
CE0L
[11]
CE1L
[10]
VDDIOL VDDIOL VDDIOL VCORE VCORE
VDDIO
R
VDDIO
R
VDDIO
R
CE1R
[10]
CE0R
[11]
A3R
A2R
F
A4L
A5L
CNTINT
L [12]
BE3L
VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
R
BE3R
CNTINT
R [12]
A5R
A4R
G
A6L
A7L
BUSYL
[2,5]
BE2L
REVL
[2,3]
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
R
BE2R
BUSYR
[2,5]
A7R
A6R
H
A8L
A9L
CL
VTTL
VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VCORE
VTTL
CR
A9R
A8R
J
A10L
A11L
VSS
PORTS
TD1L[2, VCORE
4]
VSS
VSS
VSS
VSS
VSS
VSS
PORTS
VCORE TD1R[2,
4]
VSS
A11R
A10R
K
A12L
A13L
OEL
BE1L
VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
R
BE1R
OER
A13R
A12R
L
A14L
A15L
[6]
ADSL
[11]
BE0L
VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
R
BE0R
ADSR
[11]
A15R
[6]
A14R
M
A16L
[7]
A17L
[8]
R/WL
REVL
[2,4]
VDDIOL VDDIOL VDDIOL VCORE VCORE
VDDIO
R
VDDIO
R
VDDIO
R
REVR
[2,4]
R/WR
A17R
[8]
A16R
[7]
N
A18L
[9]
A19L
[2,5]
CNT/M VREFL
[2,4]
SKL [10]
PortST
D0L
[2,4]
READY
L [2,5]
REVL
[2,3]
VTTL
VTTL
REVR
[2,3]
READY
R [2,5]
PortST
D0R
[2,4]
VREFR
[2,4]
CNT/M
SKR
[10]
A19R
[2,5]
A18R
[9]
P
DQ16L
DQ17L
CNTEN CNTRS
L [11]
TL [10]
NC
[2,5]
NC
[2,5]
TCK
TMS
TDO
TDI
NC
[2,5]
NC
[2,5]
R
DQ15L
DQ13L
DQ11L
DQ9L
DQ7L
DQ5L
DQ3L
DQ1L
DQ1R
DQ3R
DQ5R
DQ7R
DQ9R
DQ11R
DQ13R
DQ15R
T
DQ14L
DQ12L
DQ10L
DQ8L
DQ6L
DQ4L
DQ2L
DQ0L
DQ0R
DQ2R
DQ4R
DQ6R
DQ8R
DQ10R
DQ12R
DQ14R
VREFL FTSELL LOWSP
[2,4]
[2,3]
DL [2,4]
CNTRS CNTEN
DQ17R
TR [10] R [11]
DQ16R
Notes
2. This ball represents a next generation Dual-Port feature. For more information about this feature, contact Cypress Sales.
3. Connect this ball to VDDIO. For more information about this next generation Dual-Port feature contact Cypress Sales.
4. Connect this ball to VSS. For more information about this next generation Dual-Port feature, contact Cypress Sales.
5. Leave this ball unconnected. For more information about this feature, contact Cypress Sales.
6. Leave this ball unconnected for 32K x 36configuration.
7. Leave this ball unconnected for a 64K x 36, 32K x 36 configurations.
8. Leave this ball unconnected for a 128K x 36, 64K x 36 and 32K x 36 configurations.
9. Leave this ball unconnected for a 256K x 36, 128K x 36, 64K x 36, and 32K x 36 configurations.
10. These balls are not applicable for CYD18S36V device. They need to be tied to VDDIO.
11. These balls are not applicable for CYD18S36V device. They need to be tied to VSS.
12. These balls are not applicable for CYD18S36V device. They need to be no connected.
Document Number: 38-06076 Rev. *G
Page 3 of 28
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CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Pin Definitions
Left Port
Right Port
A0L–A18L
A0R–A18R
BE0L–BE3L
BE0R–BE3R
Byte Enable Inputs. Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
BUSYL[2,5]
BUSYR[2,5]
Port Busy Output. When the collision is detected, a BUSY is asserted.
CL
CR
[11]
Description
Address Inputs.
Input Clock Signal.
CE1L[10]
CE0R[11]
CE1R[10]
DQ0L–DQ35L
DQ0R–DQ35R
OEL
OER
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ
data pins during Read operations.
INTL
INTR
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INTL is asserted LOW
when the right port writes to the mailbox location of the left port, and vice versa. An interrupt
to a port is deasserted HIGH when it reads the contents of its mailbox.
LowSPDL[2,4]
LowSPDR[2,4]
CE0L
PORTSTD[1:0]L
[2,4]
PORTSTD[1:0]R
R/WL
R/WR
READYL[2,5]
READYR[2,5]
Active High Chip Enable Input.
[2,4]
Data Bus Input/Output.
Port Low Speed Select Input.
Port Address/Control/Data IO Standard Select Inputs.
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual
port memory array.
Port Ready Output. This signal is asserted when a port is ready for normal operation.
CNTENL[11]
CNTRSTL[10]
CNTINTL[12]
CNT/MSKR[10]
ADSR[11]
CNTENR[11]
CNTRSTR[10]
CNTINTR[12]
WRPL[2,3]
WRPR[2,3]
Port Counter Wrap Input. The burst counter wrap control input.
[2,3]
RETR[2,3]
Port Counter Retransmit Input. Counter control input.
CNT/MSKL
[10]
Active Low Chip Enable Input.
ADSL[11]
RETL
FTSELL[2,3]
FTSELR
VREFL[2,4]
VREFR[2,4]
VDDIOL
VDDIOR
REVL
[2,3]
REVR[2, 3, 4]
[2, 3, 4]
MRST
TRST[2,5]
Port Counter/Mask Select Input. Counter control input.
Port Counter Address Load Strobe Input. Counter control input.
Port Counter Enable Input. Counter control input.
Port Counter Reset Input. Counter control input.
Port Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of
the counter is incremented to all “1s”.
Flow-Through Select. Use this pin to select Flow-Through mode. When is de-asserted,
the device is in pipelined mode.
Port External High-Speed IO Reference Input.
Port IO Power Supply.
Reserved pins for future features.
Master Reset Input. MRST is an asynchronous input signal and affects both ports. A
maser reset operation is required at power up.
JTAG Reset Input.
TMS
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
TDI
JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers.
TCK
JTAG Test Clock Input.
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is
normally three-stated except when captured data is shifted out of the JTAG TAP.
VSS
Ground Inputs.
VCORE[13]
VTTL
Document Number: 38-06076 Rev. *G
Core Power Supply.
LVTTL Power Supply for JTAG IOs
Page 4 of 28
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CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Master Reset
The FLEx36 family devices undergo a complete reset by taking
its MRST input LOW. The MRST input can switch asynchronously to the clocks. An MRST initializes the internal burst
counters to zero, and the counter mask registers to all ones
(completely unmasked). MRST also forces the Mailbox Interrupt
(INT) flags and the Counter Interrupt (CNTINT) flags HIGH.
MRST must be performed on the FLEx36 family devices after
power up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports of CYD18S36V. The
highest memory location, 7FFFF is the mailbox for the right port
and 7FFFE is the mailbox for the left port. Table 2 shows that to
set the INTR flag, a Write operation by the left port to address
7FFFF asserts INTR LOW. At least one byte must be active for a
Write to generate an interrupt. A valid Read of the 7FFFF
location by the right port resets INTR HIGH. At least one byte
must be active in order for a Read to reset the interrupt. When
one port Writes to the other port’s mailbox, the INT of the port
that the mailbox belongs to is asserted LOW. The INT is reset
when the owner (port) of the mailbox Reads the contents of the
mailbox. The interrupt flag is set in a flow-thru mode (i.e., it
follows the clock edge of the writing port). Also, the flag is reset
in a flow-thru mode (i.e., it follows the clock edge of the reading
port).
Each port can read the other port’s mailbox without resetting the
interrupt. And each port can write to its own mailbox without
setting the interrupt. If an application does not require message
passing, INT pins must be left open.
Address Counter and Mask Register
Operations[19]
This section describes the features only apply to 1Mbit, 2 Mbit,
4 Mbit and 9 Mbit devices. It does not apply to 18Mbit device.
Each port of these devices has a programmable burst address
counter. The burst counter contains three registers: a counter
register, a mask register, and a mirror register.
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only by
the Mask Load and Mask Reset operations, and by the MRST.
The mask register defines the counting range of the counter
register. It divides the counter register into two regions: zero or
more “0s” in the most significant bits define the masked region,
one or more “1s” in the least significant bits define the unmasked
region. Bit 0 may also be “0,” masking the least significant
counter bit and causing the counter to increment by two instead
of one.l
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and Counter Reset operations, and by the MRST.
Table 3 on page 6 summarizes the operation of these registers
and the required input control signals. The MRST control signal
is asynchronous. All the other control signals in Table 3 on page
6 (CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1).
Table 2. Interrupt Operation Example [1, 14, 15, 16, 17, 18]
Function
Left Port
Right Port
R/WL
CEL
A0L–18L
INTL
R/WR
CER
A0R–18R
INTR
Set Right INTR Flag
L
L
7FFFF
X
X
X
X
L
Reset Right INTR Flag
X
X
X
X
H
L
7FFFF
H
Set Left INTL Flag
X
X
X
L
L
L
7FFFE
X
Reset Left INTL Flag
H
L
7FFFE
H
X
X
X
X
Notes
13. This family of Dual-Ports does not use VCORE, and these pins are internally NC. The next generation Dual-Port family, the FLEx36-E™, uses VCORE of 1.5V or 1.8V.
Please contact local Cypress FAE for more information.
14. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge.
15. OE is “Don’t Care” for mailbox operation.
16. At least one of BE0, BE1, BE2, or BE3 must be LOW.
17. A17x is a NC for CYD04S36V, therefore the Interrupt Addresses are 1FFFF and 1FFFE. A17x and A16x are NC for CYD02S36V/36VA, therefore the Interrupt Addresses
are FFFF and FFFE; A17x, A16x and A15x are NC for CYD01S36V, therefore the Interrupt Addresses are 7FFF and 7FFE.
18. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
19. This section describes the CYD09S36V, CYD04S36V, CYD02S36V/36VA, and CYD01S36V which have 18, 17, 16 and 15 address bits.
Document Number: 38-06076 Rev. *G
Page 5 of 28
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CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Counter Reset Operation
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and use the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This Read’s or Write’s one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array, and loops
back to the start. Counter reset (CNTRST) is used to reset the
unmasked portion of the burst counter to 0s. A counter-mask
register is used to control the counter wrap.
All unmasked bits of the counter and mirror registers are reset to
“0.” All masked bits remain unchanged. A Mask Reset followed
by a Counter Reset resets the counter and mirror registers to
00000, as does master reset (MRST).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port) [18, 20]
CLK
MRST
CNT/MSK
CNTRST
ADS
CNTEN
X
L
X
X
X
X
Master Reset
Operation
Reset address counter to all 0s and mask
register to all 1s.
Description
H
H
L
X
X
Counter Reset
Reset counter unmasked portion to all 0s.
H
H
H
L
L
Counter Load
Load counter with external address value
presented on address lines.
H
H
H
L
H
Counter Readback
Read out counter internal value on address
lines.
H
H
H
H
L
Counter Increment
Internally increment address counter value.
H
H
H
H
H
Counter Hold
Constantly hold the address value for multiple
clock cycles.
H
L
L
X
X
Mask Reset
Reset mask register to all 1s.
H
L
H
L
L
Mask Load
Load mask register with value presented on
the address lines.
H
L
H
L
H
Mask Readback
Read out mask register value on address
lines.
H
L
H
H
X
Reserved
Operation undefined
Note
20. Counter operation and mask register operation is independent of chip enables.
Document Number: 38-06076 Rev. *G
Page 6 of 28
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CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Counter Increment Operation
Once the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incremented.
The corresponding bit in the mask register must be a “1” for a
counter bit to change. The counter register is incremented by 1
if the least significant bit is unmasked, and by 2 if it is masked. If
all unmasked bits are “1,” the next increment wraps the counter
back to the initially loaded value. If an Increment results in all the
unmasked bits of the counter being “1s,” a counter interrupt flag
(CNTINT) is asserted. The next Increment returns the counter
register to its initial value, which was stored in the mirror register.
The counter address can instead be forced to loop to 00000 by
externally connecting CNTINT to CNTRST.[21] An increment that
results in one or more of the unmasked bits of the counter being
“0” de-asserts the counter interrupt flag. The example in Figure
3 on page 9 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit “0” as the LSB
and bit “16” as the MSB. The maximum value the mask register
can be loaded with is 3FFFFh. Setting the mask register to this
value allows the counter to access the entire memory space. The
address counter is then loaded with an initial value of 8h. The
base address bits (in this case, the 6th address through the 16th
address) are loaded with an address value but do not increment
once the counter is configured for increment operation. The
counter address starts at address 8h. The counter increments its
internal address value till it reaches the mask register value of
3Fh. The counter wraps around the memory block to location 8h
at the next count. CNTINT is issued when the counter reaches
its maximum value.
Counter Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are needed,
or when address is available a few cycles ahead of data in a
shared bus interface.
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset and
Mask Load operations, and by MRST.
Counter Readback Operation
The internal value of the counter register can be read out on the
address lines. Readback is pipelined; the address is valid tCA2
after the next rising edge of the port’s clock. If address readback
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the
data lines (DQs) are three-stated. Figure 2 on page 8 shows a
block diagram of the operation.
Retransmit
Retransmit is a feature that allows the Read of a block of memory
more than once without the need to reload the initial address.
This eliminates the need for external logic to store and route
data. It also reduces the complexity of the system design and
saves board space. An internal “mirror register” is used to store
the initially loaded address counter value. When the counter
unmasked portion reaches its maximum value set by the mask
register, it wraps back to the initial value stored in this “mirror
register.” If the counter is continuously configured in increment
mode, it increments again to its maximum value and wraps back
to the value initially stored into the “mirror register.” Thus, the
repeated access of the same data is allowed without the need
for any external logic.
Mask Reset Operation
The mask register is reset to all “1s,” which unmasks every bit of
the counter. Master reset (MRST) also resets the mask register
to all “1s.”
Mask Load Operation
The mask register is loaded with the address value presented at
the address lines. Not all values permit correct increment operations. Permitted values are of the form 2n – 1 or 2n – 2. From the
most significant bit to the least significant bit, permitted values
have zero or more “0s,” one or more “1s,” or one “0.” Thus
7FFFF, 003FE, and 00001 are permitted values, but 7F0FF,
003FC, and 00000 are not.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address is valid tCM2
after the next rising edge of the port’s clock. If mask readback
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the
data lines (DQs) are three-stated. Figure 2 on page 8 shows a
block diagram of the operation.
Counting by Two
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the x36
devices as a 72-bit single port SRAM in which the counter of one
port counts even addresses and the counter of the other port
counts odd addresses. This even-odd address scheme stores
one half of the 72-bit data in even memory locations, and the
other half in odd memory locations.
Note
21. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
Document Number: 38-06076 Rev. *G
Page 7 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Figure 2. Counter, Mask, and Mirror Logic Block Diagram[1]
CNT/MSK
CNTEN
Decode
Logic
ADS
CNTRST
MRST
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
Address
RAM
Decode
Array
CLK
From
Address
Lines
Load/Increment
17
Mirror
1
From
Mask
Register
From
Mask
From
Counter
Increment
Logic
Wrap
17
17
17
17
Bit 0
+1
Wrap
Detect
1
+2
Wrap
0
1
0
Document Number: 38-06076 Rev. *G
To Readback
and Address
Decode
0
0
17
Counter
1
17
To
Counter
Page 8 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Figure 3. Programmable Counter-Mask Register Operation[1, 22]
Example:
Load
Counter-Mask
Register = 3F
CNTINT
H
0
0
0s
216 215
H
X X
Xs
216 215
Max
Address
Register
L
X X
H
X X
216 215
IEEE 1149.1 Serial Boundary Scan (JTAG)[23]
The FLEx36 family devices incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1-compliant TAPs. The TAP operates
using JEDEC-standard 3.3V IO logic levels. It is composed of
three input connections and one output connection required by
the test logic defined by the standard.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the device is operating. An
MRST must be performed on the devices after power up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan
chain outputs the next bit in the chain twice. For example, if the
value expected from the chain is 1010101, the device outputs a
11010101. This extra bit causes some testers to report an
erroneous failure for the devices in a scan test. Therefore the
tester must be configured to never enter the PAUSE-DR state.
1
1 1
1
Unmasked Address
X 0
0
1
0 0
Xs
X 1 1
1
1
Mask
Register
bit-0
0
26 25 24 23 22 21 20
216 215
Max + 1
Address
Register
1
26 25 24 23 22 21 20
Masked Address
Load
Address
Counter = 8
0 1
1
1
Address
Counter
bit-0
26 25 24 23 22 21 20
Xs
X 0 0
1
0 0
0
26 25 24 23 22 21 20
Boundary Scan Hierarchy for 9-Mbit and 18-Mbit
Devices
Internally, the devices have multiple DIEs. Each DIE contains all
the circuitry required to support boundary scan testing. The
circuitry includes the TAP, TAP controller, instruction register,
and data registers. The circuity and operation of the DIE
boundary scan are described in detail below.
The scan chain for 9-Mbit and 18-Mbit devices uses a hierarchical approach as shown in Figure 4 on page 10 and Figure 5
on page 10. TMS and TCK are connected in parallel to each DIE
to drive all 2- or 4-TAP controllers in unison. In many cases, each
DIE is supplied with the same instruction. In other cases, it might
be useful to supply different instructions to each DIE. One
example would be testing the device ID of one DIE while
bypassing the rest.
Each pin of the devices is typically connected to multiple DIEs.
For connectivity testing with the EXTEST instruction, it is
desirable to check the internal connections between DIEs and
the external connections to the package. This can be accomplished by merging the netlist of the devices with the netlist of the
user’s circuit board. To facilitate boundary scan testing of the
devices, Cypress provides the BSDL file for each DIE, the
internal netlist of the device, and a description of the device scan
chain. The user can use these materials to easily integrate the
devices into the board’s boundary scan environment. Further
information can be found in the Cypress application note Using
JTAG Boundary Scan For System in a Package (SIP) Dual-Port
SRAMs.
Notes
22. The “X” in this diagram represents the counter upper bits.
23. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
Document Number: 38-06076 Rev. *G
Page 9 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Figure 4. Scan Chain for 18-Mbit Device
TDO
TDO
TDO
D2
D4
TDI
TDI
TDO
TDO
D1
D3
TDI
TDI
TDI
Figure 5. Scan Chain for 9-Mbit Device
TDO
TDO
D2
TDI
TDO
D1
TDI
TDI
Table 4. Identification Register Definitions
Instruction Field
Value
Revision Number (31:28)
0h
Cypress Device ID (27:12)
Description
Reserved for version number.
C002h
Defines Cypress part number for CYD04S36V, CYD09S36V and CYD18S36V
C001h
Defines Cypress part number for CYD02S36V/36VA
C092h
Defines Cypress part number for CYD01S36V
Cypress JEDEC ID (11:1)
034h
Allows unique identification of the DP family device vendor.
ID Register Presence (0)
1
Indicates the presence of an ID register.
Table 5. Scan Register Sizes
Register Name
Bit Size
Instruction
4
Bypass
1
Identification
32
Boundary Scan
n[24]
Note
24. See details in the device BSDL files.
Document Number: 38-06076 Rev. *G
Page 10 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Table 6. Instruction Identification Codes
Instruction
Code
Description
EXTEST
0000
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
BYPASS
1111
Places the BYR between TDI and TDO.
IDCODE
1011
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
HIGHZ
0111
Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state.
CLAMP
0100
Controls boundary to 1/0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD
1000
Captures the input/output ring contents. Places BSR between TDI and TDO.
NBSRST
1100
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
RESERVED
All other codes
Other combinations are reserved. Do not use other than the above.
Document Number: 38-06076 Rev. *G
Page 11 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
Exceeding maximum ratings[25] may shorten the useful life of the
device. User guidelines are not tested.
(JEDEC JESD22-A114-2000B)
Storage Temperature .................................. –65°C to +150°C
Latch-up Current..................................................... > 200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +4.6V
DC Voltage Applied to
Outputs in High-Z State .......................... –0.5V to VDD +0.5V
Static Discharge Voltage........................................... > 2000V
Operating Range
Ambient
Temperature
Range
Commercial
0°C to +70°C
Industrial
VCORE[13]
VDDIO/VTTL
3.3V±165 mV 1.8V±100 mV
–40°C to +85°C 3.3V±165 mV 1.8V±100 mV
DC Input Voltage .............................. –0.5V to VDD + 0.5V[26]
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
IOZ
IIX1
IIX2
ICC
ISB1[27]
ISB2[27]
ISB3[27]
ISB4[27]
ISB5
ICORE[13]
Description
Output HIGH Voltage (VDD = Min, IOH= –4.0 mA)
Output LOW Voltage (VDD = Min, IOL= +4.0 mA)
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
Input Leakage Current Except TDI, TMS, MRST
Input Leakage Current TDI, TMS, MRST
Operating Current for
CYD01S36V
(VDD = Max.,IOUT = 0 mA), Outputs CYD02S36V/
Disabled
CYD02S36VA/
CYD04S36V
CYD09S36V
CYD18S36V
Standby Current (Both Ports TTL Level)
CEL and CER ≥ VIH, f = fMAX
Standby Current (One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
Standby Current (Both Ports CMOS Level)
CEL and CER ≥ VDD – 0.2V, f = 0
Standby Current (One Port CMOS Level)
CEL | CER ≥ VIH, f = fMAX
Operating Current (VDDIO = Max, CYD18S36V
Iout = 0 mA, f = 0) Outputs Disabled
Core Operating Current for (VDD = Max, IOUT = 0 mA),
Outputs Disabled
-167
-133
Min Typ. Max Min Typ. Max
2.4
2.4
0.4
0.4
2.0
2.0
0.8
0.8
–10
10 –10
10
–10
10 –10
10
–1.0
0.1 –1.0
0.1
225 300
225 300
450
600
90
-100
Unit
Typ. Max
V
0.4
V
2.0
V
0.8
V
–10
10
μA
–10
10
μA
–1.0
0.1 mA
mA
Min
2.4
mA
mA
mA
115
370
410
90
540
580
115
160
210
160
210
mA
55
75
55
75
mA
160
210
160
210
mA
315
75
0
0
0
0
0
450
75
mA
0
mA
Capacitance
Part Number
CYD01S36/
CYD02S36V/36VA/
CYD04S36V
CYD09S36V
CYD18S36V
Parameter[28]
CIN
Description
Input Capacitance
COUT
CIN
COUT
CIN
COUT
Output Capacitance
Input Capacitance
Output Capacitance
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V
Max
13
Unit
pF
10
22
10[29]
40
20
pF
pF
pF
pF
pF
Notes
25. The voltage on any input or IO pin cannot exceed the power pin during power up.
26. Pulse width < 20 ns.
27. ISB1, ISB2, ISB3 and ISB4 are not applicable for CYD18S36V because it cannot be powered down by using chip enable pins.
28. COUT also references CIO.
29. Except INT and CNTINT which are 20 pF.
Document Number: 38-06076 Rev. *G
Page 12 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Figure 6. AC Test Load and Waveforms
Z0 = 50Ω
3.3V
R = 50Ω
R1 = 590 Ω
OUTPUT
OUTPUT
C = 10 pF
C = 5 pF
VTH = 1.5V
(a) Normal Load (Load 1)
3.0V
ALL INPUT PULSES
(b) Three-state Delay (Load 2)
90%
90%
10%
10%
Vss
R2 = 435 Ω
< 2 ns
< 2 ns
Switching Characteristics Over the Operating Range
-167
Parameter
Description
-133
CYD01S36V
CYD02S36V/
CYD02S36VA
CYD04S36V
CYD09S36V
Min
Max
-100
CYD01S36V
CYD02S36V
CYD04S36V
CYD09S36V
CYD18S36V
CYD18S36V
Min
Min
Min
Max
Max
Unit
Max
fMAX2
Maximum Operating Frequency
tCYC2
Clock Cycle Time
tCH2
Clock HIGH Time
2.7
3.0
3.4
4.5
ns
tCL2
Clock LOW Time
2.7
3.0
3.4
4.5
ns
tR[30]
Clock Rise Time
2.0
2.0
2.0
3.0
ns
tF[30]
Clock Fall Time
2.0
2.0
2.0
3.0
ns
tSA
Address Setup Time
2.3
2.5
2.2
2.7
ns
tHA
Address Hold Time
0.6
0.6
1.0
1.0
ns
tSB
Byte Select Setup Time
2.3
2.5
2.2
2.7
ns
tHB
Byte Select Hold Time
0.6
0.6
1.0
1.0
ns
tSC
Chip Enable Setup Time
2.3
2.5
NA
NA
ns
tHC
Chip Enable Hold Time
0.6
0.6
NA
NA
ns
tSW
R/W Setup Time
2.3
2.5
2.2
2.7
ns
tHW
R/W Hold Time
0.6
0.6
1.0
1.0
ns
tSD
Input Data Setup Time
2.3
2.5
2.2
2.7
ns
tHD
Input Data Hold Time
0.6
0.6
1.0
1.0
ns
tSAD
ADS Setup Time
2.3
2.5
NA
NA
ns
tHAD
ADS Hold Time
0.6
0.6
NA
NA
ns
167
6.0
133
7.5
133
7.5
100
10.0
MHz
ns
tSCN
CNTEN Setup Time
2.3
2.5
NA
NA
ns
tHCN
CNTEN Hold Time
0.6
0.6
NA
NA
ns
tSRST
CNTRST Setup Time
2.3
2.5
NA
NA
ns
tHRST
CNTRST Hold Time
0.6
0.6
NA
NA
ns
tSCM
CNT/MSK Setup Time
2.3
2.5
NA
NA
ns
Note
30. Except JTAG signals (tr and tf < 10 ns [max.]).
Document Number: 38-06076 Rev. *G
Page 13 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Switching Characteristics Over the Operating Range (continued)
-167
Parameter
-133
CYD01S36V
CYD02S36V/
CYD02S36VA
CYD04S36V
CYD09S36V
Description
Min
Max
0.6
-100
CYD01S36V
CYD02S36V
CYD04S36V
CYD09S36V
CYD18S36V
CYD18S36V
Min
Min
Min
Max
0.6
Max
Max
tHCM
CNT/MSK Hold Time
tOE
Output Enable to Data Valid
tOLZ[31, 32]
OE to Low Z
0
tOHZ[31, 32]
OE to High Z
0
tCD2
Clock to Data Valid
4.4
4.4
tCA2
Clock to Counter Address Valid
4.0
4.4
tCM2
Clock to Mask Register Readback
Valid
4.0
4.4
NA
tDC
Data Output Hold After Clock HIGH
tCKHZ[31, 32]
tCKLZ[31, 32]
Clock HIGH to Output High Z
0
4.0
0
4.4
0
4.7
0
5.0
ns
Clock HIGH to Output Low Z
1.0
4.0
1.0
4.4
1.0
4.7
1.0
5.0
ns
tSINT
Clock to INT Set Time
0.5
6.7
0.5
7.5
0.5
7.5
0.5
10.0
ns
tRINT
Clock to INT Reset Time
0.5
6.7
0.5
7.5
0.5
7.5
0.5
10.0
ns
tSCINT
Clock to CNTINT Set Time
0.5
5.0
0.5
5.7
NA
NA
NA
NA
ns
tRCINT
Clock to CNTINT Reset time
0.5
5.0
0.5
5.7
NA
NA
NA
NA
ns
4.4
NA
Unit
4.4
0
4.0
1.0
0
NA
5.5
ns
5.5
ns
5.0
5.2
ns
NA
NA
ns
NA
ns
0
4.4
1.0
ns
5.5
0
0
5.5
1.0
ns
0
1.0
ns
Port to Port Delays
tCCS
Clock to Clock Skew
5.2
6.0
5.7
8.0
ns
5.0
5.0
5.0
5.0
cycles
Master Reset Timing
tRS
Master Reset Pulse Width
tRS
Master Reset Setup Time
6.0
6.0
6.0
8.5
ns
tRSR
Master Reset Recovery Time
5.0
5.0
5.0
5.0
cycles
tRSF
Master Reset to Outputs Inactive
10.0
10.0
10.0
10.0
ns
tRSINT
Master Reset to Counter and Mailbox
Interrupt Flag Reset Time
10.0
10.0
NA
NA
ns
JTAG Timing
Parameter
fJTAG
tTCYC
tTH
tTL
tTMSS
tTMSH
tTDIS
tTDIH
tTDOV
tTDOX
Description
Maximum JTAG TAP Controller Frequency
TCK Clock Cycle Time
TCK Clock HIGH Time
TCK Clock LOW Time
TMS Setup to TCK Clock Rise
TMS Hold After TCK Clock Rise
TDI Setup to TCK Clock Rise
TDI Hold After TCK Clock Rise
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
167/133/100
Min
Max
10
100
40
40
10
10
10
10
30
0
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
31. This parameter is guaranteed by design, but it is not production tested.
32. Test conditions used are Load 2.
Document Number: 38-06076 Rev. *G
Page 14 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
JTAG Switching Waveform
tTH
Test Clock
TCK
tTMSS
tTL
tTCYC
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Switching Waveforms
MRST
ALL
ADDRESS/
DATA
LINES
tRSF
tRSS
ALL
OTHER
INPUTS
TMS
Figure 7. Master Reset
tRS
tRSR
INACTIVE
ACTIVE
tRSINT
CNTINT
INT
TDO
Document Number: 38-06076 Rev. *G
Page 15 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms
(continued)
Figure 8. Read Cycle[14, 33, 34, 35, 36]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSB
tHB
tSW
tSA
tHW
tHA
tSC
tHC
BE0–BE3
R/W
ADDRESS
DATAOUT
An
An+1
1 Latency
An+2
tDC
tCD2
Qn
tCKLZ
An+3
Qn+1
tOHZ
Qn+2
tOLZ
OE
tOE
Notes
33. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
34. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
35. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock.
36. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK.
Numbers are for reference only.
Document Number: 38-06076 Rev. *G
Page 16 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms
(continued)
Figure 9. Bank Select Read[37, 38]
tCYC2
tCH2
tCL2
CLK
tHA
tSA
ADDRESS(B1)
A0
A1
A3
A2
A4
A5
tHC
tSC
CE(B1)
tCD2
tHC
tSC
tCD2
tHA
tSA
A0
ADDRESS(B2)
tDC
A1
tDC
tCKLZ
A3
A2
tCKHZ
Q3
Q1
Q0
DATAOUT(B1)
tCD2
tCKHZ
A4
A5
tHC
tSC
CE(B2)
tSC
tCD2
tHC
tCKHZ
DATAOUT(B2)
tCD2
Q4
Q2
tCKLZ
Figure 10. Read-to-Write-to-Read (OE =
tCH2
tCYC2
tCKLZ
LOW)[36, 39, 40, 41, 42]
tCL2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
tSA
An+1
An+2
An+2
An+3
tSD tHD
tHA
DATAIN
An+2
tCD2
tDC
tCKHZ
Dn+2
Qn
DATAOUT
READ
NO OPERATION
WRITE
Notes
37. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx36 device from this data sheet. ADDRESS(B1)
= ADDRESS(B2).
38. ADS = CNTEN= BE0 – BE3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
39. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
40. During “No Operation,” data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity.
41. CE0 = OE = BE0 – BE3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
42. CE0 = BE0 – BE3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed
(labelled as no operation). One clock cycle is required to three-state the IO for the Write operation on the next rising edge of CLK.
Document Number: 38-06076 Rev. *G
Page 17 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms
(continued)
Figure 11. Read-to-Write-to-Read (OE Controlled)[36, 39, 41, 42]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSW tHW
R/W
ADDRESS
tSW
tHW
An
tSA
An+1
An+2
tHA
An+3
An+4
An+5
tSD tHD
Dn+2
DATAIN
Dn+3
tCD2
DATAOUT
tCD2
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Figure 12. Read with Address Counter Advance[41]
tCH2
tCYC2
tCL2
CLK
tSA
ADDRESS
tHA
An
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DATAOUT
tHCN
Qx–1
tCD2
Qx
READ
EXTERNAL
ADDRESS
Document Number: 38-06076 Rev. *G
tDC
Qn
READ WITH COUNTER
Qn+1
COUNTER HOLD
Qn+2
Qn+3
READ WITH COUNTER
Page 18 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms
(continued)
Figure 13. Write with Address Counter Advance [42]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
tSAD
tHAD
tSCN
tHCN
An+1
An+2
An+3
An+4
ADS
CNTEN
Dn
DATAIN
tSD
tHD
WRITE EXTERNAL
ADDRESS
Document Number: 38-06076 Rev. *G
Dn+1
Dn+1
WRITE WITH
COUNTER
Dn+2
WRITE COUNTER
HOLD
Dn+3
Dn+4
WRITE WITH COUNTER
Page 19 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms
(continued)
Figure 14. Counter Reset [43, 44]
tCYC2
tCH2 tCL2
CLK
tSA
INTERNAL
ADDRESS
Ax
tSW
tHW
tSD
tHD
An
1
0
Ap
Am
An
ADDRESS
tHA
Ap
Am
R/W
ADS
CNTEN
tSRST tHRST
CNTRST
DATAIN
D0
tCD2
tCD2
[45]
DATAOUT
Q0
COUNTER
RESET
WRITE
ADDRESS 0
tCKLZ
READ
ADDRESS 0
READ
ADDRESS 1
Q1
READ
ADDRESS An
Qn
READ
ADDRESS Am
Notes
43. CE0 = BE0 – BE3 = LOW; CE1 = MRST = CNT/MSK = HIGH.
44. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
45. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value
Document Number: 38-06076 Rev. *G
Page 20 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms
(continued)
Figure 15. Readback State of Address Counter or Mask Register[46, 47, 48, 49]
tCYC2
tCH2 tCL2
CLK
tCA2 or tCM2
tSA tHA
EXTERNAL
ADDRESS
A0–A16
An*
An
INTERNAL
ADDRESS
An+1
An
An+2
An+3
An+4
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tCD2
DATAOUT
Qx-2
LOAD
EXTERNAL
ADDRESS
tCKHZ
Qx-1
Qn
READBACK
COUNTER
INTERNAL
ADDRESS
INCREMENT
tCKLZ
Qn+1
Qn+2
Qn+3
Notes
46. CE0 = OE = BE0 – BE3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
47. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle.
48. Address in input mode. Host can drive address bus after tCKHZ.
49. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Document Number: 38-06076 Rev. *G
Page 21 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms
(continued)
Figure 16. Left_Port (L_Port) Write to Right_Port (R_Port) Read[50, 51, 52]
tCH2
tCYC2
tCL2
CLKL
tHA
tSA
L_PORT
ADDRESS
An
tSW
tHW
R/WL
tCKHZ
tSD
L_PORT
tCKLZ
Dn
DATAIN
CLKR
tHD
tCYC2
tCL2
tCCS
tCH2
R_PORT
ADDRESS
tSA
tHA
An
R/WR
tCD2
R_PORT
Qn
DATAOUT
tDC
Notes
50. CE0 = OE = ADS = CNTEN = BE0 – BE3 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
51. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data is Read out.
52. If tCCS < minimum specified value, then R_Port Reads the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock. If tCCS >
minimum specified value, then R_Port Reads the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock.
Document Number: 38-06076 Rev. *G
Page 22 of 28
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CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms
(continued)
Figure 17. Counter Interrupt and Retransmit[17, 45, 53, 54, 55, 56]
tCH2
tCYC2
tCL2
CLK
tSCM
tHCM
CNT/MSK
ADS
CNTEN
COUNTER
INTERNAL
ADDRESS
3FFFC
3FFFD
3FFFE
tSCINT
3FFFF
Last_Loaded
Last_Loaded +1
tRCINT
CNTINT
Notes
53. CE0 = OE = BE0 – BE3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
54. CNTINT is always driven.
55. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
56. The mask register assumed to have the value of 3FFFFh.
Document Number: 38-06076 Rev. *G
Page 23 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Switching Waveforms
(continued)
Figure 18. MailBox Interrupt Timing[57, 58, 59, 60, 61]
tCH2
tCYC2
tCL2
CLKL
tSA
L_PORT
ADDRESS
tHA
7FFFF
An+1
An
An+2
An+3
tSINT
tRINT
INTR
tCH2
tCYC2
tCL2
CLKR
tSA
R_PORT
ADDRESS
tHA
Am+1
Am
7FFFF
Am+3
Am+4
Table 7. Read/Write and Enable Operation (Any Port)[1, 18, 62, 63, 64]
Inputs
OE
Operation
CE0
CE1
R/W
DQ0 – DQ35
X
H
X
X
High-Z
Deselected
X
X
L
X
High-Z
Deselected
X
L
H
L
DIN
Write
L
L
H
H
DOUT
Read
L
H
X
High-Z
Outputs Disabled
H
CLK
Outputs
X
Notes
57. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
58. Address “7FFFF” is the mailbox location for R_Port of the 9-Mbit device.
59. L_Port is configured for Write operation, and R_Port is configured for Read operation.
60. At least one byte enable (BE0 – BE3) is required to be active during interrupt operations.
61. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
62. OE is an asynchronous input signal.
63. When CE changes state, deselection and Read happen after one cycle of latency.
64. CE0 = OE = LOW; CE1 = R/W = HIGH.
Document Number: 38-06076 Rev. *G
Page 24 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Ordering Information
512K × 36 (18-Mbit) 3.3V Synchronous CYD18S36V Dual-Port SRAM
Speed(
MHz)
133
100
Ordering Code
CYD18S36V-133BBC
Package
Name
Package Type
Operating
Range
BB256B
256-ball Grid Array 23 mm × 23 mm with 1.0-mm pitch (BGA) Commercial
CYD18S36V-133BBI
BB256B
256-ball Grid Array 23 mm × 23 mm with 1.0-mm pitch (BGA) Industrial
CYD18S36V-100BBC
BB256B
256-ball Grid Array 23 mm × 23 mm with 1.0-mm pitch (BGA) Commercial
CYD18S36V-100BBI
BB256B
256-ball Grid Array 23 mm × 23 mm with 1.0-mm pitch (BGA) Industrial
256K × 36 (9-Mbit) 3.3V Synchronous CYD09S36V Dual-Port SRAM
Speed(
MHz)
Ordering Code
Package
Name
Package Type
Operating
Range
167
CYD09S36V-167BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Commercial
133
CYD09S36V-133BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Commercial
CYD09S36V-133BBI
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Industrial
128K × 36 (4-Mbit) 3.3V Synchronous CYD04S36V Dual-Port SRAM
Speed(
MHz)
Ordering Code
Package
Name
Package Type
Operating
Range
167
CYD04S36V-167BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Commercial
133
CYD04S36V-133BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Commercial
CYD04S36V-133BBI
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Industrial
64K × 36 (2-Mbit) 3.3V Synchronous CYD02S36V Dual-Port SRAM
Speed(
MHz)
167
133
Ordering Code
Package
Name
Package Type
Operating
Range
CYD02S36V-167BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Commercial
CYD02S36VA-167BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA)
CYD02S36V-133BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Commercial
CYD02S36V-133BBI
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Industrial
32K × 36 (1-Mbit) 3.3V Synchronous CYD01S36V Dual-Port SRAM
Speed(
MHz)
167
133
Ordering Code
Package
Name
Package Type
Operating
Range
CYD01S36V-167BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Commercial
CYD01S36V-133BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Commercial
CYD01S36V-133BBI
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0-mm pitch (BGA) Industrial
Document Number: 38-06076 Rev. *G
Page 25 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Package Diagrams
Figure 19. 256-Ball FBGA (17 x 17 mm) BB256
TOP VIEW
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
Ø0.45±0.05(256X)-CPLD DEVICES (37K & 39K)
PIN 1 CORNER
+0.10
-0.05
Ø0.50 (256X)-ALL OTHER DEVICES
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
B
C
C
D
D
1.00
A
E
E
F
F
G
H
J
K
H
15.00
17.00±0.10
G
J
K
L
M
7.50
L
M
N
N
P
P
R
R
T
T
1.00
7.50
0.15 C
0.70±0.05
0.25 C
B
15.00
A
17.00±0.10
A
0.20(4X)
SEATING PLANE
+0.10
-0.05
C
A1 0.36
0.56
REFERENCE JEDEC MO-192
0.35
A1
A 1.40 MAX. 1.70 MAX.
51-85108-*F
Document Number: 38-06076 Rev. *G
Page 26 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Package Diagrams (continued)
Figure 20. 256-ball FBGA (23 mm x 23 mm x 1.7 mm) BB256B
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
+0.10
-0.05
Ø0.50 (256X)
PIN 1 CORNER
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
A
B
B
C
D
1.00
C
D
E
E
F
F
G
J
K
H
15.00
23.00±0.10
G
H
J
K
L
M
7.50
L
M
N
N
P
P
R
R
T
T
1.00
B
7.50
+0.10
-0.05
23.00±0.10
0.20(4X)
51-85201-*A
0.35
0.56
SEATING PLANE
C
0.15 C
1.70 MAX.
0.70±0.05
0.25 C
15.00
A
JEDEC MO-192
Document Number: 38-06076 Rev. *G
Page 27 of 28
[+] Feedback
CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Document History Page
Document Title: CYD01S36V CYD02S36V/36VA/CYD04S36V CYD09S36V/CYD18S36V FLEx36™ 3.3V
32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM
Document Number: 38-06076
REV.
ECN NO.
Orig. of
Change
Submission
Date
Description of Change
**
232012
WWZ
See ECN
New data sheet
*A
244232
WWZ
See ECN
Changed pinout
Changed FTSEL# to FTSEL in the block diagram
*B
313156
YDT
See ECN
Changed pinout D10 from NC to VSS to reflect test mode pin swap, C10 from
rev[2,4] to VSS to reflect SC removal.
Changed tRSCNTINT to tRSINT
Added tRSINT to the master reset timing diagram
Added CYD01S36V to data sheet
Added ISB5 and changed IIX2
*C
321033
YDT
See ECN
Added CYD18S36V-133BBI to the Ordering Information Section
*D
327338
AEQ
See ECN
Change Pinout C10 from VSS to NC[2,5]
Change Pinout G5 from VDDIOL to REVL[2,3]
*E
365315
YDT
See ECN
Added note for VCORE
Removed preliminary status
*F
2193427
NXR/AESA
See ECN
Changed tCD2 and tOE Spec from 4ns to 4.4ns for -167.
Template Update.
*G
2623658
VKN/PYRS
12/17/08
Added CYD02S36VA-15AXC part
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© Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-06076 Rev. *G
Revised Decenber 09, 2008
Page 28 of 28
FLEx36 and FLEx36-E are trademarks of Cypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are property of the respective corporations. All products
and company names mentioned in this document may be the trademarks of their respective holders.
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