CYD02S36V/36VA
FLEx36™ 3.3 V (64K × 36) Synchronous
Dual-Port RAM
FLEx36™ 3.3 V (64K × 36) Synchronous Dual-Port RAM
Features
Functional Description
■
True dual-ported memory cells that enable simultaneous
access of the same memory location
■
Synchronous pipelined operation
■
Pipelined output mode allows fast operation
■
0.18 micron complementary metal oxide semiconductor
(CMOS) for optimum speed and power
■
High speed clock to data access
■
3.3 V low power
❐ Active as low as 225 mA (typ.)
❐ Standby as low as 55 mA (typ.)
■
Mailbox function for message passing
■
Global master reset
■
Separate byte enables on both ports
■
Commercial and industrial temperature ranges
■
IEEE 1149.1-compatible joint test action group (JTAG)
boundary scan
■
256-ball fine-pitch ball grid array (FBGA) (1-mm pitch)
■
Counter wrap around control
❐ Internal mask register controls counter wrap-around
❐ Counter-interrupt flags to indicate wrap-around
❐ Memory block retransmit operation
The FLEx36™ family includes 2-Mbit pipelined, synchronous,
true dual-port static RAMs that are high speed, low power 3.3 V
CMOS. Two ports are provided, permitting independent,
simultaneous access to any location in memory. A particular port
can write to a certain location while another port is reading that
location. The result of writing to the same location by more than
one port at the same time is undefined. Registers on control,
address, and data lines allow for minimal setup and hold time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
■
Counter readback on address lines
■
Mask register readback on address lines
■
Dual chip enables on both ports for easy depth expansion
■
Seamless migration to next-generation dual-port family
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
For a complete list of related documentation, click here.
Seamless Migration to Next-Generation Dual-Port
Family
Cypress offers a migration path for all devices in this family to the
next-generation devices in the Dual-Port family with a compatible
footprint. Please contact Cypress Sales for more details.
Product Selection Guide
2-Mbit
(64K × 36)
Density
Part number
CYD02S36V/36VA
Max. speed (MHz)
167
Max. access time – clock to data (ns)
4.4
Typical operating current (mA)
225
Package
Cypress Semiconductor Corporation
Document Number: 38-06076 Rev. *N
256 FBGA
(17 mm × 17 mm)
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 5, 2017
CYD02S36V/36VA
Logic Block Diagram
FTSELL
FTSELR
CONFIG Block
CONFIG Block
PORTSTD[1:0]R
PORTSTD[1:0]L
DQ [35:0]L
BE [3:0]L
CE0L
CE1L
OEL
IO
Control
IO
Control
DQ [35:0]R
BE [3:0]R
CE0R
CE1R
OER
R/WR
R/WL
Dual Ported Array
BUSYL
A [15:0]L
CNT/MSKL
ADSL
CNTENL
CNTRSTL
RETL
CNTINTL
CL
Arbitration Logic
Address &
Counter Logic
BUSYR
Address &
Counter Logic
WRPL
WRPR
JTAG
TRST
TMS
TDI
TDO
TCK
RESET
LOGIC
MRST
READYR
LowSPDR
Mailboxes
INTL
INTR
READYL
LowSPDL
Document Number: 38-06076 Rev. *N
A [15:0]R
CNT/MSKR
ADSR
CNTENR
CNTRSTR
RETR
CNTINTR
CR
Page 2 of 33
CYD02S36V/36VA
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Master Reset ..................................................................... 7
Mailbox Interrupts ............................................................ 7
Address Counter and Mask Register Operations .......... 8
Counter Reset Operation ............................................ 9
Counter Load Operation .............................................. 9
Counter Increment Operation ...................................... 9
Counter Hold Operation ............................................ 10
Counter Interrupt ....................................................... 10
Counter Readback Operation .................................... 10
Retransmit ................................................................. 10
Mask Reset Operation ............................................... 10
Mask Load Operation ................................................ 10
Mask Readback Operation ........................................ 10
Counting by Two ....................................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG)[19] ............. 12
Performing a TAP Reset ........................................... 12
Performing a Pause/Restart ...................................... 12
Identification Register Definitions ................................ 12
Scan Register Sizes ....................................................... 12
Maximum Ratings ........................................................... 13
Operating Range ............................................................. 13
Electrical Characteristics ............................................... 13
Document Number: 38-06076 Rev. *N
Capacitance .................................................................... 14
AC Test Loads and Waveforms ..................................... 14
JTAG Timing ................................................................... 15
JTAG Switching Waveform ............................................ 15
Switching Characteristics .............................................. 16
Switching Waveforms .................................................... 18
Read/Write and Enable Operation ................................. 28
Ordering Information ...................................................... 29
2-Mbit (64K × 36) 3.3 V
Synchronous CYD02S36V Dual-Port SRAM .................... 29
Ordering Code Definitions ......................................... 29
Package Diagram ............................................................ 30
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC® Solutions ...................................................... 33
Cypress Developer Community ................................. 33
Technical Support ..................................................... 33
Page 3 of 33
CYD02S36V/36VA
Pin Configurations
Figure 1. Pin Diagram - 256-ball FBGA (Top View)
CYD02S36V/36VA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
DQ32L
DQ30L
DQ28L
DQ26L
DQ24L
DQ22L
DQ20L
DQ18L
DQ18R
DQ20R
DQ22R
DQ24R
DQ26R
DQ28R
DQ30R
DQ32R
B
DQ33L
DQ31L
DQ29L
DQ27L
DQ25L
DQ23L
DQ21L
DQ19L
DQ19R
DQ21R
DQ23R
DQ25R
DQ27R
DQ29R
DQ31R
DQ33R
C
DQ34L
DQ35L
RETL
[1, 2]
INTL
NC [1, 3] NC [1, 3]
REVL
[1, 4]
TRST
[1, 3]
MRST
NC [1, 3] NC [1, 3] NC [1, 3]
INTR
RETR
[1, 2]
DQ35R
DQ34R
D
A0L
A1L
WRPL
[1, 2]
VREFL
[1, 4]
FTSELL LOWSP
[1, 2] DL [1, 4]
VSS
VTTL
VTTL
VREFL
[1, 4]
WRPR
[1, 2]
A1R
A0R
E
A2L
A3L
CE0L
CE1L
VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIO
R
F
A4L
A5L
CNTINTL
BE3L
VDDIOL
VSS
VSS
VSS
VSS
G
A6L
A7L
BUSYL
[1, 3]
BE2L
REVL
[1, 2]
VSS
VSS
VSS
H
A8L
A9L
CL
VTTL
VCORE
VSS
VSS
J
A10L
A11L
VSS
PORTST
D1L
[1, 4]
VCORE
VSS
K
A12L
A13L
OEL
BE1L
VDDIOL
L
A14L
A15L
ADSL
BE0L
VDDIOL
VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIO
R
M
NC [1, 3] NC [1, 3]
R/WL
REVL
[1, 4]
N
NC [1, 3] NC [1, 3]
CNT/
MSKL
VREFL
[1, 4]
PortST
D0L
[1, 4]
VSS
LOWSP FTSEL
DR [1, 4] R [1, 2]
VDDIO
R
VDDIO
R
CE1R
CE0R
A3R
A2R
VSS
VSS
VDDIO
R
BE3R
CNTINTR
A5R
A4R
VSS
VSS
VSS
VDDIO
R
BE2R
BUSYR
[1, 3]
A7R
A6R
VSS
VSS
VSS
VSS
VCORE
VTTL
CR
A9R
A8R
VSS
VSS
VSS
VSS
VSS
VCORE
PORTSTD
1R
[1, 4]
VSS
A11R
A10R
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
R
BE1R
OER
A13R
A12R
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
R
BE0R
ADSR
A15R
A14R
VDDIO
R
VDDIO
R
REVR
[1, 4]
R/WR
NC [1, 3] NC [1, 3]
READY
R [1, 3]
PortST
D0R
[1, 4]
VREFR
[1, 4]
CNT/
MSKR
NC [1, 3] NC [1, 3]
READY
L [1, 3]
REVL
[1, 2]
VTTL
VTTL
REVR
[1, 2]
CNTENL CNTRSTL NC [1, 3] NC [1, 3]
TCK
TMS
TDO
TDI
P
DQ16L
DQ17L
R
DQ15L
DQ13L
DQ11L
DQ9L
DQ7L
DQ5L
DQ3L
DQ1L
DQ1R
DQ3R
DQ5R
DQ7R
DQ9R
DQ11R
DQ13R
DQ15R
T
DQ14L
DQ12L
DQ10L
DQ8L
DQ6L
DQ4L
DQ2L
DQ0L
DQ0R
DQ2R
DQ4R
DQ6R
DQ8R
DQ10R
DQ12R
DQ14R
NC [1, 3] NC [1, 3] CNTRSTR CNTENR DQ17R
DQ16R
Notes
1. This ball represents a next generation Dual-Port feature. For more information about this feature, contact Cypress Sales.
2. Connect this ball to VDDIO. For more information about this next generation Dual-Port feature contact Cypress Sales.
3. Leave this ball unconnected. For more information about this feature, contact Cypress Sales.
4. Connect this ball to VSS. For more information about this next generation Dual-Port feature, contact Cypress Sales.
Document Number: 38-06076 Rev. *N
Page 4 of 33
CYD02S36V/36VA
Pin Definitions
Left Port
Right Port
A0L–A15L
A0R–A15R
Description
BE0L–BE3L
BE0R–BE3R
Byte enable inputs. Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
BUSYL[5, 6]
BUSYR[5, 6]
Port busy output. When the collision is detected, a BUSY is asserted.
CL
CR
CE0L
CE0R
Active low chip enable input
Active high chip enable input
Address inputs
Input clock signal
CE1L
CE1R
DQ0L–DQ35L
DQ0R–DQ35R
OEL
OER
Output enable input. This asynchronous signal must be asserted LOW to enable the
DQ data pins during read operations.
INTL
INTR
Mailbox interrupt flag output. The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INTL is asserted LOW
when the right port writes to the mailbox location of the left port, and vice versa. An
interrupt to a port is deasserted HIGH when it reads the contents of its mailbox.
LowSPDL[5, 8]
PORTSTD[1:0]L
LowSPDR[5, 8]
[5, 8]
Data bus input/output.
Port low speed select input.
PORTSTD[1:0]R[5, 8] Port address/control/data io standard select inputs.
R/WL
R/WR
READYL[5, 6]
READYR[5, 6]
CNT/MSKL
CNT/MSKR
ADSL
ADSR
Read/write enable input. Assert this pin LOW to write to, or HIGH to Read from the dual
port memory array.
Port ready output. This signal is asserted when a port is ready for normal operation.
Port counter/mask select input. Counter control input.
Port counter address load strobe input. Counter control input.
CNTENL
CNTENR
CNTRSTL
CNTRSTR
Port counter reset input. Counter control input.
CNTINTL
CNTINTR
Port counter interrupt output. This pin is asserted LOW when the unmasked portion
of the counter is incremented to all “1s”.
WRPL[5, 7]
WRPR[5, 7]
Port counter wrap input. The burst counter wrap control input.
RETR[5, 7]
FTSELR[5, 7]
Port counter retransmit input. Counter control input.
VREFL[5, 8]
VREFR[5, 8]
Port external high-speed io reference input.
VDDIOL
VDDIOR
RETL
[5, 7]
Port counter enable input. Counter control input.
FTSELL
REVL
[5, 7]
[5, 7, 8]
REVR
[5, 7, 8]
MRST
TRST[5, 6]
Flow-through select. Use this pin to select Flow-Through mode. When is de-asserted,
the device is in pipelined mode.
Port I/O power supply.
Reserved pins for future features.
Master reset input. MRST is an asynchronous input signal and affects both ports. A
maser reset operation is required at power up.
JTAG reset input.
Notes
5. This ball represents a next generation Dual-Port feature. For more information about this feature, contact Cypress Sales.
6. Leave this ball unconnected. For more information about this feature, contact Cypress Sales.
7. Connect this ball to VDDIO. For more information about this next generation Dual-Port feature contact Cypress Sales.
8. Connect this ball to VSS. For more information about this next generation Dual-Port feature, contact Cypress Sales.
Document Number: 38-06076 Rev. *N
Page 5 of 33
CYD02S36V/36VA
Pin Definitions (continued)
Left Port
Right Port
Description
TMS
JTAG test mode select input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
TDI
JTAG test data input. Data on the TDI input is shifted serially into selected registers.
TCK
JTAG test clock input.
TDO
JTAG test data output. TDO transitions occur on the falling edge of TCK. TDO is
normally three-stated except when captured data is shifted out of the JTAG TAP.
VSS
Ground inputs.
VCORE[9]
VTTL
Core power supply.
LVTTl power supply for JTAG IOs
Note
9. This family of Dual-Ports does not use VCORE, and these pins are internally NC. The next generation Dual-Port family, the FLEx36-E™, uses VCORE of 1.5 V or 1.8V.
Please contact local Cypress FAE for more information.
Document Number: 38-06076 Rev. *N
Page 6 of 33
CYD02S36V/36VA
Master Reset
The FLEx36 family devices undergo a complete reset by taking
its MRST input LOW. The MRST input can switch asynchronously to the clocks. An MRST initializes the internal burst
counters to zero, and the counter mask registers to all ones
(completely unmasked). MRST also forces the Mailbox Interrupt
(INT) flags and the Counter Interrupt (CNTINT) flags HIGH.
MRST must be performed on the FLEx36 family devices after
power up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 1
shows the interrupt operation for both ports of
CYD02S36V/36VA. The highest memory location, FFFF is the
mailbox for the right port and FFFE is the mailbox for the left port.
Table 1 shows that to set the INTR flag, a Write operation by the
left port to address FFFF asserts INTR LOW. At least one byte
must be active for a Write to generate an interrupt. A valid Read
of the FFFF location by the right port resets INTR HIGH. At least
one byte must be active in order for a Read to reset the interrupt.
When one port Writes to the other port’s mailbox, the INT of the
port that the mailbox belongs to is asserted LOW. The INT is
reset when the owner (port) of the mailbox Reads the contents
of the mailbox. The interrupt flag is set in a flow-thru mode (i.e.,
it follows the clock edge of the writing port). Also, the flag is reset
in a flow-thru mode (i.e., it follows the clock edge of the reading
port).
Each port can read the other port’s mailbox without resetting the
interrupt. And each port can write to its own mailbox without
setting the interrupt. If an application does not require message
passing, INT pins must be left open.
Table 1. Interrupt Operation Example [10, 11, 12, 13]
Function
Left Port
Right Port
R/WL
CEL
A0L–15L
INTL
R/WR
CER
A0R–15R
INTR
Set Right INTR Flag
L
L
FFFF
X
X
X
X
L
Reset Right INTR Flag
X
X
X
X
H
L
FFFF
H
Set Left INTL Flag
X
X
X
L
L
L
FFFE
X
Reset Left INTL Flag
H
L
FFFE
H
X
X
X
X
Notes
10. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge.
11. OE is “Don’t Care” for mailbox operation.
12. At least one of BE0, BE1, BE2, or BE3 must be LOW.
13. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
Document Number: 38-06076 Rev. *N
Page 7 of 33
CYD02S36V/36VA
Address Counter and Mask Register
Operations
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and Counter Reset operations, and by the MRST.
Each port of these devices has a programmable burst address
counter. The burst counter contains three registers: a counter
register, a mask register, and a mirror register.
Table 2 summarizes the operation of these registers and the
required input control signals. The MRST control signal is
asynchronous. All the other control signals in Table 2
(CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1).
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only by
the Mask Load and Mask Reset operations, and by the MRST.
The mask register defines the counting range of the counter
register. It divides the counter register into two regions: zero or
more “0s” in the most significant bits define the masked region,
one or more “1s” in the least significant bits define the unmasked
region. Bit 0 may also be “0,” masking the least significant
counter bit and causing the counter to increment by two instead
of one.
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and use the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter increments on each LOW to HIGH transition of
that port’s clock signal. This Read’s or Write’s one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array, and loops
back to the start. Counter reset (CNTRST) is used to reset the
unmasked portion of the burst counter to 0s. A counter-mask
register is used to control the counter wrap.
Table 2. Address Counter and Counter-Mask Register Control Operation (Any Port) [14, 15]
CLK
MRST
CNT/MSK
CNTRST
ADS
CNTEN
Operation
Description
X
L
X
X
X
X
Masterreset
Reset address counter to all 0s and mask
register to all 1s.
H
H
L
X
X
Counter reset
Reset counter unmasked portion to all 0s.
H
H
H
L
L
Counter load
Load counter with external address value
presented on address lines.
H
H
H
L
H
Counter readback
Read out counter internal value on address
lines.
H
H
H
H
L
Counter increment
Internally increment address counter value.
H
H
H
H
H
Counter hold
Constantly hold the address value for multiple
clock cycles.
H
L
L
X
X
Mask reset
Reset mask register to all 1s.
H
L
H
L
L
Mask load
Load mask register with value presented on
the address lines.
H
L
H
L
H
Mask readback
Read out mask register value on address
lines.
H
L
H
H
X
Reserved
Operation undefined
Notes
14. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
15. Counter operation and mask register operation is independent of chip enables.
Document Number: 38-06076 Rev. *N
Page 8 of 33
CYD02S36V/36VA
Counter Reset Operation
All unmasked bits of the counter and mirror registers are reset to
“0.” All masked bits remain unchanged. A Mask Reset followed
by a Counter Reset resets the counter and mirror registers to
0000, as does master reset (MRST).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Counter Increment Operation
Once the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incremented.
The corresponding bit in the mask register must be a “1” for a
counter bit to change. The counter register is incremented by 1
if the least significant bit is unmasked, and by 2 if it is masked. If
all unmasked bits are “1,” the next increment wraps the counter
back to the initially loaded value. If an Increment results in all the
unmasked bits of the counter being “1s,” a counter interrupt flag
(CNTINT) is asserted. The next Increment returns the counter
register to its initial value, which was stored in the mirror register.
The counter address can instead be forced to loop to 0000 by
externally connecting CNTINT to CNTRST.[16] An increment that
results in one or more of the unmasked bits of the counter being
“0” de-asserts the counter interrupt flag. The example in Figure 2
shows the counter mask register loaded with a mask value of
003Fh unmasking the first 6 bits with bit “0” as the LSB and bit
“16” as the MSB. The maximum value the mask register can be
loaded with is FFFFh. Setting the mask register to this value
allows the counter to access the entire memory space. The
address counter is then loaded with an initial value of 8h. The
base address bits (in this case, the 6th address through the 16th
address) are loaded with an address value but do not increment
once the counter is configured for increment operation. The
counter address starts at address 8h. The counter increments its
internal address value till it reaches the mask register value of
3Fh. The counter wraps around the memory block to location 8h
at the next count. CNTINT is issued when the counter reaches
its maximum value.
Figure 2. Programmable Counter-Mask Register Operation [17]
Example:
Load
Counter-Mask
Register = 3F
CNTINT
H
0
0
0s
215 214
H
X X
Xs
215 214
Max
Address
Register
L
X X
H
X X
215 214
1
1 1
1
Unmasked Address
X 0
0
1
0 0
Xs
X 1 1
1
1
Mask
Register
bit-0
0
26 25 24 23 22 21 20
215 214
Max + 1
Address
Register
1
26 25 24 23 22 21 20
Masked Address
Load
Address
Counter = 8
0 1
1
1
Address
Counter
bit-0
26 25 24 23 22 21 20
Xs
X 0 0
1
0 0
0
26 25 24 23 22 21 20
Notes
16. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
17. The “X” in this diagram represents the counter upper bits.
Document Number: 38-06076 Rev. *N
Page 9 of 33
CYD02S36V/36VA
Counter Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are needed,
or when address is available a few cycles ahead of data in a
shared bus interface.
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset and
Mask Load operations, and by MRST.
Counter Readback Operation
The internal value of the counter register can be read out on the
address lines. Readback is pipelined; the address is valid tCA2
after the next rising edge of the port’s clock. If address readback
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the
data lines (DQs) are three-stated. Figure 3 on page 11 shows a
block diagram of the operation.
Retransmit
Retransmit is a feature that allows the Read of a block of memory
more than once without the need to reload the initial address.
This eliminates the need for external logic to store and route
data. It also reduces the complexity of the system design and
saves board space. An internal “mirror register” is used to store
the initially loaded address counter value. When the counter
unmasked portion reaches its maximum value set by the mask
register, it wraps back to the initial value stored in this “mirror
register.” If the counter is continuously configured in increment
mode, it increments again to its maximum value and wraps back
Document Number: 38-06076 Rev. *N
to the value initially stored into the “mirror register.” Thus, the
repeated access of the same data is allowed without the need
for any external logic.
Mask Reset Operation
The mask register is reset to all “1s,” which unmasks every bit of
the counter. Master reset (MRST) also resets the mask register
to all “1s.”
Mask Load Operation
The mask register is loaded with the address value presented at
the address lines. Not all values permit correct increment operations. Permitted values are of the form 2n – 1 or 2n – 2. From the
most significant bit to the least significant bit, permitted values
have zero or more “0s,” one or more “1s,” or one “0.” Thus FFFF,
03FE, and 0001 are permitted values, but F0FF, 03FC, and 0000
are not.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address is valid tCM2
after the next rising edge of the port’s clock. If mask readback
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the
data lines (DQs) are three-stated. Figure 3 on page 11 shows a
block diagram of the operation.
Counting by Two
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the ×36
devices as a 72-bit single port SRAM in which the counter of one
port counts even addresses and the counter of the other port
counts odd addresses. This even-odd address scheme stores
one half of the 72-bit data in even memory locations, and the
other half in odd memory locations.
Page 10 of 33
CYD02S36V/36VA
Figure 3. Counter, Mask, and Mirror Logic Block Diagram
CNT/MSK
CNTEN
Decode
Logic
ADS
CNTRST
MRST
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
Address
RAM
Decode
Array
CLK
From
Address
Lines
Load/Increment
16
Mirror
1
From
Mask
Register
From
Mask
From
Counter
Increment
Logic
Wrap
16
16
16
16
Bit 0
+1
Wrap
Detect
1
+2
Wrap
0
1
0
Document Number: 38-06076 Rev. *N
To Readback
and Address
Decode
0
0
16
Counter
1
16
To Counter
Page 11 of 33
CYD02S36V/36VA
IEEE 1149.1 Serial Boundary Scan (JTAG)[18]
The FLEx36 family devices incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1-compliant TAPs. The TAP operates
using JEDEC-standard 3.3V IO logic levels. It is composed of
three input connections and one output connection required by
the test logic defined by the standard.
Performing a TAP Reset
devices, and may be performed while the device is operating. An
MRST must be performed on the devices after power up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan
chain outputs the next bit in the chain twice. For example, if the
value expected from the chain is 1010101, the device outputs a
11010101. This extra bit causes some testers to report an
erroneous failure for the devices in a scan test. Therefore the
tester must be configured to never enter the PAUSE-DR state.
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
Identification Register Definitions
Instruction Field
Value
Revision number (31:28)
0h
Cypress device ID (27:12)
C001h
Cypress JEDEC ID (11:1)
034h
ID register presence (0)
1
Description
Reserved for version number.
Defines Cypress part number for CYD02S36V/36VA
Allows unique identification of the DP family device vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
4
Bypass
1
Identification
32
Boundary Scan
n[19]
Table 3. Instruction Identification Codes
Instruction
EXTEST
Code
Description
0000
Captures the input/output ring contents. Places the BSR between the TDI and TDO.
BYPASS
1111
Places the BYR between TDI and TDO.
IDCODE
1011
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
HIGHZ
0111
Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state.
CLAMP
0100
Controls boundary to 1/0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD
1000
Captures the input/output ring contents. Places BSR between TDI and TDO.
NBSRST
1100
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
RESERVED
All other codes
Other combinations are reserved. Do not use other than the above.
Notes
18. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
19. See details in the device BSDL files.
Document Number: 38-06076 Rev. *N
Page 12 of 33
CYD02S36V/36VA
DC Input Voltage ........................... –0.5 V to VDD + 0.5 V[21]
Maximum Ratings
Exceeding maximum ratings[20] may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature
with Power Applied .................................. –55 °C to +125 °C
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage
(JEDEC JESD22-A114-2000B) .............................. > 2000 V
Latch-up Current .................................................... > 200 mA
Operating Range
Supply Voltage to Ground Potential .............–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High-Z State ..................................... –0.5 V to VDD +0.5 V
Range
Ambient
Temperature
VDDIO/VTTL
VCORE[22]
Commercial 0 °C to +70 °C 3.3 V ± 165 mV 1.8 V ± 100 mV
Electrical Characteristics
Over the Operating Range
Parameter
Description
-167
Min
Typ
Max
Unit
VOH
Output HIGH voltage (VDD = Min, IOH= –4.0 mA)
2.4
–
–
V
VOL
Output LOW voltage (VDD = Min, IOL= +4.0 mA)
–
–
0.4
V
VIH
Input HIGH voltage
2.0
–
–
V
VIL
Input LOW voltage
–
–
0.8
V
IOZ
Output leakage current
–10
–
10
A
IIX1
Input leakage current except TDI, TMS, MRST
–10
–
10
A
IIX2
Input leakage current TDI, TMS, MRST
–1.0
–
0.1
mA
ICC
Operating current for (VDD = Max., IOUT = 0 mA), outputs disabled
–
225
300
mA
ISB1
Standby current (both ports TTL level)
–
90
115
mA
–
160
210
mA
–
55
75
mA
–
160
210
mA
–
0
0
mA
CEL and CER VIH, f = fMAX
ISB2
Standby current (one port TTL level)
CEL | CER VIH, f = fMAX
ISB3
Standby current (both ports CMOS level)
CEL and CER VDD – 0.2V, f = 0
ISB4
Standby current (one port CMOS level)
CEL | CER VIH, f = fMAX
ICORE[22]
Core operating current for (VDD = Max, IOUT = 0 mA), outputs disabled
Notes
20. The voltage on any input or IO pin cannot exceed the power pin during power-up.
21. Pulse width < 20 ns.
22. This family of Dual-Ports does not use VCORE, and these pins are internally NC. The next generation Dual-Port family, the FLEx36-E™, uses VCORE of 1.5 V or 1.8 V.
Please contact local Cypress FAE for more information.
Document Number: 38-06076 Rev. *N
Page 13 of 33
CYD02S36V/36VA
Capacitance
Part Number
CYD02S36V/36VA
Parameter [23]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
TA = 25 °C, f = 1 MHz,
VDD = 3.3 V
13
pF
10
pF
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
Z0 = 50
3.3 V
R = 50
R1 = 590
OUTPUT
OUTPUT
C = 10 pF
C = 5 pF
VTH = 1.5 V
(a) Normal Load (Load 1)
3.0 V
ALL INPUT PULSES
(b) Three-state Delay (Load 2)
90%
10%
Vss
< 2 ns
R2 = 435
90%
10%
< 2 ns
Note
23. COUT also references CIO.
Document Number: 38-06076 Rev. *N
Page 14 of 33
CYD02S36V/36VA
JTAG Timing
Parameter
167
Description
Unit
Min
Max
–
10
MHz
fJTAG
Maximum JTAG TAP controller frequency
tTCYC
TCK clock cycle time
100
–
ns
tTH
TCK clock HIGH time
40
–
ns
tTL
TCK clock LOW time
40
–
ns
tTMSS
TMS setup to TCK clock rise
10
–
ns
tTMSH
TMS hold After TCK clock rise
10
–
ns
tTDIS
TDI setup to TCK clock rise
10
–
ns
tTDIH
TDI hold after TCK clock rise
10
–
ns
tTDOV
TCK clock LOW to TDO valid
–
30
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
JTAG Switching Waveform
Figure 5. JTAG Switching Waveform
tTH
tTL
Test Clock
TCK
tTMSS
tTCYC
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
Document Number: 38-06076 Rev. *N
tTDOV
Page 15 of 33
CYD02S36V/36VA
Switching Characteristics
Over the Operating Range
-167
Parameter
Description
CYD02S36V/CYD02S36VA
Unit
Min
Max
–
167
MHz
Clock cycle time
6.0
–
ns
tCH2
Clock HIGH time
2.7
–
ns
tCL2
Clock LOW time
2.7
–
ns
tR[24]
Clock rise time
–
2.0
ns
tF[24]
Clock fall time
–
2.0
ns
tSA
Address setup time
2.3
–
ns
tHA
Address hold time
0.6
–
ns
tSB
Byte select setup time
2.3
–
ns
tHB
Byte select hold time
0.6
–
ns
tSC
Chip enable setup time
2.3
–
ns
tHC
Chip enable hold time
0.6
–
ns
tSW
R/W setup time
2.3
–
ns
tHW
R/W hold time
0.6
–
ns
tSD
Input data setup time
2.3
–
ns
tHD
Input data hold time
0.6
–
ns
tSAD
ADS setup time
2.3
–
ns
tHAD
ADS hold time
0.6
–
ns
tSCN
CNTEN setup time
2.3
–
ns
tHCN
CNTEN hold time
0.6
–
ns
tSRST
CNTRST setup time
2.3
–
ns
tHRST
CNTRST hold time
0.6
–
ns
tSCM
CNT/MSK setup time
2.3
–
ns
tHCM
CNT/MSK hold time
0.6
–
ns
fMAX2
Maximum operating frequency
tCYC2
Note
24. Except JTAG signals (tr and tf < 10 ns [max.]).
Document Number: 38-06076 Rev. *N
Page 16 of 33
CYD02S36V/36VA
Switching Characteristics (continued)
Over the Operating Range
-167
Parameter
Description
CYD02S36V/CYD02S36VA
Min
Max
Unit
tOE
Output enable to data valid
–
4.4
ns
tOLZ[25, 26]
tOHZ[25, 26]
OE to Low Z
0
–
ns
OE to High Z
0
4.0
ns
tCD2
Clock to data valid
–
4.4
ns
tCA2
Clock to counter address valid
–
4.0
ns
tCM2
Clock to mask register readback valid
–
4.0
ns
tDC
Data output hold after clock HIGH
1.0
–
ns
tCKHZ[25, 26]
Clock HIGH to output high Z
0
4.0
ns
tCKLZ[25, 26]
Clock HIGH to output low Z
1.0
4.0
ns
tSINT
Clock to INT set time
0.5
6.7
ns
tRINT
Clock to INT reset time
0.5
6.7
ns
tSCINT
Clock to CNTINT set time
0.5
5.0
ns
tRCINT
Clock to CNTINT reset time
0.5
5.0
ns
5.2
–
ns
Port to Port Delays
tCCS
Clock to clock skew
Master Reset Timing
tRS
Master reset pulse width
5.0
–
cycle
s
tRS
Master reset setup time
6.0
–
ns
tRSR
Master reset recovery time
5.0
–
cycle
s
tRSF
Master reset to outputs inactive
–
10.0
ns
tRSINT
Master reset to counter and mailbox interrupt flag reset time
–
10.0
ns
Notes
25. This parameter is guaranteed by design, but it is not production tested.
26. Test conditions used are Load 2.
Document Number: 38-06076 Rev. *N
Page 17 of 33
CYD02S36V/36VA
Switching Waveforms
Figure 6. Master Reset
tRS
MRST
tRSF
ALL
ADDRESS/
DATA
LINES
tRSS
ALL
OTHER
INPUTS
TMS
tRSR
INACTIVE
ACTIVE
tRSINT
CNTINT
INT
TDO
Figure 7. Read Cycle [27, 28, 29, 30, 31]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSB
tHB
tSW
tSA
tHW
tHA
tSC
tHC
BE0–BE3
R/W
ADDRESS
DATAOUT
An
An+1
1 Latency
An+2
tDC
tCD2
Qn
tCKLZ
An+3
Qn+1
tOHZ
Qn+2
tOLZ
OE
tOE
Notes
27. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge.
28. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
29. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
30. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock.
31. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK.
Numbers are for reference only.
Document Number: 38-06076 Rev. *N
Page 18 of 33
CYD02S36V/36VA
Switching Waveforms (continued)
Figure 8. Bank Select Read [32, 33]
tCH2
tCYC2
tCL2
CLK
tHA
tSA
ADDRESS(B1)
A0
A1
A3
A2
A4
A5
tHC
tSC
CE(B1)
tCD2
tHC
tSC
tCD2
tHA
tSA
A0
ADDRESS(B2)
tDC
A1
tDC
tSC
tCKLZ
A3
A2
tCKHZ
Q3
Q1
Q0
DATAOUT(B1)
tCD2
tCKHZ
A4
A5
tHC
CE(B2)
tSC
tHC
tCD2
DATAOUT(B2)
tCKHZ
tCD2
Q4
Q2
tCKLZ
tCKLZ
Notes
32. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx36 device from this data sheet. ADDRESS(B1)
= ADDRESS(B2).
33. ADS = CNTEN= BE0 – BE3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
Document Number: 38-06076 Rev. *N
Page 19 of 33
CYD02S36V/36VA
Switching Waveforms (continued)
Figure 9. Read-to-Write-to-Read (OE = LOW) [34, 35, 36, 37, 38]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
tSA
An+1
An+2
An+2
An+3
tSD tHD
tHA
DATAIN
An+2
tCD2
tDC
tCKHZ
Dn+2
Qn
DATAOUT
READ
NO OPERATION
WRITE
Notes
34. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK.
Numbers are for reference only.
35. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
36. During “No Operation,” data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity.
37. CE0 = OE = BE0 – BE3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
38. CE0 = BE0 – BE3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the IO for the Write operation on the next rising edge of CLK.
Document Number: 38-06076 Rev. *N
Page 20 of 33
CYD02S36V/36VA
Switching Waveforms (continued)
Figure 10. Read-to-Write-to-Read (OE Controlled) [39, 40, 41, 42]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSW tHW
R/W
ADDRESS
tSW
tHW
An
tSA
An+1
An+2
tHA
An+3
An+4
An+5
tSD tHD
Dn+2
DATAIN
Dn+3
tCD2
DATAOUT
tCD2
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Figure 11. Read with Address Counter Advance [41]
tCH2
tCYC2
tCL2
CLK
tSA
ADDRESS
tHA
An
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DATAOUT
tHCN
Qx–1
tCD2
Qx
READ
EXTERNAL
ADDRESS
tDC
Qn
READ WITH COUNTER
Qn+1
COUNTER HOLD
Qn+2
Qn+3
READ WITH COUNTER
Notes
39. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK.
Numbers are for reference only.
40. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
41. CE0 = OE = BE0 – BE3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
42. CE0 = BE0 – BE3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the IO for the Write operation on the next rising edge of CLK.
Document Number: 38-06076 Rev. *N
Page 21 of 33
CYD02S36V/36VA
Switching Waveforms (continued)
Figure 12. Write with Address Counter Advance [43]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
tSAD
tHAD
tSCN
tHCN
An+1
An+2
An+3
An+4
ADS
CNTEN
Dn
DATAIN
tSD
tHD
WRITE EXTERNAL
ADDRESS
Dn+1
Dn+1
WRITE WITH
COUNTER
Dn+2
WRITE COUNTER
HOLD
Dn+3
Dn+4
WRITE WITH COUNTER
Note
43. CE0 = BE0 – BE3 = LOW; CE1 = MRST = CNT/MSK = HIGH.
Document Number: 38-06076 Rev. *N
Page 22 of 33
CYD02S36V/36VA
Switching Waveforms (continued)
Figure 13. Counter Reset [44, 45]
tCYC2
tCH2 tCL2
CLK
tSA
INTERNAL
ADDRESS
Ax
tSW
tHW
tSD
tHD
An
1
0
Ap
Am
An
ADDRESS
tHA
Ap
Am
R/W
ADS
CNTEN
tSRST tHRST
CNTRST
DATAIN
D0
tCD2
tCD2
[46]
DATAOUT
Q0
COUNTER
RESET
WRITE
ADDRESS 0
tCKLZ
READ
ADDRESS 0
READ
ADDRESS 1
Qn
Q1
READ
ADDRESS An
READ
ADDRESS Am
Notes
44. CE0 = BE0 – BE3 = LOW; CE1 = MRST = CNT/MSK = HIGH.
45. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
46. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
Document Number: 38-06076 Rev. *N
Page 23 of 33
CYD02S36V/36VA
Switching Waveforms (continued)
Figure 14. Readback State of Address Counter or Mask Register [47, 48, 49, 50]
tCYC2
tCH2 tCL2
CLK
tCA2 or tCM2
tSA tHA
EXTERNAL
ADDRESS
A0–A16
An*
An
INTERNAL
ADDRESS
An+1
An
An+2
An+3
An+4
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tCD2
DATAOUT
Qx-2
LOAD
EXTERNAL
ADDRESS
tCKHZ
Qx-1
Qn
READBACK
COUNTER
INTERNAL
ADDRESS
INCREMENT
tCKLZ
Qn+1
Qn+2
Qn+3
Notes
47. CE0 = OE = BE0 – BE3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
48. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle.
49. Address in input mode. Host can drive address bus after tCKHZ.
50. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Document Number: 38-06076 Rev. *N
Page 24 of 33
CYD02S36V/36VA
Switching Waveforms (continued)
Figure 15. Left_Port (L_Port) Write to Right_Port (R_Port) Read [51, 52, 53]
tCH2
tCYC2
tCL2
CLKL
tHA
tSA
L_PORT
ADDRESS
An
tSW
tHW
R/WL
tCKHZ
tSD
L_PORT
DATAIN
CLKR
tHD
tCKLZ
Dn
tCYC2
tCL2
tCCS
tCH2
R_PORT
ADDRESS
tSA
tHA
An
R/WR
tCD2
R_PORT
Qn
DATAOUT
tDC
Notes
51. CE0 = OE = ADS = CNTEN = BE0 – BE3 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
52. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data is Read out.
53. If tCCS < minimum specified value, then R_Port Reads the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock. If tCCS
> minimum specified value, then R_Port Reads the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock.
Document Number: 38-06076 Rev. *N
Page 25 of 33
CYD02S36V/36VA
Switching Waveforms (continued)
Figure 16. Counter Interrupt and Retransmit [54, 55, 56, 57, 58, 59]
tCH2
tCYC2
tCL2
CLK
tSCM
tHCM
CNT/MSK
ADS
CNTEN
COUNTER
INTERNAL
ADDRESS
FFFC
FFFD
FFFE
tSCINT
FFFF
Last_Loaded
Last_Loaded +1
tRCINT
CNTINT
Notes
54. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
55. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
56. CE0 = OE = BE0 – BE3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
57. CNTINT is always driven.
58. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
59. The mask register assumed to have the value of FFFFh.
Document Number: 38-06076 Rev. *N
Page 26 of 33
CYD02S36V/36VA
Switching Waveforms (continued)
Figure 17. MailBox Interrupt Timing [60, 61, 62, 63, 64]
tCH2
tCYC2
tCL2
CLKL
tSA
L_PORT
ADDRESS
tHA
FFFF
An+1
An
An+2
An+3
tSINT
tRINT
INTR
tCH2
tCYC2
tCL2
CLKR
tSA
R_PORT
ADDRESS
Am
tHA
Am+1
FFFF
Am+3
Am+4
Notes
60. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
61. Address “FFFF” is the mailbox location for R_Port of this device.
62. L_Port is configured for Write operation, and R_Port is configured for Read operation.
63. At least one byte enable (BE0–BE3) is required to be active during interrupt operations.
64. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
Document Number: 38-06076 Rev. *N
Page 27 of 33
CYD02S36V/36VA
Read/Write and Enable Operation
Table 4. Read/Write and Enable Operation (Any Port) [65, 66, 67, 68]
Inputs
OE
Operation
CE0
CE1
R/W
DQ0–DQ35
X
H
X
X
High-Z
Deselected
X
X
L
X
High-Z
Deselected
X
L
H
L
DIN
Write
L
L
H
H
DOUT
Read
L
H
X
High-Z
Outputs disabled
H
CLK
Outputs
X
Notes
65. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
66. OE is an asynchronous input signal.
67. When CE changes state, deselection and Read happen after one cycle of latency.
68. CE0 = OE = LOW; CE1 = R/W = HIGH.
Document Number: 38-06076 Rev. *N
Page 28 of 33
CYD02S36V/36VA
Ordering Information
2-Mbit (64K × 36) 3.3 V Synchronous CYD02S36V Dual-Port SRAM
Speed
(MHz)
167
Ordering Code
CYD02S36VA-167BBC
Package
Name
BB256
CYD02S36VA-167BBXC
Package Type
256-ball BGA
Operating
Range
Commercial
256-ball BGA Pb-free
Ordering Code Definitions
CY D
02
S
36 VA - 167 BB X
C
Temperature Range:
C = Commercial
X = Pb-free; blank = non Pb-free
Package Type:
BB = 256-ball BGA
Speed Grade: 167 MHz
VA = 3.3 V
Width: 36 = × 36
S = Sync
Density: 02 = 2 Mb
Marketing Code: D = Dual-Port SRAM
Company ID: CY = Cypress
Document Number: 38-06076 Rev. *N
Page 29 of 33
CYD02S36V/36VA
Package Diagram
Figure 18. 256-ball FBGA (17 × 17 × 1.7 mm) Package Outline, 51-85108
51-85108 *J
Document Number: 38-06076 Rev. *N
Page 30 of 33
CYD02S36V/36VA
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BGA
Ball Grid Array
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
FBGA
Fine-Pitch Ball Grid Array
MHz
megahertz
I/O
Input/Output
A
microampere
JTAG
Joint Test Action Group
mA
milliampere
SRAM
Static Random Access Memory
ns
nanosecond
ohm
pF
picofarad
V
volt
W
watt
Document Number: 38-06076 Rev. *N
Symbol
Unit of Measure
Page 31 of 33
CYD02S36V/36VA
Document History Page
Document Title: CYD02S36V/36VA, FLEx36™ 3.3 V (64K × 36) Synchronous Dual-Port RAM
Document Number: 38-06076
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
232012
WWZ
See ECN
New data sheet.
*A
244232
WWZ
See ECN
Changed pinout
Changed FTSEL# to FTSEL in the block diagram
*B
313156
YDT
See ECN
Changed pinout D10 from NC to VSS to reflect test mode pin swap, C10 from
rev[2,4] to VSS to reflect SC removal.
Changed tRSCNTINT to tRSINT
Added tRSINT to the master reset timing diagram
Added CYD01S36V to data sheet
Added ISB5 and changed IIX2
*C
321033
YDT
See ECN
Added CYD18S36V-133BBI to the Ordering Information Section
*D
327338
AEQ
See ECN
Change Pinout C10 from VSS to NC[2,5]
Change Pinout G5 from VDDIOL to REVL[2,3]
*E
365315
YDT
See ECN
Added note for VCORE
Removed preliminary status
*F
2193427
NXR /
AESA
See ECN
Changed tCD2 and tOE Spec from 4ns to 4.4ns for -167.
Template Update.
*G
2623658
VKN /
PYRS
12/17/08
Added CYD02S36VA-15AXC part
*H
2899734
VKN
03/26/2010
Modified title on page 1
Removed 1M, 4M, 9M, and 18M densities and their related information
Modified Logic block diagram and pin configuration
Removed Industrial operating grade
Removed 133 ns and 100ns speed bins
Removed “BB256B” (23 x 23 x 1.7mm) 256-Ball FBGA package
Updated Ordering Information table
Updated “BB256” (17 x 17 x 1.7mm) 256-Ball FBGA package diagram
*I
3110296
ADMU
12/14/2010
Updated Ordering Information.
Added Ordering Code Definitions.
*J
3202287
ADMU
03/22/2011
Updated notes
Added Acronyms and Units of Measure.
Updated to new template.
*K
3843734
SMCH
12/17/2012
Updated Ordering Information:
Updated part numbers.
Updated Package Diagram:
spec 51-85108 – Changed revision from *H to *I.
*L
4336717
ADMU
04/08/2014
Updated to new template.
*M
4581625
ADMU
11/27/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*N
5726610
VINI
05/05/2017
Updated Package Diagram:
spec 51-85108 – Changed revision from *I to *J.
Updated to new template.
Completing Sunset Review.
Document Number: 38-06076 Rev. *N
Description of Change
Page 32 of 33
CYD02S36V/36VA
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Internet of Things
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-06076 Rev. *N
FLEx36 and FLEx36-E are trademarks of Cypress Semiconductor Corporation.
Revised May 05, 2017
Page 33 of 33
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