CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
FLEx18™ 3.3V 64K/128K/256K/512K x 18
Synchronous Dual-Port RAM
Features
Functional Description
• True dual-ported memory cells that allow simultaneous
access of the same memory location
• Synchronous pipelined operation
• Organization of 1 Mbit, 2 Mbits, 4 Mbits and 9 Mbits
devices
• Pipelined output mode allows fast operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access
• 3.3V low power
— Active as low as 225 mA (typ)
— Standby as low as 55 mA (typ)
• Mailbox function for message passing
• Global master reset
The FLEx18™ family includes 1-Mbit, 2-Mbit, 4-Mbit and
9-Mbit pipelined, synchronous, true dual-port static RAMs that
are high-speed, low-power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. The result of writing to the same location
by more than one port at the same time is undefined. Registers
on control, address, and data lines allow for minimal set-up
and hold time.
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address internally (more details to follow). The internal Write pulse width is
independent of the duration of the R/W input signal. The
internal Write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 256-ball FBGA (1 mm pitch)
• Counter wrap-around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
• Counter readback on address lines
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CYD09S18V device in this family has limited features.
Please see Address Counter and Mask Register Operations
on page 5 for details.
• Mask register readback on address lines
• Dual Chip Enables on both ports for easy depth
expansion
Seamless Migration to Next Generation Dual Port Family
• Seamless migration to next-generation dual-port family
Cypress offers a migration path for all devices in this family to
the next-generation devices in the Dual-Port family with a
compatible footprint. Please contact Cypress Sales for more
details.
Table 1. Product Selection Guide
1 Mbit
(64K x 18)
2 Mbit
(128K x 18)
4 Mbit
(256K x 18)
9 Mbit
(512K x 18)
CYD01S18V
CYD02S18V
CYD04S18V
CYD09S18V
Max. Speed (MHz)
167
167
167
133
Max. Access Time – Clock to Data (ns)
4.0
4.0
4.0
4.7
225
225
225
270
Density
Part Number
Typical operating current (mA)
Package
Cypress Semiconductor Corporation
Document #: 38-06077 Rev. *C
256FBGA
256FBGA
256FBGA
256FBGA
(17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm) (17 mm x 17 mm)
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised May 5, 2005
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Logic Block Diagram[1]
FTSELL
FTSELR
CONFIG Block
CONFIG Block
PORTSTD(1:0)R
PORTSTD(1:0)L
DQ (17:0)L
BE (1:0)L
CE0L
CE1L
OEL
IO
Control
IO
Control
DQ (17:0)R
BE (1:0)R
CE0R
CE1R
OER
R/WR
R/WL
Dual Ported Array
BUSYL
A (18:0)L
CNT/MSKL
ADSL
CNTENL
CNTRSTL
RETL
CNTINTL
CL
Arbitration Logic
Address &
Counter Logic
BUSYR
Address &
Counter Logic
WRPL
A (18:0)R
CNT/MSKR
ADSR
CNTENR
CNTRSTR
RETR
CNTINTR
CR
WRPR
JTAG
TRST
TMS
TDI
TDO
TCK
RESET
LOGIC
MRST
READYR
LowSPDR
Mailboxes
INTL
INTR
READYL
LowSPDL
Note:
1. CYD01S18V has 16 address bits, CYD02S18V has 17 address bits, CY04S18V has 18 address bits and CYD09S18V has 19 address bits.
Document #: 38-06077 Rev. *C
Page 2 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Pin Configurations
256-ball BGA Top View
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
NC
NC
NC
DQ17L
DQ16L
DQ13L
DQ12L
DQ9L
DQ9R
DQ12R
DQ13R
DQ16R
DQ17R
NC
NC
NC
B
NC
NC
NC
NC
DQ15L
DQ14L
DQ11L
DQ10L
DQ10R
DQ11R
DQ14R
DQ15R
NC
NC
NC
NC
C
NC
NC
RETL
INTL
NC
[2,5]
NC
[2,5]
REVL
MRST
[2,5]
NC
[2,5]
NC
[2,5]
INTR
RETR
[2,4]
TRST
[2,5]
NC
[2,3]
NC
NC
D
A0L
A1L
WRPL
[2,3]
VREFL
[2,4]
FTSELL
[2,3]
LowSPDL
[2,4]
VSS
VTTL
VTTL
VSS
LowSPDR
[2,4]
FTSELR
[2,3]
VREFR
[2,4]
WRPR
[2,3]
A1R
A0R
E
A2L
A3L
CE0L
F
A4L
A5L
G
A6L
H
[2,3]
CE1L
[9]
VDDIOL
VDDIOL
VDDIOL
VCORE
VCORE
VDDIOR
VDDIOR
VDDIOR
CE1R
CE0R
[10]
[10]
A3R
A2R
CNTINTL
[11]
NC
VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
NC
CNTINTR
[11]
A5R
A4R
A7L
BUSYL
NC
REVL
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
NC
BUSYR
[2,5]
A7R
A6R
A8L
A9L
CL
VTTL
VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VCORE
VTTL
CR
A9R
A8R
J
A10L
A11L
VSS
PortSTD1L
[2,4]
VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VCORE
PortSTD1R
[2,4]
VSS
A11R
A10R
K
A12L
A13L
OEL
BE1L
VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
BE1R
OER
A13R
A12R
L
A14L
A15L
ADSL
BE0L
VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
BE0R
ADSR
A15R
A14R
M
A16L
[6]
A17L
[7]
RWL
VDDIOL
VDDIOL
VDDIOL
VCORE
VCORE
VDDIOR
VDDIOR
VDDIOR
RWR
A17R
[7]
A16R
[6]
N
A18L
[8]
NC
CNT/
MSKL
[9]
VREFL
[2,4]
PortSTD0L
[2,4]
READYL
[2,5]
REVL
VTTL
VTTL
[2,3]
READYR
[2,5]
PortSTD0R
[2,4]
VREFR
[2,4]
CNT/
MSKR
[9]
NC
A18R
[8]
P
NC
NC
CNTENL
[10]
CNTRSTL
[9]
NC
[2,5]
NC
[2,5]
TCK
TMS
TDO
TDI
NC
[2,5]
NC
[2,5]
CNTRSTR
[9]
CNTENR
[10]
NC
NC
R
NC
NC
NC
NC
DQ6L
DQ5L
DQ2L
DQ1L
DQ1R
DQ2R
DQ5R
DQ6R
NC
NC
NC
NC
T
NC
NC
NC
DQ8L
DQ7L
DQ4L
DQ3L
DQ0L
DQ0R
DQ3R
DQ4R
DQ7R
DQ8R
NC
NC
NC
[2,5]
[10]
REVL
[2,4]
[2,3]
[2,3]
REVR
[9]
[10]
REVR
[2,4]
Notes:
2. This ball will represent a next generation FLEx18-E Dual-Port feature. For more information about this feature, contact Cypress Sales.
3. Connect this ball to VDDIO. For more information about this next generation FLEx18-E Dual-Port feature contact Cypress Sales.
4. Connect this ball to VSS. For more information about this next generation FLEx18-E Dual-Port feature, contact Cypress Sales.
5. Leave this ball unconnected. For more information about this feature, contact Cypress Sales.
6. Leave this ball unconnected for a 64K x 18.
7. Leave this ball unconnected for a 128K x 18 and 64K x 18.
8. Leave this ball unconnected for a 256K x 18, 128K x 18 and 64K x 18.
9. These balls are not applicable for CYD09S18V device. They need to be tied to VDDIO.
10. These balls are not applicable for CYD09S18V device. They need to be tied to VSS.
11. These balls are not applicable for CYD09S18V device. They need to be no connected.
Document #: 38-06077 Rev. *C
Page 3 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Pin Definitions
Left Port
Right Port
A0L–A18L
A0R–A18R
BE0L–BE1L
BE0R–BE1R
Byte Enable Inputs. Asserting these signals enables Read and Write operations to
the corresponding bytes of the memory array.
BUSYL[2,5]
BUSYR[2,5]
Port Busy Output. When the collision is detected, a BUSY is asserted.
CL
CR
Input Clock Signal.
[10]
Active Low Chip Enable Input.
CE1L[9]
CE1R[9]
Active High Chip Enable Input.
DQ0L–DQ17L
DQ0R–DQ17R
OEL
OER
Output Enable Input. This asynchronous signal must be asserted LOW to enable
the DQ data pins during Read operations.
INTL
INTR
Mailbox Interrupt Flag Output. The mailbox permits communications between ports.
The upper two memory locations can be used for message passing. INTL is asserted
LOW when the right port writes to the mailbox location of the left port, and vice versa.
An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox.
LowSPDL[2,4]
LowSPDR[2,4]
Port Low Speed Select Input. When operating at less than 100 MHz, the LowSPD
disables the port DLL.
CE0L
[10]
Description
Address Inputs.
CE0R
Data Bus Input/Output.
PORTSTD[1:0]L[2,4] PORTSTD[1:0]R[2,4] Port Address/Control/Data I/O Standard Select Input.
R/WL
R/WR
READYL[2,5]
READYR[2,5]
Port Ready Output. This signal will be asserted when a port is ready for normal
operation.
CNT/MSKL[9]
CNT/MSKR[9]
Port Counter/Mask Select Input. Counter control input.
ADSL[10]
CNTENL[10]
CNTRSTL[9]
CNTINTL[11]
ADSR[10]
CNTENR[10]
CNTRSTR[9]
CNTINTR[11]
Port Counter Address Load Strobe Input. Counter control input.
WRPL[2,3]
WRPR[2,3]
Port Counter Wrap Input. After the burst counter reaches the maximum count, if
WRP is low, the unmasked counter bits will be set to 0. If high, the counter will be
loaded with the value stored in the mirror register.
RETL[2,3]
RETR[2,3]
Port Counter Retransmit Input. Counter control input.
[2,3]
FTSELR
[2,4]
VREFR[2,4]
FTSELL
VREFL
[2,3]
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to read from the
dual-port memory array.
Port Counter Enable Input. Counter control input.
Port Counter Reset Input. Counter control input.
Port Counter Interrupt Output. This pin is asserted LOW when the unmasked
portion of the counter is incremented to all “1s”.
Flow-Through Mode Select Input.
Port External High-Speed IO Reference Input.
VDDIOL
VDDIOR
Port IO Power Supply.
REVL[2,4]
REVR[2,4]
Reserved pins for future features.
MRST
TRST[2,5]
Master Reset Input. MRST is an asynchronous input signal and affects both ports.
A master reset operation is required at power-up.
JTAG Reset Input.
TMS
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine.
State machine transitions occur on the rising edge of TCK.
TDI
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected
registers.
TCK
JTAG Test Clock Input.
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is
normally three-stated except when captured data is shifted out of the JTAG TAP.
Document #: 38-06077 Rev. *C
Page 4 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Pin Definitions (continued)
Left Port
Right Port
VSS
Description
Ground Inputs.
VCORE[12]
Core Power Supply.
VTTL
LVTTL Power Supply.
Master Reset
The FLEx18 family devices undergo a complete reset by
taking its MRST input LOW. The MRST input can switch
asynchronously to the clocks. The MRST initializes the
internal burst counters to zero, and the counter mask registers
to all ones (completely unmasked). The MRST also forces the
Mailbox Interrupt (INT) flags and the Counter Interrupt
(CNTINT) flags HIGH. The MRST must be performed on the
FLEx18 family devices after power-up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table
shows the interrupt operation for both ports of CYD09S18V.
The highest memory location, 7FFFF is the mailbox for the
right port and 7FFFE is the mailbox for the left port. Table
shows that in order to set the INTR flag, a Write operation by
the left port to address 7FFFF will assert INTR LOW. At least
one byte has to be active for a Write to generate an interrupt.
A valid Read of the 7FFFF location by the right port will reset
INTR HIGH. At least one byte has to be active in order for a
Read to reset the interrupt. When one port Writes to the other
port’s mailbox, the INT of the port that the mailbox belongs to
is asserted LOW. The INT is reset when the owner (port) of the
mailbox Reads the contents of the mailbox. The interrupt flag
is set in a flow-thru mode (i.e., it follows the clock edge of the
writing port). Also, the flag is reset in a flow-thru mode (i.e., it
follows the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
Address Counter and Mask Register
Operations
This section describes the features only apply to 1-Mbit,
2-Mbit, and 4-Mbit devices. It does not apply to a 9-Mbit
device. Each port of these devices has a programmable burst
address counter. The burst counter contains three registers: a
counter register, a mask register, and a mirror register.[17]
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only
by the Mask Load and Mask Reset operations, and by the
MRST. The mask register defines the counting range of the
counter register. It divides the counter register into two
regions: zero or more “0s” in the most significant bits define
the masked region, one or more “1s” in the least significant bits
define the unmasked region. Bit 0 may also be “0,” masking
the least significant counter bit and causing the counter to
increment by two instead of one.
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and Counter Reset operations, and by the MRST.
Table 3 summarizes the operation of these registers and the
required input control signals. The MRST control signal is
asynchronous. All the other control signals in Table 3
(CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1).
Table 2. Interrupt Operation Example [1, 13, 14, 15, 16]
Left Port
Function
Right Port
R/WL
CEL
A0L–18L
INTL
R/WR
CER
A0R–18R
INTR
Set Right INTR Flag
L
L
7FFFF
X
X
X
X
L
Reset Right INTR Flag
X
X
X
X
H
L
7FFFF
H
Set Left INTL Flag
X
X
X
L
L
L
7FFFE
X
Reset Left INTL Flag
H
L
7FFFE
H
X
X
X
X
Notes:
12. This family of Dual-Ports does not use VCORE, and these pins are internally NC. The next generation Dual-Port family, the FLEx18-E™, will use VCORE of 1.5V
or 1.8V. Please contact local Cypress FAE for more information.
13. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK
and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
14. OE is “Don’t Care” for mailbox operation.
15. At least one of BE0, BE1 must be LOW.
16. A18x is a NC for CYD04S18V, therefore the Interrupt Addresses are 3FFFF and 3FFFE. A18x and A17x are NC for CYD02S18V, therefore the Interrupt addresses
are 1FFFF and 1FFFE; A18x, A17x and A16x are NC for CYD01S18V, therefore the Interrupt Addresses are FFFF and FFFE.
17. This section describes the CYD04S18V, CYD02S18V, CYD01S18V 18, 17, and 16 address bits.
Document #: 38-06077 Rev. *C
Page 5 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port) [18, 19]
CLK
MRST
CNT/MSK
CNTRST
ADS
CNTEN
X
L
X
X
X
X
Master Reset
Reset address counter to all 0s and mask
register to all 1s.
H
H
L
X
X
Counter Reset
Reset counter unmasked portion to all 0s.
H
H
H
L
L
Counter Load
Load counter with external address value
presented on address lines.
H
H
H
L
H
Counter Readback Read out counter internal value on address
lines.
H
H
H
H
L
Counter Increment Internally increment address counter value.
H
H
H
H
H
Counter Hold
Constantly hold the address value for
multiple clock cycles.
H
L
L
X
X
Mask Reset
Reset mask register to all 1s.
H
L
H
L
L
Mask Load
Load mask register with value presented on
the address lines.
H
L
H
L
H
Mask Readback
Read out mask register value on address lines.
H
L
H
H
X
Reserved
Operation undefined
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH
transition of that port’s clock signal. This will Read/Write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array, and will loop back to the start. Counter reset (CNTRST)
is used to reset the unmasked portion of the burst counter to
0s. A counter-mask register is used to control the counter
wrap.
Counter Reset Operation
All unmasked bits of the counter and mirror registers are reset
to “0.” All masked bits remain unchanged. A Mask Reset
followed by a Counter Reset will reset the counter and mirror
registers to 00000, as will master reset (MRST).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Counter Increment Operation
Once the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incremented. The corresponding bit in the mask register must be
a “1” for a counter bit to change. The counter register is incremented by 1 if the least significant bit is unmasked, and by 2
Operation
Description
if it is masked. If all unmasked bits are “1,” the next increment
will wrap the counter back to the initially loaded value. If an
Increment results in all the unmasked bits of the counter being
“1s,” a counter interrupt flag (CNTINT) is asserted.
The next Increment will return the counter register to its initial
value, which was stored in the mirror register. The counter
address can instead be forced to loop to 00000 by externally
connecting CNTINT to CNTRST.[20] An increment that results
in one or more of the unmasked bits of the counter being “0”
will deassert the counter interrupt flag. The example in
Figure 2 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit “0” as the
LSB and bit “16” as the MSB. The maximum value the mask
register can be loaded with is 3FFFFh. Setting the mask
register to this value allows the counter to access the entire
memory space. The address counter is then loaded with an
initial value of 8h. The base address bits (in this case, the 6th
address through the 16th address) are loaded with an address
value but do not increment once the counter is configured for
increment operation. The counter address will start at address
8h. The counter will increment its internal address value till it
reaches the mask register value of 3Fh. The counter wraps
around the memory block to location 8h at the next count.
CNTINT is issued when the counter reaches its maximum
value.
Counter Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are
needed, or when address is available a few cycles ahead of
data in a shared bus interface.
Notes:
18. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
19. Counter operation and mask register operation is independent of chip enables.
20. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
Document #: 38-06077 Rev. *C
Page 6 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Counter Interrupt
Mask Reset Operation
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
deasserted by Counter Reset, Counter Load, Mask Reset and
Mask Load operations, and by MRST.
The mask register is reset to all “1s,” which unmasks every bit
of the counter. Master reset (MRST) also resets the mask
register to all “1s.”
Counter Readback Operation
The internal value of the counter register can be read out on
the address lines. Readback is pipelined; the address will be
valid tCA2 after the next rising edge of the port’s clock. If
address readback occurs while the port is enabled (CE0 LOW
and CE1 HIGH), the data lines (DQs) will be three-stated.
Figure 1 shows a block diagram of the operation.
Retransmit
Retransmit is a feature that allows the Read of a block of
memory more than once without the need to reload the initial
address. This eliminates the need for external logic to store
and route data. It also reduces the complexity of the system
design and saves board space. An internal “mirror register” is
used to store the initially loaded address counter value. When
the counter unmasked portion reaches its maximum value set
by the mask register, it wraps back to the initial value stored in
this “mirror register.” If the counter is continuously configured
in increment mode, it increments again to its maximum value
and wraps back to the value initially stored into the “mirror
register.” Thus, the repeated access of the same data is
allowed without the need for any external logic.
Document #: 38-06077 Rev. *C
Mask Load Operation
The mask register is loaded with the address value presented
at the address lines. Not all values permit correct increment
operations. Permitted values are of the form 2n – 1 or 2n – 2.
From the most significant bit to the least significant bit,
permitted values have zero or more “0s,” one or more “1s,” or
one “0.” Thus 3FFFF, 003FE, and 00001 are permitted values,
but 3F0FF, 003FC, and 00000 are not.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address will be valid
tCM2 after the next rising edge of the port’s clock. If mask
readback occurs while the port is enabled (CE0 LOW and CE1
HIGH), the data lines (DQs) will be three-stated. Figure 1
shows a block diagram of the operation.
Counting by Two
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the
x18 devices as a 36-bit single port SRAM in which the counter
of one port counts even addresses and the counter of the other
port counts odd addresses. This even-odd address scheme
stores one half of the 36-bit data in even memory locations,
and the other half in odd memory locations.
Page 7 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
CNT/MSK
CNTEN
Decode
Logic
ADS
CNTRST
MRST
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
Address
RAM
Decode
Array
CLK
From
Address
Lines
Load/Increment
17
Mirror
Counter
1
To Readback
and Address
Decode
1
0
From
Mask
Register
0
17
Increment
Logic
Wrap
17
From
Mask
From
Counter
17
17
Bit 0
17
+1
Wrap
Detect
1
+2
Wrap
0
1
0
17
To
Counter
Figure 1. Counter, Mask, and Mirror Logic Block Diagram[1]
Document #: 38-06077 Rev. *C
Page 8 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Example:
Load
Counter-Mask
Register = 3F
CNTINT
H
0 0
0s
216 215
H
X X
Xs
216 215
Max
Address
Register
L
H
1
1
1
X X
X X
216 215
Unmasked Address
X 0 0
1
0
0
Xs
X 1 1
1
Mask
Register
bit-0
0
26 25 24 23 22 21 20
216 215
Max + 1
Address
Register
1
26 25 24 23 22 21 20
Masked Address
Load
Address
Counter = 8
0 1 1
1 1
Address
Counter
bit-0
1
26 25 24 23 22 21 20
Xs
X 0
0
1
0 0
0
26 25 24 23 22 21 20
Figure 2. Programmable Counter-Mask Register Operation[1, 21]
IEEE 1149.1 Serial Boundary Scan (JTAG)[22]
The FLEx18 family devices incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1-compliant TAPs. The TAP
operates using JEDEC-standard 3.3V I/O logic levels. It is
composed of three input connections and one output
connection required by the test logic defined by the standard.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the device is operating.
An MRST must be performed on the devices after power-up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the
scan chain will output the next bit in the chain twice. For
example, if the value expected from the chain is 1010101, the
device will output a 11010101. This extra bit will cause some
testers to report an erroneous failure for the devices in a scan
test. Therefore the tester should be configured to never enter
the PAUSE-DR state.
Boundary Scan Hierarchy for 9-Mbit Device
Internally, the CYD09S18V have two DIEs. Each DIE contains
all the circuitry required to support boundary scan testing. The
circuitry includes the TAP, TAP controller, instruction register,
and data registers. The circuity and operation of the DIE
boundary scan are described in detail below. The scan chain
of each DIEs are connected serially to form the scan chain of
the CYD09S18V as shown in Figure 3. TMS and TCK are
connected in parallel to each DIE to drive all TAP controllers
in unison. In many cases, each DIE will be supplied with the
same instruction. In other cases, it might be useful to supply
different instructions to each DIE. One example would be
testing the device ID of one DIE while bypassing the others.
Each pin of the FLEx18 9-Mb device is typically connected to
two DIEs. For connectivity testing with the EXTEST
instruction, it is desirable to check the internal connections
between DIEs as well as the external connections to the
package. This can be accomplished by merging the netlist of
the devices with the netlist of the user’s circuit board. To facilitate boundary scan testing of the devices, Cypress provides
the BSDL file for each DIE, the internal netlist of the device,
and a description of the device scan chain. The user can use
these materials to easily integrate the devices into the board’s
boundary scan environment. Further information can be found
in the Cypress application note Using JTAG Boundary Scan
For System In a Package (SIP) Dual-Port SRAMs.
Notes:
21. The “X” in this diagram represents the counter upper bits.
22. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
Document #: 38-06077 Rev. *C
Page 9 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
TDO
TDO
D2
TDI
TDO
D1
TDI
TDI
Figure 3. Scan Chain for 9-Mbit Device
Table 4. Identification Register Definitions
Instruction Field
Value
Description
Revision Number (31:28)
0h
Reserved for version number.
Cypress Device ID (27:12)
C090h
Defines Cypress part number for CYD04S18V and CYD09S18V DIE
C091h
Defines Cypress part number for CYD02S18V
C093h
Defines Cypress part number for CYD01S18V
Cypress JEDEC ID (11:1)
034h
Allows unique identification of the DP family device vendor.
ID Register Presence (0)
1
Indicates the presence of an ID register.
Table 5. Scan Register Sizes
Register Name
Bit Size
Instruction
4
Bypass
1
Identification
32
Boundary Scan
n[23]
Table 6. Instruction Identification Codes
Instruction
Code
Description
EXTEST
0000
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
BYPASS
1111
Places the BYR between TDI and TDO.
IDCODE
1011
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
HIGHZ
0111
Places BYR between TDI and TDO. Forces all device output drivers to a High-Z state.
CLAMP
0100
Controls boundary to 1/0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD
1000
Captures the input/output ring contents. Places BSR between TDI and TDO.
NBSRST
1100
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
RESERVED
All other codes
Other combinations are reserved. Do not use other than the above.
Note:
23. See details in the device BSDL file.
Document #: 38-06077 Rev. *C
Page 10 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Maximum Ratings[24]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2000V
(Above which the useful life may be impaired. For user guidelines, not tested.)
(JEDEC JESD22-A114-2000B)
Storage Temperature ................................. –65°C to +150°C
Latch-up Current..................................................... > 200 mA
Ambient Temperature with
Operating Range
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
Range
Ambient
Temperature
DC Voltage Applied to
Outputs in High-Z State...........................–0.5V to VDD +0.5V
Commercial
0°C to +70°C
Industrial
DC Input Voltage...............................–0.5V to VDD + 0.5V[25]
VCORE[12]
VDDIO/VTTL
3.3V±165 mV 1.8V±100 mV
–40°C to +85°C 3.3V±165 mV 1.8V±100 mV
Electrical Characteristics Over the Operating Range
-167
Parameter
Description
-133
-100
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
VOH
Output HIGH Voltage (VDD = Min., IOH= –4.0 mA) 2.4
VOL
Output LOW Voltage (VDD = Min., IOL= +4.0 mA)
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IOZ
Output Leakage Current
2.4
2.4
0.4
2.0
0.4
2.0
10
0.4
V
2.0
0.8
–10
V
V
0.8
–10
10
–10
0.8
V
10
µA
IIX1
Input Leakage Current Except TDI, TMS, MRST –10
10
–10
10
–10
10
µA
IIX2
Input Leakage Current TDI, TMS, MRST
0.1
–1.0
0.1
–1.0
0.1
mA
ICC
Operating Current for
(VDD = Max.,IOUT = 0 mA),
Outputs Disabled
–1.0
CYD01S18V
CYD02S18V
CYD04S18V
225
300
CYD09S18V
[26]
225
300
270
400
mA
200
310
mA
Standby Current (Both Ports TTL Level)
CEL and CER ≥ VIH, f = fMAX
90
115
90
115
mA
ISB2[26]
Standby Current (One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
160
210
160
210
mA
ISB3[26]
Standby Current (Both Ports CMOS Level)
CEL and CER ≥ VDD – 0.2V, f = 0
55
75
55
75
mA
ISB4[26]
Standby Current (One Port CMOS Level)
CEL | CER ≥ VIH, f = fMAX
160
210
160
210
mA
ISB5
Operating Current (VDDIO =
Max, Iout=0mA,f=0)
Outputs Disabled
ICORE[12]
Core Operating Current for (VDD = Max.,
IOUT = 0 mA), Outputs Disabled
ISB1
CYD09S18V
75
0
0
0
0
0
75
mA
0
mA
Capacitance[27]
Part Number
Parameter
Description
CYD01S18V
CYD02S18V
CYD04S18V
CIN
Input Capacitance
COUT
Output Capacitance
CYD09S18V
CIN
Input Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V
COUT
Output Capacitance
Notes:
24. The voltage on any input or I/O pin can not exceed the power pin during power-up.
25. Pulse width < 20 ns.
26. ISB1, ISB2, ISB3 and ISB4 are not applicable for CYD09S18V because it can not be powered down by using chip enable pins.
27. COUT also references CI/O
Document #: 38-06077 Rev. *C
Max.
Unit
13
pF
10
pF
22
pF
20
pF
Page 11 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
AC Test Load and Waveforms
3.3V
Z0 = 50Ω
R = 50Ω
R1 = 590Ω
OUTPUT
OUTPUT
C = 10 pF
C = 5 pF
VTH = 1.5V
(a) Normal Load (Load 1)
R2 = 435Ω
(b) Three-state Delay (Load 2)
3.0V
90%
ALL INPUT PULSES
90%
10%
10%
Vss
< 2 ns
< 2 ns
Switching Characteristics Over the Operating Range
-167
Parameter
Description
-133
-100
CYD01S18V
CYD02S18V
CYD04S18V
CYD01S18V
CYD02S18V
CYD04S18V
CYD09S18V
CYD09S18V
Min.
Min.
Min.
Min.
Max.
167
Max.
133
Max.
Unit
100
MHz
Maximum Operating Frequency
tCYC2
Clock Cycle Time
6.0
7.5
7.5
10
ns
tCH2
Clock HIGH Time
2.7
3.0
3.0
4.0
ns
tCL2
Clock LOW Time
2.7
tR[28]
Clock Rise Time
tF[28]
Clock Fall Time
tSA
Address Set-up Time
tHA
Address Hold Time
0.6
0.6
0.6
0.6
ns
tSB
Byte Select Set-up Time
2.3
2.5
2.5
3.0
ns
tHB
Byte Select Hold Time
0.6
0.6
0.6
0.6
ns
tSC
Chip Enable Set-up Time
2.3
2.5
NA
NA
ns
tHC
Chip Enable Hold Time
0.6
0.6
NA
NA
ns
tSW
R/W Set-up Time
2.3
2.5
2.5
3.0
ns
tHW
R/W Hold Time
0.6
0.6
0.6
0.6
ns
tSD
Input Data Set-up Time
2.3
2.5
2.5
3.0
ns
tHD
Input Data Hold Time
0.6
0.6
0.6
0.6
ns
tSAD
ADS Set-up Time
2.3
2.5
NA
NA
ns
tHAD
ADS Hold Time
0.6
0.6
NA
NA
ns
tSCN
CNTEN Set-up Time
2.3
2.5
NA
NA
ns
tHCN
CNTEN Hold Time
0.6
0.6
NA
NA
ns
tSRST
CNTRST Set-up Time
2.3
2.5
NA
NA
ns
tHRST
CNTRST Hold Time
0.6
0.6
NA
NA
ns
tSCM
CNT/MSK Set-up Time
2.3
2.5
NA
NA
ns
tHCM
CNT/MSK Hold Time
0.6
tOE
Output Enable to Data Valid
tOLZ[29, 30]
OE to Low Z
3.0
2.0
3.0
3.0
NA
4.4
ns
ns
5.0
0
ns
ns
NA
4.7
0
ns
3.0
2.0
2.5
0.6
0
4.0
2.0
2.0
2.5
4.0
0
3.0
2.0
2.0
2.3
133
Max.
fMAX2
ns
ns
Notes:
28. Except JTAG signals (tr and tf < 10 ns [max.]).
29. This parameter is guaranteed by design, but it is not production tested.
30. Test conditions used are Load 2.
Document #: 38-06077 Rev. *C
Page 12 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Characteristics Over the Operating Range (continued)
-167
Parameter
Description
-133
-100
CYD01S18V
CYD02S18V
CYD04S18V
CYD01S18V
CYD02S18V
CYD04S18V
CYD09S18V
CYD09S18V
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
0
4.0
0
4.4
0
4.7
0
5.0
ns
5.0
ns
tOHZ[29, 30]
OE to High Z
tCD2
Clock to Data Valid
4.0
4.4
tCA2
Clock to Counter Address Valid
4.0
4.4
NA
NA
ns
tCM2
Clock to Mask Register Readback
Valid
4.0
4.4
NA
NA
ns
tDC
Data Output Hold After Clock HIGH
tCKHZ[29,30]
tCKLZ[29, 30]
Clock HIGH to Output High Z
0
4.0
0
4.4
0
4.7
0
5.0
ns
Clock HIGH to Output Low Z
1.0
4.0
1.0
4.4
1.0
4.7
1.0
5.0
ns
tSINT
Clock to INT Set Time
0.5
6.7
0.5
7.5
0.5
7.5
0.5
10
ns
tRINT
Clock to INT Reset Time
0.5
6.7
0.5
7.5
0.5
7.5
0.5
10
ns
tSCINT
Clock to CNTINT Set Time
0.5
5.0
0.5
5.7
NA
NA
NA
NA
ns
tRCINT
Clock to CNTINT Reset time
0.5
5.0
0.5
5.7
NA
NA
NA
NA
ns
1.0
1.0
4.7
1.0
1.0
ns
Port to Port Delays
tCCS
Clock to Clock Skew
5.2
6.0
6.0
8.0
ns
cycles
Master Reset Timing
tRS
Master Reset Pulse Width
5.0
5.0
5.0
5.0
tRS
Master Reset Set-up Time
6.0
6.0
6.0
8.5
ns
tRSR
Master Reset Recovery Time
5.0
5.0
5.0
5.0
cycles
tRSF
Master Reset to Outputs Inactive
10.0
10.0
10.0
10.0
ns
tRSINT
Master Reset to Counter and Mailbox
Interrupt Flag Reset Time
10.0
10.0
NA
NA
ns
JTAG Timing and Switching Waveforms
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Parameter
Description
Min.
Max.
Unit
10
MHz
fJTAG
Maximum JTAG TAP Controller Frequency
tTCYC
TCK Clock Cycle Time
100
ns
tTH
TCK Clock HIGH Time
40
ns
tTL
TCK Clock LOW Time
40
ns
tTMSS
TMS Set-up to TCK Clock Rise
10
ns
tTMSH
TMS Hold After TCK Clock Rise
10
ns
tTDIS
TDI Set-up to TCK Clock Rise
10
ns
tTDIH
TDI Hold After TCK Clock Rise
10
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
Document #: 38-06077 Rev. *C
ns
30
0
ns
ns
Page 13 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
tTH
Test Clock
TCK
tTMSS
tTL
tTCYC
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Switching Waveforms
Master Reset
tRS
MRST
ALL
ADDRESS/
DATA
LINES
tRSF
tRSS
ALL
OTHER
INPUTS
tRSR
INACTIVE
ACTIVE
TMS
tRSINT
CNTINT
INT
TDO
Document #: 38-06077 Rev. *C
Page 14 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Read Cycle[13, 31, 32, 33, 34]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSB
tHB
tSW
tSA
tHW
tHA
tSC
tHC
BE0–BE1
R/W
ADDRESS
An
DATAOUT
An+1
1 Latency
An+2
tDC
tCD2
Qn
tCKLZ
An+3
Qn+1
tOHZ
Qn+2
tOLZ
OE
tOE
Notes:
31. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
32. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
33. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock.
34. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK.
Numbers are for reference only.
Document #: 38-06077 Rev. *C
Page 15 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Bank Select Read[35, 36]
tCYC2
tCH2
tCL2
CLK
tHA
tSA
ADDRESS(B1)
A0
A1
A3
A2
A4
A5
tHC
tSC
CE(B1)
tCD2
tCD2
tHC
tSC
tHA
tSA
A0
ADDRESS(B2)
tDC
A1
tDC
tCKLZ
A3
A2
tCKHZ
Q3
Q1
Q0
DATAOUT(B1)
tCD2
tCKHZ
A4
A5
tHC
tSC
CE(B2)
tSC
tCD2
tHC
DATAOUT(B2)
tCKHZ
tCD2
Q4
Q2
tCKLZ
Read-to-Write-to-Read (OE =
tCH2
tCKLZ
LOW)[34, 37, 38, 39, 40]
tCYC2
tCL2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
ADDRESS
tSA
DATAIN
An+1
An+2
An+2
An+2
An+3
tSD tHD
tHA
tCD2
DATAOUT
tDC
Dn+2
tCKHZ
Qn
READ
NO OPERATION
WRITE
Notes:
35. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx18 device from this data sheet. ADDRESS(B1)
= ADDRESS(B2).
36. ADS = CNTEN= BE0 – BE1 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
37. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
38. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
39. CE0 = OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
40. CE0 = BE0 – BE1 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Document #: 38-06077 Rev. *C
Page 16 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Read-to-Write-to-Read (OE Controlled)[34, 37, 39, 40]
tCH2
tCYC2
tCL2
CLK
CE
tSC
tHC
tSW tHW
R/W
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
tSA
tHA
tSD tHD
Dn+2
DATAIN
Dn+3
tCD2
DATAOUT
tCD2
Qn
Qn+4
tOHZ
OE
READ
Read with Address Counter
tCH2
WRITE
READ
Advance[39]
tCYC2
tCL2
CLK
tSA
ADDRESS
tHA
An
tSAD
tHAD
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSCN
DATAOUT
tHCN
Qx–1
READ
EXTERNAL
ADDRESS
Document #: 38-06077 Rev. *C
tCD2
Qx
Qn
tDC
READ WITH COUNTER
Qn+1
COUNTER HOLD
Qn+2
Qn+3
READ WITH COUNTER
Page 17 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Write with Address Counter Advance [40]
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
tSAD
tHAD
tSCN
tHCN
An+1
An+2
An+3
An+4
ADS
CNTEN
Dn
DATAIN
tSD
tHD
WRITE EXTERNAL
ADDRESS
Document #: 38-06077 Rev. *C
Dn+1
Dn+1
WRITE WITH
COUNTER
Dn+2
WRITE COUNTER
HOLD
Dn+3
Dn+4
WRITE WITH COUNTER
Page 18 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Counter Reset[41, 42]
tCYC2
tCH2 tCL2
CLK
tSA
INTERNAL
ADDRESS
Ax
tSW
tHW
tSD
tHD
An
1
0
Ap
Am
An
ADDRESS
tHA
Ap
Am
R/W
ADS
CNTEN
tSRST tHRST
CNTRST
DATAIN
D0
tCD2
tCD2
[43]
DATAOUT
Q0
COUNTER
RESET
WRITE
ADDRESS 0
tCKLZ
READ
ADDRESS 0
READ
ADDRESS 1
Qn
Q1
READ
ADDRESS An
READ
ADDRESS Am
Notes:
41. CE0 = BE0 – BE1 = LOW; CE1 = MRST = CNT/MSK = HIGH.
42. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
43. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
Document #: 38-06077 Rev. *C
Page 19 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Readback State of Address Counter or Mask Register[44, 45, 46, 47]
tCYC2
tCH2 tCL2
CLK
tCA2 or tCM2
tSA tHA
EXTERNAL
ADDRESS
A0–A16
An*
An
INTERNAL
ADDRESS
An+1
An
An+2
An+3
An+4
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tCD2
DATAOUT
Qx-1
Qn
READBACK
COUNTER
INTERNAL
ADDRESS
INCREMENT
Qx-2
LOAD
EXTERNAL
ADDRESS
tCKHZ
tCKLZ
Qn+1
Qn+2
Qn+3
Notes:
44. CE0 = OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
45. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle.
46. Address in input mode. Host can drive address bus after tCKHZ.
47. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Document #: 38-06077 Rev. *C
Page 20 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Left_Port (L_Port) Write to Right_Port (R_Port) Read[48, 49, 50]
tCH2
tCYC2
tCL2
CLKL
tHA
tSA
L_PORT
ADDRESS
An
tSW
tHW
R/WL
tCKHZ
tSD
L_PORT
DATAIN
CLKR
tHD
tCKLZ
Dn
tCYC2
tCL2
tCCS
tCH2
tSA
R_PORT
ADDRESS
tHA
An
R/WR
tCD2
R_PORT
Qn
DATAOUT
tDC
Notes:
48. CE0 = OE = ADS = CNTEN = BE0 – BE1 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
49. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data will be Read out.
50. If tCCS < minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock. If
tCCS > minimum specified value, then R_Port will Read the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock.
Document #: 38-06077 Rev. *C
Page 21 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
Counter Interrupt and Retransmit[16, 43, 51, 52, 53, 54]
tCH2
tCYC2
tCL2
CLK
tSCM
tHCM
CNT/MSK
ADS
CNTEN
COUNTER
INTERNAL
ADDRESS
3FFFC
3FFFD
3FFFE
tSCINT
3FFFF
Last_Loaded
Last_Loaded +1
tRCINT
CNTINT
Notes:
51. CE0 = OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
52. CNTINT is always driven.
53. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
54. The mask register assumed to have the value of 3FFFFh.
Document #: 38-06077 Rev. *C
Page 22 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Switching Waveforms (continued)
MailBox Interrupt Timing[55, 56, 57, 58, 59]
tCH2
tCYC2
tCL2
CLKL
tSA
L_PORT
ADDRESS
tHA
7FFFF
An+1
An
An+2
An+3
tSINT
tRINT
INTR
tCH2
tCYC2
tCL2
CLKR
tSA
R_PORT
ADDRESS
tHA
Am+1
Am
7FFFF
Am+3
Am+4
Table 7. Read/Write and Enable Operation (Any Port)[1, 18, 60, 61, 62]
Inputs
OE
CE0
CE1
R/W
DQ0 – DQ17
X
H
X
X
High-Z
Deselected
X
X
L
X
High-Z
Deselected
X
L
H
L
DIN
Write
L
L
H
H
DOUT
Read
L
H
X
High-Z
Outputs Disabled
H
CLK
Outputs
X
Operation
Notes:
55. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
56. Address “7FFFF” is the mailbox location for R_Port of the 9Mb device.
57. L_Port is configured for Write operation, and R_Port is configured for Read operation.
58. At least one byte enable (BE0 – BE1) is required to be active during interrupt operations.
59. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
60. OE is an asynchronous input signal.
61. When CE changes state, deselection and Read happen after one cycle of latency.
62. CE0 = OE = LOW; CE1 = R/W = HIGH.
Document #: 38-06077 Rev. *C
Page 23 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Ordering Information
512K × 18 (9Mb) 3.3V Synchronous CYD09S18V Dual-Port SRAM
Speed
(MHz)
Ordering Code
Package
Name
Package Type
Operating
Range
133
CYD09S18V-133BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Commercial
100
CYD09S18V-100BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Commercial
CYD09S18V-100BBI
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Industrial
256K × 18 (4Mb) 3.3V Synchronous CYD04S36V Dual-Port SRAM
Speed
(MHz)
Ordering Code
Package
Name
167
CYD04S18V-167BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Commercial
133
CYD04S18V-133BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Commercial
CYD04S18V-133BBI
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Industrial
Package Type
Operating
Range
128K × 18 (2Mb) 3.3V Synchronous CYD02S18V Dual-Port SRAM
Speed
(MHz)
Ordering Code
Package
Name
167
CYD02S18V-167BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Commercial
133
CYD02S18V-133BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Commercial
CYD02S18V-133BBI
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Industrial
Package Type
Operating
Range
64K × 18 (1Mb) 3.3V Synchronous CYD01S18V Dual-Port SRAM
Speed
(MHz)
Ordering Code
Package
Name
Package Type
Operating
Range
167
CYD01S18V-167BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Commercial
133
CYD01S18V-133BBC
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Commercial
CYD01S18V-133BBI
BB256
256-ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (BGA) Industrial
Document #: 38-06077 Rev. *C
Page 24 of 26
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Package Diagram
256-Ball FBGA (17 x 17 mm) BB256
TOP VIEW
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
Ø0.45±0.05(256X)-CPLD DEVICES (37K & 39K)
PIN 1 CORNER
+0.10
-0.05
Ø0.50 (256X)-ALL OTHER DEVICES
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
A
B
B
C
D
1.00
C
D
E
E
F
F
G
H
J
K
H
15.00
17.00±0.10
G
J
K
L
M
7.50
L
M
N
N
P
P
R
R
T
T
1.00
7.50
0.15 C
0.70±0.05
0.25 C
B
15.00
A
17.00±0.10
A
0.20(4X)
SEATING PLANE
+0.10
-0.05
C
A1 0.36
0.56
REFERENCE JEDEC MO-192
0.35
A1
A 1.40 MAX. 1.70 MAX.
51-85108-*F
FLEx18 and FLEx18-E are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in
this document may be the trademarks of their respective holders.
Document #: 38-06077 Rev. *C
Page 25 of 26
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CYD01S18V/CYD02S18V
CYD04S18V/CYD09S18V
Document History Page
Document Title: CYD01S18V/CYD02S18V/CYD04S18V/CYD09S18V FLEx18™ 3.3V 64K/128K/256K/512K x 18
Synchronous Dual-Port RAM
Document Number: 38-06077
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
259671
See ECN
WWZ
New data sheet
*A
289711
See ECN
YDT
Change Pinout D10 from NC to VSS
Changed tRSCNTINT to tRSINT
Added tRSINT to the master reset timing diagram
Added ISB5 and changed IIX2
*B
327354
See ECN
AEQ
Change Pinout C10 from REVR[2,4] to NC[2,5]
Change Pinout G5 from VDDIOL to REVL[2,3]
*C
365320
See ECN
YDT
Added note for VCORE
Removed preliminary status
Document #: 38-06077 Rev. *C
Page 26 of 26
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