FullFlex
FullFlex™ Synchronous SDR Dual Port SRAM
Features
Functional Description
■
True dual port memory enables simultaneous access to the
shared array from each port
■
Synchronous pipelined operation with Single Data Rate (SDR)
operation on each port
❐ SDR interface at 200 MHz
❐ Up to 28.8 Gb/s bandwidth (200 MHz x 72 bit x 2 ports)
■
Selectable pipelined or flow-through mode
The FullFlex™ dual port SRAM families consist of 2 Mbit, 4 Mbit,
9 Mbit, 18 Mbit, and 36 Mbit synchronous, true dual port static
RAMs that are high speed, low power 1.8V or 1.5V CMOS. Two
ports are provided, enabling simultaneous access to the array.
Simultaneous access to a location triggers deterministic access
control. For FullFlex72 these ports operate independently with
72-bit bus widths and each port is independently configured for
two pipelined stages. Each port is also configured to operate in
pipelined or flow through mode.
■
1.5V or 1.8V core power supply
■
Commercial and Industrial temperature
■
IEEE 1149.1 JTAG boundary scan
■
Available in 484-Ball PBGA (x72) and 256-Ball FBGA (x36 and
x18) packages
■
FullFlex72 family
❐ 36 Mbit: 512K x 72 (CYD36S72V18)
❐ 18 Mbit: 256K x 72 (CYD18S72V18)
❐ 9 Mbit: 128K x 72 (CYD09S72V18)
❐ 4 Mbit: 64K x 72 (CYD04S72V18)
■
The advanced features include the following:
FullFlex36 family
❐ 36 Mbit: 1M x 36 (CYD36S36V18)
❐ 18 Mbit: 512K x 36 (CYD18S36V18)
❐ 9 Mbit: 256K x 36 (CYD09S36V18)
❐ 4 Mbit: 128K x 36 (CYD04S36V18)
❐ 2 Mbit: 64K x 36 (CYD02S36V18)
■
Variable Impedance Matching (VIM) to improve data transmission by matching the output driver impedance to the line
impedance
■
Echo clocks to improve data transfer
Each port contains an optional burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally.
FullFlex18 family
❐ 36 Mbit: 2M x 18 (CYD36S18V18)
❐ 18 Mbit: 1M x 18 (CYD18S18V18)
❐ 9 Mbit: 512K x 18 (CYD09S18V18)
❐ 4 Mbit: 256K x 18 (CYD04S18V18)
■
Built in deterministic access control to manage address collisions
❐ Deterministic flag output upon collision detection
❐ Collision detection on back-to-back clock cycles
❐ First Busy Address readback
Advanced features for improved high speed data transfer and
flexibility
❐ Variable Impedance Matching (VIM)
❐ Echo clocks
❐ Selectable LVTTL (3.3V), Extended HSTL (1.4V–1.9V), 1.8V
LVCMOS, or 2.5V LVCMOS IO on each port
❐ Burst counters for sequential memory access
❐ Mailbox with interrupt flags for message passing
❐ Dual Chip Enables for easy depth expansion
Cypress Semiconductor Corporation
Document Number: 38-06082 Rev. *H
Built in deterministic access control to manage address collisions during simultaneous access to the same memory location
To reduce the static power consumption, chip enables power
down the internal circuitry. The number of latency cycles before
a change in CE0 or CE1 enables or disables the databus
matches the number of cycles of read latency selected for the
device. For a valid write or read to occur, activate both chip
enable inputs on a port.
■
■
■
•
Additional device features include a mask register and a mirror
register to control counter increments and wrap around. The
counter interrupt (CNTINT) flags notify the host that the counter
reaches maximum count value on the next clock cycle. The host
reads the burst counter internal address, mask register address,
and busy address on the address lines. The host also loads the
counter with the address stored in the mirror register by using the
retransmit functionality. Mailbox interrupt flags are used for
message passing, and JTAG boundary scan and asynchronous
Master Reset (MRST) are also available. The Logic Block
Diagram on page 2 shows these features.
The FullFlex72 is offered in a 484-Ball plastic BGA package. The
FullFlex36 and FullFlex18 are available in 256-Ball fine pitch
BGA package.
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 15, 2008
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FullFlex
Logic Block Diagram
The Logic Block Diagram for FullFlex72, FullFlex36, and FullFlex18 family follows: [1, 2, 3]
FTSELL
FTSELR
CQENL
CONFIG Block
CONFIG Block
PORTSTD[1:0]L
CQENR
PORTSTD[1:0]R
DQ[71:0]L
BE [7:0]L
CE0L
CE1L
OEL
IO
Control
IO
Control
DQ [71:0]R
BE [7:0]R
CE0R
CE1R
OER
R/WR
R/WL
CQ1L
CQ1L
CQ0L
CQ0L
CQ1R
CQ1R
CQ0R
CQ0R
Dual Port Array
BUSYL
A [20:0]L
CNT/MSKL
ADSL
CNTENL
CNTRSTL
RETL
CNTINTL
CL
Collision Detection Logic
Address &
Counter Logic
BUSYR
Address &
Counter Logic
WRPL
A [20:0]R
CNT/MSKR
ADSR
CNTENR
CNTRSTR
RETR
CNTINTR
CR
WRPR
Mailboxes
INTL
INTR
ZQ0L
ZQ1L
READYL
LowSPDL
JTAG
RESET
LOGIC
TRST
TMS
TDI
TDO
TCK
ZQ0R
ZQ1R
MRST
READYR
LowSPDR
Notes
1. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and
CYD09S18V18 devices have 19 address bits. The CYD18S72V18, CYD09S36V18, and CYD04S18V18 devices have 18 address bits. The CYD09S72V18 and
CYD04S36V18 devices have 17 address bits. The CYD04S72V18 and CYD02S36V18 have 16 address bits.
2. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines.
3. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte enables.
Document Number: 38-06082 Rev. *H
Page 2 of 52
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FullFlex
Figure 1. FullFlex72 SDR 484-Ball BGA Pinout (Top View)
1
A
DNU
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
DQ61L DQ59L DQ57L DQ54L DQ51L DQ48L DQ45L DQ42L DQ39L DQ36L DQ36R DQ39R DQ42R DQ45R DQ48R DQ51R DQ54R DQ57R DQ59R DQ61R
22
DNU
B
DQ63L DQ62L DQ60L DQ58L DQ55L DQ52L DQ49L DQ46L DQ43L DQ40L DQ37L DQ37R DQ40R DQ43R DQ46R DQ49R DQ52R DQ55R DQ58R DQ60R DQ62R DQ63R
C
DQ65L DQ64L
VSS
VSS
D
DQ67L DQ66L
VSS
VSS
VSS
CQ1L
E
DQ69L DQ68L VDDIO
L
VSS
VSS
VDDIO VDDIO VDDIO VDDIO VDDIO VTTL
L
L
L
L
L
F
DQ71L DQ70L CE1L
CE0L VDDIO VDDIO VDDIO VDDIO VDDIO VCOR VCOR VCOR VCOR VDDIO VDDIO VDDIO VDDIO VDDIO CE0R
L
L
L
L
L
E
E
E
E
R
R
R
R
R
CE1R DQ70R DQ71R
RETR
A1R
A0R
DQ56L DQ53L DQ50L DQ47L DQ44L DQ41L DQ38L DQ38R DQ41R DQ44R DQ47R DQ50R DQ53R DQ56R
CQ1L VSS
LOWS PORTS ZQ0L BUSYL CNTIN PORTS
[4]
PDL
TD0L
TL
TD1L
VTTL
DNU
CQ1R
VSS
VSS
DQ64R DQ65R
VSS
DQ66R DQ67R
CQ1R
VSS
VSS
VTTL VDDIO VDDIO VDDIO VDDIO
R
R
R
R
DNU
VSS
G
A0L
A1L
RETL
BE4L VDDIO VDDIO VREFL
L
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H
A2L
A3L
WRPL
BE5L VDDIO VDDIO
L
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO VDDIO BE5R WRPR
R
R
A3R
A2R
J
A4L
A5L
READY BE6L VDDIO VDDIO
L
L
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO VDDIO BE6R READY
R
R
R
A5R
A4R
K
A6L
A7L
ZQ1L
BE7L
VTTL
VCOR
E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCOR VDDIO BE7R
E
R
ZQ1R
A7R
A6R
L
A8L
A9L
CL
OEL
VTTL
VCOR
E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCOR
E
VTTL
OER
CR
A9R
A8R
M
A10L
A11L
VSS
BE3L
VTTL
VCOR
E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCOR
E
VTTL
BE3R
VSS
A11R
A10R
N
A12L
A13L
ADSL
BE2L VDDIO VCOR
L
E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCOR
E
VTTL
BE2R
ADSR
A13R
A12R
P
A14L
A15L
CNT/M BE1L VDDIO VDDIO
SKL
L
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO VDDIO BE1R CNT/M A15R
R
R
SKR
A14R
R
A16L
A17L CNTEN BE0L VDDIO VDDIO
[7]
L
L
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO VDDIO BE0R CNTEN A17R
[7]
R
R
R
A16R
T
A18L
DNU CNTRS INTL
TL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
[8]
[6]
[4, 5]
VDDIO VDDIO VREFL
L
L
VREFR VDDIO VDDIO BE4R
R
R
VDDIO DQ68R DQ69R
R
VREFR VDDIO VDDIO
R
R
INTR CNTRS DNU
TR
U
DQ35L DQ34L R/WL CQENL VDDIO VDDIO VDDIO VDDIO VDDIO VCOR VCOR VCOR VCOR VDDIO VDDIO VDDIO VDDIO VDDIO CQEN
L
L
L
L
L
E
E
E
E
R
R
R
R
R
R
V
DQ33L DQ32L FTSEL VDDIO
L
L
DNU
VDDIO VDDIO VDDIO VDDIO VTTL
L
L
L
L
W
DQ31L DQ30L
VSS
MRST
VSS
CQ0L
Y
DQ29L DQ28L
VSS
VSS
AA
AB
CQ0L
DNU
VTTL
[4, 5]
[8]
A18R
[6]
R/WR DQ34R DQ35R
VTTL VDDIO VDDIO VDDIO VDDIO VDDIO TRST VDDIO FTSEL DQ32R DQ33R
R
R
R
R
R
R
R
PORTS CNTIN BUSYR ZQ0R PORTS LOWS
[4]
TR
TD1R
TD0R PDR
VSS
CQ0R
CQ0R
VSS
TDI
TDO
DQ30R DQ31R
TMS
TCK
DQ28R DQ29R
DQ20L DQ17L DQ14L DQ11L DQ8L
DQ5L
DQ2L
DQ2R
DQ5R
DQ8R DQ11R DQ14R DQ17R DQ20R
DQ27L DQ26L DQ24L DQ22L DQ19L DQ16L DQ13L DQ10L DQ7L
DQ4L
DQ1L
DQ1R
DQ4R
DQ7R DQ10R DQ13R DQ16R DQ19R DQ22R DQ24R DQ26R DQ27R
DQ3L
DQ0L
DQ0R
DQ3R
DQ6R
DNU
DQ25L DQ23L DQ21L DQ18L DQ15L DQ12L DQ9L
DQ6L
DQ9R DQ12R DQ15R DQ18R DQ21R DQ23R DQ25R
DNU
Notes
4. Leave this ball unconnected to disable VIM.
5. This ball is applicable only for 36 Mbit and DNU for 18 Mbit and lower densities.
6. Leave this Ball unconnected for CYD18S72V18, CYD09S72V18, and CYD04S72V18.
7. Leave this Ball unconnected for CYD09S72V18 and CYD04S72V18.
8. Leave this Ball unconnected for CYD04S72V18.
Document Number: 38-06082 Rev. *H
Page 3 of 52
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FullFlex
Figure 2. FullFlex36 SDR 484-Ball BGA Pinout (Top View)[9]
1
2
3
4
5
A
DNU
DNU
DNU
DNU
DNU
B
DNU
DNU
DNU
DNU
C
DNU
DNU
VSS
D
DNU
DNU
E
DNU
F
18
19
20
21
22
DQ33L DQ30L DQ27L DQ24L DQ21L DQ18L DQ18R DQ21R DQ24R DQ27R DQ30R DQ33R
DNU
DNU
DNU
DNU
DNU
DNU
DQ34L DQ31L DQ28L DQ25L DQ22L DQ19L DQ19R DQ22R DQ25R DQ28R DQ31R DQ34R
DNU
DNU
DNU
DNU
DNU
VSS
DNU
DQ35L DQ32L DQ29L DQ26L DQ23L DQ20L DQ20R DQ23R DQ26R DQ29R DQ32R DQ35R
DNU
VSS
VSS
DNU
DNU
VSS
VSS
VSS
CQ1L
CQ1R
VSS
VSS
VSS
DNU
DNU
DNU
VDDIO
L
VSS
VSS
VDDIO VDDIO VDDIO VDDIO VDDIO VTTL
L
R
R
R
R
VTTL VDDIO VDDIO VDDIO VDDIO
L
L
L
L
DNU
VSS
VDDIO
R
DNU
DNU
DNU
DNU
CE1L
CE0L VDDIO VDDIO VDDIO VDDIO VDDIO VCOR VCOR VCOR VCOR VDDIO VDDIO VDDIO VDDIO VDDIO CE0R
L
L
R
R
R
E
E
E
E
L
L
L
R
R
CE1R
DNU
DNU
G
A0L
A1L
RETL
BE2L VDDIO VDDIO VREFL
L
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RETR
A1R
A0R
H
A2L
A3L
WRPL
BE3L VDDIO VDDIO
L
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO VDDIO BE3R WRPR
R
R
A3R
A2R
J
A4L
A5L
READY DNU
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO VDDIO
R
R
DNU READY
R
A5R
A4R
K
A6L
A7L
ZQ1L
DNU
VTTL
VCOR
E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCOR VDDIO
E
R
DNU
ZQ1R
A7R
A6R
L
A8L
A9L
CL
OEL
VTTL
VCOR
E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCOR
E
VTTL
OER
CR
A9R
A8R
M
A10L
A11L
VSS
DNU
VTTL
VCOR
E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCOR
E
VTTL
DNU
VSS
A11R
A10R
N
A12L
A13L
ADSL
DNU
VDDIO VCOR
L
E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCOR
E
VTTL
DNU
ADSR
A13R
A12R
P
A14L
A15L
CNT/M BE1L VDDIO VDDIO
SKL
L
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO VDDIO BE1R CNT/M A15R
R
R
SKR
A14R
R
A16L
A17L CNTEN BE0L VDDIO VDDIO
L
L
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO VDDIO BE0R CNTEN A17R
R
R
R
A16R
T
A18L
A19L CNTRS INTL
TL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U
DNU
DNU
V
DNU
DNU
W
DNU
DNU
VSS
Y
DNU
DNU
AA
DNU
AB
DNU
[4]
6
VDDIO VDDIO
L
L
7
CQ1L
VDDIO VDDIO VREFL
L
L
8
VSS
9
10
11
12
13
14
LOWS PORTS ZQ0L BUSYL CNTIN PORTS
[4]
PDL
TD0L
TL
TD1L
VTTL
15
DNU
16
CQ1R
17
VREFR VDDIO VDDIO BE2R
R
R
VREFR VDDIO VDDIO
R
R
INTR CNTRS A19R
TR
R/WL CQENL VDDIO VDDIO VDDIO VDDIO VDDIO VCOR VCOR VCOR VCOR VDDIO VDDIO VDDIO VDDIO VDDIO CQEN
L
L
R
R
R
E
E
E
E
L
L
L
R
R
R
FTSEL VDDIO
L
L
DNU
DNU
VTTL VDDIO VDDIO VDDIO VDDIO VDDIO TRST VDDIO FTSEL
L
L
L
L
R
R
R
DNU
DNU
VDDIO VDDIO VDDIO VDDIO VTTL
R
R
R
R
MRST
VSS
CQ0L
VSS
VSS
DNU
DQ17L DQ14L DQ11L DQ8L
DQ5L
DQ2L
DQ2R
DNU
DNU
DNU
DNU
DQ16L DQ13L DQ10L DQ7L
DQ4L
DQ1L
DNU
DNU
DNU
DNU
DQ15L DQ12L DQ9L
DQ3L
DQ0L
DNU
PORTS CNTIN BUSYR ZQ0R PORTS LOWS
[4]
TR
TD1R
TD0R PDR
DQ6L
A18R
R/WR
DNU
CQ0L
VTTL
[4]
VSS
CQ0R
CQ0R
VSS
TDI
TDO
DNU
DNU
DQ5R
DQ8R DQ11R DQ14R DQ17R
DNU
TMS
TCK
DNU
DNU
DQ1R
DQ4R
DQ7R DQ10R DQ13R DQ16R
DNU
DNU
DNU
DNU
DNU
DQ0R
DQ3R
DQ6R
DNU
DNU
DNU
DNU
DNU
DQ9R DQ12R DQ15R
Note
9. Use this pinout only for device CYD36S36V18 of the FullFlex36 family.
Document Number: 38-06082 Rev. *H
Page 4 of 52
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FullFlex
Figure 3. FullFlex18 SDR 484-Ball BGA Pinout (Top View)[10]
1
2
3
4
5
6
7
8
15
16
17
18
19
20
21
22
A
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DQ15L DQ12L DQ9L
DQ9R DQ12R DQ15R
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
B
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DQ16L DQ13L DQ10L DQ10R DQ13R DQ16R
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
C
DNU
DNU
VSS
VSS
DNU
DNU
DNU
DNU
DQ17L DQ14L DQ11L DQ11R DQ14R DQ17R
DNU
DNU
DNU
DNU
VSS
VSS
DNU
DNU
D
DNU
DNU
VSS
VSS
VSS
CQ1L
CQ1L VSS
LOWS PORTS ZQ0L BUSYL CNTIN PORTS
[4]
PDL
TD0L
TL
TD1L
DNU
CQ1R
CQ1R
VSS
VSS
VSS
DNU
DNU
E
DNU
DNU
VDDIO
L
VSS
VSS
VDDIO VDDIO VDDIO VDDIO VDDIO VTTL
L
R
R
R
R
VTTL VDDIO VDDIO VDDIO VDDIO
L
L
L
L
DNU
VSS
VDDIO
R
DNU
DNU
F
DNU
DNU
CE1L
CE0L VDDIO VDDIO VDDIO VDDIO VDDIO VCOR VCOR VCOR VCOR VDDIO VDDIO VDDIO VDDIO VDDIO CE0R
L
L
R
R
R
E
E
E
E
L
L
L
R
R
CE1R
DNU
DNU
G
A0L
A1L
RETL
BE1L VDDIO VDDIO VREFL
L
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RETR
A1R
A0R
H
A2L
A3L
WRPL
DNU
VDDIO VDDIO
L
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO VDDIO
R
R
DNU
WRPR
A3R
A2R
J
A4L
A5L
READY DNU
L
VDDIO VDDIO
L
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO VDDIO
R
R
DNU READY
R
A5R
A4R
K
A6L
A7L
ZQ1L
DNU
VTTL
VCOR
E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCOR VDDIO
E
R
DNU
ZQ1R
A7R
A6R
L
A8L
A9L
CL
OEL
VTTL
VCOR
E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCOR
E
VTTL
OER
CR
A9R
A8R
M
A10L
A11L
VSS
DNU
VTTL
VCOR
E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCOR
E
VTTL
DNU
VSS
A11R
A10R
N
A12L
A13L
ADSL
DNU
VDDIO VCOR
L
E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCOR
E
VTTL
DNU
ADSR
A13R
A12R
P
A14L
A15L
CNT/M
SKL
DNU
VDDIO VDDIO
L
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO VDDIO
R
R
DNU
CNT/M A15R
SKR
A14R
R
A16L
A17L CNTEN BE0L VDDIO VDDIO
L
L
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO VDDIO BE0R CNTEN A17R
R
R
R
A16R
T
A18L
A19L CNTRS INTL
TL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U
A20L
DNU
V
DNU
DNU
W
DNU
DNU
VSS
Y
DNU
DNU
AA
DNU
AB
DNU
[4]
VDDIO VDDIO VREFL
L
L
9
10
11
12
VTTL
13
14
VREFR VDDIO VDDIO BE1R
R
R
VREFR VDDIO VDDIO
R
R
INTR CNTRS A19R
TR
R/WL CQENL VDDIO VDDIO VDDIO VDDIO VDDIO VCOR VCOR VCOR VCOR VDDIO VDDIO VDDIO VDDIO VDDIO CQEN
L
L
R
R
R
E
E
E
E
L
L
L
R
R
R
FTSEL VDDIO
L
L
VTTL
[4]
A18R
R/WR
DNU
A20R
VTTL VDDIO VDDIO VDDIO VDDIO VDDIO TRST VDDIO FTSEL
L
L
L
L
R
R
R
DNU
DNU
DNU
VDDIO VDDIO VDDIO VDDIO VTTL
R
R
R
R
MRST
VSS
CQ0L
CQ0L
DNU
VSS
VSS
DNU
DNU
DNU
DNU
DQ8L
DQ5L
DQ2L
DQ2R
DQ5R
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DQ7L
DQ4L
DQ1L
DQ1R
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DQ6L
DQ3L
DQ0L
DQ0R
PORTS CNTIN BUSYR ZQ0R PORTS LOWS
[4]
TR
TD1R
TD0R PDR
VSS
CQ0R
CQ0R
VSS
TDI
TDO
DNU
DNU
DQ8R
DNU
DNU
DNU
DNU
TMS
TCK
DNU
DNU
DQ4R
DQ7R
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DQ3R
DQ6R
DNU
DNU
DNU
DNU
DNU
DNU
DNU
DNU
Note
10. Use this pinout only for device CYD36S18V18 of the FullFlex18 family.
Document Number: 38-06082 Rev. *H
Page 5 of 52
[+] Feedback
FullFlex
Figure 4. FullFlex36 SDR 256-Ball BGA (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
DQ32L
DQ30L
DQ28L
DQ26L
DQ24L
DQ22L
DQ20L
DQ18L
DQ18R
DQ20R
DQ22R
DQ24R
DQ26R
DQ28R
DQ30R
DQ32R
B
DQ33L
DQ31L
DQ29L
DQ27L
DQ25L
DQ23L
DQ21L
DQ19L
DQ19R
DQ21R
DQ23R
DQ25R
DQ27R
DQ29R
DQ31R
DQ33R
C
DQ34L
DQ35L
RETL
INTL
CQ1L
CQ1L
DNU
TRST
MRST
ZQ0R[4]
CQ1R
CQ1R
INTR
RETR
DQ35R
DQ34R
D
A0L
A1L
WRPL
VREFL
FTSELL
LOWSPDL
VSS
VTTL
VTTL
VSS
LOWSPD
R
FTSELR
VREFR
WRPR
A1R
A0R
E
A2L
A3L
CE0L
CE1L
VDDIOL
VDDIOL
VDDIOL
VCORE
VCORE
VDDIOR
VDDIOR
VDDIOR
CE1R
CE0R
A3R
A2R
F
A4L
A5L
CNTINTL
BE3L
VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
BE3R
CNTINTR
A5R
A4R
G
A6L
A7L
BUSYL
BE2L
ZQ0L[4]
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
BE2R
BUSYR
A7R
A6R
H
A8L
A9L
CL
VTTL
VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VCORE
VTTL
CR
A9R
A8R
J
A10L
A11L
VSS
PORTSTD
1L
VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VCORE
PORTSTD
1R
VSS
A11R
A10R
K
A12L
A13L
OEL
BE1L
VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
BE1R
OER
A13R
A12R
L
A14L
A15L
ADSL
BE0L
VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
BE0R
ADSR
A15R
A14R
M
A16L[13]
A17L[12]
R/WL
CQENL
VDDIOL
VDDIOL
VDDIOL
VCORE
VCORE
VDDIOR
VDDIOR
VDDIOR
CQENR
R/WR
A17R[12]
A16R[13]
N
A18L[11]
DNU
CNT/MSK
L
VREFL
DNU
VTTL
VTTL
DNU
VREFR
CNT/MSK
R
DNU
A18R[11]
P
DQ16L
DQ17L
CNTENL
CNTRSTL
CQ0L
CQ0L
TCK
TMS
TDO
TDI
CQ0R
CQ0R
DQ17R
DQ16R
R
DQ15L
DQ13L
DQ11L
DQ9L
DQ7L
DQ5L
DQ3L
DQ1L
DQ1R
DQ3R
DQ5R
DQ7R
DQ9R
DQ11R
DQ13R
DQ15R
T
DQ14L
DQ12L
DQ10L
DQ8L
DQ6L
DQ4L
DQ2L
DQ0L
DQ0R
DQ2R
DQ4R
DQ6R
DQ8R
DQ10R
DQ12R
DQ14R
PORTSTD READYL
0L
READYR PORTSTD
0R
CNTRSTR CNTENR
Notes
11. Leave this ball unconnected for CYD09S36V18, CYD04S36V18, and CYD02S36V18.
12. Leave this ball unconnected for CYD04S36V18 and CYD02S36V18.
13. Leave this ball unconnected for CYD02S36V18.
Document Number: 38-06082 Rev. *H
Page 6 of 52
[+] Feedback
FullFlex
Figure 5. FullFlex18 SDR 256-Ball BGA (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
DNU
DNU
DNU
DQ17L
DQ16L
DQ13L
DQ12L
DQ9L
DQ9R
DQ12R
DQ13R
DQ16R
DQ17R
DNU
DNU
DNU
B
DNU
DNU
DNU
DNU
DQ15L
DQ14L
DQ11L
DQ10L
DQ10R
DQ11R
DQ14R
DQ15R
DNU
DNU
DNU
DNU
C
DNU
DNU
RETL
INTL
CQ1L
CQ1L
DNU
TRST
MRST
ZQ0R[4]
CQ1R
CQ1R
INTR
RETR
DNU
DNU
D
A0L
A1L
WRPL
VREFL
FTSELL
LOWSPDL
VSS
VTTL
VTTL
VSS
LOWSPD
R
FTSELR
VREFR
WRPR
A1R
A0R
E
A2L
A3L
CE0L
CE1L
VDDIOL
VDDIOL
VDDIOL
VCORE
VCORE
VDDIOR
VDDIOR
VDDIOR
CE1R
CE0R
A3R
A2R
F
A4L
A5L
CNTINTL
DNU
VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
DNU
CNTINTR
A5R
A4R
G
A6L
A7L
BUSYL
DNU
ZQ0L[4]
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
DNU
BUSYR
A7R
A6R
H
A8L
A9L
CL
VTTL
VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VCORE
VTTL
CR
A9R
A8R
J
A10L
A11L
VSS
PORTSTD
1L
VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VCORE
PORTSTD
1R
VSS
A11R
A10R
K
A12L
A13L
OEL
BE1L
VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
BE1R
OER
A13R
A12R
L
A14L
A15L
ADSL
BE0L
VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
BE0R
ADSR
A15R
A14R
M
A16L
A17L
R/WL
CQENL
VDDIOL
VDDIOL
VDDIOL
VCORE
VCORE
VDDIOR
VDDIOR
VDDIOR
CQENR
R/WR
A17R
A16R
N
A18L[15]
A19L[14]
CNT/MSK
L
VREFL
DNU
VTTL
VTTL
DNU
VREFR
CNT/MSK
R
A19R[14]
A18R[15]
P
DNU
DNU
CNTENL
CNTRSTL
CQ0L
CQ0L
TCK
TMS
TDO
TDI
CQ0R
CQ0R
DNU
DNU
R
DNU
DNU
DNU
DNU
DQ6L
DQ5L
DQ2L
DQ1L
DQ1R
DQ2R
DQ5R
DQ6R
DNU
DNU
DNU
DNU
T
DNU
DNU
DNU
DQ8L
DQ7L
DQ4L
DQ3L
DQ0L
DQ0R
DQ3R
DQ4R
DQ7R
DQ8R
DNU
DNU
DNU
PORTSTD READYL
0L
READYR PORTSTD
0R
CNTRSTR CNTENR
Notes
14. Leave this ball unconnected for CYD09S18V18 and CYD04S18V18.
15. Leave this ball unconnected for CYD04S18V18.
Document Number: 38-06082 Rev. *H
Page 7 of 52
[+] Feedback
FullFlex
Selection Guide
–200
–167
Unit
fMAX[17]
Parameter
200
167
MHz
Maximum Access Time (Clock to Data)
3.3
4.0
ns
[16]
Typical Operating Current ICC
800
[16]
Typical Standby Current for ISB3 (Both Ports CMOS Level)
210
[16]
mA
[16]
mA
700
210
Pin Definitions
Left Port
Right Port
Description
[1]
A[20:0]L
A[20:0]R
Address Inputs.
DQ[71:0]L
DQ[71:0]R
Data Bus Input and Output.[2]
BE[7:0]L
BE[7:0]R
Byte Select Inputs.[3] Asserting these signals enables read and write operations to the corresponding
bytes of the memory array.
BUSYL
BUSYR
Port Busy Output. When there is an address match and both chip enables are active for both ports,
an external BUSY signal is asserted on the fifth clock cycles from when the collision occurs.
CL
CR
Clock Signal. Maximum clock input rate is fMAX.
CE0L
CE0R
Active LOW Chip Enable Input.
CE1L
CE1R
Active HIGH Chip Enable Input.
CQENL
CQENR
Echo Clock Enable Input. Assert HIGH to enable echo clocking on respective port.
CQ0L
CQ0R
Echo Clock Signal Output for DQ[35:0] for FullFlex72 Devices. Echo Clock Signal Output for
DQ[17:0] for FullFlex36 devices. Echo Clock Signal Output for DQ[8:0] for FullFlex18 devices.
CQ0L
CQ0R
Inverted Echo Clock Signal Output for DQ[35:0] for FullFlex72 Devices. Inverted Echo Clock
Signal Output for DQ[17:0] for FullFlex36 devices. Inverted Echo Clock Signal Output for DQ[8:0] for
FullFlex18 devices.
CQ1L
CQ1R
Echo Clock Signal Output for DQ[71:36] for FullFlex72 Devices. Echo Clock Signal Output for
DQ[35:18] for FullFlex36 devices. Echo Clock Signal Output for DQ[17:9] for FullFlex18 devices.
CQ1L
CQ1R
Inverted Echo Clock Signal Output for DQ[71:36] for FullFlex72 Devices. Inverted Echo Clock
Signal Output for DQ[35:18] for FullFlex36 devices. Inverted Echo Clock Signal Output for DQ[17:9]
forFullFlex18 devices.
ZQ[1:0]L
ZQ[1:0]R
VIM Output Impedance Matching Input.[18] To use, connect a calibrating resistor between ZQ and
ground. The resistor must be five times larger than the intended line impedance driven by the dual
port. Assert HIGH or leave DNU to disable VIM.
OEL
OER
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data pins
during read operations.
INTL
INTR
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper two
memory locations are used for message passing. INTL is asserted LOW when the right port writes to
the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when
it reads the contents of its mailbox.
LowSPDL
LowSPDR
Port Low Speed Select Input. Assert this pin LOW to disable the DLL. For operation at less than
100 MHz, assert this pin LOW.
Notes
16. For 18 Mbit x72 commercial configuration only, refer to Electrical Characteristics on page 18 for complete information.
17. SDR mode with two pipelined stages.
18. The pin ZQ[1] is applicable only for 36 Mbit devices. This pin is DNU for 18 Mbit and lower density devices.
Document Number: 38-06082 Rev. *H
Page 8 of 52
[+] Feedback
FullFlex
Pin Definitions (continued)
Left Port
Right Port
Description
PORTSTD[1:0] PORTSTD[1:0] Port Clock/Address/Control/Data/Echo Clock/I/O Standard Select Input. Assert these pins
[19]
[19]
LOW/LOW for LVTTL, LOW/HIGH for HSTL, HIGH/LOW for 2.5V LVCMOS, and HIGH/HIGH for 1.8V
R
LVCMOS, respectively. These pins are driven by VTTL referenced levels.
L
R/WL
R/WR
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to read from the dual port memory
array.
READYL
READYR
Port DLL Ready Output. This signal is asserted LOW when the DLL and Variable Impedance
Matching circuits complete calibration. This is a wired OR capable output.
CNT/MSKL
CNT/MSKR
Port Counter/Mask Select Input. Counter control input.
ADSL
ADSR
Port Counter Address Load Strobe Input. Counter control input.
CNTENL
CNTENR
Port Counter Enable Input. Counter control input.
CNTRSTL
CNTRSTR
Port Counter Reset Input. Counter control input.
CNTINTL
CNTINTR
Port Counter Interrupt Output. This pin is asserted LOW one cycle before the unmasked portion
of the counter is incremented to all “1s”.
WRPL
WRPR
Port Counter Wrap Input. When the burst counter reaches the maximum count, on the next counter
increment WRP is set LOW to load the unmasked counter bits to 0. It is set HIGH to load the counter
with the value stored in the mirror register.
RETL
RETR
Port Counter Retransmit Input. Assert this pin LOW to reload the initial address for repeated access
to the same segment of memory.
VREFL
VREFR
Port External HSTL IO Reference Input. This pin is left DNU when HSTL is not used.
VDDIOL
VDDIOR
Port Data IO Power Supply.
FTSELL
FTSELR
Port Flow through Mode Select Input. Assert this pin LOW to select Flow through mode. Assert
this pin HIGH to select Pipelined mode.
MRST
Master Reset Input. MRST is an asynchronous input signal and affects both ports. Asserting MRST
LOW performs all of the reset functions as described in the text. A MRST operation is required at
power up. This pin is driven by a VDDIOL referenced signal.
TMS
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State machine
transitions occur on the rising edge of TCK. Operation for LVTTL or 2.5V LVCMOS.
TDI
JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers. Operation for
LVTTL or 2.5V LVCMOS.
TRST
JTAG Reset Input. Operation for LVTTL or 2.5V LVCMOS.
TCK
JTAG Test Clock Input. Operation for LVTTL or 2.5V LVCMOS.
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally tri-stated
except when captured data is shifted out of the JTAG TAP. Operation for LVTTL or 2.5V LVCMOS.
VSS
Ground Inputs.
VCORE
Device Core Power Supply.
VTTL
LVTTL Power Supply.
Note
19. PORTSTD[1:0]L and PORTSTD[1:0]R have internal pull down resistors.
Document Number: 38-06082 Rev. *H
Page 9 of 52
[+] Feedback
FullFlex
Selectable IO Standard
The FullFlex device families offer the option to choose one of the
four port standards for the device. Each port independently
selects standards from single ended HSTL class I, single ended
LVTTL, 2.5V LVCMOS, or 1.8V LVCMOS. The selection of the
standard is determined by the PORTSTD pins for each port.
These pins must be connected to an LVTTL power suppy. This
determines the input clock, address, control, data, and Echo
clock standard for each port as shown in Table 1.
Table 1. Port Standard Selection
PORTSTD1
PORTSTD0
I/O Standard
VSS
VSS
LVTTL
VSS
VTTL
HSTL
VTTL
VSS
2.5V LVCMOS
VTTL
VTTL
1.8V LVCMOS
Clocking
Separate clocks synchronize the operations on each port. Each
port has one clock input C. In this mode, all the transactions on
the address, control, and data are on the C rising edge. All transactions on the address, control, data input, output, and byte
enables occur on the C rising edge.
Echo Clocking
As the speed of data increases, on-board delays caused by
parasitics make it extremely difficult to provide accurate clock
trees. To counter this problem, the FullFlex families incorporate
Echo Clocks. Echo Clocks are enabled on a per port basis. The
dual port receives input clocks that are used to clock in the
address and control signals for a read operation. The dual port
retransmits the input clocks relative to the data output. The
buffered clocks are provided on the CQ1/CQ1 and CQ0/CQ0
outputs. Each port has a pair of Echo clocks. Each clock is
associated with half the data bits. The output clock matches the
corresponding ports IO configuration.
To enable echo clock outputs, tie CQEN HIGH. To disable echo
clock outputs, tie CQEN LOW.
Figure 6. SDR Echo Clock Delay
Input Clock
Data Out
Echo Clock
Table 2. Data Pin Assignment
BE Pin Name
Data Pin Name
BE[7]
DQ[71:63]
BE[6]
DQ[62:54]
BE[5]
DQ[53:45]
BE[4]
DQ[44:36]
BE[3]
DQ[35:27]
BE[2]
DQ[26:18]
BE[1]
DQ[17:9]
BE[0]
DQ[8:0]
Selectable Pipelined or Flow through Mode
To meet data rate and throughput requirements, the FullFlex
families offer selectable pipelined or flow through mode. Echo
clocks are not supported in flow through mode and the DLL must
be disabled.
Flow through mode is selected by the FTSEL pin. Strapping this
pin HIGH selects pipelined mode. Strapping this pin LOW selects
flow through mode.
DLL
The FullFlex familes of devices have an on-chip DLL. Enabling
the DLL reduces the clock to data valid (tCD) time enabling more
setup time for the receiving device. For operation below
100 MHz, the DLL must be disabled. This is selectable by
strapping LowSPD low.
Whenever the operating frequency is altered beyond the Clock
Input Cycle to Cycle Jitter specification, reset the DLL, followed
by 1024 clocks before any valid operation.
Document Number: 38-06082 Rev. *H
LowSPD pins are used to reset the DLLs for a single port
independent of all other circuitry. MRST is used to reset all DLLs
on the chip. For more information on DLL lock and reset time,
see Master Reset on page 17.
Echo Clock
Deterministic Access Control
Deterministic Access Control is provided for ease of design. The
circuitry detects when both ports access the same location and
provides an external BUSY flag to the port on which data is
corrupted. The collision detection logic saves the address in
conflict (Busy Address) to a readable register. In the case of
multiple collisions, the first busy address is written to the busy
address register.
If both ports access the same location at the same time and only
one port is doing a write, if tCCS is met, then the data written to
and read from the address is valid data. For example, if the right
port is reading and the left port is writing and the left ports clock
meets tCCS, then the data read from the address by the right port
is the old data. In the same case, if the right ports clock meets
tCCS, then the data read out of the address from the right port is
the new data. In the above case, if tCCS is violated by the either
ports clock with respect to the other port and the right port gets
the external BUSY flag, the data from the right port is corrupted.
Table 3 on page 11 shows the tCCS timing that must be met to
guarantee the data.
Table 4 on page 11 shows that, in the case of the left port writing
and the right port reading, when an external BUSY flag is
asserted on the right port, the data read out of the device is not
guaranteed.
The value in the busy address register is read back to the
address lines. The required input control signals for this function
are shown in Table 7 on page 13. The value in the busy address
register is read out to the address lines tCA after the same
amount of latency as a data read operation. After an initial
address match, the BUSY flag is asserted and the address under
contention is saved in the busy address register. All the following
Page 10 of 52
[+] Feedback
FullFlex
address matches enable to generate the BUSY flag. However,
none of the addresses are saved into the busy address register.
When a busy readback is performed, the address of the first
match that happens at least two clocks cycles after the busy
readback is saved into the busy address register.
Table 3. tCCS Timing for All Operating Modes
Port A—Early Arriving Port
Port B—Late Arriving Port
Mode
Active Edge
Mode
Active Edge
SDR
C
SDR
C
tCCS
C Rise to Opposite C Rise Setup Time for Non Corrupt Data
Unit
tCYC(min) – 0.5
ns
Table 4. Deterministic Access Control Logic
Left Port
Right Port
Left Clock
Right Clock
BUSYL
BUSYR
Read
Read
X
X
H
H
No Collision
Write
Read
>tCCS
0
H
H
Read OLD Data
0
>tCCS
H
H
Read NEW Data
tCCS
H
H
Read OLD Data
tCCS
0
H
L
Array Stores Left Port Data
Variable Impedance Matching
Each port contains a Variable Impedance Matching circuit to set
the impedance of the IO driver to match the impedance of the
on-board traces. The impedance is set for all outputs except
JTAG and is done by port. To take advantage of the VIM feature,
connect a calibrating resistor (RQ) that is five times the value of
the intended line impedance from the ZQ[1:0][18] pin to VSS. The
output impedance is then adjusted to account for drifts in supply
voltage and temperature every 1024 clock cycles. If a port’s clock
is suspended, the VIM circuit retains its last setting until the clock
is restarted. On restart, it then resumes periodic adjustment. In
the case of a significant change in device temperature or supply
voltage, recalibration happens every 1024 clock cycles. A Master
Reset initializes the VIM circuitry. Table 5 shows the VIM parameters and Table 6 describes the VIM operation modes.
To disable VIM, connect the ZQ pin to VDDIO of the relative
supply for the IOs before a Master Reset.
Document Number: 38-06082 Rev. *H
Table 5. Variable Impedance Matching Parameters
Min
Max
Unit
Tolerance
RQ Value
Parameter
100
275
Ω
± 2%
Output Impedance
20
55
Ω
± 15%
Reset Time
N/A
1024 Cycles
N/A
Update Time
N/A
1024 Cycles
N/A
Table 6. Variable Impedance Matching Operation
RQ Connection
Output Configuration
100Ω - 275Ω to VSS Output Driver Impedance = RQ/5 ± 15%
at Vout = VDDIO/2
ZQ to VDDIO
VIM Disabled. Rout < 20Ω at Vout =
VDDIO/2
Page 11 of 52
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FullFlex
Address Counter and Mask Register Operations [1]
Counter Load Operation [1]
Each port of the FullFlex family contains a programmable burst
address counter. The burst counter contains four registers: a
counter register, a mask register, a mirror register, and a busy
address register.
The address counter and mirror registers are loaded with the
address value presented on the address lines. This value ranges
from 0 to 1FFFFF.
The counter register contains the address used to access the
RAM array. It is changed only by the Master Reset (MRST),
Counter Reset, Counter Load, Retransmit, and Counter
Increment operations.
The mask register value affects the Counter Increment and
Counter Reset operations by preventing the corresponding bits
of the counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is only changed by
Mask Reset, Mask Load, and MRST. The Mask Load operation
loads the value of the address bus into the mask register. The
mask register defines the counting range of the counter register.
The mask register is divided into two or three consecutive
regions. Zero or more 0s define the masked region and one or
more 1s define the unmasked portion of the counter register. The
counter register may be divided up to three regions. The region
containing the least significant bits must be no more than two 0s.
Bits one and zero may be 10 respectively, masking the least
significant counter bit and causing the counter to increment by
two instead of one. If bits one and zero are 00, the two least
significant bits are masked and the counter increments by four
instead of one. For example, in the case of a 256Kx72 configuration, a mask register value of 003FC divides the mask register
into three regions. With bit 0 being the least significant bit and bit
17 being the most significant bit, the two least significant bits are
masked, the next eight bits are unmasked, and the remaining bits
are masked.
The mirror register reloads a counter register on retransmit
operations (see Retransmit on page 14) and wrap functions (see
Counter Interrupt on page 14 below). The last value loaded into
the counter register is stored in the mirror register. The mirror
register is only changed by master reset (MRST), counter reset,
and counter load.
Table 7 on page 13 summarizes the operations of these registers
and the required input control signals. All signals except MRST
are synchronized to the ports clock.
Document Number: 38-06082 Rev. *H
Mask Load Operation [1]
The mask register is loaded with the address value presented on
the address bus. This value ranges from 0 to 1FFFFF though not
all values permit correct increment operations. Permitted values
are in the form of 2n–1, 2n–2, or 2n–4. The counter register is only
segmented up to three regions. From the most significant bit to
the least significant bit, permitted values have zero or more 0s,
one or more 1s, and the least significant two bits are 11, 10, or
00. Thus 1FFFFE, 07FFFF, and 003FFC are permitted values
but 02FFFF, 003FFA, and 07FFE4 are not.
Counter Readback Operation
The internal value of the counter register is read out on the
address lines. The address is valid tCA after the selected number
of latency cycles configured by FTSEL. The data bus (DQ) is
tri-stated on the cycle that the address is presented on the
address lines. Figure 7 on page 15 shows a block diagram of this
logic.
Mask Readback Operation
The internal value of the mask register is read out on the address
lines. The address is valid tCA after the selected number of
latency cycles configured by FTSEL. The data bus (DQ) is
tri-stated on the cycle that the address is presented on the
address lines. Figure 7 on page 15 shows a block diagram of the
operation.
Counter Reset Operation
All unmasked bits of the counter and mirror registers are reset to
‘0’. All masked bits remain unchanged. A mask reset followed by
a counter reset resets the counter and mirror registers to 00000.
Mask Reset Operation
The mask register is reset to all 1s, that unmasks every bit of the
burst counter.
Page 12 of 52
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FullFlex
Table 7. Burst Counter and Mask Register Control Operations
The burst counter and mask register control operation for any port follows. [20, 21]
C
MRST
CNTRST CNT/MSK CNTEN ADS RET
Operation
Description
X
L
X
X
X
X
X
Master Reset
Reset address counter to all 0s, mask register to all
1s, and busy address to all 0s.
H
L
H
X
X
X
Counter Reset
Reset counter and mirror unmasked portion to all 0s.
H
L
L
X
X
X
Mask Reset
Reset mask register to all 1s.
H
H
H
L
L
X
Counter Load
Load burst counter and mirror with external address
value presented on address lines.
H
H
L
L
L
X
Mask Load
Load mask register with value presented on the
address lines.
H
H
H
L
H
L
Retransmit
Load counter with value in the mirror register.
H
H
H
L
H
H
Counter
Increment
Internally increment address counter value.
H
H
H
H
H
H
Counter Hold
Constantly hold the address value for multiple clock
cycles.
H
H
H
H
L
H
Counter
Readback
Read out counter internal value on address lines.
H
H
L
H
L
H
Mask Readback Read out mask register value on address lines.
H
H
L
H
H
L
Busy Address
Readback
H
H
L
L
H
X
Reserved
H
H
L
H
L
L
Reserved
H
H
L
H
H
H
Reserved
H
H
H
H
L
L
Reserved
H
H
H
H
H
L
Reserved
Read out first busy address after last busy address
readback.
Notes
20. “X” = Don’t Care, “H” = HIGH, “L” = LOW.
21. Counter operation and mask register operation is independent of chip enables.
Document Number: 38-06082 Rev. *H
Page 13 of 52
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FullFlex
Increment Operation[1]
Retransmit
After the address counter is initially loaded with an external
address, the counter can internally increment the address value
and address the entire memory array. Only the unmasked bits of
the counter register are incremented. For a counter bit to
change, the corresponding bit in the mask register must be 1. If
the two least significant bits of the mask register are 11, the burst
counter increments by one. If the two least significant bits are 10,
the burst counter increments by two, and if they are 00, the burst
counter increments by four. If all unmasked counter bits are
incremented to 1 and WRP is deasserted, the next increment l
wraps the counter back to the initially loaded value. The cycle
before the increment that results in all unmasked counter bits to
become 1s, a counter interrupt flag (CNTINT) is asserted if the
counter is incremented again. This increment causes the counter
to reach its maximum value and the next increment returns the
counter register to its initial value that was stored in the mirror
register if WRP is deasserted. If WRP is asserted, the unmasked
portion of the counter is filled with 0 instead. The example shown
in Figure 8 on page 16 shows an example of the
CYDD36S18V18 device with the mask register loaded with a
mask value of 00007F unmasking the seven least significant bits.
Setting the mask register to this value enables the counter to
access the entire memory space. The address counter is then
loaded with an initial value of 000005 assuming WRP is
deasserted. The masked bits, the seventh address through the
twenty-first address, do not increment in an increment operation.
The counter address starts at address 000005 and increments
its internal address value until it reaches the mask register value
of 00007F. The counter wraps around the memory block to
location 000005 at the next count. CNTINT is issued when the
counter reaches the maximum –1 count.
Retransmit enables repeated access to the same block of
memory without the need to reload the initial address. An internal
mirror register stores the address counter value last loaded.
While RET is asserted low, the counter continues to wrap back
to the value in the mirror register independent of the state of
WRP.
Hold Operation
The value of all three registers is constantly maintained
unchanged for an unlimited number of clock cycles. This
operation is useful in applications where wait states are needed
or when address is available a few cycles ahead of data in a
shared bus interface.
Document Number: 38-06082 Rev. *H
Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW one clock cycle
before an increment operation that results in the unmasked
portion of the counter register being all 1s. It is deasserted by
counter reset, counter load, mask reset, mask load, and MRST.
Counting by Two
When the two least significant bits of the mask register are 10,
the counter increments by two.
Counting by Four
When the two least significant bits of the mask register are 00,
the counter increments by four.
Mailbox Interrupts
Use the upper two memory locations for message passing and
permit communications between ports. Table 8 on page 16
shows the interrupt operation for both ports. The highest memory
location is the mailbox for the right port and the maximum
address – 1 is the mailbox for the left port.
When one port writes to the other port’s mailbox, the INT flag of
the port that the mailbox belongs to is asserted LOW. The INT
flag remains asserted until the mailbox location is read by the
other port. When a port reads its mailbox, the INT flag is
deasserted high after one cycle of latency with respect to the
input clock of the port to which the mailbox belongs and is
independent of OE.
As shown in Table 8 on page 16, to set the INTR flag, a write
operation by the left port to address 1FFFFF asserts INTR LOW.
A valid read of the 1FFFFF location by the right port resets INTR
HIGH after one cycle of latency with respect to the right port’s
clock. You must activate at least one byte enable to set or reset
the mailbox interrupt.
Page 14 of 52
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FullFlex
Figure 7. Counter, Mask, and Mirror Logic Block Diagram
Figure 7 shows the counter, mask, and mirror logic block diagram. [1]
CNT/MSK
CNTEN
Decode
Logic
A
CNTRST
RET
MRST
A
Mask
Register
Counter/
Address
Register
Address
Decode
RAM
Array
C
From
Address
Lines
Load/Increment
20
Counter
Mirror
To Readback
and Address
Decode
1
1
0
From
Mask
Register
From
Mask
From
Counter
0
20
Increment
Logic
Wrap
20
20
20
Bit 0
and 1
20
+1
Wrap
Detect
1
+2
Wrap
0
1
+4
20
To
Counter
0
Document Number: 38-06082 Rev. *H
Page 15 of 52
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FullFlex
Figure 8. Programmable Counter-Mask Register Operation with WRP deasserted
Figure 8 shows the programmable counter-mask operation with WRP deasserted. [1, 25]
CNTINT
Example:
Load
Counter-Mask
H
Register = 00007F
0 0
0s
220 219
0
1 1 1
H
X X
Xs
220 219
Max
Address
Value
L
H
1
1
Unmasked Address
X
0
0 0
0
1
0
X X
Xs
X
1
1 1
1
Mask
Register
LSB
1
6
5
4
3 2
1
0
27 2 2 2 2 2 2 2
220 219
Max + 1
Address
Value
1
6
5
4
3 2
1
0
27 2 2 2 2 2 2 2
Masked Address
Load
Address
Counter = 000005
1
1 1
Address
Counter
LSB
1
6
5
4
3 2
1
0
27 2 2 2 2 2 2 2
X X
Xs
220 219
X
0 0
0
0
1 0
1
6
5
4
3 2
1
0
27 2 2 2 2 2 2 2
Table 8. Interrupt Operation Example
Table 8 shows the interrupt operation example. [1, 20, 22, 23, 24]
Function
Left Port
R/WL
Right Port
CEL
A0L–20L
INTL
R/WR
CER
A0R–20R
INTR
Set Right INTR Flag
L
L
Max Address
X
X
X
X
L
Reset Right INTR Flag
X
X
X
X
H
L
Max Address
H
Set Left INTL Flag
X
X
X
L
L
L
Max Address–1
X
Reset Left INTL Flag
H
L
Max Address–1
H
X
X
X
X
Notes
22. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single read operation, CE only needs to be asserted once at the rising edge of the C and is
deasserted after that. Data is out after the following C edge and is tri-stated after the next C edge.
23. OE is “Don’t Care” for mailbox operation.
24. At least one of BE0, BE1, BE2, BE3, BE4, BE5, BE6, or BE7 must be LOW.
25. The “X” in this diagram represents the counter’s upper bits.
Document Number: 38-06082 Rev. *H
Page 16 of 52
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FullFlex
Master Reset
The FullFlex family of Dual Ports undergoes a complete reset
when MRST is asserted. MRST must be driven by VDDIOL referenced levels. The MRST is asserted asynchronously to the
clocks and must remain asserted for at least tRS. When asserted
MRST deasserts READY, initializes the internal burst counters,
internal mirror registers, and internal busy addresses to zero. It
also initializes the internal mask register to all 1s. All mailbox
interrupts (INT), busy address outputs (BUSY), and burst
counter interrupts (CNTINT) are deasserted upon master reset.
Additionally, do not release MRST until all power supplies
including VREF are fully ramped and all port clocks and mode
select inputs (LOWSPD, ZQ, CQEN, FTSEL, and PORTSTD)
are valid and stable. This begins calibration of the DLL and VIM
circuits. READY is asserted within 1024 clock cycles. READY is
a wired OR capable output with a strong pull up and weak pull
down. Up to four outputs may be connected together. For faster
pull down of the signal, connect a 250 Ohm resistor to VSS. If
the DLL and VIM circuits are disabled for a port, the port is operational within five clock cycles. However, the READY is asserted
within 160 clock cycles.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The FullFlex families incorporate an IEEE 1149.1 serial
boundary scan test access port (TAP). The TAP operates using
JEDEC-standard 3.3V or 2.5V IO logic levels depending on the
VTTL power supply. It is composed of four input connections and
one output connection required by the test logic defined by the
standard.
Table 9. JTAG IDCODE Register Definitions
Part Number
Configuration
Value
CYD36S72V18
512Kx72
0C026069h (x2)
CYD36S36V18
1024Kx36
0C023069h
CYD36S18V18
2048Kx36
0C024069h
CYD18S72V18
256Kx72
0C025069h
CYD18S36V18
512Kx36
0C026069h
CYD18S18V18
1024Kx18
0C027069h
CYD09S72V18
128Kx72
0C028069h
CYD09S36V18
256Kx36
0C029069h
CYD09S18V18
512Kx18
0C02A069h
CYD04S72V18
64Kx72
0C02B069h
CYD04S36V18
128Kx36
0C02C069h
CYD04S18V18
256Kx18
0C02D069h
CYD02S36V18
64Kx36
0C030069h
Table 10.Scan Registers Sizes
Register Name
Instruction
Bit Size
4
Bypass
1
Identification
32
Boundary Scan
n[26]
Table 11.Instruction Identification Codes
Instruction
EXTEST
Code
0000
Description
Captures the input and output ring contents. Places the BSR between the TDI and TDO.
BYPASS
1111
Places the BYR between TDI and TDO.
IDCODE
1011
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
HIGHZ
0111
Places BYR between TDI and TDO. Forces all FullFlex72 and FullFlex36 output drivers to a
High-Z state.
CLAMP
0100
Controls boundary to 1 or 0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD
1000
Captures the input and output ring contents. Places BSR between TDI and TDO.
RESERVED
All other
codes
Other combinations are reserved. Do not use other than the mentioned combinations.
Note
26. Details of the boundary scan length is found in the BSDL file for the device.
Document Number: 38-06082 Rev. *H
Page 17 of 52
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FullFlex
Maximum Ratings
Operating Range
Range
Ambient
Temperature
VCORE
Storage Temperature ................................ –65°C to + 150°C
Commercial
0°C to +70°C
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
1.8V ± 100 mV
1.5V ± 80 mV
Industrial
–40°C to +85°C
1.8V ± 100 mV
1.5V ± 80 mV
Exceeding maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Supply Voltage to Ground Potential...............–0.5V to + 4.1V
DC Voltage Applied to
Outputs in High-Z State ...................... –0.5V to VDDIO + 0.5V
Power Supply Requirements
Min
Typ
Max
Output Current into Outputs (LOW)............................ 20 mA
LVTTL VDDIO
3.0V
3.3V
3.6V
Static Discharge Voltage........................................... > 2200V
2.5V LVCMOS VDDIO
2.3V
2.5V
2.7V
(JEDEC JESD8-6, JESD8-B)
HSTL VDDIO
1.4V
1.5V
1.9V
Latch-up Current..................................................... > 200 mA
1.8V LVCMOS VDDIO
1.7V
1.8V
1.9V
3.3V VTTL
3.0V
3.3V
3.6V
DC Input Voltage ................................ –0.5V to VDDIO + 0.5V
2.5V VTTL
2.3V
2.5V
2.7V
HSTL VREF
0.68V
0.75V
0.95V
Electrical Characteristics
Over the Operating Range
Parameter
VOH
Description
VIL
Min
Typ
Unit
Max
LVTTL
2.4[27]
V
(VDDIO = Min, IOH = –4 mA)
HSTL (DC)[28]
VDDIO – 0.4[27]
V
(VDDIO = Min, IOH = –4 mA)
HSTL
(AC)[28]
0.5[27]
V
(VDDIO = Min, IOH = –6 mA)
2.5V LVCMOS
1.8V LVCMOS
VDDIO –
1.7[27]
VDDIO –
V
0.45[27]
V
Output HIGH Voltage
(VDDIO = Min, IOL = 8 mA)
LVTTL
0.4[27]
V
(VDDIO = Min, IOL = 4 mA)
HSTL(DC)[28]
0.4[27]
V
(VDDIO = Min, IOL = 4 mA)
HSTL
(AC)[28]
0.5[27]
V
(VDDIO = Min, IOL = 6 mA)
2.5V LVCMOS
0.7[27]
V
1.8V LVCMOS
0.45[27]
V
(VDDIO = Min, IOL = 4 mA)
VIH
All Speed Bins
Output HIGH Voltage
(VDDIO = Min, IOH = –8 mA)
(VDDIO = Min, IOH = –4 mA)
VOL
Configuration
Input HIGH Voltage
Input LOW Voltage
LVTTL
2
VDDIO + 0.3
V
HSTL(DC)[28]
VREF + 0.1
VDDIO + 0.3
V
2.5V LVCMOS
1.7
1.8V LVCMOS
0.65 x VDDIO
LVTTL
–0.3
0.8
HSTL(DC)[28]
–0.3
V
V
V
VREF – 0.1
V
2.5V LVCMOS
0.7
V
1.8V LVCMOS
0.35 x VDDIO
V
Notes
27. These parameters are met with VIM disabled.
28. The DC specifications are measured under steady state conditions. The AC specifications are measured while switching at speed. AC VIH/VIL in HSTL mode are
measured with 1V/ns input edge rates
Document Number: 38-06082 Rev. *H
Page 18 of 52
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FullFlex
Electrical Characteristics
Over the Operating Range (continued)
Parameter
READY
VOH
Description
Configuration
All Speed Bins
Min
Typ
Unit
Max
Output HIGH Voltage
(VDDIO = Min, IOH = –24 mA)
LVTTL
2.7[27]
(VDDIO = Min, IOH = –12 mA)
HSTL(DC)[28]
VDDIO – 0.4[27]
V
(VDDIO = Min, IOH = –12 mA)
HSTL (AC)
[28]
[27]
V
(VDDIO = Min, IOH = –15 mA)
2.5V LVCMOS
2.0[27]
(VDDIO = Min, IOH = –12 mA)
1.8V LVCMOS
VDDIO – 0.45[27]
VDDIO – 0.5
V
V
V
LVTTL
0.4[27]
V
(VDDIO = Min, IOL = 0.12 mA)
HSTL(DC)[28]
0.4[27]
V
(VDDIO = Min, IOL = 0.12 mA)
HSTL
(AC)[28]
0.5[27]
V
(VDDIO = Min, IOL = 0.15 mA)
2.5V LVCMOS
0.7[27]
V
1.8V LVCMOS
0.45[27]
V
Output HIGH Voltage
READY VOL (VDDIO = Min, IO = 0.12 mA)
(VDDIO = Min, IOL = 0.08 mA)
IOZ
Output Leakage Current
–10
10
μA
IIX1
Input Leakage Current Except
TDI, TMS, MRST, PORTSTD
–10
10
μA
IIX2
Input Leakage Current TDI,
TMS, MRST
–300
10
μA
IIX3
Input Leakage Current
PORTSTD
–10
300
μA
Document Number: 38-06082 Rev. *H
Page 19 of 52
[+] Feedback
FullFlex
Electrical Characteristics
Over the Operating Range
Parameter
ICC
Description
Operating Current
(VCORE = Max,IOUT = 0 mA)
Outputs Disabled
Configuration
–167
Typ
Max
Com.
1440
1800
Ind.
N/A
N/A
1024Kx36
Com.
1180
1500
Ind.
N/A
2048Kx18
Com.
1130
Ind.
N/A
N/A
512Kx72
256Kx72
Typ
–133
Unit
Max
Typ
Max
1280
1620
1120
1430
mA
1330
1730
1170
1550
mA
1050
1350
930
1220
mA
N/A
1110
1470
980
1330
mA
1430
1000
1290
890
1160
mA
1060
1410
940
1280
mA
Com.
800
980
700
880
N/A
N/A
mA
Ind.
820
1030
730
930
N/A
N/A
mA
512Kx36
Com.
640
800
570
720
N/A
N/A
mA
Ind.
670
860
590
780
N/A
N/A
mA
1024Kx18
Com.
610
770
540
690
N/A
N/A
mA
Ind.
640
830
570
750
N/A
N/A
mA
128Kx72
Com.
640
790
560
700
N/A
N/A
mA
Ind.
660
830
580
740
N/A
N/A
mA
256Kx36
Com.
540
640
470
570
N/A
N/A
mA
Ind.
550
670
490
600
N/A
N/A
mA
512Kx18
Com.
550
660
480
580
N/A
N/A
mA
Ind.
570
690
500
610
N/A
N/A
mA
64Kx72
Com.
620
740
540
650
N/A
N/A
mA
Ind.
630
770
550
680
N/A
N/A
mA
128Kx36
Com.
510
590
450
520
N/A
N/A
mA
Ind.
520
600
460
530
N/A
N/A
mA
256Kx18
Com.
530
610
460
530
N/A
N/A
mA
Ind.
540
620
470
550
N/A
N/A
mA
64Kx36
Document Number: 38-06082 Rev. *H
–200
Com.
N/A
N/A
mA
Ind.
N/A
N/A
mA
Page 20 of 52
[+] Feedback
FullFlex
Electrical Characteristics
Over the Operating Range (continued)
Parameter
ISB1
Description
Standby Current
(Both Ports TTL Level)
CEL and CER ≥ VIH, f = fMAX
Configuration
–167
Typ
Max
Com.
1000
1250
Ind.
N/A
N/A
1024Kx36
Com.
910
1140
820
Ind.
N/A
N/A
2048Kx18
Com.
890
1110
Ind.
N/A
N/A
512Kx72
256Kx72
Typ
–133
Unit
Max
Typ
Max
920
1160
830
1060
mA
970
1260
880
1170
mA
1050
740
960
mA
880
1160
790
1080
mA
810
1030
730
940
mA
860
1140
780
1050
mA
Com.
500
630
460
580
N/A
N/A
mA
Ind.
530
680
490
630
N/A
N/A
mA
512Kx36
Com.
460
570
410
530
N/A
N/A
mA
Ind.
480
630
440
580
N/A
N/A
mA
1024Kx18
Com.
450
560
410
520
N/A
N/A
mA
Ind.
470
610
430
570
N/A
N/A
mA
128Kx72
Com.
400
490
360
450
N/A
N/A
mA
Ind.
420
540
380
490
N/A
N/A
mA
256Kx36
Com.
380
440
340
400
N/A
N/A
mA
Ind.
390
470
360
430
N/A
N/A
mA
512Kx18
Com.
390
460
350
410
N/A
N/A
mA
Ind.
410
480
370
440
N/A
N/A
mA
64Kx72
Com.
380
450
340
400
N/A
N/A
mA
Ind.
390
480
350
430
N/A
N/A
mA
128Kx36
Com.
360
400
320
360
N/A
N/A
mA
Ind.
360
410
330
370
N/A
N/A
mA
256Kx18
Com.
370
410
320
370
N/A
N/A
mA
Ind.
370
420
330
380
N/A
N/A
mA
64Kx36
Document Number: 38-06082 Rev. *H
–200
Com.
N/A
N/A
mA
Ind.
N/A
N/A
mA
Page 21 of 52
[+] Feedback
FullFlex
Electrical Characteristics
Over the Operating Range (continued)
Parameter
ISB2
Description
Standby Current
(One Port TTL or CMOS Level)
CEL | CER ≥ VIH, f = fMAX
Configuration
–167
Typ
Max
Com.
1300
Ind.
N/A
1024Kx36
Com.
1090
Ind.
2048Kx18
Com.
Ind.
N/A
512Kx72
256Kx72
–133
Unit
Typ
Max
Typ
Max
1570
1160
1410
1020
1260
mA
N/A
1210
1520
1070
1370
mA
1330
980
1210
870
1100
mA
N/A
N/A
1030
1330
920
1210
mA
1040
1270
930
1160
830
1050
mA
N/A
980
1270
880
1160
mA
Com.
650
790
580
710
N/A
N/A
mA
Ind.
680
840
610
760
N/A
N/A
mA
512Kx36
Com.
550
670
490
610
N/A
N/A
mA
Ind.
570
730
520
670
N/A
N/A
mA
1024Kx18
Com.
520
640
470
580
N/A
N/A
mA
Ind.
550
690
490
640
N/A
N/A
mA
128Kx72
Com.
520
630
460
560
N/A
N/A
mA
Ind.
550
670
480
610
N/A
N/A
mA
256Kx36
Com.
460
530
400
470
N/A
N/A
mA
Ind.
480
560
430
500
N/A
N/A
mA
512Kx18
Com.
460
530
410
480
N/A
N/A
mA
Ind.
480
560
430
510
N/A
N/A
mA
64Kx72
Com.
500
580
440
510
N/A
N/A
mA
Ind.
510
610
450
550
N/A
N/A
mA
128Kx36
Com.
440
480
380
420
N/A
N/A
mA
Ind.
450
500
390
440
N/A
N/A
mA
256Kx18
Com.
440
490
390
430
N/A
N/A
mA
Ind.
450
500
400
450
N/A
N/A
mA
64Kx36
Document Number: 38-06082 Rev. *H
–200
Com.
N/A
N/A
mA
Ind.
N/A
N/A
mA
Page 22 of 52
[+] Feedback
FullFlex
Electrical Characteristics
Over the Operating Range (continued)
Parameter
ISB3
Description
Standby Current
(Both Ports CMOS Level)
CEL and CER ≥ VCORE – 0.2V, f = 0
All Speed Bins
Configuration
Typ
Max
Unit
512Kx72
Com.
410
590
Ind.
460
700
mA
1024Kx36
Com.
410
590
mA
Ind.
460
700
mA
2048Kx18
mA
Com.
410
590
mA
Ind.
460
700
mA
256Kx72
Com.
210
300
mA
Ind.
230
350
mA
512Kx36
Com.
210
300
mA
Ind.
230
350
mA
1024Kx18
Com.
210
300
mA
Ind.
230
350
mA
128Kx72
Com.
150
200
mA
Ind.
170
220
mA
256Kx36
Com.
150
200
mA
Ind.
170
220
mA
512Kx18
Com.
150
200
mA
Ind.
170
220
mA
64Kx72
Com.
130
150
mA
Ind.
140
170
mA
128Kx36
Com.
130
150
mA
Ind.
140
170
mA
256Kx18
Com.
130
150
mA
Ind.
140
170
mA
Table 12.Capacitance
Signals
OE
Packages
CYD18S72V18
CYD09S72V18
CYD04S72V18
CYD18S36V18
CYD09S36V18
CYD04S36V18
CYD02S36V18
CYD18S18V18
CYD09S18V18
CYD04S18V18
CYD36S72V18
CYD36S36V18
CYD36S18V18
12 pF
12 pF
20 pF
20 pF
BE, DQ
10 pF
18 pF
16 pF
30 pF
All other signals
10 pF
10 pF
16 pF
16 pF
Document Number: 38-06082 Rev. *H
Page 23 of 52
[+] Feedback
FullFlex
AC Test Load and Waveforms
Figure 9. Output Test Load for LVTTL/CMOS
V
V
REF
V T H = 1 .5 V fo r L V T T L
V T H = 5 0 % V D D IO fo r 2 .5 V C M O S
V T H = 5 0 % V D D IO fo r 1 .8 V C M O S
= NC
REF
50 O hm
50 O hm
O u tp u t
T e s t P o in t
R=250 O hm
VTH
ZQ
READY
D e v ic e u n d e r
te s t
C = 10pF
R Q =250 O hm
Figure 10. Output Test Load for HSTL
V T H
V
V
R E F
= 5 0 %
V D D IO
= 0 .7 5 V
R E F
5 0 O h m
5 0 O h m
O u tp u t
R = 2 5 0 O h m
T e s t P o in t
R E A D Y
V T H
Z Q
D e v ic e u n d e r
te s t
C = 1 0 p F fo r S D R
R Q = 2 5 0 O h m
Figure 11. HSTL Input Waveform
Document Number: 38-06082 Rev. *H
Page 24 of 52
[+] Feedback
FullFlex
Switching Characteristics Over the Operating Range
Table 13.SDR Mode, Signals Affected by DLL
DLL ON (LOWSPD=1)[31]
DLL OFF
(LOWSPD=0)
Description
[31]
Parameter
–200
Min
tCD2[34]
C Rise to DQ Valid for Pipelined
Mode
tCCQ[34]
C Rise to CQ Rise
1.00
tCKHZ2[29, 34]
C Rise to DQ Output High Z in
Pipelined Mode
1.00
tCKLZ2[29, 34]
C Rise to DQ Output Low Z in
Pipelined Mode
1.00
Max
–167
Min
Max
3.30
Min
Max
4.00
[30, 33]
1.00
3.30
1.00
1.00
4.00
1.00
1.00
Max
[30, 33]
4.00[33]
[30, 33]
Min
4.50
[30, 33]
3.30[33]
[30, 33]
–133
1.00
4.50
1.00
[30, 33]
1.00
6.00
ns
6.00[33]
ns
6.00
ns
[30, 33]
4.50[33]
Unit
[30, 33]
1.00
ns
Table 14.SDR Mode
Parameter
Description
–200
Min
Max
Min
Max
100
200
100
167
100
133
MHz
55.6
MHz
10.00
ns
fMAX (FLOW
THROUGH)
Maximum Operating Frequency for Flow Through
Mode
tCYC
(PIPELINED)
C Clock Cycle Time for Pipelined Mode
5.00
tCYC (FLOW X
THROUGH)
C Clock Cycle Time for Flow Through Mode
13.00
tCKD
C Clock Duty Time
tSD
Data Input Setup Time HSTL
to C Rise
1.8V LVCMOS
77
[33]
tSAC
Address and Control
HSTL
Input Setup Time to C 1.8V LVCMOS
Rise
2.5V LVCMOS 3.3V
LVTTL
tHAC[32]
Address and Control Input Hold Time after C Rise
tOE
Output Enable to Data Valid
tOLZ[29]
OE to Low Z
10.00
66.7
6.00
[33]
10.00
15.00
[33]
45
Data Input Hold Time after C Rise
Unit
Max
Maximum Operating Frequency for Pipelined Mode
tHD[32]
–133
Min
fMAX
(PIPELINED)
2.5V LVCMOS 3.3V
LVTTL
–167
1.50
45
ns
[33]
55
1.70
[30, 33]
[33]
18.00
[33]
55
7.00
[30, 33]
45
55
1.80
ns
[30, 33]
1.95
%
[30, 33]
[30, 33]
[30, 33]
2.05
ns
0.5
0.5
0.5
ns
1.80
ns
1.75
1.50
1.70
[30, 32,
33]
[30, 32,
33]
1.75
[30, 32,
33]
[30, 32,
33]
[30, 32,
33]
1.95
[30, 32,
33]
2.05
ns
0.50
0.60
0.70
ns
4.40
5.00
[30,33]
1.00
5.50
[30,33]
1.00
[30,33]
1.00
ns
ns
Notes
29. Parameters specified with the load capacitance in Figure 9 and Figure 10.
30. For the x18 devices, add 200 ps to this parameter in Table 14.
31. Test conditions assume a signal transition time of 2 V/ns.
32. Add 300 ps to this timing for 36M devices.
33. Add 15% to this parameter if a VCORE of 1.5V is used.
34. This parameter assumes input clock cycle to cycle jitter of ± 0ps.
Document Number: 38-06082 Rev. *H
Page 25 of 52
[+] Feedback
FullFlex
Table 14.SDR Mode (continued)
Parameter
Description
tOHZ[29]
OE to High Z
tCD1
C Rise to DQ Valid for Flow Through Mode
(LowSPD = 1)
tCA1
–200
Min
1.00
–167
Max
Min
4.40
1.00
[30, 33]
–133
Max
Min
5.00
1.00
[30, 33]
Unit
5.50
ns
[30, 33]
[30, 33]
[30, 33]
[30, 33]
13.00
ns
C Rise to Address Readback Valid for Flow Through
Mode
9.00[33]
11.00[33]
13.00
ns
tCA2
C Rise to Address Readback Valid for Pipelined
Mode
5.00[33]
6.00[33]
7.50[33]
ns
tDC[34]
DQ Output Hold after C Rise
tJIT
Clock Input Cycle to Cycle Jitter
tCQHQV[34]
9.00
1.00
Echo Clock (CQ) High HSTL
to Output Valid
1.8V LVCMOS
2.5V LVCMOS 3.3V
LVTTL
tCQHQX[34]
Echo Clock (CQ) High HSTL
to Output Hold
1.8V LVCMOS
2.5V LVCMOS 3.3V
LVTTL
11.00
Max
1.00
[33]
1.00
ns
+/- 200
+/- 200
+/- 200
ps
[30]
[30]
[30]
0.70
0.80
0.90
ns
0.80[30]
0.90[30]
1.00[30]
ns
–0.70
–0.80
–0.90
ns
–0.85
–0.95
–1.05
ns
tCKHZ1[29]
C Rise to DQ Output High Z in Flow Through Mode 1.00
tCKLZ1[29]
C Rise to DQ Output Low Z in Flow Through Mode 1.00
1.00
1.00
ns
tAC
Address Output Hold after C Rise
1.00
1.00
ns
[29]
9.00
[30, 33]
1.00
1.00
11.00
[30, 33]
1.00
13.00
[30, 33]
ns
1.00
9.00[33]
1.00
11.00
1.00
13.00
ns
tCKHZA2[29]
C Rise to Address Output High Z for Pipelined Mode 1.00
5.00[33]
1.00
6.00[33]
1.00
7.50[33]
ns
tCKLZA[29]
C Rise to Address Output Low Z
1.00
tSCINT
C Rise to CNTINT Low
1.00
3.30[33]
1.00
4.00[33]
1.00
4.50[33]
ns
tRCINT
C Rise to CNTINT High
1.00
3.30[33]
1.00
4.00[33]
1.00
4.50[33]
ns
tSINT
C Rise to INT Low
0.50
7.00[33]
0.50
8.00[33]
0.50
8.50[33]
ns
0.50
7.00[33]
0.50
8.00[33]
0.50
8.50[33]
ns
1.00
3.30[33]
1.00
4.00[33]
1.00
4.50[33]
ns
tCKHZA1
tRINT
tBSY
C Rise to Address Output High Z for Flow Through
Mode
C Rise to INT High
C Rise to BUSY Valid
Document Number: 38-06082 Rev. *H
[33]
1.00
[33]
1.00
ns
Page 26 of 52
[+] Feedback
FullFlex
Table 15.Master Reset Timing
Parameter
Description
–200
Min
–167
Max
Min
–133
Max
Min
Unit
Max
tPUP
Power Up Time
1
1
1
ms
tRS
Master Reset Pulse Width
5
5
5
cycles
tRSR
Master Reset Recovery Time
5
tRSF
Master Reset to Outputs Inactive/Hi Z
[35]
5
5
15
18
cycles
22.50
ns
tRDY
Master Reset Release to Port Ready
1024
1024
1024
cycles
tCORDY[36]
C Rise to Port Ready
9.5[33]
11[33]
13[33]
ns
Table 16.JTAG Timing
Parameter
Description
–200
Min
–167
Max
Min
20
–133
Max
Min
20
Max
fJTAG
JTAG TAP Controller Frequency
tTCYC
TCK Cycle Time
50
50
50
ns
tTH
TCK High Time
20
20
20
ns
tTL
TCK Low Time
20
20
20
ns
tTMSS
TMS Setup to TCK Rise
10
10
10
ns
tTMSH
TMS Hold to TCK Rise
10
10
10
ns
tTDIS
TDI Setup to TCK Rise
10
10
10
ns
tTDIH
TDI Hold to TCK Rise
10
tTDOV
TCK Low to TDO Valid
tTDOX
TCK Low to TDO Invalid
tJXZ
TCK Low to TDO High Z
15
15
15
ns
tJZX
TCK Low to TDO Active
15
15
15
ns
tJZX
TCK Low to TDO Active
15
15
15
ns
10
10
0
20
Unit
10
10
0
MHz
ns
10
0
ns
ns
.
Notes
35. READY is a wired OR capable output with a weak pull down. For a decreased falling delay, connect a 250-Ω resistor to VSS.
36. Add this propagation delay after tRDY for all Master Reset Operations
Document Number: 38-06082 Rev. *H
Page 27 of 52
[+] Feedback
FullFlex
Switching Waveforms
Figure 12. JTAG Timing
tTH
Test Clock
TCK
tTL
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Figure 13. Master Reset [35]
~
VCORE
tPUP
tRS
MRST
~
C
~
tRDY
READY
All Address
& Data
tRSF
tCORDY
~
~
tRSR
All Other
Inputs
Document Number: 38-06082 Rev. *H
~
Page 28 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 14. READ Cycle for Pipelined Mode
tCYC
C
CE
OE
tSAC
tHAC
R/W
A
An
An+1
2 Pipelined stages
DQ DQx-1
An+2
DQx
DQn
An+3
DQn+1
tDC
An+4
DQn+2
An+5
DQn+3
An+6
DQn+4
tCD2
Figure 15. WRITE Cycle for Pipelined and Flow Through Modes
tCYC
C
CE
R/W
A
An
An+1
An+2
An+3
An+4
An+5
An+6
DQn+1
DQn+2
DQn+3
DQn+4
DQn+5
DQn+6
2 Pipelined stages
DQ
DQn
tSD
Document Number: 38-06082 Rev. *H
tHD
Page 29 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 16. READ with Address Counter Advance for Pipelined Mode
tCYC
C
A
An
Internal
Address
An
An+1
An+2
An+3
ADS
CNTEN
DQ
DQx-1
DQx
DQn
DQn+1
DQn+2
DQn+3
Figure 17. READ with Address Counter Advance for Flow Through Mode
tC Y C
C
tS A C tH A C
A
An
ADS
t S AC t H AC
C NT E N
tC D 1
DQ
DQx
DQ n
DQn + 1
DQn + 2
DQ n + 3
DQn + 4
tD C
R EA D E XT E R N A L A D D R E SS
Document Number: 38-06082 Rev. *H
R E AD W IT H C O U N TE R
C OU N T ER H O L D
R EA D W IT H C O U N T E R
Page 30 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 18. Port-to-Port WRITE–READ for Pipelined Mode
tCYC
Left Port
CL
An
AL
R/WL
DQL
DQn
Right Port
tCCS
CR
tCYC
AR
An
R/WR
tSAC tHAC
DQR
DQn
tCD2
tDC
Figure 19. Chip Enable READ for Pipelined Mode
tCYC
C
CE0
CE1
R/W
tSAC tHAC
A
An
An+1
An+2
An+3
An+4
tCD2
Document Number: 38-06082 Rev. *H
An+6
DQn+3
DQn
DQ
An+5
tDC
tCKLZ2
Page 31 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 20. OE Controlled WRITE for Pipelined Mode
tCYC
C
A
Ax+1
Ax+2
Ax+3
An
An+1
An+2
An+3
DQn
DQn+1
DQn+2
DQn+3
R/W
OE
tOHZ
DQx+1
DQ
DQx-1
DQx
Figure 21. OE Controlled WRITE for Flow Through Mode
tCYC
C
A
Ax+1
Ax+2
Ax+3
An
An+1
An+2
An+3
DQn
DQn+1
DQn+2
DQn+3
R/W
OE
tOHZ
DQx+2
DQ
DQx
DQx+1
Document Number: 38-06082 Rev. *H
Page 32 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 22. Byte-Enable READ for Pipelined Mode
tCYC
C
A
An
An+1
An+2
An+3
R/W
BE7
BE6
BE5
BE4
BE3
BE2
BE1
BE0
tCKLZ2
t
DQn+1(63:71) CKHZ2
DQ63:71
DQ54:62
DQn+1(54:62)
DQn+2(45:53)
DQ45:53
DQn+2(36:44)
DQ36:44
DQn+1(27:35)
DQ27:35
DQ18:26
DQn+2(18:26)
DQn+3(9:17)
DQ9:17
DQ0:8
Document Number: 38-06082 Rev. *H
DQn+3(0:8)
Page 33 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 23. Port-to-Port WRITE-to-READ for Flow Through Mode
CL
R /W L
tS A C
AL
tH A C
NO MATCH
M A TC H
tS D
DQL
tH D
V A LID
tC C S
CR
tCD1
R /W R
tH A C
tS A C
AR
NO MATCH
M A TC H
tC D 1
VA LID
DQR
tD C
Document Number: 38-06082 Rev. *H
V A L ID
tDC
Page 34 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 24. Busy Address Readback for Pipelined and Flow Through Modes, CNT/MSK = RET = LOW[37]
tCYC
~
C
Internal
Amatch+2
Address
Amatch+3
~
Amatch+4
BUSY
~
~
CNTEN
~
ADS
External
Address
Pipelined
~
Amatch
tCA2
External
Address
Flow through
~
tAC
Amatch
tAC
tCA1
Figure 25. Read Cycle for Flow Through Mode
t CY C
C
CE 0
t SA C
t H AC
CE 1
B En
R /W
t S AC
A
t H AC
An + 1
An
tC D 1
DQ
An + 2
DQ n
t C KLZ 1
An + 3
t C KH Z 1
tD C
DQn + 1
tO H Z
DQn + 2
tD C
tOLZ
OE
tO E
Note
37. Amatch is the matching address that is reported on the address bus of the losing port. The counter operation selected for reporting the address is “Busy Address
Readback.”
Document Number: 38-06082 Rev. *H
Page 35 of 52
[+] Feedback
FullFlex
Switching Waveforms (continued)
Figure 26. READ-to-WRITE for Pipelined Mode (OE = VIL)[38, 39, 40]
tCYC
tCL
C
A
tCH
Ax
An
An+1
tSAC tHAC
R/W
DQ
An+2
tSAC tHAC
tCKLZ2
DQx-2
DQx-1
DQx
tDC
tCD2
DQn
DQn+1
tCKHZ2
DQn+2
tSD tHD
Figure 27. READ-to-WRITE for Pipelined Mode (OE Controlled)[41, 42]
tCYC
C
A
Ax
Ax+1
Ax+2
An
An+1
An+2
An+3
DQn+1
DQn+2
DQn+3
tSAC tHAC
R/W
OE
tOHZ
tSD
tHD
DQx
DQ
DQx-2
DQx-1
DQn
Notes
38. When OE = VIL, the last read operation is enabled to complete before the DQ bus is tri-stated and the user is enabled to drive write data.
39. Two dummy writes are issued to accomplish bus turnaround. The third instruction is the first valid write.
40. Chip enable or all byte enables are held inactive during the two dummy writes to avoid data corruption.
41. OE is deasserted and tOHZ enabled to elapse before the first write operation is issued.
42. Any write scheduled to complete after OE is deasserted is pre-empted.
Document Number: 38-06082 Rev. *H
Page 36 of 52
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Switching Waveforms (continued)
Figure 28. Read-to-Write-to-Read for Flow Through Mode (OE = LOW)
t CYC
C
t SAC t HAC
CE0
CE 1
B En
t SAC t HAC
R/W
A
An
An + 1
An + 2
An + 2
t SD
DQ IN
An + 3
An + 4
tH D
DQn + 2
t CD1
t C D1
DQ n
D Q O UT
t C D1
DQn + 1
t CD1
DQ n + 3
t CKHZ1
t CKLZ1
tD C
READ
Document Number: 38-06082 Rev. *H
tD C
NO P
W RITE
R EAD
Page 37 of 52
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FullFlex
Switching Waveforms (continued)
Figure 29. Read-to-Write-to-Read for Flow Through Mode (OE Controlled)
t C YC
C
t SA C t H AC
CE0
CE1
BEn
t SA C t H A C
R /W
A
An
An + 1
An + 2
tS D
D Q IN
DQn + 2
tC D 1
D Q O UT
An + 3
An + 4
An + 5
tH D
DQn + 3
tD C
tO E
tC D 1
tC D 1
DQn
DQn + 4
t C KL Z 1
tO H Z
tD C
OE
READ
Document Number: 38-06082 Rev. *H
W R IT E
R EA D
Page 38 of 52
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Switching Waveforms (continued)
Figure 30. BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow Through Modes, Clock Timing Violates tCCS.
(Flag Both Ports)
Port A
C
A
R/W
BUSY
< tCCS
tBSY
tBSY
Port B
C
A
R/W
tBSY
BUSY
tBSY
Figure 31. BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow Through Modes, Clock Timing Meets tCCS.
(Flag Losing Port)
Losing Port
C
A
R/W
BUSY
tccs
tBSY
tBSY
Winning Port
C
A
Match
R/W
BUSY
Document Number: 38-06082 Rev. *H
Page 39 of 52
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Switching Waveforms (continued)
Figure 32. Read with Echo Clock for Pipelined Mode (CQEN = HIGH)
C
tSAC
tHAC
R/W
A
An
An+1
An+2
An+3
An+4
An+5
An+6
CQ0
CQ0
tCCQ
CQ1
CQ1
tCQHQX
tCQHQV
DQ
DQx-1
DQx
Document Number: 38-06082 Rev. *H
DQn
DQn+1
DQn+2
DQn+3
DQn+4
Page 40 of 52
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FullFlex
Switching Waveforms (continued)
Figure 33. Mailbox Interrupt Output
tCYC
CL
AL
AMAX
R/WL
DQL
INTR
tSINT
tRINT
CR
AR
AMAX
R/WR
DQR
Document Number: 38-06082 Rev. *H
DQMAX
Page 41 of 52
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Ordering Information
512K × 72 (36 Mbit) 1.8V/1.5V Synchronous CYD36S72V18 Dual Port SRAM
Speed
(MHz)
200
Ordering Code
CYD36S72V18-200BGXC
Package
Diagram
CYD36S72V18-167BGXC
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
CYD36S72V18-167BGC
CYD36S72V18-167BGXI
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free)
CYD36S72V18-167BGI
133
CYD36S72V18-133BGXC
Industrial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
CYD36S72V18-133BGC
CYD36S72V18-133BGXI
Operating
Range
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
CYD36S72V18-200BGC
167
Package Type
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free)
CYD36S72V18-133BGI
Industrial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
256K × 72 (18 Mbit) 1.8V/1.5V Synchronous CYD18S72V18 Dual Port SRAM
Speed
(MHz)
200
Ordering Code
CYD18S72V18-200BGXC
Package
Diagram
51-85218
CYD18S72V18-200BGC
CYD18S72V18-200BGXI
CYD18S72V18-167BGXC
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free)
Industrial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
51-85218
CYD18S72V18-167BGC
CYD18S72V18-167BGXI
Operating
Range
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
51-85218
CYD18S72V18-200BGI
167
Package Type
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
51-85218
CYD18S72V18-167BGI
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free)
Industrial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
128K × 72 (9 Mbit) 1.8V/1.5V Synchronous CYD09S72V18 Dual Port SRAM
Speed
(MHz)
200
Ordering Code
CYD09S72V18-200BGXC
Package
Diagram
51-85218
CYD09S72V18-200BGC
CYD09S72V18-200BGXI
CYD09S72V18-167BGXC
51-85218
CYD09S72V18-167BGI
Document Number: 38-06082 Rev. *H
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free)
Industrial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
51-85218
CYD09S72V18-167BGC
CYD09S72V18-167BGXI
Operating
Range
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
CYD09S72V18-200BGI
167
Package Type
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
51-85218
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free)
Industrial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
Page 42 of 52
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Ordering Information (continued)
64K × 72 (4 Mbit) 1.8V/1.5V Synchronous CYD04S72V18 Dual Port SRAM
Speed
(MHz)
200
Ordering Code
CYD04S72V18-200BGXC
Package
Diagram
51-85218
CYD04S72V18-200BGC
CYD04S72V18-200BGXI
CYD04S72V18-167BGXC
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free)
Industrial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
51-85218
CYD04S72V18-167BGC
CYD04S72V18-167BGXI
Operating
Range
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
51-85218
CYD04S72V18-200BGI
167
Package Type
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free) Commercial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
51-85218
CYD04S72V18-167BGI
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch (Pb-Free)
Industrial
484-Ball Grid Array 23 mm x 23 mm with 1.0 mm pitch
1024K × 36 (36 Mbit) 1.8V/1.5V Synchronous CYD36S36V18 Dual Port SRAM
Speed
(MHz)
200
Ordering Code
CYD36S36V18-200BGXC
Package
Diagram
CYD36S36V18-167BGXC
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
CYD36S36V18-167BGC
CYD36S36V18-167BGXI
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free)
CYD36S36V18-167BGI
133
CYD36S36V18-133BGXC
Industrial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
CYD36S36V18-133BGC
CYD36S36V18-133BGXI
Operating
Range
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
CYD36S36V18-200BGC
167
Package Type
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free)
CYD36S36V18-133BGI
Industrial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
512K × 36 (18 Mbit) 1.8V/1.5V Synchronous CYD18S36V18 Dual Port SRAM
Speed
(MHz)
200
Ordering Code
CYD18S36V18-200BBAXC
Package
Diagram
51-85108
CYD18S36V18-200BBAC
CYD18S36V18-200BBAXI
CYD18S36V18-167BBAXC
51-85108
CYD18S36V18-167BBAI
Document Number: 38-06082 Rev. *H
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free)
Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108
CYD18S36V18-167BBAC
CYD18S36V18-167BBAXI
Operating
Range
256-ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
CYD18S36V18-200BBAI
167
Package Type
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free)
Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
Page 43 of 52
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Ordering Information (continued)
256K × 36 (9 Mbit) 1.8V/1.5V Synchronous CYD09S36V18 Dual Port SRAM
Speed
(MHz)
200
Ordering Code
CYD09S36V18-200BBXC
Package
Diagram
51-85108
CYD09S36V18-200BBC
CYD09S36V18-200BBXI
CYD09S36V18-167BBXC
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free)
Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108
CYD09S36V18-167BBC
CYD09S36V18-167BBXI
Operating
Range
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108
CYD09S36V18-200BBI
167
Package Type
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108
CYD09S36V18-167BBI
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free)
Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
128K × 36 (4 Mbit) 1.8V/1.5V Synchronous CYD04S36V18 Dual Port SRAM
Speed
(MHz)
200
Ordering Code
CYD04S36V18-200BBXC
Package
Diagram
51-85108
CYD04S36V18-200BBC
CYD04S36V18-200BBXI
CYD04S36V18-167BBXC
51-85108
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free)
Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108
CYD04S36V18-167BBC
CYD04S36V18-167BBXI
Operating
Range
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
CYD04S36V18-200BBI
167
Package Type
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108
CYD04S36V18-167BBI
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free)
Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
64K × 36 (2 Mbit) 1.8V/1.5V Synchronous CYD02S36V18 Dual Port SRAM
Speed
(MHz)
Ordering Code
Package
Diagram
Package Type
Operating
Range
200
CYD02S36V18-200BBXI
51-85108
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free)
Industrial
167
CYD02S36V18-167BBXI
51-85108
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free)
Industrial
Document Number: 38-06082 Rev. *H
Page 44 of 52
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Ordering Information (continued)
2048K × 18 (36 Mbit) 1.8V/1.5V Synchronous CYD36S18V18 Dual Port SRAM
Speed
(MHz)
200
Ordering Code
CYD36S18V18-200BGXC
Package
Diagram
CYD36S18V18-167BGXC
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
CYD36S18V18-167BGC
CYD36S18V18-167BGXI
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free)
CYD36S18V18-167BGI
133
CYD36S18V18-133BGXC
Industrial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
CYD36S18V18-133BGC
CYD36S18V18-133BGXI
Operating
Range
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free) Commercial
CYD36S18V18-200BGC
167
Package Type
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
001-07825 484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch (Pb-Free)
CYD36S18V18-133BGI
Industrial
484-Ball Grid Array 27 mm x 27 mm with 1.0 mm pitch
1024K × 18 (18 Mbit) 1.8V/1.5V Synchronous CYD18S18V18 Dual Port SRAM
Speed
MHz)
200
Ordering Code
CYD18S18V18-200BBAXC
Package
Diagram
51-85108
CYD18S18V18-200BBAC
CYD18S18V18-200BBAXI
CYD18S18V18-167BBAXC
51-85108
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free)
Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108
CYD18S18V18-167BBAC
CYD18S18V18-167BBAXI
Operating
Range
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
CYD18S18V18-200BBAI
167
Package Type
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108
CYD18S18V18-167BBAI
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free)
Industrial
256-Ball Grid Array 17 mm x 17mm with 1.0 mm pitch
512K × 18 (9 Mbit) 1.8V/1.5V Synchronous CYD09S18V18 Dual Port SRAM
Speed
(MHz)
200
Ordering Code
CYD09S18V18-200BBXC
Package
Diagram
51-85108
CYD09S18V18-200BBC
CYD09S18V18-200BBXI
CYD09S18V18-167BBXC
CYD09S18V18-167BBI
Document Number: 38-06082 Rev. *H
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free)
Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108
CYD09S18V18-167BBC
CYD09S18V18-167BBXI
Operating
Range
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108
CYD09S18V18-200BBI
167
Package Type
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free)
Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
Page 45 of 52
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Ordering Information (continued)
256K × 18 (4 Mbit) 1.8V or 1.5V Synchronous CYD04S18V18 Dual Port SRAM
Speed
(MHz)
200
Ordering Code
CYD04S18V18-200BBXC
Package
Diagram
51-85108
CYD04S18V18-200BBC
CYD04S18V18-200BBXI
CYD04S18V18-167BBXC
CYD04S18V18-167BBI
Document Number: 38-06082 Rev. *H
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free)
Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108
CYD04S18V18-167BBC
CYD04S18V18-167BBXI
Operating
Range
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108
CYD04S18V18-200BBI
167
Package Type
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free) Commercial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
51-85108
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch (Pb-Free)
Industrial
256-Ball Grid Array 17 mm x 17 mm with 1.0 mm pitch
Page 46 of 52
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Package Diagrams
Figure 34. 256-Ball FBGA (17 x 17 mm), 51-85108
TOP VIEW
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
Ø0.45±0.05(256X)-CPLD DEVICES (37K & 39K)
PIN 1 CORNER
+0.10
-0.05
Ø0.50 (256X)-ALL OTHER DEVICES
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
B
C
C
D
D
1.00
A
E
E
F
F
G
H
J
K
H
15.00
17.00±0.10
G
J
K
L
M
7.50
L
M
N
N
P
P
R
R
T
T
1.00
7.50
0.15 C
0.70±0.05
0.25 C
B
15.00
A
17.00±0.10
A
0.20(4X)
SEATING PLANE
+0.10
-0.05
C
A1 0.36
0.56
REFERENCE JEDEC MO-192
0.35
A1
A 1.40 MAX. 1.70 MAX.
51-85108-*F
Document Number: 38-06082 Rev. *H
Page 47 of 52
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Package Diagrams
Figure 35. 484-Ball PBGA (23 mm x 23 mm x 2.03 mm), 51-85218
Ø0.50~Ø0.70(484X)
PIN #1 CORNER
1
3
2
5
4
7
6
9
8
15
13
11
10
12
14
19
17
16
18
21
20
21
22
22
Ø1.00(3X) REF.
18
14
9
11
13
15
16
12
10
7
8
4
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
21.00
23.00±0.20
20.00 REF.
1
3
5
6
1.00
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
17
19
20
1.00
-B-
21.00
3.20*45°(4x)
-A20.00 REF.
23.00±0.20
0.35 C
0.20 C
f
0.25 C
30° TYP.
f
0.97 REF.
0.20(4X)
Jedec Outline - Design Guide 4.14
Document Number: 38-06082 Rev. *H
2.03 ± 0.13
0.40~0.60
SEATING PLANE
0.56 REF.
-C-
Package Weight - 2.0 grams
51-85218-**
Page 48 of 52
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Package Diagrams
Figure 36. 484-Ball PBGA (27 mm x 27 mm x 2.33 mm), 001-07825
001-07825-**
Document Number: 38-06082 Rev. *H
Page 49 of 52
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Document History Page
Document Title: FullFlex™ Synchronous SDR Dual Port SRAM
Document Number: 38-06082
REV.
ECN NO.
Submission
Date
Orig. of
Change
Description of Change
**
302411
See ECN
YDT
New data sheet
*A
334036
See ECN
YDT
Corrected typo on page 1
Reproduced PDF file to fix formatting errors
*B
395800
See ECN
SPN
Added statement about no echo clocks for flow through mode
Updated electrical characteristics
Added note 16 and 17 (1.5V timing)
Added note 33 (timing for x18 devices)
Updated input edge rate (note 34)
Updated table 5 on deterministic access control logic
Added description of busy readback in deterministic access control section
Changed dummy write descriptions
Updated ZQ pins connection details
Updated note 24, B0 to BE0
Added power supply requirements to MRST and VC_SEL
Added note 4 (VIM disable)
Updated supply voltage to ground potential to 4.1V
Updated parameters on table 15
Updated and added parameters to table 16
Updated x72 pinout to SDR only pinout
Updated 484 PBGA pin diagram
Updated the pin definition of MRST
Updated the pin definition of VC_SEL
Updated READY description to include Wired OR note
Updated master reset to include wired OR note for READY
Updated minimum VOH value for the 1.8V LVCMOS configuration
Updated electrical characteristics to include IOH and IOL values
Updated electrical characteristics to include READY
Added IIX3
Updated maximum input capacitance
Added Notes 33 and 34Removed Notes 15 and 17
Updated Pin Definitions for CQ0, CQ0, CQ1, and CQ1
Removed -100 Speed bin from Table.1 Selection Guide
Changed voltage name from VDDQ to VDDIO
Changed voltage name from VDD to VCORE
Moved the Mailbox Interrupt Timing Diagram to be the final timing diagram
Updated the Package Type for the CYD36S18V18 parts
Updated the Package Type for the CYD36S18V18 parts
Updated the Package Type for the CYD18S18V18 parts
Updated the Package Type for the CYD18S36V18 parts
Included the Package Diagram for the 256-Ball FBGA (19 x 19 mm) BW256
Included an OE Controlled Write for Flow through Mode Switching Waveform
Included a Read with Echo Clock Switching Waveform
Updated Figure 5 and Figure 6
Updated Electrical Characteristics for READY VOH and READY V
Updated Electrical Characteristics for VOH and VOL for the -167 and -133 speeds
Included a Unit column for Table 5
Removed Switching Characteristic tCA from chart
Included tOHZ in Switching Waveform OE Controlled Write for Pipelined Mode
Included tCKLZ2 in Waveform Read-to-Write-to-Read for Flow through Mode
Document Number: 38-06082 Rev. *H
Page 50 of 52
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Document History Page
Document Title: FullFlex™ Synchronous SDR Dual Port SRAM
Document Number: 38-06082
REV.
ECN NO.
Submission
Date
Orig. of
Change
*C
402238
SEE ECN
KGH
Updated AC Test Load and Waveforms
Included FullFlex36 SDR 484-Ball BGA Pinout (Top View)
Included FullFlex18 SDR 484-Ball BGA Pinout (Top View)
Included Timing Parameter tCORDY
*D
458131
SEE ECN
YDT
Changed ordering information with Pb-free part numbers
Removed VC_SEL
Added IO and core voltage adders
Removed references to bin drop for LVTTL/2.5V LVCMOS and 1.5V core modes
Updated Cin and Cout
Updated ICC, ISB1, ISB2 and ISB3 tables
Updated busy address read back timing diagram
Added HTSL input waveform
Removed HSTL (AC) from DC tables
Added 484-ball 27 mmx27 mmx2.33 mm PBGA package
*E
470031
SEE ECN
YDT
Changed VOL of 1.8V LVCMOS to 0.45V
Updated tRSF
VREF is DNU when HSTL is not used
Formatted pin description table
Changed VDDIO pins for 36M x 36 and 36M x 18 pinouts
Changed 36Mx72 JTAG IDCODE
*F
500001
SEE ECN
YDT
DLL Change, added Clock Input Cycle to Cycle Jitter
Modified DLL description
Changed Input Capacitance Table
Changed tCCS number
Added note 31
*G
627539
SEE ECN
QSL
change all NC to DNU
corrected switching waveform for (CQEN = High) from both Pipeline and Flow
through mode to only pipeline mode
Modified master reset description
Modified switching characteristics tables, extracted signals effected by the DLL
into one table and combine all other signals into one table
updated package name
Added footnote for tHD, tHAC and tSAC
changed note 26 description
Document Number: 38-06082 Rev. *H
Description of Change
Page 51 of 52
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Document History Page
Document Title: FullFlex™ Synchronous SDR Dual Port SRAM
Document Number: 38-06082
REV.
ECN NO.
Submission
Date
Orig. of
Change
Description of Change
*H
2505003
See ECN
VKN/
AESA
Modified footnote #1
Removed 250 MHz speed bin
Added 2-Mbit part and it’s related information
Changed ball name ZQ1 to DNU for 18M and lesser density devices
Added 256-Ball (17 x 17 mm) BGA package for 18M
Made PORTSTD[1:0] left and right pins driven only by LVTTL reference level
For 1.8V LVCMOS level, Changed VIH(min) from 1.26V to 0.65 times VDDIO and
Changed VIL(max) from 0.36V to 0.35 times VDDIO
Changed tHD, tHAC specs for 36M from 0.6 ns/0.7 ns to 0.8 ns (See footnote# 32)
Updated Ordering Information table
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Document Number: 38-06082 Rev. *H
Revised May 15, 2008
Page 52 of 52
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