CYD18S18V18-167BBAXI

CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex™ Synchronous SDR Dual-Port SRAM FullFlex™ Synchronous SDR Dual-Port SRAM Features Functional Description ■ True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate (SDR) operation on each port ❐ SDR interface at 200 MHz ❐ Up to 28.8 Gbps bandwidth (200 MHz × 72-bit × 2 ports) ■ Selectable pipelined or flow-through mode ■ 1.5 V or 1.8 V core power supply ■ Commercial and Industrial temperature ■ IEEE 1149.1 JTAG boundary scan ■ Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36 and × 18) packages ■ FullFlex72 family ❐ 36-Mbit: 512K × 72 (CYD36S72V18) ❐ 18-Mbit: 256K × 72 (CYD18S72V18) ❐ 9-Mbit: 128K × 72 (CYD09S72V18) ■ FullFlex36 family ❐ 36-Mbit: 1M × 36 (CYD36S36V18) ❐ 18-Mbit: 512K × 36 (CYD18S36V18) ❐ 9-Mbit: 256K × 36 (CYD09S36V18) ❐ 2-Mbit: 64K × 36 (CYD02S36V18) ■ FullFlex18 family ❐ 36-Mbit: 2M × 18 (CYD36S18V18) ❐ 18-Mbit: 1M × 18 (CYD18S18V18) ❐ 9-Mbit: 512K × 18 (CYD09S18V18) The FullFlex™ dual port SRAM families consist of 2-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static RAMs that are high-speed, low-power 1.8 V or 1.5 V CMOS. Two ports are provided, enabling simultaneous access to the array. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports operate independently with 72-bit bus widths and each port is independently configured for two pipelined stages. Each port is also configured to operate in pipelined or flow through mode. The advanced features include the following: ■ Built-in deterministic access control to manage address collisions during simultaneous access to the same memory location ■ Variable impedance matching (VIM) to improve data transmission by matching the output driver impedance to the line impedance ■ Echo clocks to improve data transfer To reduce the static power consumption, chip enables power down the internal circuitry. The number of latency cycles, before a change in CE0 or CE1 enables or disables the databus, matches the number of cycles of read latency selected for the device. For a valid write or read to occur, activate both chip enable inputs on a port. Each port contains an optional burst counter on the input address register. After externally loading the counter with the initial address, the counter increments the address internally. ■ Built-in deterministic access control to manage address collisions ❐ Deterministic flag output upon collision detection ❐ Collision detection on back-to-back clock cycles ❐ First busy address readback ■ Advanced features for improved high-speed data transfer and flexibility ❐ Variable impedance matching (VIM) ❐ Echo clocks [1] ❐ Selectable LVTTL (3.3 V), Extended HSTL (1.4 V to 1.9 V), 1.8 V LVCMOS, or 2.5 V LVCMOS I/O on each port ❐ Burst counters for sequential memory access ❐ Mailbox with interrupt flags for message passing ❐ Dual chip enables for easy depth expansion Additional device features include a mask register and a mirror register to control counter increments and wrap around. The counter interrupt (CNTINT) flags notify the host that the counter reaches maximum count value on the next clock cycle. The host reads the burst counter internal address, mask register address, and busy address on the address lines. The host also loads the counter with the address stored in the mirror register by using the retransmit functionality. Mailbox interrupt flags are used for message passing, and JTAG boundary scan and asynchronous Master Reset (MRST) are also available. The Logic Block Diagram on page 2 shows these features. The FullFlex72 is offered in a 484-ball plastic BGA package. The FullFlex36 and FullFlex18 are available in 256-ball fine pitch BGA package except the 36-Mbit devices which are offered in 484-ball plastic BGA package. For a complete list of related documentation, click here. Note 1. HSTL support and the corresponding tests support has been removed from the device from WW1830. This change does not impact any other functionality. Cypress Semiconductor Corporation Document Number: 38-06082 Rev. *S • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 24, 2018 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Logic Block Diagram The Logic Block Diagrams for the FullFlex72, FullFlex36, and FullFlex18 families follow.[2, 3, 4] FTSELL FTSELR CQENL CONFIG Block PORTSTD[1:0]L CONFIG Block CQENR PORTSTD[1:0]R DQ[71:0]L BE [7:0]L CE0L CE1L OEL IO Control IO Control DQ [71:0]R BE [7:0]R CE0R CE1R OER R/WR R/WL CQ1L CQ1L CQ0L CQ0L CQ1R CQ1R CQ0R CQ0R Dual Port Array BUSYL A [20:0]L CNT/MSKL ADSL CNTENL CNTRSTL RETL CNTINTL CL Collision Detection Logic Address & Counter Logic BUSYR Address & Counter Logic WRPL A [20:0]R CNT/MSKR ADSR CNTENR CNTRSTR RETR CNTINTR CR WRPR Mailboxes INTL INTR ZQ0L ZQ1L READYL LowSPDL JTAG RESET LOGIC TRST TMS TDI TDO TCK ZQ0R ZQ1R MRST READYR LowSPDR Notes 2. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits. The CYD02S36V18 has 16 address bits. 3. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines. 4. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte enables. Document Number: 38-06082 Rev. *S Page 2 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Contents Selection Guide ................................................................ 9 Pin Definitions .................................................................. 9 Functional Overview ...................................................... 11 Selectable IO Standard ............................................. 11 Clocking ..................................................................... 11 Selectable Pipelined or Flow through Mode .............. 11 DLL ............................................................................ 11 Echo Clocking ........................................................... 11 Deterministic Access Control .................................... 11 Variable Impedance Matching ................................... 12 Address Counter and Mask Register Operations [28] ................................... 13 Counter Load Operation [28] ................................................. 13 Mask Load Operation [28] .......................................... 13 Counter Readback Operation .................................... 13 Mask Readback Operation ........................................ 13 Counter Reset Operation .......................................... 13 Mask Reset Operation ............................................... 13 Increment Operation[31] ............................................. 15 Hold Operation .......................................................... 15 Retransmit ................................................................. 15 Counter Interrupt ....................................................... 15 Counting by Two ....................................................... 15 Counting by Four ....................................................... 15 Mailbox Interrupts ...................................................... 15 Master Reset ............................................................. 18 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 18 Maximum Ratings ........................................................... 19 Operating Range ............................................................. 19 Power Supply Requirements ......................................... 19 Electrical Characteristics ............................................... 19 Electrical Characteristics ............................................... 21 Electrical Characteristics ............................................... 23 Capacitance .................................................................... 23 Thermal Resistance ........................................................ 23 AC Test Load and Waveforms ....................................... 24 Document Number: 38-06082 Rev. *S Switching Characteristics .............................................. 25 Switching Waveforms .................................................... 28 Ordering Information ...................................................... 42 512K × 72 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S72V18 Dual-Port SRAM ................ 42 256K × 72 (18-Mbit) 1.8 V/1.5 V Synchronous CYD18S72V18 Dual-Port SRAM ................ 42 128K × 72 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S72V18 Dual-Port SRAM ................ 42 1024K × 36 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S36V18 Dual-Port SRAM ................ 42 512K × 36 (18-Mbit) 1.8 V/1.5 V Synchronous CYD18S36V18 Dual-Port SRAM ................ 42 256K × 36 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S36V18 Dual-Port SRAM ................ 42 64K × 36 (2-Mbit) 1.8 V or 1.5 V Synchronous CYD02S36V18 Dual-Port SRAM ................ 42 2048K × 18 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S18V18 Dual-Port SRAM ................ 42 1024K × 18 (18-Mbit) 1.8 V/1.5 V Synchronous CYD18S18V18 Dual-Port SRAM ................ 42 512K × 18 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S18V18 Dual-Port SRAM ................ 42 Ordering Code Definitions ......................................... 43 Package Diagrams .......................................................... 44 Acronyms ........................................................................ 47 Document Conventions ................................................. 47 Units of Measure ....................................................... 47 Document History Page ................................................. 48 Sales, Solutions, and Legal Information ...................... 51 Worldwide Sales and Design Support ....................... 51 Products .................................................................... 51 PSoC® Solutions ...................................................... 51 Cypress Developer Community ................................. 51 Technical Support ..................................................... 51 Page 3 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Figure 1. FullFlex72 SDR 484-ball BGA Pinout (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A DNU DQ61L DQ59L DQ57L DQ54L DQ51L DQ48L DQ45L DQ42L DQ39L B DQ63L DQ62L DQ60L DQ58L DQ55L DQ52L DQ49L DQ46L DQ43L DQ40L DQ41L DQ38L DQ38R 15 16 DQ36L DQ36R DQ39R DQ42R DQ45R DQ48R DQ37L DQ37R DQ40R DQ43R DQ46R DQ49R 17 18 19 20 21 DQ51R DQ54R DQ57R DQ59R DQ61R DNU DQ52R DQ55R DQ58R DQ60R DQ62R DQ63R C DQ65L DQ64L VSS VSS DQ56L DQ53L DQ50L DQ47L DQ44L D DQ67L DQ66L VSS VSS VSS CQ1L CQ1L VSS LOWSPDL E DQ69L DQ68L VDDIOL VSS VSS VDDIOL VDDIOL VDDIOL VDDIOL VDDIOL F DQ71L DQ70L CE1L CE0L VDDIOL VDDIOL VDDIOL VDDIOL VDDIOL VCORE G A0L A1L RETL BE4L VDDIOL VDDIOL VREFL VSS VSS VSS VSS VSS VSS VSS VSS VREFR VDDIOR VDDIOR H A2L A3L WRPL BE5L VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR J A4L A5L READYL BE6L VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR K A6L A7L ZQ1L[5, 6] BE7L VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VDDIOR PORTSTD0L ZQ0L[5] BUSYL VTTL VTTL VCORE VCORE 22 DQ41R DQ44R DQ47R DQ50R DQ53R DQ56R VSS VSS DQ64R DQ65R CNTINTL PORTSTD1L DNU CQ1R CQ1R VSS VSS VSS DQ66R DQ67R VTTL VDDIOR VDDIOR VDDIOR VDDIOR VSS VDDIOR DQ68R DQ69R VCORE VDDIOR VDDIOR VDDIOR VDDIOR VDDIOR CE0R CE1R DQ70R DQ71R BE4R RETR A1R A0R BE5R WRPR A3R A2R BE6R READYR A5R A4R BE7R ZQ1R[5, 6] A7R A6R DNU L A8L A9L CL OEL VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL OER CR A9R A8R M A10L A11L VSS BE3L VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL BE3R VSS A11R A10R N A12L A13L ADSL BE2L VDDIOL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL BE2R ADSR A13R A12R P A14L A15L CNT/MSKL BE1L VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR BE1R CNT/MSKR A15R A14R A16R[9] [9] A17L[8] CNTENL BE0L VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR BE0R CNTENR A17R[8] CNTRSTL INTL VDDIOL VDDIOL VREFL VSS VSS VSS VSS VSS VSS VSS VSS VREFR VDDIOR VDDIOR INTR CNTRSTR DNU A18R[7] VCORE VDDIOR VDDIOR VDDIOR VDDIOR VDDIOR CQENR R/WR DQ34R DQ35R VDDIOR VDDIOR VDDIOR VDDIOR VDDIOR VDDIOR FTSELR DQ32R DQ33R R A16L T A18L[7] DNU U DQ35L DQ34L R/WL CQENL VDDIOL VDDIOL VDDIOL VDDIOL VDDIOL VCORE V DQ33L DQ32L FTSELL VDDIOL DNU VDDIOL VDDIOL VDDIOL VDDIOL VTTL VCORE VCORE VTTL VTTL W DQ31L DQ30L VSS MRST VSS CQ0L CQ0L DNU PORTSTD1R CNTINTR BUSYR ZQ0R[5] Y DQ29L DQ28L VSS VSS DQ20L DQ17L DQ14L DQ11L DQ8L DQ5L DQ2L DQ2R AA DQ27L DQ26L DQ24L DQ22L DQ19L DQ16L DQ13L DQ10L DQ7L DQ4L DQ1L DQ1R AB DNU DQ25L DQ23L DQ21L DQ18L DQ15L DQ12L DQ9L DQ6L DQ3L DQ0L DQ0R PORTSTD0R LOWSPDR TRST VSS CQ0R CQ0R VSS TDI TDO DQ30R DQ31R DQ8R DQ11R DQ14R DQ17R DQ20R TMS TCK DQ28R DQ29R DQ4R DQ7R DQ10R DQ13R DQ16R DQ19R DQ22R DQ24R DQ26R DQ27R DQ3R DQ6R DQ9R DQ12R DQ15R DQ18R DQ21R DQ23R DQ25R DNU DQ5R Notes 5. Leave this ball unconnected to disable VIM. 6. This ball is applicable only for 36-Mbit and DNU for 18-Mbit and lower densities. 7. Leave this ball unconnected for CYD18S72V18 and CYD09S72V18. 8. Leave this ball unconnected for CYD09S72V18. 9. Leave this ball unconnected for CYD04S72V18. Document Number: 38-06082 Rev. *S Page 4 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Figure 2. FullFlex36 SDR 484-ball BGA Pinout (Top View)[10] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A DNU DNU DNU DNU DNU DQ33L DQ30L DQ27L DQ24L DQ21L DQ18L DQ18R DQ21R DQ24R DQ27R DQ30R DQ33R DNU DNU DNU DNU DNU B DNU DNU DNU DNU DNU DQ34L DQ31L DQ28L DQ25L DQ22L DQ19L DQ19R DQ22R DQ25R DQ28R DQ31R DQ34R DNU DNU DNU DNU DNU C DNU DNU VSS VSS DNU DQ35L DQ32L DQ29L DQ26L DQ23L DQ20L DQ20R DQ23R DQ26R DQ29R DQ32R DQ35R DNU VSS VSS DNU DNU ZQ0L[11] BUSYL CNTINTL PORTSTD1L DNU CQ1R CQ1R VSS VSS VSS DNU DNU D DNU DNU VSS E F VSS VSS DNU DNU VDDIOL VSS VSS DNU DNU CE1L CE0L VDDIOL CQ1L CQ1L VSS LOWSPDL PORTSTD0L VDDIOL VDDIOR VDDIOR VDDIOR VDDIOR VTTL VTTL VTTL VDDIOL VDDIOL VDDIOL VDDIOL DNU VSS VDDIOR DNU DNU VDDIOL VDDIOR VDDIOR VDDIOR VCORE VCORE VCORE VCORE VDDIOL VDDIOL VDDIOL VDDIOR VDDIOR CE0R CE1R DNU DNU G A0L A1L RETL BE2L VDDIOL VDDIOL VREFL VSS VSS VSS VSS VSS VSS VSS VSS VREFR VDDIOR VDDIOR BE2R RETR A1R A0R H A2L A3L WRPL BE3L VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR BE3R WRPR A3R A2R J A4L A5L READYL DNU VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR DNU READYR A5R A4R A7L ZQ1L[11] DNU ZQ1R[11] A7R A6R A8R K A6L DNU VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VDDIOR L A8L A9L CL OEL VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL OER CR A9R M A10L A11L VSS DNU VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL DNU VSS A11R A10R N A12L A13L DNU VDDIOL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL DNU ADSR A13R A12R P A14L A15L CNT/MSKL BE1L VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR BE1R R A16L A17L CNTENL BE0L VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR BE0R T A18L A19L CNTRSTL INTL VDDIOL VDDIOL VREFL VSS VSS VSS VSS VSS VSS VSS VSS VREFR VDDIOR VDDIOR INTR U DNU DNU R/WL CQENL VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR VCORE VCORE VCORE VCORE VDDIOL VDDIOL VDDIOL VDDIOR VDDIOR CQENR R/WR DNU DNU V DNU DNU FTSELL VDDIOL DNU VDDIOR VDDIOR VDDIOR VDDIOR VTTL VTTL VTTL VDDIOL VDDIOL VDDIOL VDDIOL VDDIOR TRST VDDIOR FTSELR DNU DNU ADSL CNT/MSKR A15R A14R CNTENR A17R A16R CNTRSTR A19R A18R W DNU DNU VSS MRST VSS CQ0L CQ0L DNU PORTSTD1R CNTINTR BUSYR ZQ0R[11] VSS CQ0R CQ0R VSS TDI TDO DNU DNU Y DNU DNU VSS VSS DNU DQ17L DQ14L DQ11L DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DQ11R DQ14R DQ17R DNU TMS TCK DNU DNU AA DNU DNU DNU DNU DNU DQ16L DQ13L DQ10L DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DQ10R DQ13R DQ16R DNU DNU DNU DNU DNU AB DNU DNU DNU DNU DNU DQ15L DQ12L DQ9L DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DQ9R DQ12R DQ15R DNU DNU DNU DNU DNU PORTSTD0R LOWSPDR Notes 10. Use this pinout only for the CYD36S36V18 device of the FullFlex36 family. 11. Leave this ball unconnected to disable VIM. Document Number: 38-06082 Rev. *S Page 5 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Figure 3. FullFlex18 SDR 484-ball BGA Pinout (Top View)[12] 1 2 3 4 5 6 7 8 9 10 A DNU DNU DNU DNU DNU DNU DNU DNU DQ15L DQ12L B DNU DNU DNU DNU DNU DNU DNU DNU DQ16L DQ13L C DNU DNU VSS VSS DNU DNU DNU DNU DQ17L DQ14L LOWSPDL PORTSTD0L D DNU DNU VSS VSS VSS CQ1L CQ1L VSS 11 12 13 14 15 16 17 18 19 20 21 22 DQ9L DQ9R DQ12R DQ15R DNU DNU DNU DNU DNU DNU DNU DNU DQ10L DQ10R DQ13R DQ16R DNU DNU DNU DNU DNU DNU DNU DNU DQ11L DQ11R DQ14R DQ17R DNU DNU DNU DNU VSS VSS DNU DNU ZQ0L[13] BUSYL CNTINTL PORTSTD1L DNU CQ1R CQ1R VSS VSS VSS DNU DNU E DNU DNU VDDIOL VSS VSS VDDIOL VDDIOR VDDIOR VDDIOR VDDIOR VTTL VTTL VTTL VDDIOL VDDIOL VDDIOL VDDIOL DNU VSS VDDIOR DNU DNU F DNU DNU CE1L CE0L VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR VCORE VCORE VCORE VCORE VDDIOL VDDIOL VDDIOL VDDIOR VDDIOR CE0R CE1R DNU DNU G A0L A1L RETL BE1L VDDIOL VDDIOL VREFL VSS VSS VSS VSS VSS VSS VSS VSS VREFR VDDIOR VDDIOR BE1R RETR A1R A0R H A2L A3L WRPL DNU VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR DNU WRPR A3R A2R J A4L A5L READYL DNU VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR DNU READYR A5R A4R A7L ZQ1L[13] DNU ZQ1R[13] A7R A6R A8R K A6L DNU VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VDDIOR L A8L A9L CL OEL VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL OER CR A9R M A10L A11L VSS DNU VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL DNU VSS A11R A10R ADSL ADSR A13R A12R N A12L A13L DNU VDDIOL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL DNU P A14L A15L CNT/MSKL DNU VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR DNU R A16L A17L CNTENL BE0L VDDIOL VDDIOL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR BE0R T A18L A19L CNTRSTL INTL VDDIOL VDDIOL VREFL VSS VSS VSS VSS VSS VSS VSS VSS VREFR VDDIOR VDDIOR INTR U A20L DNU R/WL CQENL VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR VCORE VCORE VCORE VCORE VDDIOL VDDIOL VDDIOL VDDIOR VDDIOR CQENR R/WR V DNU DNU FTSELL VDDIOL DNU VDDIOR VDDIOR VDDIOR VDDIOR VTTL VTTL VTTL VDDIOL VDDIOL VDDIOL VDDIOL VDDIOR TRST VDDIOR FTSELR CNT/MSKR A15R A14R CNTENR A17R A16R CNTRSTR A19R A18R DNU A20R DNU DNU W DNU DNU VSS MRST VSS CQ0L CQ0L DNU PORTSTD1R CNTINTR BUSYR ZQ0R[13] VSS CQ0R CQ0R VSS TDI TDO DNU DNU Y DNU DNU VSS VSS DNU DNU DNU DNU DQ8L DQ5L DQ2L DQ2R DQ5R DQ8R DNU DNU DNU DNU TMS TCK DNU DNU AA DNU DNU DNU DNU DNU DNU DNU DNU DQ7L DQ4L DQ1L DQ1R DQ4R DQ7R DNU DNU DNU DNU DNU DNU DNU DNU AB DNU DNU DNU DNU DNU DNU DNU DNU DQ6L DQ3L DQ0L DQ0R DQ3R DQ6R DNU DNU DNU DNU DNU DNU DNU DNU PORTSTD0R LOWSPDR Notes 12. Use this pinout only for device CYD36S18V18 of the FullFlex18 family. 13. Leave this ball unconnected to disable VIM. Document Number: 38-06082 Rev. *S Page 6 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Figure 4. FullFlex36 SDR 256-ball BGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A DQ32L DQ30L DQ28L DQ26L DQ24L DQ22L DQ20L DQ18L DQ18R DQ20R DQ22R DQ24R DQ26R DQ28R DQ30R DQ32R B DQ33L DQ31L DQ29L DQ27L DQ25L DQ23L DQ21L DQ19L DQ19R DQ21R DQ23R DQ25R DQ27R DQ29R DQ31R DQ33R C DQ34L DQ35L RETL INTL CQ1L CQ1L DNU TRST MRST ZQ0R[14] CQ1R CQ1R INTR RETR DQ35R DQ34R D A0L A1L WRPL VREFL FTSELL LOWSPDL VSS VTTL VTTL VSS LOWSPDR FTSELR VREFR WRPR A1R A0R E A2L A3L CE0L CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CE1R CE0R A3R A2R F A4L A5L CNTINTL BE3L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE3R CNTINTR A5R A4R G A6L A7L BUSYL BE2L ZQ0L[14] VSS VSS VSS VSS VSS VSS VDDIOR BE2R BUSYR A7R A6R H A8L A9L CL VTTL VCORE VSS VSS VSS VSS VSS VSS VCORE VTTL CR A9R A8R J A10L A11L VSS PORTSTD1L VCORE VSS VSS VSS VSS VSS VSS VCORE PORTSTD1R VSS A11R A10R K A12L A13L OEL BE1L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE1R OER A13R A12R L A14L A15L ADSL BE0L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE0R ADSR A15R A14R M A16L[17] A17L[16] R/WL CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CQENR R/WR A17R[16] A16R[17] N A18L[15] DNU CNT/MSKL VREFL PORTSTD0L READYL DNU VTTL VTTL DNU VREFR CNT/MSKR DNU A18R[15] P DQ16L DQ17L CNTENL CNTRSTL CQ0L CQ0L TCK TMS TDO TDI CQ0R CQ0R CNTRSTR CNTENR DQ17R DQ16R R DQ15L DQ13L DQ11L DQ9L DQ7L DQ5L DQ3L DQ1L DQ1R DQ3R DQ5R DQ7R DQ9R DQ11R DQ13R DQ15R T DQ14L DQ12L DQ10L DQ8L DQ6L DQ4L DQ2L DQ0L DQ0R DQ2R DQ4R DQ6R DQ8R DQ10R DQ12R DQ14R READYR PORTSTD0R Notes 14. Leave this ball unconnected to disable VIM. 15. Leave this ball unconnected for CYD09S36V18 and CYD02S36V18. 16. Leave this ball unconnected for CYD02S36V18. 17. Leave this ball unconnected for CYD02S36V18. Document Number: 38-06082 Rev. *S Page 7 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Figure 5. FullFlex18 SDR 256-ball BGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A DNU DNU DNU DQ17L DQ16L DQ13L DQ12L DQ9L DQ9R DQ12R DQ13R DQ16R DQ17R DNU DNU DNU B DNU DNU DNU DNU DQ15L DQ14L DQ11L DQ10L DQ10R DQ11R DQ14R DQ15R DNU DNU DNU DNU C DNU DNU RETL INTL CQ1L CQ1L DNU TRST MRST ZQ0R[18] CQ1R CQ1R INTR RETR DNU DNU D A0L A1L WRPL VREFL FTSELL LOWSPDL VSS VTTL VTTL VSS LOWSPDR FTSELR VREFR WRPR A1R A0R E A2L A3L CE0L CE1L VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CE1R CE0R A3R A2R F A4L A5L CNTINTL DNU VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR DNU CNTINTR A5R A4R G A6L A7L BUSYL DNU ZQ0L[18] VSS VSS VSS VSS VSS VSS VDDIOR DNU BUSYR A7R A6R H A8L A9L CL VTTL VCORE VSS VSS VSS VSS VSS VSS VCORE VTTL CR A9R A8R J A10L A11L VSS PORTSTD1L VCORE VSS VSS VSS VSS VSS VSS VCORE PORTSTD1R VSS A11R A10R K A12L A13L OEL BE1L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE1R OER A13R A12R L A14L A15L ADSL BE0L VDDIOL VSS VSS VSS VSS VSS VSS VDDIOR BE0R ADSR A15R A14R M A16L A17L R/WL CQENL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR CQENR R/WR A17R A16R N A18L[20] A19L[19] CNT/MSKL VREFL PORTSTD0L READYL DNU VTTL VTTL DNU READYR PORTSTD0R VREFR CNT/MSKR A19R[19] A18R[20] P DNU DNU CNTENL CNTRSTL CQ0L CQ0L TCK TMS TDO TDI CQ0R CQ0R CNTRSTR CNTENR DNU DNU R DNU DNU DNU DNU DQ6L DQ5L DQ2L DQ1L DQ1R DQ2R DQ5R DQ6R DNU DNU DNU DNU T DNU DNU DNU DQ8L DQ7L DQ4L DQ3L DQ0L DQ0R DQ3R DQ4R DQ7R DQ8R DNU DNU DNU Notes 18. Leave this ball unconnected to disable VIM. 19. Leave this ball unconnected for CYD09S18V18. 20. Leave this ball unconnected for CYD04S18V18. Document Number: 38-06082 Rev. *S Page 8 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Selection Guide –200 –167 Unit fMAX[22] Parameter 200 167 MHz Maximum access time (clock to data) 3.3 4.0 ns [21] Typical operating current ICC 800 Typical standby current for ISB3 (both ports CMOS level) 210[21] [21] 700 mA 210[21] mA Pin Definitions Left Port Right Port Description [23] A[20:0]L A[20:0]R Address inputs. DQ[71:0]L DQ[71:0]R Data bus input and output.[24] BE[7:0]L BE[7:0]R Byte select inputs.[25] Asserting these signals enables read and write operations to the corresponding bytes of the memory array. BUSYL BUSYR Port busy output. When there is an address match and both chip enables are active for both ports, an external BUSY signal is asserted on the fifth clock cycles from when the collision occurs. CL CR Clock signal. Maximum clock input rate is fMAX. CE0L CE0R Active LOW chip enable input. CE1L CE1R Active HIGH chip enable input. CQENL CQENR Echo clock enable input. Assert HIGH to enable echo clocking on respective port. CQ0L CQ0R Echo clock signal output for DQ[35:0] for FullFlex72 devices. Echo clock signal output for DQ[17:0] for FullFlex36 devices. Echo clock signal output for DQ[8:0] for FullFlex18 devices. CQ0L CQ0R Inverted echo clock signal output for DQ[35:0] for FullFlex72 devices. Inverted echo clock signal output for DQ[17:0] for FullFlex36 devices. Inverted echo clock signal output for DQ[8:0] for FullFlex18 devices. CQ1L CQ1R Echo clock signal output for DQ[71:36] for FullFlex72 devices. Echo clock signal output for DQ[35:18] for FullFlex36 devices. Echo clock signal output for DQ[17:9] for FullFlex18 devices. CQ1L CQ1R Inverted echo clock signal output for DQ[71:36] for FullFlex72 devices. Inverted echo clock signal output for DQ[35:18] for FullFlex36 devices. Inverted echo clock signal output for DQ[17:9] for FullFlex18 devices. ZQ[1:0]L ZQ[1:0]R VIM output impedance matching input.[26] To use, connect a calibrating resistor between ZQ and ground. The resistor must be five times larger than the intended line impedance driven by the dual port. Assert HIGH or leave DNU to disable VIM. OEL OER Output enable input. This asynchronous signal must be asserted LOW to enable the DQ data pins during read operations. INTL INTR Mailbox interrupt flag output. The mailbox permits communications between ports. The upper two memory locations are used for message passing. INTL is asserted LOW when the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox. Notes 21. For 18 Mbit x72 commercial configuration only; refer to Electrical Characteristics on page 19 for complete information. 22. SDR mode with two pipelined stages. 23. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits. The CYD02S36V18 has 16 address bits. 24. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines. 25. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte enables. 26. The pin ZQ[1] is applicable only for 36 Mbit devices. This pin is DNU for 18 Mbit and lower density devices. Document Number: 38-06082 Rev. *S Page 9 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Pin Definitions (continued) Left Port LowSPDL Right Port LowSPDR Description Port low speed select input. Assert this pin LOW to disable the DLL. In flow through mode, this pin needs to be asserted low. PORTSTD[1:0]L[27, PORTSTD[1:0]R[27, Port clock/Address/Control/Data/Echo clock/I/O standard select input. Assert these pins 28] 28] R/WL R/WR Read/Write enable input. Assert this pin LOW to write to, or HIGH to read from the dual port memory array. READYL READYR Port DLL ready output. This signal is asserted LOW when the DLL and variable impedance matching circuits complete calibration. This is a wired OR capable output. CNT/MSKL CNT/MSKR Port counter/Mask select input. Counter control input. ADSL ADSR Port counter address load strobe input. Counter control input. CNTENL CNTENR Port counter enable input. Counter control input. CNTRSTL CNTRSTR Port counter reset input. Counter control input. CNTINTL CNTINTR Port counter interrupt output. This pin is asserted LOW one cycle before the unmasked portion of the counter is incremented to all “1s”. WRPL WRPR Port counter wrap input. When the burst counter reaches the maximum count, on the next counter increment WRP is set LOW to load the unmasked counter bits to 0. It is set HIGH to load the counter with the value stored in the mirror register. RETL RETR Port counter retransmit input. Assert this pin LOW to reload the initial address for repeated access to the same segment of memory. VREFL[28] VREFR[28] Port external HSTL I/O reference input. This pin is left DNU when HSTL is not used. VDDIOL VDDIOR Port data I/O power supply. FTSELL FTSELR Port flow through mode select input. Assert this pin LOW to select flow through mode. Assert this pin HIGH to select Pipelined mode. LOW/LOW for LVTTL, LOW/HIGH for HSTL, HIGH/LOW for 2.5 V LVCMOS, and HIGH/HIGH for 1.8 V LVCMOS, respectively. These pins are driven by VTTL referenced levels. MRST Master reset input. MRST is an asynchronous input signal and affects both ports. Asserting MRST LOW performs all of the reset functions as described in the text. A MRST operation is required at power up. This pin is driven by a VDDIOL referenced signal. TMS JTAG test mode select input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. Operation for LVTTL or 2.5 V LVCMOS. TDI JTAG test data input. Data on the TDI input is shifted serially into selected registers. Operation for LVTTL or 2.5 V LVCMOS. TRST JTAG reset input. Operation for LVTTL or 2.5 V LVCMOS. TCK JTAG test clock input. Operation for LVTTL or 2.5 V LVCMOS. TDO JTAG test data output. TDO transitions occur on the falling edge of TCK. TDO is normally tri-stated except when captured data is shifted out of the JTAG TAP. Operation for LVTTL or 2.5 V LVCMOS. VSS Ground inputs. VCORE Device core power supply. VTTL LVTTL power supply. Notes 27. PORTSTD[1:0]L and PORTSTD[1:0]R have internal pull-down resistors. 28. HSTL support and the corresponding tests support has been removed from the device from WW1830. This change does not impact any other functionality. Document Number: 38-06082 Rev. *S Page 10 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Functional Overview Whenever the operating frequency is altered beyond the Clock Input Cycle to Cycle Jitter specification, reset the DLL, followed by 1024 clocks before any valid operation. Selectable I/O Standard The FullFlex device families offer the option to choose one of the four port standards for the device. Each port independently selects standards from single-ended HSTL class I, single-ended LVTTL, 2.5 V LVCMOS, or 1.8 V LVCMOS. The selection of the standard is determined by the PORTSTD pins for each port. These pins must be connected to an LVTTL power suppy. This determines the input clock, address, control, data, and Echo clock standard for each port as shown in Table 1. Table 1. Port Standard Selection PORTSTD1 PORTSTD0 I/O Standard VSS VSS LVTTL VSS VTTL HSTL VTTL VSS 2.5 V LVCMOS VTTL VTTL 1.8 V LVCMOS LowSPD pins are used to reset the DLLs for a single port independent of all other circuitry. MRST is used to reset all DLLs on the chip. For more information on DLL lock and reset time, see Master Reset on page 18. Echo Clocking As the speed of data increases, on-board delays caused by parasitics make it extremely difficult to provide accurate clock trees. To counter this problem, the FullFlex families incorporate Echo Clocks. Echo Clocks are enabled on a per port basis. The dual port receives input clocks that are used to clock in the address and control signals for a read operation. The dual port retransmits the input clocks relative to the data output. The buffered clocks are provided on the CQ1/CQ1 and CQ0/CQ0 outputs. Each port has a pair of Echo clocks. Each clock is associated with half the data bits. The output clock matches the corresponding ports I/O configuration. To enable echo clock outputs, tie CQEN HIGH. To disable echo clock outputs, tie CQEN LOW. Clocking Separate clocks synchronize the operations on each port. Each port has one clock input C. In this mode, all the transactions on the address, control, and data are on the C rising edge. All transactions on the address, control, data input, output, and byte enables occur on the C rising edge. Table 2. Data Pin Assignment Data Out Echo Clock BE Pin Name Data Pin Name BE[7] DQ[71:63] BE[6] DQ[62:54] BE[5] DQ[53:45] BE[4] DQ[44:36] BE[3] DQ[35:27] BE[2] DQ[26:18] BE[1] DQ[17:9] BE[0] DQ[8:0] Selectable Pipelined or Flow through Mode To meet data rate and throughput requirements, the FullFlex families offer selectable pipelined or flow through mode. Echo clocks are not supported in flow through mode and the DLL must be disabled. Flow through mode is selected by the FTSEL pin. Strapping this pin HIGH selects pipelined mode. Strapping this pin LOW selects flow through mode. DLL The FullFlex familes of devices have an on-chip DLL. Enabling the DLL reduces the clock to data valid (tCD) time enabling more setup time for the receiving device. In flow through mode, the DLL must be disabled. This is selectable by strapping LowSPD low. Document Number: 38-06082 Rev. *S Figure 6. SDR Echo Clock Delay Input Clock Echo Clock Deterministic Access Control Deterministic Access Control is provided for ease of design. The circuitry detects when both ports access the same location and provides an external BUSY flag to the port on which data is corrupted. The collision detection logic saves the address in conflict (Busy Address) to a readable register. In the case of multiple collisions, the first busy address is written to the busy address register. If both ports access the same location at the same time and only one port is doing a write, if tCCS is met, then the data written to and read from the address is valid data. For example, if the right port is reading and the left port is writing and the left ports clock meets tCCS, then the data read from the address by the right port is the old data. In the same case, if the right ports clock meets tCCS, then the data read out of the address from the right port is the new data. In the above case, if tCCS is violated by the either ports clock with respect to the other port and the right port gets the external BUSY flag, the data from the right port is corrupted. Table 3 on page 12 shows the tCCS timing that must be met to guarantee the data. Table 4 on page 12 shows that, in the case of the left port writing and the right port reading, when an external BUSY flag is asserted on the right port, the data read out of the device is not guaranteed. The value in the busy address register is read back to the address lines. The required input control signals for this function are shown in Table 7 on page 14. The value in the busy address register is read out to the address lines tCA after the same Page 11 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 amount of latency as a data read operation. After an initial address match, the BUSY flag is asserted and the address under contention is saved in the busy address register. All the following address matches enable to generate the BUSY flag. However, none of the addresses are saved into the busy address register. When a busy readback is performed, the address of the first match that happens at least two clocks cycles after the busy readback is saved into the busy address register. Table 3. tCCS Timing for All Operating Modes Port A - Early Arriving Port Port B - Late Arriving Port Mode Active Edge Mode Active Edge SDR C SDR C tCCS Unit C Rise to Opposite C Rise Setup Time for Non Corrupt Data tCYC(min) – 0.5 ns Table 4. Deterministic Access Control Logic Left Port Right Port Left Clock Right Clock BUSYL BUSYR Read Read X X H H No collision Write Read > tCCS 0 H H Read OLD data 0 > tCCS H H Read NEW data < tCCS 0 H H Read OLD data H L Data not guaranteed H H Read NEW data H L Data Not guaranteed 0 Read Write > tCCS 0 H H Read NEW data 0 > tCCS H H Read OLD data < tCCS 0 H H Read NEW data L H Data Not guaranteed H H Read OLD data L H Data not guaranteed 0 Write Write < tCCS Description < tCCS 0 > –tCCS & < tCCS L L Array data corrupted 0 > tCCS L H Array stores right port data > tCCS 0 H L Array stores left port data Variable Impedance Matching Each port contains a variable impedance matching circuit to set the impedance of the I/O driver to match the impedance of the on-board traces. The impedance is set for all outputs except JTAG and is done by port. To take advantage of the VIM feature, connect a calibrating resistor (RQ) that is five times the value of the intended line impedance from the ZQ[1:0][29] pin to VSS. The output impedance is then adjusted to account for drifts in supply voltage and temperature every 1024 clock cycles. If a port’s clock is suspended, the VIM circuit retains its last setting until the clock is restarted. On restart, it then resumes periodic adjustment. In the case of a significant change in device temperature or supply voltage, recalibration happens every 1024 clock cycles. A master reset initializes the VIM circuitry. Table 5 shows the VIM parameters and Table 6 describes the VIM operation modes. To disable VIM, connect the ZQ pin to VDDIO of the relative supply for the I/Os before a Master Reset. Table 5. Variable Impedance Matching Parameters Parameter RQ value Output impedance Reset time Update time Min 100 20 – – Max 275 55 1024 1024 Unit   Cycles Cycles Tolerance ±2% ±15% – – Table 6. Variable Impedance Matching Operation RQ Connection Output Configuration 100 –275  to VSS Output driver impedance = RQ/5 ± 15% at Vout = VDDIO/2 ZQto VDDIO VIM disabled. Rout < 20 at Vout = VDDIO/2 Note 29. The pin ZQ[1] is applicable only for 36 Mbit devices. This pin is DNU for 18 Mbit and lower density devices. Document Number: 38-06082 Rev. *S Page 12 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Address Counter and Mask Register Operations [30] Counter Load Operation [30] Each port of the FullFlex family contains a programmable burst address counter. The burst counter contains four registers: a counter register, a mask register, a mirror register, and a busy address register. For both non-burst and burst read or write accesses, the external address is loaded through counter load operation as shown in Table 7 on page 14. The address counter and mirror registers are loaded with the address value presented on the address lines. This value ranges from 0 to 1FFFFF. The counter register contains the address used to access the RAM array. It is changed only by the master reset (MRST), counter reset, counter load, retransmit, and counter increment operations. The mask register value affects the counter increment and counter reset operations by preventing the corresponding bits of the counter register from changing. It also affects the counter interrupt output (CNTINT). The mask register is only changed by mask reset, mask load, and MRST. The mask load operation loads the value of the address bus into the mask register. The mask register defines the counting range of the counter register. The mask register is divided into two or three consecutive regions. Zero or more 0s define the masked region and one or more 1s define the unmasked portion of the counter register. The counter register may be divided up to three regions. The region containing the least significant bits must be no more than two 0s. Bits one and zero may be 10 respectively, masking the least significant counter bit and causing the counter to increment by two instead of one. If bits one and zero are 00, the two least significant bits are masked and the counter increments by four instead of one. For example, in the case of a 256 K × 72 configuration, a mask register value of 003FC divides the mask register into three regions. With bit 0 being the least significant bit and bit 17 being the most significant bit, the two least significant bits are masked, the next eight bits are unmasked, and the remaining bits are masked. The mirror register reloads a counter register on retransmit operations (see Retransmit on page 15) and wrap functions (see Counter Interrupt on page 15 below). The last value loaded into the counter register is stored in the mirror register. The mirror register is only changed by master reset (MRST), counter reset, and counter load. Table 7 on page 14 summarizes the operations of these registers and the required input control signals. All signals except MRST are synchronized to the ports clock. Mask Load Operation [30] The mask register is loaded with the address value presented on the address bus. This value ranges from 0 to 1FFFFF though not all values permit correct increment operations. Permitted values are in the form of 2n–1, 2n–2, or 2n–4. The counter register is only segmented up to three regions. From the most significant bit to the least significant bit, permitted values have zero or more 0s, one or more 1s, and the least significant two bits are 11, 10, or 00. Thus 1FFFFE, 07FFFF, and 003FFC are permitted values but 02FFFF, 003FFA, and 07FFE4 are not. Counter Readback Operation The internal value of the counter register is read out on the address lines. The address is valid tCA after the selected number of latency cycles configured by FTSEL. The data bus (DQ) is tri-stated on the cycle that the address is presented on the address lines. Figure 7 on page 16 shows a block diagram of this logic. Mask Readback Operation The internal value of the mask register is read out on the address lines. The address is valid tCA after the selected number of latency cycles configured by FTSEL. The data bus (DQ) is tri-stated on the cycle that the address is presented on the address lines. Figure 7 on page 16 shows a block diagram of the operation. Counter Reset Operation All unmasked bits of the counter and mirror registers are reset to ‘0’. All masked bits remain unchanged. A mask reset followed by a counter reset resets the counter and mirror registers to 00000. Mask Reset Operation The mask register is reset to all 1s, that unmasks every bit of the burst counter. Note 30. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits. The CYD02S36V18 has 16 address bits. Document Number: 38-06082 Rev. *S Page 13 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Table 7. Burst Counter and Mask Register Control Operations The burst counter and mask register control operation for any port follows. [31, 32] C MRST CNTRST CNT/MSK CNTEN ADS RET Operation Description X L X X X X X Master reset Reset address counter to all 0s, mask register to all 1s, and busy address to all 0s. H L H X X X Counter reset Reset counter and mirror unmasked portion to all 0s. H L L X X X Mask reset Reset mask register to all 1s. H H H L L X Counter load for Load burst counter and mirror with external burst/external address address value presented on address lines. load for non-burst H H L L L X Mask load Load mask register with value presented on the address lines. H H H L H L Retransmit Load counter with value in the mirror register. H H H L H H Counter increment Internally increment address counter value. H H H H H H Counter hold Constantly hold the address value for multiple clock cycles. H H H H L H Counter readback Read out counter internal value on address lines. H H L H L H Mask readback Read out mask register value on address lines. H H L H H L Busy address readback Read out first busy address after last busy address readback. H H L L H X Reserved H H L H L L Reserved H H L H H H Reserved H H H H L L Reserved H H H H H L Reserved Notes 31. “X” = Don’t Care, “H” = HIGH, “L” = LOW. 32. Counter operation and mask register operation is independent of chip enables. Document Number: 38-06082 Rev. *S Page 14 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Increment Operation[33] Counter Interrupt After the address counter is initially loaded with an external address, the counter can internally increment the address value and address the entire memory array. Only the unmasked bits of the counter register are incremented. For a counter bit to change, the corresponding bit in the mask register must be 1. If the two least significant bits of the mask register are 11, the burst counter increments by one. If the two least significant bits are 10, the burst counter increments by two, and if they are 00, the burst counter increments by four. If all unmasked counter bits are incremented to 1 and WRP is deasserted, the next increment l wraps the counter back to the initially loaded value. The cycle before the increment that results in all unmasked counter bits to become 1s, a counter interrupt flag (CNTINT) is asserted if the counter is incremented again. This increment causes the counter to reach its maximum value and the next increment returns the counter register to its initial value that was stored in the mirror register if WRP is deasserted. If WRP is asserted, the unmasked portion of the counter is filled with 0 instead. The example shown in Figure 8 on page 17 shows an example of the CYDD36S18V18 device with the mask register loaded with a mask value of 00007F unmasking the seven least significant bits. Setting the mask register to this value enables the counter to access the entire memory space. The address counter is then loaded with an initial value of 000005 assuming WRP is deasserted. The masked bits, the seventh address through the twenty-first address, do not increment in an increment operation. The counter address starts at address 000005 and increments its internal address value until it reaches the mask register value of 00007F. The counter wraps around the memory block to location 000005 at the next count. CNTINT is issued when the counter reaches the maximum –1 count. The counter interrupt (CNTINT) is asserted LOW one clock cycle before an increment operation that results in the unmasked portion of the counter register being all 1s. It is deasserted by counter reset, counter load, counter increment, mask reset, mask load, and MRST. Hold Operation The value of all three registers is constantly maintained unchanged for an unlimited number of clock cycles. This operation is useful in applications where wait states are needed or when address is available a few cycles ahead of data in a shared bus interface. Counting by Two When the two least significant bits of the mask register are 10, the counter increments by two. Counting by Four When the two least significant bits of the mask register are 00, the counter increments by four. Mailbox Interrupts Use the upper two memory locations for message passing and permit communications between ports. Table 8 on page 17 shows the interrupt operation for both ports. The highest memory location is the mailbox for the right port and the maximum address – 1 is the mailbox for the left port. When one port writes to the other port’s mailbox, the INT flag of the port that the mailbox belongs to is asserted LOW. The INT flag remains asserted until the mailbox location is read by the other port. When a port reads its mailbox, the INT flag is deasserted high after one cycle of latency with respect to the input clock of the port to which the mailbox belongs and is independent of OE. As shown in Table 8 on page 17, to set the INTR flag, a write operation by the left port to address 1FFFFF asserts INTR LOW. A valid read of the 1FFFFF location by the right port resets INTR HIGH after one cycle of latency with respect to the right port’s clock. You must activate at least one byte enable to set or reset the mailbox interrupt. Retransmit Retransmit enables repeated access to the same block of memory without the need to reload the initial address. An internal mirror register stores the address counter value last loaded. While RET is asserted low, the counter continues to wrap back to the value in the mirror register independent of the state of WRP. Note 33. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits. The CYD02S36V18 has 16 address bits. Document Number: 38-06082 Rev. *S Page 15 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Figure 7 shows the counter, mask, and mirror logic block diagram. [34] Figure 7. Counter, Mask, and Mirror Logic Block Diagram CNT/MSK CNTEN Decode Logic A CNTRST RET MRST A Mask Register Counter/ Address Register Address Decode RAM Array C From Address Lines Load/Increment 20 Mirror 1 From Mask Register From Mask From Counter Increment Logic Wrap 20 20 To Readback and Address Decode 0 0 20 Counter 1 20 20 +1 +2 +4 Bit 0 and 1 Wrap Detect 1 Wrap 0 1 20 To Counter 0 Note 34. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits. The CYD02S36V18 has 16 address bits. Document Number: 38-06082 Rev. *S Page 16 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Figure 8 shows the programmable counter-mask operation with WRP deasserted. [38, 40] Figure 8. Programmable Counter-Mask Register Operation with WRP deasserted CNTINT Example: Load Counter-Mask H Register = 00007F 0 0 0s 220 219 0 1 1 H X X Xs 220 219 Max Address Value L H 1 1 1 X Unmasked Address 0 0 0 0 1 0 X X Xs X 1 1 1 1 1 Mask Register LSB 1 6 5 4 3 2 1 0 27 2 2 2 2 2 2 2 220 219 Max + 1 Address Value 1 6 5 4 3 2 1 0 27 2 2 2 2 2 2 2 Masked Address Load Address Counter = 000005 1 1 1 Address Counter LSB 6 5 4 3 2 1 0 27 2 2 2 2 2 2 2 X X Xs 220 219 X 0 0 0 0 1 0 1 6 5 4 3 2 1 0 27 2 2 2 2 2 2 2 Table 8. Interrupt Operation Example Table 8 shows the interrupt operation example. [35, 36, 37, 39, 40] Function Left Port Right Port R/WL CEL A0L–20L INTL R/WR CER A0R–20R INTR Set Right INTR Flag L L Max Address X X X X L Reset Right INTR Flag X X X X H L Max Address H Set Left INTL Flag X X X L L L Max Address–1 X Reset Left INTL Flag H L Max Address–1 H X X X X Notes 35. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single read operation, CE only needs to be asserted once at the rising edge of the C and is deasserted after that. Data is out after the following C edge and is tri-stated after the next C edge. 36. OE is “Don’t Care” for mailbox operation. 37. At least one of BE0, BE1, BE2, BE3, BE4, BE5, BE6, or BE7 must be LOW. 38. The “X” in this diagram represents the counter’s upper bits. 39. “X” = Don’t Care, “H” = HIGH, “L” = LOW. 40. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits. The CYD02S36V18 has 16 address bits. Document Number: 38-06082 Rev. *S Page 17 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Master Reset The FullFlex family of Dual Ports undergoes a complete reset when MRST is asserted. MRST must be driven by VDDIOL referenced levels. The MRST is asserted asynchronously to the clocks and must remain asserted for at least tRS. When asserted MRST deasserts READY, initializes the internal burst counters, internal mirror registers, and internal busy addresses to zero. It also initializes the internal mask register to all 1s. All mailbox interrupts (INT), busy address outputs (BUSY), and burst counter interrupts (CNTINT) are deasserted upon master reset. Additionally, do not release MRST until all power supplies including VREF are fully ramped and all port clocks and mode select inputs (LOWSPD, ZQ, CQEN, FTSEL, and PORTSTD) are valid and stable. This begins calibration of the DLL and VIM circuits. READY is asserted within 1024 clock cycles. READY is a wired OR capable output with a strong pull up and weak pull down. Up to four outputs may be connected together. For faster pull down of the signal, connect a 250 Ohm resistor to VSS. If the DLL and VIM circuits are disabled for a port, the port is operational within five clock cycles. However, the READY is asserted within 160 clock cycles. Table 9. JTAG IDCODE Register Definitions Part Number Value CYD36S72V18 512K × 72 CYD36S36V18 1024K × 36 CYD36S18V18 2048K × 18 0C024069h CYD18S72V18 256K × 72 0C025069h CYD18S36V18 512K × 36 0C026069h CYD18S18V18 1024K × 18 0C027069h CYD09S72V18 128K × 72 0C028069h CYD09S36V18 256K × 36 0C029069h CYD09S18V18 512K × 18 0C02A069h CYD02S36V18 64K × 36 0C030069h 0C026069h (× 2) 0C023069h Table 10. Scan Registers Sizes IEEE 1149.1 Serial Boundary Scan (JTAG) The FullFlex families incorporate an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic levels depending on the VTTL power supply. It is composed of four input connections and one output connection required by the test logic defined by the standard. Configuration Register Name Instruction Bit Size 4 Bypass 1 Identification 32 Boundary Scan n[41] Table 11. Instruction Identification Codes Instruction EXTEST Code 0000 Description Captures the input and output ring contents. Places the BSR between the TDI and TDO. BYPASS 1111 Places the BYR between TDI and TDO. IDCODE 1011 Loads the IDR with the vendor ID code and places the register between TDI and TDO. HIGHZ 0111 Places BYR between TDI and TDO. Forces all FullFlex72 and FullFlex36 output drivers to a High Z state. CLAMP 0100 Controls boundary to 1 or 0. Places BYR between TDI and TDO. SAMPLE/PRELOAD 1000 Captures the input and output ring contents. Places BSR between TDI and TDO. RESERVED All other codes Other combinations are reserved. Do not use other than the mentioned combinations. Note 41. Details of the boundary scan length is found in the BSDL file for the device. Document Number: 38-06082 Rev. *S Page 18 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Maximum Ratings Operating Range Range Ambient Temperature VCORE Storage temperature .............................. –65 °C to + 150 °C Commercial 0 °C to +70 °C Ambient temperature with power applied .................................. –55 °C to + 125 °C 1.8 V  100 mV 1.5 V 80 mV Industrial –40 °C to +85 °C 1.8 V  100 mV 1.5 V 80 mV Exceeding maximum ratings may impair the useful life of the device. User guidelines are not tested. Supply voltage to ground potential .............–0.5 V to + 4.1 V DC voltage applied to outputs in high Z State .................................. –0.5 V to VDDIO + 0.5 V Power Supply Requirements DC input voltage .............................. –0.5 V to VDDIO + 0.5 V Output current into outputs (LOW) ............................ 20 mA Static discharge voltage (JEDEC JESD8-6, JESD8-B) ................................. > 2200 V Latch-up current .................................................... > 200 mA Min Typ Max LVTTL VDDIO 3.0 V 3.3 V 3.6 V 2.5 V LVCMOS VDDIO 2.3 V 2.5 V 2.7 V HSTL VDDIO[44] 1.4 V 1.5 V 1.9 V 1.8 V LVCMOS VDDIO 1.7 V 1.8 V 1.9 V 3.3 V VTTL 3.0 V 3.3 V 3.6 V 2.5 V VTTL 2.3 V 2.5 V 2.7 V HSTL VREF 0.68 V 0.75 V 0.95 V Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL Min All Speed Bins Typ Max LVTTL 2.4[42] – – V HSTL (DC)[43] HSTL (AC)[43] 2.5 V LVCMOS 1.8 V LVCMOS VDDIO – 0.4[42] VDDIO – 0.5[42] 1.7[42] VDDIO – 0.45[42] – – – – – – – – V V V V LVTTL – – 0.4[42] V HSTL(DC)[43] HSTL (AC)[43] 2.5 V LVCMOS 1.8 V LVCMOS – – – – – – – – Input HIGH voltage LVTTL HSTL(DC)[43] 2.5 V LVCMOS 1.8 V LVCMOS 2 VREF + 0.1 1.7 0.65 × VDDIO – – – – 0.4[42] 0.5[42] 0.7[42] 0.45[42] VDDIO + 0.3 VDDIO + 0.3 V V V V V V V V Input LOW voltage LVTTL HSTL(DC)[43] 2.5 V LVCMOS 1.8 V LVCMOS –0.3 –0.3 – – – – – – 0.8 VREF – 0.1 0.7 0.35 × VDDIO V V V Description Output HIGH voltage (VDDIO = Min, IOH = –8 mA) (VDDIO = Min, IOH = –4 mA) (VDDIO = Min, IOH = –4 mA) (VDDIO = Min, IOH = –6 mA) (VDDIO = Min, IOH = –4 mA) Output HIGH voltage (VDDIO = Min, IOL = 8 mA) (VDDIO = Min, IOL = 4 mA) (VDDIO = Min, IOL = 4 mA) (VDDIO = Min, IOL = 6 mA) (VDDIO = Min, IOL = 4 mA) Configuration Unit V Notes 42. These parameters are met with VIM disabled. 43. The DC specifications are measured under steady state conditions. The AC specifications are measured while switching at speed. AC VIH/VIL in HSTL mode are measured with 1 V/ns input edge rates. 44. HSTL Support and the corresponding tests support has been removed from the device from WW1830. No other functionality is impacted with this change Document Number: 38-06082 Rev. *S Page 19 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Electrical Characteristics (continued) Over the Operating Range Parameter READY VOH READY VOL IOZ IIX1 IIX2 IIX3 Description Output HIGH voltage (VDDIO = Min, IOH = –24 mA) (VDDIO = Min, IOH = –12 mA) (VDDIO = Min, IOH = –12 mA) (VDDIO = Min, IOH = –15 mA) (VDDIO = Min, IOH = –12 mA) Output HIGH voltage (VDDIO = Min, IOL = 0.12 mA) (VDDIO = Min, IOL = 0.12 mA) (VDDIO = Min, IOL = 0.12 mA) (VDDIO = Min, IOL = 0.15 mA) (VDDIO = Min, IOL = 0.08 mA) Output leakage current Input leakage current except TDI, TMS, MRST, PORTSTD Input leakage current TDI, TMS, MRST Input leakage current PORTSTD Configuration All Speed Bins Unit Min Typ Max LVTTL 2.7[45] – – V HSTL(DC)[46, 47] HSTL (AC)[46. 47] 2.5 V LVCMOS 1.8 V LVCMOS VDDIO – 0.4[45] VDDIO – 0.5[45] 2.0[45] VDDIO – 0.45[45] – – – – – – – – V V V V LVTTL – – 0.4[45] V HSTL(DC)[46, 47] – – 0.4[45] V – – – –10 – – – – 0.5[45] 0.7[45] 0.45[45] 10 V V V A –10 – 10 A –300 – 10 A –10 – 300 A (AC)[46, 47] HSTL 2.5 V LVCMOS 1.8 V LVCMOS Notes 45. These parameters are met with VIM disabled. 46. The DC specifications are measured under steady state conditions. The AC specifications are measured while switching at speed. AC VIH/VIL in HSTL mode are measured with 1 V/ns input edge rates. 47. HSTL Support and the corresponding tests support has been removed from the device from WW1830. No other functionality is impacted with this change Document Number: 38-06082 Rev. *S Page 20 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Electrical Characteristics Over the Operating Range Parameter Description Configuration 512K × 72 1024K × 36 2048K × 18 256K × 72 ICC Operating current (VCORE = Max, IOUT = 0 mA) outputs disabled 512K × 36 1024K × 18 128K × 72 256K × 36 512K × 18 64K × 36 512K × 72 1024K × 36 2048K × 18 256K × 72 ISB1 Standby current (both ports TTL Level) CEL and CER  VIH, f = fMAX 512K × 36 1024K × 18 128K × 72 256K × 36 512K × 18 64K × 36 Document Number: 38-06082 Rev. *S -200 -167 Typ Max Unit Typ Max Commercial 1440 1800 1280 1620 mA Industrial – – 1330 1730 mA Commercial 1180 1500 1050 1350 mA Industrial – – 1110 1470 mA Commercial 1130 1430 1000 1290 mA Industrial – – 1060 1410 mA Commercial 800 980 700 880 mA Industrial 820 1030 730 930 mA Commercial 640 800 570 720 mA Industrial 670 860 590 780 mA Commercial 610 770 540 690 mA Industrial 640 830 570 750 mA Commercial 640 790 560 700 mA Industrial 660 830 580 740 mA Commercial 540 640 470 570 mA Industrial 550 670 490 600 mA Commercial 550 660 480 580 mA Industrial 570 690 500 610 mA Commercial – – – – mA Industrial – – – – mA Commercial 1000 1250 920 1160 mA Industrial – – 970 1260 mA Commercial 910 1140 820 1050 mA Industrial – – 880 1160 mA Commercial 890 1110 810 1030 mA Industrial – – 860 1140 mA Commercial 500 630 460 580 mA Industrial 530 680 490 630 mA Commercial 460 570 410 530 mA Industrial 480 630 440 580 mA Commercial 450 560 410 520 mA Industrial 470 610 430 570 mA Commercial 400 490 360 450 mA Industrial 420 540 380 490 mA Commercial 380 440 340 400 mA Industrial 390 470 360 430 mA Commercial 390 460 350 410 mA Industrial 410 480 370 440 mA Commercial – – – – mA Industrial – – – – mA Page 21 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Electrical Characteristics (continued) Over the Operating Range Parameter Description Configuration 512K × 72 1024K × 36 2048K × 18 256K × 72 ISB2 Standby current (one port TTL or CMOS level) CEL | CER  VIH, f = fMAX 512K × 36 1024K × 18 128K × 72 256K × 36 512K × 18 64K × 36 Document Number: 38-06082 Rev. *S Commercial -200 -167 Typ Max Typ Max 1300 1570 1160 1410 Unit mA Industrial – – 1210 1520 mA Commercial 1090 1330 980 1210 mA Industrial – – 1030 1330 mA Commercial 1040 1270 930 1160 mA Industrial – – 980 1270 mA Commercial 650 790 580 710 mA Industrial 680 840 610 760 mA Commercial 550 670 490 610 mA Industrial 570 730 520 670 mA Commercial 520 640 470 580 mA Industrial 550 690 490 640 mA Commercial 520 630 460 560 mA Industrial 550 670 480 610 mA Commercial 460 530 400 470 mA Industrial 480 560 430 500 mA Commercial 460 530 410 480 mA Industrial 480 560 430 510 mA Commercial – – – – mA Industrial – – – – mA Page 22 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Electrical Characteristics Over the Operating Range Parameter Description 512K × 72 1024K × 36 2048K × 18 256K × 72 Standby current (both ports CMOS level) CEL and CER  VCORE – 0.2 V, f = 0 ISB3 All Speed Bins Configuration 512K × 36 1024K × 18 128K × 72 256K × 36 512K × 18 Typ Max Commercial 410 590 Unit mA Industrial 460 700 mA Commercial 410 590 mA Industrial 460 700 mA Commercial 410 590 mA Industrial 460 700 mA Commercial 210 300 mA Industrial 230 350 mA Commercial 210 300 mA Industrial 230 350 mA Commercial 210 300 mA Industrial 230 350 mA Commercial 150 200 mA Industrial 170 220 mA Commercial 150 200 mA Industrial 170 220 mA Commercial 150 200 mA Industrial 170 220 mA Capacitance Packages CYD18S72V18[54] CYD09S72V18 CYD18S36V18 CYD09S36V18 CYD02S36V18 Signals CYD18S18V18 CYD09S18V18 CYD36S72V18 CYD36S36V18 CYD36S18V18 OE 12 pF 12 pF 20 pF 20 pF BE, DQ 10 pF 18 pF 16 pF 30 pF All other signals 10 pF 10 pF 16 pF 16 pF Thermal Resistance Parameter Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Document Number: 38-06082 Rev. *S Test Conditions 484-ball BGA 256-ball BGA (18 Mbit only) 256-ball BGA (9 Mbit & 2 Mbit) Unit Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 14.92 17.02 18.31 °C/W 3.6 1.25 1.68 °C/W Page 23 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 AC Test Load and Waveforms Figure 9. Output Test Load for LVTTL/CMOS VTH = 1.5V for LVTTL VTH = 50% VDDIO for 2.5V CMOS VTH = 50% VDDIO for 1.8V CMOS VREF = NC VREF 50 Ohm 50 Ohm Output Test Point R=250 Ohm READY VTH ZQ Device under test RQ=250 Ohm C = 10pF Figure 10. Output Test Load for HSTL[54] VTH = 50% VDDIO VREF = 0.75V VREF 50 Ohm 50 Ohm Output R=250 Ohm Test Point VTH READY ZQ Device under test C= 10pF for SDR RQ=250 Ohm Figure 11. HSTL Input Waveform[54] Document Number: 38-06082 Rev. *S Page 24 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Switching Characteristics Over the Operating Range Table 12. SDR Mode, Signals Affected by DLL DLL ON (LOWSPD=1)[50] Description Parameter –200 tCD2[53] C rise to DQ valid for pipelined mode tCCQ[53] C rise to CQ rise tCKHZ2 [48, 53] C rise to DQ output high Z in pipelined mode tCKLZ2[48, 53] C rise to DQ output low Z in pipelined mode DLL OFF (LOWSPD=0)[50] –167 Unit Min Max Min Max Min Max – 3.30[49, 52] – 4.00[49, 52] – 6.00[49, 52] ns 1.00 3.30 [52] 1.00 4.00[52] 1.00 6.00[52] ns 1.00 [49, 52] 1.00 – 1.00 3.30 1.00 [49, 52] 1.00 – 1.00 4.00 [49, 52] ns – ns 6.00 Table 13. SDR Mode Parameter –200 Description –167 Unit Min Max Min Max 100 200 100 167 MHz – 77 – 66.7 MHz fMAX (PIPELINED) Maximum operating frequency for pipelined mode fMAX (FLOW THROUGH) Maximum operating frequency for flow through mode tCYC (PIPELINED) C clock cycle time for pipelined mode 5.00[52] 10.00 6.00[52] 10.00 ns tCYC (FLOW X THROUGH) C clock cycle time for flow through mode 13.00[52] – 15.00[52] – ns tCKD C clock duty time 45 tSD tHD[51] tSAC 55 45 55 % Data input setup time to C HSTL rise 1.8 V LVCMOS 1.50[49, 52] – 1.70[49, 52] – ns 2.5 V LVCMOS 3.3 V LVTTL 1.75[49, 52] – 1.95[49, 52] 0.5 – Data input hold time after C rise [54] Address and control input HSTL 1.8 V L VCMOS setup time to C rise 2.5 V LVCMOS 3.3 V LVTTL tHAC[51] Address and control input hold time after C rise tOE Output enable to data valid tOLZ[48] OE to low Z – ns – [49, 51, 52] 1.70 – ns – 1.95[49, 51, 52] – ns 0.50 – 0.60 – ns – 4.40[49, 52] – 5.00[49, 52] ns 1.00 – 1.00 – ns [49, 51, 52] 1.50 1.75[49, 51, 52] 0.5 ns Notes 48. Parameters specified with the load capacitance in Figure 9 on page 24 and Figure 10 on page 24. 49. For the x18 devices, add 200 ps to this parameter in Table 13. 50. Test conditions assume a signal transition time of 2 V/ns. 51. Add 300 ps to this timing for 36M devices. 52. Add 15% to this parameter if a VCORE of 1.5 V is used. 53. This parameter assumes input clock cycle to cycle jitter of ± 0 ps. 54. HSTL Support and the corresponding tests support has been removed from the device from WW1830. No other functionality is impacted with this change Document Number: 38-06082 Rev. *S Page 25 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Table 13. SDR Mode (continued) Parameter tOHZ[55] –200 Description OE to high Z –167 Min Max Min Max 1.00 4.40[56, 57] 1.00 5.00[56, 57] tCD1 C rise to DQ valid for flow through mode (LowSPD = 0) – tCA1 C rise to address readback valid for flow through mode – 9.00[57] – [57] tCA2 C rise to address readback valid for pipelined mode tDC[58] DQ output hold after C rise tJIT Clock input cycle to cycle jitter 11.00 11.00[57] ns – [57] ns 6.00 – 1.00 – – ±200 – ±200 0.80[56] – 0.90[56] ns –0.70 – –0.80 – ns –0.85 – –0.95 – ns C rise to DQ output high Z in flow through mode 1.00 9.00[56, 57] 1.00 11.00[56, 57] ns C rise to DQ output low Z in flow through mode 1.00 – 1.00 – ns tAC Address output hold after C rise 1.00 – 1.00 – ns tCKHZA1[55] C rise to address output high Z for flow through mode 1.00 9.00[57] 1.00 11.00[57] ns C rise to address output high Z for pipelined mode 1.00 5.00[57] 1.00 6.00[57] ns C rise to address output low Z 1.00 – 1.00 – ns 1.00 4.00[57] ns 1.00 4.00[57] ns 0.50 8.00[57] ns 0.50 8.00[57] ns 1.00 [57] ns tCKHZ1[55] tCKLZ1 [55] tCKHZA2 [55] tCKLZA[55] 2.5 V LVCMOS 3.3 V LVTTL – HSTL[59] 1.8 V LVCMOS 2.5 V LVCMOS 3.3 V LVTTL ps ns Echo clock (CQ) high to output hold 0.70 ns 0.80 tCQHQX[58] – ns – 1.00 [56] ns – Echo clock (CQ) high to output valid HSTL 1.8 V LVCMOS 5.00 – [56, 57] [56] tCQHQV[58] [59] 9.00 [56, 57] Unit tSCINT C rise to CNTINT low 1.00 3.30[57] tRCINT C rise to CNTINT high 1.00 3.30[57] 0.50 7.00[57] 0.50 7.00[57] 1.00 [57] tSINT tRINT tBSY C rise to INT low C rise to INT high C rise to BUSY valid 3.30 4.00 Notes 55. Parameters specified with the load capacitance in Figure 9 on page 24 and Figure 10 on page 24. 56. For the × 18 devices, add 200 ps to this parameter in Table 13. 57. Add 15% to this parameter if a VCORE of 1.5 V is used. 58. This parameter assumes input clock cycle-to-cycle jitter of ±0 ps. 59. HSTL Support and the corresponding tests support has been removed from the device from WW1830. No other functionality is impacted with this change Document Number: 38-06082 Rev. *S Page 26 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Table 14. Master Reset Timing Parameter Description –200 –167 Min Max Min Max Unit tPUP Power-up time 1 – 1 – ms tRS Master reset pulse width 5 – 5 – cycles tRSR Master reset recovery time 5 – 5 – cycles tRSF Master reset to outputs inactive/Hi Z – 15 – 18 ns tRDY[60] Master reset release to port ready – 1024 – 1024 cycles tCORDY[61] C rise to port ready – 9.5[62] – 11[62] ns Min Max Min Max Table 15. JTAG Timing Parameter Description –200 –167 Unit fJTAG JTAG TAP controller frequency – 20 – 20 MHz tTCYC TCK cycle time 50 – 50 – ns tTH TCK high time 20 – 20 – ns tTL TCK low time 20 – 20 – ns tTMSS TMS setup to TCK rise 10 – 10 – ns tTMSH TMS hold to TCK rise 10 – 10 – ns tTDIS TDI setup to TCK rise 10 – 10 – ns tTDIH TDI hold to TCK rise 10 – 10 – ns tTDOV TCK low to TDO valid – 10 – 10 ns tTDOX TCK low to TDO invalid 0 – 0 – ns tJXZ TCK low to TDO high Z – 15 – 15 ns tJZX TCK low to TDO active – 15 – 15 ns tJZX TCK low to TDO active – 15 – 15 ns . Notes 60. READY is a wired OR capable output with a weak pull-down. For a decreased falling delay, connect a 250- resistor to VSS. 61. Add this propagation delay after tRDY for all Master Reset Operations. 62. Add 15% to this parameter if a VCORE of 1.5 V is used. Document Number: 38-06082 Rev. *S Page 27 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Switching Waveforms Figure 12. JTAG Timing tTH Test Clock TCK tTL tTCYC tTMSS tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOX tTDOV Figure 13. Master Reset [63] ~ VCORE tPUP tRS MRST ~ C ~ tRDY READY All Address & Data tRSF tCORDY ~ ~ tRSR All Other Inputs ~ Note 63. READY is a wired OR capable output with a weak pull-down. For a decreased falling delay, connect a 250- resistor to VSS. Document Number: 38-06082 Rev. *S Page 28 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Switching Waveforms (continued) Figure 14. READ Cycle for Pipelined Mode tCYC C CE OE tSAC tHAC R/W A An An+1 2 Pipelined stages DQ DQx-1 An+2 DQx DQn An+3 DQn+1 tDC An+4 DQn+2 An+5 DQn+3 An+6 DQn+4 tCD2 Figure 15. WRITE Cycle for Pipelined and Flow through Modes tCYC C CE R/W A An An+1 An+2 An+3 An+4 An+5 An+6 DQn+1 DQn+2 DQn+3 DQn+4 DQn+5 DQn+6 2 Pipelined stages DQ DQn tSD Document Number: 38-06082 Rev. *S tHD Page 29 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Switching Waveforms (continued) Figure 16. READ with Address Counter Advance for Pipelined Mode tCYC C An A Internal Address An An+2 An+1 An+3 ADS CNTEN DQ DQx-1 DQx DQn DQn+1 DQn+2 DQn+3 Figure 17. READ with Address Counter Advance for Flow through Mode tC Y C C tS A C tH A C A An ADS t S AC t H AC C NT E N tCD1 DQ DQx DQ n DQn + 1 DQn + 2 DQ n + 3 DQn + 4 tD C R EA D E XT E R N A L A D D R E SS Document Number: 38-06082 Rev. *S R E AD W IT H C O U N TE R C O U N T ER H O L D R EA D W IT H C O U N T E R Page 30 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Switching Waveforms (continued) Figure 18. Port-to-Port WRITE–READ for Pipelined Mode tCYC Left Port CL An AL R/WL DQL DQn Right Port tCCS CR tCYC AR An R/WR tSAC tHAC DQR DQn tCD2 tDC Figure 19. Chip Enable READ for Pipelined Mode tCYC C CE0 CE1 R/W tSAC tHAC A An An+1 An+2 An+3 An+4 tCD2 Document Number: 38-06082 Rev. *S An+6 DQn+3 DQn DQ An+5 tDC tCKLZ2 Page 31 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Switching Waveforms (continued) Figure 20. OE Controlled WRITE for Pipelined Mode tCYC C A Ax+1 Ax+2 Ax+3 An An+1 An+2 An+3 DQn DQn+1 DQn+2 DQn+3 R/W OE tOHZ DQx+1 DQ DQx-1 DQx Figure 21. OE Controlled WRITE for Flow through Mode tCYC C A Ax+1 Ax+2 Ax+3 An An+1 An+2 An+3 DQn DQn+1 DQn+2 DQn+3 R/W OE tOHZ DQx+2 DQ DQx DQx+1 Document Number: 38-06082 Rev. *S Page 32 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Switching Waveforms (continued) Figure 22. Byte-Enable READ for Pipelined Mode tCYC C A An An+1 An+2 An+3 R/W BE7 BE6 BE5 BE4 BE3 BE2 BE1 BE0 tCKLZ2 t DQn+1(63:71) CKHZ2 DQ63:71 DQ54:62 DQn+1(54:62) DQn+2(45:53) DQ45:53 DQn+2(36:44) DQ36:44 DQn+1(27:35) DQ27:35 DQ18:26 DQ9:17 DQ0:8 Document Number: 38-06082 Rev. *S DQn+2(18:26) DQn+3(9:17) DQn+3(0:8) Page 33 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Switching Waveforms (continued) Figure 23. Port-to-Port WRITE-to-READ for Flow through Mode CL R /W L tS A C AL tH A C M A TC H NO MATCH tS D DQL tH D V A LID tC C S CR tCD1 R /W R tH A C tS A C AR NO MATCH M A TC H tC D 1 VA LID DQR tD C Document Number: 38-06082 Rev. *S V A L ID tDC Page 34 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Switching Waveforms (continued) Figure 24. Busy Address Readback for Pipelined and Flow through Modes, CNT/MSK = RET = LOW [64] tCYC ~ C Internal Amatch+2 Address Amatch+3 ~ Amatch+4 BUSY ~ ~ CNTEN ~ ADS External Address Pipelined ~ External Address Flow through ~ Amatch tCA2 tAC Amatch tAC tCA1 Figure 25. Read Cycle for Flow through Mode t CY C C CE 0 t SA C t H AC CE 1 B En R /W t S AC A t H AC An + 1 An tC D 1 DQ An + 2 t C KH Z 1 tD C DQn t C KLZ 1 An + 3 DQn + 1 tO H Z DQn + 2 tD C t O LZ OE tO E Note 64. Amatch is the matching address that is reported on the address bus of the losing port. The counter operation selected for reporting the address is “Busy Address Readback.” Document Number: 38-06082 Rev. *S Page 35 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Switching Waveforms (continued) Figure 26. READ-to-WRITE for Pipelined Mode (OE = VIL) [65, 66, 67] tCYC tCL C A tCH Ax An An+1 tSAC tHAC R/W DQ An+2 tSAC tHAC tCKLZ2 DQx-2 DQx-1 DQx tDC tCD2 DQn DQn+1 tCKHZ2 DQn+2 tSD tHD Figure 27. READ-to-WRITE for Pipelined Mode (OE Controlled) [68, 69] tCYC C A Ax Ax+1 Ax+2 An An+1 An+2 An+3 DQn+1 DQn+2 DQn+3 tSAC tHAC R/W OE DQ tOHZ DQx-2 DQx-1 DQx tSD tHD DQn Notes 65. When OE = VIL, the last read operation is enabled to complete before the DQ bus is tristated and the user is enabled to drive write data. 66. Two dummy writes are issued to accomplish bus turnaround. The third instruction is the first valid write. 67. Chip enable or all byte enables are held inactive during the two dummy writes to avoid data corruption. 68. OE is deasserted and tOHZ enabled to elapse before the first write operation is issued. 69. Any write scheduled to complete after OE is deasserted is pre-empted. Document Number: 38-06082 Rev. *S Page 36 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Switching Waveforms (continued) Figure 28. Read-to-Write-to-Read for Flow through Mode (OE = LOW) t CYC C t SAC t HAC CE0 CE 1 B En t SAC t HAC R/W A An An + 1 An + 2 An + 2 t SD DQ IN An + 3 An + 4 tH D DQn + 2 t CD1 t C D1 DQ n D Q O UT t C D1 DQn + 1 t CD1 DQ n + 3 t CKHZ1 t CKLZ1 tD C R EAD Document Number: 38-06082 Rev. *S tD C NO P W RITE R EAD Page 37 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Switching Waveforms (continued) Figure 29. Read-to-Write-to-Read for Flow through Mode (OE Controlled) t C YC C t SA C t H AC CE0 CE1 BEn t SA C t H A C R /W A An An + 1 An + 2 tS D D Q IN DQn + 2 tC D 1 D Q OUT An + 3 An + 4 An + 5 tH D DQn + 3 tD C tO E tC D 1 tC D 1 DQn DQn + 4 t C KLZ 1 tO H Z tD C OE READ Document Number: 38-06082 Rev. *S W R IT E R EA D Page 38 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Switching Waveforms (continued) Figure 30. BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow through Modes, Clock Timing Violates tCCS. (Flag Both Ports) Port A C A R/W BUSY < tCCS tBSY tBSY Port B C A R/W tBSY BUSY tBSY Figure 31. BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow through Modes, Clock Timing Meets tCCS. (Flag Losing Port) Losing Port C A R/W BUSY tccs tBSY tBSY Winning Port C A Match R/W BUSY Document Number: 38-06082 Rev. *S Page 39 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Switching Waveforms (continued) Figure 32. Read with Echo Clock for Pipelined Mode (CQEN = HIGH) C tSAC tHAC R/W A An An+1 An+2 An+3 An+4 An+5 An+6 CQ0 CQ0 tCCQ CQ1 CQ1 tCQHQX tCQHQV DQ DQx-1 DQx Document Number: 38-06082 Rev. *S DQn DQn+1 DQn+2 DQn+3 DQn+4 Page 40 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Switching Waveforms (continued) Figure 33. Mailbox Interrupt Output tCYC CL AL AMAX R/WL DQL INTR tSINT tRINT CR AR AMAX R/WR DQR Document Number: 38-06082 Rev. *S DQMAX Page 41 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Ordering Information Speed (MHz) Ordering Code Package Diagram Package Type Operating Range 512K × 72 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S72V18 Dual-Port SRAM 200 CYD36S72V18-200BGXC 001-07825 484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free) Commercial 256K × 72 (18-Mbit) 1.8 V/1.5 V Synchronous CYD18S72V18 Dual-Port SRAM 200 CYD18S72V18-200BGXI 51-85218 484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch (Pb-free) Industrial 200 CYD18S72V18-200BGI 51-85218 484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch Industrial 167 CYD18S72V18-167BGI 51-85218 484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch Industrial 128K × 72 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S72V18 Dual-Port SRAM 167 CYD09S72V18-167BBXC 51-85218 484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch (Pb-free) Commercial 1024K × 36 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S36V18 Dual-Port SRAM 167 CYD36S36V18-167BGXI 001-07825 484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free) Industrial 512K × 36 (18-Mbit) 1.8 V/1.5 V Synchronous CYD18S36V18 Dual-Port SRAM 200 CYD18S36V18-200BBAXI 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) Industrial 167 CYD18S36V18-167BBAI 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch Industrial 256K × 36 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S36V18 Dual-Port SRAM 200 CYD09S36V18-200BBXI 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) Industrial 167 CYD09S36V18-167BBXC 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) Commercial 64K × 36 (2-Mbit) 1.8 V or 1.5 V Synchronous CYD02S36V18 Dual-Port SRAM 200 CYD02S36V18-200BBXC 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) Commercial 2048K × 18 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S18V18 Dual-Port SRAM 167 CYD36S18V18-167BGXI 001-07825 484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free) Industrial 1024K × 18 (18-Mbit) 1.8 V/1.5 V Synchronous CYD18S18V18 Dual-Port SRAM 200 CYD18S18V18-200BBAXI 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) 200 CYD18S18V18-200BBAXC 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) Commercial Industrial 167 CYD18S18V18-167BBAXI 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) Industrial 512K × 18 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S18V18 Dual-Port SRAM 167 CYD09S18V18-167BBXI Document Number: 38-06082 Rev. *S 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) Industrial Page 42 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Ordering Code Definitions CY DXX SXX V18 - XXX XXX X X Temperature Range: X = C or I C = Commercial; I = Industrial Pb-free Package Type: (XXX = BG or BB or BBA) BG = 484-ball BGA; BBA or BB = 256-ball BGA Speed Grade: XXX = 167 MHz or 200 MHz V18 = 1.8 V Data Width: SXX = S72 or S36 or S18 Density in Mb: DXX = D36 or D 18 or D09 or D02 CY = Cypress Document Number: 38-06082 Rev. *S Page 43 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Package Diagrams Figure 34. 256-ball FBGA (17 × 17 × 1.7 mm) BB256/BW0BD Package Outline, 51-85108 51-85108 *J Document Number: 38-06082 Rev. *S Page 44 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Package Diagrams (continued) Figure 35. 484-ball PBGA (23 × 23 × 2.03 mm) BY484 Package Outline, 51-85218 51-85218 *C Document Number: 38-06082 Rev. *S Page 45 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Package Diagrams (continued) Figure 36. 484-ball PBGA (27 × 27 × 2.33 mm) BY484S Package Outline, 001-07825 001-07825 *C Document Number: 38-06082 Rev. *S Page 46 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Acronyms Acronym Document Conventions Description Units of Measure BGA Ball Grid Array CMOS Complementary Metal Oxide Semiconductor °C degree Celsius DLL Delay Lock Loop MHz megahertz FBGA Fine-Pitch Ball Grid Array µA microampere HSTL High Speed Transceiver Logic mA milliampere I/O Input/Output ms millisecond SDR Single Data Rate mV millivolt SRAM Static Random Access Memory ns nanosecond TCK Test Clock pF picofarad TDI Test Data-In V volt TDO Test Data-Out W watt TMS Test Mode Select VIM Variable Impedance Matching Document Number: 38-06082 Rev. *S Symbol Unit of Measure Page 47 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Document History Page Document Title: CYDXXS72V18/CYDXXS36V18/CYDXXS18V18, FullFlex™ Synchronous SDR Dual-Port SRAM Document Number: 38-06082 Rev. ECN No. Orig. of Change Submission Date ** 302411 YDT See ECN New data sheet. *A 334036 YDT See ECN Corrected typo on page 1 Reproduced PDF file to fix formatting errors *B 395800 SPN See ECN Added statement about no echo clocks for flow through mode Updated electrical characteristics Added note 16 and 17 (1.5 V timing) Added note 33 (timing for x18 devices) Updated input edge rate (note 34) Updated table 5 on deterministic access control logic Added description of busy readback in deterministic access control section Changed dummy write descriptions Updated ZQ pins connection details Updated note 24, B0 to BE0 Added power supply requirements to MRST and VC_SEL Added note 4 (VIM disable) Updated supply voltage to ground potential to 4.1 V Updated parameters on table 15 Updated and added parameters to table 16 Updated x72 pinout to SDR only pinout Updated 484 PBGA pin diagram Updated the pin definition of MRST Updated the pin definition of VC_SEL Updated READY description to include Wired OR note Updated master reset to include wired OR note for READY Updated minimum VOH value for the 1.8 V LVCMOS configuration Updated electrical characteristics to include IOH and IOL values Updated electrical characteristics to include READY Added IIX3 Updated maximum input capacitance Added Notes 33 and 34Removed Notes 15 and 17 Updated Pin Definitions for CQ0, CQ0, CQ1, and CQ1 Removed -100 Speed bin from Selection Guide Changed voltage name from VDDQ to VDDIO Changed voltage name from VDD to VCORE Moved the Mailbox Interrupt Timing Diagram to be the final timing diagram Updated the Package Type for the CYD36S18V18 parts Updated the Package Type for the CYD36S18V18 parts Updated the Package Type for the CYD18S18V18 parts Updated the Package Type for the CYD18S36V18 parts Included the Package Diagram for the 256-Ball FBGA (19 x 19 mm) BW256 Included an OE Controlled Write for Flow through Mode Switching Waveform Included a Read with Echo Clock Switching Waveform Updated Figure 5 and Figure 6 Updated Electrical Characteristics for READY VOH and READY V Updated Electrical Characteristics for VOH and VOL for the -167 and -133 speeds Included a Unit column for Table 5 Removed Switching Characteristic tCA from chart Included tOHZ in Switching Waveform OE Controlled Write for Pipelined Mode Included tCKLZ2 in Waveform Read-to-Write-to-Read for Flow through Mode Document Number: 38-06082 Rev. *S Description of Change Page 48 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Document History Page (continued) Document Title: CYDXXS72V18/CYDXXS36V18/CYDXXS18V18, FullFlex™ Synchronous SDR Dual-Port SRAM Document Number: 38-06082 Rev. ECN No. Orig. of Change Submission Date *C 402238 KGH SEE ECN Updated AC Test Load and Waveforms Included FullFlex36 SDR 484-Ball BGA Pinout (Top View) Included FullFlex18 SDR 484-Ball BGA Pinout (Top View) Included Timing Parameter tCORDY *D 458131 YDT SEE ECN Changed ordering information with Pb-free part numbers Removed VC_SEL Added IO and core voltage adders Removed references to bin drop for LVTTL/2.5 V LVCMOS and 1.5 V core modes Updated Cin and Cout Updated ICC, ISB1, ISB2 and ISB3 tables Updated busy address read back timing diagram Added HTSL input waveform Removed HSTL (AC) from DC tables Added 484-ball 27 mm × 27 mm × 2.33 mm PBGA package *E 470031 YDT SEE ECN Changed VOL of 1.8 V LVCMOS to 0.45 V Updated tRSF VREF is DNU when HSTL is not used Formatted pin description table Changed VDDIO pins for 36M × 36 and 36M × 18 pinouts Changed 36M × 72 JTAG IDCODE *F 500001 YDT SEE ECN DLL Change, added Clock Input Cycle to Cycle Jitter Modified DLL description Changed Input Capacitance Table Changed tCCS number Added note 31 *G 627539 QSL SEE ECN change all NC to DNU corrected switching waveform for (CQEN = High) from both Pipeline and Flow through mode to only pipeline mode Modified master reset description Modified switching characteristics tables, extracted signals effected by the DLL into one table and combine all other signals into one table updated package name Added footnote for tHD, tHAC and tSAC changed note 26 description *H 2505003 VKN / AESA See ECN Modified footnote #1 Removed 250 MHz speed bin Added 2-Mbit part and it’s related information Changed ball name ZQ1 to DNU for 18M and lesser density devices Added 256-ball (17 × 17 mm) BGA package for 18M Made PORTSTD[1:0] left and right pins driven only by LVTTL reference level For 1.8 V LVCMOS level, Changed VIH(min) from 1.26 V to 0.65 times VDDIO and changed VIL(max) from 0.36 V to 0.35 times VDDIO Changed tHD, tHAC specs for 36M from 0.6 ns/0.7 ns to 0.8 ns (See footnote# 32) Updated Ordering Information table Document Number: 38-06082 Rev. *S Description of Change Page 49 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Document History Page (continued) Document Title: CYDXXS72V18/CYDXXS36V18/CYDXXS18V18, FullFlex™ Synchronous SDR Dual-Port SRAM Document Number: 38-06082 Rev. ECN No. Orig. of Change Submission Date Description of Change *I 2898491 RAME 07/01/2010 Modified “Counter Load Operation” section on page 12 and in Table7 on page 13. Corrected typo in Table 14. by making LowSPD = 0 for tCD1 spec in the description. Modified figure 16. on page 30. Removed inactive parts from Ordering Information. Updated Packaging Information. Corrected “Counter Interrupt operation” Section in Page 14 of the data sheet Updated ordering information with the parts, CYD02S36V18-200BBC and CYD36S72V18-167BGI. *J 2995098 RAME 07/28/2010 Updated Ordering Information: Updated part numbers. Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits. *K 3267210 ADMU 05/26/2011 Removed information for 4Mb devices. Updated Electrical Characteristics on page 21 (Removed 133 MHz speed bin). Updated Switching Characteristics on page 25 (Removed 133 MHz speed bin). Updated Ordering Information: Updated part numbers. *L 3357888 ADMU 08/30/2011 Updated Pin configuration Figure 1 through 5. Added Thermal Resistance. *M 3349458 ADMU 10/28/2011 Minor edits in Figure 5 (removed overbars in balls C5 and C12). Updated Package Diagrams. *N 3845411 ADMU 01/29/2013 Updated Ordering Information (Updated part numbers). Updated Package Diagrams: spec 001-07825 – Changed revision from *A to *B. *O 3895845 ADMU 02/05/2013 Updated Ordering Information (Updated part numbers). *P 4413766 ADMU 06/19/2014 Updated Package Diagrams: spec 51-85218 – Changed revision from *A to *B. Updated to new template. *Q 4581625 ADMU 11/27/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *R 5787387 NILE 06/27/2017 Updated Ordering Information: Updated part numbers. Updated Package Diagrams: spec 51-85108 – Changed revision from *I to *J. spec 51-85218 – Changed revision from *B to *C. spec 001-07825 – Changed revision from *B to *C. Updated to new template. Completing Sunset Review. *S 6259481 NILE 07/24/2018 Added a footnote about removal of support to HSTL signalling in these products from WW1830. Document Number: 38-06082 Rev. *S Page 50 of 51 CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Document Number: 38-06082 Rev. *S Revised July 24, 2018 Page 51 of 51