CYDM064B16
CYDM128B16
CYDM256B16
®
1.8 V, 4K/8K/16K × 16 MoBL Dual-Port
Static RAM
1.8 V, 4K/8K/16K × 16 MoBL® Dual-Port Static RAM
Features
Functional Description
■
True dual ported memory cells that allow simultaneous access
of the same memory location
■
4, 8, or 16K × 16 organization
■
Ultra Low operating power
❐ Active: ICC = 15 mA (typical) at 55 ns
❐ Standby: ISB3 = 2 A (typical)
■
Small footprint: available in a 6 × 6 mm 100-pin Pb-free vfBGA
■
Port independent 1.8 V, 2.5 V, and 3.0 V I/Os
■
Full asynchronous operation
■
Automatic power down
■
Pin select for Master or Slave
■
Expandable data bus to 32-bits with Master or Slave chip select
when using more than one device
■
On-chip arbitration logic
■
Semaphores included to permit software handshaking
between ports
■
Input read registers and output drive registers
■
INT flag for port-to-port communication
■
Separate upper-byte and lower-byte control
■
Industrial temperature ranges
The CYDM256B16, CYDM128B16, and CYDM064B16 are low
power CMOS 4K, 8K,16K × 16 dual-port static RAMs. Arbitration
schemes are included on the devices to handle situations when
multiple processors access the same piece of data. Two ports
are provided that permit independent, asynchronous access for
reads and writes to any location in memory. The devices can be
used as standalone 16-bit dual-port static RAMs or multiple
devices can be combined to function as a 32-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 32-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor or multiprocessor designs, communications status buffering, and
dual-port video or graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY indicates that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems through a mail box.
The semaphores are used to pass a flag or token, from one port
to the other, to indicate that a shared resource is in use. The
semaphore logic consists of eight shared latches. Only one side
can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a Chip Enable (CE) pin.
The CYDM256B16, CYDM128B16, CYDM064B16 are available
in 100-ball 0.5 mm pitch Ball Grid Array (BGA) packages.
Cypress Semiconductor Corporation
Document Number: 001-00217 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 12, 2018
CYDM064B16
CYDM128B16
CYDM256B16
Selection Guide for VCC = 1.8V
Parameter
CYDM256B16/CYDM128B16/CYDM064B16
(-55)
Port I/O Voltages (P1–P2)
Unit
1.8 V–1.8 V
V
Maximum Access Time
55
ns
Typical Operating Current
15
mA
Typical Standby Current for ISB1
2
A
Typical Standby Current for ISB3
2
A
Selection Guide for VCC = 2.5 V
Parameter
CYDM256B16/CYDM128B16/CYDM064B16
(-55)
Port I/O Voltages (P1–P2)
Unit
2.5 V–2.5 V
V
Maximum Access Time
55
ns
Typical Operating Current
28
mA
Typical Standby Current for ISB1
6
A
Typical Standby Current for ISB3
4
A
Selection Guide for VCC = 3.0 V
Parameter
Port I/O Voltages (P1–P2)
CYDM256B16/CYDM128B16/CYDM064B16
(-55)
Unit
3.0 V–3.0 V
V
Maximum Access Time
55
ns
Typical Operating Current
42
mA
Typical Standby Current for ISB1
7
A
Typical Standby Current for ISB3
6
A
Document Number: 001-00217 Rev. *K
Page 2 of 33
CYDM064B16
CYDM128B16
CYDM256B16
Logic Block Diagram [1, 2]
IO[15:0]R
IO[15:0]L
UBR
UBL
LBL
LBR
IO
Control
IO
Control
16K X 16
Dual Ported Array
Address Decode
Address Decode
A[13:0]L
CE L
A [13:0]R
CE R
Interrupt
Arbitration
Semaphore
OE L
R/W L
SEML
BUSY L
INTL
IRR0 ,IRR1
Mailboxes
CEL
OEL
R/WL
INTR
OE R
R/W R
SEMR
BUSY R
M/S
Input Read
Register and
Output Drive
Register
CE R
OE R
R/W R
ODR0 - ODR4
SFEN
Notes
1. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.
2. BUSY is an output in master mode and an input in slave mode.
Document Number: 001-00217 Rev. *K
Page 3 of 33
CYDM064B16
CYDM128B16
CYDM256B16
Contents
Pinouts .............................................................................. 5
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Power Supply .............................................................. 7
Write Operation ........................................................... 7
Read Operation ........................................................... 7
Interrupts ..................................................................... 8
Busy ............................................................................ 8
Master/Slave ............................................................... 8
Input Read Register .................................................... 8
Output Drive Register .................................................. 9
Semaphore Operation ................................................. 9
Architecture .................................................................... 10
Maximum Ratings ........................................................... 11
Operating Range ............................................................. 11
Electrical Characteristics for VCC = 1.8 V .................... 12
Electrical Characteristics for VCC = 2.5 V .................... 14
Electrical Characteristics for VCC = 3.0 V .................... 15
Capacitance .................................................................... 16
AC Test Loads and Waveforms ..................................... 16
Document Number: 001-00217 Rev. *K
Switching Characteristics for VCC = 1.8 V ................... 17
Switching Characteristics for VCC = 2.5 V ................... 19
Switching Characteristics for VCC = 3.0 V ................... 21
Switching Waveforms .................................................... 23
Ordering Information ...................................................... 29
16K × 16 1.8 V Asynchronous Dual-Port SRAM ....... 29
8K × 16 1.8 V Asynchronous Dual-Port SRAM ......... 29
4K × 16 1.8 V Asynchronous Dual-Port SRAM ......... 29
Ordering Code Definitions ......................................... 29
Package Diagram ............................................................ 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC® Solutions ...................................................... 33
Cypress Developer Community ................................. 33
Technical Support ..................................................... 33
Page 4 of 33
CYDM064B16
CYDM128B16
CYDM256B16
Pinouts
Figure 1. Ball Diagram - 100-ball 0.5 mm Pitch BGA (Top View) [3, 4, 5, 6, 7]
CYDM064B16/CYDM128B16/CYDM256B16
1
2
3
4
5
6
7
8
9
10
A
A5R
A8R
A11R
UBR
VSS
SEMR
IO15R
IO12R
IO10R
VSS
A
B
A3R
A4R
A7R
A9R
CER
R/WR
OER
VDDIOR
IO9R
IO6R
B
C
A0R
A1R
A2R
A6R
LBR
IRR1[6] IO14R
IO11R
IO7R
VSS
C
ODR4 ODR2 BUSYR INTR
A10R
A12R[3] IO13R
IO8R
IO5R
IO2R
D
IO1R
VSS
E
D
ODR3
INTL
VSS
VSS
IO4R
VDDIOR
F
SFEN ODR1 BUSYL
A1L
VCC
VSS
IO3R
IO0R
IO15L VDDIOL
F
G
ODR0
A2L
A5L
A12L[3]
OEL
IO3L
IO11L
IO12L
IO14L
IO13L
G
H
A0L
A4L
A9L
LBL
CEL
IO1L
VDDIOL NC[7]
NC[7]
IO10L
H
J
A3L
A7L
A10L
IRR0[5]
VCC
VSS
IO4L
IO6L
IO8L
IO9L
J
K
A6L
A8L
A11L
UBL
SEML
R/WL
IO0L
IO2L
IO5L
IO7L
K
1
2
3
4
5
6
7
8
9
10
E
VSS
M/S
Notes
3. A12L and A12R are NC pins for CYDM064B16.
4. IRR functionality is not supported for the CYDM256B16 device.
5. This pin is A13L for CYDM256B16 device.
6. This pin is A13R for CYDM256B16 device.
7. Leave this pin unconnected. No trace or power component can be connected to this pin.
Document Number: 001-00217 Rev. *K
Page 5 of 33
CYDM064B16
CYDM128B16
CYDM256B16
Pin Definitions
100-ball 0.5 mm pitch BGA (CYDM064B16/CYDM128B16/CYDM256B16)
Left Port
Right Port
Description
CEL
CER
Chip Enable
R/WL
R/WR
Read or Write Enable
OEL
OER
Output Enable
A0L–A13L
A0R–A13R
Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices)
IO0L–IO15L
IO0R–IO15R
Data Bus Input or Output for x16 devices
SEML
SEMR
Semaphore Enable
UBL
UBR
Upper Byte Select (IO8–IO15)
LBL
LBR
Lower Byte Select (IO0–IO7)
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
IRR0, IRR1
ODR0-ODR4
SFEN
Input Read Register for CYDM064B16 and CYDM128B16
A13L and A13R for CYDM256B16.
Output Drive Register. These outputs are Open Drain.
Special Function Enable
M/S
Master or Slave Select
VCC
Core Power
GND
Ground
VDDIOL
VDDIOR
NC
Left Port I/O Voltage
Right Port I/O Voltage
No Connect. Leave this pin Unconnected.
Document Number: 001-00217 Rev. *K
Page 6 of 33
CYDM064B16
CYDM128B16
CYDM256B16
Functional Overview
Write Operation
Power Supply
The core voltage (VCC) can be 1.8 V, 2.5 V, or 3.0 V, as long as
it is lower than or equal to the I/O voltage.
Each port can operate on independent I/O voltages. This is
determined by what is connected to the VDDIOL and VDDIOR pins.
The supported I/O standards are 1.8 V or 2.5 V LVCMOS and
3.0V LVTTL.
Data must be set up for a duration of tSD before the rising edge
of R/W to guarantee a valid write. A write operation is controlled
by either the R/W pin (see Figure 6 on page 24) or the CE pin
(see Figure 7 on page 24). Required inputs for noncontention
operations are summarized in Table 1.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output. Otherwise, the
data read is not deterministic. Data is valid on the port tDDD after
the data is presented on the other port.
Table 1. NonContending Read/Write
Inputs
Outputs
IO8–IO15
Operation
IO0–IO7
CE
R/W
OE
UB
LB
SEM
H
X
X
X
X
H
High Z
High Z
Deselected: Power down
X
X
X
H
H
H
High Z
High Z
Deselected: Power down
L
L
X
L
H
H
Data In
High Z
Write to Upper Byte Only
L
L
X
H
L
H
High Z
Data In
Write to Lower Byte Only
L
L
X
L
L
H
Data In
Data In
Write to Both Bytes
L
H
L
L
H
H
Data Out
High Z
Read Upper Byte Only
L
H
L
H
L
H
High Z
Data Out
Read Lower Byte Only
L
H
L
L
L
H
Data Out
Data Out
Read Both Bytes
X
X
H
X
X
X
High Z
High Z
Outputs Disabled
H
H
L
X
X
L
Data Out
Data Out
Read Data in Semaphore Flag
X
H
L
H
H
L
Data Out
Data Out
Read Data in Semaphore Flag
H
X
X
X
L
Data In
Data In
Write DIN0 into Semaphore Flag
X
X
H
H
L
Data In
Data In
Write DIN0 into Semaphore Flag
L
X
X
L
X
L
Not Allowed
L
X
X
X
L
L
Not Allowed
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available tACE after CE or tDOE after OE is
Document Number: 001-00217 Rev. *K
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must
also be asserted.
Page 7 of 33
CYDM064B16
CYDM128B16
CYDM256B16
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CYDM064B16, 1FFF for the CYDM128B16, 3FFF for the
CYDM256B16) is the mailbox for the right port and the
second-highest memory location (FFE for the CYDM064B16,
1FFE for the CYDM128B16, 3FFE for the CYDM256B16) is the
mailbox for the left port. When one port writes to the other port’s
mailbox, an interrupt is generated to the owner. The interrupt is
reset when the owner reads the contents of the mailbox. The
message is user-defined.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin. On power up, an initialization program must be run and
the interrupts for both ports must be read to reset them.
The operation of the interrupts and their interaction with Busy are
summarized in Table 2.
Table 2. Interrupt Operation Example (Assumes BUSYL = BUSYR = HIGH) [8]
Left Port
Function
Right Port
R/WL
CEL
OEL
A0L–13L
INTL
R/WR
CER
OER
A0R–13R
INTR
Set Right INTR Flag
L
L
X
3FFF[11]
X
X
X
X
X
L[10]
Reset Right INTR Flag
X
X
X
X
X
X
L
L
3FFF[11]
H[9]
Set Left INTL Flag
X
X
X
X
L[9]
L
L
X
3FFE[11]
X
Reset Left INTL Flag
X
L
L
3FFE[11]
H[10]
X
X
X
X
X
Busy
The CYDM256B16, CYDM128B16, and CYDM064B16 provide
on-chip arbitration to resolve simultaneous memory location
access (contention). If both port CEs are asserted and an
address match occurs within tPS of each other, the busy logic
determines which port has access. If tPS is violated, one port
definitely gains permission to the location. However, which port
gets this permission cannot be predicted. BUSY is asserted tBLA
after an address match or tBLC after CE is taken LOW.
Master/Slave
An M/S pin is provided to expand the word width by configuring
the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This allows
the device to interface to a master device with no external
components. Writing to slave devices must be delayed until after
the BUSY input has settled (tBLC or tBLA). Otherwise, the slave
chip may begin a write cycle during a contention situation. When
tied HIGH, the M/S pin allows the device to be used as a master
and, as a result, the BUSY line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
Input Read Register
The Input Read Register (IRR) captures the status of two
external input devices that are connected to the Input Read pins.
The contents of the IRR read from address x0000 from either
port. During reads from the IRR, DQ0 and DQ1 are valid bits and
DQ are don’t care. Writes to address x0000 are not
allowed from either port.
Address x0000 is not available for standard memory accesses
when SFEN = VIL. When SFEN = VIH, address x0000 is available
for memory accesses.
The inputs are 1.8V/2.5V LVCMOS or 3.0V LVTTL, depending
on the core voltage supply (VCC). Refer to Table 3 on page 8 for
Input Read Register operation.
IRR is not available in the CYDM256B16, because the IRR pins
are used as extra address pins A13L and A13R.
Table 3. Input Read Register Operation[12, 13]
SFEN
CE
R/W
OE
UB
LB
ADDR
IO0–IO1
IO2–IO15
H
L
H
L
L
L
x0000-Max
VALID[14]
VALID[14]
L
L
H
L
X
L
x0000
[15]
VALID
X
Mode
Standard Memory Access
IRR Read
Notes
8. See Interrupts Functional Description for specific highest memory locations by device.
9. If BUSYR = L, then no change.
10. If BUSYL = L, then no change.
11. See section Functional Description on page 1 for specific addresses by device.
12. SFEN = VIL for IRR reads.
13. SFEN active when either CEL = VIL or CER = VIL. It is inactive when CEL = CER = VIH.
14. UB or LB = VIL. If LB = VIL, then DQ are valid. If UB = VIL then DQ are valid.
15. LB must be active (LB = VIL) for these bits to be valid.
Document Number: 001-00217 Rev. *K
Page 8 of 33
CYDM064B16
CYDM128B16
CYDM256B16
Output Drive Register
The Output Drive Register (ODR) determines the state of up to
five external binary state devices by providing a path to VSS for
the external circuit. These outputs are Open Drain.
The five external devices can operate at different voltages
(1.5 V VDDIO 3.5 V) but the combined current cannot exceed
40 mA (8 mA max for each external device). The status of the
ODR bits are set using standard write accesses from either port
to address x0001 with a “1” corresponding to on and “0” corresponding to off.
The status of the ODR bits can be read with a standard read
access to address x0001. When SFEN = VIL, the ODR is active
and address x0001 is not available for memory accesses. When
SFEN = VIH, the ODR is inactive and address x0001 can be used
for standard accesses.
During reads and writes to ODR DQ are valid and
DQ are don’t care. Refer to Table 4 for Output Drive
Register operation.
Table 4. Output Drive Register [16]
SFEN
H
CE
L
R/W
H
OE
L
L
L
X
X
L
L
H
L
[17]
UB
LB
L[18]
L[18]
X
L
X
L
ADDR
IO0–IO4 IO5–IO15
Mode
x0000-Max VALID[18] VALID[18] Standard Memory Access
x0001
X
VALID[19]
ODR Write[16, 20]
x0001
X
VALID[19]
ODR Read[16]
Semaphore Operation
The CYDM256B16, CYDM128B16, and CYDM064B16 provide
eight semaphore latches, which are separate from the dual-port
memory locations. Semaphores are used to reserve resources
that are shared between the two ports. The state of the
semaphore indicates that a resource is in use. For example, if
the left port wants to request a given resource, it sets a latch by
writing a zero to a semaphore location. The left port then verifies
its success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for tSOP before
attempting to read the semaphore. The semaphore value is
available tSWRD + tDOE after the rising edge of the semaphore
write. If the left port is successful (reads a zero), it assumes
control of the shared resource. Otherwise (reads a one), it
assumes the right port has control and continues to poll the
semaphore. When the right side has relinquished control of the
semaphore (by writing a one), the left side succeeds in gaining
control of the semaphore. If the left side no longer requires the
semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only IO0 is used. If a zero is
written to the left port of an available semaphore, a one appears
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore is set to one
for both sides. However, if the right port requests the semaphore
(written a zero) while the left port has control, the right port
immediately owns the semaphore as soon as the left port
releases it. Table 5 shows sample semaphore operations.
Table 5. Semaphore Operation Example
Function
No action
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
Left port writes 1 to semaphore
IO0–IO15 Left
1
0
0
1
1
0
1
1
1
0
1
IO0–IO15 Right
1
1
1
0
0
1
1
0
1
1
1
Status
Semaphore free
Left Port has semaphore token
No change. Right side has no write access to semaphore.
Right port obtains semaphore token
No change. Left port has no write access to semaphore.
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
Notes
16. SFEN = VIL for ODR reads and writes.
17. Output enable must be low (OE = VIL) during reads for valid data to be output.
18. UB or LB = VIL. If LB = VIL, then DQ are valid. If UB = VIL then DQ are valid.
19. LB must be active (LB = VIL) for these bits to be valid.
20. During ODR writes data are also written to the memory.
Document Number: 001-00217 Rev. *K
Page 9 of 33
CYDM064B16
CYDM128B16
CYDM256B16
When reading a semaphore, all sixteen data lines output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore is definitely
obtained by one side or the other, but there is no guarantee which
side controls the semaphore. On power up, both ports must write
“1” to all eight semaphores.
Architecture
The CYDM256B16, CYDM128B16, and CYDM064B16 consist
of an array of 4K, 8K, or 16K words of 16 dual-port RAM cells,
I/O and address lines, and control signals (CE, OE, R/W). These
Document Number: 001-00217 Rev. *K
control pins permit independent access for reads or writes to any
location in memory. To handle simultaneous writes or reads to
the same location, a BUSY pin is provided on each port. Two
Interrupt (INT) pins can be used for port-to-port communication.
Two Semaphore (SEM) control pins are used to allocate shared
resources. With the M/S pin, the devices can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The devices also have an automatic power down feature
controlled by CE. Each port is provided with its own output
enable control (OE), which allows data to be read from the
device.
Page 10 of 33
CYDM064B16
CYDM128B16
CYDM256B16
Maximum Ratings
Exceeding maximum ratings[19] may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ........................................... –55°C to +125°C
Static Discharge Voltage ......................................... > 2000V
Latch-up Current ................................................... > 200 mA
Operating Range
Range
Commercial
Ambient Temperature
VCC
0 °C to +70 °C
1.8 V ± 100 mV
2.5 V ± 100 mV
3.0 V ± 300 mV
–40 °C to +85 °C
1.8 V ± 100 mV
2.5 V ± 100 mV
3.0 V ± 300 mV
Supply Voltage to Ground Potential ...............–0.5V to +3.3V
DC Voltage Applied to Outputs
in High Z State ...................................... –0.5V to VCC + 0.5V
DC Input Voltage[20] .............................. –0.5V to VCC + 0.5V
Industrial
Output Current into Outputs (LOW) ............................ 90 mA
Notes
19. The voltage on any input or I/O pin can not exceed the power pin during power up.
20. Pulse width < 20 ns.
Document Number: 001-00217 Rev. *K
Page 11 of 33
CYDM064B16
CYDM128B16
CYDM256B16
Electrical Characteristics for VCC = 1.8 V
Over the Operating Range
CYDM256B16/CYDM128B16/CYDM064B16
Parameter
VOH
VOL
VOL ODR
VIH
VIL
IOZ
ICEX ODR
IIX
Description
-55
Unit
P1 I/O Voltage P2 I/O Voltage
Min
Typ
Max
Output HIGH Voltage (IOH = –100 A)
1.8 V (any port)
VDDIO – 0.2
–
–
V
Output HIGH Voltage (IOH = –2 mA)
2.5 V (any port)
2.0
–
–
V
Output HIGH Voltage (IOH = –2 mA)
3.0 V (any port)
2.1
–
–
V
Output LOW Voltage (IOL = 100 A
1.8 V (any port)
–
–
0.2
V
Output HIGH Voltage (IOL = 2 mA)
2.5 V (any port)
–
–
0.4
V
Output HIGH Voltage (IOL = 2 mA)
3.0 V (any port)
–
–
0.4
V
ODR Output LOW Voltage (IOL = 8 mA
1.8 V (any port)
–
–
0.2
V
2.5 V (any port)
–
–
0.2
V
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
ODR Output Leakage Current. VOUT = VDDIO
Input Leakage Current
Document Number: 001-00217 Rev. *K
3.0 V (any port)
–
–
0.2
V
1.8 V (any port)
1.2
–
VDDIO + 0.2
V
2.5 V (any port)
1.7
–
VDDIO + 0.3
V
3.0 V (any port)
2.0
–
VDDIO + 0.2
V
1.8 V (any port)
–0.2
–
0.4
V
2.5 V (any port)
–0.3
–
0.6
V
3.0 V (any port)
–0.2
–
0.7
V
1.8 V
1.8 V
–1
–
1
A
2.5 V
2.5 V
–1
–
1
A
3.0 V
3.0 V
–1
–
1
A
1.8 V
1.8 V
–1
–
1
A
2.5 V
2.5 V
–1
–
1
A
3.0 V
3.0 V
–1
–
1
A
1.8 V
1.8 V
–1
–
1
A
2.5 V
2.5 V
–1
–
1
A
3.0 V
3.0 V
–1
–
1
A
Page 12 of 33
CYDM064B16
CYDM128B16
CYDM256B16
Electrical Characteristics for VCC = 1.8 V (continued)
Over the Operating Range
CYDM256B16/CYDM128B16/CYDM064B16
Parameter
Description
-55
P1 I/O Voltage P2 I/O Voltage
Unit
Min
Typ
Max
–
15
25
mA
ICC
Operating Current
(VCC = Max., IOUT = 0 mA),
Outputs Disabled
Industrial
1.8 V
1.8 V
ISB1
Standby Current
(Both Ports TTL Level)
CEL and CER VCC – 0.2,
SEML = SEMR = VCC – 0.2,
f = fMAX
Industrial
1.8 V
1.8 V
2
6
A
ISB2
Standby Current
(One Port TTL Level)
CEL | CER VIH, f = fMAX
Industrial
1.8 V
1.8 V
8.5
14
mA
ISB3
Standby Current
(Both Ports CMOS Level)
CEL and CER VCC 0.2,
SEML and SEMR > VCC – 0.2,
f=0
Industrial
1.8 V
1.8 V
2
6
A
ISB4
Standby Current
(One Port CMOS Level)
CEL | CER VIH,
f = fMAX[21]
Industrial
1.8 V
1.8 V
8.5
14
mA
Notes
21. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
Document Number: 001-00217 Rev. *K
Page 13 of 33
CYDM064B16
CYDM128B16
CYDM256B16
Electrical Characteristics for VCC = 2.5 V
Over the Operating Range
CYDM256B16, CYDM128B16, CYDM064B16
Parameter
Description
-55
Unit
P1 I/O Voltage P2 I/O Voltage
Min
Typ
Max
–
VOH
Output HIGH Voltage (IOH = –2 mA)
2.5 V (any port)
2.0
–
3.0 V (any port)
2.1
–
–
V
VOL
Output LOW Voltage (IOL = 2 mA
2.5 V (any port)
–
–
0.4
V
3.0 V (any port)
–
–
0.4
V
2.5 V (any port)
–
–
0.2
V
VOL ODR
ODR Output LOW Voltage (IOL = 8 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IOZ
Output Leakage Current
V
3.0 V (any port)
–
–
0.2
V
2.5 V (any port)
1.7
–
VDDIO + 0.3
V
3.0 V (any port)
2.0
–
VDDIO + 0.2
V
2.5 V (any port)
–0.3
–
0.6
V
3.0 V (any port)
–0.2
–
0.7
V
2.5 V
2.5 V
–1
–
1
A
3.0 V
3.0 V
–1
–
1
A
2.5 V
–1
–
1
A
ICEX ODR
ODR Output Leakage Current. VOUT = VCC
2.5 V
3.0 V
3.0 V
–1
–
1
A
IIX
Input Leakage Current
2.5 V
2.5 V
–1
–
1
A
3.0 V
3.0 V
–1
–
1
A
ICC
Operating Current
(VCC = Max., IOUT = 0 mA),
Outputs Disabled
Industrial
2.5 V
2.5 V
–
28
40
mA
ISB1
Standby Current
(Both Ports TTL Level)
CEL and CER VCC – 0.2,
SEML= SEMR = VCC – 0.2,
f = fMAX
Industrial
2.5 V
2.5 V
–
6
8
A
ISB2
Standby Current
(One Port TTL Level)
CEL | CER VIH,
f = fMAX
Industrial
2.5 V
2.5 V
18
25
mA
ISB3
Standby Current
(Both Ports CMOS Level)
CEL and CER VCC 0.2,
SEML and SEMR > VCC – 0.2,
f=0
Industrial
2.5 V
2.5 V
4
6
A
ISB4
Standby Current
(One Port CMOS Level)
CEL | CER VIH,
f = fMAX[22]
Industrial
2.5 V
2.5 V
18
25
mA
Notes
22. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
Document Number: 001-00217 Rev. *K
Page 14 of 33
CYDM064B16
CYDM128B16
CYDM256B16
Electrical Characteristics for VCC = 3.0 V
Over the Operating Range
CYDM256B16/CYDM128B16/CYDM064B16
Parameter
Description
-55
Unit
P1 I/O Voltage P2 I/O Voltage
Min
Typ
Max
VOH
Output HIGH Voltage (IOH = –2 mA)
3.0 V (any port)
2.1
–
–
V
VOL
Output LOW Voltage (IOL = 2 mA
3.0 V (any port)
–
–
0.4
V
VOL ODR
ODR Output LOW Voltage (IOL = 8 mA
3.0 V (any port)
–
–
0.2
V
VIH
Input HIGH Voltage
3.0 V (any port)
2.0
–
VDDIO + 0.2
V
VIL
Input LOW Voltage
3.0 V (any port)
–0.2
–
0.7
V
IOZ
Output Leakage Current
3.0 V
3.0 V
–1
–
1
A
ICEX ODR
ODR Output Leakage Current. VOUT = VCC
3.0 V
3.0 V
–1
–
1
A
IIX
Input Leakage Current
3.0 V
3.0 V
–1
–
1
A
ICC
Operating Current
(VCC = Max., IOUT = 0 mA),
Outputs Disabled
Industrial
3.0 V
3.0 V
–
42
60
mA
ISB1
Standby Current
(Both Ports TTL Level)
CEL and CER VCC – 0.2,
SEML = SEMR = VCC – 0.2,
f = fMAX
Industrial
3.0 V
3.0 V
7
10
A
ISB2
Standby Current
(One Port TTL Level)
CEL | CER VIH,
f = fMAX
Industrial
3.0 V
3.0 V
25
35
mA
ISB3
Standby Current
(Both Ports CMOS Level)
CEL and CER VCC 0.2,
SEML and SEMR > VCC – 0.2,
f=0
Industrial
3.0 V
3.0 V
6
8
A
ISB4
Standby Current (One Port CMOS Industrial
Level)
CEL | CER VIH,
f = fMAX[23]
3.0 V
3.0 V
25
35
mA
Notes
23. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
Document Number: 001-00217 Rev. *K
Page 15 of 33
CYDM064B16
CYDM128B16
CYDM256B16
Capacitance
Parameter [24]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz,
VCC = 3.0 V
Max
Unit
9
pF
10
pF
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.0V/2.5V/1.8V
3.0V/2.5V/1.8V
R1
OUTPUT
OUTPUT
C = 30 pF
RTH = 6 k
R1
OUTPUT
C = 30 pF
R2
VTH = 0.8V
(a) Normal Load
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
3.0V/2.5V
1.8V
R1
1022
13500
R2
792
10800
1.8V
GND
10%
90%
3 ns
C = 5 pF
R2
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, and tLZWE
including scope and jig)
90%
10%
3 ns
Note
24. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-00217 Rev. *K
Page 16 of 33
CYDM064B16
CYDM128B16
CYDM256B16
Switching Characteristics for VCC = 1.8 V
Over the Operating Range
CYDM256B16/CYDM128B16/CYDM064B16
Parameter
[23]
Description
-55
Unit
Min
Max
Read Cycle
tRC
Read Cycle Time
55
–
ns
tAA
Address to Data Valid
–
55
ns
tOHA
Output Hold From Address Change
5
–
ns
tACE[24]
CE LOW to Data Valid
–
55
ns
tDOE
OE LOW to Data Valid
–
30
ns
OE Low to Low Z
5
–
ns
OE HIGH to High Z
–
25
ns
CE LOW to Low Z
5
–
ns
CE HIGH to High Z
–
25
ns
CE LOW to Power up
0
–
ns
CE HIGH to Power down
–
55
ns
Byte Enable Access Time
–
55
ns
tWC
Write Cycle Time
55
–
ns
tSCE[24]
CE LOW to Write End
45
–
ns
tAW
Address Valid to Write End
45
–
ns
tHA
Address Hold From Write End
0
–
ns
tSA[24]
Address Setup to Write Start
0
–
ns
tPWE
Write Pulse Width
40
–
ns
tSD
Data Setup to Write End
30
–
ns
tHD
Data Hold From Write End
0
–
ns
tHZWE[26, 27]
tLZWE[26, 27]
tWDD[28]
tDDD[28]
R/W LOW to High Z
–
25
ns
R/W HIGH to Low Z
0
–
ns
Write Pulse to Data Delay
–
80
ns
Write Data Valid to Read Data Valid
–
80
ns
tLZOE
[25, 26, 27]
tHZOE[25, 26, 27]
tLZCE[25, 26, 27]
tHZCE[25, 26, 27]
tPU[27]
tPD[27]
tABE[24]
Write Cycle
Notes
23. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified IOI/IOH
and 30 pF load capacitance.
24. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
25. At any temperature and voltage condition for any device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
26. Test conditions used are Load 3.
27. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy
waveform.
28. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
Document Number: 001-00217 Rev. *K
Page 17 of 33
CYDM064B16
CYDM128B16
CYDM256B16
Switching Characteristics for VCC = 1.8 V (continued)
Over the Operating Range
CYDM256B16/CYDM128B16/CYDM064B16
Parameter
[23]
Description
-55
Unit
Min
Max
Busy Timing[29]
tBLA
BUSY LOW from Address Match
–
45
ns
tBHA
BUSY HIGH from Address Mismatch
–
45
ns
tBLC
BUSY LOW from CE LOW
–
45
ns
tBHC
BUSY HIGH from CE HIGH
–
45
ns
tPS[30]
Port Setup for Priority
5
–
ns
tWB
R/W HIGH after BUSY (Slave)
0
–
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
35
–
ns
BUSY HIGH to Data Valid
–
40
ns
tBDD[31]
Interrupt
Timing[29]
tINS
INT Set Time
–
45
ns
tINR
INT Reset Time
–
45
ns
Semaphore Timing
tSOP
SEM Flag Update Pulse (OE or SEM)
15
–
ns
tSWRD
SEM Flag Write to Read Time
10
–
ns
tSPS
SEM Flag Contention Window
10
–
ns
tSAA
SEM Address Access Time
–
55
ns
Notes
29. Test conditions used are Load 2.
30. Add 2 ns to this parameter if VCC and VDDIOR are 2.5 V at temperature
