CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
®
16k/8k/4k x 16 MoBL ADM
Asynchronous Dual-Port Static RAM
Features
■
True dual-ported memory block that allow simultaneous
independent access
❐ One port with dedicated time multiplexed address and data
(ADM) interface
❐ One port configurable to standard SRAM or time multiplexed
address and data interface
■
16k/8k/4k × 16 memory configuration
■
High speed access
❐ 65 ns or 90 ns ADM interface
❐ 40 ns or 60 ns standard SRAM interface
■
Fully asynchronous operation
■
Port independent 1.8V, 2.5V, and 3.0V IOs
■
Ultra low operating power
❐ Active: ICC = 15 mA (typical) at 90 ns
❐ Active: ICC = 25 mA (typical) at 65 ns
❐ Standby: ISB3 = 2 A (typical)
■
Port independent power down
■
On-chip arbitration logic
■
Mailbox interrupt for port to port communication
■
Input Read and Output Drive registers
■
Upper byte and lower byte control
■
Small package: 6x6 mm, 100-ball Pb-free BGA
■
Industrial temperature range
Block Diagram
SFEN#
I/OL15-I/OL8
I/OL7-I/OL0
ADV#L
UB#L
LB#L
DataL
Mux'ed
Address /
Data
I/O Control
IRR1-IRR0 [note 2]
ODR4-ODR0
IRR/ODR
DataR
Dual Ported
Memory Array
16k/8k/4k x 16
AddrL
Mux'ed
Address/
Data
I/O Control
AddrR
I/OR15-I/OR8
I/OR7-I/OR0
ADV#R
UB#R
LB#R
A13-A0 [note 1]
Address
Decode
CS#L
OE#L
WE#L
Address
Decode
MSEL
CS#R
OE#R
WE#R
Control Logic
BUSY#L
INT#L
BUSY#R
INT#R
Notes
1. A13-A0 for CYDMX256A16 and CYDMX256B16; A12-A0 for CYDMX128A16 and CYDMX128B16; and A11-A0 for CYDMX064A16 and CYDMX064B16.
2. IRR1 and IRR2 not available for CYDMX256A16 and CYDMX256B16.
Cypress Semiconductor Corporation
Document #: 001-08090 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-260
Revised October 8, 2010
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Contents
Pin Configurations ................................................................ 3
Electrical Characteristics for VCC = 1.8V ............................ 8
Pin Definitions ....................................................................... 4
Electrical Characteristics for VCC = 2.5V .......................... 10
Functional Description .......................................................... 4
Power Supply ................................................................... 4
ADM Interface Read or Write Operation .......................... 4
Standard SRAM Interface Read or Write Operation ........ 5
Byte Select Operation ...................................................... 5
Chip Select Operation ...................................................... 5
Output Enable Operation .................................................. 5
Mailbox Interrupts ............................................................. 5
Arbitration Logic ............................................................... 5
Input Read Register ......................................................... 5
Output Drive Register ....................................................... 5
Electrical Characteristics for 3.0V ..................................... 11
Architecture ........................................................................... 6
Maximum Ratings .................................................................. 8
Capacitance ......................................................................... 11
Switching Characteristics for VCC = 1.8V ......................... 12
Switching Waveforms ......................................................... 15
Ordering Information ........................................................... 21
Ordering Code Definitions .............................................. 21
Package Diagram ................................................................. 22
Document History Page ...................................................... 23
Sales, Solutions, and Legal Information ........................... 24
Worldwide Sales and Design Support ............................ 24
Products ......................................................................... 24
PSoC Solutions .............................................................. 24
Operating Range .................................................................... 8
Document #: 001-08090 Rev. *E
Page 2 of 24
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Pin Configurations
Figure 1. 100-Ball 0.5 mm Pitch BGA (Top View)
1
2
3
4
5
6
7
8
9
10
A
A5
A8
A11
UB#R
VSS
ADV#R
I/OR15
I/OR12
I/OR10
VSS
A
B
A3
A4
A7
A9
CE#R
WE#R
OE#R
VDDIOR
I/OR9
I/OR6
B
C
A0
A1
A2
A6
LB#R
IRR1[3]
I/OR14
I/OR11
I/OR7
VSS
C
D
ODR4
ODR2 BUSY#R INT#R
A10
A12[4]
I/OR13
I/OR8
I/OR5
I/O2R
D
E
VSS
DNU
ODR3
INT#L
VSS
VSS
I/OR4
VDDIOR
I/OR1
VSS
E
ODR1
BUSY#L
DNU
VCC
VSS
I/OR3
I/OR0
I/OL15 VDDIOL F
F SFEN#
G
ODR0
DNU
DNU
DNU
OE#L
I/OL3
I/OL11
I/OL12
I/OL14
I/OL13 G
H
DNU
DNU
DNU
LB#L
CE#L
I/OL1
VDDIOL
MSEL
DNU
I/OL10 H
J
DNU
DNU
DNU
IRR0[5]
VCC
VSS
I/OL4
I/OL6
I/OL8
I/OL9
J
K
DNU
DNU
DNU
UB#L
ADV#L
WE#L
I/OL0
I/OL2
I/OL5
I/OL7
K
1
2
3
4
5
6
7
8
9
10
.
Notes
3. This pin is A13 for CYDMX256A16 and CYDMX256B16.
4. This pin is DNU for CYDMX064A16 and CYDMX064B16.
5. This pin is DNU for CYDMX256A16 and CYDMX256B16.
6. DNU pins are “do not use” pins. No trace or power component can be connected to these pins.
Document #: 001-08090 Rev. *E
Page 3 of 24
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Pin Definitions
Left Port
Right Port
Description
CS#L
CS#R
Chip Select
WE#L
WE#R
Read/Write Enable
OE#R
Output Enable
OE#L
A0–A13
MSEL
IOL0–IOL15
IOR0–IOR15
ADV#L
ADV#R
UB#L
UB#R
Address (A0–A11 for 4k device; A0–A12 for 8k device; A0–A13 for 16k device)
Right Port Interface Mode Select (0: Standard SRAM; 1: Address/Data Mux)
Address/Data Bus Input/Output
Address Latch Enable; ADV#R only use when R-port is in ADM mode
Upper Byte Select (IO8–IO15)
LB#L
LB#R
Lower Byte Select (IO0–IO7)
INT#L
INT#R
Interrupt Flag
BUSY#L
BUSY#R
SFEN#
IRR0-IRR1
ODR0-ODR4
Busy Flag
Special Function Enable Signal
Input Signals for Input Read Registers for CYDM128A16, CYDM128B16,
CYDMX064A16 and CYDMX064B16;
IRR0 is DNU and IRR1 is A13 for CYDMX256A16 and CYDMX256B16
Output Signals for Output Drive Registers; These are open drained outputs
VCC
Core Power Supply
GND
Ground
VDDIOL
Left Port IO Power Supply
VDDIOR
Right Port IO Power Supply
DNU
No Connect; Do not connect trace or power component to these pins
Functional Description
The CYDMX256A16, CYDMX128A16, CYDMX064A16,
CYDMX256B16, CYDMX128B16, and CYDMX064B16 are low
power CMOS 16k/8k/4k x 16 dual-port static RAMs. The two
ports are: one dedicated time multiplexed address and data
(ADM) interface and one configurable standard SRAM or ADM
interface. The two ports permit independent, asynchronous read
and write access to any memory locations. Each port has
independent control pins: Chip Select (CS#), Write Enable
(WE#), and Output Enable (OE#). Two output flags are provided
on each port (BUSY# and INT#). BUSY# flag is triggered when
the port is trying to access the same memory location currently
being accessed by the other port. The Interrupt flag (INT#)
permits communication between ports or systems by means of
a mailbox. Power down feature is controlled independently on
each port by a Chip Select (CS#) pin.
The CYDMX256A16, CYDMX128A16, CYDMX064A16,
CYDMX256B16, CYDMX128B16, and CYDMX064B16 are
available in 100-ball 0.5-mm pitch Ball Grid Array (BGA)
packages. Application areas include interprocessor and multiprocessor designs, communications status buffering, and
dual-port video and graphics memory.
Power Supply
connected to the VDDIOL and VDDIOR pins. The supported IO
standards are 1.8V and 2.5V LVCMOS and 3.0V LVTTL.
ADM Interface Read or Write Operation
This description is applicable to both the left ADM port and right
port configured as an ADM port.
Three control signals, ADV#, WE#, and CS# are used to perform
the read and write operations. Address signals are first applied
to the IO bus along with CS# LOW. The addresses are loaded
from the IO bus in response to the rising edge of the Address
Latch Enable (ADV#) signal. It is necessary to meet the setup
(tAVDS) and hold (tAVDH) times given in the AC specifications with
valid address information to properly latch the addresses.
After the address signals are latched in, a read operation is
issued when WE# stays HIGH. The IO bus becomes High-Z
when the address signals meet tAVDH. The read data is driven on
the IO bus tOE after the OE# is asserted LOW, and held until
tHZOE or tHZCS after the rising edge of OE# or CS#, whichever
comes first.
A write operation is issued when WE# is asserted LOW. The
write data is applied to the IO bus right after address meets the
hold time (tAVDH). And write data is written with the rising edge
of either WE# or CS#, whichever comes first, and meets data
setup (tSD) and hold (tHD) times.
The core voltage (VCC) can be 1.8V, 2.5V, or 3.0V, as long as it
is lower than or equal to the IO voltage. Each port operates on
independent IO voltages. This is determined by what is
Document #: 001-08090 Rev. *E
Page 4 of 24
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Standard SRAM Interface Read or Write Operation
This description is applicable to the right access port configured
as standard SRAM port. Read and write operations with
standard SRAM interface configuration is the same as the ADM
port except addresses are presented on the A bus. Operation is
controlled by CS#, OE#, and WE#. A read operation is issued
when WE# is asserted HIGH. A write operation is issued when
WE# is asserted LOW. The IO bus is the destination for read data
and the source for write data when the read operation is issued.
However, write data must be driven to IO when the write
operation is issued.
Byte Select Operation
resets when the owner reads the contents of its own mailbox.
The message written to the mailbox is user defined.
Each port reads the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and resetting the interrupt to it.
On power up, both interrupts are set by default. An initialization
program must be run to reset the interrupts.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The fundamental word size is 16 bits. Each word is broken up
into two 8-bit bytes. Each port has two active LOW byte enables:
UB# and LB#. Activating or deactivating the byte enables alters
the result of read and write operations to the port. During a write,
byte enable asserted HIGH inhibits the corresponding byte to be
updated in the addressed memory location. During a read, both
byte enables are inputs to the asynchronous output enable
control logic. When a byte enable is asserted HIGH, the corresponding data byte is tri-stated. Subsequently, when the byte
enable is asserted LOW, the corresponding data byte is driven
with the read data.
Arbitration Logic
Chip Select Operation
Input Read Register
Each port has one active LOW chip select signal, CS#. CS# must
be asserted LOW for the port to be considered active. To issue
a valid read or write operation, the chip select input must be
asserted LOW throughout the read or write cycle. When CS# is
deasserted HIGH during a write, if tWRL, tSD, and tHD are not met,
the contents of the addressed location is not altered.
The Input Read Register (IRR) feature is available only for
CYDMX128A16, CYDMX128B16, CYDMX064A16, and
CYDMX064B16 devices. When SFEN# = VIL, the IRR captures
the status of two external devices connected to the Input Read
pins (IRR0 and IRR1) to address location 0x0000. Address
0x0000 is not available for standard memory accesses when
SFEN# = VIL. When SFEN# = VIH, address 0x0000 is available
for normal memory accesses. Either port accesses the contents
of IRR with normal read operation from address 0x0000. During
reads from the IRR, IO are valid bits and IO are
don’t care. The IRR inputs are 1.8V and 2.5V LVCMOS or 3.0V
LVTTL, depending on the core voltage supply (VCC).
An automatic power down feature controlled by deactivating the
chip select (CS# HIGH) permits the on-chip circuitry of each port
to enter a very low standby power mode.
Output Enable Operation
Each port has one output enable signal, OE#. When OE# is
asserted HIGH, IO bus is tri-stated after tHZOE. When OE# is
asserted LOW, control of the IO bus is assumed by the
asynchronous output enable logic (the logic is controlled by
inputs WE#, CS#, UB#, and LB#).
Mailbox Interrupts
The upper two memory locations are used for message passing.
The highest memory location (0xFFF for CYDMX064A16 and
CYDMX064B16, 0x1FFF for CYDMX128A16 and CYDMX128B16,
and 0x3FFF for CYDMX256A16 and CYDMX256B16) is the
mailbox for the right port. The second highest memory location
(0xFFE for CYDMX064A16 and CYDMX064B16, 0x1FFE for
CYDMX128A16 and CYDMX128B16, and 0x3FFE for
CYDMX256A16 and CYDMX256B16) is the mailbox for the left
port. When one port writes to the opposite port’s mailbox, an
interrupt signal is generated to the opposite port. The interrupt
Document #: 001-08090 Rev. *E
The CYDMX256A16, CYDMX128A16, CYDMX064A16,
CYDMX256B16, CYDMX128B16, and CYDMX064B16 provide
on-chip arbitration to resolve simultaneous memory location
access (collision). If both ports’ CS# signals are asserted and an
address match occurs within each other, the busy logic determines which port has access. If tPS is violated, one of the two
ports gains permission to the location, but it is not predictable
which port gets the permission. BUSY# is asserted tBLA after an
address match or tBLC after CS# is taken LOW.
Output Drive Register
The Output Drive Register (ODR) determines the state of up to
five external binary state devices by providing a path to VSS for
the external circuit. These outputs are open drain. The five
external devices operates at different voltages (1.5V VDDIO
3.5V) but the combined current cannot exceed 40 mA (8 mA
maximum for each external device). The status of the ODR bits
are set using standard write accesses from either port to address
0x0001 with a ‘1’ corresponding to on and ‘0’ corresponding to
off. The status of the ODR bits are read with a normal read
access to address 0x0001. When SFEN# = VIL, the ODR is
active and address 0x0001 is not available for memory
accesses. When SFEN# = VIH, the ODR is inactive and address
0x0001 is used for standard accesses. During reads and writes
to ODR, IO are valid and IO are don’t care.
Page 5 of 24
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Architecture
The CYDMX256A16, CYDMX128A16, CYDMX064A16,
CYDMX256B16, CYDMX128B16, and CYDMX064B16 consist
of an array of 16k, 8k, and 4k words of 16 dual-ported SRAM
cells, IO, address lines, and control signals (CS#, ADV#, OE#,
and WE#). Between the two access ports, one is a dedicated
time multiplexed address and data interface; the other is a pin
selectable port to either standard SRAM or time multiplexed
address and data interface. Independent control signals for each
port permit simultaneous access to any location in memory. To
handle the situation of writing and reading to the same location,
a BUSY# pin is provided on each port. For port to port communication, an Interrupt (INT#) pin is also available on each port.
Table 1. ADM Interface Read/Write with Byte Select Operations
ADV#
CS#
WE#
OE#
UB#
LB#
X
H
X
X
X
X
High-Z
IO0 - IO15
Deselected or power down
Mode
X
X
X
H
X
X
High-Z
Output disable
X
X
X
X
H
H
High-Z
Upper and lower byte
deselected
Pulse
L
H
L
L
L
Data Out (IO0-IO15)
Read upper and lower bytes
Pulse
L
H
L
H
L
Data Out (IO0-IO7)
High-Z (IO8-IO15)
Read lower byte only
Pulse
L
H
L
L
H
High-Z (IO0-IO7)
Data Out (IO8-IO15)
Read upper byte only
Pulse
L
L
X
L
L
Data In (IO0-IO15)
Write upper and lower bytes
Pulse
L
L
X
H
L
Data In (IO0-IO7)
High-Z (IO8-IO15)
Write lower byte only
Pulse
L
L
X
L
H
High-Z (IO0-IO7)
Data In (IO8-IO15)
Write upper byte only
Table 2. Standard SRAM Interface Read/Write with Byte Select Operations
CS#
WE#
OE#
UB#
LB#
IO0-IO15
Mode
H
X
X
X
X
High-Z
Deselected or power down
X
X
H
X
X
High-Z
Output disable
X
X
X
H
H
High-Z
Upper and lower byte deselected
L
H
L
L
L
Data Out (IO0-IO15)
Read upper and lower bytes
L
H
L
H
L
Data Out (IO0-IO7)
High-Z (IO8-IO15)
Read lower byte only
L
H
L
L
H
High-Z (IO0-IO7)
Data Out (IO8-IO15)
Read upper byte only
L
L
X
L
L
Data In (IO0-IO15)
Write upper and lower bytes
L
L
X
H
L
Data In (IO0-IO7)
High-Z (IO8-IO15)
Write lower byte only
L
L
X
L
H
High-Z (IO0-IO7)
Data In (IO8-IO15)
Write upper byte only
Document #: 001-08090 Rev. *E
Page 6 of 24
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Table 3. Interrupt Operation Example (Assumes BUSY#L = BUSY#R = HIGH)
Left Port
Function
WE#L CS#L OE#L
Set Right INT#R Flag
L
L
Right Port
AddressL
X
0x3FFF
INT#L WE#R CS#R OE#R
[7]
X
X
X
AddressR
INT#R
X
X
L
H
Reset Right INT#R Flag
X
X
X
X
X
X
L
L
0x3FFF[7]
Set Left INT#L Flag
X
X
X
X
L
L
L
X
0x3FFE[8]
X
H
X
X
X
X
X
Reset Left INT#L Flag
X
L
L
0x3FFE
[8]
Table 4. Arbitration Winning Port
CS#L
CS#R
Address Match
Left/Right Port
BUSY#L
BUSY#R
Function
X
X
No Match
H
H
Normal
H
X
Match
H
H
Normal
X
H
Match
H
H
Normal
Match
Note[9]
Note[9]
L
L
See
See
Write Inhibit[10]
Table 5. Input Read Register Operation[11]
SFEN#
CS#
WE#
OE#
UB#
LB#
H
L
H
L
L
L
ADDR
IO0–IO1
IO2–IO15
L
L
H
L
X
L
x0000
VALID[13]
X
Mode
x0000-Max VALID[12] VALID[12] Standard Memory Access
IRR Read
Table 6. Output Drive Register[15]
SFEN#
CS#
WE#
OE#
UB#
LB#
ADDR
IO0–IO4
IO5–IO15
L[12]
L[12]
VALID[12]
Mode
H
L
H
X[16]
x0000-Max
VALID[12]
L
L
L
X
X
L
x0001
VALID[13]
X
ODR Write[17]
L
L
H
L
X
L
x0001
VALID[13]
X
ODR Read
Standard Memory Access
Notes
7. 0x3FFF for CYDMX256A16 and CYDMX256B16, 0x1FFF for CYDMX128A16 and CYDMX128B16, 0xFFF for CYDMX064A16 and CYDMX064B16.
8. 0x3FFE for CYDMX256A16 and CYDMX256B16, 0x1FFE for CYDMX128A16 and CYDMX128B16, 0xFFE for CYDMX064A16 and CYDMX064B16.
9. If it meets tPS, "L" if the CS# and address of the opposite port become stable BEFORE the current port; "H" if the CS# and address of the opposite port become
stable AFTER the current port. If tPS is not met, either BUSY#L or BUSY#R results “L”. BUSY#L and BUSY#R cannot be “L” simultaneously.
10. Write operations to the left port are internally ignored when BUSY#L is driving LOW regardless of actual logic level on the pin; Write operations to the right port
are internally ignored when BUSY#R is driving LOW regardless of actual logic level on the pin.
11. SFEN# = VIL for IRR reads.
12. UB# or LB# = VIL. If LB# = VIL, then IO are valid. If UB# = VIL then IO are valid.
13. LB# must be active (LB# = VIL) for these bits to be valid.
14. SFEN# active when either CS#L = VIL or CS#R = VIL. It is inactive when CS#L = CS#R = VIH.
15. SFEN# = VIL for ODR reads and writes.
16. Output enable must be low (OE# = VIL) during reads for valid data to be output.
17. During ODR writes data is also written to the memory.
Document #: 001-08090 Rev. *E
Page 7 of 24
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
DC Input Voltage[19]............................... –0.5V to VCC + 0.5V
Maximum Ratings
Output Current into Outputs (LOW)............................. 90 mA
Exceeding maximum ratings[18] may shorten the useful life of the
device. User guidelines are not tested.
Static Discharge Voltage.......................................... > 2000V
Storage Temperature ................................. –65°C to +150°C
Latch up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Range
Supply Voltage to Ground Potential................–0.5V to +3.3V
Ambient Temperature
VCC
–40°C to +85°C
1.8V ± 100 mV
2.5V ± 100 mV
3.0V ± 300 mV
Industrial
DC Voltage Applied to
Outputs in High-Z State ......................... –0.5V to VCC + 0.5V
Parameter
Electrical Characteristics for VCC = 1.8V Over the Operating Range
VOH
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16
–65
–65
–90
Description
Unit
P1 IO P2 IO
Voltage Voltage
Min
Output HIGH Voltage
(IOH = –100 A)
1.8V (any port)
VDDIO
– 0.2
VDDIO
– 0.2
VDDIO
– 0.2
V
Output HIGH Voltage (IOH = –2 mA)
2.5V (any port)
2.0
2.0
2.0
V
Output HIGH Voltage (IOH = –2 mA)
3.0V (any port)
2.1
Typ
Max
Min
Typ
Max
2.1
Min
Typ Max
2.1
V
Output LOW Voltage (IOL = 100 A 1.8V (any port)
0.2
0.2
0.2
V
Output HIGH Voltage (IOH = 2 mA)
2.5V (any port)
0.4
0.4
0.4
V
Output HIGH Voltage (IOH = 2 mA)
3.0V (any port)
0.4
0.4
0.4
V
VOL
ODR
ODR Output LOW Voltage
(IOL = 8 mA
1.8V (any port)
0.2
0.2
0.2
V
2.5V (any port)
0.2
0.2
0.2
V
0.2
V
VIH
Input HIGH Voltage
1.8V (any port)
1.2
VDDIO
+ 0.2
1.2
VDDIO
+ 0.2
1.2
VDDIO
+ 0.2
V
2.5V (any port)
1.7
VDDIO
+ 0.3
1.7
VDDIO
+ 0.3
1.7
VDDIO
+ 0.3
V
3.0V (any port)
2.0
VDDIO
+ 0.2
2.0
VDDIO
+ 0.2
2.0
VDDIO
+ 0.2
V
1.8V (any port)
–0.2
0.4
–0.2
0.4
–0.2
0.4
V
2.5V (any port)
–0.3
0.6
–0.3
0.6
–0.3
0.6
V
3.0V (any port)
–0.2
0.7
–0.2
0.7
–0.2
0.7
V
VOL
3.0V (any port)
VIL
IOZ
ICEX
ODR
Input LOW Voltage
Output Leakage Current
ODR Output Leakage Current.
VOUT = VDDIO
0.2
0.2
1.8V
1.8V
–1
1
–1
1
–1
1
A
2.5V
2.5V
–1
1
–1
1
–1
1
A
3.0V
3.0V
–1
1
–1
1
–1
1
A
1.8V
1.8V
–1
1
–1
1
–1
1
A
2.5V
2.5V
–1
1
–1
1
–1
1
A
3.0V
3.0V
–1
1
–1
1
–1
1
A
Notes
18. The voltage on any input or IO pin cannot exceed the power pin during power up.
19. Pulse width < 20 ns.
Document #: 001-08090 Rev. *E
Page 8 of 24
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Parameter
Electrical Characteristics for VCC = 1.8V Over the Operating Range (continued)
IIX
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16
–65
–65
–90
Description
P1 IO P2 IO
Voltage Voltage
Input Leakage Current
Min
Typ
Max
Min
Typ
Max
Min
Unit
Typ Max
1.8V
1.8V
–1
1
–1
1
–1
1
A
2.5V
2.5V
–1
1
–1
1
–1
1
A
3.0V
3.0V
–1
1
–1
1
–1
1
A
ICC
Operating Current (VCC = Max., Ind
IOUT = 0 mA) Outputs Disabled .
1.8V
1.8V
25
40
25
40
15
25
mA
ISB1
Standby Current (Both Ports
TTL Level) CE#L and CE#R
VCC – 0.2, f = fMAX
Ind
.
1.8V
1.8V
2
6
2
6
2
6
A
ISB2
Standby Current (One Port TTL Ind
Level) CE#L or CE#R VIH, f = .
fMAX
1.8V
1.8V
8.5
18
8.5
18
8.5
14
mA
ISB3
Standby Current (Both Ports
Ind
CMOS Level) CE#L and CE#R .
VCC 0.2V, f = 0
1.8V
1.8V
2
6
2
6
2
6
A
ISB4
Standby Current (One Port
Ind
CMOS Level) CE#L or CE#R .
VIH, f = fMAX[20]
1.8V
1.8V
8.5
18
8.5
18
8.5
14
mA
Note
20. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
standby ISB3.
Document #: 001-08090 Rev. *E
Page 9 of 24
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Parameter
Electrical Characteristics for VCC = 2.5V Over the Operating Range
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16
–65
–65
–90
Description
P1 IO
P2 IO
Voltage Voltage
Min
Typ
Max
Min
Typ
Max
Min
Typ
Unit
Max
VOH
Output HIGH Voltage (IOH =
–2 mA)
2.5V (any port)
2.0
3.0V (any port)
2.1
VOL
Output LOW Voltage (IOL = 2
mA
2.5V (any port)
0.4
0.4
0.4
V
3.0V (any port)
0.4
0.4
0.4
V
2.0
2.0
2.1
V
2.1
V
VOL
ODR
ODR Output LOW Voltage
(IOL = 8 mA
2.5V (any port)
0.2
0.2
0.2
V
3.0V (any port)
0.2
0.2
0.2
V
VIH
Input HIGH Voltage
2.5V (any port)
1.7
VDDIO
+ 0.3
1.7
VDDIO
+ 0.3
1.7
VDDIO
+ 0.3
V
3.0V (any port)
2.0
VDDIO
+ 0.2
2.0
VDDIO
+ 0.2
2.0
VDDIO
+ 0.2
V
2.5V (any port)
–0.3
0.6
–0.3
0.6
–0.3
0.6
V
3.0V (any port)
–0.2
0.7
–0.2
0.7
–0.2
0.7
V
VIL
IOZ
Input LOW Voltage
Output Leakage Current
2.5V
2.5V
–1
1
–1
1
–1
1
A
3.0V
3.0V
–1
1
–1
1
–1
1
A
ICEX
ODR
ODR Output Leakage
Current. VOUT = VCC
2.5V
2.5V
–1
1
–1
1
–1
1
A
3.0V
3.0V
–1
1
–1
1
–1
1
A
IIX
Input Leakage Current
2.5V
2.5V
–1
1
–1
1
–1
1
A
3.0V
3.0V
–1
1
–1
1
–1
1
A
ICC
Operating Current (VCC Ind.
= Max., IOUT = 0 mA)
Outputs Disabled
2.5V
2.5V
39
55
39
55
28
40
mA
ISB1
Standby Current (Both Ind.
Ports TTL Level) CE#L
and CE#R VCC – 0.2,
f=fMAX
2.5V
2.5V
6
8
6
8
6
8
A
ISB2
Standby Current (One Ind.
Port TTL Level) CE#L
or CE#R VIH, f = fMAX
2.5V
2.5V
21
30
21
30
18
25
mA
ISB3
Standby Current (Both Ind.
Ports CMOS Level)
CE#L and CE#R
VCC 0.2V, f = 0
2.5V
2.5V
4
6
4
6
4
6
A
ISB4
Standby Current (One Ind.
Port CMOS Level) CE#L
or CE#R VIH, f =
fMAX[20]
2.5V
2.5V
21
30
21
30
18
25
mA
Document #: 001-08090 Rev. *E
Page 10 of 24
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Parameter
Electrical Characteristics for 3.0V Over the Operating Range
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16
–65
–65
–90
Description
P1 IO P2 IO
Voltage Voltage Min Typ
Max
Min
Typ
Max
Min
Typ
Unit
Max
VOH
Output HIGH Voltage (IOH = –2 mA)
3.0V (any port)
VOL
Output LOW Voltage (IOL = 2 mA
3.0V (any port)
0.4
0.4
0.4
V
VOL
ODR
ODR Output LOW Voltage (IOL = 8
mA
3.0V (any port)
0.2
0.2
0.2
V
VIH
Input HIGH Voltage
3.0V (any port)
2.0
VDDIO
+ 0.2
2.0
VDDIO
+ 0.2
V
2.1
2.1
2.1
V
VDDIO 2.0
+ 0.2
VIL
Input LOW Voltage
3.0V (any port)
–0.2
0.7
–0.2
0.7
–0.2
0.7
V
IOZ
Output Leakage Current
3.0V
3.0V
–1
1
–1
1
–1
1
A
ICEX
ODR
ODR Output Leakage Current.
VOUT = VCC
3.0V
3.0V
–1
1
–1
1
–1
1
A
–1
1
–1
1
–1
IIX
Input Leakage Current
3.0V
3.0V
1
A
ICC
Operating Current (VCC = Max., Ind.
IOUT = 0 mA) Outputs Disabled
3.0V
3.0V
49
70
49
70
42
60
mA
ISB1
Standby Current (Both Ports
TTL Level) CE#L and CE#R
VCC – 0.2, f=fMAX
Ind.
3.0V
3.0V
7
10
7
10
7
10
A
Ind.
3.0V
3.0V
28
40
28
40
25
35
mA
Standby Current (One Port TTL Ind.
Level) CE#L or CE#R VIH, f = Ind.
fMAX
3.0V
3.0V
6
8
6
8
6
8
A
3.0V
3.0V
28
40
28
40
25
35
mA
ISB2
ISB3
ISB4
Capacitance[22]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.0V
Max
Unit
9
pF
10
pF
Notes
21. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
standby ISB3.
22. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-08090 Rev. *E
Page 11 of 24
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Figure 2. AC Test Loads and Waveforms
3.0V/2.5V/1.8V
3.0V/2.5V/1.8V
R1
RTH = 6 k
OUTPUT
OUTPUT
R1
OUTPUT
C = 30 pF
C = 30 pF
R2
C = 5 pF
R2
VTH = 0.8V
(a) Normal Load
(c) Three-State Delay (Load 2)
(b) Thévenin Equivalent (Load 1)
(Used for tLZ, tHZ, tHZWE, and tLZWE
including scope and jig)
ALL INPUT PULSES
3.0V/2.5V
1.8V
R1
1022
13500
1.8V
R2
792
10800
GND
10%
90%
10%
90%
3 ns
3 ns
Switching Characteristics for VCC = 1.8V
Over the Operating Range [23]
Parameter
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16
–65
–65
–90
Description
Min
AD Mux Port Read Cycle
Max
Min
Max
Min
Unit
Max
[25]
tRC
Read Cycle Time
65
65
90
ns
tACC1
Random access ADV# Low to Data Valid
65
65
90
ns
tACC2
Random access Address to Data Valid
65
65
90
ns
tACC3
Random access CS# to Data Valid
65
65
90
ns
tAVDA
Random access ADV# High to Data Valid
35
35
50
ns
tAVD
ADV# Low Pulse
15
15
20
ns
tAVDS
Address Setup-up to ADV# rising edge
15
15
20
ns
tAVDH
Address Hold from ADV# rising edge
3
3
5
ns
tCSS
CS# Set-up to ADV# rising edge
7
7
10
ns
tOE
OE# Low to Data Valid
tLZOE[24]
OE# Low to IO Low-Z
tHZOE
OE# High to IO High-Z
15
15
25
tHZCS
CS# High to IO High-Z
15
15
25
tDBE
UB#/LB# Low to IO Valid
tLZBE
UB#/LB# Low to IO Low-Z
tHZBE
UB#/LB# High to IO High-Z
tAVOE
ADV# High to OE# Low
35
3
35
3
35
3
35
3
15
0
50
5
ns
50
5
15
0
ns
ns
25
0
ns
Notes
23. All timing parameters are measured with Load 2 specified in Figure 2.
24. This parameter is guaranteed by not tested.
Document #: 001-08090 Rev. *E
Page 12 of 24
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Switching Characteristics for VCC = 1.8V
Over the Operating Range [23] (continued)
Parameter
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16
–65
–65
–90
Description
Min
AD Mux Port Write Cycle
Max
Min
Max
Min
Unit
Max
[25]
tWC
Write Cycle Time
65
65
90
ns
tSCS
CS# Low to Write End
65
65
90
ns
tAVD
ADV# Low Pulse
15
15
20
ns
tAVDS
Address Set-up to ADV# rising edge
15
15
20
ns
tAVDH
Address Hold from ADV# rising edge
3
3
5
ns
tCSS
CS# Set-up to ADV# rising edge
7
7
10
ns
tWRL
WE# Pulse Width
28
28
45
ns
tBW
UB#/LB# Low to Write End
28
28
45
ns
tSD
Data Set-up to Write End
20
20
30
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE# High to IO Low-Z
0
0
0
ns
tAVWE
ADV# High to WE# Low
0
0
0
ns
40
60
60
Standard Port Read Cycle[26]
tRC
Read Cycle Time
tAA
Address to Data Valid
40
Output Hold From Address Change
tACS
CS# to Data Valid
40
60
60
OE# Low to Data Valid
25
35
35
tLZOE
[24]
OE# Low to Data Low-Z
5
60
tOHA
tDOE
5
60
5
5
5
10
5
tHZOE
OE# High to Data High-Z
tLZCS
CS# Low to Data Low-Z
tHZCS
CS# High to Data High-Z
tLZBE
UB#/LB# Low to Data Low-Z
tHZBE
UB#/LB# High to Data High-Z
10
30
30
tABE
UB#/LB# Access Time
40
60
60
5
30
5
10
5
30
5
30
5
30
5
Standard SRAM Port Write Cycle
tWC
Write Cycle Time
40
60
60
ns
tSCS
CS# Low to Write End
30
50
50
ns
tAW
Address Valid to Write End
30
50
50
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
Notes
25. AD Mux port timing applies to left AD Mux port and right port configured to AD Mux port.
26. Standard SRAM port timing applies to right port configured to standard SRAM port.
Document #: 001-08090 Rev. *E
Page 13 of 24
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Switching Characteristics for VCC = 1.8V
Over the Operating Range [23] (continued)
Parameter
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16
–65
–65
–90
Description
Min
Max
Min
Max
Min
Unit
Max
tWRL
Write Pulse Width
25
45
45
ns
tSD
Data Set-up to Write End
20
30
30
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE
WE# Low to Data High-Z
tLZWE
WE# High to Data Low-Z
15
0
25
0
25
0
ns
ns
Arbitration Timing
tBLA
BUSY# Low from Address Match
30
50
50
ns
tBHA
BUSY# High from Address Mismatch
30
50
50
ns
tBLC
BUSY# Low from CS# Low
30
50
50
ns
tBHC
BUSY# High from CS# High
30
50
50
ns
tPS[27]
Port Set-Up fro Priority
tBDD
BUSY# High to Data Valid
tWDD
Write Pulse to Data Delay
tDDD
Write Data Valid to Read Data Valid
5
5
30
5
50
50
55
85
85
45
70
70
Interrupt Timing
tINS
INT# Set Time
35
55
55
ns
tINR
INT# Reset Time
35
55
55
ns
Note
27. Add 2 ns to this parameter if VCC and VDDIOR are 2.5V at temperature
