CYIFS731
Low EMI Spread Spectrum Clock
Low EMI Spectrum Spread Clock
Functional Description
■
Reduces Systemic EMI.
■
Modulates external clocks including crystals, crystal oscillators
and ceramic resonators.
■
1X and 2X modulated frequency outputs.
■
Modulation programmable with simple external loop filter (LF).
■
4 to 68 MHz operating frequency range.
■
Digitally controlled modulation.
■
TTL/CMOS compatible outputs.
■
Center Spread Modulation.
■
Low short term jitter.
■
Bi-Directional buffers for reduced pin count.
■
3–5 Volt power supply.
■
Low Power Dissipation;
❐ 3.3 VDC = 30 mW - typical
❐ 5.0 VDC = 100 mW - typical
■
Available in 8 pin SOIC package.
The CYIFS731 is a Frequency Spreading EMI Attenuator
designed for the purpose of reducing Electro Magnetic
Interference (EMI) found in today’s high speed digital systems.
The CYIFS731 uses a proprietary technique to modulate the
output clock, Modout. By modulating the frequency of the digital
clock, measured EMI at the fundamental and harmonic
frequencies is greatly reduced. This reduction in radiated energy
can significantly reduce the cost of complying with regulatory
requirements without degrading digital waveforms.
The CYIFS731 is a very simple device to use and provides 1X
and 2X frequency modulated outputs of the input reference
frequency. By programming the two range select lines, RS0 and
RS1, the CYIFS731 can operate over a very wide range of input
frequencies. By utilizing Bi-Directional Buffer design, the pin
count of the CYIFS731 is kept to a minimum. Bi-Directional
Buffers is a method of providing an input control signal and an
output driver circuit on the same pin. Bi-Directional Buffers is
discussed further on page 6. The CYIFS731 has a simple
frequency selection table that allows it to operate from 4 MHz to
68 MHz in four separate ranges. The bandwidth of the frequency
spread at Modout is determined by the values of the loop filter
components. The modulation rate is determined by the input
frequency and the input frequency range selected. The
bandwidth of the CYIFS731 can be programmed from as little as
0.5% up to as much as 4.0% by selecting the proper loop filter.
It is for this reason that the CYIFS731 uses an external loop filter
(LF), in contrast to an internal loop filter type device which would
severely limit the use of a wide range of bandwidths.
For a complete list of related documentation, click here.
Cypress Semiconductor Corporation
Document Number: 001-73426 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 16, 2014
Not Recommended for New Designs
Features
CYIFS731
Block Diagram
LF
4
RS0
RS1
Phase
Detector
250k
Xin
Xout
VCO
Divide
1
by R
Bi-Directional
Buffer/Divider
2
Divide
Bi-Directional
by N
Buffer/Divider
7
6
Fout/RS0
FoutX2/RS1
Power On, Reset
Logic
Document Number: 001-73426 Rev. *D
8
5
VDD
VSS
3
Page 2 of 20
Not Recommended for New Designs
Modulation
Control Logic
CYIFS731
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 4
Frequency Range Selection Table .................................. 5
Functional Overview ........................................................ 6
Bi-directional Buffers ................................................... 6
Loop Filters .................................................................. 6
SSCG Modulation Profile ............................................ 9
Theory of Operation ....................................................... 10
EMI ............................................................................ 10
SSCG ........................................................................ 10
Modulation Rate ........................................................ 12
Application Notes and Schematics ............................... 13
Calculating dB Reduction .......................................... 13
Absolute Maximum Ratings .......................................... 14
Electrical Characteristics ............................................... 14
Document Number: 001-73426 Rev. *D
Timing Characteristics ................................................... 15
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagram ............................................................ 17
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC® Solutions ...................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Page 3 of 20
Not Recommended for New Designs
Contents
CYIFS731
Pin Configurations
Figure 1. CYIFS731, SOIC Package Pin Assignment
Pin Definitions
Pin No.
Pin Name
I/O
1, 2
XIN, XOUT
I/O
4
LF
O
Analog
Single ended tri-state output of the phase detector. A two pole passive loop
filter is connected to LF. See Table 1 on page 7 and Table 2 on page 8 for
proper values.
3, 5
VSS
–
Ground
Circuit Ground.
6
FoutX2/RS1
I/O
CMOS/TTL Bi-Directional pin used for range selection input and FoutX2 driver output.
During power up, RS1 serves as an input control line for selecting the proper
frequency operating range. After RS1 is latched into an internal register, this
pin becomes an output for the modulated FoutX2 driver. Refer to
Bi-directional Buffers on page 6 for more information. The center frequency
of FoutX2 is 2 times the reference frequency at XIN. FoutX2/RS1 has an
internal 250 k pull-up resistor to VDD.
7
Fout/RS0
I/O
CMOS/TTL Bi-Directional pin used for range selection input and Fout driver output.
During power up, RS0 serves as an input control line for selecting the proper
frequency operating range. After power has reached VDD/3, RS0 is latched
into a register and this pin becomes an output pin for the Fout driver. Fout
is a modulated output clock of the reference frequency, XIN, being the center
frequency and the modulation bandwidth and rate determined by the applied
loop filter. Refer to Table 1 on page 7 and Table 2 on page 8 respectively.
Fout/RS0 has internal 250k ohm pull-up resistor to VDD.
8
VDD
–
Document Number: 001-73426 Rev. *D
Type
Description
CMOS/TTL Pins form an on-chip reference oscillator when connected to terminals of an
external parallel resonant crystal. XIN may be connected to TTL/CMOS
external clock source. If XIN is connected to an external clock other than a
crystal, leave XOUT (pin 2) unconnected.
Power
Positive Circuit Power Supply.
Page 4 of 20
Not Recommended for New Designs
CYIFS731
CYIFS731
XIN Range
RS1
RS0
4–8 MHz
0
0
8–16 MHz
0
1
16–40 MHz
1
0
40–68 MHz
1
1
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields; however,
precautions should be taken to avoid application of any voltage
higher than the absolute maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to the
range, VSS < (VIN or VOUT) < VDD. All digital inputs are tied high
or low internally. Refers to electrical specifications for operating
supply range.
Not Recommended for New Designs
Frequency Range Selection Table
Figure 2. Frequency vs. Idd
Document Number: 001-73426 Rev. *D
Page 5 of 20
CYIFS731
Functional Overview
Figure 3. External Loop Filter
Two pins on the CYIFS731 are connected to bi-directional
buffers. Using bi-directional buffers is a method of sharing an
input circuit and an output circuit with the same pin on the IC
assembly, thereby reducing the pin count. Each bi-directional I/O
acts as an input during power up and as an output after power
has reached a certain voltage. For the CYIFS731, that voltage is
approximately VDD/3. At VDD/3, the CYIFS731 latches the logic
state of the respective line in an internal register for as long as
power is applied to the CYIFS731. After VDD/3 has been reached
and the power on reset has occurred, the respective pin is
switched from an input gate to an output driver. This pin remains
an output driver for as long as power is applied.
Loop Filters
The CYIFS731 requires an external loop filter to provide the
proper operation and bandwidth for a given input frequency.
Since the CYIFS731 operates over a wide range of frequencies,
the loop filter will change depending on the frequency of
operation. The following loop filter values are recommended for
best performance and modulation profile at 5.0 Volts and
3.3 Volts VDD, measured across pin 8 (VDD) and 5 (VSS).
Document Number: 001-73426 Rev. *D
The Table 1 on page 7 and Table 2 on page 8 contain the loop
filter values for the a power supply voltage of 5.0 and 3.3 VDC,
+/–10%. The values in both Table 1 on page 7 and Table 2 on
page 8 were bench tested for accuracy and optimal
performance. The loop filter values were determined by taking
4 MHz segments of the overall operating range and testing for
the optimal performance at the center frequency of each 4 MHz
band. This means that in the first band in the table below,
4–8 MHz, the loop filter values shown in the table produce the
most optimized performance for 6 MHz. It is possible to deviate
slightly from these values for optimal performance at some other
center frequency. Also note that the values listed in these tables
are all commonly manufactured components.
Page 6 of 20
Not Recommended for New Designs
Bi-directional Buffers
CYIFS731
Input
(MHz)
RS1
RS0
BW = 1%
(+/–0.5%)
BW = 2%
(+/–1%)
BW = 3%
(+/–1.5%)
BW = 4%
(+/–2%)
4–8
0
0
R1 = 2.2K
C1 = 270 pF
C2 = 22 pF
R1 = 2.2K
C1 = 120 pF
C2 = 22 pF
R1 = 2.2K
C1 = 82 pF
C2 = 22 pF
R1 = 2.2K
C1 = 56 pF
C2 = 22 pF
8–12
0
1
R1 = 2.2K
C1 = 470 pF
C2 = 22 pF
R1 = 2.2K
C1 = 220 pF
C2 = 22 pF
R1 = 2.2K
C1 = 150 pF
C2 = 22 pF
R1 = 2.2K
C1 = 100 pF
C2 = 22 pF
12–16
0
1
R1 = 2.2K
C1 = 180 pF
C2 = 22 pF
R1 = 2.2K
C1 = 82 pF
C2 = 22 pF
R1 = 2.2K
C1 = 56 pF
C2 = 22 pF
R1 = 2.2K
C1 = 33 pF
C2 = 22 pF
16–20
1
0
R1 = 2.2K
C1 = 680 pF
C2 = 22 pF
R1 = 2.2K
C1 = 330 pF
C2 = 22 pF
R1 = 2.2K
C1 = 220 pF
C2 = 22 pF
R1 = 2.2K
C1 = 150 pF
C2 = 22 pF
20–24
1
0
R1 = 2.2K
C1 = 470 pF
C2 = 22 pF
R1 = 2.2K
C1 = 220 pF
C2 = 22 pF
R1 = 2.2K
C1 = 150 pF
C2 = 22 pF
R1 = 2.2K
C1 = 100 pF
C2 = 22 pF
24–28
1
0
R1 = 2.2K
C1 = 220 pF
C2 = 22 pF
R1 = 2.2K
C1 = 100 pF
C2 = 22 pF
R1 = 2.2K
C1 = 82 pF
C2 = 22 pF
R1 = 2.2K
C1 = 56 pF
C2 = 22 pF
28–32
1
0
R1 = 4.7K
C1 = 220 pF
C2 = 0 pF
R1 = 4.7K
C1 = 100 pF
C2 = 0 pF
R1 = 4.7K
C1 = 68 pF
C2 = 0 pF
R1 = 4.7K
C1 = 47 pF
C2 = 0 pF
32–36
1
0
R1 = 4.7K
C1 = 120 pF
C2 = 0 pF
R1 = 4.7K
C1 = 68 pF
C2 = 0 pF
R1 = 4.7K
C1 = 47 pF
C2 = 7 pF
R1 = 4.7K
C1 = 27 pF
C2 = 15 pF
36–40
1
0
R1 = 4.7K
C1 = 100 pF
C2 = 0 pF
R1 = 4.7K
C1 = 33 pF
C2 = 0 pF
R1 = 4.7K
C1 = 27 pF
C2 = 0 pF
R1 = 4.7K
C1 = 18 pF
C2 = 0 pF
40–44
1
1
R1 = 2.2K
C1 = 470 pF
C2 = 0 pF
R1 = 2.2K
C1 = 180 pF
C2 = 22 pF
R1 = 2.2K
C1 = 120 pF
C2 = 22 pF
R1 = 2.2K
C1 = 82 pF
C2 = 22 pF
44–48
1
1
R1 = 2.2K
C1 = 330 pF
C2 = 0 pF
R1 = 2.2K
C1 = 150 pF
C2 = 22 pF
R1 = 2.2K
C1 = 120 pF
C2 = 16 pF
R1 = 2.2K
C1 = 82 pF
C2 = 10 pF
48–52
1
1
R1 = 2.2K
C1 = 270 pF
C2 = 0 pF
R1 = 2.2K
C1 = 120 pF
C2 = 0 pF
R1 = 2.2K
C1 = 100 pF
C2 = 0 pF
R1 = 2.2K
C1 = 68 pF
C2 = 0 pF
52–56
1
1
R1 = 2.2K
C1 = 220 pF
C2 = 0 pF
R1 = 2.2K
C1 = 100 pF
C2 = 0 pF
R1 = 2.2K
C1 = 82 pF
C2 = 0 pF
R1 = 2.2K
C1 = 56 pF
C2 = 0 pF
56–60
1
1
R1 = 2.2K
C1 = 220 pF
C2 = 0 pF
R1 = 2.2K
C1 = 100 pF
C2 = 0 pF
R1 = 2.2K
C1 = 68 pF
C2 = 0 pF
R1 = 2.2K
C1 = 39 pF
C2 = 0 pF
60–64
1
1
R1 = 7.5K
C1 = 120 pF
C2 = 33 pF
R1 = 7.5K
C1 = 68 pF
C2 = 0 pF
R1 = 7.5K
C1 = 47 pF
C2 = 0 pF
R1 = 7.5K
C1 = 33 pF
C2 = 0 pF
64–68
1
1
R1 = 7.5K
C1 = 120 pF
C2 = 33 pF
R1 = 7.5K
C1 = 68 pF
C1 = 0 pF
R1 = 7.5K
C1 = 47 pF
C2 = 0 pF
R1 = 7.5K
C1 = 27 pF
C2 = 0 pF
Notes
1. 0 pF means that the capacitor is removed.
2. When clock frequency is on boundary between two ranges, it is recommended that the higher range be used.
Document Number: 001-73426 Rev. *D
Page 7 of 20
Not Recommended for New Designs
Table 1. Recommended Loop Filter Values (VDD = 5.0 VDC, +/– 10%) [1, 2]
CYIFS731
Input
(MHz)
RS1
RS0
BW = 1%
(+/–0.5%)
BW = 2%
(+/–1%)
BW = 3%
(+/–1.5%)
BW = 4%
(+/–2%)
4–8
0
0
R1 = 2.2K
C1 = 220 pF
C2 = 22 pF
R1 = 2.2K
C1 = 100 pF
C2 = 22 pF
R1 = 2.2K
C1 = 68 pF
C2 = 22 pF
R1 = 2.2K
C1 = 39 pF
C2 = 22 pF
8–12
0
1
R1 = 2.2K
C1 = 470 pF
C2 = 22 pF
R1 = 2.2K
C1 = 220 pF
C2 = 22 pF
R1 = 2.2K
C1 = 150 pF
C2 = 22 pF
R1 = 2.2K
C1 = 100 pF
C2 = 22 pF
12–16
0
1
R1 = 2.2K
C1 = 120 pF
C2 = 22 pF
R1 = 2.2K
C1 = 56 pF
C2 = 22 pF
R1 = 2.2K
C1 = 39 pF
C2 = 22 pF
R1 = 2.2K
C1 = 27 pF
C2 = 8 pF
16–20
1
0
R1 = 2.2K
C1 = 680 pF
C2 = 22 pF
R1 = 2.2K
C1 = 390 pF
C2 = 22 pF
R1 = 2.2K
C1 = 270 pF
C2 = 22 pF
R1 = 2.2K
C1 = 180 pF
C2 = 22 pF
20–24
1
0
R1 = 2.2K
C1 = 560 pF
C2 = 22 pF
R1 = 2.2K
C1 = 220 pF
C2 = 22 pF
R1 = 2.2K
C1 = 120 pF
C2 = 22 pF
R1 = 2.2K
C1 = 82 pF
C2 = 22 pF
24–28
1
0
R1 = 2.2K
C1 = 220 pF
C2 = 22 pF
R1 = 2.2K
C1 = 82 pF
C2 = 22 pF
R1 = 2.2K
C1 = 56 pF
C2 = 22 pF
R1 = 2.2K
C1 = 39 pF
C2 = 10 pF
28–32
1
0
R1 = 4.7K
C1 = 180 pF
C2 = 0 pF
R1 = 4.7K
C1 = 68 pF
C2 = 0 pF
R1 = 4.7K
C1 = 39 pF
C2 = 0 pF
R1 = 4.7K
C1 = 27 pF
C2 = 0 pF
32–36
1
0
R1 = 4.7K
C1 = 82 pF
C2 = 0 pF
R1 = 4.7K
C1 = 33 pF
C2 = 0 pF
R1 = 4.7K
C1 = 22 pF
C2 = 0 pF
R1 = 4.7K
C1 = 12 pF
C2 = 0 pF
36–40
1
1
R1 = 47K
C1 = 1.0 µF
C2 = 390 pF
R1 = 47K
C1 = 1.0 µF
C2 = 220 pF
R1 = 47K
C1 = 1.0 µF
C2 = 150 pF
R1 = 47K
C1 = 1.0 µF
C2 = 100 pF
40–44
1
1
R1 = 2.2K
C1 = 680 pF
C2 = 0 pF
R1 = 2.2K
C1 = 270 pF
C2 = 0 pF
R1 = 2.2K
C1 = 180 pF
C2 = 10 pF
R1 = 2.2K
C1 = 120 pF
C2 = 10 pF
44–48
1
1
R1 = 2.2K
C1 = 330 pF
C2 = 0 pF
R1 = 2.2K
C1 = 180 pF
C2 = 0 pF
R1 = 2.2K
C1 = 120 pF
C2 = 0 pF
R1 = 2.2K
C1 = 82 pF
C2 = 0 pF
48–52
1
1
R1 = 2.2K
C1 = 270 pF
C2 = 0 pF
R1 = 2.2K
C1 = 120 pF
C2 = 0 pF
R1 = 2.2K
C1 = 82 pF
C2 = 0 pF
R1 = 2.2K
C1 = 56 pF
C2 = 0 pF
52–56
1
1
R1 = 2.2K
C1 = 220 pF
C2 = 0 pF
R1 = 2.2K
C1 = 100 pF
C2 = 0 pF
R1 = 2.2K
C1 = 68 pF
C2 = 0 pF
R1 = 2.2K
C1 = 33 pF
C2 = 0 pF
56–60
1
1
R1 = 2.2K
C1 = 150 pF
C2 = 0 pF
R1 = 2.2K
C1 = 68 pF
C2 = 5 pF
R1 = 3.3K
C1 = 47 pF
C2 = 12 pF
R1 = 4.7K
C1 = 33 pF
C2 = 22 pF
60–64
1
1
R1 = 4.7K
C1 = 100 pF
C2 = 0 pF
R1 = 4.7K
C1 = 47 pF
C2 = 0 pF
R1 = 4.7K
C1 = 27 pF
C2 = 0 pF
R1 = 4.7K
C1 = 18 pF
C2 = 0 pF
64–68
1
1
R1 = 7.5K
C1 = 68 pF
C2 = 0 pF
R1 = 7.5K
C1 = 33 pF
C1 = 0 pF
R1 = 7.5K
C1 = 22 pF
C2 = 0 pF
R1 = 7.5K
C1 = 15 pF
C2 = 0 pF
Notes
3. 0 pF means that the capacitor is removed.
4. When clock frequency is on boundary between two ranges, it is recommended that the higher range be used.
Document Number: 001-73426 Rev. *D
Page 8 of 20
Not Recommended for New Designs
Table 2. Recommended Loop Filter Values (VDD = 3.3 VDC, +/– 10%) [3, 4]
CYIFS731
SSCG Modulation Profile
Example: Freq. of XIN = 25 MHz
Operating Range = 16–40 MHz
Modrate = Fxin/240 = 104.166 kHz.
Table 3. Chart for determination of modulation rate of
CYIFS731
XIN Range
Mod. rate divider
4–8 MHz
60
8–16 MHz
120
16–40 MHz
240
40–68 MHz
480
Not Recommended for New Designs
The modulation rate of the CYIFS731 is determined by the input
frequency and the operating range. The input frequency is
divided by a fixed number, depending on the operating range that
is selected. The modulation rate of the CYIFS731 can be
determined from Table 3.
Figure 4. Frequency Profile in Time Domain
Document Number: 001-73426 Rev. *D
Page 9 of 20
CYIFS731
The CYIFS731 is a Phase Lock Loop (PLL) type clock generator
using Direct Digital Synthesis (DDS). By precisely controlling the
bandwidth of the output clock, the CYIFS731 becomes a Low
EMI clock generator. The theory and detailed operation of the
CYIFS731 will be discussed in the following sections.
EMI
All clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50%. Because of the 50/50 duty cycle, digital
clocks generate most of their harmonic energy in the odd
harmonics, i.e.; 3rd, 5th, 7th etc. It is possible to reduce the
amount of energy contained in the fundamental and harmonics
by increasing the bandwidth of the fundamental clock frequency.
Conventional digital clocks have a very high Q factor, which
means that all of the energy at that frequency is concentrated in
a very narrow bandwidth, consequently, higher energy peaks.
Regulatory agencies test electronic equipment by the amount of
peak energy radiated from the equipment. By reducing the peak
energy at the fundamental and harmonics, the equipment under
test is able to satisfy agency requirements for Electro-Magnetic
Interference (EMI). Conventional methods of reducing EMI have
been to use shielding, filtering, multi-layer PCB’s etc. The
CYIFS731 uses the approach of reducing the peak energy in the
clock by increasing the clock bandwidth, and lowering the Q.
SSCG
The CYIFS731 uses a proprietary technique to modulate the
clock over a very narrow bandwidth and controlled rate of
change, both peak and cycle to cycle. The CYIFS731 takes a
narrow band digital reference clock in the range 4–68 MHz and
produces a clock that sweeps between a controlled start and
stop frequency and precise rate of change. To understand what
happens to an SSCG clock, consider that we have a 20 MHz
clock with a 50% duty cycle. From a 20 MHz clock we know the
following.
Figure 5. SSCG clock
Consider that this 20 MHz clock is applied to the Xin input of the
CYIFS731, either as an externally driven clock or as the result of
a parallel resonant crystal connected to pins 1 and 2 of the
CYIFS731. Also consider that the CYIFS731 is operating from a
5 Volt DC power supply and the loop filter is set for a total
bandwidth spread of 2%. Refer to Table 1 on page 7.
Figure 6. Perfect clock with no noise
From the above parameters, the output clock at Modout will be
sweeping symmetrically around a center frequency of 20 MHz.
The minimum and maximum extremes of this clock will be
+200 kHz and –200 kHz. So, we have a clock that is sweeping
from 19.8 MHz to 20.2 MHz and back again. If we were to look
at this clock on a spectrum analyzer we would see the picture in
Figure 6. Keep in mind that this is a drawing of a perfect clock
with no noise.
We see that the original 20 MHz reference clock is at the center
Frequency, FC, and the minimum and maximum extremes are
positioned symmetrically about the center frequency. This type
of modulation is called Center-Spread. Figure 6 illustrates this as
it is seen on a spectrum analyzer.
Document Number: 001-73426 Rev. *D
Page 10 of 20
Not Recommended for New Designs
Theory of Operation
CYIFS731
Figure 7. Period Comparison Chart
The difference in the peak energy of the modulated clock and the
non-modulated clock in typical applications will see a 2–3 dB
reduction at the fundamental and as much as 8–10 dB reduction
at the intermediate harmonics, 3rd, 5th, 7th etc. At the higher
harmonics, it is quite possible to reduce the peak harmonic
energy, compared to the unmodulated clock, by as much as 12
to 18 dB.
The following images are actual scans of the CYIFS741. The
CYIFS741 is the same part as the CYIFS731 but has a times 2
output instead of the Refout.These scans are from a spectrum
analyzer and time domain analyzer of the CYIFS741 at various
frequencies running at 3.3 Volts DC.
Figure 8 at the right shows a modulated 10 MHz clock at Modout
of the CYIFS741. The following parameters apply to this scan;
Fin = 10 MHz.
BW = 2% (total)
Vertical scale = 6 dB/div.
From this scan it can be seen the bandwidth of the clock is wider
than a conventional clock. Notice the EMI filters displayed at the
bottom of the image. This is the same filter settings that are used
by regulatory agencies.
Figure 8. Modulated 10 MHz clock at Modout of CYIFS741
The CYIFS731 is a center spread clock, meaning that it
symmetrically spreads above and below the reference
frequency.
Looking at Figure 6 on page 10, you will note that the peak
amplitude of the 20 MHz non-modulated clock is higher than the
wideband modulated clock. This difference in peak amplitudes
between modulated and unmodulated clocks is the reason why
SSCG clocks are so effective in digital systems. The Figure 6 on
page 10 refers to the fundamental frequency of a clock. A very
important characteristic of the SSCG clock is that the bandwidth
of the harmonics is multiplied by the harmonic number. In other
words, if the bandwidth of a 20 MHz clock is 200 kHz, the
bandwidth of the 3rd harmonic will be 3 times 200 kHz, or 600
kHz. The amount of bandwidth is relative to the amount of energy
in the clock. Consequently, the wider the bandwidth, the greater
the energy reduction of the clock.
Most applications will not have a problem meeting agency
specifications at the fundamental frequency. It is the higher
harmonics that usually cause the most problems. With an SSCG
clock, the bandwidth and peak energy reduction increases with
the harmonic number. Consider that the 11th harmonic of a 20
MHz clock is 220 MHz. With a total spread of 200 kHz at 20 MHz,
the spread at the 11th harmonic would be 2.20 MHz which greatly
reduces the peak energy content.
Document Number: 001-73426 Rev. *D
It is clear from Figure 8, that the peak amplitude of the modulated
clock is lower in amplitude than the non-modulated clock. In fact,
this image indicates that the difference between the two peaks
is approximately 2 dB.
Page 11 of 20
Not Recommended for New Designs
Figure 7 on page 11 shows a 20 MHz clock as it would be seen
on an oscilloscope. The top trace is the non-modulated reference
clock, or the Refout clock at pin 7. The bottom trace is the
modulated clock at pin 6. From this comparison chart you can
see that the frequency is decreasing and the period of each
successive clock increasing. The TC measurements on the left
and right of the bottom trace indicate the max. and min. extremes
of the clock. Intermediate clock changes are small and
accumulate to achieve the total period deviation. The reverse of
this Figure would show the clock going from min. extreme back
to the high extreme.
CYIFS731
results in 1/60, 1/120, 1/240 and 1/480 of the input frequency in
each range, respectively. Refer to the Table 3 on page 9.
Figure 10. Frequency Modulation Profile
Figure 9. 3rd Harmonic of the 10 MHz clock
The XIN reference clock determines the modulation frequency
but the internal SSCG control logic determines the actual
modulation profile. It is very important to note that the Bandwidth
of the clock modulation is determined by the values of the loop
filter applied to pin 4.
Modulation Rate
The CYIFS731 moves from max to min frequencies of its
bandwidth at a pre-determined rate and profile. The modulation
frequency is determined by the input frequency and the range
that is selected. The CYIFS731 has four input frequency
operating ranges, 4–8 MHz, 8–16 MHz, 16–40 MHz and
40–68 MHz. The modulation rate is determined by a divider that
Document Number: 001-73426 Rev. *D
Figure 10 shows the modulation profile of the CYIFS731. This
type of test is done with a time domain analyzer. What this shows
is the amount of time that the clock spends at any one frequency
within its modulation envelope. From this type of picture, the
amount of modulation percentage and modulation rate can be
determined. This picture shows that the CYIFS731 is modulating
2% around the 10 MHz input and the modulation rate is
83.06 kHz.
Page 12 of 20
Not Recommended for New Designs
Figure 9 on page 12, shows the 3rd Harmonic of the 10 MHz clock
in Figure 8. The big difference here is that the bandwidth of the
3rd. harmonic is 3 times greater than the bandwidth at the
fundamental frequency. Since the energy is spread over a much
wider bandwidth, the peak energy reduction will be greater. As
can be seen in this picture, the difference between the modulated
and un-modulated peaks is approximately 8 dB. With the
bandwidth of the fundamental at 2% or 200 kHz, the bandwidth
at the 3rd. harmonic will be 600 kHz.
CYIFS731
Application Notes and Schematics
The schematic diagram shown below is a simple minimum component application example of an CYIFS731 design. In the case shown
below, the control lines are configured for the following parameters.
CYIFS731
Calculating dB Reduction
The circuit shown in Figure 12 is the equivalent oscillator circuit
used in the CYIFS731.
Figure 12. Equivalent oscillator circuit used in the CYIFS731
The dB reduction for a give frequency and spread can be
calculated using a simple formula. This formula is only helpful in
determining a relative dB reduction for a given application. This
formula assumes an ideal clock with 50% duty cycle and
therefore only predicts the EMI reduction of odd harmonics.
Other circumstances such as non-ideal clock and noise will affect
the actual dB reduction. The formula is as follows;
dB = 6.5 + 9(Log10(F)) + 9(Log10(P))
Where; F = Frequency in MHz, P = total % spread (2.5% = 0.025)
Using a 50 MHz clock with a 2.5% spread, the theoretical dB
reduction would be;
dB @ 50 MHz (Fund) = 6.5 + 15.29 – 14.42 = 7.37
dB @ 150 MHz (3rd) = 6.5 + 19.58 – 14.42 = 11.66
dB @ 550 MHz (11th) = 6.5 + 24.66 – 14.42 = 16.74
Note
5. C3 and C4 values assume a first order crystal with CL = 18 pF.
Document Number: 001-73426 Rev. *D
Page 13 of 20
Not Recommended for New Designs
Figure 11. Simple minimum component application example of an CYIFS731 design [5]
CYIFS731
Item
Symbol
Min
Max
Units
VDD
3.0
6.0
VDC
Input, relative to VSS
VIRVSS
–0.3
VDD + 0.3
VDC
Output, relative to VSS
VORVSS
–0.3
VDD + 0.3
VDC
Temperature, Operating
TOP
0
+70
°C
Temperature, Storage
TST
–65
+150
°C
ESDHBM
1300
–
V
Min
Typ
Max
Units
Operating Voltage
ESD protection, JEDEC Standard JS-001-2012
Electrical Characteristics
Characteristic
Symbol
Input Low Voltage
VIL
–
–
0.8
VDC
Input High Voltage
VIH
2.0
–
–
VDC
Input Low Current
IIL
–
–
100
µA
Input High Current
IIH
–
–
100
µA
Output Low Voltage IOL = 8 mA, VDD = 5 V
VOL
–
–
0.4
VDC
Output High Voltage IOH = 8 mA, VDD = 5 V
VOH
VDD – 1.0
–
–
VDC
Output Low Voltage IOL = 5 mA, VDD = 3.3 V
VOL
–
–
0.4
VDC
Output High Voltage IOH = 3 mA, VDD = 3.3 V
VOH
2.4
–
–
VDC
Input Capacitance (Pin 1)
CIN1
–
3
4
pF
Output Capacitance (Pin 2)
CIN2
–
5
6
pF
Tri-State Leakage Current (Pin 7)
IOZ
–
–
5.0
µA
5 Volt Supply Current @30 MHz, No Load.
IDD
–
20
25
mA
3.3 Volt Supply Current @ 30 MHz, No Load.
IDD
–
9
12
mA
Short Circuit Current (Refout or Modout)
ISC
–
–
25
mA
Test measurements performed at VDD = 3.3 V and 5.0 V ± 10%, XIN = 30 MHz, TA = 0 °C to 70 °C
Document Number: 001-73426 Rev. *D
Page 14 of 20
Not Recommended for New Designs
Absolute Maximum Ratings
CYIFS731
Symbol
Min
Typ
Max
Units
Output Rise Time Measured at 10%–90% @ 5 VDC
Characteristic
tTLH
4.5
5.1
5.7
ns
Output Fall Time Measured at 10%–90% @ 5 VDC
tTHL
4.0
4.3
4.7
ns
Output Rise Time Measured at 0.8 V–2.0 V @ 5 VDC
tTLH
850
900
975
ps
Output Fall Time Measured at 0.8 V–2.0 V @ 5 VDC
tTHL
1.3
1.4
1.5
ns
Output Rise Time Measured at 10%–90% @ 3.3 VDC
tTLH
5.0
5.3
5.9
ns
Output Fall Time Measured at 10%–90% @ 3.3 VDC
tTHL
4.8
5.1
5.4
ns
Output Rise Time Measured at 0.8 V–2.0 V @ 3.3 VDC
tTLH
1.8
1.9
2.0
ns
Output Fall Time Measured at 0.8 V–2.0 V @ 3.3 VDC
tTHL
2.0
2.2
2.4
ns
TsymF1
45
50
55
%
ccj, Jitter @ 5.0 VDC, 50 MHz
ccj
–
300
350
ps
ccj, Jitter @ 3.3 VDC, 50 MHz
ccj
–
200
250
ps
Output Duty Cycle
Measurements performed at VDD = 3.3 V and 5.0 V ± 10%, TA = 0 °C to 70 °C, CL = 15 pF, XIN = 30 MHz.
Document Number: 001-73426 Rev. *D
Page 15 of 20
Not Recommended for New Designs
Timing Characteristics
CYIFS731
Ordering Information
Part and Package Type
Operating Range
8-pin SOIC
Commercial, 0 °C to 70 °C
CYIFS731SXCT
8-pin SOIC, Tape and Reel
Commercial, 0 °C to 70 °C
Not Recommended for New Designs
Ordering Code
CYIFS731SXC
Ordering Code Definitions
CY
IFS731
S
X
C
T
T = Tape and Reel; blank = Tube
Temperature range:
C = Commercial, 0 °C to 70 °C
Pb-free
Package Type:
S = 8-pin SOIC (150 Mil)
Part Identifier
Company ID: CY = Cypress
Document Number: 001-73426 Rev. *D
Page 16 of 20
CYIFS731
Package Diagram
Not Recommended for New Designs
Figure 13. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066
51-85066 *F
Document Number: 001-73426 Rev. *D
Page 17 of 20
CYIFS731
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
DDS
Direct Digital Synthesis
°C
degree Celsius
EMI
Electromagnetic Interference
dB
decibel
IC
Integrated Circuit
kHz
kilohertz
I/O
Input/Output
k
kilohm
LAN
Local Area Network
MHz
megahertz
LCD
Liquid Crystal Display
µA
microampere
LF
Loop Filter
mA
milliampere
PCB
Printed Circuit Board
mW
milliwatt
PLL
Phase Locked Loop
SOIC
Small-Outline Integrated Circuit
TTL
Transistor-Transistor Logic
WAN
Wide Area Network
Document Number: 001-73426 Rev. *D
Symbol
Unit of Measure
ns
nanosecond
%
percent
pF
picofarad
V
volt
Not Recommended for New Designs
Acronyms
Page 18 of 20
CYIFS731
Document History Page
Document Title: CYIFS731, Low EMI Spread Spectrum Clock
Document Number: 001-73426
ECN No.
Issue Date
Orig. of
Change
**
3403637
10/12/2011
PURU
*A
4457908
07/26/2014
XHT
Description of Change
New data sheet.
Updated Block Diagram.
Updated Package Diagram:
spec 51-85066 – Changed revision from *E to *F.
Updated to new template.
*B
4526925
10/07/2014
XHT
Post to external web.
*C
4565316
11/09/2014
XHT
Updated Absolute Maximum Ratings:
Added ESDHBM parameter and its details.
Added watermark “Not Recommended for New Designs”.
Completing Sunset Review.
*D
4598681
12/16/2014
XHT
Added related documentation hyperlink in page 1.
Document Number: 001-73426 Rev. *D
Not Recommended for New Designs
Rev.
Page 19 of 20
CYIFS731
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
cypress.com/go/psoc
cypress.com/go/touch
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2011-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-73426 Rev. *D
Revised December 16, 2014
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 20 of 20
Not Recommended for New Designs
Products
