Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CCG1 Datasheet
USB Type-C Port Controller
with Power Delivery
THIS PRODUCT IS NOT RECOMMENDED FOR NEW DESIGNS
General Description
CCG1 provides a complete USB Type-C and USB Power Delivery port control solution. The core architecture of CCG1 enables a
base Type-C solution that can scale to a complete 100-W USB Power Delivery with Alternate Mode multiplex support. CCG1 is also
a Type-C cable ID IC for active and passive cables. The CCG1 controller detects connector insert, plug orientation and VCONN
switching signals. CCG1 makes it easier to add USB Power Delivery to any architecture because it provides control signals to manage
external VBUS and VCONN power management solutions and external mux controls for most single cable-docking solutions.
The CCG1 family of devices are fixed-function parts that use a configuration table to control their operation in different applications.
The functionality is implemented in firmware and will be certified against USB Implementers Forum (USB-IF) compliance tests when
available. The programmability allows CCG1 devices to track any USB Specification changes. For information on accessing the source
code, contact Cypress support. CCG1 devices are not recommended for new designs. However, customers may continue to purchase
these CCG1 devices for their existing designs already in production.
Applications
Type-C Support
■
Notebooks, tablets, monitors, docking stations
■
■
Power adapters, USB Type-C cables
■
■
Features
PD Support
■
32-bit MCU Subsystem
■
48-MHz ARM Cortex-M0 CPU with 32-KB flash and 4-KB
SRAM
■
■
12-bit, 1-Msps ADC for VBUS voltage and current monitoring
■ Dynamic overcurrent and overvoltage protection
■
Integrated digital blocks
■
Two configurable 16-bit TCPWM blocks
2
■ One I C master or slave
■
■
■
3.2 V to 5.5 V operation
Sleep 1.3 mA, Deep Sleep 1.3 A[1]
Packages
■
•
Supports Provider and Consumer roles
Supports all power profiles
Low-Power Operation
Integrated analog blocks
Cypress Semiconductor Corporation
Document Number: 001-93639 Rev. *L
Integrated transceiver (BB PHY)
Supports up to two USB ports with PD
Supports routing of all protocols through an external mux
198 Champion Court
40-pin QFN
16-pin SOIC
35-ball wafer-level CSP (WLCSP)
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 3, 2020
CCG1 Datasheet
Figure 1. CCG1 Block Diagram[2, 3, 4, 5, 6, 7]
Notes
1. Values measured for CCG1 silicon only. Application specific power numbers may be higher.
2. Timer, counter, pulse-width modulation block.
3. Serial communication block configurable as I2C.
4. Base band.
5. Termination resistor denoting a Downstream Facing Port (DFP).
6. Termination resistor denoting a Upstream Facing Port (UFP).
7. Termination resistor denoting an Electronically Marked Cable Assembly (EMCA).
Document Number: 001-93639 Rev. *L
Page 2 of 31
CCG1 Datasheet
Contents
Functional Definition ........................................................ 4
CPU and Memory Subsystem ..................................... 4
System Resources ...................................................... 4
GPIO ........................................................................... 4
Pin Definitions .................................................................. 5
Pinouts ............................................................................ 11
Power ............................................................................... 12
Electrical Specifications ................................................ 13
Absolute Maximum Ratings ...................................... 13
Device-Level Specifications ...................................... 13
Digital Peripherals ..................................................... 15
Memory ..................................................................... 16
System Resources .................................................... 16
Document Number: 001-93639 Rev. *L
Applications in Detail ..................................................... 18
Ordering Information ...................................................... 23
Ordering Code Definitions ......................................... 23
Packaging ........................................................................ 24
Acronyms ........................................................................ 27
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Revision History ............................................................. 29
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support ....................... 31
Products .................................................................... 31
PSoC® Solutions ...................................................... 31
Cypress Developer Community ................................. 31
Technical Support ..................................................... 31
Page 3 of 31
CCG1 Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in the CCG1 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and a Wakeup Interrupt Controller
(WIC). The WIC can wake the processor up from the Deep Sleep
mode, allowing power to be switched off to the main processor
when the chip is in the Deep Sleep mode. The Cortex-M0 CPU
provides a Non-Maskable Interrupt (NMI) input, which is made
available to the user when it is not in use for system functions
requested by the user.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a 2-wire form of JTAG; the debug
configuration used for CCG1 has four break-point (address)
comparators and two watchpoint (data) comparators.
Flash
The CCG1 device has a flash module with a flash accelerator,
tightly coupled to the CPU to improve average access times from
the flash block. The flash block is designed to deliver 1 wait-state
(WS) access time at 48 MHz and 0-WS access time at 24 MHz.
The flash accelerator delivers 85% of single-cycle SRAM access
performance on average. Part of the flash module can be used
to emulate EEPROM operation if required.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
FIFO for receive and transmit which, by increasing the time given
for the CPU to read data, greatly reduces the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices, as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/O is implemented with GPIO in open-drain modes.
The CCG1 is not completely compliant with the I2C spec in the
following respects:
■
GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
■
Fast-mode Plus has an IOL specification of 20 mA at a VOL of
0.4 V. The GPIO cells can sink a maximum of 8 mA IOL with a
VOL maximum of 0.6 V.
■
Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the Bus Load.
■
■
The CCG1 has up to 30 GPIOs, which are configured for various
functions. Refer to the pinout tables for the definitions. The GPIO
block implements the following:
■
Eight drive strength modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
■
Input threshold select (CMOS or LVTTL).
■
Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes.
■
Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode).
■
Selectable slew rates for dV/dt related noise control to improve
EMI.
Power System
Serial Communication Blocks (SCB)
The CCG1 has one SCB, which can implement an I2C interface.
The hardware I2C block implements a full multi-master and slave
interface (it is capable of multimaster arbitration). This block is
capable of operating at speeds of up to 1 Mbps (Fast Mode Plus)
and has flexible buffering options to reduce interrupt overhead
and latency for the CPU. It also supports EZ-I2C that creates a
mailbox address range in the memory of the CCG1 and effectively reduces I2C communication to reading from and writing to
an array in memory. In addition, the block supports an 8-deep
Document Number: 001-93639 Rev. *L
When the SCB is in the I2C Slave mode, and Address Match
on External Clock is enabled (EC_AM = 1) along with operation
in the internally clocked mode (EC_OP = 0), then its I2C
address must be even.
GPIO
System Resources
The power system is described in detail in the section Power on
page 12. It provides assurance that voltage levels are as
required for each respective mode and either delay mode entry
(on power-on reset (POR), for example) until voltage levels are
as required for proper function or generate resets (Brown-Out
Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). The
CCG1 operates with a single external supply over the range of
3.2 V to 5.5 V operation and has three different power modes:
Active, Sleep, and Deep Sleep; transitions between modes are
managed by the power system.
When the SCB is an I2C Master, it interposes an IDLE state
between NACK and Repeated Start; the I2C spec defines Bus
free as following a Stop condition so other Active Masters do
not intervene but a Master that has just become activated may
start an Arbitration cycle.
During power-on and reset, the I/O pins are forced to the disable
state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network, known as a high-speed
I/O matrix, is used to multiplex between various signals that may
connect to an I/O pin.
Page 4 of 31
CCG1 Datasheet
Pin Definitions
Table 1 provides the pin definition for 35-Ball WLCSP for the Cable/EMCA application. Refer to Table 23 for part numbers to package
mapping.
Table 1. Pin Definitions for 35-ball WLCSP for EMCA Cable Application
CYPD110335FNXIT
Balls
Type
CC1_RX
C4
I
CC1 control
0: TX enabled
z: RX sense
CC1_TX
D7
O
Configuration Channel 1
SWD_IO
D1
I/O
SWD I/O
SWD_CLK
C1
I
I2C_SCL
B1
I/O
I2C clock signal
I2C_SDA
B2
I/O
I2C data signal
XRES
B6
I
VCCD
A7
POWER
Regulated digital supply output. Connect a 1 to 1.6-µF capacitor.
No external source should be connected
VDDD
C7
POWER
Power supply for both analog and digital sections
VSSA
B7
GND
CC_VREF
C5
I
Data reference signal for CC lines
Signals for internal use only. The TX_U output signal should be
connected to the TX_M signal
Functional Pin Name
Description
SWD clock
Reset
Analog ground
TX_U
B3
O
TX_M
B5
I
TX_REF_IN
D3
I
TX_GND
A3
I
Connect to GND via 2K 1% resistor
TX_REF_OUT
D4
O
Reference signal generated by connecting internal current source to
two 1K external resistors
RA_DISCONNECT
E4
O
Optional control signal to remove RA after assertion of VCONN
0: RA disconnected
1: RA connected
VCONN_DET
C6
I
Local VCONN detection signal
0: VCONN is not locally applied
1: VCONN is locally applied
CC1_LPREF
A5
I
Reference signal for internal use. Connect to the output of resistor
divider from VDDD.
–
Reference signal for internal use.
Connect to TX_REF output via a 2.4K 1% resistor
RA_FAR_DISCONNECT
E5
O
Optional control signal to remove RA after assertion of VCONN (NC
for 2 chip/cable)
0: RA disconnected
1: RA connected
BYPASS
D5
I
Bypass capacitor for internal analog circuits
C3
I
Configuration channel 1 RX signal for Low Power States
A1, A2, A4, A6,
B4, C2, D2, D6,
E1, E2, E3, E6,
E7
–
General-purpose I/Os
CC1_LPRX
GPIO
Document Number: 001-93639 Rev. *L
Page 5 of 31
CCG1 Datasheet
Table 2 provides the pin definitions for 40-pin QFN and 35-ball WLCSP for the notebook, tablet, smartphone, and monitor
applications. Refer to Table 23 on page 23 for part numbers to package mapping.
Table 2. Pin Definitions for 40-QFN and 35-ball WLCSP for Notebook, Tablet, SmartPhone and Monitor Applications
Functional Pins
CYPD
CYPD
CYPD
1122-40LQXI 1121-40LQXI 1131-35FNXIT
Pins[8]
Pins[9]
Balls[10]
Type
Description
MUXSEL_1
1
1
D5
O
External Data Mux Select signal 1
MUXSEL_2
2
2
D6
O
External Data Mux Select signal 2
CC1_CTRL
3
3
D3
I/O
CC2_CTRL
4
4
E4
I/O
MUXSEL_3
5
5
E5
O
External Data Mux Select signal 3
MUXSEL_4
6
6
E6
O
External Data Mux Select signal 4
CS_P
7
7
E3
I
Current Sensing Plus input
CS_M
8
8
E2
I
Current Sensing Minus input I
VSS
9
9
–
GND
CC1
10
10
-
I/O
Configuration Channel 1
CC_SEL_REF_1
11
11
E1
O
CC Reference Select signal
SWD_IO
12
12
D1
I/O
SWD IO
SWD_CLK
13
13
C1
I
HOTPLUG_DET
14
14
C2
I/O
HotPlug Detection for Display Port Alternate Mode
GPIO1
15
–
–
I/O
General-purpose I/O
VSEL2
–
15
–
O
Voltage Select signal 2 for selecting output voltage
GPIO2
16
–
–
I/O
General-purpose I/O
GPIO3
17
–
–
I/O
General-purpose I/O
IFAULT
–
17
–
I
I2C_SCL
18
18
B1
I/O
I2C Clock signal
I2C_SDA
19
19
B2
I/O
I2C Data signal
I2C_INT
20
20
A2
O
I2C Interrupt
CC_SEL_REF_2
21
21
A1
O
CC Reference Select signal
CC1 control
0: TX enabled
z: RX sense
CC2 control
0: TX enabled
z: RX sense
Ground
SWD Clock
Current Fault Indication
0: No fault
1: Current fault
CC1_RD
22
22
C3
O
Open Drain signal to connect RD to CC 1 line
z: RD not connected
0: RD connected for Monitor application
1: RD connected for Notebook application
CC1_RP
23
23
A5
O
Open Source signal to connect RP to CC 1 line
z: RP not connected
1: RP connected
Notes
8. Pinout for Notebook DRP application for 40-QFN.
9. Pinout for Monitor DRP application for 40-QFN.
10. Pinout for Notebook DRP application for 35-CSP.
Document Number: 001-93639 Rev. *L
Page 6 of 31
CCG1 Datasheet
Table 2. Pin Definitions for 40-QFN and 35-ball WLCSP for Notebook, Tablet, SmartPhone and Monitor Applications (continued)
Functional Pins
CYPD
CYPD
CYPD
1122-40LQXI 1121-40LQXI 1131-35FNXIT
[8]
[9]
Pins
Pins
Balls[10]
Type
Description
CC1_VCONN_CTRL
24
24
A4
O
Open Drain signal to control a PFET power switch
for VCONN on CC 1 line
0: VCONN switch closed
z: VCONN switch open
VBUS_DISCHARGE
25
25
A3
O
Signal used for discharging VBUS line during
voltage change
CC2
26
26
B3
O
Configuration Channel 2
CC2_RD
27
27
A6
O
Open Drain signal to connect RD to CC 2 line
z: RD not connected
0: RD connected for Monitor application
1: RD connected for Notebook application
CC2_RP
28
28
B4
O
Open Source signal to connect RP to CC 2 line
z: RP not connected
1: RP connected
CC2_VCONN_CTRL
29
29
B5
O
Open Drain signal to control a PFET power switch
for VCONN on CC 2 line
0: VCONN switch closed
z: VCONN switch open
XRES
30
30
B6
I
Reset
VCCD
31
31
A7
Regulated digital supply output. Connect a 1 to
POWER 1.6-μF capacitor. No external source should be
connected
VDDD
32
32
C7
POWER Power supply for digital sections
VDDA
33
33
C7
POWER Power Supply for analog sections
VSSA
34
34
B7
GND
VBUS_VMON
35
35
C4
I
VBUS Overvoltage Protection monitoring signal
VBUS_VREF
36
36
C5
I
VBUS reference signal for Overvoltage Protection
detection
–
O
Voltage Select signal 1 for selecting the output
voltage
C6
O
CC Reference Select signal
VSEL1
–
CC_SEL_REF_3
37
37
16
Analog ground pin
Full rail control signal for enabling/disabling
Consumer load FET
VBUS_C_CTRL
38
–
D7
VBUS_OK
–
38
–
CC_VREF
39
39
D4
I
Data reference signal for CC lines
VBUS_P_CTRL
40
40
E7
O
Full rail control signal for enabling/disabling Provider
load FET
O
VBUS_OK=1 - VBUS Voltage ok
VBUS_OK=0 - VBUS Overvoltage detected
Notes
8. Pinout for Notebook DRP application for 40-QFN.
9. Pinout for Monitor DRP application for 40-QFN.
10. Pinout for Notebook DRP application for 35-CSP.
Document Number: 001-93639 Rev. *L
Page 7 of 31
CCG1 Datasheet
Table 3 provides the pin definition for 40-pin QFN for Notebook (DFP) application. Refer to Table 23 for part numbers to package
mapping.
Table 3. Pin Definitions for 40-Pin QFN for Notebook (DFP)
HIGH/
Functional Pin Name Active
LOW
Drive Mode
CYPD
1134-40LQXI
Pins
Type
Description
MUXSEL_1
–
Open drain, drives low
1
O
External Data Mux Select signal 1
MUXSEL_2
–
Open drain, drives low
2
O
External Data Mux Select signal 2
CC1_CTRL
–
Analog input/Strong
drive (push pull)
3
IO
CC1 control
0:Tx enabled
z: RX sense
CC2_CTRL
–
Analog input/Strong
drive (push pull)
4
IO
CC2 control
0: TX enabled
z: RX sense
MUXSEL_3
–
Open drain, drives low
5
O
External Data Mux Select signal 3
MUXSEL_4
–
Open drain, drives low
6
O
External Data Mux Select signal 4
CS_P
–
Analog input
7
I
Current Sensing Plus input
CS_M
–
Analog input
8
I
Current Sensing Minus input
VSS
–
CC1
–
CC1_RP_1.5
9
GND
Strong drive (push pull)
10
O
Configuration Channel 1
Active HIGH Open drain, drives high
11
O
Open Drain signal to connect RP to CC1
line (1.5A current)
z: RP not connected
1: RP connected
SWD IO
–
Ground
SWD_IO
–
–
12
IO
SWD_CLK
–
–
13
I
SWD Clock
O
Open Source signal to connect RP to
CC1 line (3A current)
z: RP not connected
1: RP connected
O
Open Drain signal to connect RP to CC1
line (Default current)
z: RP not connected
1: RP connected
CC1_RP_3.0
CC1_RP_DEF
Active HIGH Open drain, drives high
Active HIGH Open drain, drives high
14
15
CC2_RP_DEF
Active HIGH Open drain, drives high
16
O
Open Drain signal to connect RP to CC2
line (Default current)
z: RP not connected
1: RP connected
CC2_RP_1.5
Active HIGH Open drain, drives high
17
O
Open Drain signal to connect RP to CC2
line (1.5A current)
z: RP not connected
1: RP connected
I2C_SCL
Active LOW Open drain, drives low
18
IO
I2C Clock signal
I2C_SDA
Active LOW Open drain, drives low
19
IO
I2C Data signal
I2C_INT
Active LOW Open drain, drives low
20
O
I2C Interrupt
Document Number: 001-93639 Rev. *L
Page 8 of 31
CCG1 Datasheet
Table 3. Pin Definitions for 40-Pin QFN for Notebook (DFP) (continued)
HIGH/
Functional Pin Name Active
LOW
CC2_RP_3.0
Drive Mode
Active HIGH Open drain, drives high
CYPD
1134-40LQXI
Pins
Type
Description
21
O
Open Source signal to connect RP to
CC2 line (3A current)
z: RP not connected
1: RP connected
Configuration channel 1 RX signal for
Low Power states
CC1_LPRX
–
Analog input
22
I
CC1_LPREF
–
Analog input
23
I
Reference signal for internal use.
CC2_LPRX
–
Analog input
24
I
Configuration channel 2 RX signal for
Low Power states
CC2_LPREF
–
Analog input
25
I
Reference signal for internal use.
CC2
–
Strong drive (push pull)
26
O
Configuration Channel 2
27
O
Open Drain signal to control a PFET
power switch for VCONN on CC1 line
0: VCONN switch closed
z: VCONN switch open
CC1_VCONN_CTRL
Active LOW Open drain, drives low
CC2_VCONN_CTRL
Active LOW Open drain, drives low
28
O
Open Drain signal to control a PFET
power switch for VCONN on CC2 line
0: VCONN switch closed
z: VCONN switch open
IFAULT
Active HIGH Digital input
29
I
Current Fault Indication on VBUS
0: No fault
1: Over Current fault
XRES
Active LOW Analog input
30
I
Reset
Connect 1uf Capacitor between VCCD
and Ground
VCCD
–
–
31
POWER
VDDD
–
–
32
POWER 5-V Supply
VDDA
–
–
33
POWER 5-V Supply
VSSA
–
–
34
GND
–
E-PAD
–
–
E-PAD
GND
–
VBUS_VMON
–
Analog input
35
I
VBUS_VREF
–
Analog input
36
I
VBUS_P_CTRL
Active HIGH Strong drive (Push Pull)
37
O
HOTPLUG_DET
Active HIGH Open drain, drives low
38
IO
Analog input/Strong
drive (Push Pull)
39
IO
Open drain, drives low
40
O
CC_VREF/
VBUS_DISCHARGE
MUXSEL_5
-/Active HIGH
–
Document Number: 001-93639 Rev. *L
VBUS Over-voltage Protection
monitoring signal
VBUS reference signal for Over-voltage
Protection detection
Full rail control signal for
enabling/disabling Provider load FET
HotPlug Detection for Display Port
Alternate Mode
Data reference signal for CC lines /
Signal used for discharging VBUS line
during voltage change
External Data Mux Select signal 5
Page 9 of 31
CCG1 Datasheet
Table 4 provides the pin definition for 16-pin SOIC for the Power Adapter application. Refer to Table 23 on page 23 for part numbers
to package mapping.
Table 4. Pin Definitions for 16-pin SOIC for Power Adapter Application
CYPD
1132-16SXI
Pins
Type
SWD_CLK
1
I
SWD Clock
VBUS_P_CTRL
2
O
Full rail control signal for enabling/disabling provider load FET
VBUS_VMON
3
I
VBUS over-voltage protection monitoring signal
Functional Pin Name
Description
VBUS_VREF
4
I
VBUS reference signal for over-voltage protection detection
XRES
5
–
Active Low Reset
VCCD
6
–
Connect 1 µF capacitor between VCCD and GROUND
VSSD
7
–
Ground
VDDD
8
–
Power 3.3 V/5 V
VSSA
9
–
Ground
CC_VREF/VBUS_DISCHARGE
10
I/O
Data reference signal for CC line (0.55 Volt) / Signal used for
discharging VBUS line during voltage decrease
CC_CTRL
11
I/O
CC1 control
0: TX enabled
z: RX sense
CS
12
I
Low Side Current Sense
VSEL1
13
O
Voltage select signal for selecting the output voltage 5/12/20 V
VSEL2
14
O
Voltage select signal for selecting the output voltage 5/12/20 V
CC
15
I/O
Configuration Channel TX/RX
SWD_IO
16
I/O
SWD I/O
Document Number: 001-93639 Rev. *L
Page 10 of 31
CCG1 Datasheet
Pinouts
40
39
38
37
36
35
34
33
32
31
VBUS_P_CTRL
CC_VREF
VBUS_C_CTRL/VBUS_OK
CC_SEL_REF_3/VSEL1
VBUS_VREF
VBUS_VMON
VSSA
VDDA
VDDD
VCCD
Figure 2. Pinout for CYPD1122-40LQXI/CYPD1121-40LQXI
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
QFN
16
17
18
19
20
GPIO2/CC_SEL_REF_3
GPIO3/iFAULT
I2C_SCL
I2C_SDA
I2C_INT
13
14
15
12
SWD_CLK
HOTPLUG_DET
GPIO1/VSEL2
11
SWD_IO
(Top View )
CC_SEL_REF_1
MUXSEL _1
MUXSEL _2
CC1_CTRL
CC2_CTRL
MUXSEL _3
MUXSEL _4
CS _P
CS_M
VSS
CC1
XRES
CC2_VCONN _CTRL
CC2_RP
CC2_RD
CC2
VBUS _DISCHARGE
CC1_VCONN _CTRL
CC1_RP
CC1_RD
CC_SEL_REF_2
40
39
38
37
36
35
34
33
32
31
MUXSEL_5
CC_VREF/VBUS_DISCHARGE
HOTPLUG_DET
VBUS_P_CTRL
VBUS_VREF
VBUS_VMON
VSSA
VDDA
VDDD
VCCD
Figure 3. Pinout for CYPD1134-40LQXI
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
QFN
(Top View)
16
17
18
19
20
CC2_RP_DEF
CC2_RP_1.5
I2C_SCL
I2C_SDA
I2C_INT
13
SWD_CLK
CC1_RP_3.0
14
15
12
CC1_RP_DEF
11
SWD_IO
21
CC1_RP_1.5
MUXSEL _1
MUXSEL _2
CC1_CTRL
CC2_CTRL
MUXSEL _3
MUXSEL _4
CS _P
CS_M
VSS
CC1
XRES
IFAULT
CC2_VCONN _CTRL
CC1_VCONN _CTRL
CC2
CC2_LPREF
CC2_LPRX
CC1_LPREF
CC1_LPRX
CC2_RP _3.0
Figure 4. Pinout for CYPD1132-16SXI
Document Number: 001-93639 Rev. *L
SWD_CLK
1
16
SWD_IO
VBUS_P_CTRL
2
15
CC
VBUS_VMON
3
14
VSEL2
VBUS_VREF
4
13
VSEL1
XRES
5
12
CS
VCCD
6
11
CC_CTRL
VSSD
7
10
CC_VREF/VBUS_DISCHARGE
VDDD
8
9
SOIC
(Top View)
VSSA
Page 11 of 31
CCG1 Datasheet
Figure 5. Pinout for CYPD1103-35FNXIT/CYPD1131-FNXIT
7
6
5
4
3
2
1
VCCD
GPIO/
CC2_RD
CC1_LPRE
F/CC1_RP
GPIO/
CC1_VCO
NN_CTRL
TX_GND/
VBUS_DIS
CHARGE
GPIO/
I2C_INT
GPIO/
CC_SEL_R
EF_2
A
VSSA
XRES
TX_M/
CC2_VCON
N_CTRL
GPIO/
CC2_RP
TX_U/
CC2
I2C_SDA
I2C_SCL
B
VDDD/
VDDA
VCONN_D
ET/
CC_SEL_R
EF_3
CC_VREF/
VBUS_VRE
F
CC1_RX/
VBUS_VMO
N
CC1_LPRX/
CC1_RD
GPIO/
HOTPLUG_
DET
SWD_CLK
C
CC1_TX/
VBUS_C_C
TRL
GPIO/
MUXSEL_2
BYPASS/
MUXSEL_1
TX_REF_O
UT/
CC_VREF
TX_REF_IN
/CC1_CTRL
GPIO
SWD_IO
D
GPIO/
VBUS_P_C
TRL
GPIO/
MUXSEL_4
RA_FAR_D
ISCONNEC
T/
MUXSEL_3
RA_DISCO
NNECT/
CC2_CTRL
GPIO/
CS_P
GPIO/
CS_M
GPIO/
CC_SEL_R
EF_1
E
Power
The following power system diagram shows the minimum set of
power supply pins as implemented for the CCG1. The system
has one regulator in Active mode for the digital circuitry. There is
no analog regulator; the analog circuits run directly from the
VDDA input. There is a separate regulator for the Deep Sleep
mode. There is a separate low-noise regulator for the bandgap.
The supply voltage range is 3.2 V to 5.5 V with all functions and
circuits operating over that range.
VDDA and VDDD must be shorted together; the grounds, VSSA
and VSS must also be shorted together. Bypass capacitors must
be used from VDDD to ground. The typical practice for systems
in this frequency range is to use a capacitor in the 1-µF range in
parallel with a smaller capacitor (0.1 µF, for example). Note that
these are simply rules of thumb and that, for critical applications,
the PCB layout, lead inductance, and the bypass capacitor
parasitic should be simulated to design and obtain optimal
bypassing.
Refer to Application Diagrams for bypassing schemes.
Document Number: 001-93639 Rev. *L
Page 12 of 31
CCG1 Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 5. Absolute Maximum Ratings[11]
Spec ID
SID1
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VDDD_ABS
Digital supply relative to VSSD
–0.50
–
6.00
V
Absolute max
SID2
VCCD_ABS
Direct digital core voltage input
relative to VSSD
–0.50
–
1.95
V
Absolute max
SID3
VGPIO_ABS
GPIO voltage
–0.50
–
VDDD+0.50
V
Absolute max
SID4
IGPIO_ABS
Maximum current per GPIO
–25.00
–
25.00
mA
Absolute max
SID5
GPIO injection current, Max for VIH >
IGPIO_injection
VDDD, and Min for VIL < VSS
Absolute max,
current injected per pin
BID44
ESD_HBM
BID45
BID46
–0.50
–
0.50
mA
Electrostatic discharge human body
model
2200.00
–
–
V
–
ESD_CDM
Electrostatic discharge charged
device model
500.00
–
–
V
–
LU
Pin current for latch-up
–200.00
–
200.00
mA
–
Device-Level Specifications
All specifications are valid for –40 °C TA 85 °C and TJ 100 °C for 35-CSP and 40-QFN package options. Specifications are valid
for –40 °C TA 105 °C and TJ 120 °C for 16-SOIC package options. Specifications are valid for 3.2 V to VDD’s maximum value,
depending on the type of application.
Table 6. DC Specifications
Spec ID Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VDDD
Power supply input voltage
3.20
–
5.20
V
Notebook, tablet, monitor and
power adapter applications
SID53_A VDDD
SID54
VCCD
Power supply input voltage
3.20
–
5.50
V
EMCA applications
–
1.80
–
V
SID55
CEFC
External regulator voltage bypass
1.00
1.30
1.60
μF
X5R ceramic or better
SID56
CEXC
Power supply decoupling capacitor
–
1.00
–
μF
X5R ceramic or better
T = 25 °C
SID53
Output voltage (for core logic)
–
Active Mode, VDDD = 3.2 to 5.5 V. Typical values measured at VDD = 3.3 V.
SID19
IDD14
Execute from flash; CPU at 48 MHz
–
12.80
–
mA
SID20
IDD15
Execute from flash; CPU at 48 MHz
–
–
13.80
mA
–
Sleep Mode, VDDD = 3.2 to 5.5 V
SID25A
IDD20A
I2C
wakeup and comparators on
–
–
1.70
2.2 0
mA
–
Deep Sleep Mode, VDDD = 3.2 to 3.6 V (Regulator on)
SID31
SID32
IDD26
I2C wakeup on
–
1.30
–
μA
T = 25 °C, 3.6 V
IDD27
I2C
–
–
50.00
μA
T = 85 °C
I2C wakeup
–
15.00
–
μA
T = 25 °C, 5 V
Supply current while XRES asserted
–
2.00
5.00
mA
wakeup on
Deep Sleep Mode, VDDD = 3.6 to 5.5 V
SID34
IDD29
XRES Current
SID307
IDD_XR
–
Note
11. Usage above the absolute maximum conditions listed in Table 5 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 001-93639 Rev. *L
Page 13 of 31
CCG1 Datasheet
Table 7. AC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
DC
–
48.00
MHz
3.2 VDD 5.5
SID48
FCPU
CPU frequency
SID49
TSLEEP
Wakeup from sleep mode
–
0.00
–
µs
Guaranteed by
characterization
SID50
TDEEPSLEEP
Wakeup from Deep Sleep mode
–
–
25.00
µs
24-MHz IMO.
Guaranteed by
characterization
SID52
TRESETWIDTH
External reset pulse width
1.00
–
–
µs
Guaranteed by
characterization
Min
0.70 ×
VDDD
Typ
Max
Units
–
–
V
CMOS Input
–
–
I/O
Table 8. I/O DC Specifications
Spec ID
Parameter
Description
SID57
VIH[12]
Input voltage high threshold
SID58
VIL
Input voltage low threshold
Details/Conditions
SID243 VIH[12]
LVTTL input
2.00
–
0.30 ×
VDDD
–
SID244 VIL
LVTTL input
–
0.80
V
–
SID59
VOH
Output voltage high level
–
–
V
IOH = 4 mA at 3 V VDDD
SID62
VOL
Output voltage low level
–
VDDD –
0.60
–
–
0.60
V
IOL = 8 mA at 3 V VDDD
SID62A VOL
Output voltage low level
–
–
0.40
V
IOL = 3 mA at 3 V VDDD
SID63
RPULLUP
Pull-up resistor
3.50
5.60
8.50
kΩ
–
SID64
RPULLDOWN
Pull-down resistor
3.50
5.60
8.50
kΩ
SID65
IIL
–
–
2.00
nA
–
–
4.00
nA
–
–
7.00
pF
V
CMOS Input
V
–
SID66
CIN
Input leakage current (absolute value)
Input leakage current (absolute value)
for analog pins
Input capacitance
SID67
VHYSTTL
Input hysteresis LVTTL
15.00
40.00
–
mV
SID68
VHYSCMOS
Input hysteresis CMOS
200.00
–
–
mV
SID69
IDIODE
–
–
100.00
μA
–
–
200.00
mA
SID65A IIL_CTBM
SID69A ITOT_GPIO
Current through protection diode to
VDD/VSS
Maximum Total Source or Sink Chip
Current
–
25 °C, VDDD = 3.0 V
–
–
VDDD 2.7 V.
Guaranteed by characterization
VDDD 4.5 V.
Guaranteed by characterization
Guaranteed by characterization
Guaranteed by characterization
Table 9. I/O AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter
SID70
TRISEF
Rise time
SID71
TFALLF
Description
Fall time
Min
2.00
Typ
–
Max
12.00
Units
ns
Details/Conditions
3.3-V VDDD, Cload = 25 pF
2.00
–
12.00
ns
3.3-V VDDD, Cload = 25 pF
Note
12. VIH must not exceed VDDD + 0.2 V.
Document Number: 001-93639 Rev. *L
Page 14 of 31
CCG1 Datasheet
XRES
Table 10. XRES DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID77
VIH
Input voltage high threshold
0.70 × VDDD
–
–
V
CMOS input
SID78
VIL
Input voltage low threshold
–
–
0.30 × VDDD
V
CMOS input
SID79
RPULLUP
Pull-up resistor
3.50
5.60
8.50
kΩ
–
SID80
CIN
Input capacitance
–
3.00
–
pF
–
SID81
VHYSXRES
Input voltage hysteresis
–
100.00
–
mV
Guaranteed by
characterization
SID82
IDIODE
Current through protection diode to
VDDD/VSS
–
–
100.00
µA
Guaranteed by
characterization
Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
Pulse Width Modulation (PWM) for VSEL and CUR_LIM Pins
Table 11. PWM AC Specifications
(Guaranteed by Characterization)
Min
Typ
Max
Units
Details/Conditions
SID140
Spec ID
TPWMFREQ
Parameter
Operating frequency
Description
–
–
48.00
MHz
–
SID141
TPWMPWINT
Pulse width (internal)
42.00
–
–
ns
–
SID142
TPWMEXT
Pulse width (external)
42.00
–
–
ns
–
SID143
TPWMKILLINT
Kill pulse width (internal)
42.00
–
–
ns
–
SID144
TPWMKILLEXT
Kill pulse width (external)
42.00
–
–
ns
–
SID145
TPWMEINT
Enable pulse width (internal)
42.00
–
–
ns
–
SID146
TPWMENEXT
Enable pulse width (external)
42.00
–
–
ns
–
SID147
TPWMRESWINT Reset pulse width (internal)
42.00
–
–
ns
–
SID148
TPWMRESWEXT Reset pulse width (external)
42.00
–
–
ns
–
I2C
Table 12. Fixed I2C DC Specifications
(Guaranteed by Characterization)
Min
Typ
Max
Units
Details/Conditions
SID149
Spec ID
II2C1
Block current consumption at 100 kHz
–
–
50
µA
–
SID150
II2C2
Block current consumption at 400 kHz
–
–
135.00
µA
–
SID151
II2C3
Block current consumption at 1 Mbps
–
–
310.00
µA
–
II2C4
I2C
–
–
1.40
µA
–
Min
Typ
Max
Units
Details/Conditions
–
–
1.00
Mbps
–
SID152
Parameter
Description
enabled in Deep Sleep mode
Table 13. Fixed I2C AC Specifications
(Guaranteed by Characterization)
Spec ID
SID153
Parameter
FI2C1
Description
Bit rate
Document Number: 001-93639 Rev. *L
Page 15 of 31
CCG1 Datasheet
Memory
Table 14. Flash DC Specifications
Spec ID
SID173
Parameter
Description
VPE
Erase and program voltage
Min
Typ
Max
Units
Details/Conditions
3.20
–
5.50
V
–
Min
Typ
Max
Table 15. Flash AC Specifications
Spec ID
Parameter
Description
[13]
SID174
TROWWRITE
SID175
TROWERASE[13]
[13]
Units
Details/Conditions
Row (block) write time (erase and
program)
Row (block) =
128 bytes
–
–
20.00
ms
Row erase time
–
–
13.00
ms
–
SID176
TROWPROGRAM
Row program time after erase
–
–
7.00
ms
–
SID178
TBULKERASE[13]
Bulk erase time (32 KB)
–
–
35.00
ms
–
SID180
TDEVPROG[13]
Total device program time
–
–
7.00
seconds
Guaranteed by
characterization
SID181
FEND
Flash endurance
100 K
–
–
cycles
Guaranteed by
characterization
SID182
FRET[14]
Flash retention. TA 55 °C, 100 K P/E
cycles
20
–
–
years
Guaranteed by
characterization
SID182A
–
Flash retention. TA 85 °C, 10 K P/E
cycles
10
–
–
years
Guaranteed by
characterization
SID182B
–
Flash retention. 85 °C < TA < 105 °C,
10K P/E cycles
3
–
–
years
Guaranteed by
characterization
System Resources
Power-on-Reset (POR) with Brown Out
Table 16. Imprecise Power On Reset (PRES)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
0.80
–
1.45
V
Guaranteed by characterization
SID185
VRISEIPOR
Rising trip voltage
SID186
VFALLIPOR
Falling trip voltage
0.75
–
1.40
V
Guaranteed by characterization
SID187
VIPORHYST
Hysteresis
15.0
–
200.0
mV
Guaranteed by characterization
Min
Typ
Max
Units
Details/Conditions
Table 17. Precise Power On Reset (POR)
Spec ID
Parameter
Description
SID190
VFALLPPOR
BOD trip voltage in active and
sleep modes
1.64
–
–
V
Guaranteed by characterization
SID192
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.40
–
–
V
Guaranteed by characterization
Notes
13. It can take as much as 20 milliseconds to write to flash. During this time the device should not be Reset, or flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
14. Cypress provides a retention calculator to calculate the retention lifetime based on customers' individual temperature profiles for operation over the –40 °C to +105 °C
ambient temperature range. Contact customercare@cypress.com.
Document Number: 001-93639 Rev. *L
Page 16 of 31
CCG1 Datasheet
SWD Interface
Table 18. SWD Interface Specifications
Spec ID
SID213
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
–
–
14.00
MHz
SWDCLK ≤1/3 CPU clock
frequency
3.2 V VDDD 5.5 V
F_SWDCLK1
SID215
T_SWDI_SETUP T = 1/f SWDCLK
0.25 × T
–
–
ns
Guaranteed by characterization
SID216
T_SWDI_HOLD
0.25 × T
–
–
ns
Guaranteed by characterization
SID217
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.50*T
ns
Guaranteed by characterization
SID217A T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
ns
Guaranteed by characterization
Description
Min
Typ
Max
Units
Details/Conditions
IMO operating current at 48 MHz
–
–
1000.00
µA
–
Min
Typ
Max
Units
Details/Conditions
–
–
±2.00
%
T = 1/f SWDCLK
Internal Main Oscillator
Table 19. IMO DC Specifications
(Guaranteed by Design)
Spec ID
SID218
Parameter
IIMO1
Table 20. IMO AC Specifications
Spec ID
SID223
Parameter
Description
FIMOTOL1
Frequency variation
SID226
TSTARTIMO
IMO startup time
–
–
12.00
µs
–
SID229
TJITRMSIMO3
RMS Jitter at 48 MHz
–
139.00
–
ps
–
With API-called calibration
Internal Low-Speed Oscillator
Table 21. ILO DC Specifications
(Guaranteed by Design)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID231
IILO1
ILO operating current at 32 kHz
–
0.30
1.05
µA
Guaranteed by characterization
SID233
IILOLEAK
ILO leakage current
–
2.00
15.00
nA
Guaranteed by design
Min
Typ
Max
Units
Table 22. ILO AC Specifications
Spec ID
Parameter
Description
Details/Conditions
SID234
TSTARTILO1
ILO startup time
–
–
2.00
ms
Guaranteed by characterization
SID236
TILODUTY
ILO duty cycle
40.00
50.00
60.00
%
Guaranteed by characterization
SID237
FILOTRIM1
32-kHz trimmed frequency
15.00
32.00
50.00
kHz
Document Number: 001-93639 Rev. *L
±60% with trim
Page 17 of 31
CCG1 Datasheet
Applications in Detail
Figure 6. Single Chip/Cable, Component Count = 19
Type-C Plug
Type-C Plug
VBUS
VCONN 1
BAT54V-7
A1
100k
10%
C2
VCONN 2
A2
100k
10%
12.4k 1%100k 1%
D
TF412S
G
BAT54V-7
C1
806
1%
D
TF412S
G
S
S
806
Ra_Far
1%
1uF
Ra
A5
CC1_LPREF
C7
VDDD
GPIO
C6 VCONN_DET
E4
TX_REF_OUT
RA_DISCONNECT
E5 RA_FAR_DISCONNECT
B6
47pF
D5
1uF A7
B7
BYPASS
D4
CC_VREF C5
TX_GND
XRES
A1, A2, A4, A6, B4, C2, D2,
D6, E1, E2, E3, E6, E7
A3 2k 1%
CYPD1103-35FNXI
D3
35CSP
TX_REF_IN
B5
TX_M
TX_U B3
VCCD
CC1_TX
VSSA
I2C_ I2C_ SWD_ SWD_
IO
CLK
SCL SDA
B2
D1
C1
B1
D7
2.2nf
2.4k 1%
2k 1%
22 1%
C4
CC1_RX
C3
CC1_LPRX
S
G
NTNS3164NZ
D
CC
CC
SuperSpeed and HighSpeed Lines
GND
Document Number: 001-93639 Rev. *L
Page 18 of 31
CCG1 Datasheet
Figure 7. Two Chip/Cable, Component Count = 15/paddle
Type-C Plug
Type-C Plug
VBUS
VBUS
VCONN 1
100k
10%
VCONN 2
D
12.4k 1% 100k 1%
TF412S
G
100k
10%
12.4k 1% 100k 1%
D
TF412S
G
S
S
Ra
1%
1uF
A5
CC1_LPREF
1uF
C7
VDDD
GPIO
TX_REF_OUT
RA_DISCONNECT
E5 RA_FAR_DISCONNECT
B6
47pF
D5
1uF
A7
B7
CC_VREF
TX_GND
XRES
BYPASS
VCCD
A5
CC1_LPREF
A1, A2, A4, A6, B4, C2, D2,
D6, E1, E2, E3, E6, E7
C6
C6 VCONN_DET
E4
D4
E4
C5
A3 2k 1%
2k 1%
CYPD1103-35FNXI
D3
35CSP
TX_REF_IN
B5
TX_M
B3
TX_U
D7
CC1_TX
2.2nf
2.4k 1%
I2C_ I2C_ SWD_ SWD_
SCL SDA
IO
CLK
B2
D1
C1
B1
C7
VDDD
GPIO
VCONN_DET
TX_REF_OUT
RA_DISCONNECT
B6
47pF
D5
1uF A7
22 1%
C4
CC1_RX
C3
CC1_LPRX
XRES
S
G
TX_U B3
CC1_TX D7
VCCD
VSSA
I2C_ I2C_ SWD_ SWD_
SCL SDA
IO
CLK
B1
B2
D1
C1
CC
D4
A3 2k 1%
CYPD1103-35FNXI TX_GND
D3
35CSP
TX_REF_IN
TX_M B5
BYPASS
Ra
A1, A2, A4, A6, B4, C2, D2,
D6, E1, E2, E3, E6, E7
CC_VREF C5
E5 RA_FAR_DISCONNECT
B7
VSSA
806
1%
2.2nf
2.4k 1%
2k 1%
22 1%
CC1_RX C4
CC1_LPRX C3
S
NTNS3164NZ
NTNS3164NZ
G
D
D
CC
SuperSpeed and HighSpeed Lines
SuperSpeed and HighSpeed Lines
GND
GND
Figure 8. 16-pin SOIC Power Adapter Application Diagram
PFET
5-20 Volts
From
Secondary
Side
DMG7401SFG-7
49.9k
1%
S
VBUS
D
G
100
1%
NFET
MGSF1N03L
G
3.9k1%
5V
0
0
12V
0
1
19.6V
1
0
To
Primary
Side
13
14
CS
VSEL1
VSEL2
3
2
3.3V
21.5k1%
VBUS_DISCHARGE/
CC_VREF
10
5.6K 1%
CYPD1132-16SXI
16SOIC
3.3v
16
SWD_IO
1
SWD_CLK
Rp
CC
5 XRES
15
VSSD
7
VSSA
9
CC_CTRL
11
4.7k 1%
3.3v
84.51%
51.11%
0.1uF
Document Number: 001-93639 Rev. *L
VBUS_DISCHARGE
4
VBUS_VREF
8
VDDD
VCCD
12
VSEL2
MGSF1N03LT1G
1uF
6
VSEL1
0.1uF
100k
1uF
VBUS
10k1%
S
VBUS_VMON
0.1uF
D
VBUS_P_CTRL
Rsense
10 m
10uF
3.3v
NFET
MGSF1N03L
Select
NFET
with Vth
> 1V
VBUS_DISCHARGE
Sense Resistor on the
return path of Secondary
100k1%
1k1%
4.7nF
330pF
NTS3164NZ
CC
CCG1 supports up to 2.2kV ESD
protection. If higher protection is
required, add external ESD.
Page 19 of 31
CCG1 Datasheet
Figure 9. Notebook (DRP) Application Diagram
To System
PFET
D
S
From
System
S
D
50k
5%
G
G
VBUS
PFET
5V
D
S
S
D
50k
5%
G
G
100k 1%
5 Volts
100 1% 1W
10k 1%
CS_P
NFET
D
D
VBUS_DISCHARGE
S
10k 1%
VDDD = 5V
0.1uF
NFET
G
CS_M
S
S
D
0.2 1%
3.9k 1%
G
G
Select
NFET
with Vth
> 1V
S
1uF
PFET
G
D
VBUS_DISCHARGE
1 MUXSEL_1
2 MUXSEL_2
5 MUXSEL_3
6 MUXSEL_4
24
VBU S_VREF
NFET
S
CC1_RP
CC1_RD
CC1_CTRL
S
10
USB
Chipset
HPD
DP0/1/2/3
Document Number: 001-93639 Rev. *L
S
VDDD
CC1
Type C
Receptacle
3
10k 1%
S
CC2_VCONN_CTRL
29
D
287 1%
PFET
NFET
S
D
G
2.2nF
VDDD
330pF
1M, 5%
CC2_CTRL 4
5.1k
10%
Rd
D
NFET
34
11
21
CC_VREF
CC_SEL_REF_3
CC_SEL_REF_2
VSSA
VSS
9
CC_SEL_REF_1
G
SS
AUX+/-
NFET
G
D
G
40QFN
4.1k
1%
DisplayPort
Chipset
G
2.2nF
80.6 1%
I2C_SDA
20 I2C_INT
XRES
5.1k
10%
Rd
CC2
19
0.1uF
NFET
287 1%
CYPD1122 -40LQXI
18 I2C_SCL
HS
1M, 5%
D
22
CC2 26
30
330pF
VDDD
10k 1%
CC1
12
SWD_IO
13
SWD_CLK
Embedded
Controller
D
G
Rp
23
80.6 1%
14 HOTPLUG_DET
HPD
VBUS_VMON
VBUS_C_CTRL/VBUS_OK
7 CS_P
8
CS_M
15 GPIO1
16 GPIO2
17 GPIO3
25 VBUS_DISCHARGE
CS_P
CS_M
35 36
CC1_VCONN_CTRL
38
40
VBUS_P_CTRL
VDD A
32
VDDD
33
VCCD
31
1uF
37
CC2_RP
CC2_RD
28
Rp
27
S
NFET
S
D
G
39
5 Volts
3.16k
1%
10k
1%
VDDD
HS
MUXSEL_x
2.32k
1%
21.5k 1%
SS/DP0/1
DP2/3
HS/SS/
DP/SBU
Lines
HS/SS/DP
Mux
AUX+/-
Page 20 of 31
CCG1 Datasheet
Figure 10. Notebook (DFP) Application Diagram
From
System
VBUS
PFET
5V
D
S
S
D
50k
5%
G
0.02 1%
G
100k 1%
Current Monitor
+ Comparator
5 Volts
10k 1%
100 1% 1W
iFAULT
CS_P
NFET
D
D
0.2 1%
3.9k 1%
G
VBUS_DISCHARGE
CS_M
S
10k 1%
VDDD = 5V
0.1uF
NFET
G
S
Select
NFET
with Vth
> 1V
S
1uF
PFET
G
D
VBUS_VREF
27
CC1_VCONN_CTRL
7 CS_P
8
CS_M
CS_P
CS_M
35 36
37
VBUS_VMON
VDDD
32
VBUS_P_CTRL
VCCD
VDDA
31 33
1uF
iFAULT
CC1_CTRL
1 MUXSEL_1
2 MUXSEL_2
5 MUXSEL_3
6 MUXSEL_4
40 MUXSEL_5
CC2_VCONN_CTRL
40QFN
USB
Chipset
23 25
9
34
CC_VREF/
VBUS_DISCHARGE
VSSA
VSS
CC2_LPREF
XRES
D
287 1%
NFET
S
2.2nF
G
D
390pF
VDDD
CC2_CTRL 4
CC1_LPREF
30
0.1uF
PFET
G
80.6 1%
19
HS
CC2
S
CC2 26
18 I2C_SCL
I2C_SDA
20 I2C_INT
Type C
Receptacle
10k 1%
28
24
CC2_LPRX
12
SWD_IO
13
SWD_CLK
Embedded
Controller
CC1
2.2nF
3
CYPD1134 -40LQXI
38 HOTPLUG_DET
HPD
390pF
287 1%
80.6 1%
iFAULT
D
G
VDDD
10k 1%
CC1_RP_3.0 14
22
CC1_LPRX
10
S
22k 1%
CC1_RP_1.5 11
CC1
29
NFET
56k 1%
CC1_RP_DEF 15
CC2_RP_DEF
16
CC2_RP_1.5 17
CC2_RP_3.0
21
56k 1%
22k 1%
10k 1%
39
HS
5 Volts
SS
MUXSEL_x
21.5k 1%
DisplayPort
Chipset
HPD
DP0/1/2/3
AUX+/-
Document Number: 001-93639 Rev. *L
VBUS_DISCHARGE
3.42k 1%
SS/DP0/1
DP2/3
HS/SS/
DP/SBU
Lines
HS/SS/DP
Mux
AUX+/-
Page 21 of 31
CCG1 Datasheet
Figure 11. Monitor Application Block Diagram
DC Input
5/12/20V
DC/DC
VBUS
PFET
D
S
S
D
50k
5%
G
G
100k 1%
5 Volts
100 1%, 1W
10k 1%
D
D
NFET
G
VBUS_DISCHARGE
3.9k 1%
CS_P
0.2 1%
S
CS_M
REG
12V
0
0
0
1
0
0V
1
1
1
2
5
6
14
HPD
HS
USB
Chipset
DisplayPort
Chipset
SS
HPD
DP0/1/2/3
AUX+/-
Document Number: 001-93639 Rev. *L
10
G
D
330pF
VDDD
VDDA
VDDD
VBUS_VREF
80.6 1%
CC1
2.2nF
Type C
Receptacle
3
CYPD1121-40LQXI
CC2
S
40QFN
CC2_VCONN_CTRL
HOTPLUG_DET
29
26
PFET
G
D
287 1%
NFET
S
80.6 1%
D
G
2.2nF
330pF
VDDD
9
34
4.1k
1%
11
21
CC_VREF
CC_SEL_REF_3
CC_SEL_REF_2
VSSA
CC_SEL_REF_1
CC2_CTRL 4
VSS
XRES
NFET
287 1%
10k
18
I2C_SCL
19
I2C_SDA
20 I2C_INT
30
5.1k
1%
S
CC1
12
SWD_IO
13
SWD_CLK
0.1uF
Rd
22
CC1_RD
CC2
Embedded
Controller
Rp 10k
1%
23
CC1_RP
CC1_CTRL
MUXSEL_1
MUXSEL_2
MUXSEL_3
MUXSEL_4
PFET
D
24
17
iFAULT
38
VBUS_C_CTRL/VBUS_OK
1
19.6V
7
CS_P
8 CS_M
37 VSEL1
15 VSEL2
35 36
25
CC1_VCONN_CTRL
5V
NFET
Select
NFET
with Vth
> 1V
S
G
VBUS_VMON
CS_P
CS_M
40
VBUS_DISCHARGE
VSEL2
32
VBUS_P_CTRL
VSEL1
33
VCCD
1uF
VBUS
VBUS_
DISCHARGE
1uF
31
S
10k 1%
VDDD = 5V
0.1uF
G
16
CC2_RP
CC2_RD
28
Rp 10k
1%
27
Rd 5.1k
1%
HS
39
5 Volts
3.16k
1%
MUXSEL_x
2.32k
1%
21.50k 1%
SS/DP0/1
DP2/3
HS/SS/
DP/SBU
Lines
HS/SS/DP
Mux
AUX+/-
Page 22 of 31
CCG1 Datasheet
Ordering Information
The CCG1 part numbers and features are listed in the following table.
Table 23. CCG1 Ordering Information
Part Number[15]
Application
Type-C Overcurrent Overvoltage Termination
Ports[16] Protection
Protection
Resistor[17]
Role[18]
Package
Si ID
35-WLCSP[20] 0490
CYPD1103-35FNXIT Cable, EMCA
1
No
No
Ra[19]
Notebook,
CYPD1131-35FNXIT Tablet,
Smartphone
1
Yes
Yes
Rp[23], Rd[21]
DRP[24] 35-WLCSP[22] 0491
CYPD1121-40LQXI
Monitor
1
Yes
Yes
Rp[23], Rd[21]
DRP[24] 40-QFN
0489
CYPD1122-40LQXI
Notebook
1
Yes
Yes
Rp[23], Rd[21]
DRP[24] 40-QFN
048A
CYPD1134-40LQXI
Notebook,
Desktop
1
Yes
Yes
Rp[23]
DFP
40-QFN
048B
CYPD1132-16SXI
Power Adapter
1
Yes
Yes
Rp[23]
DFP
16-SOIC
0498
Yes
[23]
DFP
16-SOIC
0498
CYPD1132-16SXQ
Power Adapter
1
Yes
Rp
Cable
Ordering Code Definitions
CY PD X X XX - XX XX X X X
T = Tape and reel for CSP, N/A for other packages
Temperature Range: I = Industrial; Q = Extended Industrial
Lead: X = Pb-free
Package Type: LQ = QFN; FN = CSP; S = SOIC
Number of pins in the package
0X: OCP and OVP not supported; 1X: reserved; 2X, 3X: OCP and OVP supported
Number of Type-C Ports: 1 = 1 Port; 2 = 2 Port
Product Type: 1 = First-generation product family, CCG1
Marketing Code: PD = Power delivery product family
Company ID: CY = Cypress
Notes
15. All part numbers support: Input voltage range from 3.2 V to 5.5 V. Industrial parts support -40 °C to +85 °C, Extended Industrial parts support -40 °C to 105 °C.
16. Number of USB Type-C Ports supported .
17. Default VCONN termination.
18. PD Role.
19. Type-C Cable Termination.
20. 35-WLCSP #1 pinout.
21. USB Device Termination.
22. 35-WLCSP #2 pinout.
23. USB Host Termination.
24. Dual Role Port.
Document Number: 001-93639 Rev. *L
Page 23 of 31
CCG1 Datasheet
Packaging
Table 24. Package Characteristics
Conditions
Min
Typ
Max
Units
TA (40-QFN, 35-CSP)
Parameter
Operating ambient temperature
Description
–
–40
25.00
85.00
°C
TJ (40-QFN, 35-CSP)
Operating junction temperature
–
–40
–
100.00
°C
TA (16-SOIC)
Operating ambient temperature
–
–40
25.00
105.00
°C
TJ (16-SOIC)
Operating junction temperature
–
–40
–
120.00
°C
TJA
Package JA (40-pin QFN)
–
–
15.34
–
°C/Watt
TJA
Package JA (35-CSP)
–
–
28.00
–
°C/Watt
TJA
Package JA (16-SOIC)
–
–
85.00
–
°C/Watt
TJC
Package JC (40-pin QFN)
–
–
02.50
–
°C/Watt
TJC
Package JC (35-CSP)
–
–
00.40
–
°C/Watt
TJC
Package JC (16-SOIC)
–
–
49.00
–
°C/Watt
Table 25. Solder Reflow Peak Temperature
Package
16-pin SOIC
Maximum Peak Temperature
Maximum Time at Peak Temperature
260 °C
30 seconds
40-pin QFN
260 °C
30 seconds
35-ball WLCSP
260 °C
30 seconds
Table 26. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
16-pin SOIC
MSL 3
40-pin QFN
MSL 3
35-ball WLCSP
MSL 1
Document Number: 001-93639 Rev. *L
Page 24 of 31
CCG1 Datasheet
Figure 12. 40-pin QFN Package Outline, 001-80659
001-80659 *A
The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance.
If not connected to ground, it should be electrically floating and not connected to any other signal.
Figure 13. 35-Ball WLCSP Package Outline, 001-93741
SIDE VIEW
TOP VIEW
1
2
3
4
5
6
7
A
BOTTOM VIEW
7
6
5
4
3
2
1
A
B
B
C
C
D
D
E
E
NOTES:
1. REFERENCE JEDEC PUBLICATION 95, DESIGN GUIDE 4.18
2. ALL DIMENSIONS ARE IN MILLIMETERS
Document Number: 001-93639 Rev. *L
001-93741 **
Page 25 of 31
CCG1 Datasheet
Figure 14. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068
51-85068 *F
Document Number: 001-93639 Rev. *L
Page 26 of 31
CCG1 Datasheet
Acronyms
Table 27. Acronyms Used in this Document
Acronym
Description
Table 27. Acronyms Used in this Document (continued)
Acronym
Description
opamp
operational amplifier
OCP
Overcurrent protection
OVP
Overvoltage protection
PCB
printed circuit board
PGA
programmable gain amplifier
PHY
physical layer
POR
power-on reset
ADC
analog-to-digital converter
API
application programming interface
ARM®
advanced RISC machine, a CPU architecture
CC
Configuration Channel
CPU
central processing unit
CRC
cyclic redundancy check, an error-checking
protocol
CS
Current Sense
PRES
DFP
downstream facing port
PSoC
Programmable System-on-Chip™
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
PWM
pulse-width modulator
RAM
random-access memory
EEPROM
electrically erasable programmable read-only
memory
RISC
reduced-instruction-set computing
EMI
electromagnetic interference
ESD
electrostatic discharge
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
IC
®
precise power-on reset
RMS
root-mean-square
RTC
real-time clock
RX
receive
SAR
successive approximation register
SCL
I2C serial clock
SDA
I2C serial data
integrated circuit
S/H
sample and hold
IDE
integrated development environment
SPI
I2C, or IIC
Inter-Integrated Circuit, a communications
protocol
Serial Peripheral Interface, a communications
protocol
SRAM
static random access memory
ILO
internal low-speed oscillator, see also IMO
SWD
serial wire debug, a test protocol
IMO
internal main oscillator, see also ILO
TX
transmit
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
I/O
input/output, see also GPIO, DIO, SIO, USBIO
LVD
low-voltage detect
LVTTL
low-voltage transistor-transistor logic
MCU
microcontroller unit
NC
UFP
upstream facing port
USB
Universal Serial Bus
no connect
USBIO
USB input/output, PSoC pins used to connect to
a USB port
NMI
nonmaskable interrupt
XRES
external reset I/O pin
NVIC
nested vectored interrupt controller
Document Number: 001-93639 Rev. *L
Page 27 of 31
CCG1 Datasheet
Document Conventions
Units of Measure
Table 28. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
Hz
hertz
KB
1024 bytes
kHz
kilohertz
k
kilo ohm
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
V
volt
Document Number: 001-93639 Rev. *L
Page 28 of 31
CCG1 Datasheet
Revision History
Description Title: CCG1 Datasheet USB Type-C Port Controller with Power Delivery
Document Number: 001-93639
Submission
Date
Revision
ECN
**
4520316
09/30/2014 New datasheet
4531795
Updated Functional Definition.
Updated Figure 8, Figure , Figure 7, Figure , Figure 14, Figure 9.
Added Figure 11.
Updated Pinouts.
Updated Power.
10/13/2014 Updated Figure , Figure 8.
Updated Ordering Information
Added Note 24 and referred the same note in 40-pin QFN corresponding to
CYPD1122-40LQXI.
Added Note 27 and referred the same note in 40-pin QFN corresponding to
CYPD1134-40LQXI.
*B
4569912
Updated Features.
Added 16-pin SOIC related information.
Updated Functional Definition.
Updated Pin Definitions.
Added Table 2.
Updated Pinouts.
Updated Figure 2, Figure 5.
Added Figure 4.
Updated Power.
Updated Figure , Figure 8.
Added Figure 6.
Updated Electrical Specifications.
11/21/2014 Updated Device-Level Specifications.
Updated Memory.
Added Note 14 and referred the same note in FRET parameter.
Added details corresponding to spec ID SID182B under FRET parameter.
Updated Figure 14, Figure 9, Figure 11. Added Figure 8 and Figure 10.
Updated Ordering Information.
Updated part numbers.
Added a column “Si ID”.
Updated Packaging.
Updated Table 24.
Updated details in maximum value column corresponding to TA and TJ parameters.
Added 16-pin SOIC related information.
Updated Table 25.
*C
4596141
12/14/2014
*D
4646123
Updated pin definitions for 40-pin QFN and 35-ball WLCSP.
Updated Pinout for CYPD1122-40LQXI/CYPD1121-40LQXI and Ordering Information.
02/04/2015
Updated conditions for Device-Level Specifications.
Updated diagrams in Applications in Detail section.
*E
4686050
Removed information about 28-pin SSOP.
03/13/2015 Updated Table 3, Table 23, Table 24, Table 25, Table 26, Table 27.
Updated Figure 2, Figure .
4747272
Updated General Description.
Added Note 1 and referenced it in Features.
05/13//2015 Updated Figure 6, Figure 8 through Figure 11.
Removed Figure 9. Single Chip/Cable, Component Count = 13.
Removed Figure 11. Two Chip/Cable, Component Count = 11/paddle.
*A
*F
Document Number: 001-93639 Rev. *L
Description of Change
Updated Figure 6, Figure 14, Figure 16.
Updated Table 8, Table 23.
Page 29 of 31
CCG1 Datasheet
Revision History (continued)
Description Title: CCG1 Datasheet USB Type-C Port Controller with Power Delivery
Document Number: 001-93639
Revision
ECN
Submission
Date
Description of Change
*G
4800534
Updated Low-Power Operation.
Updated the number of GPIOs to “up to 30” in GPIO.
Updated “1.8 to 5.5 V” to “3.2 V to 5.5 V” in Low-Power Operation, Power System, Power,
Device-Level Specifications and Note 15.
Updated Table 2, Table 4, Table 5, Table 6, Table 7, Table 8, Table 14 and Table 18.
07/02/2015
Added table footnotes 8, 9 and 10.
Deleted footnotes 25 through 28.
Updated Figure 2 and Figure 8 through Figure 11.
Added Figure 3.
Updated the following in Power: Removed Figures 5 through 8. Updated the section.
*H
4939764
09/29/2015
Removed specs SID241 and 242.
Updated 40-pin QFN package to current revision.
*I
5179365
03/17/2016
Updated max value of II2C1 from 10.50 µA to 50 µA.
Updated copyright information and sales links at the end of the document.
*J
5459633
Added compliance information regarding the USB Specification.
10/03/2016 Updated copyright notice to include WICED.
Added IoT link in Sales, Solutions, and Legal Information.
*K
5725038
05/03/2017
*L
7036611
Updated General Description: Added “THIS PRODUCT IS NOT RECOMMENDED FOR
12/03/2020 NEW DESIGNS” on page 1.
Updated Figure 14 in Packaging (spec 51-85068 *E to *F).
Document Number: 001-93639 Rev. *L
Updated Cypress logo.
Updated Copyright information.
Page 30 of 31
CCG1 Datasheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
Notice regarding compliance with Universal Serial Bus specification: Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB Type-C™
Cable and Connector Specification, and other specifications of USB Implementers Forum, Inc (USB-IF). You may use Cypress or third-party software tools, including sample code, to modify the firmware
for Cypress USB products. Modification of such firmware could cause the firmware/hardware combination to no longer comply with the relevant USB-IF specification. You are solely responsible for
ensuring the compliance of any modifications you make, and you must follow the compliance requirements of USB-IF before using any USB-IF trademarks or logos in connection with any modifications
you make. In addition, if Cypress modifies firmware based on your specifications, then you are responsible for ensuring compliance with any desired standard or specifications as if you had made the
modification. CYPRESS IS NOT RESPONSIBLE IN THE EVENT THAT YOU MODIFY OR HAVE MODIFIED A CERTIFIED CYPRESS PRODUCT AND SUCH MODIFIED PRODUCT NO LONGER
COMPLIES WITH THE RELEVANT USB-IF SPECIFICATIONS.
© Cypress Semiconductor Corporation, 2014-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or
firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, "Security
Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device"
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-93639 Rev. *L
Revised December 3, 2020
Page 31 of 31
工商网监
湘ICP备2023018690号
