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CYPD3126-42FNXIT

CYPD3126-42FNXIT

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    42-UFBGA,CSPBGA

  • 描述:

    CCG3

  • 数据手册
  • 价格&库存
CYPD3126-42FNXIT 数据手册
Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com EZ-PD™ CCG3 USB Type-C Port Controller General Description EZ-PD™ CCG3 is a highly integrated USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG3 provides a complete USB Type-C and USB-Power Delivery port control solution for notebooks, dongles, monitors, docking stations and power adapters. CCG3 uses Cypress’s proprietary M0S8 technology with a 32-bit, 48-MHz ARM® Cortex® -M0 processor with 128-KB flash, 8-KB SRAM, 20 GPIOs, full-speed USB device controller, a Crypto engine for authentication, a 20V-tolerant regulator, and a pair of FETs to switch a 5V (VCONN) supply, which powers cables. CCG3 also integrates two pairs of gate drivers to control external VBUS FETs and system level ESD protection. CCG3 is available in 40-QFN, 32-QFN, and 42-WLCSP packages. Features Clocks and Oscillators ■ Type-C and USB-PD Support Integrated oscillator eliminating the need for external clock ■ Integrated USB Power Delivery 3.0 support Integrated USB-PD BMC transceiver ■ Integrated VCONN FETs ■ Configurable resistors RA, RP, and RD ■ Dead Battery Detection support ■ Integrated fast role swap and extended data messaging ■ Supports one USB Type-C port ■ Integrated Hardware based overcurrent protection (OCP) and overvoltage protection (OVP) Power ■ ■ 2.7 V to 21.5 V operation ■ 2x Integrated dual-output gate drivers for external VBUS FET switch control ■ Independent supply voltage pin for GPIO that allows 1.71 V to 5.5 V signaling on the I/Os ■ Reset: 30 µA, Deep Sleep: 30 µA, Sleep: 3.5 mA 32-bit MCU Subsystem ■ ■ 48-MHz ARM Cortex-M0 CPU 128-KB Flash ■ 8-KB SRAM ■ ■ On CC, SBU, DPLUS, DMINUS and VBUS pins ± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based on IEC61000-4-2 level 4C Packages Integrated Digital Blocks Hardware Crypto block enables Authentication Full-Speed USB Device Controller supporting Billboard Device Class ■ Integrated timers and counters to meet response times required by the USB-PD protocol ■ Four run-time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI, or UART functionality ■ ■ Cypress Semiconductor Corporation Document Number: 002-03288 Rev. *J System-Level ESD Protection • ■ 40-pin QFN, 32-pin QFN, and 42-ball CSP for Notebooks/Accessories ■ Supports industrial temperature range (–40 °C to +105 °C) 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 23, 2018 EZ-PD™ CCG3 Logic Block Diagram Document Number: 002-03288 Rev. *J Page 2 of 45 EZ-PD™ CCG3 Contents EZ-PD CCG3 Block Diagram ............................................ 4 Functional Overview ........................................................ 5 CPU and Memory Subsystem ..................................... 5 Crypto Block ................................................................ 5 Integrated Billboard Device ......................................... 5 USB-PD Subsystem (USBPD SS) .............................. 5 Full-Speed USB Subsystem ........................................ 6 Peripherals .................................................................. 6 GPIO ........................................................................... 7 Power Systems Overview ................................................ 8 Pinouts .............................................................................. 9 Available Firmware and Software Tools ....................... 13 EZ-PD Configuration Utility ....................................... 13 CCG3 Programming and Bootloading .......................... 14 Programming the Device Flash over SWD Interface ..................................................................... 14 Application Firmware Update over Specific Interfaces (I2C, CC, USB) ......................................... 14 Applications .................................................................... 17 Document Number: 002-03288 Rev. *J Electrical Specifications ................................................ 23 Absolute Maximum Ratings ....................................... 23 Device-Level Specifications ...................................... 24 Digital Peripherals ..................................................... 26 System Resources .................................................... 28 Ordering Information ...................................................... 34 Ordering Code Definitions ......................................... 34 Packaging ........................................................................ 35 Acronyms ........................................................................ 38 Document Conventions ................................................. 39 Units of Measure ....................................................... 39 References and Links to Applications Collaterals ..... 40 Document History Page ................................................. 41 Sales, Solutions, and Legal Information ...................... 45 Worldwide Sales and Design Support ....................... 45 Products .................................................................... 45 PSoC® Solutions ...................................................... 45 Cypress Developer Community ................................. 45 Technical Support ..................................................... 45 Page 3 of 45 EZ-PD™ CCG3 EZ-PD CCG3 Block Diagram Figure 1. EZ-PD CCG3 Block Diagram[1] CPU Subsystem FLASH 2x64 KB SRAM 8 KB ROM 8 KB FAST MUL NVIC, IRQMX Read Accelerator SRAM Controller ROM Controller System Resources Lite Power Modes Active/Sleep Deep Sleep High Speed I/O Matrix ADC / ACA CHG DET Pads, ESD USB-FS CC BB PHY 2 X VCONN FET OCP 2 X GATE DRIVER USB-PD SS 2 x 2 ANALOG XBAR Test DFT Logic DFT Analog Peripheral Interconnect (MMIO) PCLK OVP Reset Reset Control XRES Peripherals 4 x TCPWM Clock Clock Control WDT IMO ILO System Interconnect (Single Layer AHB) IOSS GPIO (3 x ports) Power Sleep Control WIC POR REF PWRSYS HV REG AHB-Lite SPCIF CRYPTO 32-bit SWD/TC Cortex M0 48 MHz 4 x SCB CCG3 FS-PHY 22 x GPIOs, 2 x OVTs I/O Subsystem Note 1. See Acronyms section for more details. Document Number: 002-03288 Rev. *J Page 4 of 45 EZ-PD™ CCG3 Functional Overview CPU and Memory Subsystem USB-PD Subsystem (USBPD SS) CPU The USB-PD subsystem contains all of the blocks related to USB Type-C and Power Delivery. The subsystem consists of the following: The Cortex-M0 CPU in EZ-PD CCG3 is part of the 32-bit MCU subsystem, which is optimized for low-power operation with extensive clock gating. It mostly uses 16-bit instructions and executes a subset of the Thumb-2 instruction set. This enables fully compatible binary upward migration of the code to higher performance processors such as the Cortex-M3 and M4, thus enabling upward compatibility. The Cypress implementation includes a hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt controller (NVIC) block with 32 interrupt inputs and also includes a Wakeup Interrupt Controller (WIC). The WIC can wake the processor up from the Deep Sleep mode, allowing power to be switched off to the main processor when the chip is in the Deep Sleep mode. The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI) input, which is made available to the user when it is not in use for system functions requested by the user. The CPU also includes a serial wire debug (SWD) interface, which is a two-wire form of JTAG. The debug configuration used for EZ-PD CCG3 has four break-point (address) comparators and two watchpoint (data) comparators. Flash The EZ-PD CCG3 device has a flash module with two banks of 64 KB flash, a flash accelerator, tightly coupled to the CPU to improve average access times from the flash block. The flash block is designed to deliver 1 wait-state (WS) access time at 48 MHz and with 0-WS access time at 24 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average. Part of the flash module can be used to emulate EEPROM operation if required. SROM A supervisory ROM that contains boot and configuration routines is provided. Crypto Block CCG3 integrates a crypto block for hardware assisted authentication of firmware images. It also supports field upgradeability of firmware in a trusted ecosystem. The CCG3 Crypto block provides cryptography functionality. It includes hardware acceleration blocks for Advanced Encryption Standard (AES) block cipher, Secure Hash Algorithm (SHA-1 and SHA-2), Cyclic Redundancy Check (CRC), and pseudo random number generation. Integrated Billboard Device CCG3 integrates a complete full speed USB 2.0 device controller capable of functioning as a Billboard class device. The USB 2.0 device controller can also support other device classes. Document Number: 002-03288 Rev. *J ■ Biphase Marked Coding (BMC) PHY: USB-PD Transceiver with Fast Role Swap (FRS) transmit and detect ■ VCONN power FETs for the CC lines ■ VCONN RA Termination and Leakers ■ Analog Crossbar to switch between the SBU1/SBU2 and AUX_P/AUX_N pins ■ Programmable pull-up and pull-down termination on the AUX_P/AUX_N pins ■ Hot Plug Detect (HPD) processor ■ VBUS_C regulator (20V LDO) ■ Power switch between VSYS supply and VBUS_C regulator output ■ VBUS_C overvoltage (OV) and undervoltage (UV) detectors ■ Current sense amplifier (CSA) for overcurrent detection ■ Gate Drivers for VBUS_P and VBUS_C external Power FETs ■ VBUS_C discharge switch ■ USB2.0 Full-Speed (FS) PHY with integrated 5.0 V to 3.3 V regulator ■ Charger Detection/Emulation for USB BC1.2 and other proprietary protocols ■ Two instances of 8-bit SAR ADCs ■ 8-kV IEC ESD Protection on the following pins: VBUS_C, CC1, CC2, SBU1, SBU2, DP, DM The EZ-PD CCG3 USB-PD subsystem interfaces to the pins of a USB Type-C connector. It includes a USB Type-C baseband transceiver and physical-layer logic. This transceiver performs the BMC and the 4b/5b encoding and decoding functions as well as integrating the 1.2-V analog front end (AFE). This subsystem integrates the required terminations to identify the role of the CCG3 device, including RP and RD for UFP/DFP roles and RA for EMCA/VCONN powered accessories. The programmable VCONN leakers are included to discharge VCONN capacitance during a disconnect event. It also integrates power FETs for supplying VCONN power to the CC1/CC2 pins from the V5V pin. The analog crossbar enables connecting either of the SBU1/SBU2 pins to either of the AUX_P/AUX_N pins to support DisplayPort sideband signaling. The integrated HPD processor can be used to control or monitor the HPD signal of a DisplayPort source or sink. Page 5 of 45 EZ-PD™ CCG3 The Overvoltage/Undervoltage (OV/UV) block monitors the VBUS_C supply for programmable overvoltage and undervoltage conditions. The CSA amplifies the voltage across an external sense resistor, which is proportional to the current being drawn from the external DC-DC VBUS supply converter. The CSA output can either be measured with an ADC or configured to detect an overcurrent condition. The VBUS_P and VBUS_C gate drivers control the gates of external power FETs for the VBUS_C and VBUS_P supplies. The gate drivers can be configured to support both P and N type external power FETs. The gate drivers are configured by default for nFET devices. In applications using pFETs, the gate drivers must be appropriately configured. The OV/UV and CSA blocks can generate interrupts to automatically turn off the power FETs for the programmed overvoltage and overcurrent conditions. The VBUS_C discharge switch allows for discharging the VBUS_C line through an external resistor. The USB-PD subsystem also contains two 8-bit Successive Approximation Register (SAR) ADCs for analog to digital conversions. The voltage reference for the ADCs is generated from the VDDD supply. Each ADC includes an 8-bit DAC and a comparator. The DAC output forms the positive input of the comparator. The negative input of the comparator is from a 4-input multiplexer. The four inputs of the multiplexer are a pair of global analog multiplex busses, an internal bandgap voltage and an internal voltage proportional to the absolute temperature. Each GPIO pin can be connected to the global Analog Multiplex Busses through a switch, which allows either ADC to sample the pin voltage. When sensing the GPIO pin voltage with an ADC, the pin voltage cannot exceed the VDDIO supply value. Figure 2. USB-PD Subsystem CONSUMER N/PFETs charger PRODUCER N/PFETs dc-dc VBUS_P OC VBUS_P_CTRL Gate Driver CSA VBUS_C_CTRL Gate Driver VBUS_DISCHARGE VDDD VSYS POWER SWITCH RA VBUS_C OV/UV VCONN SWITCH Leaker CC1 V5V CC2 PROGRAMMABLE PULL-UP, PULL-DOWN BMC PHY w/ FRS AUX_P SBU1 ANALOG CROSS-BAR AUX_N HPD SBU2 USB Type-C Port VCONN LDO DP HPD 2x ADCs USB 2.0 FS PHY CHARGER DETECT DM USB PD SubSystem Full-Speed USB Subsystem The FSUSB subsystem contains a full-speed USB device controller as described in the Integrated Billboard Device section. Peripherals Serial Communication Blocks (SCB) EZ-PD CCG3 has four SCBs, which can be configured to implement an I2C, SPI, or UART interface. The hardware I2C blocks implement full multi-master and slave interfaces capable of multimaster arbitration. In the SPI mode, the SCB blocks can be configured to act as master or slave. In the I2C mode, the SCB blocks are capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and have flexible buffering options to reduce interrupt overhead and latency for the CPU. These blocks also support I2C that creates a mailbox address range in the memory of EZ-PD CCG3 and effectively reduce I2C communication to reading from and writing to an array in memory. In addition, the blocks support 8-deep FIFOs for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduce the need for clock stretching caused by the CPU not having read data on time. The I2C peripherals are compatible with the I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/Os are implemented with GPIO in open-drain modes. Document Number: 002-03288 Rev. *J Page 6 of 45 EZ-PD™ CCG3 The I2C port on SCB 1-3 blocks of EZ-PD CCG3 are not completely compliant with the I2C specification in the following aspects: ■ The GPIO cells for SCB 1's I2C port are not overvoltage-tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the I2C system. ■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a VOL maximum of 0.6 V. ■ Fast-mode and Fast-mode Plus specify minimum Fall times, which are not met with the GPIO cell; Slow strong mode can help meet this spec depending on the bus load. Timer/Counter/PWM Block (TCPWM) EZ-PD CCG3 has four TCPWM blocks. Each implements a 16-bit timer, counter, pulse-width modulator (PWM), and quadrature decoder functionality. GPIO EZ-PD CCG3 has up to 20 GPIOs (these GPIOs can be configured for GPIOs, SCB, SBU, and Aux signals) and SWD pins, which can also be used as GPIOs. The I2C pins from SCB 0 are overvoltage-tolerant. The GPIO block implements the following: ■ Seven drive strength modes: ❐ Input only ❐ Weak pull-up with strong pull-down ❐ Strong pull-up with weak pull-down ❐ Open drain with strong pull-down ❐ Open drain with strong pull-up ❐ Strong pull-up with strong pull-down ❐ Weak pull-up with weak pull-down ■ Input threshold select (CMOS or LVTTL) ■ Individual control of input and output buffer enabling/disabling in addition to the drive strength modes ■ Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode) ■ Selectable slew rates for dV/dt related noise control to improve EMI During power-on and reset, the I/O pins are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Document Number: 002-03288 Rev. *J Page 7 of 45 EZ-PD™ CCG3 Power Systems Overview Figure 3 shows an overview of the CCG3 power system requirement. CCG3 shall be able to operate from two possible external supply sources VBUS (4.0 V–21.5 V) or VSYS (2.7 V– 5.5 V). The VBUS supply is regulated inside the chip with a low-dropout regulator (LDO) down to 3.3-V level. The chip’s internal VDDD rail is intelligently switched between the output of the VBUS regulator and unregulated VSYS. The switched supply, VDDD is either used directly inside some analog blocks or further regulated down to VCCD which powers majority of the core using regulators. Besides Reset mode, CCG3 has three different power modes: Active, Sleep and Deep Sleep, transitions between which are managed by the Power System. A separate power domain VDDIO is provided for the GPIOs. The VDDD and VCCD pins, both the output of regulators are brought out for connecting a 1-µF capacitor for the regulator stability only. These pins are not supported as power supplies. When CCG3 is powered from VSYS that is greater than 3.3 V, the dedicated USB regulator allows USB operation. Figure 3. EZ-PD CCG3 Power System Block Diagram VSYS 1uF Switch VBUS LDO VBUS_P OC VBUS_P_CTRL VCONN VBUS_DISCHARGE OVP OCP RA VDDIO VSS VBUS_C_CTRL USB Regulator Regulator GPIO Gate Driver VDDD Gate Driver VCCD 1uF 1uF Core FS-USB TX/RX CC Tx/Rx 1uF DP, DM CC1, CC2 VSS CCG3 Table 1. CCG3 Power Modes Mode Description RESET Power is Valid and XRES is not asserted. An internal reset source is asserted or SleepController is sequencing the system out of reset. ACTIVE Power is Valid and CPU is executing instructions. SLEEP Power is Valid and CPU is not executing instructions. All logic that is not operating is clock gated to save power. DEEP SLEEP Main regulator and most hard-IP are shut off. Deep Sleep regulator powers logic, but only low-frequency clock is available. Document Number: 002-03288 Rev. *J Page 8 of 45 EZ-PD™ CCG3 Pinouts Table 2. CCG3 Pin Description for 42-CSP, 32-QFN, and 40-QFN Devices Pin Map 42-CSP Pin Map 32-QFN Pin Map 40-QFN Name A5 1 1 VBUS_P_CTRL1 VBUS Gate Driver Control 1 for Producer Switch A6 1 2 VBUS_P_CTRL0 VBUS Gate Driver Control 0 for Producer Switch B6 2 3 CC2 USB PD connector detect/Configuration Channel 2 C5 N/A N/A CC2 USB PD connector detect/Configuration Channel 2 D4 3 4 V5V Input Supply Voltage for VCONN FETs V5V = 5.0V – 5.5V to supply VCONN > 4.75V @ 1.5W V5V = 3.5V – 5.5V to supply VCONN > 3.00V @ 1W C6 4 5 CC1 USB PD connector detect/Configuration Channel 1 D6 N/A N/A CC1 USB PD connector detect/Configuration Channel 1 E6 N/A 6 VCONN F6 5 7 P1.0 D5 N/A 8 P1.1 GPIO/UART_2_RX / SPI_2_SEL Description VCONN Input - provides RA termination for cable applications GPIO/UART_2_TX / SPI_2_MISO E5 6 9 P1.2 GPIO/UART_0_RX/ UART_3_CTS/ SPI_3_MOSI/ I2C_3_SCL G6 7 10 P1.3 GPIO/UART_0_TX/ UART_3_RTS/ SPI_3_CLK/ I2C_3_SDA E4 N/A 11 AUX_P / P1.6 DisplayPort AUX_P signal / GPIO / UART_1_TX / SPI_1_MISO F5 8 12 SBU1 / P1.4 USB Type-C SBU1 signal / GPIO / UART_3_TX/ SPI_3_MISO/ SWD_1_CLK G5 9 13 SBU2 / P1.5 USB Type-C SBU2 signal / GPIO / UART_3_RX/ SPI_3_SEL/ SWD_1_DAT G4 N/A 14 AUX_N / P1.7 DisplayPort AUX_N signal / GPIO / UART_1_RX / SPI_1_SEL F4 10 15 P2.0 GPIO / UART_1_CTS / SPI_1_CLK/ I2C_1_SCL / SWD_0_DAT G3 11 16 P2.1 GPIO / UART_1_RTS / SPI_1_MOSI/ I2C_1_SDA / SWD_0_CLK G2 13 17 VDDD VDDD supply Input / Output (2.7 V–5.5 V) F3 14 18 VDDIO 1.71 V–5.5 V supply for I/Os. This supply also powers the global analog multiplex buses. F2 15 19 VCCD 1.8-V regulator output for filter capacitor G1 16 20 VSYS System power supply (2.7 V–5.5 V) F1 17 21 DPLUS USB 2.0 DP USB 2.0 DM E1 18 22 DMINUS E2 19 23 P2.4 GPIO D3 20 24 P2.5 GPIO / UART_0_TX/ SPI_0_MOSI D2 N/A 25 P2.6 GPIO / UART_0_RX/ SPI_0_CLK D1 21 26 XRES C3 22 27 Document Number: 002-03288 Rev. *J P0.0 External Reset Input. Internally pulled-up to VDDIO. I2C_0_SDA / GPIO_OVT / UART_0_CTS / SPI_0_SEL/ TCPWM0 Page 9 of 45 EZ-PD™ CCG3 Table 2. CCG3 Pin Description for 42-CSP, 32-QFN, and 40-QFN Devices (continued) Pin Map 42-CSP Pin Map 32-QFN Pin Map 40-QFN Name C2 23 28 P0.1 C1 24 29 VBUS_C_CTRL1 C4 24 30 VBUS_C_CTRL0 B1 25 31 VBUS A1 26 32 12, 27 33 VSS EPAD EPAD VSS A2 28 34 P3.2 B2 N/A 35 P3.3 E3 Description I2C_0_SCL / GPIO_OVT / UART_0_RTS / SPI_0_MISO/ TCPWM1 VBUS Gate Driver Control 1 for Consumer Switch VBUS Gate Driver Control 0 for Consumer Switch VBUS Input VBUS_DISCHARGE VBUS Discharge Control output Ground Supply (GND) GPIO / TCPWM0 GPIO / TCPWM1 B3 29 36 P3.4 GPIO / UART_2_CTS / SPI_2_MOSI/ I2C_2_SDA / TCPWM2 A3 30 37 P3.5 GPIO / UART_2_RTS / SPI_2_CLK/ I2C_2_SCL / TCPWM3 B4 N/A 38 P3.6 GPIO A4 31 39 OC Overcurrent sensor input B5 32 40 VBUS_P Document Number: 002-03288 Rev. *J VBUS producer input Page 10 of 45 EZ-PD™ CCG3 GPIO GPIO GPIO GPIO GND VBUS_DISCHARGE 35 34 33 32 31 VBUS GPIO EPAD 14 15 16 17 18 19 20 AUX_N GPIO GPIO VDDD VDDIO VCCD 30 VBUS_C_CTRL0 29 28 27 26 VBUS_C_CTRL1 GPIO_OVT GPIO_OVT XRES 25 24 23 22 21 GPIO GPIO GPIO DMINUS DPLUS VSYS 12 13 SBU2 11 SBU1 8 9 10 AUX_P GPIO GPIO GPIO 37 36 6 7 OC VCONN GPIO 38 2 3 4 5 VBUS_P 1 VBUS_P_CTRL0 CC2 V5V CC1 39 VBUS_P_CTRL1 40 Figure 4. Pinout of 40-QFN Package (Top View) Document Number: 002-03288 Rev. *J VBUS_P OC GPIO GPIO GPIO VSS VBUS_DISCHARGE VBUS 31 30 29 28 27 26 25 6 7 8 24 23 22 VBUS_C_CTRL GPIO_OVT GPIO_OVT 21 20 19 18 XRES GPIO 12 13 14 15 16 VDDD VDDIO VCCD VSYS VSS 11 10 17 GPIO GPIO SBU1 EPAD 9 GPIO GPIO GPIO 1 2 3 4 5 SBU2 VBUS_P_CTRL CC2 V5V CC1 32 Figure 5. Pinout of 32-QFN Package (Top View) GPIO DMINUS DPLUS Page 11 of 45 EZ-PD™ CCG3 Figure 6. Pinout of 42-WLCSP Bottom (Balls Up) View 6 5 VBUS_P_CT VBUS_P_CT RL0 RL1 4 3 2 1 OC GPIO P3.5 GPIO P3.2 VBUS_DISC HARGE A CC2 VBUS_P GPIO P3.6 GPIO P3.4 GPIO P3.3 VBUS B CC1 CC2 VBUS_C_CT RL0 GPIO_OVT P0.0 GPIO_OVT P0.1 VBUS_C_CT RL1 C CC1 GPIO P1.1 V5V GPIO P2.5 GPIO P2.6 XRES D VCONN GPIO P1.2 AUX_P VSS GPIO P2.4 DMINUS E GPIO P1.0 SBU1 GPIO P2.0 VDDIO VCCD DPLUS F GPIO P1.3 SBU2 AUX_N GPIO P2.1 VDDD VSYS G Document Number: 002-03288 Rev. *J Page 12 of 45 EZ-PD™ CCG3 Available Firmware and Software Tools EZ-PD Configuration Utility The EZ-PD Configuration Utility is a GUI-based Microsoft Windows application developed by Cypress to guide a CCGx user through the process of configuring and programming the chip. The utility allows users to: 1. Select and configure the parameters they want to modify 2. Program the resulting configuration onto the target CCGx device. The utility works with the Cypress supplied CCG1, CCG2, CCG3, and CCG4 kits, which host the CCGx controllers along with a USB interface. This version of the EZ-PD Configuration Utility supports configuration and firmware update operations on CCGx controllers implementing EMCA and Display Dongle applications. Support for other applications, such as Power Adapters and Notebook port controllers, will be provided in later versions of the utility. You can download the EZ-PD Configuration Utility and its associated documentation at the following link: http://www.cypress.com/documentation/software-and-drivers/ez-pd-configuration-utility Document Number: 002-03288 Rev. *J Page 13 of 45 EZ-PD™ CCG3 CCG3 Programming and Bootloading There are two ways to program application firmware into a CCG3 device: 1. Programming the device flash over SWD Interface 2. Application firmware update over specific interfaces (CC, USB, I2C) Generally, the CCG3 devices are programmed over SWD interface only during development or during the manufacturing process of the end product. Once the end product is manufactured, the CCG3 device's application firmware can be updated via the appropriate bootloader interface. Programming the Device Flash over SWD Interface The CCG3 family of devices can be programmed using the SWD interface. Cypress provides a programming kit (CY8CKIT-002 MiniProg3 Kit) called MiniProg3 which can be used to program the flash as well as debug firmware. The flash is programmed by downloading the information from a hex file. This hex file is a binary file generated as an output of building the firmware project in PSoC Creator Software. Click here for more information on how to use the MiniProg3 programmer. There are many third-party programmers that support mass programming in a manufacturing environment. As shown in the block diagram in Figure 7, the SWD_0_DAT and SWD_0_CLK pins are connected to the host programmer's SWDIO (data) and SWDCLK (clock) pins respectively. During SWD programming, the device can be powered by the host programmer by connecting its VTARG (power supply to the target device) to VSYS pin of CCG3 device. If the CCG3 device is powered using an on-board power supply, it can be programmed using the “Reset Programming” option. For more details, refer to the CYPD3XXX Programming Specifications. The CYPD3105 device for Thunderbolt cable applications is pre-programmed with a micro-bootloader that allows users to program the flash using the alternate SWD pins (SBU1 for SWD_1_CLK and SBU2 for SWD_1_DAT) that can be connected to the SBU interface of a Type-C connector. Note that this interface can be used to program the flash only once. Subsequent re-programming of this device can be done through the primary SWD interface (SWD_0_CLK and SWD_0_DAT pins). Irrespective of which SWD interface is used for programming the device, once the device is programmed with the hex file provided by Cypress for thunderbolt cable application, subsequent updates to the application firmware can be done over the CC line. Refer to Application Firmware Update over Specific Interfaces (I2C, CC, USB) for more details. Figure 7. Connecting the Programmer to CYPD3xxx Device 3.0 V VDD Host Programmer CYPD3xxx VCCD VDD VSYS SWDCLK SWD_0_CLK SWDIO SWD_0_DAT XRES 1F 10V X7R VDDD XRES GND VSS VDDIO 1F 10V X7R GND Application Firmware Update over Specific Interfaces (I2C, CC, USB) The application firmware can be updated over three different interfaces depending on the default firmware programmed into the CCG3 device. Refer to Table 38 for more details on default firmware that various part numbers of the CCG3 family of devices are pre-programmed with (note that some of the devices have bootloader only and some have bootloader plus application firmware). The application firmware provided by Cypress for all CCG3 applications have dual images. This allows fail-safe update of the alternate image while executing from the current image. For more information, refer to the EZ-PD Configuration Utility User Manual. Document Number: 002-03288 Rev. *J Application Firmware Update over I2C Interface This method primarily applies to CYPD3122, CYPD3125, and CYPD3126 devices of the CCG3 family. In these applications, the CCG3 device interfaces to an on-board application processor or an embedded controller over I2C interface. Refer to Figure 8 for more details. Cypress provides pseudo-code for the host processor for updating the CCG3 device firmware. Page 14 of 45 EZ-PD™ CCG3 Figure 8. Application Firmware Update over I2C Interface VDDD 2.2K 2.2K 2.2K I2C_SDA I2C_SCL Embedded Controller/ Application Processor I2C_INT CYPD3xxx Device To be Programmed Application Firmware Update over CC Line This method primarily applies to the CYPD3135 device of the CCG3 family. In these applications, the CY4531 CCG3 EVK can be used to send programming and configuration data as Cypress specific Vendor Defined Messages (VDMs) over the CC line. The CY4531 CCG3 EVK is connected to the system containing the CCG3 device on one end and a Windows PC running the EZ-PDTM Configuration Utility as shown in Figure 9 on the other end to program the CCG3 device. Figure 9. Application Firmware Update over CC Line USB Serial Device of CCG3 Daughter Card PC Running EZ-PD Configuration Utility USB Mini-B cable I2C CC Line CCG3 Device on CCG3 Daughter Card Mini-B Receptacle CY4531 CCG3 EVK Application Firmware Update over USB This method primarily applies to the CYPD3120 and CYPD3121 devices of the CCG3 family. In these applications, the firmware update can be performed over the D+/D- lines (USB2.0) using various possible options as shown in Figure 10. Option 1 is to have a Windows PC running EZ-PD Configuration Utility connected to the device to be programmed via the CY4531 CCG3 EVK. This setup can be avoided using option 2, where the Document Number: 002-03288 Rev. *J CYPD3135 device to be Programmed Type-C Receptacle user has a Type-A to Type-C cable. This option requires that the system contain the CCG3 device to be programmed to have a Type-C receptacle. The other option (Option 3) is to have a Windows PC with a native Type-C connector as shown in Figure 10. Page 15 of 45 EZ-PD™ CCG3 Figure 10. Application Firmware Update over USB Option 1 PC Running EZ-PD Configuration Utility USB Type-A to Type-B cable Type-B Receptacle D+/D- CY4531 CCG3 EVK CYPD 312x device to be Programmed Type-C Receptacle OR Option 2 USB Type-A to Type-C cable PC Running EZ-PD Configuration Utility CYPD 312x device to be Programmed OR Option 3 Windows PC with Native Type-C Connector Running EZ-PD Configuration Utility CYPD 312x device to be Programmed Type-C Receptacle Document Number: 002-03288 Rev. *J Type-C plug Page 16 of 45 EZ-PD™ CCG3 Applications Figure 11 illustrates the application diagram of a power adapter using a CCG3 device. In this application, CCG3 is used as DFP (power provider) only. The maximum power profile that can be supported by power adapters is up to 20 V, 100 W using 40-pin QFN CCG3 devices. CCG3 has the ability to drive both types of FETs and the state of GPIO P1.0 (floating or grounded) indicates the type of FET (N-MOS or P-MOS FET) being used in the power provider path. The power provider FETs are controlled by high-voltage gate driver outputs (VBUS_P_CTRL0 and VBUS_P_CTRL1 pins of CCG3 device). The CCG3 device is also capable of supporting proprietary charging protocols over the DP and DM lines of the Type-C receptacle. By providing a 5-V source at the V5V pin of the CCG3 device, the device becomes capable of delivering the VCONN supply over either the CC1 or CC2 pins of the Type-C connector. CCG3 integrates all termination resistors and uses GPIOs (VSEL0 and VSEL1) to indicate the negotiated power profile. If required, the power profile can also be selected using CCG3 serial interfaces (I2C, SPI) or PWM. The VBUS voltage on the Type-C port is monitored using internal circuits to detect undervoltage and overvoltage conditions. To ensure quick discharge of VBUS when the power adapter cable is detached, a discharge path is provided with a resistor connected to the VBUS_DISCHARGE pin of the CCG3 device. The CCG3 family's power adapter parts are shipped with bootloader and application firmware with limited functionality. Its purpose is to facilitate application flashing over CC line using the EZ-PD Configuration Utility. The power adapter requires an explicit power contract to be negotiated prior to enabling the EZ-PD Configuration utility to flash the application firmware. This application firmware, based on the state of the GPIO (P1.0), determines the type of provider load switch (NFET/PFET) and supplies the 5-V VBUS over Type-C. Overcurrent protection is enabled by sensing the current through the 10-m sense resistor using the “OC” and “VBUS_P” pins of the CCG3 device. The VBUS provider through the Type-C connector can be turned on or off using the provider path FETs. Figure 11. Power Adapter Application Diagram (40-QFN Device) DC/DC OR AC-DC Secondary (5-20V) VBUS_OC VBUS_IN D 10 m 1% VBUS_OUT DMN3018SSD-13 DMN3018SSD-13 S S VBUS D G G 10M 10F 50V 10M VSEL1 VSEL2 100 2 39 28 27 40 31 1F 50V X7R 33 X 20 17 18 1F 10V X7R X X X 11 14 6 OC VSEL2/P0.0 VBUS_P_CTRL0 VBUS_P_CTRL1 VSEL1/P0.1 VBUS_DISCHARGE CC1 VBUS VBUS_C_CTRL1 GND CYPD3135-40LQXIT 40QFN VBUS_C_CTRL0 VSYS VDDD V5V VDDIO P2.4 AUX_P DPLUS AUX_N DMINUS VCONN GPIO XRES VCCD 26 19 1.3F 10V X7R Document Number: 002-03288 Rev. *J 32 CC2 3 VBUS_P 0.1F 1 SBU1 SBU2 P1.0 13 X 7 X 12 X CC2 5 29 CC1 X 30 X 4 5V VBUS_OUT 390pF 5% X7R 390pF 5% X7R Type-C Receptacle 100K 23 21 10K 22 8, 9, 10, 15, 16, 24, 25, 34, 35, 36, 37, 38 P1.0 indicates FET type in design. Floating condition indicates NFETs and connected to GND indicates PFETs in provider path. GND Page 17 of 45 EZ-PD™ CCG3 The CCG3 device negotiates power contracts between the power bank and the sink/source device connected to the Type-C receptacle. The CCG3 device also controls and drives the provider and consumer path FETs and can monitor overcurrent and overvoltage conditions on the Type-C VBUS line. Figure 12 illustrates a power bank application diagram using a CCG3 device. In this application, the Type-C receptacle is used for providing as well as consuming power. The consumer path will be active when the battery is charged using a Type-C power source that is connected to the Type-C receptacle in Figure 12. The provider path will be active when the power bank is used for providing power to a sink device connected to the Type-C receptacle. Additionally, a Type-A receptacle can also be provided for providing power to the sinks that have a legacy USB interface. Figure 12. Power Bank Application Diagram (40-QFN Device) Consumer Path D 10M S D DMN3018SSD-13 D 1F 35V X7R 7, 8, 15, 16, 23, 24, 25, 27, 28, 38 17 0.1F 10V 0.1F 10V 1F 10V 18 10F 50V 10M 1 2 VBUS_P_CTRL0 VBUS_P_CTRL1 4 V5V X 31 VBUS 40 VBUS_P 20 1F 10V D G 10M 39 VBATT 10M CCG3 gate driver control configuration needs to be appropriately set, based on the VBUS FET type (nFET/pFET). DMN3018SSD-13 S S G OC VBUS G VBUS Provider Path 10 m 1% 0.1F 10V S G Power Subsystem + Battery 0.1F 10V DMN3018SSD-13 DMN3018SSD-13 VBUS_C_CTRL1 29 VBUS VSYS VBUS_C_CTRL0 GPIO VBUS_DISCHARGE VDDD VDDIO CYPD3121-40LQXIT 40QFN CC1 DPLUS 13 GPIO/SBU2 X 37 I2C_SCL/GPIO 36 I2C_SDA/GPIO 34 GPIO DMINUS VCCD 35 19 32 CC2 5 6 CC1 AUX_N/GPIO 14 X X 26 33 0.1F 10V X7R 1uF 10V X7R Document Number: 002-03288 Rev. *J Discrete Ckts to support Legacy Charge Source SS DP DN GND From Power Subsystem CCG3 GPIO Type-C Receptacle 390pF 5% X7R 22 11 X GND I2C_ I2C_ SCL/GPIO SDA/GPIO 9 10 390pF 5% X7R X 21 AUX_P/GPIO XRES GPIO 30 CC2 3 VCONN 12 GPIO/SBU1 X 100 VBUS Type-A Receptacle DP DN GND Page 18 of 45 EZ-PD™ CCG3 Figure 13 illustrates a USB Type-C to DisplayPort (4-lane) adapter application, which enables connectivity between a PC that supports a Type-C port with DisplayPort Alternate Mode support and a legacy monitor that has a DisplayPort interface. The application meets the requirements described in Section 4.2 of the VESA DisplayPort Alt Mode on USB Type-C Standard Version 1.0 (Scenarios 2a and 2b USB Type-C to DisplayPort Cables). Figure 13. USB Type-C to DisplayPort Adapter Application Diagram 4 31 VCONN 0.1F 10V 1F 10V 1F 10V 40 20 7, 8, 15, 16, 24, 25, 27, 28, 38 0.1F 10V 1F 10V mDP/ DP V5V VBUS_C_CTRL1 18 37 34 11 14 35 29 VBUS VBUS_P VCONN VBUS_C_CTRL0 VDDD VDDIO CYPD3120-40LQXIT 40QFN CC1 DPLUS I2C_INT / P3.2 DMINUS AUX_P SBU1 AUX_N SBU2 HOTPLUG_DET / P3.3 P2.4 VCCD 23 19 X P2.4 indicates type of end application. Floating condition indicates usage for Type-C to DP application and connected to GND indicates usage for Type-C to HDMI adapter application. 30 VCONN 0.1F 10V 32 CC2 3 I2C_SCL / P3.5 I2C_SDA / P3.4 VBUS 6 VSYS VBUS_DISCHARGE 36 HotPlug Detect VBUS_P_CTRL0 VBUS_P_CTRL1 GPIO 17 1F 10V 1 2 39 OC XRES MUX_I2C_ MUX_I2C_ GND SCL/P1.2 SDA/P1.3 9 10 5 CC 390pF 5% 21 X7R Type-C Plug DP 22 DN 12 SBU1 13 SBU2 26 33 SS 0.1F 10V X7R GND 1F 10V X7R Display Port Data Lanes Document Number: 002-03288 Rev. *J Page 19 of 45 EZ-PD™ CCG3 Figure 14 illustrates a USB Type-C to HDMI adapter application, which enables connectivity between a PC that supports a Type-C port with DisplayPort Alternate Mode support and a legacy monitor that has HDMI interface. It enables users of any Notebook that implements USB-Type C to connect to other display types. This application meets the requirements described in Section 4.3 of the VESA DisplayPort Alt Mode on USB Type-C Standard Version 1.0. This application supports display output at a resolution of up to 4K Ultra HD (3840x2160) at 60 Hz. Figure 14. USB Type-C to HDMI Adapter Application 1.2V VBUS 5V 3.3V Regulator VCONN Power OR BuckBoost 5V BuckBoost not needed for DVI/VGA 4 31 VCONN 0.1uF 10V 1uF 10V 40 1uF 10V 20 7, 8, 15, 16, 24, 25, 27, 28, 38 VBUS_P_CTRL0 VBUS_P_CTRL1 VBUS_C_CTRL1 V5V P2.4 VBUS VBUS_P VCONN VBUS_C_CTRL0 GPIO VBUS_DISCHARGE 18 17 1uF 10V 0.1uF 10V 1uF 10V 37 36 34 11 14 VDDIO VDDD CYPD3120-40LQXIT 40QFN 3.3V 23 CC1 I2C_SCL / P3.5 I2C_SDA / P3.4 DPLUS I2C_INT / P3.2 P2.4 indicates type of end application. Floating condition indicates usage for Type-C to DP application and connected to GND indicates usage for Type-C to HDMI adapter application. 6 30 VBUS VCONN 0.1uF 10V 32 CC2 3 DMINUS AUX_P SBU1 AUX_N SBU2 XRES AUX_P/N 29 VSYS 3.3V HDMI/ DVI/ VGA 1 2 39 OC MUX_I2C_ MUX_I2C_ GND 35 HOTPLUG_ DET / P3.3 VCCD SCL/P1.2 SDA/P1.3 19 10 9 1uF HotPlug 10V Detect X7R 5 CC Type-C Plug 390pF 5% 21 X7R DP 22 DN 12 SBU1 13 SBU2 26 33 SS 0.1uF 10V X7R GND 1.2V DP to HDMI/ DVI/VGA Convertor Document Number: 002-03288 Rev. *J Display Port Data Lanes Page 20 of 45 EZ-PD™ CCG3 Figure 15 illustrates a Notebook DRP application diagram using a CCG3 device. The Type-C port can be used as a power provider or a power consumer. The CCG3 device communicates with the embedded controller (EC) over I2C. It also controls the Data Mux to route the HighSpeed signals either to the USB chipset (during normal mode) or the DisplayPort Chipset (during Alternate Mode). The SBU, SuperSpeed, and HighSpeed lines are routed directly from the Display Mux of the notebook to the Type-C receptacle. Figure 15. DRP Application Diagram VINT20 DMN3018SSD-13 DMN3018SSD-13 Charger D S S D G 10M G 10M VBUS VBUS_SUPPLY DMN3018SSD-13 DC/DC 1uF 35V X7R 10 m 1% V3P3 and V5P0 are 3.3V and 5V supplies coming from the motherboard. V5P0 VBUS 4 31 40 V3P3 20 0.1uF 10V 0.1uF 10V 1uF 10V 7, 8, 15, 16, 23, 24, 25, 27, 28, 38 VDDD 0.1uF 10V 0.1uF 10V 17 18 1uF 10V X 2.2K 2.2K X 12 13 37 36 Embedded Controller USB Chipset DisplayPort Chipset D 34 D+/HPD SS 10uF 50V G 10M 10M 1 OC VBUS_P_CTRL0 VBUS_P_CTRL1 V5V VBUS_C_CTRL1 29 VBUS VBUS_P VBUS VSYS VBUS_C_CTRL0 GPIO VBUS_DISCHARGE VDDD VDDIO CYPD3125-40LQXIT 40QFN SBU1 CC1 DPLUS SBU2 DMINUS I2C_SCL / P3.5 AUX_P I2C_SDA / P3.4 AUX_N I2C_INT / P3.2 XRES HOTPLUG_ MUX_I2C_ MUX_I2C_ GND DET / P3.3 VCCD SCL/P1.2 SDA/P1.3 35 19 9 10 1uF 10V X7R HPD SCL SDA 100 30 32 CC2 3 VCONN VDDD 2.2K S S G 2 39 CCG3 gate driver control configuration needs to be appropriately set, based on the VBUS FET type (nFET/pFET). D DMN3018SSD-13 CC2 5 6 CC1 390pF 5% X7R X 21 390pF 5% X7R Type-C Receptacle 22 11 14 X X 26 33 0.1uF 10V X7R D+/- SS DP/DN GND HS/SS/ DP/SBU Lines SS DP0/1/2/3 AUX+/- Document Number: 002-03288 Rev. *J Data Mux Page 21 of 45 EZ-PD™ CCG3 Figure 16 illustrates a CCG3 device based Charge-through Dongle application block diagram. This Charge-through dongle application also implements Cypress’s USB SuperSpeed Hub controller HX3 (CYUSB3304-68LTXI) available in 68-QFN package, Low-power single chip USB 3.0 to Gigabit Ethernet Bridge Controller GX3 (CYUSB3610-68LTXC) available in 68-QFN package and the CCG2 (CYPD2122-24LQXI) which acts as an Upstream Facing Port (UFP) and sinks power when connected to USB Type-C chargers. This application enables connectivity between a USB Type-C Notebook and HDMI Display, legacy USB device and Gigabit Ethernet while also connecting a USB Type-C charging cable. The Charge-Through Dongle solution allows simultaneous HDMI display, Superspeed data transfers, Ethernet connection and charging of a USB Type-C Notebook. Charge-Through Dongle is also widely known as Multiport Adapter. More details including the schematic of the CCG3 device based Charge-through Dongle reference design can be found here. Figure 16. Charge-through Dongle Application Block Diagram (40-QFN Device) VBUS_C VBUS_N VCONN_N Power 5.0V 3.3V 1.2V 3.3V 2x lane DP 4 1.2V 5V DP to HDMI Protocol Convertor MegaChips MCDP2900 HDMI Receptacle To Display VBUS_A SS/HS lines DS1 Cypress HX3 DS2 CYUSB304CYUSB3304 HS lines 68-QFN 4 SS lines 8 DS3 3.3V 1.2V To Notebook VBUS_N VCONN_N Legacy USB devices 5V Cypress GX3 CYUSB3610 68-QFN Type-C plug USB3.1 Type-A Receptacle Ethernet Port HS lines VBUS_C CC CCG3 DRP CYPD3123 40-QFN Document Number: 002-03288 Rev. *J I2C CCG2 UFP CC CYPD2122 24-QFN Type-C receptacle for Charging From DFP Charger Page 22 of 45 EZ-PD™ CCG3 Electrical Specifications Absolute Maximum Ratings Table 3. Absolute Maximum Ratings Parameter Description Min Typ Max Units VSYS_MAX Digital supply relative to VSS –0.5 – 6 V V5V Max supply voltage relative to VSS – – 6 V VBUS_MAX_ON Max supply voltage relative to VSS, VBUS regulator enabled – – 26 V Max supply voltage relative to VSS, VBUS regulator enabled 100% of the time – – 24.5 V Max supply voltage relative to VSS, VBUS regulator enabled 25% of the time – – 26 V VDDIO_MAX Max supply voltage relative to VSS – – 6 V VGPIO_ABS GPIO voltage VBUS_MAX_OFF –0.5 – VDDIO + 0.5 V VGPIO_OVT_ABS OVT GPIO voltage –0.5 – 6 V IGPIO_ABS Maximum current per GPIO –25 – 25 mA VCONN_MAX Max voltage relative to VSS – – 6 V VCC_ABS Max voltage on CC1 and CC2 pins – – 6 V –0.5 – 0.5 mA GPIO injection current, Max for VIH > IGPIO_INJECTION VDDD, and Min for VIL < VSS Details/Conditions Absolute max Absolute max, current injected per pin ESD_HBM Electrostatic discharge human body model 2200 – – V – ESD_CDM Electrostatic discharge charged device model 500 – – V – LU Pin current for latch-up –100 – 100 mA ESD_IEC_CON Electrostatic discharge IEC61000-4-2 8000 – – V Contact discharge on CC1, CC2, VBUS, DPLUS, DMINUS, SBU1 and SBU2 pins ESD_IEC_AIR – – V Air discharge for CC1, CC2, VBUS, DPLUS, DMINUS, SBU1 and SBU2 pins Electrostatic discharge IEC61000-4-2 15000 Document Number: 002-03288 Rev. *J Tested at 125 °C Page 23 of 45 EZ-PD™ CCG3 Device-Level Specifications All specifications are valid for –40 °C  TA  105 °C and TJ  120 °C, except where noted. Table 4. DC Specifications Spec ID Parameter SID.PWR#1 VSYS SID.PWR#1_A VSYS Description Min Typ Max Units – 2.7 – 5.5 V UFP Mode. – DFP/DRP or Gate Driver Modes SID.PWR#23 VCONN Power Supply Input Voltage SID.PWR#13 VDDIO IO Supply Voltage SID.PWR24 VCCD Output Voltage for core Logic SID.PWR#4 IDD Supply current SID.PWR#1_B VSYS SID.PWR#1_C Details/Conditions 3 – 5.5 V 2.7 – 5.5 V 1.71 – 5.5[2] V – 1.8 – V – From VSYS or VBUS VBUS = 5V, TA = 25 °C / VSYS = 5 V, TA = 25 °C FS USB, CC IO in Tx or Rx, no I/O sourcing current, 2 SCBs at 1 Mbps, CPU at 24 MHz. – 2.7V < VDDD < 5.5 V – 25 – mA Power supply for USB operation 4.5 – 5.5 V USB configured, USB Regulator enabled VSYS Power supply for USB operation 3.15 – 3.45 V USB configured, USB Regulator disabled SID.PWR#1_D VSYS Power supply for charger detect/emulation operation 3.15 – 5.5 V –40 °C to +85 °C TA SID.PWR#27 VBUS Power supply input voltage 3.5 – 21.5 V FS USB disabled. Total current consumption from VBUS VDDD, GPIO P2.4 cannot be used. It must be left unconnected. See Table 2 for pin numbers. Document Number: 002-03288 Rev. *J Page 24 of 45 EZ-PD™ CCG3 Table 5. AC Specifications (Guaranteed by Characterization) Spec ID SID.CLK#4 Parameter FCPU Description Min CPU input frequency Typ Max Units DC – 48 Details/Conditions MHz All VDDD SID.PWR#20 TSLEEP Wakeup from sleep mode – 0 – µs – SID.PWR#21 TDEEPSLEEP Wakeup from Deep Sleep mode – – 35 µs – SID.XRES#5 TXRES External reset pulse width 5 – – µs SYS.FES#1 Power-up to “Ready to accept I2C/CC command” – 5 25 ms T_PWR_RDY All VDDIO – I/O Table 6. I/O DC Specifications Spec ID Parameter Description Min Typ Max Units Details/Conditions SID.GIO#37 VIH_CMOS Input voltage HIGH threshold 0.7 × VDDIO – – V CMOS input SID.GIO#38 VIL_CMOS Input voltage LOW threshold – – 0.3 × VDDIO V CMOS input SID.GIO#39 VIH_VDDIO2.7- LVTTL input, VDDIO < 2.7 V 0.7× VDDIO – – V – SID.GIO#40 VIL_VDDIO2.7- LVTTL input, VDDIO < 2.7 V – – 0.3 × VDDIO V – SID.GIO#41 VIH_VDDIO2.7+ LVTTL input, VDDIO  2.7 V 2.0 – – V – SID.GIO#42 VIL_VDDIO2.7+ LVTTL input, VDDIO  2.7 V – – 0.8 V – SID.GIO#33 VOH_3V Output voltage HIGH level VDDIO –0.6 – – V IOH = 4 mA at 3V VDDIO SID.GIO#34 VOH_1.8V Output voltage HIGH level VDDIO –0.5 – – V IOH = 1 mA at 1.8V VDDIO SID.GIO#35 VOL_1.8V Output voltage LOW level – – 0.6 V IOL = 4 mA at 1.8V VDDIO SID.GIO#36 VOL_3V Output voltage LOW level – – 0.6 V IOL = 4 mA at 3V VDDIO for SBU and AUX pins SID.GIO#5 RPU Pull-up resistor value 3.5 5.6 8.5 k +25 °C TA, all VDDIO SID.GIO#6 RPD Pull-down resistor value 3.5 5.6 8.5 k +25 °C TA, all VDDIO SID.GIO#16 IIL Input leakage current (absolute value) – – 2 nA +25 °C TA, all VDDIO. Guaranteed by characterization. Max pin capacitance – 3.0 7 pF All VDDIO, all packages, all I/Os except SBU and AUX. Guaranteed by characterization. SID.GIO#17A CPIN_SBU Max pin capacitance – 16 18 pF All VDDIO, all packages, SBU pins only. Guaranteed by characterization. SID.GIO#17B CPIN_AUX Max pin capacitance – 12 14 pF All VDDIO, all packages, AUX pins only. Guaranteed by characterization. SID.GIO#43 VHYSTTL Input hysteresis, LVTTL VDDIO  2.7 V 15 40 – mV Guaranteed by characterization SID.GIO#44 VHYSCMOS Input hysteresis CMOS 0.05 × VDDIO – – mV VDDIO < 4.5 V. Guaranteed by characterization. SID69 IDIODE Current through protection diode to VDDIO/Vss – – 100 µA Guaranteed by characterization SID.GIO#45 ITOT_GPIO Maximum total sink chip current – – 85 mA Guaranteed by characterization SID.GIO#17 CPIN Document Number: 002-03288 Rev. *J Page 25 of 45 EZ-PD™ CCG3 Table 6. I/O DC Specifications (continued) Spec ID Parameter Description Min Typ Max Units – – 10.00 µA Details/Conditions OVT SID.GIO#46 Input current when Pad > VDDIO for OVT inputs IIHS Per I2C specification Table 7. I/O AC Specifications (Guaranteed by Characterization) Spec ID Parameter Description Min Typ Max Units Details/Conditions SID70 TRISEF Rise time in Fast Strong mode 2 – 12 ns 3.3 V VDDIO, Cload = 25 pF SID71 TFALLF Fall time in Fast Strong mode 2 – 12 ns 3.3 V VDDIO, Cload = 25 pF XRES Table 8. XRES DC Specifications Spec ID Parameter SID.XRES#1 VIH_XRES SID.XRES#2 VIL_XRES SID.XRES#3 CIN_XRES SID.XRES#4 VHYSXRES Description Input voltage HIGH threshold on XRES pin Input voltage LOW threshold on XRES pin Input capacitance on XRES pin Input voltage hysteresis on XRES pin Min Typ Max Units Details/Conditions 0.7 × VDDIO – – V CMOS input – – 0.3 × VDDIO V CMOS input – – 7 pF – 0.05 × VDDIO – mV Guaranteed by characterization Guaranteed by characterization Digital Peripherals The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode. Pulse Width Modulation (PWM) for GPIO Pins Table 9. PWM AC Specifications (Guaranteed by Characterization) Spec ID Parameter Description SID.TCPWM.3 TCPWMFREQ Operating frequency SID.TCPWM.4 TPWMENEXT Input trigger pulse width SID.TCPWM.5 TPWMEXT Min Typ Max Units – – Fc MHz 2/Fc – – ns Output trigger pulse width 2/Fc – – ns SID.TCPWM.5A TCRES Resolution of counter 1/Fc – – ns SID.TCPWM.5B PWMRES PWM resolution 1/Fc – – ns SID.TCPWM.5C QRES Quadrature inputs resolution 1/Fc – – ns Document Number: 002-03288 Rev. *J Details/Conditions Fc max = CLK_SYS. Maximum = 48 MHz. For all trigger events Minimum possible width of Overflow, Underflow, and CC (Counter equals Compare value) outputs Minimum time between successive counts Minimum pulse width of PWM output Minimum pulse width between quadrature-phase inputs Page 26 of 45 EZ-PD™ CCG3 I2C Table 10. Fixed I2C DC Specifications (Guaranteed by Characterization) Description Min Typ Max Units Details/Conditions SID149 Spec ID II2C1 Parameter Block current consumption at 100 kHz – – 60 µA – SID150 II2C2 Block current consumption at 400 kHz – – 185 µA – SID151 II2C3 Block current consumption at 1 Mbps – – 390 µA – SID152 II2C4 I2C enabled in Deep Sleep mode – – 1.4 µA – Min Typ Max Units Details/Conditions – – 1 Mbps – Min Typ Max Units Details/Conditions Table 11. Fixed I2C AC Specifications (Guaranteed by Characterization) Spec ID SID153 Parameter FI2C1 Description Bit rate Table 12. Fixed UART DC Specifications (Guaranteed by Characterization) Spec ID Parameter Description SID160 IUART1 Block current consumption at 100 Kb/s – – 125 µA – SID161 IUART2 Block current consumption at 1000 Kb/s – – 312 µA – Description Min Typ Max Units Details/Conditions Bit rate – – 1 Mbps – Table 13. Fixed UART AC Specifications (Guaranteed by Characterization) Spec ID SID162 Parameter FUART Table 14. Fixed SPI DC Specifications (Guaranteed by Characterization) Min Typ Max Units Details/Conditions SID163 Spec ID ISPI1 Parameter Block current consumption at 1 Mb/s Description – – 360 µA – SID164 ISPI2 Block current consumption at 4 Mb/s – – 560 µA – SID165 ISPI3 Block current consumption at 8 Mb/s – – 600 µA – Table 15. Fixed SPI AC Specifications (Guaranteed by Characterization) Spec ID Description Min Typ Max Units Details/Conditions SPI Operating frequency (Master; 6X oversampling) – – 8 MHz – Description Min Typ Max Units Details/Conditions TDMO MOSI Valid after SClock driving edge – – 15 ns SID168 TDSI MISO Valid before SClock capturing edge 20 – – ns Full clock, late MISO sampling SID169 THMO Previous MOSI data hold time 0 – – ns Referred to slave capturing edge SID166 Parameter FSPI Table 16. Fixed SPI Master Mode AC Specifications (Guaranteed by Characterization) Spec ID SID167 Parameter Document Number: 002-03288 Rev. *J – Page 27 of 45 EZ-PD™ CCG3 Table 17. Fixed SPI Slave Mode AC Specifications (Guaranteed by Characterization) Spec ID Parameter Description Min Typ Max Units Details/Conditions 40 – – ns – SID170 TDMI MOSI Valid before Sclock capturing edge SID171 TDSO MISO Valid after Sclock driving edge – – 42 + 3 × TCPU ns SID171A TDSO_EXT MISO Valid after Sclock driving edge in Ext Clk mode – – 48 ns – SID172 THSO Previous MISO data hold time 0 – – ns – SID172A TSSELSCK SSEL Valid to first SCK Valid edge 100 – – ns – TCPU = 1/FCPU System Resources Power-on-Reset (POR) with Brown Out SWD Interface Table 18. Imprecise Power On Reset (PRES) (Guaranteed by Characterization) Spec ID Parameter Description Min Typ Max Units Details/Conditions SID185 VRISEIPOR Power-on Reset (POR) rising trip voltage 0.80 – 1.50 V – SID186 VFALLIPOR POR falling trip voltage 0.70 – 1.4 V – Table 19. Precise Power On Reset (POR) (Guaranteed by Characterization) Spec ID Parameter Description Min Typ Max Units Details/Conditions 1.48 – 1.62 V – 1.1 – 1.5 V – Min Typ SID190 VFALLPPOR Brown-out Detect (BOD) trip voltage in active/sleep modes SID192 VFALLDPSLP BOD trip voltage in Deep Sleep mode Table 20. SWD Interface Specifications Spec ID Parameter Description Max Units Details/Conditions SID.SWD#1 F_SWDCLK1 3.3 V  VDDIO  5.5 V – – 14 SWDCLK 1/3 CPU clock MHz frequency SID.SWD#2 F_SWDCLK2 1.8 V  VDDIO  3.3 V – – 7 MHz SID.SWD#3 T_SWDI_SETUP T = 1/f SWDCLK 0.25 × T – – ns Guaranteed by characterization SID.SWD#4 T_SWDI_HOLD 0.25 × T – – ns Guaranteed by characterization SID.SWD#5 T_SWDO_VALID T = 1/f SWDCLK – – 0.50 × T ns Guaranteed by characterization SID.SWD#6 T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns Guaranteed by characterization T = 1/f SWDCLK Document Number: 002-03288 Rev. *J SWDCLK 1/3 CPU clock frequency Page 28 of 45 EZ-PD™ CCG3 Internal Main Oscillator Table 21. IMO DC Specifications (Guaranteed by Design) Spec ID SID218 Parameter IIMO1 Description IMO operating current at 48 MHz Min Typ Max Units Details/Conditions – – 1000 µA – Min Typ Max Units Details/Conditions Table 22. IMO AC Specifications Spec ID Parameter Description SID.CLK#13 FIMOTOL Frequency variation at 24, 36, and 48 MHz (trimmed) – – ±2 % –25 °C TA 85 °C, all VDDD SID226 TSTARTIMO IMO start-up time – – 7 µs Guaranteed by characterization SID229 TJITRMSIMO2 RMS jitter at 24 MHz – 145 – ps Guaranteed by characterization SID.CLK#1 FIMO IMO frequency 24 – 48 MHz All VDDD Internal Low-Speed OscillatorPower Down Table 23. ILO DC Specifications (Guaranteed by Design) Min Typ Max Units Details/Conditions SID231 Spec ID IILO1 Parameter ILO operating current Description – 0.3 1.05 µA – SID233 IILOLEAK ILO leakage current – 2 15 nA – Min Typ Max Units Details/Conditions Table 24. ILO AC Specifications Spec ID Parameter Description SID234 TSTARTILO1 ILO start-up time – – 2 ms Guaranteed by characterization SID238 TILODUTY ILO duty cycle 40 50 60 % Guaranteed by characterization SID.CLK#5 FILO ILO frequency 20 40 80 kHz – Description Min Typ Max Units Details/Conditions RP_std DFP CC termination for default USB Power 64 80 96 µA – Table 25. PD DC Specifications Spec ID SID.PD.1 Parameter SID.PD.2 RP_1.5A DFP CC termination for 1.5A power 166 180 194.4 µA – SID.PD.3 RP_3.0A DFP CC termination for 3.0A power 304 330 356.4 µA – SID.PD.4 RD UFP CC termination 4.59 5.1 5.61 kΩ – SID.PD.5 RD_DB UFP Dead Battery CC termination on CC1 and CC2, valid for 1.5A and 3.0A RP termination values 4.08 5.1 6.12 kΩ UFP Dead Battery CC termination on CC1 and CC2. For Default RP termination, the voltage on CC1 and CC2 is guaranteed to be
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