CYRF69213
Programmable Radio on Chip Low Power
PRoC™ LP Features
■
USB 2.0-USB-IF certified (TID # 40000552)
■
Single Device, Two Functions
❐ 8-bit, Flash based USB peripheral MCU function and 2.4 GHz
radio transceiver function in a single device
■
Flash Based Microcontroller Function
❐ M8C based 8-bit CPU, optimized for Human Interface Devices (HID) applications
❐ 256 bytes of SRAM
❐ 8 Kbytes of Flash memory with EEPROM emulation
❐ In-System reprogrammable through D+/D– pins
❐ 16-bit free running timer
❐ Low power wake up timer
❐ 12-bit Programmable Interval Timer with interrupts
❐ Watchdog timer
■
Industry-Leading 2.4 GHz Radio Transceiver Function
❐ Operates in the unlicensed worldwide Industrial, Scientific
and Medical (ISM) band (2.4 GHz to 2.483 GHz)
❐ DSSS data rates of up to 250 Kbps
❐ GFSK data rate of 1 Mbps
❐ –97 dBm receive sensitivity
❐ Programmable output power of up to +4 dBm
❐ Auto Transaction Sequencer (ATS)
❐ Framing CRC and Auto ACK
❐ Received Signal Strength Indication (RSSI)
❐ Automatic Gain Control (AGC)
■
Component Reduction
❐ Integrated 3.3V regulator
❐ Integrated pull up on D–
❐ GPIOs that require no external components
❐ Operates off a single crystal
■
Flexible I/O
❐ 2 mA source current on all GPIO pins. Configurable 8 mA or
50 mA/pin current sink on designated pins
❐ Each GPIO pin supports high impedance inputs, configurable
pull up, open-drain output, CMOS/TTL inputs and CMOS output
❐ Maskable interrupts on all I/O pins
■
USB Specification Compliance
❐ Conforms to USB Specification Version 2.0
❐ Conforms to USB HID Specification Version 1.1
❐ Supports one Low Speed USB device address
❐ Supports one control endpoint and two data end points
❐ Integrated USB Transceiver
■
Operating Voltage from 4.0V to 5.5V DC
■
Operating Temperature from 0 to 70°C
■
Pb-Free 40-Pin QFN Package
■
Advanced Development Tools Based on Cypress’s PSoC®
Tools
Block Diagram
1ohm
VIO
VCC3
VCC2
VReg
VCC1
VBat0
VBat1
VBat2
470 nF
RST
P1.2 / VReg
nSS
MOSI
1-2 uF
VDD_MICRO
4.7uF
SCK
V bus
R F bias
RFp
RFn
4
R adio
F unction
IR Q /G P IO
P 1.5/M O S I
P 1_6:7
2
M IS O /G P IO
P 1.4 /S C K
P 2_0:1
X O U T /G P IO
P 1.3/nS S
2
P A C T L /G P IO
12 M H z
Cypress Semiconductor Corporation
Document #: 001-07552 Rev. *D
•
198 Champion Court
•
.....
GND
GND
Xtal
GND
RESV
D + /D 2
.......
VSS
P 0_1,3,4,7
M icrocontro ller
F unction
470 nF
San Jose, CA 95134-1709
•
408-943-2600
Revised February 13, 2009
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CYRF69213
Applications
The CYRF69213 PRoC LP Low Speed is targeted for the
following applications:
■
■
USB Bridge for Human Interface Devices (HID)
❐ Wireless mice
❐ Wireless keyboards
❐ Remote controls
❐ Gaming applications
USB Bridge for General Purpose Applications
❐ Consumer electronics
❐ Industrial applications
❐ White goods
❐ Home automation
❐ Personal health
Functional Description
PRoC LP devices are integrated radio and microcontroller
functions in the same package to provide a dual role single-chip
solution.
Communication between the microcontroller and the radio is via
the SPI interface between both functions.
Functional Overview
The CYRF69213 is a complete Radio System-on-Chip device,
providing a complete RF system solution with a single device and
a few discrete components. The CYRF69213 is designed to
implement low cost wireless systems operating in the worldwide
2.4 GHz Industrial, Scientific, and Medical (ISM) frequency band
(2.400 GHz–2.4835 GHz).
2.4 GHz Radio Function
The radio meets the following world wide regulatory requirements:
■
Europe
❐ ETSI EN 301 489-1 V1.4.1
❐ ETSI EN 300 328-1 V1.3.1
■
North America
❐ FCC CFR 47 Part 15
■
Japan
❐ ARIB STD-T66
Document #: 001-07552 Rev. *D
Data Transmission Modes
The radio supports four different data transmission modes:
■
In GFSK mode, data is transmitted at 1 Mbps without any DSSS
■
In 8DR mode, 1 byte is encoded in each PN code symbol transmitted
■
In DDR mode, 2 bits are encoded in each PN code symbol
transmitted
■
In SDR mode, a single bit is encoded in each PN code symbol
transmitted
Both 64-chip and 32-chip data PN codes are supported. The four
data transmission modes apply to the data after the Start of
Packet (SOP). In particular, the packet length, data and CRC are
all sent in the same mode.
USB Microcontroller Function
The microcontroller function is based on the powerful
CYRF69213 microcontroller. It is an 8-bit Flash programmable
microcontroller with integrated low speed USB interface.
The microcontroller has up to 14 GPIO pins to support USB,
PS/2 and other applications. Each GPIO port supports high
impedance inputs, configurable pull up, open drain output,
CMOS/TTL inputs and CMOS output. Up to two pins support
programmable drive strength of up to 50 mA. Additionally each
I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with
the exception of GPIO Port 0.
The microcontroller features an internal oscillator. With the
presence of USB traffic, the internal oscillator can be set to
precisely tune to USB timing requirements (24 MHz ± 1.5%).
The PRoC LP has up to 8 Kbytes of Flash for user’s firmware
code and up to 256 bytes of RAM for stack space and user
variables.
The PRoC LP includes a Watchdog timer, a vectored interrupt
controller, a 12-bit programmable interval timer with configurable
1 ms interrupt and a 16-bit free running timer with capture
registers.
Page 2 of 77
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CYRF69213
Pinout
Figure 1. Pin Diagram: 40-Pin QFN 7 × 7 mm LF48A
P1.6 32
PACTL / GPIO 31
VIO 33
4
RST 34
P0.3
36
3
P1.7 35
2
V CC
L/D 37
XTAL
VDD_1.8
1
P0.7 38
P0.4
VBAT0 39
VREG 40
Corner
tabs
CYRF69213
WirelessUSB LP
30
XOUT / GPIO
29
MISO / GPIO
28
P1.5 / MOSI
27
IRQ / GPIO
P0.1
5
26
P1.4 / SCK
V BAT1
6
25
P1.3 / SS
V CC
7
24
P1.2 / V REG_MICRO
P2.1
8
23
V DD_Micro
V BAT2
9
RF BIAS
10
22
D-
21
D+
* E-PAD Bottom Side
20 NC
19 RESV
18 NC
17 NC
16 VCC
15 P2.0
14 NC
13 RFN
12 GND
11 RFP
Pin Configuration
Pin
Name
1
P0.4
2
Xtal_in
Function
Individually configured GPIO
12 MHz Crystal. External clock in
3, 7, 16
VCC
Connected to pin 24 via 0.047 μF capacitor
4
P0.3
Individually configured GPIO
5
P0.1
Individually configured GPIO
6, 9, 39
Vbat
Connected to pin 24 via 0.047 μFshunt capacitor
8
P2.1
10
RF Bias
GPIO. Port 2 Bit 1
RF pin voltage reference
11
RFp
Differential RF input to/from antenna
12
GND
Ground
13
RFn
Differential RF to/from antenna
14, 17, 18, 20, 36
NC
15
P2.0
19
RESV
21
D+
Low speed USB I/O
22
D–
Low speed USB I/O
23
VDD_micro
24
P1.2 / VREG
GPIO. Port 2 Bit 0
Reserved. Must connect to GND
4.0–5.5 for 12 MHz CPU/4.75–5.5 for 24 MHz CPU
Must be configured as 3.3V output. It must have a 1–2 μF output capacitor
25
P1.3 / nSS
Slave select SPI Pin
26
P1.4 / SCK
Serial Clock Pin from MCU function to radio function
27
IRQ
28
P1.5 / MOSI
Document #: 001-07552 Rev. *D
Interrupt output, configure high/low or GPIO
Master Out Slave In
Page 3 of 77
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CYRF69213
Pin Configuration (continued)
Pin
Name
Function
29
MISO
Master In Slave Out, from radio function. Can be configured as GPIO
30
XOUT
Bufferd CLK, PACTL_n or GPIO
31
PACTL
32
P1.6
Control for external PA or GPIO
GPIO. Port 1 Bit 6
I/O interface voltage. Connected to pin 24 via 0.047 μF
33
VIO
34
Reset
Radio Reset. Connected to VDD via 0.47 μF capacitor or to microcontroller GPIO pin. Must have
a RESET = HIGH event the very first time power is applied to the radio otherwise the state of
the radio function control registers is unknown
35
P1.7
GPIO. Port 1 Bit 7
36
VDD_1.8
Regulated logic bypass. Connected via 0.47 μF to GND
37
L/D
Connected to GND
38
P0.7
GPIO. Port 0 Bit 7
Connected to pin 24
40
Vreg
41
E-pad
Must be connected to GND
42
Corner Tabs
Do not connect corner tabs
PRoC LP Functional Overview
The SoC is designed to implement wireless device links
operating in the worldwide 2.4 GHz ISM frequency band. It is
intended for systems compliant with worldwide regulations
covered by ETSI EN 301 489-1 V1.41, ETSI EN 300 328-1
V1.3.1 (Europe), FCC CFR 47 Part 15 (USA and Industry
Canada) and TELEC ARIB_T66_March, 2003 (Japan).
The SoC contains a 2.4 GHz 1 Mbps GFSK radio transceiver,
packet data buffering, packet framer, DSSS baseband controller,
Received Signal Strength Indication (RSSI), and SPI interface
for data transfer and device configuration.
The radio supports 98 discrete 1 MHz channels (regulations may
limit the use of some of these channels in certain jurisdictions).
In
DSSS
modes
the
baseband
performs
DSSS
spreading/despreading, while in GFSK Mode (1 Mb/s - GFSK)
the baseband performs Start of Frame (SOF), End of Frame
(EOF) detection and CRC16 generation and checking. The
baseband may also be configured to automatically transmit
Acknowledge (ACK) handshake packets whenever a valid
packet is received.
Document #: 001-07552 Rev. *D
When in receive mode, with packet framing enabled, the device
is always ready to receive data transmitted at any of the
supported bit rates, except SDR, enabling the implementation of
mixed-rate systems in which different devices use different data
rates. This also enables the implementation of dynamic data rate
systems, which use high data rates at shorter distances and/or
in a low moderate interference environment, and change to lower
data rates at longer distances and/or in high interference
environments.
The MCU function is an 8-bit Flash programmable microcontroller with integrated low speed USB interface. The instruction
set has been optimized specifically for USB operations, although
it can be used for a variety of other embedded applications.
The MCU function has up to eight Kbytes of Flash for user’s code
and up to 256 bytes of RAM for stack space and user variables.
In addition, the MCU function includes a Watchdog timer, a
vectored interrupt controller, a 16-bit Free-Running Timer, and
12-bit Programmable Interrupt Timer.
The MCU function supports in-system programming by using the
D+ and D– pins as the serial programming mode interface. The
programming protocol is not USB.
Page 4 of 77
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CYRF69213
DDR MODE
Table 1. DDR Mode
REGISTER
VALUE
DESCRIPTION
TX_CFG_ADR
0X16
32 chip PN Code, DDR, PA = 6
RX_CFG_ADR
0X4B
AGC is enabled. LNA and attenuator are disabled. Fast turn around is disabled, the device
uses high side receive injection and Hi-Lo is disabled. Overwrite to receive buffer is enabled
and the RX buffer is configured to receive eight bytes maximum.
XACT_CFG_ADR
0X05
AutoACK is disabled. Forcing end state is disabled. The device is configured to transition to
Idle mode after a Receive or Transmit. ACK timeout is set to 128 µs.
FRAMING_CFG_AD
R
0X00
All SOP and framing features are disabled. Disable LEN_EN=0 if EOP is needed.
TX_OVERRIDE_AD
R
0X04
Disable Transmit CRC-16.
RX_OVERRIDE_AD
R
0X14
The receiver rejects packets with a zero seed. The Rx CRC-16 Checker is disabled and the
receiver accepts bad packets that do not match the seed in CRC_seed registers. Basically
this helps in communication with the first generation radio that does not have CRC capabilities.
ANALOG_CTRL_AD
R
0X01
Set ALL SLOW. When set, the synthesizer settle time for all channels is the same as the slow
channels in the first generation radio.
DATA32_THOLD_AD 0X03
R
Sets the number of allowed corrupted bits to 3.
EOP_CTRL_ADR
0x01
Sets the number of consecutive symbols for non correlation to detect end of packet.
PREAMBLE_ADR
0xAAAA05
AAAA are the two preamble bytes.Other Bytes can also be written into the preamble register
file. The number of preamble bytes to be sent should be >4.
SDR MODE
Table 2. SDR Mode
REGISTER
VALUE
DESCRIPTION
TX_CFG_ADR
0X3E
64 chip PN code, SDR mode, PA = 6.
RX_CFG_ADR
0X4B
AGC is enabled. LNA and attenuator are disabled. Fast turn around is disabled, the device
uses high side receive injection and Hi-Lo is disabled. Overwrite to receive buffer is enabled
and RX buffer is configured to receive eight bytes maximum. Enables RXOW to allow new
packets to be loaded into the receive buffer. This also enables the VALID bit which is used by
the first generation radio’s error correction firmware.
XACT_CFG_ADR
0X05
AutoACK is disabled. Forcing end state is disabled. The device is configured to transition to
Idle mode after Receive or Transmit. ACK timeout is set to 128 µs.
FRAMING_CFG_AD
R
0X00
All SOP and framing features are disabled. Disable LEN_EN=0 if EOP is needed.
TX_OVERRIDE_AD
R
0X04
Disable Transmit CRC-16.
RX_OVERRIDE_AD
R
0X14
The receiver rejects packets with a zero seed. The RX CRC-16 checker is disabled and the
receiver accepts bad packets that do not match the seed in the CRC_seed registers. Basically
this helps in communication with the first generation radio that does not have CRC capabilities.
ANALOG_CTRL_AD
R
0X01
Set ALL SLOW. When set, the synthesizer settle time for all channels is the same as the slow
channels in the first generation radio, for manual ACK consistency
DATA64_THOLD_AD 0X07
R
Sets the number of allowed corrupted bits to 7 which is close to the recommended 12% value.
EOP_CTRL_ADR
0xA1
Sets the number of consecutive symbols for non correlation to detect end of packet.
PREAMBLE_ADR
0xAAAA09
AAAA are the two preamble bytes. Any other byte can also be written into the preamble
register file. The number of preamble bytes to be sent should be >8.
Document #: 001-07552 Rev. *D
Page 5 of 77
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CYRF69213
Functional Block Overview
sent in the same mode. In general, lower data rates reduces
packet error rate in any given environment.
All the blocks that make up the PRoC LP are presented here.
By combining the DATA_CODE_ADR code lengths and data
transmission modes described above, the CYRF69213 IC
supports the following data rates:
2.4 GHz Radio
The radio transceiver is a dual conversion low IF architecture
optimized for power and range/robustness. The radio employs
channel-matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to +4 dBm transmit power, with an output power
control range of 34 dB in 7 steps. The supply current of the
device is reduced as the RF output power is reduced.
Table 3. Internal PA Output Power Step Table
PA Setting
Typical Output Power (dBm)
7
+4
6
0
5
–5
4
–10
3
–15
2
–20
1
–25
0
–30
Frequency Synthesizer
Before transmission or reception may commence, it is necessary
for the frequency synthesizer to settle. The settling time varies
depending on channel; 25 fast channels are provided with a
maximum settling time of 100 μs.
The ‘fast channels’ (
