CYRF6936B-40LTXC

CYRF6936 WirelessUSB™ LP 2.4 GHz Radio SoC Features ■ 2.4 GHz Direct Sequence Spread Spectrum (DSSS) radio transceiver ■ Battery Voltage Monitoring Circuitry ■ Supports coin-cell operated applications ■ Operating voltage from 1.8 V to 3.6 V ■ Operating temperature from 0 to 70°C ■ Space saving 40-pin QFN 6x6 mm package ■ Operates in the unlicensed worldwide Industrial, Scientific, and Medical (ISM) band (2.400 GHz to 2.483 GHz) ■ 21 mA operating current (Transmit at –5 dBm) ■ Transmit power up to +4 dBm ■ Receive sensitivity up to –97 dBm ■ Wireless Keyboards and Mice ■ Sleep Current less than 1 μA ■ Wireless Gamepads ■ DSSS data rates up to 250 kbps, GFSK data rate of 1 Mbps ■ Remote Controls ■ Low external component count ■ Toys ■ Auto Transaction Sequencer (ATS) - no MCU intervention ■ VOIP and Wireless Headsets ■ Framing, Length, CRC16, and Auto ACK ■ White Goods ■ Power Management Unit (PMU) for MCU/Sensor ■ Consumer Electronics ■ Fast Startup and Fast Channel Changes ■ Home Automation ■ Separate 16-byte Transmit and Receive FIFOs ■ Automatic Meter Readers ■ AutoRate™ - dynamic data rate reception ■ Personal Health and Entertainment ■ Receive Signal Strength Indication (RSSI) Applications Support ■ Serial Peripheral Interface (SPI) control while in sleep mode ■ 4 MHz SPI microcontroller interface Applications See www.cypress.com for development tools, reference designs, and application notes. Logic Block Diagram VBAT L/D VREG VDD VCC Power Management IRQ SS SCK MISO MOSI SPI Data Interface and Sequencer PACTL GFSK Modulator RFBIAS DSSS Baseband & Framer GFSK Demodulator RSSI Xtal Osc RFP RFN Synthesizer RST XTAL XOUT Cypress Semiconductor Corporation Document #: 38-16015 Rev. *J • GND 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 18, 2011 [+] Feedback CYRF6936 Contents Functional Description ..................................................... 3 Functional Overview ........................................................ 4 Data Transmission Modes ........................................... 4 Link Layer Modes ........................................................ 4 Packet Buffers ............................................................. 5 Auto Transaction Sequencer (ATS) ............................ 5 Data Rates .................................................................. 6 Functional Block Overview .............................................. 6 2.4 GHz Radio ............................................................. 6 Frequency Synthesizer ................................................ 6 Baseband and Framer ................................................. 6 Packet Buffers and Radio Configuration Registers ..... 6 SPI Interface ................................................................ 6 Interrupts ..................................................................... 8 Clocks .......................................................................... 8 Power Management .................................................... 8 Low Noise Amplifier and Received Signal Strength Indication ............................................ 8 Receive Spurious Response ....................................... 9 Document #: 38-16015 Rev. *J Application Examples ......................................................9 Registers .........................................................................14 Absolute Maximum Ratings ...........................................15 Operating Conditions .....................................................15 DC Characteristics ..........................................................15 AC Characteristics ..........................................................16 RF Characteristics ..........................................................17 Typical Operating Characteristics .................................19 Ordering Information ......................................................22 Ordering Code Definitions .........................................22 Package Description ......................................................23 Acronyms ........................................................................25 Document Conventions .................................................25 Units of Measure .......................................................25 Document History Page .................................................26 Sales, Solutions, and Legal Information ......................28 Worldwide Sales and Design Support .......................28 Products ....................................................................28 PSoC Solutions .........................................................28 Page 2 of 28 [+] Feedback CYRF6936 Functional Description The CYRF6936 WirelessUSB™ LP radio is a second generation member of the Cypress WirelessUSB Radio System-On-Chip (SoC) family. The CYRF6936 is interoperable with the first generation CYWUSB69xx devices. The CYRF6936 IC adds a range of enhanced features, including increased operating voltage range, reduced supply current in all operating modes, higher data rate options, reduced crystal start up, synthesizer settling, and link turnaround times. Figure 1. Pin Diagram - CYRF6936 40 QFN NC 32 NC 31 VI/O 33 RST 34 VDD 35 NC 36 L/D 37 VBAT0 38 NC 39 VREG 40 Corner tabs XTAL 1 30 PACTL / GPIO NC 2 29 XOUT / GPIO VCC 3 28 MISO / GPIO NC 4 NC 5 VBAT1 6 VCC 7 24 SS VBAT2 8 23 NC NC 9 27 MOSI / SDAT CYRF6936 WirelessUSB LP 40-Pin QFN 26 IRQ / GPIO 25 SCK 22 NC * E-PAD Bottom Side 21 NC RFBIAS 10 20 NC 19 RESV 18 NC 17 NC 16 VCC 15 NC 14 NC 13 RFN 12 GND 11 RFP Table 1. Pin Description Pin Number 1 Name XTAL Type Default I I Description 12 MHz crystal. 2, 4, 5, 9, 14, 15, 17, 18, NC 20, 21, 22, 23, 31, 32, 36, 39 NC Connect to GND. 3, 7, 16 VCC Pwr VCC = 2.4 V to 3.6 V. Typically connected to VREG. 6, 8, 38 VBAT(0-2) Pwr VBAT = 1.8 V to 3.6 V. Main supply. 10 RFBIAS O O RF I/O 1.8 V reference voltage. 11 RFP I/O I Differential RF signal to and from antenna. 12 GND GND 13 RFN I/O 19 RESV I 24 SS I I SPI enable, active LOW assertion. Enables and frames transfers. 25 SCK I I SPI clock. 26 IRQ I/O O Interrupt output (configurable active HIGH or LOW), or GPIO. 27 MOSI I/O I SPI data input pin (Master Out Slave In), or SDAT. 28 MISO I/O Z SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode). Tri-states when SPI 3PIN = 0 and SS is deasserted. 29 XOUT I/O O Buffered 0.75, 1.5, 3, 6, or 12 MHz clock, PACTL, or GPIO. Tri-states in sleep mode (configure as GPIO drive LOW). 30 PACTL I/O O Control signal for external PA, T/R switch, or GPIO. 33 VI/O Pwr Document #: 38-16015 Rev. *J Ground. I Differential RF signal to and from antenna. Must be connected to GND. I/O interface voltage, 1.8–3.6 V. Page 3 of 28 [+] Feedback CYRF6936 Table 1. Pin Description (continued) Pin Number Name Type Default Description I Device reset. Internal 10 kohm pull down resistor. Active HIGH, connect through a 0.47 μF capacitor to VBAT. Must have RST = 1 event the first time power is applied to the radio. Otherwise the state of the radio control registers is unknown. 34 RST I 35 VDD Pwr Decoupling pin for 1.8 V logic regulator, connect through a 0.47 μF capacitor to GND. 37 L/D O PMU inductor/diode connection, when used. If not used, connect to GND. 40 VREG Pwr PMU boosted output voltage feedback. E-PAD GND GND Must be soldered to Ground. Corner Tabs NC NC Do Not solder the tabs and keep other signal traces clear. All tabs are common to the lead frame or paddle which is grounded after the pad is grounded. While they are visible to the user, they do not extend to the bottom. Functional Overview The CYRF6936 IC provides a complete WirelessUSB SPI to antenna wireless MODEMs. The SoC is designed to implement wireless device links operating in the worldwide 2.4 GHz ISM frequency band. It is intended for systems compliant with worldwide regulations covered by ETSI EN 301 489-1 V1.41, ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15 (USA and Industry Canada), and TELEC ARIB_T66_March, 2003 (Japan). The SoC contains a 2.4 GHz, 1 Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), and SPI interface for data transfer and device configuration. The radio supports 98 discrete 1 MHz channels (regulations may limit the use of some of these channels in certain jurisdictions). The baseband performs DSSS spreading/despreading, Start of Packet (SOP), End of Packet (EOP) detection, and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge (ACK) handshake packets whenever a valid packet is received. When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates. This enables the implementation of mixed-rate systems in which different devices use different data rates. This also enables the implementation of dynamic data rate systems that use high data rates at shorter distances or in a low-moderate interference environment or both. It changes to lower data rates at longer distances or in high interference environments or both. In addition, the CYRF6936 IC has a Power Management Unit (PMU), which enables direct connection of the device to any battery voltage in the range 1.8 V to 3.6 V. The PMU conditions the battery voltage to provide the supply voltages required by the device, and may supply external devices. Document #: 38-16015 Rev. *J Data Transmission Modes The SoC supports four different data transmission modes: ■ In GFSK mode, data is transmitted at 1 Mbps, without any DSSS. ■ In 8DR mode, eight bits are encoded in each derived code symbol transmitted. ■ In DDR mode, two bits are encoded in each derived code symbol transmitted (As in the CYWUSB6934 DDR mode). ■ In SDR mode, one bit is encoded in each derived code symbol transmitted (As in the CYWUSB6934 standard modes). Both 64 chip and 32 chip Pseudo Noise (PN) codes are supported. The four data transmission modes apply to the data after the SOP. In particular the length, data, and CRC16 are all sent in the same mode. In general, lower data rates reduce packet error rate in any given environment. Link Layer Modes The CYRF6936 IC device supports the following data packet framing features: SOP Packets begin with a two-symbol SoP marker. This is required in GFSK and 8DR modes, but is optional in DDR mode and is not supported in SDR mode. If framing is disabled then an SOP event is inferred whenever two successive correlations are detected. The SOP_CODE_ADR code used for the SOP is different from that used for the “body” of the packet, and if desired may be a different length. SOP must be configured to be the same length on both sides of the link. Length There are two options for detecting the end of a packet. If SOP is enabled, then the length field must be enabled. GFSK and 8DR must enable the length field. This is the first eight bits after the SOP symbol, and is transmitted at the payload data rate. When the length field is enabled, an EoP condition is inferred after reception of the number of bytes defined in the length field, plus two bytes for the CRC16. The alternative to using the length Page 4 of 28 [+] Feedback CYRF6936 field is to infer an EOP condition from a configurable number of successive noncorrelations; this option is not available in GFSK mode and is only recommended when using SDR mode. CRC16 The device may be configured to append a 16 bit CRC16 to each packet. The CRC16 uses the USB CRC polynomial with the added programmability of the seed. If enabled, the receiver verifies the calculated CRC16 for the payload data against the received value in the CRC16 field. The seed value for the CRC16 calculation is configurable, and the CRC16 transmitted may be calculated using either the loaded seed value or a zero seed; the received data CRC16 is checked against both the configured and zero CRC16 seeds. CRC16 detects the following errors: ■ Any one bit in error. ■ Any two bits in error (irrespective of how far apart, which column, and so on). ■ Any odd number of bits in error (irrespective of the location). ■ An error burst as wide as the checksum itself. Figure 2 shows an example packet with SOP, CRC16, and lengths fields enabled, and Figure 3 shows a standard ACK packet. Figure 2. Example Packet Format 2 n d F ra m in g S y m b o l* P re a m b le n x 16us P SOP 1 SOP 2 L e n g th C R C 16 P a y lo a d D a ta Packet le n g th 1 B y te P e rio d 1 s t F ra m in g S y m b o l* *N o te :3 2 o r 6 4 u s Figure 3. Example ACK Packet Format P r e a m b le n x 16us P 2 n d F r a m in g S y m b o l* SO P 1 SO P 2 C RC 16 C R C fie ld fr o m r e c e iv e d p a c k e t. 2 B y te p e r io d s 1 s t F r a m in g S y m b o l* *N o te :3 2 o r 6 4 u s Packet Buffers Auto Transaction Sequencer (ATS) All data transmission and reception use the 16 byte packet buffers - one for transmission and one for reception. The CYRF6936 IC provides automated support for transmission and reception of acknowledged data packets. The transmit buffer allows loading a complete packet of up to 16 bytes of payload data in one burst SPI transaction. This is then transmitted with no further MCU intervention. Similarly, the receive buffer allows receiving an entire packet of payload data up to 16 bytes with no firmware intervention required until the packet reception is complete. When transmitting in transaction mode, the device automatically: The CYRF6936 IC supports packets up to 255 bytes. However, the actual maximum packet length depends on the accuracy of the clock on each end of the link and the data mode. Interrupts are provided to allow an MCU to use the transmit and receive buffers as FIFOs. When transmitting a packet longer than 16 bytes, the MCU can load 16 bytes initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. Similarly, when receiving packets longer than 16 bytes, the MCU must fetch received data from the FIFO periodically during packet reception to prevent it from overflowing. ■ starts the crystal and synthesizer ■ enters transmit mode ■ transmits the packet in the transmit buffer ■ transitions to receive mode and waits for an ACK packet ■ transitions to the transaction end state when an ACK packet is received or a timeout period expires Similarly, when receiving in transaction mode, the device automatically: ■ waits in receive mode for a valid packet to be received ■ transitions to transmit mode, transmits an ACK packet ■ transitions to the transaction end state (receive mode to await the next packet, and so on.) The contents of the packet buffers are not affected by the transmission or reception of ACK packets. Document #: 38-16015 Rev. *J Page 5 of 28 [+] Feedback CYRF6936 In each case, the entire packet transaction takes place without any need for MCU firmware action (as long as packets of 16 bytes or less are used). To transmit data, the MCU must load the data packet to be transmitted, set the length, and set the TX GO bit. Similarly, when receiving packets in transaction mode, firmware must retrieve the fully received packet in response to an interrupt request indicating reception of a packet. Data Rates The CYRF6936 IC supports the following data rates by combining the PN code lengths and data transmission modes described in the previous sections: ■ 1000 kbps (GFSK) ■ 250 kbps (32 chip 8DR) ■ 125 kbps (64 chip 8DR) ■ 62.5 kbps (32 chip DDR) ■ 31.25 kbps (64 chip DDR) ■ 15.625 kbps (64 chip SDR) 2.4 GHz Radio The radio transceiver is a dual conversion low IF architecture optimized for power, range, and robustness. The radio employs channel-matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides up to +4 dBm transmit power, with an output power control range of 34 dB in seven steps. The supply current of the device is reduced as the RF output power is reduced. Table 2. Internal PA Output Power Step Table Typical Output Power (dBm) +4 0 –5 –13 –18 –24 –30 –35 Frequency Synthesizer Before transmission or reception may begin, the frequency synthesizer must settle. The settling time varies depending on channel; 25 fast channels are provided with a maximum settling time of 100 μs. The ‘fast channels’ (less than 100 μs settling time) are every third channel, starting at 0 up to and including 72 (for example, 0, 3, 6, 9 …. 69, 72). Document #: 38-16015 Rev. *J The baseband and framer blocks provide the DSSS encoding and decoding, SOP generation and reception, CRC16 generation and checking, and EOP detection and length field. Packet Buffers and Radio Configuration Registers Packet data and configuration registers are accessed through the SPI interface. All configuration registers are directly addressed through the address field in the SPI packet (as in the CYWUSB6934). Configuration registers allow configuration of DSSS PN codes, data rate, operating mode, interrupt masks, interrupt status, and so on. SPI Interface Functional Block Overview PA Setting 7 6 5 4 3 2 1 0 Baseband and Framer The CYRF6936 IC has an SPI interface supporting communication between an application MCU and one or more slave devices (including the CYRF6936). The SPI interface supports single-byte and multi-byte serial transfers using either 4-pin or 3-pin interfacing. The SPI communications interface consists of Slave Select (SS), Serial Clock (SCK), Master Out-Slave In (MOSI), Master In-Slave Out (MISO), or Serial Data (SDAT). SPI communication may be described as the following: ■ Command Direction (bit 7) = ‘1’ enables SPI write transaction. A ‘0’ enables SPI read transactions. ■ Command Increment (bit 6) = ‘1’ enables SPI auto address increment. When set, the address field automatically increments at the end of each data byte in a burst access. Otherwise the same address is accessed. ■ Six bits of address ■ Eight bits of data The device receives SCK from an application MCU on the SCK pin. Data from the application MCU is shifted in on the MOSI pin. Data to the application MCU is shifted out on the MISO pin. The active LOW Slave Select (SS) pin must be asserted to initiate an SPI transfer. The application MCU can initiate SPI data transfers using a multi-byte transaction. The first byte is the Command/Address byte, and the following bytes are the data bytes shown in Table 3 through Figure 6 on page 7. The SPI communications interface has a burst mechanism, where the first byte can be followed by as many data bytes as required. A burst transaction is terminated by deasserting the slave select (SS = 1). The SPI communications interface single read and burst read sequences are shown in Figure 4 and Figure 5 on page 7, respectively. The SPI communications interface single write and burst write sequences are shown in Figure 6 and Figure 7 on page 7, respectively. This interface may be optionally operated in a 3-pin mode with the MISO and MOSI functions combined in a single bidirectional data pin (SDAT). When using 3-pin mode, user firmware must ensure that the MOSI pin on the MCU is in a high impedance state except when MOSI is actively transmitting data. Page 6 of 28 [+] Feedback CYRF6936 The device registers may be written to or read from one byte at a time, or several sequential register locations may be written or read in a single SPI transaction using incrementing burst mode. In addition to single byte configuration registers, the device includes register files. Register files are FIFOs written to and read from using nonincrementing burst SPI transactions. The SPI interface is not dependent on the internal 12 MHz clock. Registers may therefore be read from or written to when the device is in sleep mode, and the 12 MHz oscillator disabled. The SPI interface and the IRQ and RST pins have a separate voltage reference pin (VI/O). This enables the device to interface directly to MCUs operating at voltages below the CYRF6936 IC supply voltage. The IRQ pin function may be optionally multiplexed onto the MOSI pin. When this option is enabled, the IRQ function is not available while the SS pin is LOW. When using this configuration, user firmware must ensure that the MOSI pin on the MCU is in a high impedance state whenever the SS pin is HIGH. Table 3. SPI Transaction Format Parameter Bit # Bit Name Byte 1 7 DIR 6 INC Byte 1+N [7:0] Data [5:0] Address Figure 4. SPI Single Read Sequence SCK SS cmd MOSI DIR 0 INC addr A5 A4 A3 A2 A1 A0 data to mcu MISO D7 D6 D5 D4 D3 D2 D1 D0 Figure 5. SPI Incrementing Burst Read Sequence SCK SS cmd MOSI DIR 0 INC addr A5 A4 A3 A2 A1 A0 data to mcu1 MISO D7 D6 D5 D4 D3 data to mcu1+N D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 Figure 6. SPI Single Write Sequence SCK SS cmd MOSI DIR 1 INC addr A5 A4 A3 A2 data from mcu A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 MISO Figure 7. SPI Incrementing Burst Write Sequence SCK SS cmd MOSI DIR 1 INC addr A5 A4 A3 A2 data from mcu1 A1 A0 D7 D6 D5 D4 D3 D2 data from mcu1+N D1 D0 D7 D6 D5 D4 D3 D2 MISO Document #: 38-16015 Rev. *J Page 7 of 28 [+] Feedback CYRF6936 Interrupts The device provides an interrupt (IRQ) output, which is configurable to indicate the occurrence of various different events. The IRQ pin may be programmed to be either active HIGH or active LOW, and be either a CMOS or open drain output. The available interrupts are described in the section Registers on page 14. The CYRF6936 IC features three sets of interrupts: transmit, receive, and system interrupts. These interrupts all share a single pin (IRQ), but can be independently enabled or disabled. The contents of the enable registers are preserved when switching between transmit and receive modes. If more than one interrupt is enabled at any time, it is necessary to read the relevant status register to determine which event caused the IRQ pin to assert. Even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate status register. It is therefore possible to use the devices without the IRQ pin, by polling the status registers to wait for an event, rather than using the IRQ pin. Clocks A 12 MHz crystal (30 ppm or better) is directly connected between XTAL and GND without the need for external capacitors. A digital clock out function is provided, with selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This output may be used to clock an external microcontroller (MCU) or ASIC. This output is enabled by default, but may be disabled. The requirements to directly connect the crystal to the XTAL pin and GND are: ■ Nominal Frequency: 12 MHz ■ Operating Mode: Fundamental Mode ■ Resonance Mode: Parallel Resonant ■ Frequency Stability: ±30 ppm ■ Series Resistance: