CYRF6986-40LTXC

CYRF6986 WirelessUSB™ LPstar 2.4 GHz Radio SoC WirelessUSB™ LPstar 2.4 GHz Radio SoC Features Simple Development ■ 2.4 GHz direct sequence spread spectrum (DSSS) radio transceiver ■ Operates in the unlicensed worldwide Industrial, Scientific, and Medical (ISM) band (2.400 GHz to 2.483 GHz) ■ Auto transaction sequencer (ATS): Enables MCU to sleep longer ■ Framing, length, CRC16, and auto ACK ■ Separate 16-byte transmit and receive FIFOs ■ On Air compatible with second generation radio WirelessUSB™ LP and PRoC LP ■ Receive signal strength indication (RSSI) ■ Pin-to-pin compatible with WirelessUSB LP except the Pin30 and Pin37 ■ Serial peripheral interface (SPI) control while in sleep mode ■ 4 MHz SPI microcontroller interface Low Power BOM Savings ■ Operating current: 21 mA (transmit at –5 dBm) ■ Low external component count ■ Sleep current less than 1 A ■ Battery voltage monitoring circuitry ■ Operating voltage: 2.7 V to 3.6 V ■ Small footprint 40-pin QFN (6 mm × 6 mm) ■ Fast startup and fast channel changes Applications ■ Supports coin-cell operated applications ■ Wireless keyboards and mice Reliable and Robust ■ Presentation tools ■ Receive Sensitivity typical –90 dBm ■ Wireless gamepads ■ AutoRate™ – dynamic data rate reception ❐ Enables data reception for any of the supported bit rates automatically. ❐ DSSS (250 Kbps), GFSK (1 Mbps) ■ Remote controls ■ Toys ■ Fitness ■ Operating Temperature: 0 °C to 70 °C ■ Closed-loop frequency synthesis for minimal frequency drift Applications Support See www.cypress.com for development tools, reference designs, and application notes. Logic Block Diagram IRQ SS SCK MISO MOSI GFSK Modulator Data Interface and Sequencer DSSS Baseband & Framer RFP RFN RFBIAS Frequency Synthesizer SPI GFSK Demodulator RSSI Power Management RST VBAT Cypress Semiconductor Corporation Document Number: 001-66073 Rev. *D • VDD VCC 198 Champion Court GND • San Jose, CA 95134-1709 • 408-943-2600 Revised January 6, 2014 CYRF6986 Contents Functional Description ..................................................... 3 Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Functional Overview ........................................................ 4 Data Transmission Modes ........................................... 4 Link Layer Modes ........................................................ 4 Packet Buffers ............................................................. 5 Auto Transaction Sequencer (ATS) ............................ 5 Functional Block Overview .............................................. 5 2.4 GHz Radio ............................................................. 5 Frequency Synthesizer ................................................ 6 Baseband and Framer ................................................. 6 Packet Buffers and Radio Configuration Registers ............................................ 6 SPI Interface ................................................................ 6 Interrupts ..................................................................... 8 Clocks .......................................................................... 8 Power Management .................................................... 8 Low Noise Amplifier and Received Signal Strength Indication ................................... 8 Application Example ........................................................ 9 Registers ......................................................................... 11 Document Number: 001-66073 Rev. *D Absolute Maximum Ratings .......................................... 12 Operating Conditions ..................................................... 12 DC Characteristics ......................................................... 12 AC Characteristics ......................................................... 13 SPI Interface .............................................................. 13 RF Characteristics .......................................................... 14 Typical Operating Characteristics ................................ 16 AC Test Loads and Waveforms for Digital Pins .......... 18 Ordering Information ...................................................... 19 Ordering Code Definitions ......................................... 19 Package Diagram ............................................................ 20 Acronyms ........................................................................ 21 Document Conventions ................................................. 21 Units of Measure ....................................................... 21 Document History Page ................................................. 22 Sales, Solutions, and Legal Information ...................... 23 Worldwide Sales and Design Support ....................... 23 Products .................................................................... 23 PSoC® Solutions ...................................................... 23 Cypress Developer Community ................................. 23 Technical Support ..................................................... 23 Page 2 of 23 CYRF6986 Functional Description The CYRF6986 WirelessUSB LPstar radio is a second generation member of the Cypress WirelessUSB Radio System-On-Chip (SoC) family. The CYRF6986 IC adds a range of enhanced features, including reduced supply current in all operating modes, reduced crystal start up, synthesizer settling, and link turnaround times. Pinouts Figure 1. 40-pin QFN pinout NC 31 33 NC 32 VIO 35 RST 34 VDD NC 36 GND 37 38 NC 39 VBAT0 VCC 40 XTAL 1 30 NC NC 2 29 XOUT / GPIO VCC 3 28 MISO / GPIO NC 4 NC 5 VBAT1 6 VCC 7 24 SS VBAT2 8 23 NC NC 9 27 MOSI / SDAT CYRF6986 WirelessUSB LPstar 40-Pin QFN 26 IRQ / GPIO 25 SCK 22 NC * E-PAD Bottom Side 21 NC RFBIAS 10 20 NC 19 RESV 18 NC 17 NC 16 VCC 15 NC 14 NC 13 RFN 12 GND 11 RFP Pin Definitions Pin Number Name Type Default Description 1 XTAL I I 2, 4, 5, 9, 14, 15, 17, 18, 20, 21, 22, 23, 31, 32, 36, 39 NC NC Connect to GND. 3, 7, 16, 40 VCC Pwr VCC = 2.7 V to 3.6 V. 6, 8, 38 VBAT(0-2) Pwr 10 RFBIAS O O RF IO 1.8 V reference voltage. 11 RFP I/O I Differential RF signal to and from antenna. 12 GND GND 13 RFN IO 19 RESV I 24 SS I I SPI enable, active LOW assertion. Enables and frames transfers. 25 SCK I I SPI clock. 12 MHz crystal. VBAT = 2.7 V to 3.6 V. Main supply. Ground. I Differential RF signal to and from antenna. Must be connected to GND. 26 IRQ I/O O Interrupt output (configurable active HIGH or LOW), or GPIO. 27 MOSI I/O I SPI data input pin (Master Out Slave In), or SDAT. Document Number: 001-66073 Rev. *D Page 3 of 23 CYRF6986 Pin Definitions (continued) Pin Number Name Type Default 28 MISO I/O Z SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode). Tri-states when SPI 3PIN = 0 and SS is deasserted. 29 XOUT I/O O Buffered 0.75, 1.5, 3, 6, or 12 MHz clock or GPIO. Tri-states in sleep mode (configure as GPIO drive LOW). 30 NC NC Must be floating. 33 VIO Pwr I/O interface voltage, 2.7–3.6 V. 34 RST I 35 VDD Pwr Decoupling pin for 1.8 V logic regulator, connect through a 0.47 F capacitor to GND. 37 GND GND Must be connected to ground. E-PAD GND GND Must be soldered to ground. I Description Device reset. Internal 10 k pull down resistor. Active HIGH, connect through a 0.47 F capacitor to VBAT. Must have RST = 1 event the first time power is applied to the radio. Otherwise the state of the radio control registers is unknown. Functional Overview The CYRF6986 IC provides a complete WirelessUSB SPI to antenna wireless MODEMs. The SoC is designed to implement wireless device links operating in the worldwide 2.4 GHz ISM frequency band. It is intended for systems compliant with worldwide regulations covered by ETSI EN 301 489-1 V1.41, ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15 (USA and Industry Canada), and TELEC ARIB_T66_March, 2003 (Japan). The SoC contains a 2.4 GHz, 1 Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), and SPI interface for data transfer and device configuration. The radio supports 98 discrete 1 MHz channels (regulations may limit the use of some of these channels in certain jurisdictions). The baseband performs DSSS spreading/despreading, Start of Packet (SOP), End of Packet (EOP) detection, and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge (ACK) handshake packets whenever a valid packet is received. When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates. This enables the implementation of mixed-rate systems in which different devices use different data rates. This also enables the implementation of dynamic data rate systems that use high data rates at shorter distances or in a low-moderate interference environment or both. It changes to lower data rates at longer distances or in high interference environments or both. Data Transmission Modes The SoC supports two different data transmission modes: ■ ■ 32-chip pseudo noise (PN) codes are supported. The two data transmission modes apply to the data after the SOP. In particular the length, data, and CRC16 are all sent in the same mode. In general, DSSS reduce packet error rate in any given environment. Link Layer Modes The CYRF6986 IC device supports the following data packet framing features: SOP Packets begin with a two-symbol SoP marker. If framing is disabled then an SOP event is inferred whenever two successive correlations are detected. The SOP_CODE_ADR code used for the SOP is different from that used for the “body” of the packet, and if desired may be a different length. SOP must be configured to be the same length on both sides of the link. Length Length field is the first eight bits after the SOP symbol, and is transmitted at the payload data rate. An EoP condition is inferred after reception of the number of bytes defined in the length field, plus two bytes for the CRC16. CRC16 The device may be configured to append a 16 bit CRC16 to each packet. The CRC16 uses the USB CRC polynomial with the added programmability of the seed. If enabled, the receiver verifies the calculated CRC16 for the payload data against the received value in the CRC16 field. The seed value for the CRC16 calculation is configurable, and the CRC16 transmitted may be calculated using either the loaded seed value or a zero seed; the received data CRC16 is checked against both the configured and zero CRC16 seeds. In GFSK mode, data is transmitted at 1 Mbps, without any DSSS. CRC16 detects the following errors: ■ Any one bit in error. In DSSS mode eight bits (8DR, 32-chip) are encoded in each derived code symbol transmitted, resulting in effective 250 kbps data rate. ■ Any two bits in error (irrespective of how far apart, which column, and so on). Document Number: 001-66073 Rev. *D Page 4 of 23 CYRF6986 ■ Any odd number of bits in error (irrespective of the location). ■ An error burst as wide as the checksum itself. Figure 2 shows an example packet with SOP, CRC16, and lengths fields enabled, and Figure 3 shows a standard ACK packet. Figure 2. Example Packet Format 2nd Framing Symbol* Preamble N*16us Preamble SOP1 SOP2 1st Framing Symbol* Length CRC 16 Packet length 1 Byte Period *Note: 32 us Figure 3. Example ACK Packet Format Pream ble N *16us Pream ble 2nd Fram ing Sym bol* SOP1 SO P2 CRC 16 C R C Field From Received Packet. 1st Fram ing Sym bol* 2 Byte Periods *Note: 32 us Packet Buffers All data transmission and reception use the 16 byte packet buffers - one for transmission and one for reception. The transmit buffer allows loading a complete packet of up to 16 bytes of payload data in one burst SPI transaction. This is then transmitted with no further MCU intervention. Similarly, the receive buffer allows receiving an entire packet of payload data up to 16 bytes with no firmware intervention required until the packet reception is complete. The CYRF6986 IC supports packets up to 255 bytes. However, the actual maximum packet length depends on the accuracy of the clock on each end of the link and the data mode. Interrupts are provided to allow an MCU to use the transmit and receive buffers as FIFOs. When transmitting a packet longer than 16 bytes, the MCU can load 16 bytes initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. Similarly, when receiving packets longer than 16 bytes, the MCU must fetch received data from the FIFO periodically during packet reception to prevent it from overflowing. Auto Transaction Sequencer (ATS) The CYRF6986 IC provides automated support for transmission and reception of acknowledged data packets. When transmitting in transaction mode, the device automatically: ■ Starts the crystal and synthesizer ■ Enters transmit mode ■ Transmits the packet in the transmit buffer ■ Transitions to receive mode and waits for an ACK packet ■ Transitions to the transaction end state when an ACK packet is received or a timeout period expires Document Number: 001-66073 Rev. *D Similarly, when receiving in transaction mode, the device automatically: ■ Waits in receive mode for a valid packet to be received ■ Transitions to transmit mode, transmits an ACK packet ■ Transitions to the transaction end state (receive mode to await the next packet, and so on.) The contents of the packet buffers are not affected by the transmission or reception of ACK packets. In each case, the entire packet transaction takes place without any need for MCU firmware action (as long as packets of 16 bytes or less are used). To transmit data, the MCU must load the data packet to be transmitted, set the length, and set the TX GO bit. Similarly, when receiving packets in transaction mode, firmware must retrieve the fully received packet in response to an interrupt request indicating reception of a packet. Data Rates The CYRF6986 IC supports the following data rates by combining the PN code lengths and data transmission modes described in the previous sections: ■ 1000 kbps (GFSK) ■ 250 kbps (32 chip 8DR) Functional Block Overview 2.4 GHz Radio The radio transceiver is a dual conversion low IF architecture optimized for power, range, and robustness. The radio employs channel-matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides up to 0 dBm transmit power, with an output power Page 5 of 23 CYRF6986 control range of 35 dB in six steps. The supply current of the device is reduced as the RF output power is reduced. Table 1. Internal PA Output Power Step Table PA Setting 6 5 4 3 2 1 0 Typical Output Power (dBm) 0 –5 –13 –18 –24 –30 –35 Frequency Synthesizer Before transmission or reception may begin, the frequency synthesizer must settle. The settling time varies depending on channel; 25 fast channels are provided with a maximum settling time of 100 s. The ‘fast channels’ (less than 100 s settling time) are every third channel, starting at 0 up to and including 72 (for example, 0, 3, 6, 9 …. 69, 72). Baseband and Framer ✟ Command Increment (bit 6) = ‘1’ enables SPI auto address increment. When set, the address field automatically increments at the end of each data byte in a burst access. Otherwise the same address is accessed. ✟ Six bits of address ✟ Eight bits of data The device receives SCK from an application MCU on the SCK pin. Data from the application MCU is shifted in on the MOSI pin. Data to the application MCU is shifted out on the MISO pin. The active LOW Slave Select (SS) pin must be asserted to initiate an SPI transfer. The application MCU can initiate SPI data transfers using a multi-byte transaction. The first byte is the Command/Address byte, and the following bytes are the data bytes shown in Table 2 through Figure 6 on page 7. The SPI communications interface has a burst mechanism, where the first byte can be followed by as many data bytes as required. A burst transaction is terminated by deasserting the slave select (SS = 1). The SPI communications interface single read and burst read sequences are shown in Figure 4 on page 7 and Figure 5 on page 7, respectively. The SPI communications interface single write and burst write sequences are shown in Figure 6 on page 7 and Figure 7 on page 7, respectively. Packet Buffers and Radio Configuration Registers This interface may be optionally operated in a 3-pin mode with the MISO and MOSI functions combined in a single bidirectional data pin (SDAT). When using 3-pin mode, user firmware must ensure that the MOSI pin on the MCU is in a high impedance state except when MOSI is actively transmitting data. Packet data and configuration registers are accessed through the SPI interface. All configuration registers are directly addressed through the address field in the SPI packet. Configuration registers allow configuration of DSSS PN codes, data rate, operating mode, interrupt masks, interrupt status, and so on. The device registers may be written to or read from one byte at a time, or several sequential register locations may be written or read in a single SPI transaction using incrementing burst mode. In addition to single byte configuration registers, the device includes register files. Register files are FIFOs written to and read from using nonincrementing burst SPI transactions. The baseband and framer blocks provide the DSSS encoding and decoding, SOP generation and reception, CRC16 generation and checking, and EOP detection and length field. SPI Interface The CYRF6986 IC has an SPI interface supporting communication between an application MCU and one or more slave devices (including the CYRF6986). The SPI interface supports single-byte and multi-byte serial transfers using either 4-pin or 3-pin interfacing. The SPI communications interface consists of Slave Select (SS), Serial Clock (SCK), Master Out-Slave In (MOSI), Master In-Slave Out (MISO), or Serial Data (SDAT). SPI communication may be described as the following: ✟ Command Direction (bit 7) = ‘1’ enables SPI write transaction. A ‘0’ enables SPI read transactions. The IRQ pin function may be optionally multiplexed onto the MOSI pin. When this option is enabled, the IRQ function is not available while the SS pin is LOW. When using this configuration, user firmware must ensure that the MOSI pin on the MCU is in a high impedance state whenever the SS pin is HIGH. The SPI interface is not dependent on the internal 12 MHz clock. Registers may therefore be read from or written to when the device is in sleep mode, and the 12 MHz oscillator disabled. The SPI interface and the IRQ and RST pins have a separate voltage reference pin (VIO). This enables the device to interface directly to MCUs operating at voltages below the CYRF6986 IC supply voltage. Table 2. SPI Transaction Format Parameter Bit # Bit Name Byte 1 7 DIR 6 INC Document Number: 001-66073 Rev. *D [5:0] Address Byte 1+N [7:0] Data Page 6 of 23 CYRF6986 Figure 4. SPI Single Read Sequence SCK SS cmd MOSI DIR 0 INC addr A5 A4 A3 A2 A1 A0 data to mcu MISO D7 D6 D5 D4 D3 D2 D1 D0 Figure 5. SPI Incrementing Burst Read Sequence SCK SS cmd MOSI DIR 0 INC addr A5 A4 A3 A2 A1 A0 data to mcu1 MISO D7 D6 D5 D4 D3 data to mcu1+N D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 Figure 6. SPI Single Write Sequence SCK SS cmd MOSI DIR 1 INC addr A5 A4 A3 A2 data from mcu A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 MISO Figure 7. SPI Incrementing Burst Write Sequence SCK SS cmd MOSI DIR 1 INC addr A5 A4 A3 A2 data from mcu1 A1 A0 D7 D6 D5 D4 D3 D2 data from mcu1+N D1 D0 D7 D6 D5 D4 D3 D2 MISO Document Number: 001-66073 Rev. *D Page 7 of 23 CYRF6986 Interrupts Power Management The device provides an interrupt (IRQ) output, which is configurable to indicate the occurrence of various different events. The IRQ pin may be programmed to be either active HIGH or active LOW, and be either a CMOS or open drain output. The available interrupts are described in the section Registers on page 11. The operating voltage of the device is 2.7 V to 3.6 V DC, which is applied to the VBAT pin. The device can be shut down to a fully static sleep mode by writing to the FRC END = 1 and END STATE = 000 bits in the XACT_CFG_ADR register over the SPI interface. The device enters sleep mode within 35 µs after the last SCK positive edge at the end of this SPI transaction. Alternatively, the device may be configured to automatically enter sleep mode after completing the packet transmission or reception. When in sleep mode, the on-chip oscillator is stopped, but the SPI interface remains functional. The device wakes from sleep mode automatically when the device is commanded to enter transmit or receive mode. When resuming from sleep mode, there is a short delay while the oscillator restarts. The device can be configured to assert the IRQ pin when the oscillator has stabilized. The CYRF6986 IC features three sets of interrupts: transmit, receive, and system interrupts. These interrupts all share a single pin (IRQ), but can be independently enabled or disabled. The contents of the enable registers are preserved when switching between transmit and receive modes. If more than one interrupt is enabled at any time, it is necessary to read the relevant status register to determine which event caused the IRQ pin to assert. Even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate status register. It is therefore possible to use the devices without the IRQ pin, by polling the status registers to wait for an event, rather than using the IRQ pin. Clocks A 12 MHz crystal (30 ppm or better) is directly connected between XTAL and GND without the need for external capacitors. A digital clock out function is provided, with selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This output may be used to clock an external microcontroller (MCU) or ASIC. This output is enabled by default, but may be disabled. The requirements to directly connect the crystal to the XTAL pin and GND are: ■ Nominal Frequency: 12 MHz ■ Operating Mode: Fundamental Mode ■ Resonance Mode: Parallel Resonant ■ Frequency Stability: ±30 ppm ■ Series Resistance: 2000 V Static discharge voltage (RF) [9] ................................ 1100 V Latch-up current .....................................+200 mA, –200 mA Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ................................... –55 °C to +125 °C Supply voltage on any power supply pin relative to VSS ..............................................–0.3 V to +3.9 V DC voltage to logic inputs [8] ................. –0.3 V to VIO +0.3 V DC voltage applied to outputs in High-Z State ...................................... –0.3 V to VIO +0.3 V Operating Conditions VCC ................................................................. 2.7 V to 3.6 V VIO ...................................................................2.7 V to 3.6 V VBAT .................................................................2.7 V to 3.6 V TA (Ambient Temperature Under Bias) .......... 0 °C to +70 °C Ground Voltage ................................................................ 0 V FOSC (Crystal Frequency) .......................... 12 MHz ±30 ppm DC Characteristics (T = 25 C, VBAT = 2.7 V, fOSC = 12.000000 MHz) Parameter Description Conditions 0–70 C Min Typ Max Unit 2.7 – 3.6 V 2.7 – 3.6 V 2.7 – 3.6 V VIO – 0.2 VIO – V VIO – 0.4 VIO – V – 0 0.45 V VBAT Battery Voltage VIO[10] VIO Voltage VCC VCC Voltage VOH1 VOH2 Output High Voltage Condition 1 At IOH = –100.0 µA Output High Voltage Condition 2 At IOH = –2.0 mA VOL Output Low Voltage VIH Input High Voltage 0.7 × VIO VIO V VIL Input Low Voltage 0 0.3 × VIO V IIL Input Leakage Current 0 < VIN < VIO –1 0.26 +1 µA CIN Pin Input Capacitance except XTAL, RFN, RFP, RFBIAS – 3.5 10 pF Average TX ICC, 1 Mbps, slow channel PA = 5, 2 way, 4 bytes/10 ms – 0.87 – mA ICC (32-8DR)[11] Average TX ICC, 250 kbps, fast channel PA = 5, 2 way, 4 bytes/10 ms – 1.2 – mA ISB[12] Sleep Mode ICC – 0.8 10 µA IDLE ICC Radio off, XTAL Active – 1.0 – mA ICC (GFSK)[11] 0–70 C At IOL = 2.0 mA XOUT disabled Isynth ICC during Synth Start – 8.4 – mA TX ICC ICC during Transmit PA = 5 (–5 dBm) – 20.8 – mA TX ICC ICC during Transmit PA = 6 (0 dBm) – 26.2 – mA RX ICC ICC during Receive LNA off, ATT on – 18.4 – mA RX ICC ICC during Receive LNA on, ATT off – 21.2 – mA Notes 8. It is permissible to connect voltages above VIO to inputs through a series resistor limiting input current to 1 mA. AC timing not guaranteed. 9. Human Body Model (HBM). 10. In sleep mode, the IO interface voltage reference is VBAT. 11. Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including SOP and CRC16), changing to receive mode, and receiving ACK handshake. Device is in sleep except during this transaction. 12. ISB is not guaranteed if any IO pin is connected to voltages higher than VIO. Document Number: 001-66073 Rev. *D Page 12 of 23 CYRF6986 AC Characteristics SPI Interface Parameter [13, 14] Description Min Typ Max Unit 238.1 – – ns tSCK_CYC SPI Clock Period tSCK_HI SPI Clock High Time 100 – – ns tSCK_LO SPI Clock Low Time 100 – – ns tDAT_SU SPI Input Data Setup Time 25 – – ns tDAT_HLD SPI Input Data Hold Time 10 – – ns tDAT_VAL SPI Output Data Valid Time 0 – 50 ns tDAT_VAL_TRI SPI Output Data Tri-state (MOSI from Slave Select Deassert) – – 20 ns tSS_SU SPI Slave Select Setup Time before first positive edge of SCK[15] 10 – – ns tSS_HLD SPI Slave Select Hold Time after last negative edge of SCK 10 – – ns tSS_PW SPI Slave Select Minimum Pulse Width 20 – – ns tSCK_SU SPI Slave Select Setup Time 10 – – ns tSCK_HLD SPI SCK Hold Time 10 – – ns tRESET Minimum RST Pin Pulse Width 10 – – ns Figure 8. SPI Timing tSCK_CYC tSCK_HI SCK tSCK_LO tSCK_HLD tSCK_SU nSS tSS_SU tDAT_SU tSS_HLD tDAT_HLD MOSI input tDAT_VAL tDAT_VAL_TRI MISO MOSI output Notes 13. AC values are not guaranteed if voltage on any pin exceeding VIO. 14. CLOAD = 30 pF 15. SCK must start low at the time SS goes LOW, otherwise the success of SPI transactions are not guaranteed. Document Number: 001-66073 Rev. *D Page 13 of 23 CYRF6986 RF Characteristics Table 5. Radio Parameters Parameter Description RF Frequency Range Conditions Note 19 Min Typ Max Unit 2.400 – 2.497 GHz Receiver (T = 25 °C, VCC = VBAT = 3.0 V, fOSC = 12.000000 MHz, BER < 1E-3) Sensitivity 250 kbps 32-8DR BER 1E-3 – –90 – dBm Sensitivity GFSK BER 1E-3, ALL SLOW = 1 – –84 – dBm LNA Gain – 22.8 – dB ATT Gain – –31.7 – dB –15 –6 – dBm RSSI Value for PWRin –60 dBm LNA On – 21 – Count RSSI Slope – 1.9 – dB/Count Maximum Received Signal LNA On Interference Performance (CER 1E-3) Co-channel Interference rejection Carrier-to-Interference (C/I) C = –60 dBm – 9 – dB Adjacent (±1 MHz) channel selectivity C/I 1 MHz C = –60 dBm – 3 – dB Adjacent (±2 MHz) channel selectivity C/I 2 MHz C = –60 dBm – –30 – dB Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz C = –67 dBm – –38 – dB Out-of-Band Blocking 30 MHz–12.75 MHz[20] C = –67 dBm – –30 – dBm Inter modulation C = –64 dBm, f = 5,10 MHz – –36 – dBm 800 MHz 100 kHz ResBW – –79 – dBm 1.6 GHz 100 kHz ResBW – –71 – dBm 3.2 GHz 100 kHz ResBW – –65 – dBm Maximum RF Transmit Power PA = 6 –2 0 +2 dBm Maximum RF Transmit Power PA = 5 –7 –5 –3 dBm Maximum RF Transmit Power PA = 0 – –35 – 35 dB RF Power Range Control Step Size Six steps, monotonic – 5.6 dB Frequency Deviation Min PN Code Pattern 10101010 – 270 kHz Frequency Deviation Max PN Code Pattern 11110000 – 323 kHz Error Vector Magnitude (FSK error) >0 dBm – 10 – %rms Occupied Bandwidth –6 dBc, 100 kHz ResBW 500 876 – kHz Receive Spurious Emission Transmitter (T = 25 °C, VCC = 3.0 V) RF Power Control Range dBm Notes 19. Subject to regulation. 20. Exceptions F/3 & 5C/3. Document Number: 001-66073 Rev. *D Page 14 of 23 CYRF6986 Table 5. Radio Parameters (continued) Parameter Description Conditions Min Typ Max Unit In-band Spurious Second Channel Power (±2 MHz) – –38 – dBm In-band Spurious Third Channel Power (>3 MHz) – –44 – dBm Non-Harmonically Related Spurs (800 MHz) – –38 – dBm Non-Harmonically Related Spurs (1.6 GHz) – –34 – dBm Non-Harmonically Related Spurs (3.2 GHz) – –47 – dBm Harmonic Spurs (Second Harmonic) – –43 – dBm Harmonic Spurs (Third Harmonic) – –48 – dBm Fourth and Greater Harmonics – –59 – dBm – 0.7 1.3 ms Transmit Spurious Emission (PA = 6) Power Management (Crystal PN# eCERA GF-1200008) Crystal Start to 10 ppm Crystal Start to IRQ XSIRQ EN = 1 – 0.6 – ms Synth Settle Slow channels – – 270 µs Synth Settle Medium channels – – 180 µs Synth Settle Fast channels – – 100 µs Link Turnaround Time GFSK – – 30 µs Link Turnaround Time 250 kbps – – 62 µs Max Packet Length