CYT2B63CADQ0AZEGS

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CYT2B6 Datasheet 32-bit Arm® Cortex®-M4F Microcontroller Traveo™ II Family General Description CYT2B6 is a family of Traveo™ II microcontrollers targeted at automotive systems such as body control units. CYT2B6 has an Arm® Cortex®-M4 CPU for primary processing and an Arm Cortex-M0+ CPU for peripheral and security processing. These devices contain embedded peripherals supporting Controller Area Network with Flexible Data rate (CAN FD), and Local Interconnect Network (LIN). Traveo II devices are manufactured on an advanced 40-nm process. CYT2B6 incorporates Cypress' low-power flash memory, multiple high-performance analog and digital peripherals, and enables the creation of a secure computing platform. Features ■ ■ ■ ■ Dual CPU Subsystem ❐ 80-MHz (max) 32-bit Arm Cortex-M4F CPU with • Single-cycle multiply • Single-precision floating point unit (FPU) • Memory Protection Unit (MPU) ❐ 80-MHz (max) 32-bit Arm Cortex M0+ CPU with • Single-cycle multiply • Memory Protection Unit ❐ Inter-processor communication in hardware ❐ Three DMA controllers • Peripheral DMA controller #0 (P-DMA0) with 54 channels • Peripheral DMA controller #1 (P-DMA1) with 26 channels • Memory DMA controller #0 (M-DMA0) with 2 channels Integrated Memories ❐ 576 KB of code-flash with an additional 64 KB of work-flash • Read-While-Write (RWW) allows updating the code-flash/work-flash while executing from it • Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA]) • Flash programming through SWD/JTAG interface ❐ 64 KB of SRAM with selectable retention granularity Crypto Engine[1] ❐ Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM) ❐ Secure boot and authentication • Using digital signature verification • Using fast secure boot ❐ AES: 128-bit blocks, 128-/192-/256-bit keys [2] ❐ 3DES : 64-bit blocks, 64-bit key [2] ❐ Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve (ECC) [2] ❐ SHA-1/2/3 : SHA-512, SHA-256, SHA-160 with variable length input data [2] ❐ CRC : supports CCITT CRC16 and IEEE-802.3 CRC32 ❐ True random number generator (TRNG) and pseudo random number generator (PRNG) ❐ Galois/Counter Mode (GCM) Watchdog timer (WDT) Multi-counter watchdog timer (MCWDT) ❐ Low-voltage detector (LVD) ❐ Brown-out detector (BOD) ❐ Overvoltage detection (OVD) ❐ Clock supervisor (CSV) ❐ Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash) ❐ ❐ ■ Low-Power 2.7-V to 5.5-V Operation ❐ Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power management ❐ Configurable options for robust BOD • Two threshold levels (2.7 V and 3.0 V) for BOD on VDDD and VDDA • One threshold level (1.1 V) for BOD on VCCD ■ Wakeup Support ❐ A GPIO pin to wakeup from Hibernate mode ❐ Up to 78 GPIO pins to wakeup from Sleep modes ❐ Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes ■ Clock Sources ❐ Internal main oscillator (IMO) ❐ Internal low-speed oscillator (ILO) ❐ External crystal oscillator (ECO) ❐ Watch crystal oscillator (WCO) ❐ Phase-locked loop (PLL) ❐ Frequency-locked loop (FLL) ■ Communication Interfaces ❐ Up to four CAN FD channels • Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and transceivers • Compliant to ISO 11898-1:2015 • Supports all the requirements of Bosch CAN FD Specification V1.0 for non-ISO CAN FD • ISO 16845:2015 certificate available ❐ Up to six runtime-reconfigurable SCB (serial communication block) channels, each configurable as I2C, SPI, or UART ❐ Up to five independent LIN channels • LIN protocol compliant with ISO 17987 Functional Safety for ASIL-B ❐ Memory protection unit (MPU) ❐ Shared memory protection unit (SMPU) ❐ Peripheral protection unit (PPU) Notes 1. The Crypto engine features are available on select MPNs. 2. This feature is not available in “eSHE only” parts; for more information, refer to Ordering Information. Cypress Semiconductor Corporation Document Number: 002-25756 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 8, 2021 CYT2B6 Datasheet ■ ■ Timers ❐ Up to 50 16-bit and two 32-bit Timer/Counter Pulse-Width Modulator (TCPWM) blocks • Up to four 16-bit counters for motor control • Up to 46 16-bit counters and two 32-bit counters for regular operations • Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time (PWM_DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes ❐ Up to 11 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep • Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion, and so on) Real Time Clock (RTC) ❐ Year/Month/Date, Day-of-week, Hour:Minute:Second fields ❐ 12- and 24-hour formats ❐ Automatic leap-year correction ■ I/O ❐ Up to 78 programmable I/Os ❐ Two I/O types • GPIO Standard (GPIO_STD) • GPIO Enhanced (GPIO_ENH) ■ Regulators ❐ Generates 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply ❐ Two types of regulators • DeepSleep • Core internal ■ Each ADC supports 12-bit resolution and sampling rates of up to 1 Msps ❐ Each ADC also supports up to six internal analog inputs like • Bandgap reference to establish absolute voltage levels • Calibrated diode for junction temperature calculations • Two AMUXBUS inputs and two direct connections to monitor supply levels ❐ Each ADC supports addressing of external multiplexers ❐ Each ADC has a sequencer supporting autonomous scanning of configured channels ❐ Synchronized sampling of all ADCs for motor-sense applications ❐ ■ Smart I/O™ ❐ Up to three Smart I/O blocks, which can perform Boolean operations on signals going to and from I/Os ❐ Up to 16 I/Os (GPIO_STD) supported ■ Debug interface ❐ JTAG controller and interface compliant to IEEE-1149.1-2001 ❐ Arm SWD (Serial Wire Debug) port ❐ Supports Arm Embedded Trace Macrocell (ETM) Trace • Data trace using SWD • Instruction and data trace using JTAG ■ Compatible with industry-standard tools ❐ GHS/MULTI or IAR EWARM for code development and debugging ■ Packages ❐ 64-LQFP, 10 × 10 × 1.7 mm (max), 0.5-mm lead pitch ❐ 80-LQFP, 12 × 12 × 1.7 mm (max). 0.5-mm lead pitch ❐ 100-LQFP, 14 × 14 × 1.7 mm (max), 0.5-mm lead pitch Programmable Analog ❐ Three SAR A/D converters with up to 35 external channels (32 I/Os + 3 I/Os for motor control) • ADC0 supports 11 logical channels, with 11 + 1 physical connections • ADC1 supports 13 logical channels, with 13 + 1 physical connections • ADC2 supports 8 logical channels, with 8 + 1 physical connections • Any external channel can be connected to any logical channel in the respective SAR Document Number: 002-25756 Rev. *B Page 2 of 139 CYT2B6 Datasheet Contents Features List ..................................................................... 4 Communication Peripheral Instance List..................... 5 Blocks and Functionality ................................................. 6 Functional Description..................................................... 7 CPU Subsystem .......................................................... 7 System Resources ...................................................... 7 Peripherals .................................................................. 9 I/Os............................................................................ 11 CYT2B6 Address Map .................................................... 12 Flash Base Address Map ............................................... 13 Peripheral I/O Map .......................................................... 14 CYT2B6 Clock Diagram.................................................. 16 CYT2B6 CPU Start-up Sequence .................................. 17 Pin Assignment .............................................................. 18 High-Speed I/O Matrix Connections ............................. 24 Electrical Specifications ................................................ 72 Absolute Maximum Ratings....................................... 72 Device-Level Specifications ...................................... 74 DC Specifications ...................................................... 75 Reset Specifications.................................................. 79 I/O.............................................................................. 80 Analog Peripherals .................................................... 86 AC Specifications ...................................................... 90 Digital Peripherals ..................................................... 91 Memory ................................................................... 101 System Resources .................................................. 102 Debug...................................................................... 111 Clock Specifications ................................................ 113 Ordering Information.................................................... 119 Part Number Nomenclature..................................... 119 Packaging...................................................................... 121 Power Pin Assignments................................................. 28 Appendix ....................................................................... 125 Bootloading or End-of-line Programming ................ 125 External IP Revisions .............................................. 126 Alternate Function Pin Assignments............................ 29 Acronyms ...................................................................... 127 Interrupts and Wake-up Assignments.......................... 34 Errata ............................................................................. Document History Page ............................................... Revision History Change Log.................................. Sales, Solutions, and Legal Information .................... Worldwide Sales and Design Support..................... Products .................................................................. PSoC® Solutions .................................................... Cypress Developer Community............................... Technical Support ................................................... Package Pin List and Alternate Functions................... 25 Core Interrupt Types ...................................................... 40 Trigger Multiplexer ......................................................... 41 Triggers Group Inputs.................................................... 42 Triggers Group Outputs................................................. 51 Triggers One-to-One ...................................................... 52 Peripheral Clocks ........................................................... 56 129 134 135 139 139 139 139 139 139 Faults ............................................................................... 58 Peripheral Protection Unit Fixed Structure Pairs ........ 61 Bus Masters .................................................................... 69 Miscellaneous Configuration ........................................ 70 Development Support .................................................... 71 Documentation .......................................................... 71 Tools.......................................................................... 71 Document Number: 002-25756 Rev. *B Page 3 of 139 CYT2B6 Datasheet 1. Features List Table 1-1. CYT2B6 Feature List for All Packages Features CPU Core Functional safety Operating voltage Core voltage Operating frequency MPU, PPU FPU DSP-MUL/DIV/MAC Memory Code-flash Work-flash SRAM (configurable for retention) ROM Communication Interfaces CAN 0 (CAN FD: Up to 8 Mbps) CAN 1 (CAN FD: Up to 8 Mbps) CAN RAM Serial communication block (SCB/UART) Serial communication block (SCB/I2C) Serial communication block (SCB/SPI) LIN0 Timers RTC TCPWM (16-bit) (Motor Control) TCPWM (16-bit) TCPWM (32-bit) External Interrupts Analog 12-bit, 1 Msps SAR ADC Motor Control Input Security Flash Security (program/work read protection) Flash Chip erase enable eSHE Packages 64-LQFP 80-LQFP 100-LQFP 32-bit Arm Cortex-M4F CPU and 32-bit Arm Cortex M0+ CPU ASIL-B 2.7 V to 5.5 V 1.05 V to 1.15 V Arm Cortex-M4 80 MHz (max) and Arm Cortex-M0+ 80 MHz (max), related by integer frequency ratio (that is, 1:1, 1:2, 1:3, and so on) Supported Single precision (32-bit) Supported by Arm Cortex-M4F CPU 576 KB (448 KB + 128 KB) 64 KB (48 KB + 16 KB) 64 KB 32 KB 2 ch 1 ch 5 ch 3 ch 49 2 ch 24 KB per instance (2 ch), 48 KB in total 6 ch 6 ch 6 ch 5 ch 1 ch 4 ch 46 ch 2 ch 63 78 3 Units (SAR0/11, SAR1/13, SAR2/8 logical channels) 22 external channels 28 external channels 32 external channels (SAR0 8 ch, SAR1 7 ch, (SAR0 10 ch, (SAR0 11 ch, SAR1 13 ch, SAR2 7 ch) SAR1 10 ch, SAR2 8 ch) SAR2 8 ch) 18 ch (6 per ADC) Internal sampling 3 ch (synchronous sampling of one channel on each of the 3 ADCs) Supported Configurable By separate firmware[3] Note 3. Enhanced Secure Hardware Extension (eSHE) is enabled by third-party firmware. Document Number: 002-25756 Rev. *B Page 4 of 139 CYT2B6 Datasheet Table 1-1. CYT2B6 Feature List for All Packages (continued) Features Packages 80-LQFP 64-LQFP 100-LQFP System P-DMA0 with 54 channels (16 general purpose), P-DMA1 with 26 channels (8 general purpose), and M-DMA0 with 2 channels 8 MHz 32.768 kHz (nominal) Input frequency: 3.988 to 33.34 MHz, PLL output frequency: up to 80 MHz Input frequency: 0.25 to 80 MHz, FLL output frequency: up to 80 MHz Supported Supported Supported 45 59 74 4 3 blocks, 3 blocks, 3 blocks, 9 I/Os 14 I/Os 16 I/Os Two, 26 selectable levels 105 °C for S-grade and 125 °C for E-grade SWD/JTAG Arm Cortex-M4 ETB size of 8 KB, Arm Cortex M0+ MTB size of 4 KB DMA Controller Internal main oscillator Internal low-speed oscillator PLL FLL Watchdog timer and multi-counter watchdog timer Clock supervisor Cyclic wakeup from DeepSleep GPIO_STD GPIO_ENH Smart I/O (Blocks) Low-voltage detect Maximum ambient temperature Debug interface Debug trace 1.1 Communication Peripheral Instance List The following table lists the instances supported under each package for communication peripherals, based on the minimum pins needed for the functionality. Table 1-2. Peripheral Instance List Module 64-LQFP 80-LQFP 100-LQFP Minimum Pin Functions CAN0 0/1 0/1 0/1 TX, RX CAN1 0 0/1 0/1 TX, RX LIN0 0/1/2/3/4 0/1/2/3/4 0/1/2/3/4 TX, RX SCB/UART 0/1/3/4/5/7 0/1/3/4/5/7 0/1/3/4/5/7 TX, RX SCB/I2C 0/3/4/5/7 0/1/3/4/5/7 0/1/3/4/5/7 SCL, SDA SCB/SPI 0/3/4 0/1/3/4/5/7 0/1/3/4/5/7 MISO, MOSI, SCK, SELECT0 Document Number: 002-25756 Rev. *B Page 5 of 139 CYT2B6 Datasheet 2. Blocks and Functionality Figure 2-1.Block Diagram CPU Subsystem CYT2B6 SWJ/ETM/ITM/CTI SWJ/MTB/CTI CRYPTO M-DMA0 2 Channel 8 KB $ 8 KB $ Flash Controller 26 Channel FPU, NVIC, MPU Power Sleep Control POR BOD OVD LVD REF 64 KB P-DMA1 System Resources 80 MHz SRAM0 54 Channel Arm Cortex-M4 eCT Flash 576 KB Code Flash + 64 KB Work Flash P-DMA0 MXS40-HT ASIL-B SRAM Controller ROM Arm Cortex-M0+ AES, SHA, CRC, TRNG, RSA, ECC 32 KB 80 MHz Initiator/MMIO ROM Controller MUL, NVIC, MPU System Interconnect (Multi Layer AHB, IPC, MPU/SMPU) PWRSYS-HT LDO 1024 bit eFuse EVTGEN Event Generator CAN-FD Interface Up to 4x CANFD I2C, SPI, UART Up to 5x SCB SARMUX 32 ch Power Modes Active/Sleep LowePowerActive/Sleep High Speed I/O Matrix, Smart I/O, Boundary Scan DeepSleep Up to 74x GPIO_STD, 4x GPIO_ENH Hibernate 1x SCB I2C, SPI, UART LIN/UART x3 Up to 5x LIN SAR ADC (12-bit) 52x TCPWM TIMER,CTR,QD, PWM WCO RTC Prog. Analog IOSS GPIO Reset Reset Control XRES Test TestMode Entry Digital DFT Analog DFT Peripheral Interconnect (MMIO, PPU) PCLK Clock Clock Control 2xILO WDT IMO ECO FLL CSV 1xPLL 3x Smart I/O I/O Subsystem Figure 2-1. shows the CYT2B6 architecture block diagram, giving a simplified view of the interconnection between subsystems and blocks. CYT2B6 has four major subsystems: CPU, system resources, peripherals, and I/O[4, 5]. The color-coding shows the lowest power mode where the particular block is still functional. The JTAG interface is fully compatible with industry-standard third-party probes such as I-jet, J-Link, and GHS. CYT2B6 provides extensive support for programming, testing, debugging, and tracing of both hardware and firmware. Additionally, each device interface can be permanently disabled for applications concerned with phishing attacks from a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when maximum device security is enabled. Debug-on-chip functionality enables in-system debugging using the production device. It does not require special interfaces, debugging pods, simulators, or emulators. The debug circuits are enabled by default. CYT2B6 provides a high level of security with robust flash protection and the ability to disable features such as debug. Notes 4. GPIO_STD supporting 2.7 V to 5.5 V VDDIO range. 5. GPIO_ENH supporting 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages. Document Number: 002-25756 Rev. *B Page 6 of 139 CYT2B6 Datasheet 3. Functional Description 3.1 CPU Subsystem 3.1.1 CPU The CYT2B6 CPU subsystem contains a 32-bit Arm Cortex-M0+ CPU with MPU and a 32-bit Arm Cortex-M4F CPU with MPU, and single-precision FPU. This subsystem also includes P-/M-DMA controllers, a cryptographic accelerator, 576 KB of code-flash, 64 KB of work-flash, 64 KB of SRAM, and 32 KB of ROM. The Cortex-M0+ CPU provides a secure, un-interruptible boot function. This guarantees that, following completion of the boot function, system integrity is valid and privileges are enforced. Shared resources (flash, SRAM, peripherals, and so on) can be accessed through bus arbitration, and exclusive accesses are supported by an inter-processor communication (IPC) mechanism using hardware semaphores. 3.1.2 DMA Controllers CYT2B6 has three DMA controllers: P-DMA0 with 16 general-purpose and 38 dedicated channels, P-DMA1 with 8 general-purpose and 18 dedicated channels, and M-DMA0 with two channels. P-DMA is used for peripheral-to-memory and memory-to-peripheral data transfers and provides low latency for a large number of channels. Each P-DMA controller uses a single data-transfer engine that is shared by the associated channels. General-purpose channels have a rich interconnect matrix including P-DMA cross triggering, which enables demanding data-transfer scenarios. Dedicated channels have a single triggering input (such as an ADC channel) to handle common transfer needs. M-DMA is used for memory-to-memory data transfers and provides high memory bandwidth for a small number of channels. M-DMA uses a dedicated data-transfer engine for each channel. They support independent accesses to peripherals using the AHB multi-layer bus. 3.1.3 Flash CYT2B6 has 576 KB (448 KB with a 32-KB sector size, and 128 KB with an 8-KB sector size) of code-flash with an additional work-flash of up to 64 KB (48 KB with 2-KB sector size, and 16 KB with 128-B sectors size). Work-flash is optimized for reprogramming many more times than code-flash. Code-flash supports Read-While-Write (RWW) operation allowing flash to be updated while the CPU is active. Both the code-flash and work-flash areas support dual-bank operation for over-the-air (OTA) programming. 3.1.4 SRAM CYT2B6 has 64 KB of SRAM. The SRAM0 controller provides DeepSleep retention in 32-KB increments. 3.1.5 ROM CYT2B6 has 32-KB ROM that contains boot and configuration routines. This ROM enables secure boot and authentication of user flash to guarantee a secure system. Document Number: 002-25756 Rev. *B 3.1.6 Cryptography Accelerator for Security The cryptography accelerator implements (3)DES block cipher, AES block cipher, SHA hash, cyclic redundancy check, pseudo random number generation, true random number generation, galois/counter mode, and a vector unit to support asymmetric key cryptography such as RSA and ECC. Depending on the part number, this block is either completely or partially available or not available at all. See Ordering Information for more details. 3.2 System Resources 3.2.1 Power System The power system ensures that the supply voltage levels meet the requirements of each power mode, and provides a full-system reset when these levels are not valid. Internal power-on reset (POR) guarantees full-chip reset during the initial power ramp. Three Brown-Out Detection (BOD) circuits monitor the external supply voltages (VDDD, VDDA, VCCD). The BOD on VDDD and VCCD are initially enabled and cannot be disabled. The BOD on VDDA is initially disabled and can be enabled by the user. For the external supplies VDDD and VDDA, BOD circuits are software configurable with two settings; a 2.7-V minimum voltage that is robust for all internal signaling and a 3.0-V minimum voltage, which is also robust for all I/O specifications (which are guaranteed at 2.7 V). The BOD on VCCD is provided as a safety measure and is not a robust detector. Three overvoltage detection (OVD) circuits are provided for monitoring external supplies (VDDD, VDDA, VCCD), and overcurrent detection circuits (OCD) for monitoring internal and external regulators. OVD thresholds on VDDD and VDDA are configurable with two settings; a 5.0-V and 5.5-V maximum voltage. Two voltage-detection circuits are provided to monitor the external supply voltage (VDDD) for falling and rising levels, each configurable for one of the 26 selectable levels. All BOD, OVD, and OCD circuits on VDDD and VCCD generate a reset, because these protect the CPUs and fault logic. The BOD and OVD circuits on VDDA can be configured to generate either a reset or a fault. 3.2.2 Regulators CYT2B6 contains two regulators that provide power to the low-voltage core transistors: DeepSleep and core internal. These regulators accept a 2.7–5.5-V VDDD supply and provide a low-noise 1.1-V supply to various parts of the device. These regulators are automatically enabled and disabled by hardware and firmware when switching between power modes. The core internal and core external regulators operate in active mode, and provide power to the CPU subsystem and associated peripherals. DeepSleep The DeepSleep regulator is used to maintain power to a small number of blocks when in DeepSleep mode. These blocks include the ILO and WDT timers, BOD detector, SCB0, SRAM memories, Smart I/O, and other configuration memories. The DeepSleep regulator is enabled when in DeepSleep mode, and the core internal regulator is disabled. It is disabled when XRES_L is asserted (LOW) and when the core internal regulator is disabled. Page 7 of 139 CYT2B6 Datasheet Core internal The core internal regulator supports load currents up to 150 mA, and is operational during device start-up (boot process) and in Active/Sleep modes. counter determine the frequency of the reference clock as well as the upper and lower frequency limits of the monitored clock. If the frequency range comparator detects a stopped clock or a clock outside the specified frequency range, an abnormal state is signaled and either a reset or an interrupt is generated. 3.2.3 Clock System EXT_CLK The CYT2B6 clock system provides clocks to all subsystems that require them, and glitch-free switching between different clock sources. In addition, the clock system ensures that no metastable conditions occur. One of the two GPIO_STD I/Os can be used to provide an external clock input of up to 80 MHz. This clock can be used as the source clock for either the PLL or FLL, or can be used directly by the CLK_HF domain. The clock system for CYT2B6 consists of the 8-MHz IMO, two ILOs, three watchdog timers, a PLL, an FLL, five clock supervisors (CSV), a 3.988- to 33.34 MHz ECO, and a 32.768-kHz WCO. ECO The clock system supports two main clock domains: CLK_HF and CLK_LF. ■ CLK_HFx are the Active mode clocks. Each can use any of the high-frequency clock sources including IMO, EXT_CLK, ECO, FLL, or PLL ■ CLK_LF is a DeepSleep domain clock and provides a reference clock for the MCWDT or RTC modules. The reference clock for the CLK_LF domain is either disabled or selectable from ILO0, ILO1, or WCO Table 3-1. CLK_HF Destinations Name Description CLK_HF0 CPUSS clocks, PERI, and AHB infrastructure CLK_HF1 Event Generator, also available in HSIOM as an output IMO Clock Source The IMO is the frequency reference in CYT2B6 when no external reference is available or enabled. The IMO operates at a frequency of 8 MHz ±1%. The internal trim settings for the IMO can be dynamically updated to provide a tolerance = 4 and multiply of 4, Excludes system overhead time SID598 Over current detection Details/Conditions range in Active/Sleep mode (None) Guaranteed by Design Added condition SID599 Over current detection Details/Conditions range in DeepSleep mode (None) Guaranteed by Design Added condition SID332 Feedback resistor value for Details/Conditions ECO (None) Guaranteed by Design Added condition Added spec Added spec SID349C PFD frequency Min 4 MHz 3.988 MHz Updated spec SID350A FLL wake up time SID Parameter Max SID350 tFLL_WAKE Max: TBD SID350A tFLL_WAKE_A Max: 3.5 us Updated spec SID412 Minimum WDT timeout Details/Conditions When using the ILO (32.768 kHz + 5%) When using the ILO (32.768 kHz + 5%) and 32-bit WDT counter. and 16-bit WDT counter. Guaranteed by Design. Guaranteed by Design. Updated condition SID413 Maximum WDT timeout Details/Conditions When using the ILO (32.768 kHz - 5%) When using the ILO (32.768 kHz and 16-bit WDT counter. 5%) and 32-bit WDT counter. Guaranteed by Design. Guaranteed by Design. Updated condition Document Number: 002-25756 Rev. *B Page 137 of 139 CYT2B6 Datasheet Rev *B Electrical Specification Updates (continued) Spec ID SID414 Description Default WDT timeout Changed Item Typ Details/Conditions Document Number: 002-25756 Rev. *B Current Spec (Rev *A) Typ: 125 ms Details/Conditions: When using the ILO and 32-bit WDT counter at 0x1000 (default value). Guaranteed by Design. New Spec (Rev *B) Reason for Change Updated spec Typ: 1000 ms Details/Conditions: When using the ILO and 32-bit WDT counter at 0x8000 (default value). Guaranteed by Design. Page 138 of 139 CYT2B6 Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Document Number: 002-25756 Rev. *B Revised July 8, 2021 Page 139 of 139