Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
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Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
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www.infineon.com
CYUSB302x
SD3™ USB and Mass Storage
Peripheral Controller
SD3™ USB and Mass Storage Peripheral Controller
Features
■
10 × 10 mm, 0.8-mm pitch ball grid array (BGA) package
■
USB thumb drives
USB integration
❐ Certified USB 3.0 and USB 2.0 peripheral: SuperSpeed (SS),
Hi-Speed (HS), and Full-Speed (FS) only.
❐ Thirty-two physical endpoints
❐ Integrated transceiver
■
Card readers
■
Laptop with SD slots
■
SD slot in TV/STB
■
WIFI Dongles
■
USB SDIO Bridge
■
Raid on-Chip Controller
Applications
Ultra low-power in core power-down mode
❐ Less than 60 µA with VBATT on and 20 µA with VBATT off
I2C master controller at 1 MHz
Selectable input clock frequencies
❐ 19.2, 26, 38.4, and 52 MHz
❐ 19.2-MHz crystal input support
TDI
Logic Block Diagram
TDO
■
■
TCK
■
Latest-generation storage support
❐ SD3.0/SDXC – UHS1 SDR50 / DDR50 Master
❐ eMMC 4.4 Master
❐ SDIO 3.0 Master
TRST#
■
Independent power domains for core and I/O
TMS
■
■
JTAG
Embedded
SRAm
(512 kB/
256 KB)
ARM926EJ-S
SS
Peripheral
USB
EPs
GPIOs
HS/FS
Peripheral
FSLC[0]
FSLC[1]
USB INTERFACE
SSRXSSRX+
SSTXSSTX+
D+
D-
FSLC[2]
UART
CLKIN
SDIO/SD/MMC Controller
CLKIN_32
XTALIN
SPI
XTALOUT
S1_WP
MMC1_RST_OUT
S1_CLK
S1_CMD
S1_SD6
S1_SD7
S1_SD5
S1_SD3
S1_SD2
S1_SD1
S1_SD0
MMC0_RST_OUT
S0S1_INS
S1-PORT
S0_WP
S0_CLK
S0_CMD
S0_SD6
S0_SD7
S0_SD5
S0_SD4
S0_SD3
S0_SD2
S0_SD1
S0_SD0
I2C_SDA
I2C_SCL
S0-PORT
S1_SD4
I 2S
I2C
Errata: For information on silicon errata, see “Errata” on page 27. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 001-55190 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 14, 2018
CYUSB302x
Contents
Functional Overview ........................................................ 3
USB Interface (U-Port) ................................................ 3
Mass-Storage Support (S-Port) ................................... 3
I2C Interface ................................................................ 3
UART Interface ............................................................ 3
I2S Interface ................................................................ 3
SPI Interface ................................................................ 3
Boot Options ..................................................................... 4
Reset .................................................................................. 4
Clocking ............................................................................ 4
32-kHz Watchdog Timer Clock Input ........................... 4
Power ................................................................................. 5
Power Modes .............................................................. 5
Configuration Fuse ........................................................... 7
Digital I/Os ......................................................................... 7
EMI ..................................................................................... 7
System Level ESD ............................................................ 7
Pinout ................................................................................ 7
Pin Description ................................................................. 8
Electrical Specifications ................................................ 12
Absolute Maximum Ratings ....................................... 12
Operating Conditions ................................................. 12
DC Specifications ...................................................... 12
Thermal Characteristics ................................................. 14
Document Number: 001-55190 Rev. *N
AC Timing Parameters ................................................... 15
Storage Port Timing .................................................. 15
I2C Interface Timing .................................................. 18
Reset Sequence ........................................................ 23
Package Diagrams .......................................................... 24
Ordering Information ...................................................... 25
Ordering Code Definitions ......................................... 25
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Errata ............................................................................... 27
Part Numbers Affected .............................................. 27
SD3 USB and Mass Storage Peripheral Controller
Qualification Status ........................................................... 27
SD3 USB and Mass Storage Peripheral Controller
Errata Summary ............................................................... 27
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 34
Worldwide Sales and Design Support ....................... 34
Products .................................................................... 34
PSoC® Solutions ...................................................... 34
Cypress Developer Community ................................. 34
Technical Support ..................................................... 34
Page 2 of 34
CYUSB302x
Functional Overview
I2C Interface
SD3™ is a USB 3.0 SuperSpeed mass-storage controller
providing the latest SD/MMC support. SD3 complies with the SD
Specification, Version 3.0, and the MMC Specification, Version
4.41.
SD3 has an I2C interface compatible with the I2C Bus
Specification Revision 3. Because SD3’s I2C interface is capable
of operating only as I2C master, it may be used to communicate
with other I2C slave devices. For example, SD3 may boot from
an EEPROM connected to the I2C interface, as a selectable boot
option.
SD3 offers the following access paths among USB and mass
storage ports:
■
A USB-port (U-Port) supporting USB 3.0 peripheral
Two mass-storage ports (S0-Port and S1-Port) supporting
mass-storage devices. Following are the possible
configurations for the two mass-storage ports:
❐ SD and MMC
❐ SD and SD
❐ MMC and MMC
❐ SD and SDIO
❐ MMC and SDIO
❐ SDIO and SDIO
Combinations of these accesses can happen independently or
in an interleaved manner.
■
The SD3 complies with the USB 3.0 v1.0 specification and is also
backward compatible with USB 2.0.
USB Interface (U-Port)
Supports USB peripheral functionality compliant with the USB
3.0 Specification Revision 1.0 and is backward-compatible with
the USB 2.0 Specification
■
Supports up to 16 IN and 16 OUT endpoints.
■
Supports the USB 3.0 Streams feature. It also supports USB
Attached SCSI (UAS) device class to optimize mass-storage
access performance.
■
As a USB peripheral, SD3 supports UAS and Mass Storage
Class (MSC) peripheral classes.
■
When the USB port is not in use, the PHY and transceiver may
be disabled for power savings.
Figure 1. USB Interface Signals
SD3
VBUS
SSRX+
SSTXSSTX+
DD+
USB Interface
VBATT
SSRX-
The power supply for the I2C interface is VIO5, which is a
separate power domain from the other serial peripherals. This is
to allow the I2C interface the flexibility to operate at a different
voltage than the other serial interfaces.
The I2C controller supports bus frequencies of 100 kHz,
400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum
operating frequency supported is 100 kHz. When VIO5 is 1.8 V,
2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz
and 1 MHz. The I2C controller supports the clock stretching
feature to enable slower devices to exercise flow control.
Both SCL and SDA signals of the I2C interface require external
pull-up resistors. These resistors must be connected to VIO5.
UART Interface
The UART interface of SD3 supports full-duplex communication.
It includes the signals noted in Table 1.
SD3 offers the following features:
■
SD3’s I2C master controller also supports multi-master mode
functionality.
Mass-Storage Support (S-Port)
The SD3 storage interface port supports the following
specifications:
■ SD Specification, Version 3.0
■ Multimedia Card-System Specification, MMCA Technical
Committee, Version 4.4
■ SDIO Host controller compliant with SDIO Specification
Version 3.00
Document Number: 001-55190 Rev. *N
Table 1. UART Interface Signals
Signal
Description
TX
Output signal
RX
Input signal
CTS
Flow control
RTS
Flow control
The UART is capable of generating a range of baud rates, from
300 bps to 4608 Kbps, selectable by the firmware. If flow control
is enabled, then SD3's UART only transmits data when the CTS
input is asserted. In addition to this, SD3’s UART asserts the
RTS output signal, when it is ready to receive data.
I2S Interface
SD3 has an I2S port to support external audio codec devices.
SD3 functions as I2S Master as transmitter only. The I2S
interface consists of four signals: clock line (I2S_CLK), serial
data line (I2S_SD), word select line (I2S_WS), and master
system clock (I2S_MCLK). SD3 can generate the system clock
as an output on I2S_MCLK or accept an external system clock
input on I2S_MCLK.
The sampling frequencies supported by the I2S interface are
8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz and 192 kHz.
SPI Interface
SD3 supports an SPI Master interface on the Serial Peripherals
port. The maximum operation frequency is 33 MHz.
The SPI controller supports four modes of SPI communication
(see SPI Timing Specification on page 21 for details on the
modes) with the Start-Stop clock. This controller is a
single-master controller with a single automated SSN control. It
supports transaction sizes ranging from 4 bits to 32 bits.
Page 3 of 34
CYUSB302x
Boot Options
SD3 can load boot images from various sources, selected by the
configuration of the PMODE pins. The boot options for the SD3
are as follows:
■
Boot from USB
■
Boot from I2C
■
■
The input clock frequency is independent of the clock/data rate
of SD3 core or any of the device interfaces. The internal PLL
applies the appropriate clock multiply option depending on the
input frequency.
Table 3. Crystal/Clock Frequency Selection
FSLC[2]
FSLC[1]
FSLC[0]
Crystal/Clock
Frequency
Boot from eMMC on S0-Port
0
0
0
19.2-MHz crystal
Boot from SPI
❐ Cypress SPI Flash parts supported are
S25FS064S (64-Mbit), S25FS128S (128-Mbit) and
S25LFL064L (64-Mbit).
❐ W25Q32FW (32-Mbit) and equivalent parts are also
supported.
1
0
0
19.2-MHz input CLK
1
0
1
26-MHz input CLK
1
1
0
38.4-MHz input CLK
1
1
1
52-MHz input CLK
Table 2. Booting Options for SD3
PMODE[2:0] [1]
FF0
FF1
FFF
0FF
0F1
Boot From
S0-Port: eMMC
On failure, USB boot enabled
USB Boot
I2C
On Failure, USB Boot is enabled
I2C only
SPI
On Failure, USB Boot is enabled
Reset
Table 4. Input Clock Specifications for SD3
Parameter
Phase noise
Specification
Description
Min
Max
Units
100-Hz offset
–
–75
dB
1-kHz offset
–
–104
dB
10-kHz offset
–
–120
dB
100-kHz offset
–
–128
dB
1-MHz offset
–
–130
dB
Maximum frequency
deviation
–
–
150
ppm
Duty cycle
–
30
70
%
A reset is initiated by asserting the Reset# pin on SD3. The
specific reset sequence and timing requirements are detailed in
Figure 3 on page 18 and Table 15 on page 23. All I/Os are
tristated during a hard reset.
Overshoot
–
–
3
%
Undershoot
–
–
–3
%
Rise time/fall time
–
–
3
ns
Clocking
32-kHz Watchdog Timer Clock Input
SD3 allows either a crystal to be connected between the XTALIN
and XTALOUT pins or an external clock to be connected at the
CLKIN pin. The XTALIN, XTALOUT, CLKIN, and CLKIN_32 pins
can be left unconnected if not used.
SD3 includes a watchdog timer that can be used to interrupt the
core, automatically wake up SD3 in Standby mode, and reset the
core. The watchdog timer runs off a 32-kHz clock, which may
optionally be supplied from an external source on a dedicated
pin of SD3.
Crystal frequency supported is 19.2 MHz, while the external
clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.
SD3 has an on-chip oscillator circuit that uses an external
19.2 MHz (±100 ppm) crystal (when the crystal option is used).
An appropriate load capacitance is required with a crystal. Refer
to the specification of the crystal used to determine the appropriate load capacitance. The FSLC[2:0] pins must be configured
appropriately to select the crystal option/clock frequency option.
The configuration options are shown in Table 3.
Clock inputs to SD3 must meet the phase noise and jitter
requirements specified in Table 4.
The watchdog timer can be disabled by firmware.
Requirements for the optional 32-kHZ clock input are listed in
Table 5.
Table 5. 32-kHz Clock Input Requirements
Min
Max
Units
Duty cycle
Parameter
40
60
%
Frequency deviation
–
±200
ppm
Rise Time/fall Time
–
200
ns
Note
1. F indicates Floating.
Document Number: 001-55190 Rev. *N
Page 4 of 34
CYUSB302x
Power
SD3 has the following main groups of power supply domains:
■
■
■
IO_VDDQ: This refers to a group of independent supply
domains for digital I/Os. The voltage level on these supplies
are 1.8 V to 3.3 V. SD3 provides six independent supply
domains for digital I/Os listed as follows:
❐ S0VDDQ: S0-Port (for SD/MMC) I/O Power Supply Domain
❐ S1VDDQ: S1-Port (for SD/MMC) I/O Power Supply Domain
❐ S2VDDQ: S2-Port (GPIO) Power Supply Domain
❐ VIO4: S1-Port GPIO[53:57]/O Power Supply Domain (these
pins support MMC’s high nibble data line - D[7:4] on S1-Port)
❐ VIO5: I2C Power Supply Domain (supports 1.2 V to 3.3 V)
❐ CVDDQ: Clock Power Supply Domain
VDD: This is the supply voltage for the logic core. The nominal
supply voltage level is 1.2 V. This supplies the core logic
circuits. The same supply must also be used for the following:
❐ AVDD: This is the 1.2-V supply for the PLL, crystal oscillator
and other core analog circuits
❐ U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply voltages for the USB 3.0 interface.
Note: No specific power-up sequence required for SD3 power
domains. Minimum power on reset time of 1 ms should be met
and the power domains must be stable for SD3 operation.
Power Modes
SD3 supports the following power modes:
■
Normal mode: This is the full-functional operating mode. In this
mode the internal CPU clock and the internal PLLs are enabled.
Normal operating power consumption does not exceed the sum
of ICC_CORE max and ICC_USB max (see Table 8 on page 12
for current consumption specifications).
The I/O power supplies (S0VDDQ, S1VDDQ, VIO4, and VIO5)
may be turned off when the corresponding interface is not in use.
S2VDDQ cannot be turned off at any time if the S2-Port is used
in the application.
■
SD3 supports four low-power modes (see Table 6 on page 5):
❐ Suspend mode with USB 3.0 PHY enabled (L1 mode)
❐ Suspend mode with USB 3.0 PHY disabled (L2 mode)
❐ Standby mode (L3 mode)
❐ Core power-down mode (L4 mode)
VBATT/VBUS: This is the 3.2-V to 6-V battery power supply
for the USB I/O and analog circuits. This supply powers the
USB transceiver through SD3’s internal voltage regulator.
VBATT is internally regulated to 3.3 V.
Table 6. Entry and Exit Methods for Low-Power Modes
Low Power Mode
Suspend mode with
USB 3.0 PHY
Enabled (L1 mode)
Characteristics
■
The power consumption in this mode does not
exceed ISB1
■
USB 3.0 PHY is enabled and is in U3 mode
(one of the suspend modes defined by the
USB 3.0 specification). This one block alone
operates with its internal clock while all other
clocks are shut down
■
■
Methods of Entry
■
D+ transitioning to low or
high
■
D– transitioning to low or
high
■
Resume condition on
SSRX +/-
All I/Os maintain their previous state
■
Detection of VBUS
Power supply for the wakeup source and core
power must be retained. All other power
domains can be turned on/off individually
■
Assertion of GPIO[17]
■
Assertion of RESET#
■
The states of the configuration registers, buffer
memory and all internal RAM are maintained
■
All transactions must be completed before SD3
enters Suspend mode (state of outstanding
transactions are not preserved)
■
The firmware resumes operation from where it
was suspended (except when woken up by
RESET# assertion) because the program
counter does not reset
Document Number: 001-55190 Rev. *N
■
Firmware executing on the core
can put SD3 into suspend
mode. For example, on USB
suspend condition, firmware
may decide to put SD3 into
suspend mode
Methods of Exit
Page 5 of 34
CYUSB302x
Table 6. Entry and Exit Methods for Low-Power Modes (continued)
Low Power Mode
Suspend mode with
USB 3.0 PHY
disabled (L2 mode)
Standby Mode (L3
mode)
Core Power Down
Mode (L4 mode)
Characteristics
■
The power consumption in this mode does not
exceed ISB2
■
USB 3.0 PHY is disabled and the USB interface
is in suspend mode
■
The clocks are shut off. The PLLs are disabled
■
■
■
Power supply for the wakeup source and core
power must be retained. All other power
domains can be turned on/off individually
■
The states of the configuration registers, buffer
memory, and all internal RAM are maintained
■
All transactions must be completed before SD3
enters Suspend mode (state of outstanding
transactions are not preserved)
■
The firmware resumes operation from where it
was suspended (except when woken up by
RESET# assertion) because the program
counter does not reset
■
The power consumption in this mode does not
exceed ISB3
Methods of Entry
■
D+ transitioning to low or
high
■
D– transitioning to low or
high
■
Detection of VBUS
All I/Os maintain their previous state
■
Assertion of GPIO[17]
USB interface maintains the previous state
■
Assertion of RESET#
Firmware executing on the core
or external processor
configures the appropriate
register
■
Detection of VBUS
■
Assertion of GPIO[17]
■
Assertion of RESET#
Turn off VDD
■
Reapply VDD
■
Assertion of RESET#
■
All configuration register settings and
program/data RAM contents are preserved.
However, data in the buffers or other parts of
the data path, if any, is not guaranteed.
Therefore, the external processor should take
care that needed data is read before putting
SD3 into this Standby Mode
■
The program counter is reset after waking up
from Standby
■
GPIO pins maintain their configuration
■
Crystal oscillator is turned off
■
Internal PLL is turned off
■
USB transceiver is turned off
■
Core is powered down. Upon wakeup, the core
re-starts and runs the program stored in the
program/data RAM
■
Power supply for the wakeup source and core
power must be retained. All other power
domains can be turned on/off individually
■
The power consumption in this mode does not
exceed ISB4
■
Core power is turned off
■
All buffer memory, configuration registers and
the program RAM do not maintain state. It is
necessary to reload the firmware on exiting
from this mode
■
In this mode, all other power domains can be
turned on/off individually
■
■
■
Firmware executing on the core
can put SD3 into suspend
mode. For example, on USB
suspend condition, firmware
may decide to put SD3 into
suspend mode
Methods of Exit
Note: The power consumption depends on how the SD3 IOs are utilized in the application. Refer to KBA85505 to estimate the current
consumption by different power domains (VIO1–VIO5).
Document Number: 001-55190 Rev. *N
Page 6 of 34
CYUSB302x
Configuration Fuse
EMI
Fuse options are available for specific usage models. Contact
Cypress Applications/Marketing for details.
SD3 meets EMI requirements outlined by FCC 15B (USA) and
EN55022 (Europe) for consumer electronics. SD3 can tolerate
reasonable EMI, conducted by aggressor, outlined by these
specifications and continue to function as expected.
Digital I/Os
SD3 provides firmware controlled pull-up or pull-down resistors
internally on all digital I/O pins. The pins can be pulled high
through an internal 50-k resistor or can be pulled low through
an internal 10-k resistor to prevent the pins from floating. The
I/O pins may have the following states:
■
Tristated (High-Z)
■
Weak pull-up (through internal 50 k)
■
Pull down (through internal 10 k)
■
Hold (I/O hold its value) when in low power modes
All unused I/Os should be pulled high by using the internal
pull-up resistors. All unused outputs should be left floating. All
I/Os can be driven at full-strength, three-quarter strength,
half-strength, or quarter-strength. These drive strengths are
configured based on each interface.
System Level ESD
SD3 has built-in ESD protection on the D+, D–, GND pins on the
USB interface. The ESD protection levels provided on these
ports are:
■
±2.2-KV human body model (HBM) based on JESD22-A114
Specification
■
±6-KV contact discharge and ±8-KV air gap discharge based
on IEC61000-4-2 level 3A
■
±8-KV contact discharge and ±15-KV air gap discharge based
on IEC61000-4-2 level 4C.
This protection ensures the device continues to function after
ESD events up to the levels stated.
The SuperSpeed USB signals (SSRX+, SSRX-, SSTX+, SSTX-)
and S0/S1_INS have up to ±2.2 KV HBM internal ESD
protection.
Pinout
Figure 2. SD3 BGA Ball Map (Top View)
A
1
2
3
4
5
6
7
8
9
10
11
U3VSSQ
U3RXVDDQ
SSRXM
SSRXP
SSTXP
SSTXM
AV DD
VSS
DP
DM
NC
B
VIO4
FSLC[0]
R_USB3
FSLC[1]
U3TXVDDQ
CVDDQ
AV S S
VSS
VSS
V DD
TRST#
C
GPIO[54]
GPIO[55]
VDD
GPIO[57]
RESET#
XTALIN
XTALOUT
R_USB2
OTG_ID
TDO
VIO5
D
GPIO[50]
GPIO[51]
GPIO[52]
GPIO[53]
GPIO[56]
CLKIN_32
CLKIN
VSS
I2C_GPIO[58]
I2C_GPIO[59]
NC
E
GPIO[47]
VSS
S1VDDQ
GPIO[49]
GPIO[48]
FSLC[2]
TDI
TMS
VDD
V BATT
V BUS
F
S0VDDQ
GPIO[45]
GPIO[44]
GPIO[41]
GPIO[46]
TCK
GPIO[2]
GPIO[5]
GPIO[1]
GPIO[0]
VDD
G
VSS
GPIO[42]
GPIO[43]
GPIO[30]
GPIO[25]
GPIO[22]
GPIO[21]
GPIO[15]
GPIO[4]
GPIO[3]
VSS
H
VDD
GPIO[39]
GPIO[40]
GPIO[31]
GPIO[29]
GPIO[26]
GPIO[20]
GPIO[24]
GPIO[7]
GPIO[6]
S2VDDQ
J
GPIO[38]
GPIO[36]
GPIO[37]
GPIO[34]
GPIO[28]
GPIO[16]
GPIO[19]
GPIO[14]
GPIO[9]
GPIO[8]
VDD
K
GPIO[35]
GPIO[33]
VSS
VSS
GPIO[27]
GPIO[23]
GPIO[18]
GPIO[17]
GPIO[13]
GPIO[12]
GPIO[10]
L
VSS
VSS
VSS
GPIO[32]
VDD
VSS
VDD
NC
S2VDDQ
GPIO[11]
VSS
Document Number: 001-55190 Rev. *N
Page 7 of 34
CYUSB302x
Pin Description
Table 7. Pin List
Pin
No.
Power
Domain
I/O
Name
F10
VI01
I/O
GPIO[0]
GPIO
F9
VI01
I/O
GPIO[1]
GPIO
F7
VI01
I/O
GPIO[2]
GPIO
Description
S2-PORT (GPIO)
G10
VI01
I/O
GPIO[3]
GPIO
G9
VI01
I/O
GPIO[4]
GPIO
F8
VI01
I/O
GPIO[5]
GPIO
H10
VI01
I/O
GPIO[6]
GPIO
H9
VI01
I/O
GPIO[7]
GPIO
J10
VI01
I/O
GPIO[8]
GPIO
J9
VI01
I/O
GPIO[9]
GPIO
K11
VI01
I/O
GPIO[10]
GPIO
L10
VI01
I/O
GPIO[11]
GPIO
K10
VI01
I/O
GPIO[12]
GPIO
K9
VI01
I/O
GPIO[13]
GPIO
J8
VI01
I/O
GPIO[14]
GPIO
G8
VI01
I/O
GPIO[15]
GPIO
J6
VI01
I/O
GPIO[16]
GPIO
K8
VI01
I/O
GPIO[17]
GPIO
K7
VI01
I/O
GPIO[18]
GPIO
J7
VI01
I/O
GPIO[19]
GPIO
H7
VI01
I/O
GPIO[20]
GPIO
G7
VI01
I/O
GPIO[21]
GPIO
G6
VI01
I/O
GPIO[22]
GPIO
K6
VI01
I/O
GPIO[23]
GPIO
H8
VI01
I/O
GPIO[24]
GPIO
G5
VI01
I/O
GPIO[25]
GPIO
H6
VI01
I/O
GPIO[26]
GPIO
K5
VI01
I/O
GPIO[27]
GPIO
J5
VI01
I/O
GPIO[28]
GPIO
H5
VI01
I/O
GPIO[29]
GPIO
G4
VI01
I/O
GPIO[30]
PMODE[0]
H4
VI01
I/O
GPIO[31]
PMODE[1]
L4
VI01
I/O
GPIO[32]
PMODE[2]
NC
No Connect
C5
CVDDQ
I
RESET#
Active Low. Hardware Reset.
8b MMC Configuration
SD+GPIO Configuration
GPIO Configuration
K2
VI02
I/O
GPIO[33]
S0_SD0
S0_SD0
GPIO
J4
VI02
I/O
GPIO[34]
S0_SD1
S0_SD1
GPIO
K1
VI02
I/O
GPIO[35]
S0_SD2
S0_SD2
GPIO
L8
Document Number: 001-55190 Rev. *N
Page 8 of 34
CYUSB302x
Table 7. Pin List(continued)
Pin
No.
Power
Domain
I/O
Name
J2
VI02
I/O
GPIO[36]
S0_SD3
S0_SD3
GPIO
J3
VI02
I/O
GPIO[37]
S0_SD4
GPIO
GPIO
J1
VI02
I/O
GPIO[38]
S0_SD5
GPIO
GPIO
H2
VI02
I/O
GPIO[39]
S0_SD6
GPIO
GPIO
Description
H3
VI02
I/O
GPIO[40]
S0_SD7
GPIO
GPIO
F4
VI02
I/O
GPIO[41]
S0_CMD
S0_CMD
GPIO
G2
VI02
I/O
GPIO[42]
S0_CLK
S0_CLK
GPIO
G3
VI02
I/O
GPIO[43]
S0_WP
S0_WP
GPIO
F3
VI02
I/O
GPIO[44]
S0S1_INS
S0S1_INS
GPIO
F2
VI02
I/O
GPIO[45]
MMC0_RST_OUT
GPIO
GPIO
8b MMC SD + UART SD + SPI
SD +
GPIO
GPIO
GPIO +
UART +
I2S
SD + I2S
UART +
SPI + I2S
F5
VI03
I/O
GPIO[46]
S1_SD0
S1_SD0
S1_SD0
S1_SD0
GPIO
GPIO
S1_SD0
UART_
RTS
E1
VI03
I/O
GPIO[47]
S1_SD1
S1_SD1
S1_SD1
S1_SD1
GPIO
GPIO
S1_SD1
UART_
CTS
E5
VI03
I/O
GPIO[48]
S1_SD2
S1_SD2
S1_SD2
S1_SD2
GPIO
GPIO
S1_SD2
UART_TX
S1_SD3
GPIO
E4
VI03
I/O
GPIO[49]
S1_SD3
S1_SD3
S1_SD3
D1
VI03
I/O
GPIO[50]
S1_CMD
S1_CMD
S1_CMD S1_CMD GPIO
GPIO
S1_SD3 UART_RX
I2S_CLK
S1_CMD
I2S_CLK
D2
VI03
I/O
GPIO[51]
S1_CLK
S1_CLK
S1_CLK
S1_CLK
GPIO
I2S_SD
S1_CLK
I2S_SD
D3
VI03
I/O
GPIO[52]
S1_WP
S1_WP
S1_WP
S1_WP
GPIO
I2S_WS
S1_WP
I2S_WS
D4
VIO4
I/O
GPIO[53]
S1_SD4
UART_
RTS
SPI_SCK
GPIO
GPIO
UART_
RTS
GPIO
SPI_SCK
C1
VIO4
I/O
GPIO[54]
S1_SD5
UART_
CTS
SPI_SSN
GPIO
GPIO
UART_CT I2S_CLK
S
SPI_SSN
C2
VIO4
I/O
GPIO[55]
S1_SD6
UART_TX SPI_MISO
GPIO
GPIO
UART_TX
I2S_SD
SPI_MISO
D5
VIO4
I/O
GPIO[56]
S1_SD7
UART_RX SPI_MOSI
GPIO
GPIO
UART_RX
I2S_WS SPI_MOSI
I/O
MMC1_
GPIO[57] RST_OUT
GPIO
GPIO I2S_MCLK
C4
VIO4
C9
GPIO
GPIO
NC
No Connect
A3
U3RXVDDQ
I
SSRXM
USB 3.0 SuperSpeed Receive Minus
A4
U3RXVDDQ
I
SSRXP
USB 3.0 SuperSpeed Receive Plus
A6
U3TXVDDQ
O
SSTXM
USB 3.0 SuperSpeed Transmit Minus
A5
U3TXVDDQ
O
SSTXP
USB 3.0 SuperSpeed Transmit Plus
A9
VBATT/
VBUS
I/O
D+
USB (HS/FS) Data Plus
A10
VBATT/
VBUS
I/O
D-
USB (HS/FS) Data Minus
NC
No Connect
A11
B2
CVDDQ
I
FSLC[0]
FSLC[0]
C6
AVDD
I/O
XTALIN
XTALIN
C7
AVDD
I/O
XTALOUT
XTALOUT
B4
CVDDQ
I
FSLC[1]
FSLC[1]
E6
CVDDQ
I
FSLC[2]
FSLC[2]
Document Number: 001-55190 Rev. *N
I2S_
MCLK
I2S_MCLK
Page 9 of 34
CYUSB302x
Table 7. Pin List(continued)
Pin
No.
Power
Domain
I/O
D7
CVDDQ
Name
Description
I
CLKIN
CLKIN
CLKIN_32
D6
CVDDQ
I
CLKIN_3
2
D9
VIO5
I/O
I2C_
GPIO[58]
SCL (Serial Clock) for I2C Bus Interface
D10
VIO5
I/O
I2C_
GPIO[59]
SDA (Serial Data) for I2C Bus Interface
E7
VIO5
I
TDI
TDI
C10
VIO5
O
TDO
TDO
B11
VIO5
I
TRST#
TRST#
E8
VIO5
I
TMS
TMS
F6
VIO5
I
TCK
TCK
D11
VIO5
O
O[60]
GPIO
E10
PWR
VBATT
B10
PWR
VDD
A1
PWR
U3VSSQ
E11
PWR
VBUS
D8
PWR
VSS
H11
PWR
S2VDDQ
E2
PWR
VSS
L9
PWR
S2VDDQ
G1
PWR
VSS
F1
PWR
S0VDDQ
G11
PWR
VSS
E3
PWR
S1VDDQ
L1
PWR
VSS
B1
PWR
VIO4
L6
PWR
VSS
B6
PWR
CVDDQ
B5
PWR
U3TXVD
DQ
A2
PWR
U3RXVD
DQ
C11
PWR
VIO5
L11
PWR
VSS
A7
PWR
AVDD
B7
PWR
AVSS
C3
PWR
VDD
B8
PWR
VSS
E9
PWR
VDD
B9
PWR
VSS
F11
PWR
VDD
H1
PWR
VDD
L7
PWR
VDD
Document Number: 001-55190 Rev. *N
Page 10 of 34
CYUSB302x
Table 7. Pin List(continued)
Pin
No.
Power
Domain
I/O
Name
J11
PWR
VDD
L5
PWR
VDD
K4
PWR
VSS
L3
PWR
VSS
K3
PWR
VSS
L2
PWR
VSS
A8
PWR
VSS
Description
Precision Resistors
C8
VBUS/
VBATT
I/O
R_usb2 Precision resistor for USB 2.0 (Connect a 6.04 k+/-1% resistor between this pin and GND)
B3
U3TXVDDQ
I/O
R_usb3
Document Number: 001-55190 Rev. *N
Precision resistor for USB 3.0 (Connect a 200 +/-1% resistor between this pin and GND)
Page 11 of 34
CYUSB302x
Electrical Specifications
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device.
■
Additional ESD Protection levels on D+, D–, VBUS, GND pins
U-port and GPIO pins LPP-Port
■
±6-KV contact discharge, ±8-KV air gap discharge based on
IEC61000-4-2 level 3A, ±8-KV contact discharge, and ±15-KV
air gap discharge based on IEC61000-4-2 level 4C
Storage temperature ............................... –65 °C to +150 °C
Latch-up current ................................................... > 200 mA
Ambient temperature with
power supplied (Industrial) ....................... –40 °C to +85 °C
Maximum output short circuit current
for all I/O configurations. (Vout = 0 V) ................... –100 mA
Supply voltage to ground potential
VDD, AVDDQ ................................................................. 1.25 V
Operating Conditions
TA (ambient temperature under bias)
Industrial ................................................... –40 °C to +85 °C
S2VDDQ,S1VDDQ, S0VDDQ, VIO4, VIO5 ......................... 3.6 V
U3TXVDDQ, U3RXVDDQ ............................................. 1.25 V
DC input voltage to any input pin ......................... VCC + 0.3
VDD, AVDDQ, U3TXVDDQ, U3RXVDDQ
supply voltage ............................................. 1.15 V to 1.25 V
DC voltage applied to
outputs in High Z State ........................................ VCC + 0.3
VBATT supply voltage ......................................... 3.2 V to 6 V
(VCC is the corresponding I/O voltage)
S2VDDQ, S1VDDQ, S0VDDQ, VIO4, CVDDQ
supply voltage ................................................. 1.7 V to 3.6 V
Static discharge voltage ESD protection levels:
VIO5 supply voltage ....................................... 1.15 V to 3.6 V
■
±2.2-KV human body model (HBM) based on JESD22-A114
DC Specifications
Table 8. DC Specifications
Parameter
Description
Min
Max
Units
Notes
VDD
Core voltage supply
1.15
1.25
V
1.2-V typical
AVDD
Analog voltage supply
1.15
1.25
V
1.2-V typical
S0VDDQ
SD/ MMC/ CF I/O power supply
domain
1.7
3.6
V
1.8-, 2.5-, and 3.3-V typical
S1VDDQ
SD/MMC I/O power supply
domain
1.7
3.6
V
1.8-, 2.5-, and 3.3-V typical
S2VDDQ
GPIO/ CF I/O power supply
domain
1.7
3.6
V
1.8-, 2.5-, and 3.3-V typical
VIO4
GPIO/ I/O power supply domain
1.7
3.6
V
1.8-, 2.5-, and 3.3-V typical
VBATT
USB voltage supply
3.2
6
V
3.7-V typical
VBUS
USB voltage supply
4.0
6
V
5-V typical
U3TXVDDQ
USB 3.0 1.2-V supply
1.15
1.25
V
1.2-V typical. A 22-µF bypass capacitor is required
on this power supply.
U3RXVDDQ
USB 3.0 1.2-V supply
1.15
1.25
V
1.2-V typical. A 22-µF bypass capacitor is required
on this power supply.
CVDDQ
Clock voltage supply
1.7
3.6
V
1.8-, 3.3-V typical
VIO5
I2C
voltage supply
1.2
3.3
V
1.2-,1.8-, 2.5-, and 3.3-V typical
VIH1
Input HIGH voltage 1
0.625 ×
VCC
VCC + 0.3
V
For 2.0 V VCC 3.6 V (except USB port).VCC is
the corresponding I/O voltage supply.
VIH2
Input HIGH voltage 2
VCC - 0.4
VCC + 0.3
V
For 1.7 V VCC 2.0 V
(except USB port). VCC is the corresponding I/O
voltage supply.
VIL
Input LOW voltage
–0.3
0.25 × VCC
V
VCC is the corresponding I/O voltage supply.
VOH
Output HIGH voltage
0.9 × VCC
–
V
IOH (max) = –100 µA tested at quarter drive
strength. VCC is the corresponding I/O voltage
supply.
Refer to Table 9 on page 14 for values of IOH at
various drive strength and VCC.
Document Number: 001-55190 Rev. *N
Page 12 of 34
CYUSB302x
Table 8. DC Specifications(continued)
Min
Max
Units
Notes
VOL
Parameter
Output LOW voltage
Description
–
0.1 × VCC
V
IOL (min) = +100 µA tested at quarter drive strength.
VCC is the corresponding I/O voltage supply.
Refer to Table 9 on page 14 for values of IOL at
various drive strength and VCC.
IIX
Input leakage current for all pins
except
SSTXP/SSXM/SSRXP/SSRXM
–1
1
µA
All I/O signals held at VDDQ
(For I/Os that have a pull-up/down resistor
connected, the leakage current increases by
VDDQ/Rpu or VDDQ/RPD
IOZ
Output High-Z leakage current for
all pins except
SSTXP/SSXM/SSRXP/SSRXM
–1
1
µA
All I/O signals held at VDDQ
ICC Core
Core and Analog Voltage
Operating Current
–
200
mA
Total current through AVDD, VDD
ICC USB
USB voltage supply operating
current
–
60
mA
ISB1
Total suspend current during
Suspend Mode with USB 3.0
PHY enabled (L1 mode)
–
–
mA
Core current: 1.5 mA
I/O current: 20 µA
USB current: 2 mA
For typical PVT (Typical silicon, all power supplies
at their respective nominal levels at 25 C.)
ISB2
Total suspend current during
Suspend Mode with USB 3.0
PHYdisabled (L2 mode)
–
–
mA
Core current: 250 µA
I/O current: 20 µA
USB current: 1.2 mA
For typical PVT (Typical silicon, all power supplies
at their respective nominal levels at 25 C.)
ISB3
Total Standby Current during
Standby Mode (L3 mode)
–
–
µA
Core current: 60 µA
I/O current: 20 µA
USB current: 40 µA
For typical PVT (Typical silicon, all power supplies
at their respective nominal levels at 25 C.)
ISB4
Total Standby Current during
Core Power Down Mode (L4
mode)
–
–
µA
Core current: 0 µA
I/O current: 20 µA
USB current: 40 µA
For typical PVT (Typical silicon, all power supplies
at their respective nominal levels at 25 C.)
VRAMP
Voltage Ramp Rate on Core and
I/O Supplies
0.2
50
VN
Noise Level Permitted on VDD
and I/O Supplies
–
100
mV
Max p-p noise level permitted on all supplies except
AVDD
VN_AVDD
Noise Level Permitted on AVDD
Supply
–
20
mV
Max p-p noise level permitted on AVDD
Document Number: 001-55190 Rev. *N
V/ms Voltage ramp must be monotonic
Page 13 of 34
CYUSB302x
Table 9. IOH/IOL values for different drive strength and VDDIO values
VDDIO (V)
VOH (V)
VOL (V)
Drive Strength
1.7
1.53
0.17
Quarter
1.02
2.21
Half
1.51
3.28
Three-Quarters
1.83
3.85
Full
2.28
4.73
2.5
3.6
2.25
3.24
0.25
0.36
IOH max (mA)
IOL min (mA)
Quarter
5.03
3.96
Half
7.38
5.84
Three-Quarters
8.89
6.89
Full
11.07
8.61
Quarter
7.80
5.74
Half
11.36
8.64
Three-Quarters
13.64
10.15
Full
16.92
12.67
Thermal Characteristics
Table 10. Thermal Characteristics
Description
Value
Unit
125
C
Thermal resistance (junction to ambient)
34.66
C/W
Thermal resistance (junction to board)
27.03
C/W
Thermal resistance (junction to case)
13.57
C/W
Parameter
TJ MAX
JA
JB
JC
Maximum Junction Temperature
Document Number: 001-55190 Rev. *N
Page 14 of 34
CYUSB302x
AC Timing Parameters
Storage Port Timing
The S0-Port and S1-Port support the MMC Specification Version 4.4 and SD Specification Version 3.0.
Table 11 lists the timing parameters for S0-Port and S1-Port of SD3.
Table 11. S-Port Timing Parameters[2]
Parameter
Description
Min
Max
Units
MMC-20
tSDIS CMD
Host input setup time for CMD
4.8
–
ns
tSDIS DAT
Host input setup time for DAT
4.8
–
ns
tSDIH CMD
Host input hold time for CMD
4.4
–
ns
tSDIH DAT
Host input hold time for DAT
4.4
–
ns
tSDOS CMD
Host output setup time for CMD
5
–
ns
tSDOS DAT
Host output setup time for DAT
5
–
ns
tSDOH CMD
Host output hold time for CMD
5
–
ns
tSDOH DAT
Host output hold time for DAT
5
–
ns
tSCLKR
Clock rise time
–
2
ns
tSCLKF
Clock fall time
–
2
ns
tSDCK
Clock cycle time
50
–
ns
SDFREQ
Clock frequency
20
MHz
tSDCLKOD
Clock duty cycle
40
60
%
tSDIS CMD
Host input setup time for CMD
10
–
ns
tSDIS DAT
Host input setup time for DAT
10
–
ns
tSDIH CMD
Host input hold time for CMD
9
–
ns
tSDIH DAT
Host input hold time for DAT
9
–
ns
tSDOS CMD
Host output setup time for CMD
3
–
ns
tSDOS DAT
Host output setup time for DAT
3
–
ns
tSDOH CMD
Host output hold time for CMD
3
–
ns
tSDOH DAT
Host output hold time for DAT
3
–
ns
tSCLKR
Clock rise time
–
2
ns
tSCLKF
Clock fall time
–
2
ns
tSDCK
Clock cycle time
38.5
–
ns
SDFREQ
Clock frequency
tSDCLKOD
Clock duty cycle
MMC-26
26
MHz
40
60
%
MC-HS
tSDIS CMD
Host input setup time for CMD
4
–
ns
tSDIS DAT
Host input setup time for DAT
4
–
ns
tSDIH CMD
Host input hold time for CMD
3
–
ns
tSDIH DAT
Host input hold time for DAT
3
–
ns
tSDOS CMD
Host output setup time for CMD
3
–
ns
tSDOS DAT
Host output setup time for DAT
3
–
ns
Document Number: 001-55190 Rev. *N
Page 15 of 34
CYUSB302x
Table 11. S-Port Timing Parameters[2] (continued)
Min
Max
Units
tSDOH CMD
Parameter
Host output hold time for CMD
Description
3
–
ns
tSDOH DAT
Host output hold time for DAT
3
–
ns
tSCLKR
Clock rise time
–
2
ns
tSCLKF
Clock fall time
–
2
ns
tSDCK
Clock cycle time
19.2
–
ns
SDFREQ
Clock frequency
–
52
MHz
tSDCLKOD
Clock duty cycle
40
60
%
tSDIS CMD
Host input setup time for CMD
4
–
ns
tSDIS DAT
Host input setup time for DAT
0.56
–
ns
tSDIH CMD
Host input hold time for CMD
3
–
ns
tSDIH DAT
Host input hold time for DAT
2.58
–
ns
tSDOS CMD
Host output setup time for CMD
3
–
ns
tSDOS DAT
Host output setup time for DAT
2.5
–
ns
tSDOH CMD
Host output hold time for CMD
3
–
ns
tSDOH DAT
Host output hold time for DAT
2.5
–
ns
tSCLKR
Clock rise time
–
2
ns
tSCLKF
Clock fall time
–
2
ns
tSDCK
Clock cycle time
19.2
–
ns
SDFREQ
Clock frequency
tSDCLKOD
Clock duty cycle
MMC-DDR52
52
MHz
45
55
%
24
–
ns
SD-Default Speed (SDR12)
tSDIS CMD
Host input setup time for CMD
tSDIS DAT
Host input setup time for DAT
24
–
ns
tSDIH CMD
Host input hold time for CMD
2.5
–
ns
tSDIH DAT
Host input hold time for DAT
2.5
–
ns
tSDOS CMD
Host output setup time for CMD
5
–
ns
tSDOS DAT
Host output setup time for DAT
5
–
ns
tSDOH CMD
Host output hold time for CMD
5
–
ns
tSDOH DAT
Host output hold time for DAT
5
–
ns
tSCLKR
Clock rise time
–
2
ns
tSCLKF
Clock fall time
–
2
ns
tSDCK
Clock cycle time
40
–
ns
SDFREQ
Clock frequency
25
MHz
tSDCLKOD
Clock duty cycle
40
60
%
tSDIS CMD
Host input setup time for CMD
4
–
ns
tSDIS DAT
Host input setup time for DAT
4
–
ns
tSDIH CMD
Host input hold time for CMD
2.5
–
ns
tSDIH DAT
Host input hold time for DAT
2.5
–
ns
SD-High-Speed(SDR25)
Document Number: 001-55190 Rev. *N
Page 16 of 34
CYUSB302x
Table 11. S-Port Timing Parameters[2] (continued)
Min
Max
Units
tSDOS CMD
Parameter
Host output setup time for CMD
Description
6
–
ns
tSDOS DAT
Host output setup time for DAT
6
–
ns
tSDOH CMD
Host output hold time for CMD
2
–
ns
tSDOH DAT
Host output hold time for DAT
2
–
ns
tSCLKR
Clock rise time
–
2
ns
tSCLKF
Clock fall time
–
2
ns
tSDCK
Clock cycle time
20
–
ns
SDFREQ
Clock frequency
–
50
MHz
tSDCLKOD
Clock duty cycle
40
60
%
SD-SDR50
tSDIS CMD
Host input setup time for CMD
1.5
–
ns
tSDIS DAT
Host input setup time for DAT
1.5
–
ns
tSDIH CMD
Host input hold time for CMD
2.5
–
ns
tSDIH DAT
Host input hold time for DAT
2.5
–
ns
tSDOS CMD
Host output setup time for CMD
3
–
ns
tSDOS DAT
Host output setup time for DAT
3
–
ns
tSDOH CMD
Host output hold time for CMD
0.8
–
ns
tSDOH DAT
Host output hold time for DAT
0.8
–
ns
tSCLKR
Clock rise time
–
2
ns
tSCLKF
Clock fall time
–
2
ns
tSDCK
Clock cycle time
10
–
ns
SDFREQ
Clock frequency
100
MHz
tSDCLKOD
Clock duty cycle
40
60
%
tSDIS CMD
Host input setup time for CMD
4
–
ns
tSDIS DAT
Host input setup time for DAT
0.92
–
ns
tSDIH CMD
Host input hold time for CMD
2.5
–
ns
tSDIH DAT
Host input hold time for DAT
2.5
–
ns
tSDOS CMD
Host output setup time for CMD
6
–
ns
tSDOS DAT
Host output setup time for DAT
3
–
ns
tSDOH CMD
Host output hold time for CMD
0.8
–
ns
tSDOH DAT
Host output hold time for DAT
0.8
–
ns
tSCLKR
Clock rise time
–
2
ns
tSCLKF
Clock fall time
–
2
ns
tSDCK
Clock cycle time
20
–
ns
SDFREQ
Clock frequency
50
MHz
tSDCLKOD
Clock duty cycle
55
%
SD-DDR50
45
Note
2. All parameters guaranteed by design and validated through characterization.
Document Number: 001-55190 Rev. *N
Page 17 of 34
CYUSB302x
I2C Interface Timing
I2C Timing
Figure 3. I2C Timing Definition
Table 12. I2C Timing Parameters[3]
Parameter
Description
I2C
Min
Max
Units
Standard Mode Parameters
fSCL
SCL clock frequency
0
100
kHz
tHD:STA
Hold time START condition
4
–
µs
tLOW
LOW period of the SCL
4.7
–
µs
tHIGH
HIGH period of the SCL
tSU:STA
Setup time for a repeated START condition
tHD:DAT
4
–
µs
4.7
–
µs
Data hold time
0
–
µs
tSU:DAT
Data setup time
250
–
ns
tr
Rise time of both SDA and SCL signals
–
1000
ns
tf
Fall time of both SDA and SCL signals
–
300
ns
tSU:STO
Setup time for STOP condition
4
–
µs
tBUF
Bus free time between a STOP and START condition
4.7
–
µs
tVD:DAT
Data valid time
–
3.45
µs
tVD:ACK
Data valid ACK
–
3.45
µs
tSP
Pulse width of spikes that must be suppressed by input filter
n/a
n/a
Note
3. All parameters guaranteed by design and validated through characterization.
Document Number: 001-55190 Rev. *N
Page 18 of 34
CYUSB302x
Table 12. I2C Timing Parameters[3] (continued)
Parameter
Description
Min
Max
Units
0
400
kHz
I2C Fast Mode Parameters
fSCL
SCL clock frequency
tHD:STA
Hold time START condition
0.6
–
µs
tLOW
LOW period of the SCL
1.3
–
µs
tHIGH
HIGH period of the SCL
0.6
–
µs
tSU:STA
Setup time for a repeated START condition
0.6
–
µs
tHD:DAT
Data hold time
0
–
µs
tSU:DAT
Data setup time
100
–
ns
tr
Rise time of both SDA and SCL signals
–
300
ns
tf
Fall time of both SDA and SCL signals
–
300
ns
tSU:STO
Setup time for STOP condition
0.6
–
µs
tBUF
Bus-free time between a STOP and START condition
1.3
–
µs
tVD:DAT
Data valid time
–
0.9
µs
tVD:ACK
Data valid ACK
–
0.9
µs
tSP
Pulse width of spikes that must be suppressed by input filter
0
50
ns
0
1000
kHz
I2C
Fast Mode Plus Parameters (Not supported at I2C_VDDQ = 1.2V)
fSCL
SCL clock frequency
tHD:STA
Hold time START condition
0.26
–
µs
tLOW
LOW period of the SCL
0.5
–
µs
tHIGH
HIGH period of the SCL
0.26
–
µs
tSU:STA
Setup time for a repeated START condition
0.26
–
µs
tHD:DAT
Data hold time
0
–
µs
tSU:DAT
Data setup time
50
–
µs
tr
Rise time of both SDA and SCL signals
–
120
ns
tf
Fall time of both SDA and SCL signals
–
120
ns
tSU:STO
Setup time for STOP condition
0.26
–
µs
tBUF
Bus free time between a STOP and START condition
0.5
–
µs
tVD:DAT
Data valid time
–
0.45
µs
tVD:ACK
Data valid ACK
–
0.55
µs
tSP
Pulse width of spikes that must be suppressed by input filter
0
50
ns
Document Number: 001-55190 Rev. *N
Page 19 of 34
CYUSB302x
I2S Timing Diagram
Figure 4. I2S Transmit Cycle
tT
tTR
tTF
tTL
tTH
SCK
tThd
SA,
WS (output)
tTd
Table 13. I2S Timing Parameters[4]
Parameter
Description
Min
Max
Units
Ttr
–
ns
transmitter cycle LOW period
0.35 Ttr
–
ns
I2S transmitter cycle HIGH period
0.35 Ttr
–
ns
transmitter rise time
–
0.15 Ttr
ns
transmitter fall time
–
0.15 Ttr
ns
transmitter data hold time
0
–
ns
–
0.8tT
ns
tT
I2S
transmitter clock cycle
tTL
I2S
tTH
tTR
I2S
tTF
I2S
tThd
I2S
tTd
I2S transmitter delay time
Note tT is selectable through clock gears. Max Ttr is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz).
Note
4. All parameters guaranteed by design and validated through characterization.
Document Number: 001-55190 Rev. *N
Page 20 of 34
CYUSB302x
SPI Timing Specification
Figure 5. SPI Timing
SSN
(output)
tlead
SCK
(CPOL=0,
Output)
tsdi
MISO
(input)
twsck
thoi
MSB
LSB
td
tsdd
tdis
tdi
v
MOSI
(output)
tlag
trf
twsck
SCK
(CPOL=1,
Output)
tssnh
tsck
LSB
MSB
SPI Master Timing for CPHA = 0
SSN
(output)
SCK
(CPOL=0,
Output)
tssnh
tsck
tlead
twsck
trf
tlag
twsck
SCK
(CPOL=1,
Output)
tsdi
MISO
(input)
thoi
LSB
tdis
tdi
tdv
MOSI
(output)
MSB
LSB
MSB
SPI Master Timing for CPHA = 1
Document Number: 001-55190 Rev. *N
Page 21 of 34
CYUSB302x
Table 14. SPI Timing Parameters[5]
Parameter
Description
fop
Operating frequency
tsck
Cycle time
twsck
Clock high/low time
tlead
SSN-SCK lead time
tlag
Enable lag time
trf
tsdd
Min
Max
Units
0
33
MHz
30
–
ns
13.5
–
[6 ]
1/2 tsck
-5
ns
[6]
ns
[6]
1.5 tsck + 5
0.5
1.5 tsck +5
ns
Rise/fall time
–
8
ns
Output SSN to valid data delay time
–
5
ns
tdv
Output data valid time
–
5
ns
tdi
Output data invalid
0
–
ns
tssnh
Minimum SSN high time
10
–
ns
tsdi
Data setup time input
8
–
ns
thoi
Data hold time input
0
–
ns
tdis
Disable data output on SSN high
0
–
ns
Notes
5. All parameters guaranteed by design and validated through characterization.
6. Depends on LAG and LEAD setting in the SPI_CONFIG register.
Document Number: 001-55190 Rev. *N
Page 22 of 34
CYUSB302x
Reset Sequence
Table 15 provides the hard reset sequence requirements for SD3.
Table 15. Reset and Standby Timing Parameters
Parameter
tRPW
Definition
Minimum RESET# pulse width
tRH
Minimum high on RESET#
tRR
Reset Recovery Time (after which Boot loader begins
firmware download)
tSBY
Time to enter Standby/Suspend (from the time
MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set)
tWU
Time to wakeup from standby
tWH
Conditions
Min (ms)
Max (ms)
Clock Input
1
–
Crystal Input
1
–
–
5
–
–
Clock Input
1
Crystal Input
5
–
–
1
Clock Input
1
–
Crystal Input
5
–
–
5
–
Minimum time before Standby/Suspend source may be
reasserted
Figure 6. Reset Sequence
VDD
( core )
xVDDQ
XTALIN/
CLKIN
XTALIN/ CLKIN must be stable
before exiting Standby/Suspend
Mandatory
Reset Pulse
tRh
tRR
Hard Reset
RESET #
tWH
tRPW
Standby/
Suspend
Source
tSBY
Standby/Suspend source Is asserted
(MAIN_POWER_EN/ MAIN_CLK_EN bit
is set)
Document Number: 001-55190 Rev. *N
tWU
Standby/Suspend
source Is deasserted
Page 23 of 34
CYUSB302x
Package Diagrams
Figure 7. 121-ball FBGA (10 × 10 × 1.20 mm) Package Outline, 001-54471
2X
0.10 C
E1
E
B
A
11 10
9
8
7
6
5
(datum B)
4 3 2
A1 CORNER
1
7
A1 CORNER
A
B
C
D
6
E
SD
D1
F
D
(datum A)
G
H
J
K
eD
0.10 C 2X
L
6
eE
SE
TOP VIEW
BOTTOM VIEW
0.20 C
DETAIL A
A1
0.08 C
C
121XØb
5
A
Ø0.15 M C A B
Ø0.08 M C
SIDE VIEW
DETAIL A
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
MIN.
NOM.
MAX.
A
-
-
1.20
A1
0.15
-
-
D
10.00 BSC
E
10.00 BSC
D1
8.00 BSC
E1
8.00 BSC
MD
11
ME
11
N
121
b
0.30
0.25
eD
0.80 BSC
eE
0.80 BSC
SD
SE
0.00
0.00
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
0.35
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
001-54471 *F
Document Number: 001-55190 Rev. *N
Page 24 of 34
CYUSB302x
Ordering Information
Table 16. Ordering Information
Ordering Code
CYUSB3025-BZXI
SD/eMMC SDIO Ports
SRAM (KB)
2
512
Package Type
121-ball BGA
Ordering Code Definitions
CY USB
3 XXX
- BZ X
I
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range:
I = Industrial
Pb-free
Package Type:
BZ = 121-ball BGA
Marketing Part Number
Base Part Number for USB 3.0
Marketing Code: USB = USB Controller
Company ID: CY = Cypress
Document Number: 001-55190 Rev. *N
Page 25 of 34
CYUSB302x
Acronyms
Document Conventions
Table 17. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 18. Units of Measure
BGA
ball grid array
MMC
multimedia card
°C
degree Celsius
PLL
phase locked loop
MBps
Megabytes per second
SD
secure digital
MHz
mega hertz
SDIO
secure digital input / output
µA
microamperes
SLC
single-level cell
µs
microseconds
USB
universal serial bus
Document Number: 001-55190 Rev. *N
Symbol
Unit of Measure
mA
milliamperes
ms
milliseconds
ns
nanoseconds
ohms
pF
pico Farad
V
volts
Page 26 of 34
CYUSB302x
Errata
This section describes the errata for the SD3 CYUSB3025-BZXI. Details include errata trigger conditions, scope of impact, available
workarounds, and silicon revision applicability. Compare this document to the device’s datasheet for a complete functional description.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Part Number
Device Characteristics
CYUSB3025-BZXI
All Variants
SD3 USB and Mass Storage Peripheral Controller Qualification Status
Product Status: Sampling
SD3 USB and Mass Storage Peripheral Controller Errata Summary
The following table defines the errata applicability to available SD3 USB and Mass Storage Peripheral Controller family devices.
Part Number
Silicon Revision
1. Turning off VIO1 during Normal, Suspend, and Standby
modes causes the SD3 to stop working.
Items
CYUSB3025-BZXI
All
Workaround provided
Fix Status
2. USB enumeration failure in USB boot mode when SD3 is
self-powered.
CYUSB3025-BZXI
All
Workaround provided
3. Bus collision is seen when the I2C block is used as a master
in the I2C Multi-master configuration.
CYUSB3025-BZXI
All
Use SD3 in single-master
configuration
4. Low Power U1 Fast-Exit Issue with USB3.0 host controller. CYUSB3025-BZXI
All
Workaround provided
5. USB data corruption when operating on hosts with poor link
quality.
CYUSB3025-BZXI
All
Workaround provided
6. Device treats Rx Detect sequence from the USB 3.0 host
as a valid U1 exit LFPS burst.
CYUSB3025-BZXI
All
Workaround provided
7. I2C Data Valid (tVD:DAT) specification violation at 400 kHz
with a 40/60 duty cycle.
CYUSB3025-BZXI
All
No workaround needed
8. SD3 Device does not respond correctly to Port Capability
Request from Host after multiple power cycles.
CYUSB3025-BZXI
All
Workaround provided
1. Turning off VIO1 during Normal, Suspend, and Standby modes causes the SD3 to stop working.
■Problem
Definition
Turning off the VIO1 during Normal, Suspend, and Standby modes will cause the SD3 to stop working.
■Parameters
N/A
Affected
■Trigger
Conditions
This condition is triggered when the VIO1 is turned off during Normal, Suspend, and Standby modes.
■Scope
Of Impact
SD3 stops working.
■Workaround
VIO1 must stay on during Normal, Suspend, and Standby modes.
■Fix
Status
No fix. Workaround is required.
Document Number: 001-55190 Rev. *N
Page 27 of 34
CYUSB302x
2. USB enumeration failure in USB boot mode when SD3 is self-powered.
■Problem
Definition
When SD3 is self-powered and not connected to the USB host, it enters low-power mode and does not wake up when connected
to USB host afterwards. This is because the bootloader does not check the VBUS pin on the connector to detect USB connection.
It expects that the USB bus is connected to the host when it is powered on.
■Parameters
N/A
Affected
■Trigger
Conditions
This condition is triggered when SD3 is self-powered in USB boot mode.
■Scope
Of Impact
Device does not enumerate.
■Workaround
Reset the device after connecting to USB host.
■Fix
Status
No fix. Workaround is required.
3. Bus collision is seen when the I2C block is used as a master in the I2C Multi-master configuration.
■Problem
Definition
When SD3 is used as a master in the I2C multi-master configuration, there can be occasional bus collisions.
■Parameters
NA
Affected
■Trigger
Conditions
This condition is triggered only when the SD3 I2C block operates in Multi-master configuration.
■Scope
Of Impact
The SD3 I2C block can transmit data when the I2C bus is not idle leading to bus collision.
■Workaround
Use SD3 as a single master.
■Fix
Status
No fix.
4. Low Power U1 Fast-Exit Issue with USB3.0 host controller.
■Problem
Definition
When SD3 device transitions from Low power U1 state to U0 state within 5 µs after entering U1 state, the device sometimes fails
to transition back to U0 state, resulting in USB Reset.
■Parameters
NA
Affected
■Trigger
Conditions
This condition is triggered during low power transition mode.
■Scope
Of Impact
Unexpected USB warm reset during data transfer.
■Workaround
This problem can be worked around in the FW by disabling LPM (Link Power Management) during data transfer.
■Fix
Status
FW workaround is proven and reliable.
Document Number: 001-55190 Rev. *N
Page 28 of 34
CYUSB302x
5. USB data corruption when operating on hosts with poor link quality.
■Problem
Definition
If SD3 is operating on a USB 3.0 link with poor signal quality, the device could send corrupted data on any of the IN endpoints
(including the control endpoint).
■Parameters
NA
Affected
■Trigger
Conditions
This condition is triggered when the USB3.0 link signal quality is very poor.
■Scope
Of Impact
Data corruption in any of the IN endpoints (including the control endpoint).
■Workaround
The application firmware should perform an error recovery by stalling the endpoint on receiving CYU3P_USBEPSS_RESET_EVT
event, and then stop and restart DMA path when the CLEAR_FEATURE request is received.
Note: SDK versions 1.3.3 and above internally manages the DMA transfers and performs the endpoint reset when potential error
conditions are seen. For more details in application firmware, please refer to GpiftoUsb example available with SDK.
■Fix
Status
FW Work-around is proven and reliable.
6. Device treats Rx Detect sequence from the USB 3.0 host as a valid U1 exit LFPS burst.
■Problem
Definition
The USB 3.0 PHY in the SD3 device uses an electrical idle detector to determine whether LFPS is being received. The duration
for which the receiver does not see an electrical idle condition is timed to detect various LFPS bursts. This implementation causes
the device to treat an Rx Detect sequence from the USB host as a valid U1 exit LFPS burst.
■Parameters
NA
Affected
■Trigger
Conditions
This condition is triggered when the USB host is initiating an Rx Detect sequence while the USB 3.0 Link State Machine on the
SD3 is in the U1 state. Since the host will only perform Rx Detect sequence in the RX Detect and U2 states, the error condition
is seen only in cases where the USB link on the host has moved into the U2 state while the link on SD3 is in the U1 state.
■Scope
Of Impact
SD3 moves into Recovery prematurely leading to a Recovery failure followed by Warm Reset and USB re-enumeration. This
sequence can repeat multiple times resulting in data transfer failures.
■Workaround
SD3 can be configured to transition from U1 to U2 a few microseconds before the host does so. This will ensure that the link will
be in U2 on the device side before the host attempts any Rx Detect sequence; thereby preventing a false detection of U1 exit.
■Fix
Status
Workaround is implemented in FX3 SDK library 1.3.4 and above.
Document Number: 001-55190 Rev. *N
Page 29 of 34
CYUSB302x
7. I2C Data Valid (tVD:DAT) specification violation at 400 kHz with a 40/60 duty cycle.
■Problem
2
Definition
I C Data Valid (tVD:DAT) parameter at 400 kHz with a 40/60 duty cycle is 1.0625 µs, which exceeds the I2C specification limit of
0.9 µs.
■Parameters
N/A
Affected
■Trigger
Conditions
This violation occurs only at 400 kHz with a 40/60 duty cycle of the I2C clock.
■Scope
Of Impact
Setup time (tSUDAT) is met with a huge margin for the transmitted data for 400 kHz and so tvd:DAT violation will not cause any data
integrity issues.
■Workaround
No workaround needed.
■Fix
Status
No fix needed.
8. SD3 Device does not respond correctly to Port Capability Request from Host after multiple power cycles.
■Problem
Definition
During multiple power cycles, sometimes the SD3 device does not respond correctly to the Port Capability request (Link Packet)
from the USB Controller. In view of this, SD3 does not get the subsequent Port Configuration request from the USB controller,
resulting in SS.Disabled state. The device fails to recover from this state and finally results in enumeration failure.
■Parameters
N/A
Affected
■Trigger
Conditions
This condition is triggered when the SD3 provides an incorrect response to the Port Capability request from the host.
■Scope
Of Impact
Device fails to enumerate after multiple retries.
■Workaround
Since the host does not send the Port Configuration request to the SD3 device, it causes a Port Configuration request timeout
interrupt to be triggered in the device. This interrupt is handled in the FX3 SDK 1.3.4 onwards to generate and signal CY_U3P_USB_EVENT_LMP_EXCH_FAIL event to the application. This event should be handled in the user application such that it does a
USB Interface Block Restart. Refer the Knowledge Base Article (KBA225778) for more details and the firmware workaround
example project.
■Fix
Status
Suggested firmware work-around is proven and reliable.
Document Number: 001-55190 Rev. *N
Page 30 of 34
CYUSB302x
Document History Page
Document Title: CYUSB302x, SD3™ USB and Mass Storage Peripheral Controller
Document Number: 001-55190
Revision
ECN
Orig. of
Change
Submission
Date
**
2761891
VSO
09/10/2009
New data sheet.
*A
2823531
OSG
12/08/2009
Added data sheet to the USB 3.0 EROS spec 001-51884.
No technical updates.
*B
3080927
OSG
11/08/2010
Changed status from Advance to Preliminary.
Updated Logic Block Diagram.
Updated Power:
Added Power Modes.
Added Configuration Fuse.
Added Digital I/Os.
Added EMI.
Added System Level ESD.
Updated Pin Description:
Updated Table 7.
Added AC Timing Parameters.
Added Absolute Maximum Ratings.
Added DC Specifications
Added Reset Sequence.
Added Package Diagrams.
Added Ordering Information.
Description of Change
*C
3204393
OSG
03/23/2011
Added a reference to footnote 1 in Table 1.
*D
3217917
OSG
04/06/2011
Changed values of R_USB2 and R_USB3
*E
3369042
OSG
12/06/2011
Changed status from Preliminary to Final.
Updated tRR and tRPW for crystal input
Added clarification regarding IOZ and IIX
Updated 121-ball FBGA package diagram
Added clarification regarding VCC in DC Specifications table
In Power Modes description, stated that S2VDDQ cannot be turned off at any
time if the S2-port is used in the application
Updated Absolute Maximum Ratings
Added requirement for by-pass capacitor on U3RXVDDQ and U3TXVDDQ
Updated I2C interface tVD:ACK parameter for 1 MHz operation.
*F
3649782
OSG
08/16/2012
Added note about the I2C controller support for clock stretching.
Updated Clocking and Hard Reset sections.
Modified VBUS min value.
Updated Rise/fall time max value.
*G
3848148
OSG
12/20/2012
Updated Package Diagrams:
spec 001-54471 – Changed revision from *C to *D.
*H
4016006
GSZ
06/04/2013
Updated Features.
Updated Applications.
Updated Logic Block Diagram.
Updated Functional Overview.
Updated Pin Description.
Added “Pinout for WLCSP”.
Added “Pin Description for WLCSP”.
Updated AC Timing Parameters.
Updated Package Diagrams:
Added spec 001-62221 Rev. *B.
Updated Ordering Information:
Updated part numbers.
Document Number: 001-55190 Rev. *N
Page 31 of 34
CYUSB302x
Document History Page(continued)
Document Title: CYUSB302x, SD3™ USB and Mass Storage Peripheral Controller
Document Number: 001-55190
Revision
ECN
Orig. of
Change
Submission
Date
*I
4131901
GSZ
09/23/2013
Removed “Company Confidential” in all instances across the document.
Updated Package Diagrams:
spec 001-62221 – Changed revision from *B to *C.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
Completing Sunset Review.
*J
5460202
RAJV
10/14/2016
Updated Package Diagrams:
spec 001-54471 – Changed revision from *D to *E.
Added Errata.
Updated to new template.
*K
5765169
AESATMP9
06/06/2017
Updated logo and copyright.
*L
5774759
GAYA
06/15/2017
Updated Errata:
Updated entire section.
Updated to new template.
*M
6328108
HPPC
10/01/2018
Removed 131-ball WLCSP package related information in all instances across
the document.
Updated Features:
Updated description.
Updated Functional Overview:
Updated I2S Interface:
Updated description.
Updated Boot Options:
Updated description.
Updated Power:
Updated description.
Updated Power Modes:
Updated description.
Updated Table 6.
Updated Pinout:
Updated Figure 2.
Updated Pin Description:
Updated Table 7.
Updated Electrical Specifications:
Updated DC Specifications:
Updated Table 8.
Added Table 9.
Added Thermal Characteristics.
Updated Package Diagrams:
spec 001-54471 – Changed revision from *E to *F.
Removed spec 001-62221 Rev. *C.
Updated Ordering Information:
Updated part numbers.
Document Number: 001-55190 Rev. *N
Description of Change
Page 32 of 34
CYUSB302x
Document History Page(continued)
Document Title: CYUSB302x, SD3™ USB and Mass Storage Peripheral Controller
Document Number: 001-55190
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
*M (cont.)
6328108
HPPC
10/01/2018
Updated Errata:
Updated description.
Updated Part Numbers Affected:
Updated table.
Updated SD3 USB and Mass Storage Peripheral Controller Errata Summary:
Updated description.
Updated details in “Silicon Revision” column for all items in the table.
Added items “Low Power U1 Fast-Exit Issue with USB3.0 host controller.”,
“USB data corruption when operating on hosts with poor link quality.”, “Device
treats Rx Detect sequence from the USB 3.0 host as a valid U1 exit LFPS
burst.”, “I2C Data Valid (tVD:DAT) specification violation at 400 kHz with a 40/60
duty cycle.” and their corresponding details in the table.
Updated to new template.
Completing Sunset Review.
*N
6411365
HPPC
12/14/2018
Updated Pin Description:
Updated Table 7.
Updated Errata:
Updated SD3 USB and Mass Storage Peripheral Controller Errata Summary:
Updated description.
Added item “SD3 Device does not respond correctly to Port Capability Request
from Host after multiple power cycles.” and its corresponding details in the
table.
Document Number: 001-55190 Rev. *N
Page 33 of 34
CYUSB302x
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Document Number: 001-55190 Rev. *N
Revised December 14, 2018
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