CYUSB3064-BZXI

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CYUSB306X EZ-USB® CX3: MIPI CSI-2 to SuperSpeed USB Bridge Controller EZ-USB® CX3: MIPI CSI-2 to SuperSpeed USB Bridge Controller Features ■ ■ ■ Applications Universal Serial Bus (USB) integration ❐ USB 3.0 and USB 2.0 peripherals, compliant with USB 3.0 specification 1.0 ❐ 5-Gbps USB 3.0 PHY compliant with PIPE 3.0 ❐ Thirty-two physical endpoints MIPI CSI-2 RX interface nd ❐ MIPI CSI-2 compliant (Version 1.01, Revision 0.04 – 2 April 2009) ❐ Supports up to four data lanes (CYUSB3065 supports up to four lanes; CYUSB3064 supports up to two lanes) ❐ Each lane supports up to 1 Gbps (CYUSB3065 supports up to four lanes; CYUSB3064 supports up to two lanes) ❐ CCI interface for image sensor configuration Supports the following video data formats: ❐ User-defined 8-bit ❐ RAW8/10/12/14 ❐ YUV422 (CCIR/ITU 8/10bit), YUV444 ❐ RGB888/666/565 ■ Fully accessible 32-bit CPU ❐ ARM926EJ-S core with 200-MHz operation ❐ 512-KB or 256-KB embedded SRAM ■ Additional connectivity to the following peripherals: 2 ❐ I C master controller at 1 MHz 2 ❐ I S master (transmitter only) at sampling frequencies of 8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, and 192 kHz ❐ UART support of up to 4 Mbps ❐ SPI master at 33 MHz ■ Twelve GPIOs ■ Ultra-low-power in core power-down mode ■ Independent power domains for core and I/O ❐ Core operation at 1.2 V 2 ❐ I S, UART, and SPI operation at 1.8 to 3.3 V 2 ❐ I C, I/O operation at 1.8 to 3.3 V ■ 10 × 10 mm, 0.8-mm pitch Pb-free ball grid array (BGA) package ■ ■ Digital video cameras ■ Digital still cameras ■ Webcams ■ Scanners ■ Video conference systems ■ Gesture-based control ■ Surveillance cameras ■ Medical imaging devices ■ Video IP phones ■ USB microscopes ■ Industrial cameras EZ-USB® software development kit (SDK) for easy code development Cypress Semiconductor Corporation Document Number: 001-87516 Rev. *O • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 2, 2021 CYUSB306X TMS TCK TRST TDI TD0 Logic Block Diagram JTAG CPU ARM926EJ-S SSRXCP / CM SSRX+ SS D0P / D0M 32 EPs MIPI CSI-2 RX interface D1P / D1M Peripheral HS/FS D2P / D2M Peripheral D3P / D3M USB Port SSTXSSTX+ D+ D- MCLK XRST XSHUTDOWN Program RAM RESET# CLKIN CLKIN_32 Document Number: 001-87516 Rev. *O SPI UART TX RX CTS RTS I2S MISO MOSI SSN SCK I2C_SDA I2C_SCL I2C I2S_CLK I2S_SD I2S_WS I2S_MCLK REFCLK Page 2 of 40 CYUSB306X More Information ■ Knowledge Base Articles: ❐ CX3 Firmware: Frequently Asked Questions - KBA91297 ❐ CX3 Hardware: Frequently Asked Questions - KBA91295 ❐ CX3 Application Software / USB Driver: Frequently Asked Questions - KBA91298 ❐ Knowledge Base - Cypress Semiconductor Cage Code KBA89258 ■ Development Kits: ❐ Ascella - Cypress® CX3™ THine® ISP 13MP reference design kit (RDK) ❐ Denebola - USB 3.0 UVC Reference Design Kit (RDK) ❐ Tania - Cypress CX3™ Socionext® ISP reference design kit (RDK) with Dual Sony Sensors ■ Models: ❐ CX3 Device OrCad Schematic Symbol ❐ CYUSB306x - IBIS Cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources refer to the cypress web page for CX3 at www.cypress.com/CX3. ■ Overview: USB Portfolio, USB Roadmap ■ USB 3.0 Product Selectors: FX3, FX3S, CX3, GX3, HX3 ■ Application notes: Cypress offers a large number of USB application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with CX3 are: ❐ AN75705 - Getting Started with EZ-USB FX3 ❐ AN90369 - How to Interface a MIPI CSI-2 Image Sensor With EZ-USB® CX3 ❐ AN75779 - How to Implement an Image Sensor Interface with EZ-USB® FX3™ in a USB Video Class (UVC) Framework ❐ AN76405 - EZ-USB FX3 Boot Options ❐ AN70707 - EZ-USB FX3/FX3S Hardware Design Guidelines and Schematic Checklist ❐ AN86947 - Optimizing USB 3.0 Throughput with EZ-USB FX3 ■ Code Examples: ❐ USB SuperSpeed ■ Technical Reference Manual (TRM): ❐ EZ-USB® CX3 Technical Reference Manual Document Number: 001-87516 Rev. *O EZ-USB Software Development Kit Cypress delivers the complete firmware stack for CX3, in order to easily integrate SuperSpeed USB into any embedded MIPI image sensor application. The Software Development Kit (FX3 SDK) comes with tools, drivers and application examples, which help accelerate application development. The FX3 SDK Setup includes CX3 APIs and example firmware for OmniVision OV5640 and Aptina AS0260 image sensor interface. The eclipse plugin for the FX3 SDK accelerates CX3 firmware development for any other image sensor. Page 3 of 40 CYUSB306X Contents Functional Overview ........................................................ 5 Application Examples ...................................................... 5 USB Interface .................................................................... 6 ReNumeration ............................................................. 6 VBUS Overvoltage Protection ..................................... 6 MIPI CSI-2 RX Interface .................................................... 7 Additional Outputs ....................................................... 7 CPU .................................................................................... 7 JTAG Interface .................................................................. 7 Other Interfaces ................................................................ 7 UART Interface ............................................................ 7 I2C Interface ................................................................ 7 I2S Interface ................................................................ 8 SPI Interface ................................................................ 8 Boot Options ..................................................................... 8 Reset .................................................................................. 8 Hard Reset .................................................................. 8 Soft Reset .................................................................... 8 Clocking ............................................................................ 9 32-kHz Watchdog Timer Clock Input ........................... 9 Power ............................................................................... 10 Power Modes ............................................................ 10 Configuration Options ................................................... 13 Digital I/Os ....................................................................... 13 GPIOs ............................................................................... 13 EMI ................................................................................... 13 System-level ESD ........................................................... 13 Pin Configuration ........................................................... 14 Pin Description ............................................................... 15 Electrical Specifications ................................................ 17 Absolute Maximum Ratings ....................................... 17 Document Number: 001-87516 Rev. *O Operating Conditions ................................................. 17 DC Specifications ...................................................... 17 MIPI D-PHY Electrical Characteristics ...................... 19 Thermal Characteristics ................................................. 19 AC Timing Parameters ................................................... 20 MIPI Data to Clock Timing Reference ....................... 20 Reference Clock Specifications ................................. 20 MIPI CSI Signal Low Power AC Characteristics ......................................... 21 AC Specifications ...................................................... 21 Serial Peripherals Timing .......................................... 22 Reset Sequence .............................................................. 27 Ordering Information ...................................................... 28 Ordering Code Definitions ......................................... 28 Package Diagram ............................................................ 29 Acronyms ........................................................................ 30 Document Conventions ................................................. 30 Units of Measure ....................................................... 30 Errata ............................................................................... 31 Part Numbers Affected .............................................. 31 Qualification Status ................................................... 31 Errata Summary ........................................................ 31 Document History Page ................................................. 37 Sales, Solutions, and Legal Information ...................... 40 Worldwide Sales and Design Support ....................... 40 Products .................................................................... 40 PSoC® Solutions ...................................................... 40 Cypress Developer Community ................................. 40 Technical Support ..................................................... 40 Page 4 of 40 CYUSB306X Functional Overview CX3 comes with application development tools. The software development kit comes with application examples for accelerating time-to-market. Cypress’s EZ-USB CX3 is the next-generation bridge controller that can connect devices with the Mobile Industry Processor Interface – Camera Serial Interface 2 (MIPI CSI-2) interface to any USB 3.0 Host. CX3 complies with the USB 3.0 v1.0 specification and is also backward compatible with USB 2.0. It also complies with the MIPI CSI-2 v1.01, revision 0.04 specification dated 2nd April 2009. CX3 has a 4-lane CSI-2 receiver with up to 1 Gbps on each lane. It supports video data formats such as RAW8/10/12/14, YUV422 (CCIR/ITU 8/10-bit), RGB888/666/565, and user-defined 8-bit. Application Examples CX3 has integrated the USB 3.0 and USB 2.0 physical layers (PHYs) along with a 32-bit ARM926EJ-S microprocessor for powerful data processing and for building custom applications. In a typical application (see Figure 1), CX3 acts as the main processor and connects to an image sensor, an audio device, or camera control devices amongst others. CX3 contains 512 KB of on-chip SRAM (see Ordering Information on page 28) for code and data. EZ-USB CX3 also provides interfaces to connect to serial peripherals such as UART, SPI, I2C, and I2S. Figure 1. EZ-USB CX3 Example Application Clock 6-40 MHz Clock 19.2 MHz REFCLK CLKIN Power subsystem VDD MIPI CSI-2 RX EZ-USB CX3 Image sensor I2C Autofocus, Pan, Tilt, Zoom, Shutter control, Lighting, etc. Document Number: 001-87516 Rev. *O U S B I2S Audio output USB Host SPI Audio input Page 5 of 40 CYUSB306X USB Interface VBUS Overvoltage Protection ■ Supports USB peripheral functionality compliant with USB 3.0 Specification, Revision 1.0, and is also backward compatible with the USB 2.0 Specification. The maximum input voltage on CX3's VUSB pin is 6 V. A charger can supply up to 9 V on VUSB. In this case, an external overvoltage protection (OVP) device is required to protect CX3 from damage on VUSB. Figure 3 shows the system application diagram with an OVP device connected on VUSB. Refer to DC Specifications on page 17 for the operating range of VUSB. ■ As a peripheral, CX3 is capable of SuperSpeed, High-Speed, and Full-Speed. Note: The VBUS pin of the USB connector should be connected to the VUSB pin of CX3. ■ Supports up to 16 IN and 16 OUT endpoints Figure 3. System Diagram with OVP Device For VUSB ■ Supports the USB 3.0 Streams feature ■ As a USB peripheral, CX3 supports USB-attached storage (UAS), USB Video Class (UVC), and Media Transfer Protocol (MTP) USB peripheral classes. As a USB peripheral, all other device classes are supported only in pass-through mode when handled entirely by a host processor external to the device. Figure 2. USB Interface Signals 1 OVP device USB Connector USB Interface 2 SSRXSSRX+ SSTXSSTX+ DD+ AVDD VDD CVDDQ VDDIO3 VDDIO2 VDDIO1 EZ-USB CX3 EZ-USB CX3 VUSB U3TXVDDQ U3RXVDDQ POWER SUBSYSTEM SSRXSSRX+ SSTXSSTX+ DD+ 3 4 5 6 7 8 9 VUSB USB-Port CX3 complies with the following specifications and supports the following features: GND ReNumeration Because of CX3’s soft configuration, one chip can take on the identities of multiple distinct USB devices. When first plugged into USB, CX3 enumerates automatically with the Cypress Vendor ID (0x04B4) and downloads the firmware and USB descriptors over the USB interface. The downloaded firmware executes an electrical disconnect and connect. CX3 enumerates again, this time as a device defined by the downloaded information. This patented two-step process, called ReNumeration, happens instantly when the device is plugged in. Document Number: 001-87516 Rev. *O Page 6 of 40 CYUSB306X MIPI CSI-2 RX Interface The Mobile Industry Processor Interface (MIPI) association defined the Camera Serial Interface 2 (CSI-2) standard to enable image data to be sent on high-bandwidth serial lines. CX3 implements a MIPI CSI-2 Receiver with the following features: 1. It can receive clock and data in 1, 2, 3, or 4 lanes. (CYUSB3065 part supports up to four lanes; CYUSB3064 part supports up to two lanes) 2. Up to 1 Gbps of data on each CSI lane is supported (total maximum bandwidth should not exceed 2.4 Gbps). 3. Video formats such as RAW8/10/12/14, YUV422 (CCIR/ITU 8/10-bit), RGB888/666/565, and User-Defined 8-bit are supported 4. A CCI interface (compatible with 100-kHz or 400-kHz I2C interface with 7-bit addressing) is provided to configure the sensor. 5. GPIOs are available for synchronization of external flash or lighting system with image sensors to illuminate the scene that improves the image quality by improving Signal to noise ratio. 6. GPIOs can also be used to synchronize the image sensor with external events, so that image can be captured based on external event. 7. Serial interfaces (such as I2C, I2S, SPI, UART) are available to implement camera functions such as Auto focus and Pan, Tilt, Zoom (PTZ) Additional Outputs In addition to the standard MIPI CSI-2 signals, the following three additional outputs are provided: 1. XRST: this can be used to reset the image sensor 2. XSHUTDOWN: this pin can be used to put the sensor to a standby/shutdown mode 3. MCLK: this pin can provide the clock output. It can be used only for testing the image sensor. For production, use an external clock generator as clock input for image sensors. CPU CX3 has an on-chip 32-bit, 200-MHz ARM926EJ-S core CPU. The core has direct access to 16 kB of Instruction Tightly Coupled Memory (TCM) and 8 kB of data TCM. The ARM926EJ-S core provides a JTAG interface for firmware debugging. CX3 offers the following advantages: ■ ■ ■ Integrates 512 KB of embedded SRAM for code and data and 8 kB of instruction cache and data cache. Implements efficient and flexible DMA connectivity between the various peripherals (such as, USB, CSI-2 Rx, I2S, SPI, and UART), requiring firmware only to configure data accesses between peripherals, which are then managed by the DMA fabric. Allows easy application development on industry-standard development tools for ARM926EJ-S. Document Number: 001-87516 Rev. *O Examples of the CX3 firmware are available with the Cypress EZ-USB CX3 Development Kit. Software APIs that can be ported to an external processor are available with the Cypress EZ-USB CX3 Software Development Kit. JTAG Interface CX3’s JTAG interface has a standard five-pin interface to connect to a JTAG debugger in order to debug firmware through the CPU-core's on-chip-debug circuitry. Industry-standard debugging tools for the ARM926EJ-S core can be used for the CX3 application development. Other Interfaces CX3 supports the following serial peripherals: ■ UART ■ I2C ■ I2S ■ SPI The CYUSB306X Pin List on page 15 shows the details of how these interfaces are mapped. UART Interface The UART interface of CX3 supports full-duplex communication. It includes the signals noted in Table 1. Table 1. UART Interface Signals Signal Description TX Output signal RX Input signal CTS Flow control RTS Flow control The UART is capable of generating a range of baud rates, from 300 bps to 4608 Kbps, selectable by the firmware. If flow control is enabled, then CX3's UART only transmits data when the CTS input is asserted. In addition to this, CX3's UART asserts the RTS output signal, when it is ready to receive data. I2C Interface CX3’s I2C interface is compatible with the I2C Bus Specification Revision 3. This I2C interface is capable of operating only as I2C master; therefore, it may be used to communicate with other I2C slave devices. For example, CX3 may boot from an EEPROM connected to the I2C interface, as a selectable boot option. CX3’s I2C Master Controller also supports multi-master mode functionality. The power supply for the I2C interface is VDDIO1, which is a separate power domain from the other serial peripherals. This gives the I2C interface the flexibility to operate at a different voltage than the other serial interfaces. The I2C controller supports bus frequencies of 400 kHz, and 1 MHz. When VDDIO1 is 1.8 V, 2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz and 1 MHz. The I2C Page 7 of 40 CYUSB306X controller supports the clock-stretching feature to enable slower devices to exercise flow control. Boot Options The I2C interface’s SCL and SDA signals require external pull-up resistors. The pull-up resistors must be connected to VDDIO1. CX3 can load boot images from various sources, selected by the configuration of the PMODE pins. Following are the CX3 boot options: Note: I2C addresses with the pattern 0x0000111x are used internally and no slave devices with those addresses should be connected to the bus. I 2S Interface CX3 has an I2S port to support external audio codec devices. CX3 functions as I2S Master as transmitter only. The I2S interface consists of four signals: clock line (I2S_CLK), serial data line (I2S_SD), word select line (I2S_WS), and master system clock (I2S_MCLK). CX3 can generate the system clock as an output on I2S_MCLK or accept an external system clock input on I2S_MCLK. ■ Boot from USB ■ Boot from I2C ■ Boot from SPI ❐ Cypress SPI flash parts supported are S25FS064S (64-Mbit), S25FS128S (128-Mbit) and S25LFL064L (64-Mbit). ❐ W25Q32FW (32-Mbit) is also supported. Table 2. CX3 Booting Options PMODE[2:0][1] Boot From The sampling frequencies supported by the I2S interface are 8 kHz, 16 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, and 192 kHz. F11 USB boot F1F I2C, On failure, USB boot is enabled SPI Interface 1FF I2C only CX3 supports an SPI Master interface on the Serial Peripherals port. The maximum operation frequency is 33 MHz. 0F1 SPI, On failure, USB boot is enabled The SPI controller supports four modes of SPI communication (see SPI Timing Specification on page 25 for details on the modes) with the Start-Stop clock. This controller is a single-master controller with a single automated SSN control. It supports transaction sizes ranging from 4 bits to 32 bits. Reset Hard Reset A hard reset is initiated by asserting the RESET# pin on CX3. The specific reset sequence and timing requirements are detailed in Figure 11 on page 27 and Table 18 on page 27. All I/Os are tristated during a hard reset. An additional reset pin called MIPI_RESET is provided that resets the MIPI CSI-2 core. It should be pulled down with a resistor for normal operation. Soft Reset There are two types of Soft Reset: ■ CPU Reset – The CPU Program Counter is reset. Firmware does not need to be reloaded following a CPU Reset. ■ Whole Device Reset – This reset is identical to Hard Reset. The firmware must be reloaded following a Whole Device Reset. Note 1. F indicates Floating. Document Number: 001-87516 Rev. *O Page 8 of 40 CYUSB306X Clocking CSI-2 Rx Port). The internal PLL applies the appropriate clock-multiply option depending on the input frequency. CX3 requires two clocks for normal operation: 1. A 19.2-MHz clock to be connected at the CLKIN pin 2. A 6-MHz to 40-MHz clock to be connected at the REFCLK pin Note: REFCLK belongs to VDDIO1 power domain and CLKIN belongs to CVDDQ power domain. If same source is used, the clock must be passed through a buffer with two outputs and then connected to the clock pins. Make sure to power the clock buffer, CVDDQ and VDDIO1 with same voltage. Clock inputs to CX3 must meet the phase noise and jitter requirements specified in Table 3. The input clock frequency is independent of the clock and data rate of the CX3 core or any of the device interfaces (including the Table 3. CX3 Input Clock Specifications Parameter Phase noise Specification Description Min Units Max 100-Hz offset – –75 dB 1-kHz offset – –104 dB 10-kHz offset – –120 dB 100-kHz offset – –128 dB – –130 dB Maximum frequency deviation 1-MHz offset – – 150 ppm Duty cycle – 30 70 % Overshoot – – 3 % Undershoot – – –3 % Rise time/fall time – – 3 ns 32-kHz Watchdog Timer Clock Input CX3 includes a watchdog timer. The watchdog timer can be used to interrupt the ARM926EJ-S core, automatically wake up the CX3 in Standby mode, and reset the ARM926EJ-S core. The watchdog timer runs a 32-kHz clock, which may be optionally supplied from an external source on a dedicated CX3 pin. Table 4. 32-kHz Clock Input Requirements The firmware can disable the watchdog timer. Table 4 provides the requirements for the optional 32-kHz clock input Document Number: 001-87516 Rev. *O Parameter Min Max Units 40 60 % Frequency deviation – ±200 ppm Rise time/fall time – 200 ns Duty cycle Page 9 of 40 CYUSB306X Power Power Modes CX3 supports the following power modes: CX3 has the following power supply domains: ■ IO_VDDQ: This is a group of independent supply domains for digital I/Os. 2 ❐ VDDIO1: GPIO, I C, JTAG, XRST, XSHUTDOWN and REFCLK 2 ❐ VDDIO2: UART and I S (except MCLK) 2 ❐ VDDIO3: I S_MCLK and SPI ❐ CVDDQ: CLKIN ❐ VDD_MIPI: MIPI CSI-2 clock and data lanes ■ VDD: This is the supply voltage for the logic core. The nominal supply-voltage level is 1.2 V. This supplies the core logic circuits. The same supply must also be used for the following: ❐ AVDD: This is the 1.2 V supply for the PLL, crystal oscillator, and other core analog circuits. ❐ U3TXVDDQ/U3RXVDDQ: These are the 1.2 V supply voltages for the USB 3.0 interface. ■ VUSB: This is the 4 V to 6 V power supply for the USB I/O and analog circuits. This supply powers the USB transceiver through CX3’s internal voltage regulator. VUSB is internally regulated to 3.3 V. ■ Normal mode: This is the full-functional operating mode. The internal CPU clock and the internal PLLs are enabled in this mode. ❐ Normal operating power consumption does not exceed the sum of ICC Core max and ICC USB max (see DC Specifications on page 17 for current consumption specifications). ❐ The I/O power supplies VDDIO2 and VDDIO3 can be turned off when the corresponding interface is not in use. VDDIO1 should never be turned off for normal operation. ■ Low-power modes (see Table 5 on page 11): ❐ Suspend mode with USB 3.0 PHY enabled ❐ Standby mode ❐ Core power-down mode Note: The different power supplies have to be powered on or off in a specific sequence as illustrated in Figure 4. Figure 4. Power-up Sequence VUSB (VBUS) VDD (VDD, AVDD, VDD_MIPI) VDDIO1