CYUSB3302-68LTXI

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x HX3 USB 3.0 Hub HX3 USB 3.0 Hub General Description HX3 is a family of USB 3.0 hub controllers compliant with the USB 3.0 specification revision 1.0. HX3 supports SuperSpeed (SS), Hi-Speed (HS), Full-Speed (FS), and Low-Speed (LS) on all the ports. It has integrated termination, pull-up, and pull-down resistors, and supports configuration options through pin-straps to reduce the overall BOM of the system. HX3 includes the following Cypress-proprietary features: Shared Link™: Enables extra downstream (DS) ports for on-board connections in embedded applications Ghost Charge™: Enables charging of devices connected to the DS ports when no host is connected on the upstream (US) port HX3 USB 3.0 Hub Features ■ ■ USB-IF Certified Hub, TID# 330000060, 30000074 ■ Supports up to Four USB 3.0-Compliant DS ports ❐ All ports support SS (5 Gbps), and are backward-compatible with HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) ❐ SS and USB 2.0 Link Power Management (LPM) ❐ Dedicated Hi-Speed Transaction Translators (Multi-TT) ❐ LED status indicators – suspend, SS, and USB 2.0 operation ■ Shared Link™ for Embedded Applications ❐ Each DS port can simultaneously connect to an embedded SS device and a removable USB 2.0 device ❐ Enables up to eight device connections ■ Enhanced Battery Charging ❐ Each DS port complies with the USB Battery Charging v1.2 (BC v1.2) specification ❐ Ghost Charge™: Each DS port can emulate a Dedicated Charging Port (DCP) when the host is not connected to the US port ❐ Accessory Charger Adapter Dock (ACA-Dock): Enables charging and simultaneous data transfer for a smart phone or a tablet acting as a host compliant to BC v1.2 ❐ Apple charging supported on all DS ports ■ Integrated ARM® Cortex™-M0 CPU ❐ 16 KB RAM, 32 KB ROM ❐ Configure GPIOs for overcurrent protection, power enable, and LEDs 2 ❐ Upgrade firmware using (a) I C EEPROM or (b) an external I2C master Cypress Semiconductor Corporation Document Number: 001-73643 Rev. *T • Vendor-Command Support to Implement a USB-to-I2C Bridge ❐ Firmware upgrade of an external ASSP connected to HX3 through USB ❐ In-System Programming (ISP) of the EEPROM connected to HX3 through USB ■ Extensive Configuration Support ❐ Pin-strap configuration for the following functions: • Vendor ID (VID) • Charging support for each DS port • Number of active ports • Number of non-removable devices • Ganged or individual power switch enables for DS ports • Power switch polarity selection 2 ❐ Custom configuration modes supported with eFuse, I C 2 EEPROM, or I C slave • SS and USB 2.0 PHY parameters • Product ID (PID)/VID, manufacturer, and product string descriptors • Swap DP/DM signals for flexible PCB routing ■ Software Features ❐ Microsoft WHQL-certified for Windows XP/Vista/7/8/8.1 ❐ Compatible with Mac OS 10.9 and Linux kernel version 3.11 ❐ Customize configuration parameters with the easy-to-use Cypress’s “Blaster Plus” software tool ■ Flexible Packaging Options ❐ 68-pin QFN (8 × 8 × 1.0 mm) ❐ 88-pin QFN (10 × 10 × 1.0 mm) ❐ 100-ball BGA (6 × 6 × 1.0 mm) ❐ Industrial temperature range (–40 °C to +85 °C) 198 Champion Court • San Jose, CA 95134-1709 • +1-408-943-2600 Revised April 30, 2019 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Block Diagram SS PHY VBUS SSRxP/M DP DM USB 2.0  PHY SSTxP/M US Port USB 2.0 SS ARM Cortex-M0 VBUS Detect RAM USB 2.0 Controller SS Controller PHY Interface US Port Control Routing Hub Controller Hub Controller Repeater Four Transaction Translators ROM I2C 1.2 V US Buffers DS Buffers DS Port 1 Document Number: 001-73643 Rev. *T DS Port 2 DS Port 3 Port Control PWR OVR LED SSTxP/M SS PHY SSRxP/M USB 2.0 PHY DP DM Port Control PWR OVR LED SS PHY SSTxP/M USB 2.0 PHY SSRxP/M Port Control PWR OVR LED SSTxP/M SS PHY SSRxP/M USB 2.0 PHY DP DM PWR OVR LED SSTxP/M SSRxP/M DP DM Port Control 26 MHz Buffer and Routing Logic DP DM Routing Logic SS PHY I2C_CLK 3.3 V PLL USB 2.0 PHY I2C_DATA DS Port 4 Page 2 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Contents Architecture Overview ..................................................... 4 SS Hub Controller ....................................................... 4 USB 2.0 Hub Controller ............................................... 4 CPU ............................................................................. 4 I2C Interface ................................................................ 4 Port Controller ............................................................. 4 Applications ...................................................................... 4 HX3 Product Options ....................................................... 5 Product Features .............................................................. 6 Shared Link ................................................................. 6 Ghost Charge .............................................................. 6 Vendor-Command Support ......................................... 7 ACA-Dock Support ...................................................... 7 Pin Information ................................................................. 8 System Interfaces ........................................................... 24 Upstream Port (US) ................................................... 24 Downstream Ports (DS1, 2, 3, 4) .............................. 24 Communication Interfaces (I2C) ................................ 24 Oscillator ................................................................... 24 GPIOs ........................................................................ 24 Power Control ............................................................ 24 Reset ......................................................................... 24 Configuration Mode Select ........................................ 24 Configuration Options ................................................ 25 Document Number: 001-73643 Rev. *T EMI ................................................................................... 33 ESD .................................................................................. 33 Absolute Maximum Ratings .......................................... 34 Electrical Specifications ................................................ 34 DC Electrical Characteristics ..................................... 34 Power Consumption .................................................. 35 Ordering Information ...................................................... 36 Ordering Code Definitions ......................................... 37 Packaging ........................................................................ 38 Package Diagrams .......................................................... 39 Acronyms ........................................................................ 41 Reference Documents .................................................... 41 Document Conventions ................................................. 41 Units of Measure ....................................................... 41 Silicon Revision History ................................................ 42 Method of Identification ............................................. 42 Document History Page ................................................. 43 Sales, Solutions, and Legal Information ...................... 45 Worldwide Sales and Design Support ....................... 45 Products .................................................................... 45 PSoC® Solutions ...................................................... 45 Cypress Developer Community ................................. 45 Technical Support ..................................................... 45 Page 3 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Architecture Overview The Block Diagram on page 2 shows the HX3 architecture. HX3 consists of two independent hub controllers (SS and USB 2.0), the Cortex-M0 CPU subsystem, an I2C interface, and port controller blocks. SS Hub Controller This block supports the SS hub functionality based on the USB 3.0 specification. The SS hub controller supports the following: ■ SS link power management (U0, U1, U2, U3 states) ■ Full-duplex data transmission USB 2.0 Hub Controller This block supports the LS, FS, and HS hub functionalities. It includes the repeater, frame timer, and four transaction translators. The USB 2.0 hub controller block supports the following: I2C Interface The I2C interface in HX3 supports the following: ■ ■ I2C Slave, Master, and Multi-master configurations 2 2 ❐ Configure HX3 by an external I C master in I C slave mode 2 ❐ Configure HX3 from an I C EEPROM 2 ❐ Multi-master mode to share EEPROM with other I C masters In-System Programming of the I2C EEPROM from HX3’s US port Port Controller The port controller block controls DS port power to comply with the BC v1.2 and USB 3.0 specifications. This block also controls the US port power in the ACA-Dock mode. Control signals for external power switches are implemented within the chip. HX3 controls the external power switches at power-on to reduce in-rush current. The port controller block supports the following: ■ Overcurrent detection ■ USB 2.0 link power management (L0, L1, L2, L3 states) ■ SS and USB 2.0 port indicators for each DS port ■ Suspend, resume, and remote wake-up signaling ■ Ganged and individual power control modes ■ Multi-TT (one TT for each DS port) ■ Automatic port numbering based on active ports CPU Applications The ARM Cortex-M0 CPU subsystem is used for the following functions: ■ Standalone hubs ■ PC and tablet motherboards ■ Docking station ■ Hand-held cradles ■ Monitors ■ Digital TVs ■ Set-top boxes ■ Printers ■ System configuration and initialization ■ Battery charging control ■ Vendor-specific commands for the USB-to-I2C bridge ■ String-descriptor support ■ Suspend status indicator ■ Shared Link support in embedded systems Document Number: 001-73643 Rev. *T Page 4 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x HX3 Product Options Table 1. HX3 Product Options Features CYUSB3302 CYUSB3304 CYUSB3312 CYUSB3314 CYUSB3324 CYUSB3326 CYUSB3328 CYUSB2302 CYUSB2304 8 (4 SS, 4 USB 2.0) 2 (USB 2.0) 4 (USB 2.0) 2 (USB 3.0) 4 (USB 3.0) 2 (USB 3.0) 4 (USB 3.0) 4 (USB 3.0) 6 (2 USB 3.0, 2 SS, 2 USB 2.0) 0 0 0 0 0 2[1] 4 0 0 BC v1.2 Yes Yes Yes Yes Yes Yes Yes Yes Yes ACA-Dock No No No No Yes No Yes No No Ganged Ganged Individual and Ganged Individual and Ganged Individual and Ganged Individual Individual Ganged Ganged No No Yes Yes Yes Yes Yes No No I C Yes Yes Yes Yes Yes Yes Yes Yes Yes Vendor command Yes Yes Yes Yes Yes Yes Yes Yes Yes Number of DS ports Number of Shared Link ports External Power Switch Control Pin-Strap support 2 Port indicators Packages [2] Temperature range No No Yes Yes Yes No No No No 68-QFN, 100-ball BGA 68-QFN, 100-ball BGA 88-QFN, 100-ball BGA 88-QFN, 100-ball BGA 88-QFN, 100-ball BGA 88-QFN, 100-ball BGA 88-QFN, 100-ball BGA 68-QFN, 100-ball BGA 68-QFN, 100-ball BGA Industrial and Commercial Industrial and Commercial Industrial and Commercial Industrial and Commercial Industrial and Commercial Industrial and Commercial Industrial (88-QFN only) and Commercial Industrial and Commercial Industrial and Commercial Notes 1. DS1 and DS2 are Shared link Ports. 2. BGA Industrial Grade packages are limited to 1 W of active power. For power calculations refer to Table 12 on page 35. Document Number: 001-73643 Rev. *T Page 5 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Product Features Shared Link Figure 1. Application of Shared Link in a Notebook Example: Shared Link Provides Six USB Ports in a Notebook USB 2.0 2 USB 3.0 6 DS4 6 HX3 Internal SS Port USB 3.0 2 D+ D- 4 USB 3.0 SSTX+ SSTX- 6 SS (internal) 6 SSRX+ USB 3.0 6 SSRX- DS3 Standard USB 2.0 Port DS1 4 US PC Chipset USB 3.0 Host SS (internal) USB 3.0 Port Split Into SS Port and Standard USB 2.0 Port USB 2.0 WiFi Module USB 3.0 Camera DS2 Notebook PC Motherboard USB 2.0 HX3 USB 3.0 Port USB 3.0 Card Reader Shared Link is a Cypress-proprietary feature that enables a USB 3.0 port to be split into an embedded SS port and a standard USB 2.0 port. Shared Link enables a maximum of eight DS ports from a four-port USB 3.0 hub. DSx_PWREN is another output signal generated by HX3 and controls VBUS for the removable USB 2.0 device. For example, when an overcurrent condition occurs, DSx_PWREN turns off the port power. For example, if one of the DS ports is connected to an embedded SS device, such as a USB 3.0 camera, HX3 enables the system designer to reuse the USB 2.0 signals of that specific port to connect to a standard USB 2.0 port. Figure 1 shows how Shared Link can be used in an application. Ghost Charge HX3 Ghost Charge is a Cypress-proprietary feature for charging USB devices on the DS port when the US port is not connected to a host. For example, in a docking station with HX3 as shown in Figure 3, when the laptop is undocked, HX3 will emulate a dedicated charging port (DCP) to provide charge to a phone connected on a DS port. USB 3.0 DS Port Figure 3. Ghost Charge Figure 2. DS Port VBUS Control in Shared Link Embedded SuperSpeed Device Power to Smartphone (HX3’s Downstream Port) DSx_PWREN DM USB 2.0 PHY DP SSTXP/M SSRXP/M VBUS DSx_VBUSEN_SL SuperSpeed PHY VBUS Removable USB 2.0 Device The Shared Link mode requires a separate VBUS control for the removable USB 2.0 device and the embedded SS device. Figure 2 shows the VBUS control implementation. USB Cable HX3 Notebook PC Undocked Charge a smartphone without docking the notebook To ensure that the embedded SS device does not fall back to USB 2.0 operation, an external power switch is required. This switch is controlled by HX3, which generates an output signal called DSx_VBUSEN_SL. This signal controls the VBUS for the embedded device. Document Number: 001-73643 Rev. *T Page 6 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x When the US port is disconnected from the host, HX3 detects if any of the DS ports are connected to a device requesting charging. It determines the charging method and then switches to the appropriate signaling based on the detected charging specification as shown in Figure 4. The hub either emulates a USB-compliant dedicated charging port by connecting DP and DM (see the BC v1.2 specification) or other supported proprietary charging schemes. Figure 4. Ghost Charge Implementation in HX3 HX3 DS PORT Other Charging Scheme BC v1.2 Scheme Figure 5 shows the ACA-Dock system. If the ACA-Dock feature is enabled, HX3 turns on the external power switch to drive VBUS on the US port. To inform the OTG host that it is connected to an ACA-Dock, the ID pin is tied to ground using a resistor RID_A,3 as shown in Figure 5. The ACA-Dock feature can be disabled using the Configuration Options on page 25. 5V Power Switch VBUS DSx_OVRCURR Figure 5. ACA-Dock Support DSx_PWREN DM In traditional USB topologies, the host provides VBUS to enable and charge the connected devices. For OTG hosts, however, an ACA-Dock provides VBUS and a method to charge the host. HX3 supports the ACA-Dock standard (see BC v1.2 specification) by integrating the functions of the adapter controller. For example, a BC v1.2 compliant phone such as a Sony Xperia (neo V) can be docked to a HX3-based ACA-Dock system. The phone acts as an OTG host and the ACA-Dock charges the phone connected to the US port while also powering the four DS ports. Charging Scheme Detector DP ACA-Dock Support VBUS Power Source 5V Wall Charger Detector Battery Charger Power Switch US_PWREN HX3 USB Battery-Powered Device Ghost Charge is enabled by default and can be disabled through configuration. Refer to Configuration Options on page 25. Vendor-Command Support VBUS To US OTG Enabled Device ID RID_A VBUS Micro A Plug PCB HX3 supports vendor-specific requests and can also enumerate as a vendor-specific device. The vendor-specific request can be used to (a) bridge USB and I2C and (b) configure HX3. This feature can be used for the following applications: ■ Firmware upgrade of an external ASSP connected to HX3 through USB ■ In-System programming (ISP) of an EEPROM connected to HX3 through USB Note 3. 124 k is the recommended RID_A value as per BC v1.2 specification, but some portable devices use custom RID_A values. Document Number: 001-73643 Rev. *T Page 7 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Pin Information 57 56 55 54 AVDD12 60 59 58 AVDD12 XTL_OUT 62 61 XTL_IN 63 AVDD33 DS2_DM DS2_DP 64 US_DP NC 65 US_DM NC 66 DS1_DM AVDD33 67 DS1_DP NC 68 AVDD33 NC Figure 6. HX3 68-Pin QFN 2-Port Pinout 53 52 DVDD12 1 51 DS1_RXP RREF_USB2 2 50 DS1_RXM DVDD12 3 49 DVDD12 AVDD33 4 48 DS1_TXM US_TXM 5 47 DS1_TXP US_TXP 6 46 AVDD12 DVDD12 7 45 DS2_RXP US_RXM 8 44 DS2_RXM US_RXP 9 AVDD12 10 42 DS2_TXM NC 11 41 DS2_TXP NC 12 40 GND DVDD12 13 39 NC NC 14 38 NC NC 15 37 DVDD12 AVDD12 16 36 NC VBUS_US 17 35 NC 43 DVDD12 21 22 23 24 25 26 27 28 29 30 31 32 33 34 RESERVED2 MODE_SEL[0] MODE_SEL[1] NC RREF_SS DVDD12 VDD_IO PWR_EN OVRCURR RESETN I2C_CLK I2C_DATA AVDD12 VDD_EFUSE Document Number: 001-73643 Rev. *T 20 SUSPEND 19 RESERVED1 18 VBUS_DS 68-Pin QFN Page 8 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x 57 56 55 54 AVDD12 60 59 58 AVDD12 XTL_OUT 62 61 XTL_IN DS2_DP 63 AVDD33 DS2_DM 64 US_DP DS3_DM 65 US_DM DS3_DP 66 DS1_DM AVDD33 67 DS1_DP DS4_DP 68 AVDD33 DS4_DM Figure 7. HX3 68-Pin QFN 4-Port Pinout 53 52 DVDD12 1 51 DS1_RXP RREF_USB2 2 50 DS1_RXM DVDD12 3 49 DVDD12 AVDD33 4 48 DS1_TXM US_TXM 5 47 DS1_TXP US_TXP 6 46 AVDD12 DVDD12 7 45 DS2_RXP US_RXM 8 44 DS2_RXM US_RXP 9 AVDD12 10 42 DS2_TXM DS4_TXP 11 41 DS2_TXP DS4_TXM 12 40 GND DVDD12 13 39 DS3_TXM DS4_RXM 14 38 DS3_TXP DS4_RXP 15 37 DVDD12 AVDD12 16 36 DS3_RXM VBUS_US 17 35 DS3_RXP 43 DVDD12 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VBUS_DS VDD_EFUSE SUSPEND RESERVED1 RESERVED2 MODE_SEL[0] MODE_SEL[1] NC RREF_SS DVDD12 VDD_IO PWR_EN OVRCURR RESETN I2C_CLK I2C_DATA AVDD12 68-Pin QFN Document Number: 001-73643 Rev. *T Page 9 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Figure 8. HX3 100-Ball BGA Pinout for CYUSB3302 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 NC NC NC AVDD33 DS2_DM DS2_DP AVDD33 US_DM US_DP AVDD12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 NC NC NC VDD_IO VSS AVDD33 NC NC NC DVDD12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 US_TXM NC NC NC NC VSS DS1_DP DS1_DM AVDD12 DS1_RXM D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 US_TXP NC NC DVDD12 VSS DVDD12 VSS DVDD12 VSS DS1_RXP E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 DVDD12 RREF_US B2 NC NC XTL_IN XTL_OUT VDD_IO DS1_TXM VSS DVDD12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 DVDD12 OVRCUR R RESETN DS1_TXP AVDD12 DS2_RXP G5 G6 G7 G8 G9 G10 VDD_IO PWR_EN I2C_DATA VSS DS2_RXM US_RXM VSS AVDD33 MODE_SE L[1] G1 G2 G3 G4 US_RXP VBUS_DS SUSPEND H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 AVDD12 VBUS_US VDD_EFU SE RESERVE D2 RREF_SS VSS DS2_TXM DS2_TXP NC AVDD12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 VSS AVDD12 VSS GPIO NC I2C_CLK NC NC VSS NC K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 NC NC DVDD12 NC NC NC NC NC DVDD12 NC Document Number: 001-73643 Rev. *T RESERVE MODE_SE D1 L[0] Page 10 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Figure 9. HX3 100-Ball BGA Pinout for CYUSB3304 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 NC DS4_DM DS4_DP AVDD33 DS2_DM DS2_DP AVDD33 US_DM US_DP AVDD12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 NC NC NC VDD_IO VSS AVDD33 NC NC NC DVDD12 C1 C2 C3 C4 C5 C6 C7 C8 C9 10 US_TXM NC NC DS3_DP DS3_DM VSS DS1_DP DS1_DM AVDD12 DS1_RXM D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 US_TXP NC NC DVDD12 VSS DVDD12 VSS DVDD12 VSS DS1_RXP E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 DVDD12 RREF_US B2 NC NC XTL_IN XTL_OUT VDD_IO DS1_TXM VSS DVDD12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 DVDD12 OVRCUR R RESETN DS1_TXP AVDD12 DS2_RXP G5 G6 G7 G8 G9 G10 VDD_IO PWR_EN I2C_DATA VSS DS2_RXM US_RXM VSS AVDD33 MODE_SE L[1] G1 G2 G3 G4 US_RXP VBUS_DS SUSPEND H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 AVDD12 VBUS_US VDD_EFU SE RESERVE D2 RREF_SS VSS DS2_TXM DS2_TXP NC AVDD12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 VSS AVDD12 VSS GPIO NC I2C_CLK NC NC VSS DS3_RXM K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 DS4_TXP DS4_TXM DVDD12 DS4_RXP DS4_RXM NC DS3_TXP DS3_TXM DVDD12 DS3_RXP Document Number: 001-73643 Rev. *T RESERVE MODE_SE D1 L[0] Page 11 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 2. 68-Pin QFN, 100-Ball BGA Pinout for CYUSB3302 and CYUSB3304 Pin Name Type 68-QFN Pin# 100-BGA Ball # US_RXP I 9 G1 SuperSpeed receive plus US_RXM I 8 F1 SuperSpeed receive minus US_TXP O 6 D1 SuperSpeed transmit plus US_TXM O 5 C1 SuperSpeed transmit minus CYUSB3302 CYUSB3304 Description US Port US_DP I/O 57 A9 USB 2.0 data plus US_DM I/O 58 A8 USB 2.0 data minus DS1 Port DS1_RXP I 51 D10 SuperSpeed receive plus DS1_RXM I 50 C10 SuperSpeed receive minus DS1_TXP O 47 F8 SuperSpeed transmit plus DS1_TXM O 48 E8 SuperSpeed transmit minus DS1_DP I/O 60 C7 USB 2.0 data plus DS1_DM I/O 59 C8 USB 2.0 data minus DS2_RXP I 45 F10 SuperSpeed receive plus DS2_RXM I 44 G10 SuperSpeed receive minus DS2_TXP O 41 H8 SuperSpeed transmit plus DS2 Port DS2_TXM O 42 H7 SuperSpeed transmit minus DS2_DP I/O 62 A6 USB 2.0 data plus DS2_DM I/O 63 A5 USB 2.0 data minus DS3 Port NC DS3_RXP I 35 K10 SuperSpeed receive plus NC NC DS3_RXM I 36 J10 SuperSpeed receive minus DS3_TXP O 38 K7 SuperSpeed transmit plus NC DS3_TXM O 39 K8 SuperSpeed transmit minus NC DS3_DP I/O 65 C4 USB 2.0 data plus NC DS3_DM I/O 64 C5 USB 2.0 data minus DS4 Port NC DS4_RXP I 15 K4 SuperSpeed receive plus NC DS4_RXM I 14 K5 SuperSpeed receive minus NC DS4_TXP O 11 K1 SuperSpeed transmit plus NC DS4_TXM O 12 K2 SuperSpeed transmit minus NC DS4_DP I/O 67 A3 USB 2.0 data plus NC DS4_DM I/O 68 A2 USB 2.0 data minus OVRCURR I 30 F6 Ganged overcurrent input PWR_EN I/O 29 G7 Ganged power enable output Document Number: 001-73643 Rev. *T Page 12 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 2. 68-Pin QFN, 100-Ball BGA Pinout for CYUSB3302 and CYUSB3304 (continued) Pin Name Type 68-QFN Pin# 100-BGA Ball # NC I/O 25 NA NC RESERVED1 21 22 G4 This pin must be pulled HIGH using a 10 k to VDD_IO. RESERVED2 I/O I H4 This pin must be pulled HIGH using a 10 k to VDD_IO. MODE_SEL[0] I 23 G5 Device operation mode select bit 0; refer to Table 5 on page 24 MODE_SEL[1] I 24 F4 Device operation mode select bit 1; refer to Table 5 on page 24 XTL_OUT A 54 E6 Crystal out CYUSB3302 CYUSB3304 Description Mode Select, Clock, and Reset XTL_IN A 55 E5 Crystal in RESETN I 31 F7 Active LOW reset input I2C_CLK I/O 32 J6 I2C clock I2C_DATA I/O 33 G8 I2C data SUSPEND I/O 20 G3 Hub suspend status indicator. This pin is asserted if both the SS and USB 2.0 hubs are in the suspend state and is de-asserted when either of the hubs comes out of the suspend state. Power and Ground VDD_EFUSE PWR 19 AVDD12 PWR 10, 16, 34, 46, 52, 53 GND PWR 40 DVDD12 PWR 1, 3, 7, 13, 27, 37, 43, 49, VBUS _US PWR 17 VBUS_DS PWR 18 AVDD33 PWR 4, 56, 61, 66 VDD_IO PWR 28 H3 1.2 V normal operation, 2.5 V for programming. Customers should connect to 1.2 V. A10, C9, F9, 1.2 V analog supply H1, H10, J2 B5, C6, D5, D7, D9, E9, F2, G9, GND pin H6, J1, J3, J9 B10, D4, D6, D8, E1, E10, 1.2 V core supply F5, K3, K9 H2 This pin must be connected to VBUS from US port G2 This pin is used to power the Apple-charging circuit in HX3. For normal operation, connect pin to local 5 V supply to enable Apple charging and BC v1.2 charging modes (enable multi-charger mode). For BC v1.2 compliance testing or when Apple charging is not required, connect pin to GND to enable BC v1.2 charging mode (disable multi-charger mode). A4, A7, B6, F3 3.3 V analog supply B4, E7, G6 3.3 V I/O supply USB Precision Resistors RREF_USB2 A 2 E2 Connect pin to a precision resistor (6.04 k±1%) to generate a current reference for USB 2.0 PHY. RREF_SS A 26 H5 Connect pin to a precision resistor (200  ±1%) for SS PHY termination impedance calibration. Note 4. These pins are Do Not Use (DNU); they must be left floating. Document Number: 001-73643 Rev. *T Page 13 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 3. 68-Pin QFN, 100-Ball BGA Pinout for CYUSB2302 and CYUSB2304 Pin Name Type 68-QFN Pin# 100-BGA Ball # NC I 9 G1 SuperSpeed receive plus NC I 8 F1 SuperSpeed receive minus NC O 6 D1 SuperSpeed transmit plus NC O 5 C1 SuperSpeed transmit minus CYUSB2302 CYUSB2304 Description US Port US_DP I/O 57 A9 USB 2.0 data plus US_DM I/O 58 A8 USB 2.0 data minus DS1 Port NC I 51 D10 SuperSpeed receive plus NC I 50 C10 SuperSpeed receive minus NC O 47 F8 SuperSpeed transmit plus NC O 48 E8 SuperSpeed transmit minus DS1_DP I/O 60 C7 USB 2.0 data plus DS1_DM I/O 59 C8 USB 2.0 data minus NC I 45 F10 SuperSpeed receive plus NC I 44 G10 SuperSpeed receive minus NC O 41 H8 SuperSpeed transmit plus DS2 Port NC O 42 H7 SuperSpeed transmit minus DS2_DP I/O 62 A6 USB 2.0 data plus DS2_DM I/O 63 A5 USB 2.0 data minus DS3 Port NC I 35 K10 SuperSpeed receive plus NC NC I 36 J10 SuperSpeed receive minus NC NC O 38 K7 SuperSpeed transmit plus NC NC O 39 K8 SuperSpeed transmit minus NC DS3_DP I/O 65 C4 USB 2.0 data plus NC DS3_DM I/O 64 C5 USB 2.0 data minus NC DS4 Port NC NC I 15 K4 SuperSpeed receive plus NC NC I 14 K5 SuperSpeed receive minus NC NC O 11 K1 SuperSpeed transmit plus NC NC O 12 K2 SuperSpeed transmit minus NC DS4_DP I/O 67 A3 USB 2.0 data plus NC DS4_DM I/O 68 A2 USB 2.0 data minus OVRCURR I 30 F6 Ganged overcurrent input PWR_EN I/O 29 G7 Ganged power enable output Document Number: 001-73643 Rev. *T Page 14 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 3. 68-Pin QFN, 100-Ball BGA Pinout for CYUSB2302 and CYUSB2304 (continued) Pin Name Type 68-QFN Pin# 100-BGA Ball # NC I/O 25 NA NC RESERVED1 21 22 G4 This pin must be pulled HIGH using a 10 k to VDD_IO. RESERVED2 I/O I H4 This pin must be pulled HIGH using a 10 k to VDD_IO. MODE_SEL[0] I 23 G5 Device operation mode select bit 0; refer to Table 5 on page 24 MODE_SEL[1] I 24 F4 Device operation mode select bit 1; refer to Table 5 on page 24 XTL_OUT A 54 E6 Crystal out CYUSB2302 CYUSB2304 Description Mode Select, Clock, and Reset XTL_IN A 55 E5 Crystal in RESETN I 31 F7 Active LOW reset input I2C_CLK I/O 32 J6 I2C clock I2C_DATA I/O 33 G8 I2C data SUSPEND I/O 20 G3 Hub suspend status indicator. This pin is asserted if both the SS and USB 2.0 hubs are in the suspend state and is de-asserted when either of the hubs comes out of the suspend state. Power and Ground VDD_EFUSE PWR 19 AVDD12 PWR 10, 16, 34, 46, 52, 53 GND PWR 40 DVDD12 PWR 1, 3, 7, 13, 27, 37, 43, 49, VBUS _US PWR 17 VBUS_DS PWR 18 AVDD33 PWR 4, 56, 61, 66 VDD_IO PWR 28 H3 1.2 V normal operation, 2.5 V for programming. Customers should connect to 1.2 V. A10, C9, F9, 1.2 V analog supply H1, H10, J2 B5, C6, D5, D7, D9, E9, F2, G9, GND pin H6, J1, J3, J9 B10, D4, D6, D8, E1, E10, 1.2 V core supply F5, K3, K9 H2 This pin must be connected to VBUS from US port G2 This pin is used to power the Apple-charging circuit in HX3. For normal operation, connect pin to local 5 V supply to enable Apple charging and BC v1.2 charging modes (enable multi-charger mode). For BC v1.2 compliance testing or when Apple charging is not required, connect pin to GND to enable BC v1.2 charging mode (disable multi-charger mode). A4, A7, B6, F3 3.3 V analog supply B4, E7, G6 3.3 V I/O supply USB Precision Resistors RREF_USB2 A 2 E2 Connect pin to a precision resistor (6.04 k±1%) to generate a current reference for USB 2.0 PHY. RREF_SS A 26 H5 Connect pin to a precision resistor (200  ±1%) for SS PHY termination impedance calibration. Document Number: 001-73643 Rev. *T Page 15 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x VDD_IO DS3_PWREN DS2_PWREN DS3_AMBER DS2_LED_SS DVDD12 NC NC AVDD33 NC NC DS2_DM DS2_DP AVDD33 DS1_DP DS1_DM US_DM US_DP AVDD33 XTL_IN XTL_OUT AVDD12 Figure 10. HX3 88-Pin QFN 2-Port Pinout 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 DS2_OVRCURR 1 66 VDD_IO DS1_AMBER 2 65 DS3_OVRCURR DS1_GREEN 3 64 DS3_GREEN DS1_LED_SS 4 63 DS3_LED_SS DS2_AMBER 5 62 AVDD12 DS2_GREEN 6 61 DS1_RXP RREF_USB2 7 60 DS1_RXM DVDD12 8 59 DVDD12 AVDD33 9 58 DS1_TXM US_TXM 10 57 DS1_TXP US_TXP 11 DVDD12 12 US_RXM 13 54 US_RXP 14 53 DVDD12 AVDD12 15 52 DS2_TXM NC 16 51 DS2_TXP NC 17 50 GND DVDD12 18 49 NC NC 19 48 NC NC 20 47 DVDD12 AVDD12 21 46 NC VBUS_US 22 45 NC 56 88-Pin QFN 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 VBUS_DS VDD_EFUSE SUSPEND DS4_LED_SS RESERVED1 MODE_SEL[0] MODE_SEL[1] DS4_AMBER US_PWREN RREF_SS DVDD12 VDD_IO DS4_PWREN/PWR_EN4 DS4_OVRCURR RESETN DS1_PWREN US_OVRCURR I2C_CLK I2C_DATA DS1_OVRCURR DS4_GREEN AVDD12 55 DS2_RXP 23 Document Number: 001-73643 Rev. *T AVDD12 DS2_RXM Page 16 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x VDD_IO DS3_PWREN DS2_PWREN DS3_AMBER DS2_LED_SS DVDD12 DS4_DM DS4_DP AVDD33 DS3_DP DS3_DM DS2_DM DS2_DP AVDD33 DS1_DP DS1_DM US_DM US_DP AVDD33 XTL_IN XTL_OUT AVDD12 Figure 11. HX3 88-Pin QFN 4-Port Pinout 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 DS2_OVRCURR 1 66 VDD_IO DS1_AMBER 2 65 DS3_OVRCURR DS1_GREEN 3 64 DS3_GREEN DS1_LED_SS 4 63 DS3_LED_SS DS2_AMBER 5 62 AVDD12 DS2_GREEN 6 61 DS1_RXP RREF_USB2 7 60 DS1_RXM DVDD12 8 59 DVDD12 AVDD33 9 58 DS1_TXM US_TXM 10 57 DS1_TXP US_TXP 11 DVDD12 12 US_RXM 13 54 US_RXP 14 53 DVDD12 AVDD12 15 52 DS2_TXM DS4_TXP 16 51 DS2_TXP DS4_TXM 17 50 GND DVDD12 18 49 DS3_TXM DS4_RXM 19 48 DS3_TXP DS4_RXP 20 47 DVDD12 AVDD12 21 46 DS3_RXM VBUS_US 22 45 DS3_RXP 56 88-Pin QFN 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 VBUS_DS VDD_EFUSE SUSPEND DS4_LED_SS RESERVED1 MODE_SEL[0] MODE_SEL[1] DS4_AMBER US_PWREN RREF_SS DVDD12 VDD_IO DS4_PWREN/PWR_EN4 DS4_OVRCURR RESETN DS1_PWREN US_OVRCURR I2C_CLK I2C_DATA DS1_OVRCURR DS4_GREEN AVDD12 55 DS2_RXP 23 Document Number: 001-73643 Rev. *T AVDD12 DS2_RXM Page 17 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Figure 12. HX3 100-Ball BGA Pinout for CYUSB3312 A1 A2 DS3_PWR NC EN B1 B2 DS2_OVR DS2_PWR CURR EN C1 C2 DS1_AMBE US_TXM R D1 D2 DS1_LED_ US_TXP SS E1 E2 RREF_USB DVDD12 2 F1 F2 US_RXM G1 US_RXP H1 AVDD12 J1 VSS K1 NC A3 A4 A5 A6 A7 A8 A9 A10 NC AVDD33 DS2_DM DS2_DP AVDD33 US_DM US_DP AVDD12 B3 B4 B5 B6 B7 B8 B9 DS3_AMBE DS3_OVR DS3_GREE DS3_LED_ VDD_IO VSS AVDD33 R CURR N SS C3 C4 C5 C6 C7 C8 C9 DS2_LED_ NC NC VSS DS1_DP DS1_DM AVDD12 SS D3 D4 D5 D6 D7 D8 D9 DS1_GREE DVDD12 VSS DVDD12 VSS DVDD12 VSS N E3 E4 E5 E6 E7 E8 E9 DS2_GREE DS2_AMBE XTL_IN XTL_OUT VDD_IO DS1_TXM VSS N R F3 F4 F5 F6 F7 F8 F9 MODE_SE DS4_OVR VSS AVDD33 DVDD12 RESETN DS1_TXP AVDD12 L[1] CURR G2 G3 G4 G5 G6 G7 G8 G9 RESERVE MODE_SE DS4_PWR VBUS_DS SUSPEND VDD_IO I2C_DATA VSS D1 L[0] EN H2 H3 H4 H5 H6 H7 H8 H9 VDD_EFUS DS4_LED_ DS4_GREE VBUS_US RREF_SS VSS DS2_TXM DS2_TXP E SS N J2 J3 J4 J5 J6 J7 J8 J9 DS4_AMBE US_PWRE DS1_PWR DS1_OVR AVDD12 VSS I2C_CLK VSS R N EN CURR K2 K3 K4 K5 K6 K7 K8 K9 US_OVRC NC DVDD12 NC NC NC NC DVDD12 URR Document Number: 001-73643 Rev. *T B10 DVDD12 C10 DS1_RXM D10 DS1_RXP E10 DVDD12 F10 DS2_RXP G10 DS2_RXM H10 AVDD12 J10 NC K10 NC Page 18 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Figure 13. HX3 100-Ball BGA Pinout for CYUSB3314, CYUSB332x A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 DS3_PWR EN DS4_DM DS4_DP AVDD33 DS2_DM DS2_DP AVDD33 US_DM US_DP AVDD12 B4 B5 B6 B7 B8 B9 B10 DS3_GRE EN DS3_LED _SS DVDD12 B1 B2 B3 DS2_OVR CURR DS2_PWR EN DS3_AMB ER VDD_IO VSS AVDD33 DS3_OVR CURR C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 US_TXM DS1_AMB ER DS2_LED _SS DS3_DP DS3_DM VSS DS1_DP DS1_DM AVDD12 DS1_RXM D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 US_TXP DS1_LED _SS DS1_GRE EN DVDD12 VSS DVDD12 VSS DVDD12 VSS DS1_RXP E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 DVDD12 RREF_US B2 DS2_GRE EN DS2_AMB ER XTL_IN XTL_OUT VDD_IO DS1_TXM VSS DVDD12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 DVDD12 DS4_OVR CURR RESETN DS1_TXP AVDD12 DS2_RXP G5 G6 G7 G8 G9 G10 VDD_IO DS4_PWR EN I2C_DATA VSS DS2_RXM H6 H7 H8 H9 H10 AVDD12 US_RXM VSS AVDD33 MODE_SE L[1] G1 G2 G3 G4 US_RXP VBUS_DS SUSPEND H1 H2 H3 H4 AVDD12 VBUS_US VDD_EFU SE DS4_LED _SS RREF_SS VSS DS2_TXM DS2_TXP DS4_GRE EN J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 VSS AVDD12 VSS DS4_AMB ER US_PWR EN I2C_CLK DS1_PWR EN DS1_OVR CURR VSS DS3_RXM K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 DS4_RXM US_OVRC URR DS3_TXP DS3_TXM DVDD12 DS3_RXP DS4_TXP DS4_TXM DVDD12 Document Number: 001-73643 Rev. *T RESERVE MODE_SE D1 L[0] DS4_RXP H5 Page 19 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 4. 88-Pin QFN, 100-Ball BGA Pinout for CYUSB331X and CYUSB332X Pin Name CYUSB3314 CYUSB3312 CYUSB3324 Type Pin# Ball# Description CYUSB3326 CYUSB3328 US Port US_RXP I 14 G1 SuperSpeed receive plus US_RXM I 13 F1 SuperSpeed receive minus US_TXP O 11 D1 SuperSpeed transmit plus US_TXM O 10 C1 SuperSpeed transmit minus US_DP I/O 71 A9 USB 2.0 data plus US_DM I/O 72 A8 USB 2.0 data minus K6 CYUSB3324/3328: Overcurrent detect input for US port in ACA-Dock mode. If ACA-Dock mode is disabled using Configuration Options on page 25, this pin must be pulled HIGH using a 10 k to VDD_IO. Other part numbers: This pin must be pulled HIGH using a 10 k to VDD_IO. US_OVRCURR US_PWREN[5] I I/O 39 31 J5 PWR_SW_POL[6] CYUSB3324/3328: VBUS power enable output for US port in ACA-Dock mode. If ACA-Dock mode is disabled using Configuration Options on page 25, this pin can be left floating if Pin-Strap is not enabled. Other part numbers: This pin can be left floating if Pin-Strap (Pin# 63) is not enabled. This pin is called PWR_SW_POL in pin-strap configuration mode. DS1 Port DS1_RXP I 61 D10 SuperSpeed receive plus DS1_RXM I 60 C10 SuperSpeed receive minus DS1_TXP O 57 F8 SuperSpeed transmit plus DS1_TXM O 58 E8 SuperSpeed transmit minus DS1_DP I/O 74 C7 USB 2.0 data plus DS1_DM I/O 73 C8 USB 2.0 data minus DS1_OVRCURR I 42 J8 Overcurrent detect input for DS1 port I/O 38 J7 VBUS power enable output for DS1 port. When the port is disabled, this pin is in tristate. DS1_PWREN[5] DS1_CDP_EN[6] DS1_AMBER[5] ACA_DOCK[6] This pin is called DS1_CDP_EN in pin-strap configuration mode. I/O 2 C2 DS1_GREEN[5] DS1_VBUSEN_SL[5] PORT_DISABLE[1][6] This pin is called ACA-DOCK in pin-strap configuration mode. CYUSB3312/3314/3324: LED_GREEN output for DS1 port I/O 3 D3 PORT_DISABLE[0][6] DS1_LED_SS[5] LED_AMBER output for DS1 port CYUSB3326/3328: VBUS power enable output for SS port 1 This pin is called PORT_DISABLE[0] in pin-strap configuration mode. I/O 4 D2 LED_SS output for DS1 port This pin is called PORT_DISABLE[1] in pin-strap configuration mode. Notes 5. This pin can be configured as a GPIO using custom firmware. For information contact www.cypress.com/support. 6. For pin-strap configuration details, refer to Table 6 on page 26. Document Number: 001-73643 Rev. *T Page 20 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 4. 88-Pin QFN, 100-Ball BGA Pinout for CYUSB331X and CYUSB332X (continued) Pin Name CYUSB3314 CYUSB3312 CYUSB3324 Type Pin# Ball# Description CYUSB3326 CYUSB3328 DS2 Port DS2_RXP I 55 F10 SuperSpeed receive plus DS2_RXM I 54 G10 SuperSpeed receive minus DS2_TXP O 51 H8 SuperSpeed transmit plus DS2_TXM O 52 H7 SuperSpeed transmit minus DS2_DP I/O 76 A6 USB 2.0 data plus DS2_DM I/O 77 A5 USB 2.0 data minus DS2_OVRCURR I 1 B1 Overcurrent detect input for DS2 port B2 VBUS power enable output for DS2 port. When the port is disabled, this pin is in tristate. DS2_PWREN[7] DS2_CDP_EN[8] DS2_AMBER[7] NON_REMOVABLE[0][8] I/O 86 This pin is called DS2_CDP_EN in the pin-strap configuration mode. I/O 5 E4 I/O 6 E3 DS2_GREEN[7] DS2_VBUSEN_SL[7] PWR_EN_SEL[8] This pin is called NON_REMOVABLE[0] in the pin-strap configuration mode. CYUSB3312/3314/3324: LED_GREEN output for DS2 port NON_REMOVABLE[1][8] DS2_LED_SS[7] LED_AMBER output for DS2 port CYUSB3326/3328: VBUS power enable output for SS port 2 This pin is called NON_REMOVABLE[1] in the pin-strap configuration mode. I/O 84 C3 LED_SS output for DS2 port This pin is called PWR_EN_SEL in the pin-strap configuration mode. DS3 Port NC DS3_RXP I 45 K10 SuperSpeed receive plus NC DS3_RXM I 46 J10 SuperSpeed receive minus NC DS3_TXP O 48 K7 SuperSpeed transmit plus NC DS3_TXM O 49 K8 SuperSpeed transmit minus NC DS3_DP I/O 79 C4 USB 2.0 data plus NC DS3_DM I/O 78 C5 USB 2.0 data minus I 65 B7 CYUSB3314/3324/3326/3328: Overcurrent detect input for DS3 port CYUSB3312: This pin must be pulled HIGH using a 10 k to VDD_IO. I/O 87 A1 DS3_OVRCURR DS3_PWREN[7] DS3_CDP_EN[8] DS3_AMBER[7] VID_SEL[2][8] VBUS power enable output for DS3 port. When the port is disabled, this pin is in tristate. This pin is called DS3_CDP_EN in the pin-strap configuration mode. I/O 85 B3 LED_AMBER output for DS3 port This pin is called VID_SEL[2] in the pin-strap configuration mode. Notes 7. This pin can be configured as a GPIO using custom firmware. For information contact www.cypress.com/support. 8. For pin-strap configuration details, refer to Table 6 on page 26. Document Number: 001-73643 Rev. *T Page 21 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 4. 88-Pin QFN, 100-Ball BGA Pinout for CYUSB331X and CYUSB332X (continued) Pin Name CYUSB3314 CYUSB3312 CYUSB3324 Type Pin# Ball# Description CYUSB3326 CYUSB3328 DS3_GREEN[9] DS3_VBUSEN_SL[9] CYUSB3312/3314/3324: LED_GREEN output for DS3 port I/O 64 B8 VID_SEL[1][10] DS3_LED_SS[9] PIN_STRAP[10] CYUSB3328: VBUS power enable output for SS port 3 This pin is called VID_SEL[1] in the pin-strap configuration mode. For pin-strap configuration details, refer to Table 6 on page 26. LED_SS output for DS3 port I/O 63 B9 This pin is called PIN_STRAP in pin-strap configuration mode. When connected to VDD_IO through a 10-k resistor, this pin enables pin-strap configuration mode for HX3. DS4 Port NC DS4_RXP I 20 K4 SuperSpeed receive plus NC DS4_RXM I 19 K5 SuperSpeed receive minus NC DS4_TXP O 16 K1 SuperSpeed transmit plus NC DS4_TXM O 17 K2 SuperSpeed transmit minus NC DS4_DP I/O 81 A3 USB 2.0 data plus NC DS4_DM I/O 82 A2 USB 2.0 data minus I 36 F6 CYUSB3314/3324/3326/3328: Overcurrent detect input for DS4 port. CYUSB3312: This pin must be pulled HIGH using a 10 k to VDD_IO. DS4_OVRCURR DS4_PWREN/PWR_EN4 I/O 35 G7 DS4_CDP_EN[10] DS4_AMBER[9] I2C_DEV_ID[10] This pin is called DS4_CDP_EN in the pin-strap configuration mode. I/O 30 J4 I/O 43 H9 DS4_GREEN[9] DS4_VBUSEN_SL VBUS power enable output for DS4 port. This pin is also used as power enable output when configured in ganged power mode using the Blaster Plus tool. When the port is disabled, this pin is in tristate. LED_AMBER output for DS4 port This pin is called I2C_DEV_ID in the pin-strap configuration mode. CYUSB3312/3314/3324: LED_GREEN output for DS4 port VID_SEL[0][10] CYUSB3328: VBUS power enable output for SS port 4 This pin is called VID_SEL[0] in the pin-strap configuration mode. DS4_LED_SS I/O 26 H4 LED_SS output for DS4 port. The LED must be connected to GND as shown in Figure 16 on page 25. If LED is not used, this pin must be pulled HIGH using a 10 k to VDD_IO. RESERVED1 I 27 G4 This pin must be pulled HIGH using a 10 k to VDD_IO. Mode Select, Clock, and Reset MODE_SEL[0] I 28 G5 Device operation mode select bit 0; refer to Table 5 on page 24 MODE_SEL[1] I 29 F4 Device operation mode select bit 1; refer to Table 5 on page 24 XTL_OUT A 68 E6 Crystal out XTL_IN A 69 E5 Crystal in RESETN I 37 F7 Active LOW reset input I2C_CLK I/O 40 J6 I2C clock I2C_DATA I/O 41 G8 I2C data Notes 9. This pin can be configured as a GPIO using custom firmware. For information contact www.cypress.com/support. 10. For pin-strap configuration details, refer to Table 6 on page 26. Document Number: 001-73643 Rev. *T Page 22 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x Table 4. 88-Pin QFN, 100-Ball BGA Pinout for CYUSB331X and CYUSB332X (continued) Pin Name CYUSB3314 CYUSB3312 CYUSB3324 Type Pin# Ball# Description 25 G3 Hub suspend status indicator. This pin is asserted if both the SS and USB 2.0 hubs are in the suspend state and is de-asserted when either of the hubs comes out of the suspend state. H3 1.2 V normal operation, 2.5 V for programming. Customers should connect to 1.2 V CYUSB3326 CYUSB3328 SUSPEND I/O Power and Ground VDD_EFUSE AVDD12 GND DVDD12 VBUS _US PWR 24 A10, 15, 21, C9, F9, 1.2 V analog supply PWR 44, 56, H1, 62, 67 H10, J2 PWR 50 B5, C6, D5, D7, D9, E9, GND pin F2, G9, H6, J1, J3, J9 B10, 8, 12, D4, D6, 18, 33, D8, E1, 1.2 V core supply PWR 47, 53, E10, 59, 83 F5, K3, K9 PWR 22 23 H2 CYUSB3324/3328: Connect the VBUS_US pin to the local 5 V supply. If ACA-Dock mode is disabled using Configuration Options on page 25, this pin must be connected to VBUS from US port. Other part numbers: This pin must be connected to VBUS from US port. G2 This pin is used to power the Apple-charging circuit in HX3. For normal operation, connect pin to local 5 V supply to enable Apple charging and BC v1.2 charging modes (enable multi-charger mode). For BC v1.2 compliance testing or when Apple charging is not required, connect pin to GND to enable BC v1.2 charging mode (disable multi-charger mode). VBUS_DS PWR AVDD33 PWR 9, 70, A4, A7, 3.3 V analog supply 75, 80 B6, F3 VDD_IO PWR 34, 66, B4, E7, 3.3 V I/O supply 88 G6 USB Precision Resistors RREF_USB2 A 7 E2 Connect pin to a precision resistor (6.04 k ±1%) to generate a current reference for USB 2.0 PHY. RREF_SS A 32 H5 Connect pin to a precision resistor (200  ±1%) for SS PHY termination impedance calibration. Document Number: 001-73643 Rev. *T Page 23 of 45 CYUSB330x/CYUSB331x CYUSB332x/CYUSB230x System Interfaces switches for DS port power and monitor overcurrent conditions. The power switch polarity and the power control mode (individual and ganged) can be changed using the configuration options. Upstream Port (US) This port is compliant with the USB 3.0 specification and includes an integrated 1.5 k pull-up and termination resistors. It also supports ACA-Dock to enable charging an OTG host connected on the US port. Downstream Ports (DS1, 2, 3, 4) DS ports are compliant with the USB 3.0 specification and integrate 15 k pull-down and termination resistors. Ports can be disabled or enabled, and can be set to removable or non-removable options. BC v1.2 charging is enabled by default and can be disabled on each DS port using the configuration options (see Configuration Options). Communication Interfaces (I2C) Reset HX3 operates with two external power supplies, 3.3 V and 1.2 V. There is no power sequencing requirement between these two supplies. However, the RESETN pin should be held LOW until both these supplies become stable. The RESETN pin can be tied to VDD_IO through an external resistor and to ground (GND) through an external capacitor (minimum 5 ms time constant), as shown in Figure 15. This creates a clean reset signal for power-on reset (POR). HX3 does not support internal brown-out detection. If the system requires this feature, an external reset should be provided on the RESETN pin when supplies are below their valid operating ranges. The interface follows the Inter-IC Bus specification, version 3.0, with support for the standard mode (100 kHz) and the fast mode (400 kHz) frequencies. HX3 supports I2C in the slave and master modes. The I2C interface supports the multi-master mode of operation. Both the SCL and SDA signals require external pull-up resistors based on the specification. VDD_IO for HX3 is 3.3 V and it is expected that the I2C pull-up resistors will be connected to the same supply. Figure 15. Reset Connection VDD_IO 10 k RESETN Oscillator 1.5 µF HX3 requires an external crystal with a frequency of 26 MHz and an accuracy of ±150 ppm in parallel resonant, fundamental mode. The crystal drive circuit is capable of a low-power drive level (