CYV15G0402DXB-BGC

CYP15G0402DXB CYV15G0402DXB Quad HOTLink II™ SERDES Features • Second-generation HOTLink® technology • Compliant to multiple standards — Fibre Channel, Gigabit Ethernet (IEEE802.3z), ESCON® and DVB-ASI — CYV15G0402DXB compliant to SMPTE 259M and SMPTE 292M Quad-channel transceiver operates from 195 to 1500 Mbps serial data rate — Aggregate throughput of 12 Gbps 10-bit unencoded data transport Selectable parity check/generate Four independent 10-bit channels with separate Clock and Data Recovery for each channel Selectable input clocking options MultiFrame™ Receive Framer — Comma or full K28.5 detect — Single or Multi-Byte framer for byte alignment • • • • • — Low-latency option Synchronous LVTTL parallel interface Internal phase-locked loops (PLLs) with no external PLL components Optional Phase Align Buffer in Transmit Path Differential PECL-compatible serial inputs Differential PECL-compatible serial outputs — Source matched for 50Ω transmission lines — No external resistors required — Signaling rate controlled edge rates • Compatible with — Fiber-optic modules — Copper cables 10 Serial Links — Circuit board traces • JTAG boundary scan • Built-In Self-Test (BIST) for at-speed link testing • Per-channel Link Quality Indicator — Analog signal detect • • • • • — Digital signal detect Low-power 2.5W @3.3V typical Single 3.3V supply 256-ball thermally enhanced BGA Pb-Free package option available 0.25µ BiCMOS technology • • • • • • Functional Description The CYP(V)15G0402DXB[1] Quad HOTLink II™ SERDES is a point-to-point communications building block allowing the transfer of preencoded data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195 to 1500 MBaud per serial link. Each transmit channel accepts preencoded 10-bit transmission characters in an Input Register, serializes each character, and drives it out a PECL-compatible differential line driver. Each receive channel accepts a serial data stream at a differential line receiver, deserializes the stream into 10-bit characters, optionally frames these characters to the proper 10-bit character boundaries and presents these characters to an Output register. Figure 1 illustrates typical connections between independent systems and a CYP(V)15G0402DXB. The CYV15G0402DXB satisfies the SMPTE-259M and SMPTE-292M compliance as per the EG34-1999 Pathological Test Requirements. 10 Independent Channel Transceiver Independent Channel Transceiver Independent Channel Transceiver Independent Channel Transceiver 10 10 System Host With Encoder/Decoder Note: 1. CYV15G0402DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYP15G0402DXB refers to devices that are not compliant to SMPTE 259M and SMPTE 292M pathological test requirements. CYP(V)15G0402DXB refers to both devices. Cypress Semiconductor Corporation Document #: 38-02057 Rev. *G System Host With Encoder/Decoder 10 10 CYP(V)15G0402DXB 10 10 Serial Links 10 10 10 10 Serial Links 10 10 10 10 Serial Links Cable or Optical Connections Figure 1. CYP(V)15G0402DXB HOTLink II™ System Connections • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised March 31, 2005 CYP15G0402DXB CYV15G0402DXB As a second-generation HOTLink device, the CYP(V)15G0402DXB extends the HOTLink family to faster data rates, while maintaining serial link compatibility (data, command and BIST) with other HOTLink devices.The transmit (TX) section of the CYP(V)15G0402DXB Quad HOTLink II SERDES consists of four ten bit wide channels that accept a preencoded character on every clock cycle. Transmission characters are passed from the Transmit Input Register to a Serializer. The serialized characters are output from a differential transmission line driver at a bit-rate of 10 or 20 times the input reference clock. The receive (RX) section of the CYP(V)15G0402DXB Quad HOTLink II SERDES consists of four ten bit wide channels. Each channel accepts a serial bit-stream from a PECL-compatible differential line receiver and, using a completely integrated PLL Clock Synchronizer, recovers the timing information necessary for data reconstruction. Each recovered bit-stream is deserialized and framed into characters. Recovered characters are then passed to the receiver output register, along with a recovered character clock. The parallel input interface may be configured for numerous forms of clocking to provide the high flexibility in system architecture. Each transmit and receive channel contains an independent BIST pattern generator and checker. This BIST hardware allows at-speed testing of the interface data path. HOTLink II devices are ideal for a variety of applications where parallel interfaces can be replaced with high-speed, point-to-point serial links. Some applications include interconnecting backplanes on switches, routers, servers and video transmission systems. The CYV15G0402DXB is verified by testing to be compliant to all the pathological test patterns documented in SMPTE EG34-1999, for both the SMPTE 259M and 292M signaling rates. The tests ensure that the receiver recovers data with no errors for the following patterns: 1. Repetitions of 20 ones and 20 zeros. 2. Single burst of 44 ones or 44 zeros. 3. Repetitions of 19 ones followed by 1 zero or 19 zeros followed by 1 one. CYP(V)15G0402DXB Transceiver Logic Block Diagram RXDB[9:0] RXDA[9:0] RXDC[9:0] TXDA[9:0] RXDD[9:0] TXDB[9:0] TXDC[9:0] TXDD[9:0] x10 x10 x10 x10 x10 x10 x10 x10 Phase Align Buffer Serializer Framer Deserializer Phase Align Buffer Serializer Framer Deserializer Phase Align Buffer Serializer Framer Deserializer Phase Align Buffer Serializer Framer Deserializer TX RX TX RX TX RX TX RX OUTA± INA± OUTB± INB± OUTC± INC± OUTD± Document #: 38-02057 Rev. *G Page 2 of 29 IND± CYP15G0402DXB CYV15G0402DXB Transmit Path Block Diagram REFCLK+ REFCLK– = Internal Signal TXRATE SPDSEL TXCLKO+ TXCLKO– Transmit PLL Clock Multiplier Character-Rate Clock Bit-Rate Clock BISTLE BIST Enable Latch 4 Output Enable Latch 8 Phase-Align Buffer BOE[7..0] RBIST[A..D] OELE TXCKSEL TXPERA Input Register 11 11 11 BIST LFSR TXOPA Shifter Parity Check TXDA[0..9] 10 OUTA+ OUTA– HML TXLBA TXCLKA TXPERB Phase-Align Buffer BIST LFSR Input Register Shifter Parity Check TXDB[0..9] TXOPB 11 11 11 10 OUTB+ OUTB– HML TXLBB TXCLKB TXPERC Phase-Align Buffer Input Register Shifter Parity Check TXDC[0..9] TXOPC 11 11 11 BIST LFSR 10 OUTC+ OUTC– HML TXLBC TXCLKC TXPERD Phase-Align Buffer BIST LFSR Input Register Shifter Parity Check TXDD[0..9] TXOPD 11 11 11 10 OUTD+ OUTD– HML TXLBD TXCLKD TXRST PARCTL Document #: 38-02057 Rev. *G Parity Control Page 3 of 29 CYP15G0402DXB CYV15G0402DXB Receive Path Block Diagram RXLE BOE[7:0] RX PLL Enable Latch = Internal Signal TRSTZ JTAG Boundary Scan Controller TMS TCLK TDI TDO LFIA BIST LFSR Output Register Framer Parity Control Character-Rate Clock SDASEL LPENA INA+ INA– TXLBA Receive Signal Monitor Clock and Data Recovery PLL Shifter RXDA[0..9] RXOPA COMDETA RXCLKA+ RXCLKA– RFENA LPENB ÷2 Receive Signal Monitor Framer Shifter Clock and Data Recovery PLL LFIB BIST LFSR Output Register RXDB[0..9] RXOPB COMDETB RXCLKB+ RXCLKB– INB+ INB– TXLBB RFENB LPENC ÷2 Receive Signal Monitor Framer Clock and Data Recovery PLL Shifter LFIC BIST LFSR Output Register RXDC[0..9] RXOPC COMDETC RXCLKC+ RXCLKC– INC+ INC– TXLBC RFENC LPEND ÷2 Receive Signal Monitor Clock and Data Recovery PLL RBIST[A..D] Framer Shifter LFID BIST LFSR Output Register RXDD[0..9] RXOPD COMDETD RXCLKD+ RXCLKD– IND+ IND– TXLBD RFEND FRAMCHAR RXRATE RFMODE ÷2 Document #: 38-02057 Rev. *G Page 4 of 29 CYP15G0402DXB CYV15G0402DXB Pin Configuration (Top View)[2] 1 A B C D E F G H J K L M N P R T U V W Y INCINC+ TDI TCLK VCC TXPER C 2 OUTCOUTC+ TMS 3 N/C N/C 4 N/C N/C 5 VCC VCC VCC VCC 6 INDIND+ 7 OUTDOUTD+ 8 GND GND GND GND 9 N/C N/C 10 N/C N/C 11 INAINA+ 12 OUTAOUTA+ 13 GND GND GND GND 14 N/C N/C GND GND 15 N/C N/C GND GND 16 VCC VCC VCC VCC 17 INBINB+ 18 OUTBOUTB+ 19 N/C N/C N/C N/C VCC RXOP B FRAM CHAR GND RXDB [7] RXDB [9] RXCLK BTXDB [7] GND TXDB [3] TXOP B VCC 20 N/C N/C TDO N/C VCC RXDB [1] RXDB [3] GND RXDB [4] RXCLKB + TXDB [6] TXCLK B GND TXDB [2] TXPER B VCC LPENC LPENB PARCTL SDASEL RF MODE SPD SEL BOE[7] BOE[5] BOE[3] BOE[1] BOE[6] BOE[4] BOE[2] BOE[0] TXRATE RXRATE N/C VCC BISTLE GND GND RXLE VCC RXDB [0] OELE GND TRSTZ LPEND LPENA VCC TXOP C VCC TXDC [0] VCC N/C TXDC [1] GND TXDC [3] LFIC TXDC [6] RXDC [8] GND RXDC [0] TXOP D VCC TXDD [9] RXDD [8] RXCLK D– RXCLK D+ TXDC TXCKSEL TXDC [7] [4] GND TXDC [9] RXDC [4] RXDC [5] RXDC [6] GND RXDC [3] GND TXDC [5] RXCLK CRXCLK C+ RXDC [7] GND RXDC [2] GND TXDC [2} TXDC [8] TXCLK C RXDC [9] GND RXDC [1] TXPER D VCC TXDD [2] TXDD [8] LFID RXDD [9] COMDET RXDB B [2] RXDB [5] RXDB [8] TXDB [9] GND TXDB [5] TXDB [1] VCC VCC VCC VCC VCC RXDD [4] RXDD [5] RXDD [6] RXDD [7] RXDD [3] RXDD [1] RXDD [0] RXDD [2] GND GND GND GND RXOP D RFEN C REFCLK REFCLK + TXOPA TXCLK A TXDA [1] RFEN B RFEN A TXPER A GND GND GND GND TXDA [4] TXDA [3] TXDA [2] TXDA [0] TXDA [8] TXDA [7] TXDA [6] TXDA [5] VCC VCC VCC VCC RXDA [4] RXDA [9] LFIA TXDA [9] RXDB [6] LFIB TXDB [8] GND TXDB [4] TXDB [0] VCC COMDET RXOP C C VCC TXDD [0] TXDD [3] TXDD [5] TXDD [6] VCC TXDD [1] TXDD [4] TXDD [7] TXCLK D RXOPA COMDET RXDA A [0] RXDA [5] RXCLKA – RXCLKA + RXDA [2] RXDA [6] RXDA [8] RXDA [1] RXDA [3] RXDA [7] COMDET RFEN D D TXCLKO TXRST – TXCLKO + N/C Note: 2. N/C = Do Not Connect Document #: 38-02057 Rev. *G Page 5 of 29 CYP15G0402DXB CYV15G0402DXB Pin Configuration (Bottom View)[3] 20 A B C D E F G H J K L M N P R T U V W Y N/C N/C TDO N/C VCC RXDB [1] RXDB [3] GND RXDB [4] RXCLKB + TXDB [6] TXCLK B GND TXDB [2] 19 N/C N/C N/C N/C VCC RXOP B FRAM CHAR GND RXDB [7] RXDB [9] RXCLK BTXDB [7] GND TXDB [3] 18 OUTBOUTB+ 17 INBINB+ 16 VCC VCC VCC VCC 15 N/C N/C GND GND 14 N/C N/C GND GND 13 GND GND GND GND 12 OUTAOUTA+ BOE[1] BOE[0] 11 INAINA+ BOE[3] BOE[2] 10 N/C N/C BOE[5] BOE[4] 9 N/C N/C BOE[7] BOE[6] 8 GND GND GND GND 7 OUTDOUTD+ 6 INDIND+ 5 VCC VCC VCC VCC 4 N/C N/C LPENB LPENA VCC N/C TXDC [1] GND TXDC [3] LFIC TXDC [6] RXDC [8] GND RXDC [0] TXOP D VCC 3 N/C N/C LPENC LPEND VCC TXDC [0] TXDC [4] GND TXDC [2} TXDC [8] TXCLK C RXDC [9] GND RXDC [1] TXPER D VCC TXDD [2] TXDD [8] LFID RXDD [9] 2 OUTCOUTC+ TMS TRSTZ VCC TXOP C TXCK SEL GND TXDC [5] RXCLK CRXCLK C+ RXDC [7] GND RXDC [2] 1 INCINC+ TDI TCLK VCC TXPER C TXDC [7] GND TXDC [9] RXDC [4] RXDC [5] RXDC [6] GND RXDC [3] RXRATE TXRATE RXLE VCC RXDB [0] OELE GND N/C VCC BISTLE GND GND SDASEL PARCTL SPD SEL RF MODE RXDB COMDET [2] B RXDB [6] LFIB TXDB [8] GND TXDB [4] TXDB [0] VCC RXDB [5] RXDB [8] TXDB [9] GND TXDB [5] TXDB [1] VCC RXDA [4] RXDA [9] LFIA TXDA [9] VCC VCC VCC VCC TXDA [8] TXDA [7] TXDA [6] TXDA [5] TXDA [4] TXDA [3] TXDA [2] TXDA [0] GND GND GND GND TXDA [1] RFEN B RFEN A REFCLK REFCLK + TXOP A RFEN C RXOP D GND RXDD [3] RXDD [1] RXDD [0] RXDD [2] RXDD [4] RXDD [5] RXDD [6] RXDD [7] VCC VCC VCC VCC TXPERB TXOPB VCC VCC RXOP COMDET C C VCC TXDD [1] TXDD [4] TXDD [7] TXCLK D VCC TXDD [0] TXDD [3] TXDD [5] TXDD [6] RXDA COMDET RXOP [0] A A RXDA [1] RXDA [3] RXDA [7] RXDA [2] RXDA [6] RXDA [8] RXDA [5] RXCLKA – RXCLKA + TXDD [9] RXDD [8] RXCLKD – RXCLKD + RFEN COMDET GND D D TXRST TXCLKO – N/C TXCLKO + GND GND TXPER TXCLKA A Note: 3. N/C = Do Not Connect Document #: 38-02057 Rev. *G Page 6 of 29 CYP15G0402DXB CYV15G0402DXB Pin Descriptions CYP(V)15G0402DXB Quad HOTLink II™ SERDES Name TXPERA TXPERB TXPERC TXPERD I/O Characteristics Signal Description LVTTL1 Output, changes relative to REFCLK↑[4] Transmit Path Parity Error. Active HIGH. Asserted (HIGH) if parity checking is enabled and a parity error is detected at the shifter. This output is HIGH for one transmit character clock period to indicate detection of a parity error in the character presented to the shifter. If a parity error is detected, the character in error is replaced with the 10-bit character, 1001111000, to force a corresponding bad-character detection at the remote end of the link. This replacement takes place only when parity checking is enabled (PARCTL ≠ LOW). When BIST is enabled for the specific transmit channel, BIST progress is presented on these outputs. Once every 511 character times, the associated TXPERx signal will pulse HIGH for one transmit-character clock period to indicate a complete pass through the BIST sequence. These outputs also provide indication of a transmit Phase-Align Buffer underflow or overflow. When the transmit Phase-Align Buffers are enabled (TXCKSEL ≠ LOW, or TXCKSEL = LOW and TXRATE = HIGH), if an underflow or overflow condition is detected, TXPERx for the channel in error is asserted and remains asserted until either an atomic Word Sync Sequence is transmitted or TXRST is sampled LOW to re-center the transmit Phase-Align Buffers. TXDA[9:0] TXDB[9:0] TXDC[9:0] TXDD[9:0] TXOPA TXOPB TXOPC TXOPD LVTTL Input, Transmit Data Inputs. These inputs are captured on the rising edge of the transmit synchronous, interface clock as selected by TXCKSEL and passed to the transmit shifter. sampled by the TXDx[9:0] specify the specific transmission character to be sent. respective TXCLKx↑ or REFCLK↑[4] LVTTL Input, Transmit Path Odd Parity. When parity checking is enabled (PARCTL ≠ LOW), the synchronous, ODD parity captured at these inputs is XORed with the bits on the associated TXDx bus sampled by the to verify the integrity of the captured character. respective TXCLKx↑ or REFCLK↑[4] LVTTL Output Transmit Clock Output. This true and complement clock is synthesized by the transmit PLL and is synchronous to the internal transmit character clock. It has the same frequency as REFCLK (when TXRATE = LOW), or twice the frequency of REFCLK (when TXRATE = HIGH). This output clock has no direct phase relationship to REFCLK. Transmit Path Data Signals Transmit Path Clock and Control TXCLKO± TXCKSEL Three-level Select[5] Transmit Clock Select. Static Control Input Selects the clock source used to write data into the transmit Input Register of the transmit channel(s) When LOW, all four input registers are clocked by REFCLK↑. When TXCKSEL is MID, TXCLKx↑ is used as the input register clock for the associated TXDx[9:0] and TXOPx. When HIGH, TXCLKA↑ is used to clock data into the Input Register for all channels. When TXCKSEL = MID or HIGH (TXCLKx or TXCLKA selected to clock input register), TXRATE = HIGH (Half-rate REFCLK) is an invalid mode of operation. TXCLKA TXCLKB TXCLKC TXCLKD LVTTL Clock Input asynchronous, internal pull-up Transmit Path Input Clocks. These inputs are only used when TXCKSEL ≠ LOW. These clocks must be frequency-coherent to REFCLK, but may be offset in phase. The internal operating phase of each input clock (relative to REFLCK or TXCLKO±) is adjusted when TXRST = LOW and locked when TXRST = HIGH. Notes: 4. When REFCLK is configured for half-rate operation (TXRATE = HIGH), these inputs are sampled (or the outputs change) relative to both the rising and falling edges of REFCLK 5. Three-level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and HIGH. The LOW level is usually implemented by direct connection to VSS (ground). The HIGH level is usually implemented by direct connection to VCC. When not connected or allowed to float, a three-level select input will self-bias to the MID level. Document #: 38-02057 Rev. *G Page 7 of 29 CYP15G0402DXB CYV15G0402DXB Pin Descriptions CYP(V)15G0402DXB Quad HOTLink II™ SERDES (continued) Name TXRATE I/O Characteristics Signal Description LVTTL Input, asynchronous, internal pull-up Transmit PLL Clock Rate Select. When TXRATE = HIGH, the Transmit PLL multiplies REFCLK by 20 to generate the serial bit-rate clock. When TXRATE = LOW, the transmit PLL multiples REFCLK by 10 to generate the serial bit-rate clock. See Table 3 for a list of operating serial rates. When TXCKSEL = MID or HIGH (TXCLKx or TXCLKA selected to clock input register), TXRATE = HIGH (Half-rate REFCLK) is an invalid mode of operation. TXRST LVTTL Input, asynchronous, internal pull-up, sampled by REFCLK↑ [4] Transmit Clock Phase Reset. Active LOW. When sampled LOW, the transmit Phase-align Buffers are allowed to adjust their data-transfer timing (relative to the selected input clock) to allow clean transfer of data from the Input Register to the Transmit Shifter. When TXRST is sampled HIGH, the internal phase relationship between the associated TXCLKx and the internal character-rate clock is fixed and the device operates normally. When configured for half-rate REFCLK sampling of the transmit character stream (TXCKSEL = LOW and TXRATE = HIGH), assertion of TXRST is only used to clear Phase-align buffer faults caused by highly asymmetric REFCLK periods or REFCLKs with excessive cycle-to-cycle jitter. During this alignment period, one or more characters may be added to or lost from all the associated transmit paths as the transmit Phase-align Buffers are adjusted. TXRST must be sampled LOW by a minimum of two consecutive rising edges of REFCLK to ensure the reset operation is initiated correctly on all channels. This input is ignored when both TXCKSEL and TXRATE are LOW, since the phase align buffer is bypassed. In all other configurations, TXRST should be asserted during device initialization to ensure proper operation of the Phase-align buffer. TXRST should be asserted after the assertion and deassertion of TRSTZ, after the presence of a valid TXCLKx and after allowing enough time for the TXPLL to lock to the reference clock (as specified by parameter tTXLOCK). Receive Path Data Signals RXDA[9:0] RXDB[9:0] RXDC[9:0] RXDD[9:0] COMDETA COMDETB COMDETC COMDETD RXOPA RXOPB RXOPC RXOPD RFENA RFENB RFENC RFEND RXRATE LVTTL Output, synchronous to the selected RXCLKx↑ LVTTL Output, synchronous to the selected RXCLKx↑ Three-state, LVTTL Output, synchronous to the selected RXCLKx↑ output LVTTL Input, asynchronous, internal pull-down LVTTL Input Static Control Input Receive Data Output. These outputs change following the rising edge of the selected receive interface clock. Frame Character Detected. COMDETx = HIGH indicates the presence of a Framing character in that Output Register. Receive Path Odd Parity. When parity generation is enabled (PARCTL ≠ LOW), the parity output at these pins is valid for the data on the associated RXDx bus bits. When parity generation is disabled (PARCTL = LOW) these output drivers are disabled (High-Z). Reframe Enable. Active HIGH. When HIGH the framer for the associated channel is enabled to frame as per the presently enabled framing mode and selected framing character. Receive Clock Rate Select.When LOW, the RXCLKx± recovered clock outputs are complementary clocks operating at the recovered character rate. Data for the associated receive channels should be latched on the rising edge of RXCLKx+ or falling edge of RXCLKx–. When HIGH, the RXCLKx± recovered clock outputs are complementary clocks operating at half the character rate. Data for the associated receive channels should be latched alternately on the rising edge of RXCLKx+ and RXCLKx–. Receive Path Clock and Clock Control Document #: 38-02057 Rev. *G Page 8 of 29 CYP15G0402DXB CYV15G0402DXB Pin Descriptions CYP(V)15G0402DXB Quad HOTLink II™ SERDES (continued) Name FRAMCHAR I/O Characteristics Signal Description Three-level Select [5] Framing Character Select. Used to control the type of character used for framing the Static Control Input received data streams. When MID, the framer looks for both positive and negative disparity versions of the eight-bit Comma character. When HIGH, the framer looks for both positive and negative disparity versions of the K28.5 character. Configuring FRAMCHAR to LOW is reserved for component test. RXCLKA± RXCLKB± RXCLKC± RXCLKD± RFMODE LVTTL Output Clock Receive Character Clock Output. These true and complement clocks are the Receive interface clocks which are used to control timing of data output transfers. These clocks are output continuously at either the dual-character rate (1/20th the serial bit-rate) or character rate (1/10th the serial bit-rate) of the data being received, as selected by RXRATE. Three-level Select[5] Reframe Mode Select. Used to control the type of character framing used to adjust the Static Control Input character boundaries (based on detection of one or more framing characters in the received serial bit stream). This signal operates in conjunction with the type of framing character selected. When LOW, the Low-Latency Framer is selected. This will frame on each occurrence of the selected framing character(s) in the received data stream. This mode of framing stretches the recovered character clock for one or multiple cycles to align that clock with the recovered data. When MID, the Cypress-mode Multi-Byte parallel Framer is selected. This requires a pair of the selected framing character(s), on identical 10-bit boundaries, within a span of 50 bits, before the character boundaries are adjusted. The recovered character clock remains in the same phase regardless of character offset. When HIGH, the alternate mode Multi-Byte parallel Framer is selected. This requires detection of the selected framing character(s) of the allowed disparities in the received serial bit stream, on identical 10-bit boundaries, on four directly adjacent characters. The recovered character clock remains in the same phase regardless of character offset. Device Control Signals PARCTL Three-level Select[5], Parity Check/Generate Control. Used to control the different parity check and Static Control Input generate functions. When LOW, parity checking is disabled, and the RXOPx outputs are all disabled (High-Z). When MID, theTXDx[9:0] inputs are checked (along with TXOPx) for valid ODD parity, and ODD parity is generated for the RXDx[9:0] outputs and presented on RXOPx. When HIGH, parity checking and generation are enabled. The TXDx[9:0] inputs are checked (along with TXOPx) for valid ODD parity, and ODD parity is generated for the RXDx[9:0] and COMDETx outputs and presented on RXOPx. See Table 8 for details. REFCLK± Differential LVPECL Reference Clock. This clock input is used as the timing reference for the transmit PLL. or single-ended It is also used as the centering frequency of the Range Controller block of the Receive LVCMOS input clock CDR PLLs. This input clock may also be selected to clock the transmit input interface. When driven by a a single-ended LVCMOS or LVTTL clock source, connect the clock source to either the true or complement REFCLK input and leave the alternate REFCLK input open (floating). When driven by an LVPECL clock source, the clock must be a differential clock, using both inputs. When TXCKSEL = LOW, REFCLK is also used as the clock for the parallel transmit data (input) interface. SPDSEL Three-level Select[5], Serial Rate Select. This input specifies the operating bit-rate range of both transmit and Static Control Input receive PLLs. LOW = 195–400 MBaud, MID = 400–800 MBaud, HIGH = 800–1500 MBaud. When SPDSEL is LOW, setting TXRATE = HIGH (Half-rate Reference Clock) is invalid. Document #: 38-02057 Rev. *G Page 9 of 29 CYP15G0402DXB CYV15G0402DXB Pin Descriptions CYP(V)15G0402DXB Quad HOTLink II™ SERDES (continued) Name OUTA± OUTB± OUTC± OUTD± INA± INB± INC± IND± OELE I/O Characteristics Signal Description CML Differential Output Differential Serial Data Outputs. These PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission lines or standard fiber-optic transmitter modules. Analog I/O and Control LVPECL Differential Differential Serial Data Inputs. These inputs accept the serial data stream for deseriInput alization. The INx± serial streams are passed to the receiver Clock and Data Recovery (CDR) circuits to extract the data content when INSELx = HIGH. LVTTL Input, asynchronous, internal pull-up Serial Driver Output Enable Latch Enable. When OELE = HIGH, the signals on the BOE[7:0] inputs directly control the OUTx± differential drivers. When the BOE[x] input is HIGH, the associated OUTx± differential driver is enabled. When the BOE[x] input is LOW, the associated OUTx± differential driver is powered down. When OELE returns LOW, the last values present on BOE[7:0] are captured in the internal Output enable Latch. The specific mapping of BOE[7:0] signals to transmit output enables is listed in Table 2. If the device is reset (TRSTZ is sampled LOW), the latch is reset to disable all outputs. BISTLE LVTTL Input, asynchronous, internal pull-up Transmit and Receive BIST Latch Enable. Active HIGH. When BISTLE = HIGH, the signals on the BOE[7:0] inputs directly control the transmit and receive BIST enables. When the BOE[x] input is LOW, the associated transmit or receive channel is configured to generate or compare the BIST sequence. When the BOE[x] input is HIGH, the associated transmit or receive channel is configured for normal data transmission or reception. When BISTLE returns LOW the last values present on BOE[7:0] are captured in the internal BIST Enable Latch. The specific mapping of BOE[7:0] signals to transmit and receive BIST enables is listed in Table 2. When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch is reset to disable BIST on all transmit and receive channels. RXLE LVTTL Input, asynchronous, internal pull-up Receive Channel Power-Control Latch Enable. When RXLE = HIGH, the signals on the BOE[7:0] directly control the power enables for the receive PLLs and analog logic. When the BOE[7:0] input is HIGH, the receive channels PLL’s and analog logic are active. When the BOE[7:0] input is LOW, the receive channels are in a power-down mode. When RXLE returns LOW, the last values present on BOE[7:0] are captured in the internal RX PLL Enable Latch. The specific mapping of BOE[7:0] signals to the associated receive channel enables is listed in Table 2. When the device is reset (TRSTZ = LOW), the latch is reset to disable all receive channels. BOE[7:0] LVTTL Input, asynchronous, internal pull-up BIST, Serial Output, and Receive Channel Enables. These inputs are passed to and through the Output Enable Latch when OELE is HIGH, and captured in this latch when OELE returns LOW. These inputs are passed to and through the BIST Enable Latch when BISTLE is HIGH, and captured in this latch when BISTLE returns LOW. These inputs are passed to and through the Receive Channel Enable Latch when RXLE is HIGH, and captured in this latch when RXLE returns LOW. Document #: 38-02057 Rev. *G Page 10 of 29 CYP15G0402DXB CYV15G0402DXB Pin Descriptions CYP(V)15G0402DXB Quad HOTLink II™ SERDES (continued) Name SDASEL I/O Characteristics Signal Description Three-level Select[5], Signal Detect Amplitude Level Select. Allows selection of one of three predefined static configuration amplitude trip points for a valid signal indication, as listed in Table 4. input LVTTL Input, asynchronous, internal pull-down LVTTL Output, Asynchronous Loop-Back-Enable. Active HIGH. When asserted (HIGH), the transmit serial data from the associated channel is internally routed to its respective receiver clock and data recovery (CDR) circuit. The serial output for the channel where LPENx is active is forced to differential logic “1”, and serial data inputs for that channel are ignored. Link Fault Indication Output. Active LOW. LFIx is the logical OR of four internal conditions: 1. Received serial data frequency outside expected range 2. Analog amplitude below expected levels 3. Transition density lower than expected 4. Receive Channel disabled. TRSTZ LVCMOS Input, internal pull-up Device Reset. Active LOW. Initializes all state machines and counters in the device. When sampled LOW by the rising edge of REFLCK, this input resets the internal state machines and sets the Elasticity Buffer pointers to a nominal offset. When the reset is removed (TRSTZ sampled HIGH by REFCLK↑), the status and data outputs will become deterministic in fewer than 16 REFCLK cycles. The BISTLE, OELE, and RXLE latches are reset by TRSTZ. If the Elasticity Buffer or the Phase Align Buffer are used, TRSTZ should be applied after power up to initialize the internal pointers into these memory arrays. JTAG Interface TMS LVTTL Input, internal pull-up LVTTL Input, internal pull-down Three-state LVTTL Output LVTTL Input, internal pull-up Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high for >5 TCLK cycles, the JTAG test controller is reset. The TAP controller is also reset automatically upon application of power to the device. JTAG Test Clock Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not selected. Test Data In. JTAG data input port. LPENA LPENB LPENC LPEND LFIA LFIB LFIC LFID TCLK TDO TDI Power VCC GND +3.3V Power Signal and Power Ground for all internal circuits. Input Register The bits in the Input Register for each channel have fixed bit assignments, as listed in Table 1. Each input register captures a minimum of 10 bits on each input clock cycle. When parity checking is enabled, the TXOPx parity input is also captured in the associated input register. Input Register Clocking The transmit Input Registers can be configured to accept data relative to different clock sources. The selection of the clock source is controlled by TXCKSEL. When TXCKSEL = LOW, the Input Registers for all four transmit channels are clocked by REFCLK↑[4]. When TXCKSEL = HIGH, the Input Registers for all four transmit channels are clocked with TXCLKA↑. When TXCKSEL is MID, TXCLKx↑ is used as the input register clock for the associated TXDx[9:0] and TXOPx. CYP(V)15G0402DXB HOTLink II SERDES Operation The CYP(V)15G0402DXB is a highly configurable device designed to support reliable transfer of large quantities of data using high-speed serial links from one or multiple sources to multiple destinations. This device supports four characterwide channels. CYP(V)15G0402DXB Transmit Data Path Data Path The transmit path of the CYP(V)15G0402DXB supports four character-wide data paths. These four data paths are internally unencoded and require 10-bit input data that may be pre-encoded or scrambled to achieve sufficient transition density. Document #: 38-02057 Rev. *G Page 11 of 29 CYP15G0402DXB CYV15G0402DXB Table 1. Input Register Bit Mapping Signal Name Bus Weight [6] 20 TXDx[0] (LSB) TXDx[1] 21 TXDx[2] 22 TXDx[3] 23 TXDx[4] 24 TXDx[5] 25 TXDx[6] 26 TXDx[7] 27 TXDx[8] 28 29 TXDx[9] (MSB) [7] TXOPx Phase-Align Buffer Data from the Input Registers is normally routed to the associated Phase-Align Buffer. When the transmit paths are operated synchronous to REFCLK↑ (TXCKSEL = LOW and TXRATE = LOW), the Phase-Align Buffers are bypassed and data is passed directly to the Parity Check and Serializer blocks to reduce latency. When an Input-Register clock with an uncontrolled phase relationship to REFCLK is selected (TXCKSEL ≠ LOW) or if data is captured on both edges of REFCLK (TXRATE = HIGH), the Phase-Align Buffers are enabled. These buffers are used to absorb clock phase differences between the presently selected input clock and the internal character clock. Initialization of these Phase-Align Buffers takes place when the TXRST input is sampled LOW by two consecutive rising edges of REFCLK↑. When TXRST is returned HIGH, the present input clock phase relative to REFCLK is set. TXRST is an asynchronous input, but is sampled internally to synchronize it to the internal transmit path state machines. Once set, the input clocks are allowed to skew in time up to half a character period in either direction relative to REFCLK; i.e., ±180°. This time shift allows the delay paths of the character clocks (relative to REFCLK) to change due to operating voltage and temperature, while not affecting reliable data transfer. If the phase offset, between the initialized location of the input clock and REFCLK↑, exceeds the skew handling capabilities of the Phase-Align Buffer, an error is reported on the associated TXPERx output. This output indicates a continuous error until the Phase-Align Buffer is reset. While the error remains active, the transmitter for the associated channel will output a continuous 10-bit character, 1001111000b, to indicate to the remote receiver that an error condition is present in the link. Parity Support In addition to the ten data bits that are captured at each channel, a TXOPx input is also available on each channel. This allows the CYP(V)15G0402DXB to support ODD parity 10B Name a b c d e i f g h j checking for each channel. When PARCTL = LOW, parity checking is disabled. When PARCTL = MID or HIGH, parity is checked on the TXDx[9:0] and TXOPx bits. If parity checking is enabled (PARCTL ≠ LOW) and a parity error is detected, the 10-bit character in error is replaced with the 1001111000b pattern (an invalid character). Transmit BIST The transmitter interfaces contain internal pattern generators that can be used to validate both device and link operation. These generators are enabled by the associated BOE[x] signals listed in Table 2 (when the BISTLE latch enable input is HIGH). When enabled, a register in the associated transmit channel becomes a signature pattern generator by logically converting to a Linear Feedback Shift Register (LFSR). This LFSR generates a 511-character sequence that includes all Data and Special Character codes, including the explicit violation symbols. This provides a predictable yet pseudo-random sequence that can be matched to an identical LFSR in the attached Receiver(s). When the BISTLE signal is HIGH, any BOE[x] input that is LOW enables the BIST generator in the associated transmit channel (or the BIST checker in the associated receive channel). When BISTLE returns LOW, the values of all BOE[x] signals are captured in the BIST Enable Latch. These values remain in the BIST Enable Latch until BISTLE is returned HIGH to open the latch. A device reset (TRSTZ sampled LOW) presets the BIST Enable Latch to disable BIST on all channels. All data and data-control information present at the associated TXDx[9:0] inputs are ignored when BIST is active on that channel. Table 2. Output Enable, BIST, and Receive Channel Enable Signal Map Output Controlled (OELE) X OUTD± X OUTC± X OUTB± X OUTA± BIST Channel Enable (BISTLE) Transmit D Receive D Transmit C Receive C Transmit B Receive B Transmit A Receive A Receive PLL Channel Enable (RXLE) X Receive D X Receive C X Receive B X Receive A BOE Input BOE[7] BOE[6] BOE[5] BOE[4] BOE[3] BOE[2] BOE[1] BOE[0] Serial Output Drivers The serial interface Output Drivers use differential CML (Current Mode Logic) to provide a source-matched driver for the transmission lines. These drivers accept data from the Transmit Shifters. These outputs have signal swings equivalent to that of standard PECL drivers and are capable of driving AC-coupled optical modules or transmission lines. Notes: 6. LSB is shifted out first. 7. The TXOPx inputs are also captured in the associated Input Register, but their interpretation is under the separate control of PARCTL. Document #: 38-02057 Rev. *G Page 12 of 29 CYP15G0402DXB CYV15G0402DXB When configured for local loopback (LPENx = HIGH), the output drivers for all enabled ports are configured to drive a static differential logic-1. Each output can be enabled or disabled separately through the BOE[7:0] inputs, as controlled by the OELE latch-enable signal. When OELE is HIGH, the signals present on the BOE[7:0] inputs are passed through the Serial Output Enable Latch to control the Serial Output Drivers. The BOE[7:0] input associated with a specific OUTx± driver is listed in Table 2. When OELE is HIGH and BOE[x] is HIGH, the associated Serial Driver is enabled. When OELE is HIGH and BOE[x] is LOW, the associated driver is disabled and internally powered down, the associated internal logic for that channel is also powered down. When OELE returns LOW, the values present on the BOE[7:0] inputs are latched in the Output Enable Latch, and remain there until OELE returns HIGH to enable the latch. A device reset (TRSTZ sampled LOW) clears this latch and disables all output drivers. NOTE: When all transmit channels are disabled (i.e., both serial output drivers disabled in all channels) and a serial output driver is re-enabled, the data on the Serial Drivers may not meet all timing specifications for up to 200 µs. Transmit PLL Clock Multiplier The Transmit PLL Clock Multiplier accepts a character-rate or half-character-rate external clock at the REFCLK input, and multiples that clock by 10 or 20 (as selected by TXRATE) to generate a bit-rate clock for use by the Transmit Shifter. It also provides a character-rate clock used by the transmit paths. The clock multiplier PLL can accept a REFCLK input between 19.5 MHz and 150 MHz, however, this clock range is limited by the operating mode of the CYP(V)15G0402DXB clock multiplier (controlled by TXRATE) and by the level on the SPDSEL input. When TXCKSEL = MID or HIGH (TXCLKx or TXCLKA selected to clock input register), TXRATE = HIGH (Half-rate REFCLK) is an invalid mode of operation. SPDSEL is a three-level select[5] (ternary) input that selects one of three operating ranges for the serial data outputs and inputs. The operating serial signaling-rate and allowable range of REFCLK frequencies is listed in Table 3. Table 3. Operating Speed Settings REFCLK Frequency (MHz) reserved 19.5–40 20–40 40–80 40–75 80–150 800–1500 400–800 Signaling Rate (MBaud) 195-400 The REFCLK± input is a differential input with each input internally biased to 1.4V. If the REFCLK+ input is connected to a TTL, LVTTL, or LVCMOS clock source, the input signal is recognized when it passes through the internally biased reference point and REFCLK- can be left floating. When both the REFCLK+ and REFCLK– inputs are connected, the clock source must be a differential clock. This can be either a differential LVPECL clock that is DC- or AC-coupled, or a differential LVTTL or LVCMOS clock. By connecting the REFCLK– input to an external voltage source or resistive voltage divider, it is possible to adjust the reference point of the REFCLK+ input for alternate logic levels. When doing so it is necessary to ensure that the input differential crossing point remains within the parametric range supported by the input. CYP(V)15G0402DXB Receive Data Path Serial Line Receivers A differential line receiver, INx±, is available on each channel for accepting a serial bit stream. The Serial Line Receiver inputs are differential, and can accommodate wire interconnect and filtering losses or transmission line attenuation greater than 16 dB. For normal operation, these inputs should receive a signal of at least VIDIFF > 100 mV, or 200 mV peak-to-peak differential. Each Line Receiver can be DC- or AC-coupled to +3.3V powered fiber-optic interface modules (any ECL/PECL family, not limited to 100K PECL) or AC-coupled to +5V powered optical modules. The common-mode tolerance of these line receivers accommodates a wide range of signal termination voltages. Each receiver provides internal DC-restoration, to the center of the receiver’s common mode range, for AC-coupled signals. The local loopback inputs (LPENx) for each channel allows the serial transmit data outputs to be routed internally back to the Clock and Data Recovery circuit associated with that channel. When configured for local loopback, all transmit Serial Driver outputs are forced to output a differential logic-1. This prevents local diagnostic patterns from being broadcast to attached remote receivers. Signal Detect/ Link Fault Each selected Line Receiver is simultaneously monitored for • analog amplitude above limit specified by SDASEL • transition density greater than specified limit • CDR tracking data within expected frequency range as defined by REFCLK and TXRATE (± 1500 ppm)[8] • receive channel enabled All of these conditions must be valid for the Signal Detect block to indicate a valid signal is present. This status is presented on the LFIx (Link Fault Indicator) output associated with each receive channel. SPDSEL LOW MID (Open) HIGH TXRATE 1 0 1 0 1 0 Note: 8. REFCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time. REFCLK must be within ±1500 PPM (±0.15%) of the remote transmitter’s PLL reference (REFCLK) frequency. Although transmitting to a HOTLink II receiver necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500 ppm, the stability of the crystal needs to be within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. For example, to be IEEE 802.3z Gigabit Ethernet compliant, the frequency stability of the crystal needs to be within ±100 ppm. Document #: 38-02057 Rev. *G Page 13 of 29 CYP15G0402DXB CYV15G0402DXB Analog Amplitude While most signal monitors are based on fixed constants, the analog amplitude level detection is adjustable. This allows operation with highly attenuated signals, or in high-noise environments. This adjustment is made through the SDASEL signal, a three-level select[5] input, which sets the trip point for the detection of a valid signal at one of three levels, as listed in Table 4. This control input affects the analog monitors for all receive channels. When a particular channel is configured for local loopback (LPENx = HIGH), no line receivers are selected, and the LFIx output for each channel reports only the receive VCO frequency out-of-range and transition density status of the associated transmit signal. When local loopback is active, the Analog Signal Detect Monitors are disabled. Table 4. Analog Amplitude Detect Valid Signal Levels[9] SDASEL LOW HIGH Typical Signal with Peak Amplitudes Above 140 mV p-p differential 420 mV p-p differential rate, the LFIx output will be asserted LOW. While the PLL is attempting to re-lock to the incoming data stream, LFIx may be either HIGH or LOW (depending on other factors such as transition density and amplitude detection) and the recovered byte clock (RXCLKx) may run at an incorrect rate (depending on the quality or existence of the input serial data stream). After a valid serial data stream is applied, it may take up to one RANGE CONTROL SAMPLING PERIOD before the PLL locks to the input data stream, after which LFIx should be HIGH. Receive Channel Enabled The CYP(V)15G0402DXB contains four receive channels that can be independently enabled and disabled. Each channel can be enabled or disabled separately through the BOE[7:0] inputs, as controlled by the RXLE latch-enable signal. When RXLE is HIGH, the signals present on the BOE[7:0] inputs are passed through the Receive Channel Enable Latch to control the PLLs and logic of the associated receive channel. The BOE[7:0] input associated with a specific receive channel is listed in Table 2. When RXLE is HIGH and BOE[x] is HIGH, the associated receive channel is enabled to receive and recover a serial stream. When RXLE is HIGH and BOE[x] is LOW, the associated receive channel is disabled and powered down. Any disabled channel will indicate an asserted LFIx output. When RXLE returns LOW, the values present on the BOE[7:0] inputs are latched in the Receive Channel Enable Latch, and remain there until RXLE returns HIGH to open the latch again.[10] Clock/Data Recovery The extraction of a bit-rate clock and recovery of bits from each received serial stream is performed by a separate Clock/Data Recovery (CDR) block within each receive channel. The clock extraction function is performed by embedded phase-locked loops (PLLs) that track the frequency of the transitions in the incoming bit streams and align the phase of their internal bit-rate clocks to the transitions in the selected serial data streams. Each CDR accepts a character-rate (bit-rate ÷ 10) or half-character-rate (bit-rate ÷ 20) reference clock from the REFCLK input. This REFCLK input is used to • ensure that the VCO (within the CDR) is operating at the correct frequency. • to reduce PLL acquisition time • and to limit unlocked frequency excursions of the VCO when there is no input data present at the selected Serial Line Receiver. Regardless of the type of signal present, the CDR will attempt to recover a data stream from it. If the frequency of the recovered data stream is outside the limits of the range control monitor, the CDR will switch to track REFCLK instead of the data stream. Once the CDR output (RXCLKx) frequency returns back close to REFCLK frequency, the CDR input will be switched back to track the input data stream. MID (Open) 280 mV p-p differential Transition Density The Transition Detection logic checks for the absence of any transitions spanning greater than six transmission characters (60 bits). If no transitions are present in the data received on a channel, the Transition Detection logic for that channel will assert LFIx. The LFIx output remains asserted until at least one transition is detected in each of three adjacent received characters. Range Controls The Clock/Data Recovery (CDR) circuit includes logic to monitor the frequency of the Phase Locked Loop (PLL) Voltage Controlled Oscillator (VCO) used to sample the incoming data stream. This logic ensures that the VCO operates at, or near the rate of the incoming data stream for two primary cases: • when the incoming data stream resumes after a time in which it has been “missing” • when the incoming data stream is outside the acceptable frequency range To perform this function, the frequency of the VCO is periodically sampled and compared to the frequency of the REFCLK input. If the VCO is running at a frequency beyond +1500ppm[8] as defined by the reference clock frequency, it is periodically forced to the correct frequency (as defined by REFCLK, SPDSEL, and TXRATE) and then released in an attempt to lock to the input data stream. The sampling and relock period of the Range Control is calculated as follows: RANGE CONTROL SAMPLING PERIOD = (REFCLKPERIOD) * (16000). During the time that the Range Control forces the PLL VCO to run at REFCLK*10 (or REFCLK*20 when TXRATE = HIGH) Notes: 9. The peak amplitudes listed in this table are for typical waveforms that have generally 3 – 4 transitions for every ten bits. In a worse case environment the signals may have a sign-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase the values in the table above by approximately 100 mV. 10. When a disabled receive channel is reenabled, the status of the associated LFIx output and data on the parallel outputs for the associated channel may be indeterminate for up to 2 ms. Document #: 38-02057 Rev. *G Page 14 of 29 CYP15G0402DXB CYV15G0402DXB In case no data is present at the input, this switching behavior may result in brief RXCLKx frequency excursions from REFCLK. However, the validity of the input data stream is indicated by the LFIx output. The frequency of REFCLK is required to be within ±1500ppm[8] of the frequency of the clock that drives the REFCLK input of the remote transmitter to ensure a lock to the incoming data stream. Deserializer/Framer Each CDR circuit extracts bits from the associated serial data stream and clocks these bits into the Shifter/Framer at the bit-clock rate. When enabled, the Framer examines the data stream, looking for one or more Comma or K28.5 characters at all possible bit positions. The location of this character in the data stream is used to determine the character boundaries of all following characters. Framing Character The CYP(V)15G0402DXB allows selection of one of two combinations of framing characters to support requirements of different interfaces. The selection of the framing character is made through the FRAMCHAR input. Table 5. Framing Character Selector Bits Detected in Framer FRAMCHAR LOW MID (Open) HIGH Character Name Bits Detected Reserved for test Comma+ or Comma+K28.5 or -K28.5 00111110XX[11] or 11000001XX 0011111010 or 1100000101 output clock (RXRATE = LOW), the output of properly framed characters may be delayed by up to nine character-clock cycles from the detection of the selected framing character. When operated with a half-character-rate output clock (RXRATE = HIGH), the output of properly framed characters may be delayed by up to 14 character-clock cycles from the detection of the selected framing character.[8] When RFMODE is MID (open), the Cypress-mode Multi-Byte Framer is selected. The required detection of multiple framing characters makes the associated link much more robust to incorrect framing due to aliased framing characters in the data stream. In this mode, the Framer does not adjust the character clock boundary, but instead aligns the character to the already recovered character clock. This ensures that the recovered clock will not contain any significant phase changes or hops during normal operation or framing, and allows the recovered clock to be replicated and distributed to other external circuits or components using PLL-based clock distribution elements. In this framing mode, the character boundaries are only adjusted if the selected framing character is detected at least twice within a span of 50 bits, with both instances on identical 10-bit character boundaries. When RFMODE = HIGH, the Alternate-mode Multi-Byte Framer is enabled. Like the Cypress-mode Multi-Byte Framer, multiple framing characters must be detected before the character boundary is adjusted. In this mode, the Framer does not adjust the character clock boundary, but instead aligns the character to the already recovered character clock. In this mode, the data stream must contain a minimum of four of the selected framing characters, received as consecutive characters, on identical 10-bit boundaries, before character framing is adjusted. Framing is enabled for a channel when the associated RFENx input is HIGH. When RFENx is LOW, the framer for the associated channel is disabled. When a framer is disabled, no changes are made to the recovered character boundaries on that channel, regardless of the presence of framing characters in the data stream. Receive BIST Operation The Receiver interfaces contain internal pattern generators that can be used to validate both device and link operation. These generators are enabled by the associated BOE[x] signals listed in Table 2 (when the BISTLE latch enable input is HIGH). When enabled, a register in the associated receive channel becomes a pattern generator and checker by logically converting to a Linear Feedback Shift Register (LFSR). This LFSR generates a 511-character sequence that includes all Data and Special Character codes, including the explicit violation symbols. This provides a predictable yet pseudo-random sequence that can be matched to an identical LFSR in the attached Transmitter(s). When synchronized with the received data stream, the associated Receiver compares each received character with each character generated by the LFSR and indicates compare errors and BIST status at the COMDETx and RXDx[1:0] bits of the Output Register[12]. The specific bit combinations of these framing characters are listed in Table 5. When the specific bit combination of the selected framing character is detected by the Framer, the boundaries of the characters present in the received data stream are known. Framer The Framer on each channel operates in one of three different modes, as selected by the RFMODE input. In addition, the Framer for each channel may be enabled or disabled through the RFENx input. When RFENx = LOW, the framer in that receive path is disabled, and no combination of bits in a received data stream will alter the character boundaries. When RFENx = HIGH, the Framer selected by RFMODE is enabled for that channel. When RFMODE = LOW, the Low-Latency Framer is selected. This Framer operates by stretching the recovered character clock until it aligns with the received character boundaries. In this mode, the Framer starts its alignment process on the first detection of the selected framing character. To reduce the impact on external circuits that make use of a recovered clock, the clock period is not stretched by more than two bit-periods in any one clock cycle. When operated with a character-rate Notes: 11. The standard definition of a Comma contains only seven bits. However, since all valid Comma characters within the 8B/10B character set also have the eighth bit as an inversion of the seventh bit, the compare pattern is extended to a full eight bits to reduce the possibility of a framing error. 12. When Receive BIST is enabled on a channel, the Low-Latency Framer must not be enabled. The BIST sequence contains an aliased K28.5 framing character, which causes the Receiver to update its character boundaries incorrectly. Document #: 38-02057 Rev. *G Page 15 of 29 CYP15G0402DXB CYV15G0402DXB When the BISTLE signal is HIGH, any BOE[x] input that is LOW enables the BIST generator/checker in the associated Receive channel (or the BIST generator in the associated Transmit channel). When BISTLE returns LOW, the values of all BOE[x] signals are captured in the BIST Enable Latch. These values remain in the BIST Enable Latch until BISTLE is returned HIGH. All captured signals in the BIST Enable Latch are set HIGH (i.e., BIST is disabled) following a device reset (TRSTZ is switched LOW). When BIST is first recognized as being enabled in the Receiver, the LFSR is preset to the BIST-loop start-code of D0.0. This code D0.0 is sent only once per BIST loop. The status of the BIST progress and any character mismatches is presented on the COMDETx and RXDx[1:0] status outputs. COMDETx, RXDx[1:0] indicates 010b or 100b for one character period per BIST loop to indicate loop completion. This status can be used to check test pattern progress. The status reported by the BIST state machine on COMDETX and RXDx[1:0] are listed in Table 6. The specific patterns checked by each receiver are described in detail in the Cypress application note “HOTLink Built-In Self-Test.” The sequence compared by the CYP(V)15G0402DXB is identical to that in the CY7B933 and CY7C924DX, allowing interoperable systems to be built when used at compatible serial signaling rates. If the number of invalid characters received ever exceeds the number of valid characters by 16, the receive BIST state machine aborts the compare operations and resets the LFSR to the D0.0 state to look for the start of the BIST sequence again. The BIST state machine requires the characters to be correctly framed for it to detect the BIST sequence. If the Low Latency Framer is enabled (RFMODE = LOW), the Framer will misalign to an aliased K28.5 framing character within the BIST sequence. If the Alternate Multi-Byte Framer is enabled (RFMODE = HIGH), it is necessary to frame the receiver before BIST is enabled. Power Control The CYP(V)15G0402DXB supports user control of the powered up or down state of each transmit and receive channel. The receive channels are controlled by the RXLE signal and the values present on the BOE[7:0] bus. The transmit channels are controlled by the OELE signal and the values present on the BOE[7:0] bus. Powering down unused channels will save power and reduce system heat generation. Controlling system power dissipation will improve the system performance. Receive Channels When RXLE is HIGH, the signals on the BOE[7:0] inputs directly control the power enables for the receive PLLs and analog circuits. When a BOE[7:0] input is HIGH, the associated receive channel [A through D] PLL and analog logic are active. When a BOE[7:0] input is LOW, the associated receive channel [A through D] PLL and analog circuits are powered down. When RXLE returns LOW, the last values present on the BOE[7:0] inputs are captured. The specific BOE[7:0] input signal associated with a receive channel is listed in Table 2. Any disabled receive channel will indicate a constant LFIx output. Table 6. BIST Status Bits Status COMDETx RXDx[0] RXDx[1] Priority BIST Mode 7 BIST Data Compare. Data Character compared correctly. 7 BIST Command Compare. Command Character compared correctly. 2 BIST Last Good. Last Character of BIST sequence detected and valid. 5 Reserved 4 BIST Last Bad. Last Character of BIST sequence was detected invalid. 1 BIST Start. RXBISTEN recognized on this channel, but character compares have not yet commenced. Also presented when the receive PLL is tracking REFCLK instead of the selected data stream. 6 BIST Error. While comparing characters, a mismatch was found in one or more of the decoded character bits. 3 BIST Wait. The receiver is comparing characters. but has not yet found the start of BIST character to enable the LFSR. Description 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 When a disabled receive channel is re-enabled, the status of the associated LFIx output and data on the parallel outputs for the associated channel may be indeterminate for up to 2 ms. Transmit Channels When OELE is HIGH, the signals on the BOE[7:0] inputs directly control the power enables for the Serial Drivers. When a BOE[x] input is HIGH, the associated Serial Driver is enabled. When a BOE[x] input is LOW, the associated Serial Driver is disabled and powered down. If the Serial Driver of a channel is disabled, the internal logic for that channel is powered down. When OELE returns LOW, the values present on the BOE[7:0] inputs are latched in the Output Enable Latch. Device Reset State When the CYP(V)15G0402DXB is reset by assertion of TRSTZ, the Transmit Enable and Receive Enable Latches are both cleared, and the BIST Enable Latch is preset. In this state, all transmit and receive channels are disabled, and BIST is disabled on all channels. Following a device reset, it is necessary to enable the transmit and receive channels used for normal operation. This can be done by sequencing the appropriate values on the BOE[7:0] inputs while the OELE and RXLE signals are raised and lowered. For systems that do not require dynamic control of power, or want the part to power up in a fixed configuration, it is also possible to strap the RXLE and OELE control signals HIGH to permanently enable their associated latches. Connection of the associated BOE[7:0] signals to a stable HIGH will then enable the respective transmit and receive channels as soon as the TRSTZ signal is deasserted. Document #: 38-02057 Rev. *G Page 16 of 29 CYP15G0402DXB CYV15G0402DXB Output Bus Each receive channel presents a 12-signal output bus consisting of: • a 10-bit data bus • a COMMA detect indicator • a parity bit. The signals present on this output bus are shown inTable 7. Table 7. Output Register Bit Assignment Signal Name RXOPx[13] COMDETx[13] RXDx[0] (LSB) RXDx[1] RXDx[2] RXDx[3] RXDx[4] RXDx[5] RXDx[6] RXDx[7] RXDx[8] RXDx[9] (MSB) 20 21 22 23 24 25 26 27 28 29 a b c d e i f g h j Signal Name COMDETx RXDx[0] RXDx[1] RXDx[2] RXDx[3] RXDx[4] RXDx[5] RXDx[6] RXDx[7] RXDx[8] RXDx[9] BIST Status State Machine When a receive path is enabled to look for and compare the received data stream with the BIST pattern, the COMDETx and RXDx[1:0] bits identify the present state of the BIST compare operation. The BIST state machine has multiple states, as shown in Figure 2 and Table 6. When the receive PLL detects an out-of-lock condition, the BIST state is forced to the Start-of-BIST state, regardless of the present state of the BIST state machine. If the number of detected errors ever exceeds the number of valid matches by greater than 16, the state machine is forced to the WAIT_FOR_BIST state where it monitors the interface for the first character (D0.0) of the next BIST sequence. Also, if the Elasticity Buffer ever hits an overflow/underflow condition, the status is forced to the BIST_START until the buffer is re-centered (approximately nine character periods). X X X X X X X X X X Bus Weight 10B Name Parity Generation In addition to the 10-bit data and COMDETx status bit, an RXOPx ODD parity output can also be generated for each channel. Parity can be generated on • the RXDx[9:0] character • RXDx[9:0] character and COMDETx status bit. These modes differ in the number of bits which are included in the parity calculation. Only ODD parity is provided which ensures that at least one bit of the data bus is always a logic-1. Those bits covered by parity generation are listed in Table 8. Parity generation is enabled through the three-level select PARCTL input. When PARCTL = LOW, parity checking is disabled, and the RXOPx outputs are all disabled (High-Z). When PARCTL is MID, ODD parity is generated for the RXDx[9:0] bits. When PARCTL is HIGH, ODD parity is generated for both the RXDx[9:0] bits and the associated COMDETx signal. Table 8. Output Register Parity Generation Receive Parity Generate Mode (PARCTL) LOW[14] MID HIGH X[15] X X X X X X X X X X The framed 10-bit value is presented to the associated Output Register, along with a status output (COMDETx) indicating if the character in the output register matches the selected framing characters. The COMDETx output is HIGH when the character in the Output Register of the associated channel contains the selected framing character at the proper character boundary, and LOW for all other bit combinations. When the Low-Latency Framer and half-rate receive port clocking are also enabled (RFMODE = LOW, RXRATE = HIGH), the Framer will stretch the recovered clock to the nearest 20-bit boundary such that the rising edge of RXCLKx+ occurs when COMDETx is present on the associated output bus. When the Cypress or Alternate Mode Framer is enabled and half-rate receive port clocking are also enabled (RFMODE ≠ LOW and RXRATE = HIGH), the output clock is not modified when framing is detected, but a single pipeline stage may be added or subtracted from the data stream by the Framer logic such that the rising edge of RXCLKx+ occurs when COMDETx is present on the associated output bus. This adjustment only occurs when the Framer is enabled (RFEN = HIGH). When the Framer is disabled, the clock boundaries are not adjusted, and COMDETx may be asserted during the rising edge of RXCLK– (if an odd number of characters were received following the initial framing). Notes: 13. The RXOPx and COMDETx outputs are also driven from the associated output register, but their generation and interpretation are separate from the data bus. 14. Receive path parity output drivers are disabled when PARCTL is low 15. When BIST is not enabled,COMDETx is usually driven to a logic 0, but will be driven high when the character in the output buffer is the selected framing character. Document #: 38-02057 Rev. *G Page 17 of 29 CYP15G0402DXB CYV15G0402DXB JTAG Support The CYP(V)15G0402DXB contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, only boundary scan is supported. This capability is present only on the LVTTL inputs, LVTTL outputs and REFCLK± input. The high-speed serial signals are not part of the JTAG test chain. JTAG ID The JTAG device ID for the CYP(V)15G0402DXB is ‘1C801069’hex. Three-level Select Inputs Each three-level select input reports as two bits in the scan register. These bits report the LOW, MID, and HIGH state of the associated input as 00, 10, and 11, respectively. Document #: 38-02057 Rev. *G Page 18 of 29 CYP15G0402DXB CYV15G0402DXB Monitor Data Received COMDETX,RXDx[1:0] = BIST_WAIT (111) COMDETX,RXDx[1:0] = BIST_START (101) Receive BIST Detected LOW RX PLL Out of Lock No Start of BIST Detected YES COMDETX,RXDx[1:0] = BIST_COMMAND_COMPARE (001) OR BIST_DATA_COMPARE (000) Compare Next Character Mismatch COMDETX,RXDx[1:0] = Match BIST_COMMAND_COMPARE (001) Yes Auto-Abort Condition No Data or Command Command Data COMDETX,RXDx[1:0] = BIST_DATA_COMPARE (000) End-of-BIST State End-of-BIST State No Yes, COMDETX,RXDx[1:0] = BIST_LAST_BAD (100) Yes, COMDETX,RXDx[1:0] = BIST_LAST_GOOD (010) No, COMDETX,RXDx[1:0] = BIST_ERROR (110) Figure 2. Receive BIST State Machine Document #: 38-02057 Rev. *G Page 19 of 29 CYP15G0402DXB CYV15G0402DXB Maximum Ratings (Above which the useful life may be impaired. User guidelines only, not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C DC Voltage Applied to LVTTL Outputs in High−Z State .......................................–0.5V to VCC + 0.5V Supply Voltage to Ground Potential ............... –0.5V to +3.8V Output Current into LVTTL Outputs (LOW)..................60 mA DC Input Voltage....................................–0.5V to VCC + 0.5V Static Discharge Voltage.......................................... > 2000 V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Power-up Requirements The CYP(V)15G0402DXB requires one power supply. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 5% 3.3V ± 5% CYP(V)15G0402DXB DC Electrical Characteristics Over the Operating Range Parameter LVTTL-compatible Outputs VOHT VOLT IOST IOZL VIHT VILT IIHT IILT IIHPDT IILPUT VDIFF[17] VIHHP VILLP VCOMREF[18] VIHH VIMM VILL IIHH IIMM IILL Output HIGH Voltage Output LOW Voltage Output Short Circuit Current High-Z Output Leakage Current Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current REFCLK Input, VIN = VCC Other Inputs, VIN = VCC REFCLK Input, VIN = 0.0V Other Inputs, VIN = 0.0V Input HIGH Current with internal pull-down VIN = VCC Input LOW Current with internal pull-up Input Differential Voltage Highest Input HIGH Voltage Lowest Input LOW voltage Common Mode Range Three-level Input HIGH Voltage Three-level Input MID Voltage Three-level Input LOW Voltage Input High Current Input MID Current Min. ≤ VCC ≤ Max. Min. ≤ VCC ≤ Max. Min. ≤ VCC ≤ Max. Vin = Vcc Vin = Vcc/2 –50 Typ. VCC – 0.5 VCC – 0.5 VIN = 0.0V 400 1.2 0.0 1.0 0.87 * VCC 0.47 * VCC 0.0 IOH = –4 mA, VCC = Min. IOL = 4 mA, VCC = Min. VOUT = 0V[16] 2.4 0 –20 –20 2.0 –0.5 VCC 0.4 –100 20 VCC + 0.3 0.8 +1.5 +40 –1.5 –40 +200 –200 VCC VCC VCC/2 VCC – 1.2V VCC 0.53 * VCC 0.13 * VCC 200 50 –200 Max. VCC – 0.2 VCC – 0.2 V V mA mA V V mA µA mA µA µA µA mV V V V V V V µA µA µA Unit V V Description Test Conditions Min. Max. Unit LVTTL-compatible Inputs LVDIFF Inputs: REFCLK± Three-level Inputs Input LOW Current Vin = GND Differential CML Serial Outputs: OUTA±, OUTB±, OUTC±, OUTD± VOHC Output HIGH Voltage 100Ω differential load 150Ω differential load Notes: 16. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. 17. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the true (+) input is more positive than the complement (–) input. A logic-0 exists when the complement (-) input is more positive than true (+) input. 18. The common mode range defines the allowable range of REFCLK+ and REFCLK– when REFCLK+ = REFCLK–. This marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0. Document #: 38-02057 Rev. *G Page 20 of 29 CYP15G0402DXB CYV15G0402DXB CYP(V)15G0402DXB DC Electrical Characteristics Over the Operating Range (continued) Parameter VOLC VODIF Description Output LOW Voltage Output Differential Voltage |(OUT+) – (OUT–)| Input Differential Voltage |(IN+) – (IN-)| Highest Input HIGH Voltage Lowest Input LOW Voltage Input HIGH Current Input LOW Current [19, 20] Test Conditions 100Ω differential load 150Ω differential load 100Ω differential load 150Ω differential load Min. VCC – 1.1 VCC – 1.1 450 560 100 VCC – 2.0 Max. VCC – 0.7 VCC – 0.7 900 1000 1200 VCC Unit V V mV mV mV V V mA mA V Unit mA mA mA mA Differential Serial Line Receiver Inputs: INA±, INB±, INC±, IND± VDIFFS[17] VIHE VILE IIHE IILE VCOM VIN = VIHH Max. VIN = VILL Min. –700 VCC − 1.95 Typ.[22] 1350 VCC − 0.05 Max.[21] 1060 1100 830 1060 1100 Common mode input range Power Supply ICC ICC Power Supply Current REFCLK = Max. Power Supply Current REFCLK = 125 MHz Commercial Industrial Commercial Industrial 870 Test Loads and Waveforms 3.3V R1 R1 = 590Ω R2 = 435Ω CL C L ≤ 7 pF (Includes fixture and probe capacitance) 3.0V Vth = 1.4V GND ≤ 1 ns 2.0V 0.8V 2.0V 0.8V Vth = 1.4V VILE ≤ 1 ns Note 24 RL = 100Ω RL R2 Note 23 (b) CML Output Test Load VIHE 80% 20% VILE 80% Note 23 (a) LVTTL Output Test Load VIHE 20% ≤ 270 ps ≤ 270 ps (c) LVTTL Input Test Waveform (d) CML/LVPECL Input Test Waveform Notes: 19. The common mode range defines the allowable range of INPUT+ and INPUT– when INPUT+ = INPUT–. This marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0. 20. Not applicable for AC-coupled interfaces. For AC-coupled interfaces, VDIFFS requirement still needs to be satisfied. 21. Maximum ICC is measured with VCC = MAX, parallel outputs unloaded, RX channels enabled, and Serial Line Drivers enabled and sending a continuous alternating 01 pattern to the associated receive channel. 22. Typical ICC is measured under similar conditions except with VCC = 3.3V, TA = 25°C, parallel outputs unloaded, RX channels enabled, and Serial Line Drivers enabled and sending a continuous alternating 01 pattern to the associated receive channel. 23. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only. 5-pF differential load reflects tester capacitance, and is recommended at low data rates only. 24. The LVTTL switching threshold is 1.4V. All timing references are made relative to the point where the signal edges crosses the threshold voltage. Document #: 38-02057 Rev. *G Page 21 of 29 CYP15G0402DXB CYV15G0402DXB CYP(V)15G0402DXB AC Characteristics Over the Operating Range CYP(V)15G0402DXB Transmitter LVTTL Switching Characteristics Over the Operating Range Parameter fTS tTXCLK tTXCLKH [25] tTXCLKL tTXCLKF tTXDS tTXDH fTOS tTXCLKO tTXCLKOD+ tTXCLKOD– [25] Description TXCLKx Clock Frequency TXCLKx Period TXCLKx HIGH Time TXCLKx LOW Time TXCLKx Rise Time TXCLKx Fall Time Transmit Data Set-up Time to TXCLKx↑ (TXCKSEL ≠ LOW) Transmit Data Hold Time from TXCLKx↑ (TXCKSEL ≠ LOW) TXCLKO Clock Frequency = 1x or 2x REFCLK Frequency TXCLKO Period TXCLKO+ Duty Cycle with 60% HIGH time TXCLKO– Duty Cycle with 40% HIGH time Min. 19.5 6.66 2.2 2.2 0.2 0.2 1.7 0.8 19.5 6.66 –1.0 –0.5 Max. 150 51.28 Unit MHz ns ns ns tTXCLKR [25, 26, 27] [25, 26, 27] 1.7 1.7 ns ns ns ns 150 51.28 +0.5 +1.0 MHz ns ns ns CYP(V)15G0402DXB Receiver LVTTL Switching Characteristics Over the Operating Range Parameter fRS tRXCLKP tRXCLKH tRXCLKL tRXCLKD tRXCLKR [25] tRXCLKF [25] Description RXCLKx Clock Output Frequency RXCLKx Period RXCLKx HIGH Time (RXRATE = LOW) RXCLKx HIGH Time (RXRATE = HIGH) RXCLKx LOW Time (RXRATE = LOW) RXCLKx LOW Time (RXRATE = HIGH) RXCLKx Duty Cycle centered at 50% RXCLKx Rise Time RXCLKx Fall Time Status and Data Valid Time to RXCLKx Status and Data Valid Time to RXCLKx (HALF RATE RECOVERED CLOCK) Min. 9.75 6.66 2.33[25] 5.66 2.33[25] 5.66 –1.0 0.3 0.3 5UI – 1.5 5UI – 1.0 5UI – 1.8 5UI – 2.3 Max. 150 102.56 26.64 52.28 26.64 52.28 +1.0 1.2 1.2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns tRXDV– [28] tRXDV+ [28] Status and Data Valid Time from RXCLKx Status and Data Valid Time from RXCLKx (HALF RATE RECOVERED CLOCK) CYP(V)15G0402DXB REFCLK Switching Characteristics Over the Operating Range Parameter fREF tREFCLK tREFH tREFL REFCLK Clock Frequency REFCLK Period REFCLK HIGH Time (TXRATE = HIGH) REFCLK HIGH Time (TXRATE = LOW) REFCLK LOW Time (TXRATE = HIGH) REFCLK LOW Time (TXRATE = LOW) Description Min. 19.5 6.6 5.9 2.9[25] 5.9 2.9[25] Max. 150 51.28 Unit MHz ns ns ns ns ns Notes: 25. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested. 26. The ratio of rise time to falling time must not vary by greater than 2:1. 27. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time. 28. Parallel data output specifications are only valid if all inputs or outputs are loaded with similar DC and AC loads. Document #: 38-02057 Rev. *G Page 22 of 29 CYP15G0402DXB CYV15G0402DXB CYP(V)15G0402DXB REFCLK Switching Characteristics Over the Operating Range (continued) Parameter tREFD [29] tREFR [25, 26, 27] Description REFCLK Duty Cycle REFCLK Rise Time (20% – 80%) REFCLK Fall Time (20% – 80%) Transmit Data Setup Time to REFCLK (TXCKSEL = LOW) Transmit Data Hold Time from REFCLK (TXCKSEL = LOW) REFCLK Frequency Referenced to Received Clock Period Min. 30 Max. 70 2 2 Unit % ns ns ns ns tREFF [25, 26, 27] tTREFDS tTREFDH tREFRX [8] 1.7 0.8 -1500 +1500 ppm CYP(V)15G0402DXB Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range Parameter tB tRISE [25] Bit Time CML Output Rise Time 20% – 80% (CML Test Load) SPDSEL = HIGH SPDSEL = MID SPDSEL = LOW tFALL [25] Description Condition Min. 5100 50 100 180 50 100 180 Max. 660 270 500 1000 270 500 1000 25 11 200 Unit ps ps ps ps ps ps ps ps ps us UI[33] UI UI ps ps CML Output Fall Time 80% – 20% (CML Test Load) SPDSEL = HIGH SPDSEL = MID SPDSEL = LOW tDJ [25, 30, 32] tRJ [25, 31, 32] Deterministic Jitter (peak-peak) Random Jitter (σ) Transmit PLL lock to REFCLK IEEE 802.3z IEEE 802.3z tTXLOCK tRXLOCK tRXUNLOCK tJTOL tDJTOL CYP(V)15G0402DXB Receive Serial Inputs and CDR PLL Characteristics Over the Operating Range Receive PLL lock to input data stream (cold start) Receive PLL lock to input data stream Receive PLL Unlock Rate Total Jitter Tolerance Deterministic Jitter Tolerance IEEE 802.3z IEEE 802.3z 600 370 376K 376K 46 Capacitance [25] Parameter CINTTL CINPECL Description TTL Input Capacitance PECL input Capacitance Test Conditions TA = 25°C, f0 = 1 MHz, VCC = 3.3V TA = 25°C, f0 = 1 MHz, VCC = 3.3V Max. 7 4 Unit pF pF Notes: 29. The duty cycle specification is a simultaneous condition with the tREFH and tREFL parameters. This means that at faster character rates the REFCLK duty cycle cannot be as large as 30% – 70%. 30. While sending continuous K28.5s, outputs loaded to a balanced 100Ω load, measured at the cross point of differential outputs, over the operating range. 31. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the operating range. 32. Total jitter is calculated at an assumed BER of 1E −12. Hence: total jitter (tJ) = (tRJ * 14) + tDJ. 33. Receiver UI (Unit Interval) is calculated as 1 / (fREF * 20) (when RXRATE = HIGH) or 1 / (fREF * 10) (when RXRATE = LOW) if no data is being received, or 1 / (fREF * 20) (when RXRATE = HIGH) or 1 / (fREF * 10) (when RXRATE = LOW) of the remote transmitter if data is being received. In an operating link this is equivalent to tB. Document #: 38-02057 Rev. *G Page 23 of 29 CYP15G0402DXB CYV15G0402DXB CYP(V)15G0402DXB HOTLink II Transmitter Switching Waveforms Transmit Interface Write Timing TXCKSEL ≠ LOW TXCLKx TXDx[9:0], TXOPx tTXCLK tTXCLKH tTXCLKL tTXDS tTXDH Transmit Interface Write Timing TXCKSEL = LOW TXRATE = LOW REFCLK TXDx[9:0], TXOPx tREFH tREFCLK tREFL tTREFDS tTREFDH Transmit Interface Write Timing TXCKSEL = LOW TXRATE = HIGH REFCLK Note 34 tREFCLK tREFH Note 34 tREFL TXDx[9:0], TXOPx, tTREFDS tTREFDS tTREFDH tTREFDH Transmit Interface TXCLKO Timing TXCKSEL = LOW TXRATE = HIGH REFCLK Note 36 tREFCLK tREFH tREFL tTXCLKO tTXCLKOD+ tTXCLKOD– Note 35 TXCLKO Notes: 34. When REFCLK is configured for half-rate operation (TXRATE = HIGH) and data is captured using REFCLK instead of a TXCLKx clock (TXCKSEL = LOW), data is captured using both the rising and falling edges of REFCLK. 35. The TXCLKO output is at twice the rate of REFCLK when TXRATE = HIGH and same rate as REFCLK when TXRATE = LOW. TXCLKO does not follow the duty cycle of REFCLK. 36. The rising edge of TXCLKO output has no direct phase relationship to the REFCLK input. Document #: 38-02057 Rev. *G Page 24 of 29 CYP15G0402DXB CYV15G0402DXB CYP(V)15G0402DXB HOTLink II Transmitter Switching Waveforms (continued) Transmit Interface TXCLKO Timing TXCKSEL = LOW TXRATE = LOW REFCLK tREFCLK tREFH Note 35 tREFL tTXCLKO Note 36 tTXCLKOD+ tTXCLKOD– TXCLKO Switching Waveforms for the CYP(V)15G0402DXB HOTLink II Receiver Receive Interface Read Timing RXRATE = LOW RXCLKx+ tRXCLKP tRXCLKH tRXCLKL RXCLKx– tRXDV– RXDx[9:0], COMDETx RXOPx tRXDV+ Receive Interface Read Timing RXRATE = HIGH RXCLKx+ tRXCLKP tRXCLKH tRXCLKL RXCLKx– tRXDV– RXDx[9:0], COMDETx], RXOPx tRXDV+ Document #: 38-02057 Rev. *G Page 25 of 29 CYP15G0402DXB CYV15G0402DXB Table 9. Package Coordinate Signal Allocation Ball ID A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C01 C02 C03 Signal Name INC– OUTC– N/C N/C VCC IND– OUTD– GND N/C N/C INA– OUTA– GND N/C N/C VCC INB– OUTB– N/C N/C INC+ OUTC+ N/C N/C VCC IND+ OUTD+ GND N/C N/C INA+ OUTA+ GND N/C N/C VCC INB+ OUTB+ N/C N/C TDI TMS LPENC Signal Type CML IN CML OUT NO CONNECT NO CONNECT POWER CML IN CML OUT GROUND NO CONNECT CML OUT CML IN CML OUT GROUND NO CONNECT NO CONNECT POWER CML IN CML OUT NO CONNECT NO CONNECT CML IN CML OUT NO CONNECT NO CONNECT POWER CML IN CML OUT GROUND NO CONNECT NO CONNECT CML IN CML OUT GROUND NO CONNECT NO CONNECT POWER CML IN CML OUT NO CONNECT NO CONNECT LVTTL IN PU LVTTL IN PU LVTTL IN Ball ID C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E01 E02 E03 E04 E17 E18 Signal Name LPENB VCC PARCTL SDASEL GND BOE[7] BOE[5] BOE[3] BOE[1] GND GND GND VCC TXRATE RXRATE N/C TDO TCLK TRSTZ LPEND LPENA VCC RFMODE SPDSEL GND BOE[6] BOE[4] BOE[2] BOE[0] GND GND GND VCC N/C RXLE N/C N/C VCC VCC VCC VCC VCC VCC Signal Type LVTTL IN POWER 3-LEVEL SEL 3-LEVEL SEL GROUND LVTTL IN PU LVTTL IN PU LVTTL IN PU LVTTL IN PU GROUND GROUND GROUND POWER LVTTL IN PD LVTTL IN PD NO CONNECT LVTTL 3-S OUT LVTTL IN PD LVTTL IN PU LVTTL IN LVTTL IN POWER 3-LEVEL SEL 3-LEVEL SEL GROUND LVTTL IN PU LVTTL IN PU LVTTL IN PU LVTTL IN PU GROUND GROUND GROUND POWER NO CONNECT LVTTL IN PU NO CONNECT NO CONNECT POWER POWER POWER POWER POWER POWER Ball ID E19 E20 F01 F02 F03 F04 F17 F18 F19 F20 G01 G02 G03 G04 G17 G18 G19 G20 H01 H02 H03 H04 H17 H18 H19 H20 J01 J02 J03 J04 J17 J18 J19 J20 K01 K02 K03 K04 K17 K18 K19 K20 L01 Signal Name VCC VCC TXPERC TXOPC TXDC[0] N/C BISTLE RXDB[0] RXOPB RXDB[1] TXDC[7] TXCKSEL TXDC[4] TXDC[1] GND OELE FRAMCHAR RXDB[3] GND GND GND GND GND GND GND GND TXDC[9] TXDC[5] TXDC[2] TXDC[3] COMDETB RXDB[2] RXDB[7] RXDB[4] RXDC[4] RXCLKC– TXDC[8] LFIC RXDB[5] RXDB[6] RXDB[9] RXCLKB+ RXDC[5] Signal Type POWER POWER LVTTL OUT LVTTL IN PU LVTTL IN NO CONNECT LVTTL IN PU LVTTL OUT LVTTL 3-S OUT LVTTL OUT LVTTL IN 3-LEVEL SEL LVTTL IN LVTTL IN GROUND LVTTL IN PU 3-LEVEL SEL LVTTL OUT GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND LVTTL IN LVTTL IN LVTTL IN LVTTL IN LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT LVTTL IN LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT LVTTL I/O PD LVTTL OUT Document #: 38-02057 Rev. *G Page 26 of 29 CYP15G0402DXB CYV15G0402DXB Table 9. Package Coordinate Signal Allocation (continued) Ball ID L02 L03 L04 L17 L18 L19 L20 M01 M02 M03 M04 M17 M18 M19 M20 N01 N02 N03 N04 N17 N18 N19 N20 P01 P02 P03 P04 P17 P18 P19 P20 R01 R02 R03 R04 R17 R18 R19 R20 T01 T02 T03 T04 Signal Name RXCLKC+ TXCLKC TXDC[6] RXDB[8] LFIB RXCLKB– TXDB[6] RXDC[6] RXDC[7] RXDC[9] RXDC[8] TXDB[9] TXDB[8] TXDB[7] TXCLKB GND GND GND GND GND GND GND GND RXDC[3] RXDC[2] RXDC[1] RXDC[0] TXDB[5] TXDB[4] TXDB[3] TXDB[2] COMDETC RXOPC TXPERD TXOPD TXDB[1] TXDB[0] TXOPB TXPERB VCC VCC VCC VCC Signal Type LVTTL I/O PD LVTTL IN PD LVTTL IN LVTTL OUT LVTTL OUT LVTTL OUT LVTTL IN LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT LVTTL IN LVTTL IN LVTTL IN LVTTL IN PD GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT LVTTL IN LVTTL IN LVTTL IN LVTTL IN LVTTL OUT LVTTL 3-S OUT LVTTL OUT LVTTL IN PU LVTTL IN LVTTL IN LVTTL IN PU LVTTL OUT POWER POWER POWER POWER Ball ID T17 T18 T19 T20 U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 Signal Name VCC VCC VCC VCC TXDD[0] TXDD[1] TXDD[2] TXDD[9] VCC RXDD[4] RXDD[3] GND RXOPD RFENC REFCLK– TXDA[1] GND TXDA[4] TXDA[8] VCC RXDA[4] RXOPA COMDETA RXDA[0] TXDD[3] TXDD[4] TXDD[8] RXDD[8] VCC RXDD[5] RXDD[1] GND COMDETD RFEND REFCLK+ RFENB GND TXDA[3] TXDA[7] VCC RXDA[9] RXDA[5] RXDA[2] Signal Type POWER POWER POWER POWER LVTTL IN LVTTL IN LVTTL IN LVTTL IN POWER LVTTL OUT LVTTL OUT GROUND LVTTL 3-S OUT LVTTL IN PD PECL IN LVTTL IN GROUND LVTTL IN LVTTL IN POWER LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT LVTTL IN LVTTL IN LVTTL IN LVTTL OUT POWER LVTTL OUT LVTTL OUT GROUND LVTTL OUT LVTTL IN PD PECL IN LVTTL IN PD GROUND LVTTL IN LVTTL IN POWER LVTTL OUT LVTTL OUT LVTTL OUT Ball ID V20 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal Name RXDA[1] TXDD[5] TXDD[7] LFID RXCLKD– VCC RXDD[6] RXDD[0] GND TXCLKO– TXRST TXOPA RFENA GND TXDA[2] TXDA[6] VCC LFIA RXCLKA– RXDA[6] RXDA[3] TXDD[6] TXCLKD RXDD[9] RXCLKD+ VCC RXDD[7] RXDD[2] GND TXCLKO+ N/C TXCLKA TXPERA GND TXDA[0] TXDA[5] VCC TXDA[9] RXCLKA+ RXDA[8] RXDA[7] Signal Type LVTTL OUT LVTTL IN LVTTL IN LVTTL OUT LVTTL OUT POWER LVTTL OUT LVTTL OUT GROUND LVTTL OUT LVTTL IN PU LVTTL IN PU LVTTL IN PD GROUND LVTTL IN LVTTL IN POWER LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT LVTTL IN LVTTL IN LVTTL OUT LVTTL I/O PD POWER LVTTL OUT LVTTL OUT GROUND LVTTL OUT NO CONNECT LVTTL IN PD LVTTL OUT GROUND LVTTL IN LVTTL IN POWER LVTTL IN LVTTL I/O PD LVTTL OUT LVTTL OUT Document #: 38-02057 Rev. *G Page 27 of 29 CYP15G0402DXB CYV15G0402DXB Ordering Information Speed Standard Standard Standard Standard Standard Standard Standard Standard Ordering Code CYP15G0402DXB-BGC CYP15G0402DXB-BGI CYV15G0402DXB-BGC CYV15G0402DXB-BGI CYP15G0402DXB-BGXC CYP15G0402DXB-BGXI CYV15G0402DXB-BGXC CYV15G0402DXB-BGXI Package Name BL256 BL256 BL256 BL256 BL256 BL256 BL256 BL256 Package Type 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array Pb-Free 256-ball Thermally Enhanced Ball Grid Array Pb-Free 256-ball Thermally Enhanced Ball Grid Array Pb-Free 256-ball Thermally Enhanced Ball Grid Array Pb-Free 256-ball Thermally Enhanced Ball Grid Array Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Package Diagram 256-lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256 51-85123-*E HOTLink is a registered trademark, and HOTLink II and MultiFrame are trademarks, of Cypress Semiconductor Corporation. ESCON is a registered trademark of International Business Machines. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-02057 Rev. *G Page 28 of 29 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CYP15G0402DXB CYV15G0402DXB Document History Page Document Title:CYP(V)15G0402DXB Quad HOTLink II™ SERDES Document Number: 38-02057 REV. ** *A ECN NO. 116285 118985 Issue Date 07/16/02 09/30/02 Orig. of Change SDR LNM New Data Sheet Changed TXCLKO description Changed TXPERx description introduced SMPTE pathological test clause Removed the LOW setting for FRAMCHAR and related references Changed VODIF and VOLC for CML output Changed the IOST boundary values Changed the tTXCLKR and tTXCLKF min values Changed tTXDS and tTXDH and tTREFDS and tTREFDH Changed tREFADV– and tREFCDV– and tREFCDV+ Changed the JTAG ID from 0C801069 to 1C801069 Changed Minimum tRISE/tFALL for CML Changed tTXCLKOD+, tTXCLKOD- for LVTTL Changed tRXLOCK Changed tDJ, tRJ Changed tJTOL Changed tTXLOCK Changed tRXCLKH, tRXCLKL Changed Power Specs Changed verbiage...Paragraph: Clock/Data Recovery Changed verbiage...Paragraph: Range Control Updated differences to pin configuration and pin table Added Power-up Requirements Minor change Document Control corrected Document History Page Changed CYP15G0402DXB to CYP(V)15G0402DXB type corresponding to Video-compliant parts Reduced the lower limit of the serial signaling rate from 200 Mbaud to 195 Mbaud and changed the associated specifications accordingly Added tRXDV+ timing parameter Removed irrelevant timing parameters When TXCKSEL = MID or HIGH, TXRATE = HIGH is an invalid mode. Made appropriate changes to reflect this invalid condition Changed LFIx to Asynchronous output Expanded the CDR Range Controller’s permissible frequency offset between incoming serial signaling rate and Reference clock from ±200-PPM to ±1500-PPM (changed parameter tREFRX) Revised Typical Power numbers to match final characterization data Added Pb-Free Package option availability Changed MBd to MBaud in SPDSEL pin description Description of Change *B 122545 12/09/02 CGX *C *D 122211 124992 12/28/02 04/15/03 RBI POT *E *F 128367 131899 07/24/03 01/21/04 PDS PDS *G 338721 See ECN SUA Document #: 38-02057 Rev. *G Page 29 of 29