Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
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Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
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PRELIMINARY
CYW20707
Bluetooth SoC for Embedded Wireless
Devices
General Description
The Cypress CYW20707 is a single-chip Bluetooth 4.2-compliant, stand-alone baseband processor with an integrated 2.4 GHz
transceiver. Manufactured using the industry's most advanced 40 nm CMOS low-power process, the CYW20707 employs the highest
level of integration to eliminate all critical external components, thereby minimizing the device's footprint and the costs associated with
implementing Bluetooth solutions.
The CYW20707 is the optimal solution for embedded and IoT applications. Built-in firmware adheres to the Bluetooth Low Energy
(BLE) profile.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Cypress to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number
Cypress Part Number
BCM20707
CYW20707
BCM20707UA2KFFB4G
CYW20707UA2KFFB4G
BCM20707UA2EKUBGT
CYW20707UA2EKUBGT
Features
■
Complies with Bluetooth Core Specification version 4.2
including BR/EDR/BLE
■
Broadcom proprietary LE data rate up to 2 Mbps
■
BLE HID profile version 1.00 compliant
■
Bluetooth Device ID profile version 1.3 compliant
■
Supports Generic Access Profile (GAP)
■
Supports Adaptive Frequency Hopping (AFH)
■
Excellent receiver sensitivity
■
Programmable output power control
■
Integrated ARM Cortex-M3 microprocessor core
■
On-chip power-on reset (POR)
■
Support for EEPROM and serial flash interfaces
■
Integrated low dropout regulators (LDO)
■
On-chip software controlled PMU
■
PCM/I2S Interface
■
Infrared modulator
■
IR learning
■
On-chip support for SPI (master/slave modes)
■
Broadcom Serial Communications interface (compatible with
NXP I2C slaves)
■
Package types:
❐
❐
❐
49-pin FBGA package (4.5 mm x 4.0 mm) Bluetooth 4.2compliant
36-pin WLBGA package (2.8 mm x 2.5 mm) Bluetooth 4.2complaint
RoHS compliant
Applications
■
Home automation
■
Heart rate monitors
■
Point-of-sale input devices
■
Proximity sensors
■
Blood pressure monitors
■
Thermometers
■
“Find me” devices
■
Wearables
Cypress Semiconductor Corporation
•
198 Champion Court
Document No. Document Number: 002-14792 Rev. *H
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 30, 2017
PRELIMINARY
CYW20707
Figure 1. Functional Block Diagram
CYW20707
JTAG
Cortex‐M3
DMA
Scan JTAG
Address
Decoder
Bus Arb
Trap & Patch
Flash I/F
32‐bit AHB
AHB2EBI
External
Bus I/F
AHB2APB
WD Timer
Remap &
Pause
GPIO+Aux
SW
Timers
AHB2MEM
AHB2MEM
PMU Control
ROM
RAM
Interrupt
Controller
JTAG Master
32‐bit APB
Calibration &
Control
Bluetooth Radio
Digital Demod
Bit Sync
Low Power
Scan
Blue RF Registers
PMU
LPO
PCM
UART
LCU
Digital
Modulator
RF
SPI
Master
Buffer
APU
Digital I/O
Debug
UART
Blue RF I/F
I2C_Master
BT Clk/
Hopper
PTU
Rx/Tx
Buffer
I/O
Port Control
ADC
POR
Document Number: 002-14792 Rev. *H
Page 2 of 51
PRELIMINARY
CYW20707
Contents
1. Functional Description ..................................... 4
1.1
Bluetooth Baseband Core ................................... 4
1.1.1 Bluetooth 4.2 Features ............................ 4
1.1.2 Link Control Layer ................................... 5
1.1.3 Test Mode Support .................................. 5
1.1.4 Frequency Hopping Generator ................ 5
1.2
Microprocessor Unit ............................................ 6
1.2.1 NVRAM Configuration Data and Storage 6
1.2.2 One-Time Programmable Memory .......... 6
1.2.3 External Reset ......................................... 7
1.3
Integrated Radio Transceiver .............................. 8
1.3.1 Transmit ................................................... 8
1.3.2 Receiver .................................................. 8
1.3.3 Local Oscillator Generation ..................... 8
1.3.4 Calibration ............................................... 9
1.3.5 Internal LDO ............................................ 9
1.4
Collaborative Coexistence .................................. 9
1.5
Global Coexistence Interface .............................. 9
1.5.1 SECI I/O .................................................. 9
1.6
1.7
Peripheral Transport Unit .................................. 10
1.6.1 Broadcom Serial Communications
Interface ................................................. 10
1.14 Infrared Learning ................................................16
1.15 Power Management Unit ....................................17
1.15.1 RF Power Management ..........................17
1.15.2 Host Controller Power Management ......17
1.15.3 BBC Power Management .......................17
2. Pin Assignments............................................. 18
2.1
Pin Descriptions .................................................18
2.1.1 49-Pin FBGA List ....................................18
2.1.2 36-Pin WLBGA List .................................22
2.2
Ball Map .............................................................24
2.2.1 49-Pin FBGA Ball Map ...........................24
2.2.2 36-Pin WLBGA Ball Map ........................25
3. Specifications ................................................. 26
3.1
Electrical Characteristics ....................................26
3.1.1 Digital I/O Characteristics .......................29
3.1.2 Current Consumption .............................30
3.2
RF Specifications ...............................................31
3.3
Timing and AC Characteristics ...........................34
3.3.1 UART Timing ..........................................34
3.3.2 SPI Timing ..............................................35
1.6.2 UART Interface ...................................... 10
3.3.3 BSC Interface Timing .............................37
PCM Interface ................................................... 12
1.7.1 Slot Mapping .......................................... 12
1.7.2 Frame Synchronization .......................... 12
1.7.3 Data Formatting ..................................... 12
1.7.4 Burst PCM Mode ................................... 12
3.3.4 PCM Interface Timing .............................38
1.8
Clock Frequencies ............................................ 13
1.8.1 Crystal Oscillator ................................... 13
1.9
GPIO Ports ........................................................ 14
1.9.1 49-Pin FBGA Package .......................... 14
1.9.2 36-Pin WLBGA Package ....................... 14
1.10 PWM ................................................................. 15
1.11 Triac Control ...................................................... 16
1.12 Serial Peripheral Interface ................................. 16
1.13 Infrared Modulator ............................................. 16
Document Number: 002-14792 Rev. *H
3.3.5 I2S Timing ...............................................41
4. Mechanical Information.................................. 44
4.1
Package Diagrams .............................................44
4.2
Tape Reel and Packaging Specifications ...........46
5. Ordering Information...................................... 47
6. Additional information ................................... 48
6.1
Acronyms and Abbreviations .............................48
6.2
IoT Resources ....................................................49
Document History Page ................................................. 50
Sales, Solutions, and Legal Information ...................... 51
Page 3 of 51
PRELIMINARY
CYW20707
1. Functional Description
1.1 Bluetooth Baseband Core
The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation.
The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,
handles data flow control, schedules SCO/ACL and TX/RX transactions, monitors Bluetooth slot usage, optimally segments and
packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition
to these functions, it independently handles HCI event types, and HCI command types. The following transmit and receive functions
are also implemented in the BBC hardware to increase reliability and security of the TX/RX data before sending over the air:
■
Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check
(CRC), data decryption, and data dewhitening in the receiver.
■
Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the
transmitter.
1.1.1 Bluetooth 4.2 Features
Both the CYW20707 36-pin WLBGA package and the 49-pin FBGA package support all Bluetooth 4.2 and legacy features, with the
following benefits:
■
Dual-mode Bluetooth low energy (BT and BLE operation)
■
Extended inquiry response (EIR): Shortens the time to retrieve the device name, specific profile, and operating mode.
■
Encryption pause resume (EPR): Enables the use of Bluetooth technology in a much more secure environment.
■
Sniff subrating (SSR): Optimizes power consumption for low duty cycle asymmetric data flow, which subsequently extends battery
life.
■
Secure simple pairing (SSP): Reduces the number of steps for connecting two devices, with minimal or no user interaction required.
■
Link supervision time out (LSTO): Additional commands added to HCI and Link Management Protocol (LMP) for improved link
timeout supervision.
■
Quality of service (QoS) enhancements: Changes to data traffic control, which results in better link performance. Audio, human
interface device (HID), bulk traffic, SCO, and enhanced SCO (eSCO) are improved with the erroneous data (ED) and packet
boundary flag (PBF) enhancements.
■
Secure connections (BR/EDR)
■
Fast advertising interval
■
Piconet clock adjust
■
Connectionless broadcast
■
LE privacy v1.1
■
Low duty cycle directed advertising
■
LE dual mode topology
Document Number: 002-14792 Rev. *H
Page 4 of 51
PRELIMINARY
CYW20707
1.1.2 Link Control Layer
The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU).
This layer consists of the command controller that takes commands from the software, and other controllers that are activated or
configured by the command controller, to perform the link control tasks. Each task is performed in a different state in the Bluetooth
Link Controller.
■
States:
❐
❐
❐
❐
❐
❐
❐
❐
❐
Standby
Connection
Page
Page Scan
Inquiry
Inquiry Scan
Sniff
Advertising
Scanning
1.1.3 Test Mode Support
The CYW20707 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0.
This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.
In addition to the standard Bluetooth Test Mode, the CYW20707 also supports enhanced testing features to simplify RF debugging
and qualification and type-approval testing. These features include:
■
Fixed frequency carrier wave (unmodulated) transmission
❐
❐
■
Fixed frequency constant receiver mode
❐
❐
❐
■
Simplifies some type-approval measurements (Japan)
Aids in transmitter performance analysis
Receiver output directed to I/O pin
Allows for direct BER measurements using standard RF test equipment
Facilitates spurious emissions testing for receive mode
Fixed frequency constant transmission
❐
❐
8-bit fixed pattern or PRBS-9
Enables modulated signal measurements with standard RF test equipment
1.1.4 Frequency Hopping Generator
The frequency hopping sequence generator selects the correct hopping channel number based on the link controller state, Bluetooth
clock, and device address.
Document Number: 002-14792 Rev. *H
Page 5 of 51
PRELIMINARY
CYW20707
1.2 Microprocessor Unit
The CYW20707 microprocessor unit runs software from the link control (LC) layer up to the host controller interface (HCI). The
microprocessor is based on the Cortex-M3 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The
microprocessor also includes 848 KB of ROM memory for program storage and boot ROM, 352 KB of RAM for data scratch-pad, and
patch RAM code.
The internal boot ROM provides flexibility during power-on reset to enable the same device to be used in various configurations. At
power-up, the lower layer protocol stack is executed from the internal ROM.
External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. These patches
can be downloaded using external NVRAM. The device can also support the integration of user applications and profiles using an
external serial flash memory.
1.2.1 NVRAM Configuration Data and Storage
NVRAM contains configuration information about the customer application, including the following:
■
Fractional-N information
■
BD_ADDR
■
UART baud rate
■
SDP service record
■
File system information used for code, code patches, or data. The CYW20707 can use SPI Flash or I2C EEPROM/serial flash for
NVRAM storage.
1.2.2 One-Time Programmable Memory
The CYW20707 includes 2 Kbytes of one-time programmable (OTP) memory allow manufacturing customization and to avoid the
need for an on-board NVRAM. If customization is not required, then the OTP does not need to be programmed. Whether the OTP is
programmed or not, to save power it is disabled when the boot process is complete. The OTP is designed to store a minimal amount
of information. Aside from OTP data, most user configuration information will be downloaded to RAM after the CYW20707 boots and
is ready for host transport communication.
Note: The OTP is disabled internally for the 36-Pin WLBGA package.
The OTP contents are limited to:
■
Parameters required prior to downloading the user configuration to RAM.
■
Parameters unique to each part and each customer (for example, the Bluetooth device address and/or the software license key).
Document Number: 002-14792 Rev. *H
Page 6 of 51
PRELIMINARY
CYW20707
1.2.3 External Reset
An external active-low reset signal, RESET_N, can be used to put the CYW20707 in the reset state. An external voltage detector
reset IC with 50 ms delay is needed on the RESET_N. The RESET_N should be released only after the VDDO supply voltage level
has been stabilized for 50 ms.
Figure 2. Reset Timing
Low
threshold
50 ms
Reset
(External)
VDDO
~2.4 ms
VDDO POR
0.5 ms
VDDC
~2.4 ms
VDDC Reset (Internal)
10 LPO cycles
XTAL_RESET
8 LPO cycles
XTAL_BUF_PU
Note: The Reset signal should remain below this threshold 50 ms after VDDO is stable. Note that the representation of this signaling
diagram is extended and not drawn to scale.
Document Number: 002-14792 Rev. *H
Page 7 of 51
PRELIMINARY
CYW20707
1.3 Integrated Radio Transceiver
The CYW20707 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has
been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz
unlicensed ISM band. The CYW20707 is fully compliant with the Bluetooth Radio Specification and enhanced data rate (EDR)
specification and meets or exceeds the requirements to provide the highest communication link quality of service.
1.3.1 Transmit
The CYW20707 features a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block
and upconverted to the 2.4 GHz ISM band in the transmitter path. The transmitter path consists of signal filtering, I/Q upconversion,
output power amplifier, and RF filtering. The transmitter path also incorporates /4-DQPSK for 2 Mbps and 8-DPSK for 3 Mbps to
support EDR. The transmitter section is compatible with the BLE specification. The transmitter PA bias can also be adjusted to provide
Bluetooth class 1 or class 2 operation.
Digital Modulator
The digital modulator performs the data modulation and filtering required for the GFSK, /4-DQPSK, and
8-DPSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much more stable than direct VCO modulation schemes.
Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit
synchronization algorithm.
Power Amplifier
The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. This provides
greater flexibility in front-end matching and filtering. Due to the linear nature of the PA combined with some integrated filtering, external
filtering is required to meet the Bluetooth and regulatory harmonic and spurious requirements. For integrated mobile handset applications in which Bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near thermal noise levels
for spurious and radiated noise emissions. The transmitter features a sophisticated on-chip transmit signal strength indicator (TSSI)
block to keep the absolute output power variation within a tight range across process, voltage, and temperature.
1.3.2 Receiver
The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit
synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel
filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, with built-in out-of-band attenuation,
enables the CYW20707 to be used in most applications with minimal off-chip filtering. For integrated handset operation, in which the
Bluetooth function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the
receiver by the cellular transmit signal.
Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit
synchronization algorithm.
Receiver Signal Strength Indicator
The radio portion of the CYW20707 provides a receiver signal strength indicator (RSSI) signal to the baseband, so that the controller
can take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the
transmitter should increase or decrease its output power.
1.3.3 Local Oscillator Generation
A local oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels.
The LO generation subblock employs an architecture for high immunity to LO pulling during PA operation. The CYW20707 uses an
internal RF and IF loop filter.
Document Number: 002-14792 Rev. *H
Page 8 of 51
PRELIMINARY
CYW20707
1.3.4 Calibration
The CYW20707 radio transceiver features an automated calibration scheme that is fully self-contained in the radio. No user interaction
is required during normal operation or during manufacturing to provide optimal performance. Calibration tunes the performance of all
the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters, matching
between key components, and key gain blocks. This takes into account process variation and temperature variation. Calibration occurs
transparently during normal operation during the settling time of the hops, and calibrates for temperature variations as the device
cools and heats during normal operation in its environment.
1.3.5 Internal LDO
The CYW20707 uses two LDOs - one for 1.2V and the other for 2.5V. The 1.2V LDO provides power to the baseband and radio and
the 2.5V LDO powers the PA.
Figure 3. LDO Functional Block Diagram
CYW20707 PMU
VBAT
VDD2P5
1.2V LDO
VDDC_OUT
2.5V LDO
VDD2P5_OUT
(VDDC_LDO)
(BTLDO2P5)
AVSS_GND
1.4 Collaborative Coexistence
The CYW20707 provides extensions and collaborative coexistence to the standard Bluetooth AFH for direct communication with
WLAN devices. Collaborative coexistence enables WLAN and Bluetooth to operate simultaneously in a single device. The device
supports industry-standard coexistence signaling, including 802.15.2, and supports Cypress and third-party WLAN solutions.
1.5 Global Coexistence Interface
The CYW20707 supports the proprietary Cypress Global Coexistence Interface (GCI) which is a 2-wire interface.
The following key features are associated with the interface:
■
Enhanced coexistence data can be exchanged over GCI_SECI_IN and GCI_SECI_OUT a two-wire interface, one serial input
(GCI_SECI_IN), and one serial output (GCI_SECI_OUT). The pad configuration registers must be programmed to choose the digital
I/O pins that serve the GCI_SECI_IN and GCI_SECI_OUT function.
■
It supports generic UART communication between WLAN and Bluetooth devices.
■
To conserve power, it is disabled when inactive.
■
It supports automatic resynchronization upon waking from sleep mode.
■
It supports a baud rate of up to 4 Mbps.
1.5.1 SECI I/O
The CYW20707 devices have dedicated GCI_SECI_IN and GCI_SECI_OUT pins. The two pin functions can be mapped to any of
the Cypress Global Coexistence Interface (GCI) GPIO. Pin function mapping is controlled by the configuration file that is stored in
either NVRAM or downloaded directly into on-chip RAM from the host.
Document Number: 002-14792 Rev. *H
Page 9 of 51
PRELIMINARY
CYW20707
1.6 Peripheral Transport Unit
1.6.1 Broadcom Serial Communications Interface
The CYW20707 provides a 2-pin master BSC interface, which can be used to retrieve configuration information from an external
EEPROM or to communicate with peripherals such as trackball or touch-pad modules, and motion tracking ICs used in mouse devices.
The BSC interface is compatible with I2C slave devices. BSC does not support multimaster capability or flexible wait-state insertion
by either master or slave devices.
The following transfer clock rates are supported by BSC:
■
100 kHz
■
400 kHz
■
800 kHz (Not a standard I2C-compatible speed.)
■
1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed.)
The following transfer types are supported by BSC:
■
Read (Up to 127 bytes can be read.)
■
Write (Up to 127 bytes can be written.)
■
Read-then-Write (Up to 127 bytes can be read and up to 127 bytes can be written.)
■
Write-then-Read (Up to 127 bytes can be written and up to 127 bytes can be read.)
Hardware controls the transfers, requiring minimal firmware setup and supervision.
The clock pin (SCL) and data pin (SDA) are both open-drain I/O pins. Pull-up resistors external to the CYW20707 are required on
both the SCL and SDA pins for proper operation.
1.6.2 UART Interface
The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 38400 bps to 6
Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via a vendor-specific UART HCI
command. The CYW20707 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The
interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.
The UART clock default setting is 24 MHz, and can be configured to run as high as 48 MHz to support up to 6 Mbps. The baud rate
of the CYW20707 UART is controlled by two values. The first is a UART clock divisor (set in the DLBR register) that divides the UART
clock by an integer multiple of 16. The second is a baud rate adjustment (set in the DHBR register) that is used to specify a number
of UART clock cycles to stuff in the first or second half of each bit time. Up to eight UART cycles can be inserted into the first half of
each bit time, and up to eight UART clock cycles can be inserted into the end of each bit time.
Table 2 contains example values to generate common baud rates with a 24 MHz UART clock.
Document Number: 002-14792 Rev. *H
Page 10 of 51
PRELIMINARY
CYW20707
Table 2. Common Baud Rate Examples, 24 MHz Clock
Baud Rate Adjustment
Baud Rate (bps)
6M
High Nibble
0xFF
Low Nibble
0xF8
Mode
High rate
Error (%)
0.00
4M
0xFF
0xF4
High rate
0.00
3M
0xFF
0xF8
High rate
0.00
2M
0XFF
0XF4
High rate
0.00
1M
0X44
0XFF
Normal
0.00
921600
0x05
0x05
Normal
0.16
460800
0x02
0x02
Normal
0.16
230400
0x04
0x04
Normal
0.16
115200
0x00
0x00
Normal
0.16
57600
0x00
0x00
Normal
0.16
38400
0x01
0x00
Normal
0.00
Table 3 contains example values to generate common baud rates with a 48 MHz UART clock.
Table 3. Common Baud Rate Examples, 48 MHz Clock
Baud Rate (bps)
High Rate
Low Rate
Mode
Error (%)
6M
0xFF
0xF8
High rate
0
4M
0xFF
0xF4
High rate
0
3M
0x0
0xFF
Normal
0
2M
0x44
0xFF
Normal
0
1.5M
0x0
0xFE
Normal
0
1M
0x0
0xFD
Normal
0
921600
0x22
0xFD
Normal
0.16
230400
0x0
0xF3
Normal
0.16
115200
0x1
0xE6
Normal
–0.08
57600
0x1
0xCC
Normal
0.04
38400
0x11
0xB2
Normal
0
Normally, the UART baud rate is set by a configuration record downloaded after reset. Support for changing the baud rate during
normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud
rate registers.
The CYW20707 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±2%.
Document Number: 002-14792 Rev. *H
Page 11 of 51
PRELIMINARY
CYW20707
Peripheral UART Interface
The CYW20707 has a second UART that may be used to interface to other peripherals. This peripheral UART is accessed through
the optional I/O ports, which can be configured individually and separately for each functional pin as shown in Table 4.
Table 4. CYW20707 Peripheral UART
Pin Name
Configured pin name
pUART_TX
pUART_RX
pUART_CTS_N
pUART_RTS_N
P0
P2
P3
P6
P31
P33
–
P30
Note: Not all of the GPIOs above are available on the 36-pin WLBGA package.
1.7 PCM Interface
The CYW20707 includes a PCM interface that shares pins with the I2S interface. The PCM Interface on the CYW20707 can connect
to linear PCM codec devices in master or slave mode. In master mode, the CYW20707 generates the PCM_CLK and PCM_SYNC
signals. In slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYW20707.
1.7.1 Slot Mapping
The CYW20707 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three
channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample
interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or
1024 kHz). The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM
data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow
other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM
clock during the last bit of the slot.
1.7.2 Frame Synchronization
The CYW20707 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchronization
mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is
synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the
first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization
signal is again an active-high pulse at the audio frame rate; however, the duration is three-bit periods and the pulse starts coincident
with the first bit of the first slot.
1.7.3 Data Formatting
The CYW20707 may be configured to generate and accept several different data formats. For conventional narrowband speech mode,
the CYW20707 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various
data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a
programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.
1.7.4 Burst PCM Mode
In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and
save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with
an HCI command from the host.
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PRELIMINARY
CYW20707
1.8 Clock Frequencies
The CYW20707 49-pin FBGA package supports 20, 24, and 40 MHz crystals (XTAL) by selecting the correct crystal strapping options.
Other frequencies also supported by firmware configuration. Table 5 lists the strapping options.
Table 5. Crystal Strapping Options for the 49-Pin FBGA Package
Strapping Option Pin
BT_XTAL_STRAP_1
BT_XTAL_STRAP_0
XTAL Frequency
Pull Low
Pull Low
40 Mhz
Pull Low
Pull High
24 MHz
Pull High
Pull Low
20 MHz
Pull High
Pull High
Read from serial flash or EEPROM
Note: Only the Read from Serial flash or EEPROM option is available for the 36-pin WLBGA package. The strapping is set internally
in the package.
1.8.1 Crystal Oscillator
The XTAL must have an accuracy of ±20 ppm as defined by the Bluetooth specification. Two external load capacitors in the range of
5 pF to 30 pF are required to work with the crystal oscillator. The selection of the load capacitors is XTAL-dependent (see Figure 4).
Figure 4. Recommended Oscillator Configuration—12 pF Load Crystal
22 pF
XIN
Crystal
XOUT
20 pF
Table 6 shows the recommended crystal specifications.
Table 6. Reference Crystal Electrical Specifications
Parameter
Conditions
Minimum
Nominal frequency
–
20
Oscillation mode
–
Fundamental
Frequency tolerance
@25°C
Tolerance stability over temp
Typical
Maximum
Unit
24
40
–
±10
–
ppm
@0°C to +70°C
–
±10
–
ppm
Equivalent series resistance
–
–
–
60
W
Load capacitance
–
–
12
–
pF
Operating temperature range
–
0
–
+70
°C
Storage temperature range
–
–40
–
+125
°C
Drive level
–
–
–
200
μW
Aging
–
–
–
±10
ppm/year
Shunt capacitance
–
–
–
2
pF
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MHz
–
Page 13 of 51
PRELIMINARY
CYW20707
HID Peripheral Block
The peripheral blocks of the CYW20707 all run from a single 128 kHz low-power RC oscillator. The oscillator can be turned on at the
request of any of the peripherals. If the peripheral is not enabled, it shall not assert its clock request line.
The keyboard scanner is a special case, in that it may drop its clock request line even when enabled, and then reassert the clock
request line if a keypress is detected.
1.9 GPIO Ports
1.9.1 49-Pin FBGA Package
The CYW20707 49-pin FBGA package has 24 general-purpose I/Os (GPIOs). All GPIOs support programmable pull-ups and are
capable of driving up to 8 mA at 3.3V or 4 mA at 1.8V, except P26, P27, P28, and P29, which are capable of driving up to 16 mA at
3.3V or 8 mA at 1.8V. The following GPIOs are available:
■
BT_GPIO_0/P36/P38 (triple bonded; only one of three is available)
■
BT_GPIO_1/P25/P32 (triple bonded; only one of three is available)
■
BT_GPIO_3/P27/P33 (triple bonded; only one of three is available)
■
BT_CLK_REQ/P4/P24 (triple bonded; only one of three is available)
■
BT_GPIO_5/P15 (dual bonded; only one of two is available)
■
BT_GPIO_6/P11/P26 (triple bonded; only one of three is available)
■
BT_GPIO_7/P30 (Dual bonded; only one of two is available)
■
BT_CLK_REQ/P4/P24 (triple bonded; only one of three is available)
■
I2S_PCM_IN/P12 (dual bonded; only one of two is available)
■
I2S_PCM_OUT/P3/P29/P35 (quadruple bonded; only one of four is available)
■
I2S_PCM_CLK/P2/P28/P37 (quadruple bonded; only one of four is available)
■
I2S_WS_PCM_SYNC/P0/P34 (triple bonded; only one of three is available)
All of these pins can be programmed as ADC inputs.
Port 26–Port 29
P[26:29] consist of four pins. All pins are capable of sinking up to 16 mA for LEDs. These pins also have PWM functionality, which
can be used for LED dimming.
1.9.2 36-Pin WLBGA Package
The CYW20707 36-pin WLBGA package has seven GPIOs. All GPIOs support programmable pull-ups and are capable of driving up
to 8 mA at 3.3V or 4 mA at 1.8V. The following GPIOs are available:
■
BT_GPIO_3/P0/LPO_IN (triple bonded; only one of three is available)
■
BT_GPIO_5/P8/P33 (triple bonded; only one of three is available)
■
I2S_DI_PCM_IN/P3 (double bonded; only one of two is available)
■
I2S_DO_PCM_OUT/BT_GPIO_6/P9 (triple bonded; only one of three is available)
■
I2S_CLK_PCM_CLK/BT_GPIO_4/P1 (triple bonded; only one of three is available)
■
I2S_WS_PCM_SYNC/P11 (double bonded; only one of two is available)
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PRELIMINARY
CYW20707
1.10 PWM
The CYW20707 has four internal PWMs. The PWM module consists of the following:
■
PWM1–4
■
Each of the four PWM channels, PWM1–4, contains the following registers:
❐
❐
❐
■
10-bit initial value register (read/write)
10-bit toggle register (read/write)
10-bit PWM counter value register (read)
PWM configuration register shared among PWM1–4 (read/write). This 12-bit register is used:
❐
❐
❐
To configure each PWM channel
To select the clock of each PWM channel
To change the phase of each PWM channel
Figure 5 shows the structure of one PWM.
Figure 5. PWM Block Diagram
pwm#_init_val_adr register
enable
clk_sel
o_flip
pwm_cfg_adr register
pwm#_togg_val_adr register
10
10
pwm#_cntr_adr
10
cntr value is ARM readable
pwm_out
Example: PWM cntr w/ pwm#_init_val = 0 (dashed line)
PWM cntr w/ pwm#_init_val = x (solid line)
10'H3FF
pwm_togg_val_adr
10'Hx
10'H000
pwm_out
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PRELIMINARY
CYW20707
1.11 Triac Control
The CYW20707 includes hardware support for zero-crossing detection and trigger control for up to four triacs. The CYW20707 detects
zero-crossing on the AC zero detection line and uses that to provide a pulse that is offset from the zero crossing. This allows the
CYW20707 to be used in dimmer applications, as well as any other applications that require a control signal that is offset from an
input event.
The zero-crossing hardware includes an option to suppress glitches.
1.12 Serial Peripheral Interface
The CYW20707 has two independent SPI interfaces. One is a master-only interface (SPI_2) and the other (SPI_1) can be either a
master or a slave. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer. To support more flexibility for user
applications, the CYW20707 has optional I/O ports that can be configured individually and separately for each functional pin. The
CYW20707 acts as an SPI master device that supports 1.8V or 3.3V SPI slaves. The CYW20707 can also act as an SPI slave device
that supports a 1.8V or 3.3V SPI master.
Note: SPI voltage depends on VDDO; therefore, it defines the type of devices that can be supported.
1.13 Infrared Modulator
The CYW20707 includes hardware support for infrared TX. The hardware can transmit both modulated and unmodulated waveforms.
For modulated waveforms, hardware inserts the desired carrier frequency into all IR transmissions. IR TX can be sourced from
firmware-supplied descriptors, a programmable bit, or the peripheral UART transmitter.
If descriptors are used, they include IR on/off state and the duration between 1–32767 µsec. The CYW20707 IR TX firmware driver
inserts this information in a hardware FIFO and makes sure that all descriptors are played out without a glitch due to underrun (see
Figure 6).
Figure 6. Infrared TX
VCC
R1
62
D1 Infrared‐LD
R2
CYW 20707
IR TX
2.4K
Q1
M M BTA42
1.14 Infrared Learning
The CYW20707 includes hardware support for infrared learning. The hardware can detect both modulated and unmodulated signals.
For modulated signals, the CYW20707 can detect carrier frequencies between 10 kHz and 500 kHz, and the duration that the signal
is present or absent. The CYW20707 firmware driver supports further analysis and compression of the learned signal. The learned
signal can then be played back through the CYW20707 IR TX subsystem (see Figure 7).
Figure 7. Infrared RX
VCC
D2 Photodiode
CYW20707 IR RX
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PRELIMINARY
CYW20707
1.15 Power Management Unit
The Power Management Unit (PMU) provides power management features that can be invoked by software through power
management registers or packet-handling in the baseband core.
1.15.1 RF Power Management
The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz transceiver, which then processes the power-down functions accordingly.
1.15.2 Host Controller Power Management
Power is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls the
disabling of the on-chip regulator when in HIDOFF (deep sleep) mode.
1.15.3 BBC Power Management
There are several low-power operations for the BBC:
■
Physical layer packet handling turns RF on and off dynamically within packet TX and RX.
■
Bluetooth-specified low-power connection mode. While in these low-power connection modes, the CYW20707 runs on the Low
Power Oscillator and wakes up after a predefined time period.
The CYW20707 automatically adjusts its power dissipation based on user activity. The following power modes are supported:
■
Active mode
■
Idle mode
■
Sleep mode
■
HIDOFF (deep sleep) mode
The CYW20707 transitions to the next lower state after a programmable period of user inactivity. When user activity resumes, the
CYW20707 immediately enters Active mode.
In HIDOFF mode, the CYW20707 baseband and core are powered off by disabling power to VDDC_OUT and PAVDD. The VDDO
domain remains powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chip power
consumption and is intended for long periods of inactivity.
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PRELIMINARY
CYW20707
2. Pin Assignments
2.1 Pin Descriptions
2.1.1 49-Pin FBGA List
Table 7. CYW20707 49-Pin FBGA List
Pin
Signal
I/O
Power
Domain
Description
Radio
A2
RFOP
I/O
VDD_RF
RF I/O antenna port
A4
XO_IN
I
VDD_RF
Crystal or reference input
A5
XO_OUT
O
VDD_RF
Crystal oscillator output
Voltage Regulators
D1
VBAT
I
N/A
VBAT input pin. This must be less than or equal to
VDDO.
E1
VDD2P5_IN
I
N/A
2.5V LDO input
E2
VDD2P5_OUT
O
N/A
2.5V LDO output
F1
VDDC_OUT
O
N/A
1.2V LDO output
Straps
G3
BT_XTAL_STRAP_0
I
VDDO
A strap for choosing the XTAL frequencies.
F2
BT_XTAL_STRAP_1
I
VDDO
A strap for choosing the XTAL frequencies.
A6
RST_N
I
VDDO
Active-low reset input
G7
BT_TM1
I
VDDO
Reserved: connect to ground.
Digital I/O
F8
F7
E4
BT_GPIO_0
I
VDDO
BT_GPIO_0/BT_DEV_WAKE A signal from the host to
the CYW20707 that the host requires attention.
P36
I/O
VDDO
GPIO: P36
A/D converter input 3
Quadrature: QDZ0
SPI_1: SPI_CLK (master and slave)
Auxiliary Clock Output: ACLK0
External T/R switch control: ~tx_pd
P38
I/O
VDDO
GPIO: P38
A/D converter input 1
SPI_1: MOSI (master and slave) IR_TX
BT_GPIO_1
O
VDDO
BT_GPIO_1/BT_HOST_WAKE A signal from the
CYW20707 device to the host indicating that the
Bluetooth device requires attention.
P25
I/O
VDDO
GPIO: P25
SPI_1: MISO (master and slave)
Peripheral UART: puart_rx
P32
I/O
VDDO
GPIO: P32
A/D converter input 7
Quadrature: QDX0
SPI_1: SPI_CS (slave only)
Auxiliary clock output: ACLK0
Peripheral UART: puart_tx
I
VDDO
When high, this signal extends the XTAL warm-up time
for external CLK requests. Otherwise, it is typically
connected to ground.
BT_GPIO_2
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PRELIMINARY
CYW20707
Table 7. CYW20707 49-Pin FBGA List (Cont.)
Pin
C5
D6
Signal
B6
C6
Power
Domain
Description
BT_GPIO_3
I/O
VDDO
General-purpose I/O
P27
PWM1
I/O
VDDO
GPIO: P27
SPI_1: MOSI (master and slave)
Optical control output: QOC1
Triac control 2
Current: 16 mA sink
P33
I/O
VDDO
GPIO: P33
A/D converter input 6
Quadrature: QDX1
SPI_1: MOSI (slave only)
Auxiliary clock output: ACLK1
Peripheral UART: puart_rx
BT_GPIO_4
I/O
VDDO
General-purpose I/O: can also be configured as a GCI
pin.
P6
I/O
VDDO
GPIO: P6
Quadrature: QDZ0
Peripheral UART: puart_rts
SPI_1: SPI_CS (slave only)
60Hz_main
LPO_IN
B5
I/O
I
N/A
P31
I/O
VDDO
External LPO input
GPIO: P31
A/D converter input 8
Peripheral UART: puart_tx
BT_GPIO_5
I/O
VDDO
General-purpose I/O: can also be configured as a GCI
pin.
Debug UART
P15
I/O
VDDO
GPIO: P15
A/D converter input 20 IR_RX 60Hz_main
BT_GPIO_6
I/O
VDDO
General-purpose I/O: can also be configured as a GCI
pin.
P11
I/O
VDDO
GPIO: P11
Keyboard scan output (column): KSO3
A/D converter input 24
P26
PWM0
I/O
VDDO
GPIO: P26
SPI_1: SPI_CS (slave only)
Optical control output: QOC0 Triac control 1
Current: 16 mA sink
BT_GPIO_7
I/O
VDDO
General-purpose I/O: can also be configured as a GCI
pin.
P30
I/O
VDDO
GPIO: P30
A/D converter input 9
Peripheral UART: puart_rts
UART receive data
F5
BT_UART_RXD
I
VDDO
F4
BT_UART_TXD
O
VDDO
UART transmit data
F3
BT_UART_RTS_N
O
VDDO
UART request to send output
G4
BT_UART_CTS_N
I
VDDO
UART clear to send input
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PRELIMINARY
CYW20707
Table 7. CYW20707 49-Pin FBGA List (Cont.)
Pin
G8
Signal
I/O
Power
Domain
Description
BT_CLK_REQ
O
VDDO
Used for shared-clock application.
P4
I/O
VDDO
GPIO: P4
Quadrature: QDY0
Peripheral UART: puart_rx
SPI_1: MOSI (master and slave) IR_TX
P24
I/O
VDDO
GPIO: P24
SPI_1: SPI_CLK (master and slave)
Peripheral UART: puart_tx
D8
SPI2_MISO_I2C_SC
L
I/O
VDDO
BSC CLOCK
E8
SPI2_MOSI_I2C_SDA
I/O
VDDO
BSC DATA
E7
SPI2_CLK
O
VDDO
Serial flash SPI clock
D7
SPI2_CSN
O
VDDO
Serial flash active-low chip select
C7
I2S_DI/PCM_IN
I/O
VDDO
PCM/I2S data input.
I2C_SDA
P12
I/O
VDDO
GPIO: P12
A/D converter input 23
I2S_DO/PCM_OUT
I/O
VDDO
PCM/I2S data output.
I2C_SCL
P3
I/O
VDDO
GPIO: P3
Quadrature: QDX1
Peripheral UART: puart_cts
SPI_1: SPI_CLK (master and slave)
P29
PWM3
I/O
VDDO
GPIO: P29
Optical control output: QOC3
A/D converter input 10, LED2
Current: 16 mA sink
P35
I/O
VDDO
GPIO: P35
A/D converter input 4
Quadrature: QDY1
Peripheral UART: puart_cts
BSC: SDA
A8
B7
I2S_CLK/PCM_CLK
I/O
VDDO
PCM/I2S clock Fp1
P2
I/O
VDDO
GPIO: P2
Quadrature: QDX0
Peripheral UART: puart_rx
SPI_1: SPI_CS (slave only)
SPI_1: MOSI (master only)
P28
PWM2
I/O
VDDO
GPIO: P28
Optical control output: QOC2
A/D converter input 11, LED1
Current: 16 mA sink
P37
I/O
VDDO
GPIO: P37
A/D converter input 2
Quadrature: QDZ1
SPI_1: MISO (slave only)
Auxiliary clock output: ACLK1
BSC: SCL
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PRELIMINARY
CYW20707
Table 7. CYW20707 49-Pin FBGA List (Cont.)
I/O
Power
Domain
2
I S_WS/
PCM_SYNC
I/O
VDDO
PCM sync/I2S word select
P0
I/O
VDDO
GPIO: P0
A/D converter input 29
Peripheral UART: puart_tx
SPI_1: MOSI (master and slave) IR_RX, 60Hz_main
Note: Not available during TM1 = 1.
P34
I/O
VDDO
GPIO: P34
A/D converter input 5
Quadrature: QDY0
Peripheral UART: puart_rx
External T/R switch control: tx_pd
I
VDDO
•
•
Pin
C8
G2
Signal
BT_OTP_3P3V_ON
Description
If OTP is used, pull this pin high.
If OTP is not used, pull this pin low.
JTAG
D5
JTAG_SEL
I/O
VDDO
ARM JTAG debug mode control.
Connect to GND for all applications.
Supplies
G1
BT_OTP_VDD3P3V
I
N/A
3.3V OTP supply voltage
B4
BT_IFVDD1P2
I
N/A
Radio IF PLL supply
A1
BT_PAVDD2P5
I
N/A
Radio PA supply
B1
BT_LNAVDD1P2
I
N/A
Radio LNA supply
C1
BT_VCOVDD1P2
I
N/A
Radio VCO supply
A3
BT_PLLVDD1P2
I
N/A
Radio RF PLL supply
B8, G6
VDDC
I
N/A
Core logic supply
G5
VDDO
I
N/A
Digital I/O supply voltage
–
N/A
Ground
A7, B2, B3, C2, D2, F6 VSS
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PRELIMINARY
CYW20707
2.1.2 36-Pin WLBGA List
Table 8. CYW20707 36-Pin WLBGA List
Ball
Signal
I/O
Power Domain
Description
Radio
A1
RFOP
I/O
VDD_RF
RF I/O antenna port
A5
XO_IN
I
VDD_RF
Crystal or reference input
A4
XO_OUT
O
VDD_RF
Crystal oscillator output
Voltage Regulators
D2
VBAT
I
N/A
VBAT input pin. This must be less than or equal to VDDO.
D1
VDD2P5_IN
I
N/A
2.5V LDO input
C1
VDDC_OUT
O
N/A
1.2V LDO output
RST_N
I
VDDO
Active-low reset input
D6
BT_GPIO_0
I
VDDO
BT_GPIO_0/BT_DEV_WAKE. A signal from the host to
the CYW20707 indicating that the host requires attention.
E6
BT_GPIO_1
O
VDDO
BT_GPIO_1/BT_HOST_WAKE. A signal from the
CYW20707 device to the host indicating that the Bluetooth
device requires attention.
C4
BT_GPIO_2
I
VDDO
When high, this signal extends the XTAL warm-up time for
external CLK requests. Otherwise, it is typically connected
to ground.
F2
BT_GPIO_3
I/O
VDDO
General-purpose I/O
P0
I
VDDO
LPO_IN
I
N/A
External LPO input
BT_GPIO_5
I/O
VDDO
General-purpose I/O: can also be configured as a GCI pin
P8
I
VDDO
•
•
•
GPIO: P8
A/D converter input 27
External T/R Switch Control: ~tx_pd
P33
I
VDDO
•
•
•
•
•
•
GPIO: P33
A/D converter input 6
Quadrature: QDX1
SPI_1: MOSI (slave only)
Auxiliary clock output: ACLK1
Peripheral UART: puart_rx
F5
BT_UART_RXD
I
VDDO
UART receive data
E5
BT_UART_TXD
O
VDDO
UART transmit data
Straps
C6
Digital I/O
C5
• GPIO: P0
• A/D converter input 29
• Peripheral UART: puart_tx
• SPI_1: MOSI (master and slave)
• IR_RX
• 60 Hz_main
Note: Not available during TM1 = 1.
F4
BT_UART_RTS_N
O
VDDO
UART request to send output
F3
BT_UART_CTS_N
I
VDDO
UART clear to send input
F6
BT_CLK_REQ
O
VDDO
Used for shared-clock application.
F1
SPI2_MISO_I2C_SCL
I/O
VDDO
BSC CLOCK
E3
SPI2_MOSI_I2C_SDA
I/O
VDDO
BSC DATA
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PRELIMINARY
CYW20707
Table 8. CYW20707 36-Pin WLBGA List (Cont.)
Ball
Signal
I/O
Power Domain
Description
E1
SPI2_CLK
I/O
VDDO
Serial flash SPI clock
E2
SPI2_CSN
I/O
VDDO
Serial flash active-low chip select
B6
I2S_DI/PCM_IN
I/O
VDDO
•
•
PCM/I2S data input.
I2C_SDA
P3
I
VDDO
•
•
•
•
GPIO: P3
Quadrature: QDX1
Peripheral UART: puart_cts
SPI_1: SPI_CLK (master and slave)
I2S_DO/PCM_OUT
I/O
VDDO
PCM/I2S data output.
I2C_SCL
BT_GPIO_6
I/O
VDDO
General-purpose I/O: can also be configured as a GCI pin
P9
I
VDDO
GPIO:P9
A/D converter input 26
External T/R switch control: tx_pd
I2S_CLK/PCM_CLK
I/O
VDDO
PCM/I2S clock
BT_GPIO_4
I/O
VDDO
General-purpose I/O: can also be configured as a GCI pin
P1
I
VDDO
GPIO:P1
A/D converter input 28
Peripheral UART: puart_rts
SPI_1: MISO (master and slave)
IR_TX
I2S_WS/PCM_SYNC
I/O
VDDO
PCM sync/I2S word select
P11
I
VDDO
GPIO: P11
A/D converter input 24
JTAG_SEL
I/O
VDDO
ARM JTAG debug mode control. Connect to GND for all
applications.
C2
BT_IFVDD1P2
I
N/A
Radio IF PLL supply
B1
BT_PAVDD2P5
I
N/A
Radio PA supply
B3
BT_PLLVDD1P2
I
N/A
Radio RF PLL supply
D5
VDDC
I
N/A
Core logic supply
E4
VDDO
I
N/A
Digital I/O supply voltage
–
N/A
Ground
A3
B4
A6
JTAG
B5
Supplies
A2, B2, C3, VSS
D3, D4
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PRELIMINARY
CYW20707
2.2 Ball Map
2.2.1 49-Pin FBGA Ball Map
Figure 8. CYW20707 49-Pin FBGA Ball Map
1
2
3
4
5
6
7
8
A
BT_PAVDD2P5
RFOP
BT_PLLVDD1P2
XO_IN
XO_OUT
RST_N
VSS
I2S_DO/PCM_OUT/P3/
P29/P35
A
B
BT_LNAVDD1P2
VSS
VSS
BT_IFVDD1P2
BT_GPIO_5/P15
BT_GPIO_6/
P11/P26
I2S_CLK/
PCM_CLK/
P2/P28/P37
VDDC
B
C
BT_VCOVDD1P2
VSS
NC
NC
BT_GPIO_3/P27/
P33
BT_GPIO_7/
P30
D
VBAT
VSS
NC
NC
JTAG_SEL
BT_GPIO_4/
P6/LPO_IN/
P31
SPI2_CSN
SPI2_MISO_I2C_SCL
D
E
VDD2P5_IN
VDD2P5_OUT
NC
BT_GPIO_2
NC
NC
SPI2_CLK
SPI2_MOSI_I2C_SDA
E
F
VDDC_OUT
BT_XTAL_STRAP_1
BT_UART_RTS_N
BT_UART_TXD
BT_UART_RXD
VSS
BT_GPIO_1/P25/
P32
BT_GPIO_0/P36/P38
F
G
BT_OTP_VDD3P3V
BT_OTP_3P3V_ON
BT_XTAL_STRAP_0
BT_UART_CTS_N
VDDO
VDDC
BT_TM1
BT_CLK_REQ/P4/P24
G
1
2
3
4
5
6
7
8
Document Number: 002-14792 Rev. *H
I2S_DI/PCM_IN/ I2S_WS/PCM_SYNC/P0/
P12
P34
C
Page 24 of 51
PRELIMINARY
CYW20707
2.2.2 36-Pin WLBGA Ball Map
Figure 9. CYW20707 36-Pin WLBGA Ball Map
1
F
E
SPI2_MISO_I2C_
SCL
SPI2_CLK
D
VDD2P5_IN
C
VDDC_OUT
B
A
2
BT_GPIO_3
P0
LPO_IN
SPI2_CSN
VBAT
3
4
5
BT_UART_CTS_N
BT_UART_RTS_N
BT_UART_RXD
SPI2_MOSI_I2C_SDA
VDDO
BT_UART_TXD
BT_GPIO_1
BT_HOST_WAKE
VSS
VSS
VDDC
BT_GPIO_0
BT_DEV_WAKE
BT_GPIO_5
P8
P33
BT_IFVDD1P2
VSS
BT_PAVDD2P5
VSS
BT_PLLVDD1P2
I2S_CLK/PCM_CLK
BT_GPIO_4
P1
JTAG_SEL
RFOP
VSS
I2S_DO/PCM_OUT
BT_GPIO_6
P9
XO_OUT
XO_IN
Document Number: 002-14792 Rev. *H
BT_GPIO_2
6
BT_CLK_REQ
RST_N
I2S_DI_PCM_IN
P3
I2S_WS/PCM_SYNC
P11
Page 25 of 51
PRELIMINARY
CYW20707
3. Specifications
3.1 Electrical Characteristics
Table 9 shows the maximum electrical rating for voltages referenced to VDD pin.
Table 9. Absolute Maximum Ratings
Specification
Parameter
Minimum
Ambient temperature of operation
–30
Nominal
25
Maximum
85
Units
°C
Storage temperature
–40
–
150
°C
ESD tolerance HBM
–2000
–
2000
V
ESD tolerance MM
–100
–
100
V
ESD tolerance CDM
–500
–
500
V
Latch-up
–200
–
200
mA
VDDC
–0.5
–
1.38
V
VDDO
–0.5
–
3.795
V
VDD_RF (excluding PA)
–0.5
–
1.38
V
VDDPA
–0.5
–
3.565
V
VBAT
–0.5
–
3.795
V
BT_OTP_VDD3P3V
–0.5
–
3.795
V
VDD2P5_IN
–0.5
–
3.795
V
Table 10 shows the power supply characteristics for the range TJ = 0°C to 125°C.
Table 10. Power Supply Specifications
Parameter
VDD Core
Conditions
Min.
Typ.
Max.
Units
–
1.14
1.2
1.26
V
VDDO
–
1.62
3.3
3.6
V
VDDRF
Excluding class 1 PA
1.14
1.2
1.26
V
VDDPA
Class 1 operation
2.25
2.5 to 2.8
2.94
V
–
1.62
3.3
3.6
V
1
1
VBAT
BT_OTP_VDD3P3V
–
3.0
3.3
3.6
V
VDD2P5_IN
–
3.0
3.3
3.6
V
1. VDDO must be ≥ VBAT.
Document Number: 002-14792 Rev. *H
Page 26 of 51
PRELIMINARY
CYW20707
Table 11. VDDC LDO Electrical Specifications
Parameter
Conditions
Min.
Typical
Max.
Input Voltage
–
1.62
3.3
Nominal Output Voltage
–
–
1.2
DC Accuracy
Accuracy at any step, including bandgap
reference.
–5
–
5
%
Output Voltage
Programmability
Range
0.89
–
1.34
V
Step Size
–
30
–
mV
Load Current
–
–
–
40
mA
Dropout Voltage
Iload = 40 mA
–
–
200
mV
Line Regulation
Vin from 1.62V to 3.6V, Iload = 40 mA
–
–
0.2
%Vo/V
Load Regulation
Iload = 1 mA to 40 mA, Vout = 1.2V, Package + –
PCB R = 0.3Ω
0.02
0.05
%Vo/mA
Quiescent Current
No load @Vin = 3.3V
–
18
23
μA
Power down Current
Vin = 3.3V @25C
–
0.2
–
μA
Vin = 3.6 @80C
–
TBD
–
–
Iload = 15 mA, 100 kHz
–
40
nV/sqrtHz
Iload = 15 mA, 2 MHz
–
14
nV/sqrtHz
–
dB
Output Noise
PSRR
Vin = 3.3, Vout = 1.2V,
Iload = 40 mA
1 kHz
65
–
3.6
Unit
V
V
10 kHz
60
–
–
dB
100 kHz
55
–
–
dB
Over Current Limit
–
–
–
mA
Turn-on Time
VBAT = 3.3V, BG already on, LDO OFF to ON, –
Co = 1 μF, 90% of Vout
100
–
100
μs
In-rush current during turnon
During start-up, Co = 1 μF
–
–
60
mA
Transient Performance
Iload = 1 mA to 15 mA and 15 mA to 1 mA in
1 μs
–
–
40
mV
Iload = 15 mA to 40 mA and 40 mA to 15 mA in –
1 μs
–
25
–
External Output Capacitor
Ceramic cap with ESR ≤ 0.5Ω
0.8
1
4.7
μF
External Input Capacitor
Ceramic, X5R, 0402, ±20%, 10V.
–
1
–
μF
Document Number: 002-14792 Rev. *H
Page 27 of 51
PRELIMINARY
CYW20707
Table 12. BTLDO_2P5 Electrical Specifications
Parameters
Conditions
Min
Typ
Max
Units
Input supply voltage, Vin Min = Vo + 0.2V = 2.7V (for Vo = 2.5V)
Dropout voltage requirement must be met under maximum
load for performance specs.
3.0
3.3
3.6
V
Nominal output voltage,
Vo
Default = 2.5V
–
2.5
–
V
Output voltage
programmability
Range
Accuracy at any step (including line/load regulation),
load >0.1 mA
2.2
–5
–
2.8
5
V
%
Dropout voltage
At max load
–
–
200
mV
Output current
–
0.1
–
70
mA
Quiescent current
No load; Vin = Vo + 0.2V, Vin = Vo + 0.2V
–
8
660
16
700
μA
Leakage current
Power-down mode. At junction temperature 85°C.
–
1.5
5
μA
Line regulation
Vin from (Vo + 0.2V) to 3.6V, max load
–
–
3.5
mV/V
Load regulation
Load from 1 mA to 70 mA, Vin = 3.6V
–
–
0.3
mV/mA
PSRR
Vin ≥ Vo + 0.2V, Vo = 2.5V, Co = 2.2 μF, max load, 100 Hz to 20
100 kHz
–
–
dB
LDO turn-on time
LDO turn-on time when rest of chip is up
–
–
150
μs
External output
capacitor, Co
Ceramic, X5R, 0402, (ESR: 5m-240 mΩ), ±20%, 6.3V
0.7
2.2
2.64
μF
External input capacitor
Ceramic, X5R, 0402, ±20%, 10V
–
1
–
μF
Document Number: 002-14792 Rev. *H
Page 28 of 51
PRELIMINARY
CYW20707
3.1.1 Digital I/O Characteristics
Table 13. Digital I/O Characteristics
Characteristics
Value
Symbol
Minimum
Typical
Maximum
Unit
VDDO = 1.8V
VIL
–
–
0.6
V
VDDO = 3.3
VIL
–
–
0.8
V
VDDO = 1.8V
VIH
1.1
–
–
V
VDDO = 3.3V
VIH
2.0
–
–
V
–
–
0.4
V
–
–
V
Input Voltage
•
•
Low
High
Output Voltage
•
Low
–
VOL
•
High
VDDO – 0.4V
VOH
Input Current
•
Low
–
IIL
–
–
1.0
μA
•
High
–
IIH
–
–
1.0
μA
Output Current
•
Low
VDDO = 3.3V, VOL = 0.4V
IOL
–
–
2.0
mA
•
High
VDDO = 3.3V, VOH = 2.9V
IOH
–
–
4.0
mA
VDDO = 1.8V, VOH = 1.4
IOH
–
–
TBD
mA
–
CIN
–
–
0.4
pF
Input capacitance
Note: In Table 14, current consumption measurements are taken at VBAT with the assumption that VBAT is connected to VDDO and
VDD2P5_IN.
Document Number: 002-14792 Rev. *H
Page 29 of 51
PRELIMINARY
CYW20707
3.1.2 Current Consumption
Table 14. Bluetooth, BLE, BR and EDR Current Consumption, Class 1
Mode
3DH5/3DH5
Remarks
–
Typ.
Unit
37.10
mA
BLE
•
BLE
Connected 600 ms interval
211
μA
•
BLE ADV
Unconnectable 1.00 sec
176
μA
•
BLE Scan
No devices present. A 1.28-sec interval with 11.25 ms scan window.
355
μA
DMx/DHx
•
DM1/DH1
–
32.15
mA
•
DM3/DH3
–
38.14
mA
•
DM5/DH5
–
38.46
mA
HIDOFF
Deep sleep
2.69
μA
Page scan
Periodic scan rate is 1.28 sec
0.486
mA
Receive
•
1 Mbps
Peak current level during reception of a basic-rate packet.
26.373
mA
•
EDR
Peak current level during the reception of a 2 or 3 Mbps rate packet.
26.373
mA
4.95
mA
Sniff Slave
•
11.25 ms
–
•
22.5 ms
–
2.6
mA
•
495.00 ms
Based on one attempt and no timeout.
254
μA
Transmit
•
1 Mbps
Peak current level during the transmission of a basic-rate packet: GFSK output 60.289
power = 10 dBm.
mA
•
EDR
Peak current level during the transmission of a 2 or 3 Mbps rate packet. EDR
output power = 8 dBm.
mA
52.485
Note: In Table 15, current consumption measurements are taken at input of VDD2P5_IN, VDDO, and VBAT combined
(VDD2P5_IN = VDDO = VBAT = 3.0V).
Table 15. Bluetooth and BLE Current Consumption, Class 2 (0 dBm)
Mode
3DH5/3DH5
Remarks
–
Typ.
Unit
31.57
mA
BLE
•
BLE ADV
Unconnectable 1.00 sec
174
μA
•
BLE Scan
No devices present. A 1.28-sec interval with 11.25 ms scan window.
368
μA
DMx/DHx
•
DM1/DH1
–
27.5
mA
•
DM3/DH3
–
31.34
mA
•
DM5/DH5
–
32.36
mA
Document Number: 002-14792 Rev. *H
Page 30 of 51
PRELIMINARY
CYW20707
3.2 RF Specifications
Note:
■
All specifications in Table 16 are for industrial temperatures.
■
All specifications in Table 16 are single-ended. Unused inputs are left open.
Table 16. Receiver RF Specifications
Minimum
Typical 1
Maximum
–
2402
–
2480
MHz
GFSK, 0.1% BER, 1 Mbps
–
–93.5
–
dBm
LE GFSK, 0.1% BER, 1 Mbps
–
–96.5
–
dBm
/4-DQPSK, 0.01% BER, 2 Mbps
–
–95.5
–
dBm
Parameter
Conditions
Unit
General
Frequency range
RX sensitivity
2
8-DPSK, 0.01% BER, 3 Mbps
–
–89.5
–
dBm
Maximum input
GFSK, 1 Mbps
–
–
–20
dBm
Maximum input
/4-DQPSK, 8-DPSK, 2/3 Mbps
–
–
–20
dBm
Interference Performance
C/I cochannel
GFSK, 0.1% BER
–
9.5
11
dB
C/I 1 MHz adjacent channel
GFSK, 0.1% BER
–
–5
0
dB
C/I 2 MHz adjacent channel
GFSK, 0.1% BER
–
–40
–30.0
dB
C/I > 3 MHz adjacent channel
GFSK, 0.1% BER
–
–49
–40.0
dB
C/I image channel
GFSK, 0.1% BER
–
–27
–9.0
dB
C/I 1 MHz adjacent to image channel
GFSK, 0.1% BER
–
–37
–20.0
dB
C/I cochannel
11
13
dB
–
–8
0
dB
C/I 2 MHz adjacent channel
/4-DQPSK, 0.1% BER
/4-DQPSK, 0.1% BER
/4-DQPSK, 0.1% BER
–
–
–40
–30.0
dB
C/I > 3 MHz adjacent channel
8-DPSK, 0.1% BER
–
–50
–40.0
dB
C/I image channel
–27
–7.0
dB
C/I 1 MHz adjacent to image channel
/4-DQPSK, 0.1% BER
/4-DQPSK, 0.1% BER
–
–
–40
–20.0
dB
C/I cochannel
8-DPSK, 0.1% BER
–
17
21
dB
C/I 1 MHz adjacent channel
8-DPSK, 0.1% BER
–
–5
5
dB
C/I 1 MHz adjacent channel
C/I 2 MHz adjacent channel
8-DPSK, 0.1% BER
–
–40
–25.0
dB
C/I > 3 MHz adjacent channel
8-DPSK, 0.1% BER
–
–47
–33.0
dB
C/I Image channel
8-DPSK, 0.1% BER
–
–20
0
dB
C/I 1 MHz adjacent to image channel
8-DPSK, 0.1% BER
–
–35
–13.0
dB
Out-of-Band Blocking Performance (CW)3
30 MHz–2000 MHz
0.1% BER
–
–10.0
–
dBm
2000–2399 MHz
0.1% BER
–
–27
–
dBm
2498–3000 MHz
0.1% BER
–
–27
–
dBm
3000 MHz–12.75 GHz
0.1% BER
–
–10.0
–
dBm
Document Number: 002-14792 Rev. *H
Page 31 of 51
PRELIMINARY
CYW20707
Table 16. Receiver RF Specifications (Cont.)
Parameter
Conditions
Minimum
Typical 1
Maximum
Unit
Out-of-Band Blocking Performance, Modulated Interferer
776–764 MHz
CDMA
–
–104
–
dBm
824–849 MHz
CDMA
–
–104
–
dBm
1850–1910 MHz
CDMA
–
–234
–
dBm
824–849 MHz
EDGE/GSM
–
–104
–
dBm
880–915 MHz
EDGE/GSM
–
–104
–
dBm
1710–1785 MHz
EDGE/GSM
–
–234
–
dBm
1850–1910 MHz
EDGE/GSM
–
–234
–
dBm
1850–1910 MHz
WCDMA
–
–234
–
dBm
1920–1980 MHz
WCDMA
–
–234
–
dBm
–39.0
–
–
dBm
Intermodulation Performance5
BT, Df = 5 MHz
–
Spurious
Emissions6
30 MHz to 1 GHz
–
–
–
–62
dBm
1 GHz to 12.75 GHz
–
–
–
–47
dBm
65 MHz to 108 MHz
FM Rx
–
–147
–
dBm/Hz
746 MHz to 764 MHz
CDMA
–
–147
–
dBm/Hz
851–894 MHz
CDMA
–
–147
–
dBm/Hz
925–960 MHz
EDGE/GSM
–
–147
–
dBm/Hz
1805–1880 MHz
EDGE/GSM
–
–147
–
dBm/Hz
1930–1990 MHz
PCS
–
–147
–
dBm/Hz
2110–2170 MHz
WCDMA
–
–147
–
dBm/Hz
-118
-
dBm/Hz
20707 GLONASS Band Spurious Emissions7
Spurious Emissions
-
Out-of-Band Noise Floor
1570-1580MHz
GPS
-
-147
-
dBm/Hz
1592-1610MHz
GLONASS
-
-147
-
dBm/Hz
1.
2.
3.
4.
5.
Typical operating conditions are 1.22V operating voltage and 25°C ambient temperature.
The receiver sensitivity is measured at BER of 0.1% on the device interface.
Meets this specification using a front-end bandpass filter.
Numbers are referred to the pin output with an external BPF filter.
f0 = –64 dBm Bluetooth-modulated signal, f1 = –39 dBm sine wave, f2 = –39 dBm Bluetooth-modulated signal, f0 = 2f1 – f2, and |f2 –
f1| = n*1 MHz, where n is 3, 4, or 5. For the typical case, n = 4.
6. Includes baseband radiated emissions.
7. Max TX power (12dBm at chip out), Modulation is PRBS9, Modulation type is GFSK.
Note:
■
All specifications in Table 17 are for industrial temperatures.
■
All specifications in Table 17 are single-ended. Unused inputs are left open.
Document Number: 002-14792 Rev. *H
Page 32 of 51
PRELIMINARY
CYW20707
Table 17. Transmitter RF Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Unit
General
Frequency range
Class1: GFSK Tx
Class1: EDR Tx
power1
power2
–
2402
–
2480
MHz
–
–
12
–
dBm
–
–
9
–
dBm
Class 2: GFSK Tx power
–
–
2
–
dBm
Power control step
–
2
4
8
dB
Modulation Accuracy
/4-DQPSK Frequency Stability
/4-DQPSK RMS DEVM
/4-QPSK Peak DEVM
/4-DQPSK 99% DEVM
–
–10
–
10
kHz
–
–
–
20
%
–
–
–
35
%
–
–
–
30
%
8-DPSK frequency stability
–
–10
–
10
kHz
8-DPSK RMS DEVM
–
–
–
13
%
8-DPSK Peak DEVM
–
–
–
25
%
8-DPSK 99% DEVM
–
–
–
20
%
–
–
–26
dBc
In-Band Spurious Emissions
1.0 MHz < |M – N| < 1.5 MHz
–
1.5 MHz < |M – N| < 2.5 MHz
–
–
–
–20
dBm
|M – N| > 2.5 MHz
–
–
–
–40
dBm
Out-of-Band Spurious Emissions
30 MHz to 1 GHz
–
–
–
–36.03
dBm
1 GHz to 12.75 GHz
–
–
–
–30.03, 4
dBm
1.8 GHz to 1.9 GHz
–
–
–
–47.0
dBm
5.15 GHz to 5.3 GHz
–
–
–
–47.0
dBm
1.
2.
3.
4.
12 dBm output for GFSK measured with PAVDD = 2.5V.
9 dBm output for EDR measured with PAVDD = 2.5V.
Maximum value is the value required for Bluetooth qualification.
Meets this spec using a front-end band pass filter.
Document Number: 002-14792 Rev. *H
Page 33 of 51
PRELIMINARY
CYW20707
Table 18. BLE RF Specifications
Parameter
Frequency range
Rx
sense1
Tx power2
Mod Char: Delta F1 average
Mod Char: Delta F2
max3
Mod Char: Ratio
Conditions
Minimum
Typical
Maximum
Unit
N/A
2402
–
2480
MHz
GFSK, 0.1% BER, 1 Mbps
–
–96.5
–
dBm
N/A
–
9
–
dBm
N/A
225
255
275
kHz
N/A
99.9
–
–
%
N/A
0.8
0.95
–
%
1. Dirty Tx is Off.
2. The BLE Tx power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc. The output is capped at 12 dBm
out. The BLE Tx power at the antenna port cannot exceed the 10 dBm EIRP specification limit.
3. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz.
3.3 Timing and AC Characteristics
In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.
3.3.1 UART Timing
Table 19. UART Timing Specifications
Reference
Characteristics
Min.
Max.
Unit
1
Delay time, UART_CTS_N low to UART_TXD valid
–
24
Baud out cycles
2
Setup time, UART_CTS_N high before midpoint of stop bit
–
10
ns
3
Delay time, midpoint of stop bit to UART_RTS_N high
–
2
Baud out cycles
Figure 10. UART Timing
Document Number: 002-14792 Rev. *H
Page 34 of 51
PRELIMINARY
CYW20707
3.3.2 SPI Timing
The SPI interface can be clocked up to 12 MHz.
Table 20 and Figure 11 show the timing requirements when operating in SPI Mode 0 and 2.
Table 20. SPI Mode 0 and 2
Reference
1
Characteristics
Minimum
Time from slave assert SPI_INT to master assert SPI_CSN (DirectRead)
0
Maximum
Unit
∞
ns
2
Time from master assert SPI_CSN to slave assert SPI_INT (DirectWrite)
0
∞
ns
3
Time from master assert SPI_CSN to first clock edge
20
∞
ns
4
Setup time for MOSI data lines
8
1
/2 SCK
ns
5
Hold time for MOSI data lines
8
1
/2 SCK
ns
6
Time from last sample on MOSI/MISO to slave deassert SPI_INT
0
100
ns
7
Time from slave deassert SPI_INT to master deassert SPI_CSN
0
∞
ns
8
Idle time between subsequent SPI transactions
1 SCK
∞
ns
Figure 11. SPI Timing, Mode 0 and 2
8
SPI_CSN
SPI_INT
(DirectWrite)
2
6
SPI_INT
(DirectRead)
7
1
3
SPI_CLK
(Mode 0)
SPI_CLK
(Mode 2)
4
SPI_MOSI
SPI_MISO
‐
Not Driven
First Bit
First Bit
5
Second Bit
Last bit
‐
Second Bit
Last bit
Not Driven
Table 21 and Figure 12 show the timing requirements when operating in SPI Mode 0 and 2.
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Table 21. SPI Mode 1 and 3
Reference
Characteristics
Minimum
Maximum
Unit
1
Time from slave assert SPI_INT to master assert SPI_CSN
(DirectRead)
0
∞
ns
2
Time from master assert SPI_CSN to slave assert SPI_INT
(DirectWrite)
0
∞
ns
3
Time from master assert SPI_CSN to first clock edge
20
∞
ns
4
Setup time for MOSI data lines
8
1
/2 SCK
ns
5
Hold time for MOSI data lines
8
1
/2 SCK
ns
6
Time from last sample on MOSI/MISO to slave deassert SPI_INT
0
100
ns
7
Time from slave deassert SPI_INT to master deassert SPI_CSN
0
∞
ns
8
Idle time between subsequent SPI transactions
1 SCK
∞
ns
Figure 12. SPI Timing, Mode 1 and 3
SPI_CSN
8
SPI_INT
(DirectWrite)
2
6
SPI_INT
(DirectRead)
7
1
SPI_CLK
(Mode 1)
3
SPI_CLK
(Mode 3)
4
5
SPI_MOSI
‐
Invalid bit
First bit
Last bit
‐
SPI_MISO
Not Driven
Invalid bit
First bit
Last bit
Not Driven
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3.3.3 BSC Interface Timing
The specifications in Table 22 references Figure 13.
Table 22. BSC Interface Timing Specifications (up to 1 MHz)
Reference
1
Characteristics
Minimum
Clock frequency
–
Maximum
100
Unit
kHz
400
800
1000
2
START condition setup time
650
–
ns
3
START condition hold time
280
–
ns
4
Clock low time
650
–
ns
5
Clock high time
280
–
ns
0
–
ns
–
ns
6
Data input hold
7
Data input setup time
100
8
STOP condition setup time
280
–
ns
9
Output valid from clock
–
400
ns
10
Bus free time2
650
–
ns
time1
1. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START
or STOP conditions.
2. Time that the CBUS must be free before a new transaction can start.
Figure 13. BSC Interface Timing Diagram
1
5
SCL
2
4
8
6
3
7
SDA
IN
10
9
SDA
OUT
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3.3.4 PCM Interface Timing
Short Frame Sync, Master Mode
Figure 14. PCM Timing Diagram (Short Frame Sync, Master Mode)
1
2
3
P C M _ B C LK
4
P C M _ S YN C
8
PCM _OUT
H IG H IM P E D A N C E
5
7
6
P C M _ IN
Table 23. PCM Interface Timing Specifications (Short Frame Sync, Master Mode)
Reference
Characteristics
Minimum
Typical
Maximum
Unit
1
PCM bit clock frequency
–
–
20.0
MHz
2
PCM bit clock LOW
20.0
–
–
ns
3
PCM bit clock HIGH
20.0
–
–
ns
4
PCM_SYNC delay
0
–
5.7
ns
5
PCM_OUT delay
–0.4
–
5.6
ns
6
PCM_IN setup
16.9
–
–
ns
7
PCM_IN hold
25.0
–
–
ns
8
Delay from rising edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
–0.4
–
5.6
ns
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Short Frame Sync, Slave Mode
Figure 15. PCM Timing Diagram (Short Frame Sync, Slave Mode)
1
2
3
PCM _BCLK
4
5
PCM _SYN C
9
PCM _O U T
H IG H IM P E D A N C E
6
8
7
P C M _ IN
Table 24. PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)
Reference
Minimum
Typical
Maximum
PCM bit clock frequency
–
–
TBD
MHz
2
PCM bit clock LOW
TBD
–
–
ns
3
PCM bit clock HIGH
TBD
–
–
ns
4
PCM_SYNC setup
TBD
–
–
ns
5
PCM_SYNC hold
TBD
–
–
ns
6
PCM_OUT delay
TBD
–
TBD
ns
7
PCM_IN setup
TBD
–
–
ns
8
PCM_IN hold
TBD
–
–
ns
9
Delay from rising edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
TBD
–
TBD
ns
1
Characteristics
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Unit
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CYW20707
Long Frame Sync, Master Mode
Figure 16. PCM Timing Diagram (Long Frame Sync, Master Mode)
1
2
3
PCM_BCLK
4
PCM_SYNC
8
PCM_OUT
HIGH IMPEDANCE
Bit 1
Bit 0
5
7
6
Bit 0
PCM_IN
Bit 1
Table 25. PCM Interface Timing Specifications (Long Frame Sync, Master Mode)
Reference
Characteristics
Minimum
Typical
Maximum
Unit
1
PCM bit clock frequency
–
–
TBD
MHz
2
PCM bit clock LOW
TBD
–
–
ns
3
PCM bit clock HIGH
TBD
–
–
ns
4
PCM_SYNC delay
TBD
–
TBD
ns
5
PCM_OUT delay
TBD
–
TBD
ns
6
PCM_IN setup
TBD
–
–
ns
7
PCM_IN hold
TBD
–
–
ns
8
Delay from rising edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
TBD
–
TBD
ns
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CYW20707
Long Frame Sync, Slave Mode
Figure 17. PCM Timing Diagram (Long Frame Sync, Slave Mode)
1
2
3
PCM_BCLK
4
5
PCM_SYNC
9
PCM_OUT
Bit 0
HIGH IMPEDANCE
Bit 1
6
8
7
Bit 0
PCM_IN
Bit 1
Table 26. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)
Reference
Characteristics
Minimum
Typical
Maximum
Unit
1
PCM bit clock frequency
–
–
TBD
MHz
2
PCM bit clock LOW
TBD
–
–
ns
3
PCM bit clock HIGH
TBD
–
–
ns
4
PCM_SYNC setup
TBD
–
–
ns
5
PCM_SYNC hold
TBD
–
–
ns
6
PCM_OUT delay
TBD
–
TBD
ns
7
PCM_IN setup
TBD
–
–
ns
8
PCM_IN hold
TBD
–
–
ns
9
Delay from rising edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
TBD
–
TBD
ns
3.3.5 I2S Timing
The CYW20707 supports two independent I2S digital audio ports. The I2S interface supports both master and slave modes. The I2S
signals are:
■
I2S clock: I2S SCK
■
I2S Word Select: I2S WS
■
I2S Data Out: I2S SDO
■
I2S Data In: I2S SDI
I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S SDO always stays as an output. The channel
word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I2S bus, per the
I2S specification. The MSB of each data word is transmitted one bit clock cycle after the I2S WS transition, synchronous with the falling
edge of bit clock. Left-channel data is transmitted when I2S WS is low, and right-channel data is transmitted when I2S WS is high.
Data bits sent by the CYW20707 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the
rising edge of I2S_SSCK.
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CYW20707
The clock rate in master mode is either of the following:
48 kHz x 32 bits per frame = 1.536 MHz
48 kHz x 50 bits per frame = 2.400 MHz
The master clock is generated from the input reference clock using a N/M clock divider.
In the slave mode, any clock rate is supported to a maximum of 3.072 MHz.
Note: Timing values specified in Table 27 are relative to high and low threshold levels.
Table 27. Timing for I2S Transmitters and Receivers
Transmitter
Lower Limit
Receiver
Upper Limit
Lower Limit
Upper Limit
Min
Max
Min
Max
Min
Max
Min
Max
Notes
Ttr
–
–
–
Tr
–
–
–
1
Clock Period T
Master Mode: Clock generated by transmitter or receiver
HIGH tHC
0.35Ttr
–
–
–
0.35Ttr
–
–
–
2
LOWtLC
0.35Ttr
–
–
–
0.35Ttr
–
–
–
2
Slave Mode: Clock accepted by transmitter or receiver
HIGH tHC
–
0.35Ttr
–
–
–
0.35Ttr
–
–
3
LOW tLC
–
0.35Ttr
–
–
–
0.35Ttr
–
–
3
Rise time tRC
–
–
0.15Ttr
–
–
–
–
4
Transmitter
Delay tdtr
–
–
–
0.8T
–
–
–
–
5
Hold time thtr
0
–
–
–
–
–
–
–
4
Receiver
Setup time tsr
–
–
–
–
–
0.2Tr
–
–
6
Hold time thr
–
–
–
–
–
0
–
–
6
1. The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data
transfer rate.
2. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and
tLC are specified with respect to T.
3. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So
long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used.
4. Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can
result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than
or equal to zero, so long as the clock rise time tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr.
5. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving
the receiver sufficient setup time.
6. The data setup and hold time must not be less than the specified receiver setup and hold time.
Note: The time periods specified in Figure 18 and Figure 19 are defined by the transmitter speed. The receiver specifications must
match transmitter performance.
Document Number: 002-14792 Rev. *H
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CYW20707
Figure 18. I2S Transmitter Timing
T
tRC*
t LC > 0.3 5T
t H C > 0.3 5T
V H = 2.0 V
SC K
V L = 0.8 V
t h tr > 0
t o tr < 0 .8 T
SD an d W S
T = C lo ck p e riod
T tr = M in im u m allo w ed clo ck p erio d fo r tran sm itter
T = T tr
* t R C is o n ly re le v an t fo r tran sm itters in slav e m od e .
Figure 19. I2S Receiver Timing
T
t LC > 0.35T
t HC > 0.35
V H = 2.0V
SCK
V L = 0.8V
t sr > 0.2T
t hr > 0
SD and W S
T = Clock period
T r = M inim um allow ed clock period for transm itter
T > T r
Document Number: 002-14792 Rev. *H
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CYW20707
4. Mechanical Information
4.1 Package Diagrams
Figure 20. CYW20707 49-pin FBGA Package (4.5 mm x 4.0 mm)
Document Number: 002-14792 Rev. *H
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PRELIMINARY
CYW20707
Figure 21. CYW20707 36-pin WLBGA Package (2.8 mm x 2.5 mm)
Document Number: 002-14792 Rev. *H
Page 45 of 51
PRELIMINARY
CYW20707
4.2 Tape Reel and Packaging Specifications
Table 28. CYW20707 Tape Reel Specifications
Parameter
Value
Quantity per reel
2500
Reel diameter
13 inches
Hub diameter
4 inches
Tape width
16 mm
Tape pitch
12 mm
The top-left corner of the CYW20707 package is situated near the sprocket holes, as shown in Figure 22.
Figure 22. Pin 1 Orientation
Pin 1: Top left corner of package toward sprocket holes
Document Number: 002-14792 Rev. *H
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PRELIMINARY
CYW20707
5. Ordering Information
Table 29. Ordering Information
Part Number
Package
CYW20707UA2KFFB4G
49-pin FBGA
CYW20707UA2EKUBGT
36-pin WLBGA
Document Number: 002-14792 Rev. *H
Page 47 of 51
PRELIMINARY
CYW20707
6. Additional information
6.1 Acronyms and Abbreviations
The following list of acronyms and abbreviations may appear in this document.
Term
Description
ADC
analog-to-digital converter
AFH
adaptive frequency hopping
AHB
advanced high-performance bus
APB
advanced peripheral bus
APU
audio processing unit
ARM7TDMI-S™
Acorn RISC Machine 7 Thumb instruction, Debugger, Multiplier, Ice, Synthesizable
BTC
Bluetooth controller
COEX
coexistence
DFU
device firmware update
DMA
direct memory access
EBI
external bus interface
HCI
Host Control Interface
HV
high voltage
IDC
initial digital calibration
IF
intermediate frequency
IRQ
interrupt request
JTAG
Joint Test Action Group
LCU
link control unit
LDO
low dropout
LHL
lean high land
LPO
low power oscillator
LV
LogicVision™
MIA
multiple interface agent
PCM
pulse code modulation
PLL
phase locked loop
PMU
power management unit
POR
power-on reset
PWM
pulse width modulation
QD
quadrature decoder
RAM
random access memory
RC oscillator
A resistor-capacitor oscillator is a circuit composed of an amplifier, which provides the output signal, and a
resistor-capacitor network, which controls the frequency of the signal.
RF
radio frequency
ROM
read-only memory
RX/TX
receive, transmit
SPI
serial peripheral interface
SW
software
UART
universal asynchronous receiver/transmitter
UPI
µ-processor interface
WD
watchdog
Document Number: 002-14792 Rev. *H
Page 48 of 51
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CYW20707
In most cases, acronyms and abbreviations are defined upon first use. For a more complete list of acronyms and other terms used in
Cypress documents, go to: http://www.cypress.com/glossary.
6.2 IoT Resources
Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your
design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of
information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software
updates. Customers can acquire technical documentation and software from the Cypress Support Community website
(https://community.cypress.com/).
Document Number: 002-14792 Rev. *H
Page 49 of 51
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CYW20707
Document History Page
Document Title: CYW20707 Bluetooth SoC for Embedded Wireless Devices
Document Number: 002-14792
51
Revision
**
ECN
-
Orig. of
Change
-
Submission
Date
04/17/2015
Description of Change
20707-DS100-R
Initial release
*A
-
-
06/15/2015
20707-DS101-R
Updated:
• “Internal LDO”.
• Figure 3: “LDO Functional Block Diagram” (added)
• “Collaborative Coexistence” (added)
• “Global Coexistence Interface” (added)
• “SECI I/O” (added)
• Table 6: “CYW20707 49-Ball Pin List”
• Table 8: “Power Supply Specifications”
• Section 5. “Ordering Information”
•
*B
-
-
10/02/2015
20707-DS102-R
Updated:
• Table 6: “CYW20707 49-Ball Pin List”
*C
-
-
03/24/2016
20707-DS103-R
Updated:
Table 6: “CYW20707 49-Ball Pin List”
*D
-
-
04/07/2016
20707-DS104-R
Updated:
• Figure 19: “CYW20707 49-pin FBGA Package (4.5 mm x 4.0 mm)”
*E
-
-
04/20/2016
20707-DS105-R
Added:
• 36-pin WLBGA Package (2.8mm x2.5mm) feature bullet on cover page
• Added informative notes in “One-Time Programmable Memory” and “Clock
Frequencies”
• “36-Pin WLBGA Package”
• Table7. “CYW20707 49-Pin FBGA List"
• Figure 21. “CYW20707 36-pin WLBGA Package (2.8 mm x 2.5 mm)
• 36-pin WLBGA part to Section 5. “Ordering Information”
*F
-
-
05/27/2016
20707-DS106-R
Updated:
• Cover page minor edits.
• Figure 2. “Reset Timing.
• Figure 3. “LDO Functional Block Diagram.
• Figure 8. “CYW20707 49-Pin FBGA Ball Map.
• Table10. “Power Supply Specifications".
• Table11. “VDDC LDO Electrical Specifications".
• Ambient operating temperatures in Section 5. “Ordering Information” .
Added:
• “Link Control Layer”.
• Table12. “BTLDO_2P5 Electrical Specifications"
*G
5450827
LAPK
12/07/2016
Added Cypress Part Numbering Scheme and Mapping Table.
*H
5755272
NIBK
05/30/2017
Updated Cypress Logo and Copyright.
Updated to Cypress template.
Document Number: 002-14792 Rev. *H
Page 50 of 51
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CYW20707
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Lighting & Power Control
Memory
cypress.com/iot
cypress.com/powerpsoc
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs | Training
| Components
Technical Support
cypress.com/support
cypress.com/memory
PSoC
cypress.com/psoc
Touch Sensing
cypress.com/touch
USB Controllers
Wireless/RF
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP| PSoC 6
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-14792 Rev. *H
Revised May 30, 2017
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