Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CYW43362
Single-Chip IEEE 802.11™
b/g/n MAC/Baseband/Radio
The Cypress CYW43362 single-chip device provides the highest level of integration for Interent of Things applications and handheld
wireless systems, featuring integrated IEEE 802.11™ b/g and IEEE 802.11n. It includes a 2.4 GHz WLAN CMOS power amplifier
(PA) that meets the output power requirements of most handheld systems. An optional external low-noise amplifier (LNA) and external PA are also supported.
Along with the integrated power amplifier, the CYW43362 also includes integrated transmit and receive baluns, further reducing the
overall solution cost.
Host interface options include SDIO v2.0 that can operate in 4b or 1b modes.
Utilizing advanced design techniques and process technology to reduce active and idle power, the CYW43362 is designed to
address the needs of highly mobile devices that require minimal power consumption and compact size. It includes a power management unit that simplifies the system power topology and allows for operation directly from a rechargeable mobile platform battery
while maximizing battery life.
Features
■
■
■
■
■
■
Single-band 2.4 GHz IEEE 802.11 b/g/n
Integrated WLAN CMOS power amplifier with internal
power detector and closed-loop power control
Internal fractional-N PLL enables the use of a wide
range of reference clock frequencies
Supports IEEE 802.15.2 external 3-wire and 4-wire
coexistence schemes to optimize bandwidth utilization
with other co-located wireless technologies such as
Bluetooth, Zigbee, or BT Smart. Also supports sECI
coexistence interface.
Supports SDIO v2.0 (50 MHz, 4-bit and 1-bit)
Integrated ARM Cortex™-M3 CPU with on-chip memory enables running IEEE 802.11 firmware that can be
field-upgraded with future features.
Supports WMM®, WMM-PS, and Wi-Fi Voice Personal
(upgradable to Voice Enterprise in the future)
Security:
❐ Hardware WAPI acceleration engine
❐ AES and TKIP in hardware for faster data encryption and IEEE 802.11i compatibility
❐ WPA™- and WPA2™- (Personal) support for powerful encryption and authentication
Programmable dynamic power management
Supports battery voltage range from 2.3V to 4.8V supplies with internal switching regulator
1 kbit One-Time Programmable (OTP) memory for
storing board parameters
69-bump WLBGA
(4.52 mm x 2.92 mm, 0.4 mm pitch)
■
■
■
■
■
■
Figure 1. CYW43362 System Block Diagram
VIO
Vbatt
2.4 GHz WLAN Tx
WL_RST_N
WLAN Host I/F
2.4 GHz WLAN Rx
SDIO
CYW43362
CBF
System Clock
Sleep Clock
Coexistence Interface
Cypress Semiconductor Corporation
Document No. 002-14779 Rev. *H
T/R
Switch
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 30, 2017
CYW43362
Introduction
This document provides engineering design information for the CYW43362, a single chip with an integrated 2.4 GHz RF transceiver,
MAC, and baseband processor that fully supports the IEEE 802.11™ b/g/n standards.
The information provided is intended for hardware design engineers who will be incorporating the CYW43362 into their designs.
Cypress part numbering scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number
Cypress Part Number
BCM43362
CYW43362
BCM43362KUBG
CYW43362KUBG
IoT Resources
Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your
design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software
updates. Customers can acquire technical documentation and software from the Cypress Support Community website (http://community.cypress.com/).
Document No. 002-14779 Rev. *H
Page 2 of 51
CYW43362
Contents
1. Overview ............................................................ 4
8. WLAN Software Architecture......................... 22
1.1
Overview ............................................................. 4
8.1
Host Software Architecture ................................22
1.2
Standards Compliance ........................................ 5
8.2
Device Software Architecture .............................22
8.2.1 Remote Downloader ...............................22
8.3
Wireless Configuration Utility .............................23
2. Power Supplies and Power Management ....... 6
2.1
WLAN Power Management ................................. 6
2.2
Power Supply Topology ...................................... 6
2.3
Voltage Regulators .............................................. 7
9.1
Signal Assignments ............................................23
2.4
PMU Sequencing ................................................ 7
9.2
WLAN GPIO Signals and Strapping Options .....31
2.5
Low-Power Shutdown ......................................... 8
10. DC Characteristics.......................................... 32
2.6
CBUCK Regulator Features ................................ 8
10.1 Absolute Maximum Ratings ...............................32
3. Frequency References ..................................... 9
10.2 Environmental Ratings .......................................32
9. Pinout and Signal Descriptions..................... 23
3.1
Crystal Interface and Clock Generation .............. 9
10.3 Electrostatic Discharge Specifications ...............32
3.2
TCXO .................................................................. 9
3.3
External 32.768 kHz Low-Power Oscillator ....... 11
10.4 Recommended Operating Conditions and
DC Characteristics .............................................33
4. WLAN System Interfaces ............................... 12
4.1
SDIO v2.0 .......................................................... 12
4.1.1 SDIO Pin Descriptions ........................... 12
4.2
External Coexistence Interface ........................ 13
5. Wireless LAN MAC and PHY.......................... 15
5.1
MAC Features ................................................... 15
5.1.1 MAC Description .................................... 15
5.1.1.1.PSM ............................................... 16
5.1.1.2.WEP .............................................. 16
5.1.1.3.TXE ................................................ 16
5.1.1.4.RXE ............................................... 16
5.1.1.5.IFS ................................................. 17
5.1.1.6.TSF ................................................ 17
5.1.1.7.NAV ............................................... 17
5.1.1.8.MAC-PHY Interface ....................... 17
11. WLAN RF Specifications................................ 34
11.1 2.4 GHz Band General RF Specifications ..........34
11.2 WLAN 2.4 GHz Receiver Performance
Specifications .....................................................34
11.3 WLAN 2.4 GHz Transmitter Performance
Specifications .....................................................37
11.4 General Spurious Emissions Specifications .......38
12. Internal Regulator Electrical Specifications. 39
12.1 Core Buck Regulator ..........................................39
12.2 3.3V LDO (LDO3P3) ..........................................41
12.3 CLDO .................................................................41
12.4 LNLDO1 .............................................................42
13. System Power Consumption ......................... 43
PHY Description ................................................ 17
5.2.1 PHY Features ........................................ 17
14. Interface Timing and AC Characteristics ..... 44
6. WLAN Radio Subsystem ................................ 20
14.2 SDIO High-Speed Mode Timing .........................45
5.2
14.1 SDIO Default Mode Timing ................................44
6.1
Receive Path ..................................................... 20
14.3 JTAG Timing ......................................................46
6.2
Transmit Path .................................................... 20
15. Package Information ...................................... 47
6.3
Calibration ......................................................... 20
15.1 Package Thermal Characteristics ......................47
15.1.1 Junction Temperature Estimation and
PSI Versus Thetajc ..................................47
7. CPU and Global Functions............................. 21
7.1
WLAN CPU and Memory Subsystem ............... 21
7.2
One-Time Programmable Memory .................... 21
7.3
GPIO Interface .................................................. 21
17. Ordering Information...................................... 49
7.4
JTAG Interface ................................................. 21
18. References ...................................................... 49
7.5
UART Interface ................................................ 21
Document History Page ................................................. 50
16. Mechanical Information.................................. 48
Sales, Solutions, and Legal Information ...................... 51
Document No. 002-14779 Rev. *H
Page 3 of 51
CYW43362
1 . Ove rv ie w
1.1 Overview
The Cypress CYW43362 provides the highest level of integration for a Internet of Things applications and handheld wireless system,
with integrated IEEE 802.11 b/g/n. It provides a small form-factor solution with minimal external components to drive down cost for
mass volumes and allows for flexibility in size, form, and function. The CYW43362 is designed to address the needs of highly mobile
devices that require minimal power consumption and reliable operation.
Figure 2 shows the interconnect of all the major physical blocks in the CYW43362 and their associated external interfaces, which
are described in greater detail in the following sections.
Figure 2. CYW43362 Block Diagram
SWREG
LDO
PMU Ctrl
LPO
XTAL OSC
Always ON
Buffer
POR
Power
supply
SLEEP CLK
Dedicated
crystal or TCXO
TCXO signal shared
with BT/FM/GPS chip
WL_RST_N
SDIOD
SDIO
WDog timer
GPIO
GPIO
UART
UART
JTAG
JTAG
BT COEX
Document No. 002-14779 Rev. *H
PA
(Int)
RADIO
MAC
ROM
(448 KB)
802.11b/g/n
RAM
(240 KB)
2.4 GHz
ARM processor
Single-stream 802.11n PHY
JTAG
Backplane
OTP
EXT LNA/RF
Switch Control
Page 4 of 51
CYW43362
1.2 Standards Compliance
The CYW43362 supports the following standards:
■
IEEE 802.11n
■
802.11b
■
802.11g
■
802.11d
■
802.11h
■
802.11i
■
802.11j
The CYW43362 will support the following future drafts/standards:
■
802.11w—Secure Management Frames
■
802.11 Extensions:
❐ WMM®
❐ 802.11i MAC Enhancements
❐ 802.11r Fast Roaming Support (between APs)
❐ 802.11k Radio Resource Measurement
■
Security:
❐ WEP
❐ WAPI
❐ WPA™ Personal
❐ WPA2™ Personal
❐ AES (Hardware Accelerator)
❐ TKIP (HW Accelerator)
❐ CKIP (SW Support)
■
QOS Protocols:
❐ WMM
❐ WWM-PS (U-APSD)
❐ WWM-SA
■
Proprietary Protocols:
❐ WFAEC
■
Coexistence Interfaces:
❐ Supports IEEE 802.15.2 external three-wire coexistence scheme to support additional wireless technologies, such as
Bluetooth, Zigbee, or BT Smart.
Document No. 002-14779 Rev. *H
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CYW43362
2. Power Supplies and Power Management
2.1 WLAN Power Management
The CYW43362 has been designed with the stringent power consumption requirements of portable devices in mind. All areas of the
chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the CYW43362 integrated RAM is a low-leakage memory with dynamic clock control. The
dominant supply current consumed by the RAM is leakage current only.
Additionally, the CYW43362 includes an advanced WLAN power management unit (PMU) sequencer. The PMU sequencer provides
significant power savings by putting the CYW43362 into various power management states appropriate to the current environment
and activities that are being performed. The power management unit enables and disables internal regulators, switches, and other
blocks based on a computation of the required resources and a table that describes the relationship between resources and the time
needed to enable and disable them. Power-up sequences are fully programmable. Configurable, free-running counters, which run
on the 32.768 kHz low-power oscillator (LPO) sleep clock in the PMU sequencer, are used to turn individual regulators and power
switches on and off. Clock speeds are dynamically changed, or gated off, as appropriate for the current mode. Slower clock speeds
are used wherever possible.
The CYW43362 power states are described as follows:
■
Active mode—All components in the CYW43362 are powered up and fully functional with active carrier sensing and frame
transmission and receiving. All required regulators are enabled and put in the most efficient mode (PWM or Burst) based on
the load current. Clock speeds are dynamically adjusted by the PMU sequencer.
■
Sleep mode—The radio, AFE, PLLs, and the crystal oscillator are powered down. The rest of the CYW43362 remains powered up in an IDLE state. All main clocks are shut down. The 32.768-kHz LPO sleep clock is available only for the PMU
sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active mode. In
Sleep mode, the primary power consumed is due to leakage current.
■
Power-down modes—The CYW43362 has a full power-down mode and a low-power shutdown mode. A full power-down
occurs when there is no VIO voltage, and WL_RST_N and EXT_SMPRS_REQ are low. A low-power shutdown occurs
when VIO is present, and WL_RST_N and EXT_SMPRS_REQ are low. In low-power shutdown, only the band gap and
LDO3P3 are on. Both power-down modes are exited when the host asserts either WL_RST_N or EXT_SMPS_REQ high.
■
External mode—In this mode, the following are true:
❐ The assertion of EXT_SMPS_REQ turns only the Core Buck (CBUCK) regulator on.
❐ The WLAN is in reset (WL_RST_N = low).
❐ The state of LDO3P3 and the band gap are dependent on VBAT and VIO.
2.2 Power Supply Topology
The CYW43362 contains a Power Management Unit (PMU), a buck-mode switching regulator, and three low noise LDOs. These
integrated regulators simplify power supply design in WLAN embedded designs. All regulator inputs and outputs are brought out to
pins on the CYW43362, providing system designers with the flexibility to choose which of the CYW43362 integrated regulators to
use. One option is to supply the PMU from a single, variable power supply, VBAT, which can range from 2.3V to 4.8V. Using this
option, all of the required voltages are provided by CYW43362 regulators except for a low current rail, VIO, which must be provided
by the host to power the I/O signal buffers when the chip is out of reset.
Alternately, if specific rails such as 3.3V, 1.8V, and 1.2V already exist in the system, appropriate regulators in the CYW43362 can be
bypassed, thereby reducing the cost and board space associated with external regulator components such as inductors and large
capacitors.
The CBUCK and CLDO get powered whenever the reset signal is deasserted. The CBUCK regulator can be turned ON by asserting
EXT_SMPS_REQ high. Asserting EXT_PWM_REQ high will set CBUCK to PWM mode. Driving EXT_PWM_REQ low will put
CBUCK in Burst mode. Optionally, LNLDO may also be powered. All regulators are powered down only when the reset signal is
asserted.
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CYW43362
Figure 3. Power Topology
CYW43362
CYW43362
VDDIO_RF
CYW43362
LN LDO1
LDO3P31
WL Radio – Part A
RF PLL
WL OTP (3.3V)
WRF AFE
1.2V
WRF XO
2.5V to
3.4V
WRF CLPO/Ext. LPO
WRF LNA/Rx, BG, RCAL
Section
sensitive to
power supply
noise
WRFTx
WRF Radio – BB PLL
VBAT 2.3V to 4.8V
WL_RST_N
1.4V to
Core Buck 1.8V
Regulator
ext_smps_req
ext_pwm_req
CLDO
WRF OTP
1.2V
WL Digital, including
memory
Internal
LNLDO
(30 mA)
Loads not
sensitive
to power
supply noise
WRF VCO and LOGEN
VDDIO
VIO
VDDIO_SD
Notes:
1. LDO3P3 is always enabled when VIO is present in order
to provide bias for VDDIO_RF and the external RF switch.
2. Areas in dark gray are internal to the BCM43362.
3. VDDIO and VDDIO_SD can be powered from separate
supplies if SDIO signaling needs to be at a different level
than VDDIO. This diagram shows the more common case
where VDDIO and VDDIO_SD are powered from the same
supply.
Internal WLAN Power
Amplifiers
Optional
(250 mA)
External device (BT/FM/GPS/other)
2.3 Voltage Regulators
All CYW43362 regulator output voltages are PMU programmable and have the following nominal capabilities. The currents listed
below indicate regulator capabilities. See System Power Consumption on page 43 for the actual expected loads.
■
Core Buck switching regulator (CBUCK): 2.3–4.8V input, nominal 1.5V output (up to 500 mA).
■
LDO3P3: 2.3–4.8V input, nominal 3.3V output (up to 40 mA)
■
CLDO (for the core): 1.45–2.0V input, nominal 1.2V output (up to 150 mA)
■
Low-noise LNLDO1: 1.45–2.0V input, nominal 1.2V output (up to 150 mA)
See Internal Regulator Electrical Specifications on page 39 for full regulator specifications.
2.4 PMU Sequencing
The WLAN PMU sequencer is responsible for minimizing system power consumption. It enables and disables various system
resources based on a computation of the required resources and a table that describes the relationship between resources and the
time needed to enable and disable them. Resource requests come from several sources: clock requests from cores, the minimum
resources defined in the ResourceMin register, and the resources requested by any active resource request timers. The PMU
sequencer maps clock requests into a set of resources required to produce the requested clocks.
Each resource is in one of four states: enabled, disabled, transition_on, and transition_off. Each resource has a timer that contains 0
when the resource is enabled or disabled and a nonzero value in the transition states. The timer is loaded with the resource's
time_on or time_off value when the PMU determines that the resource must be enabled or disabled. That timer decrements on each
LPO sleep clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on
value is 0, the resource can go immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can
Document No. 002-14779 Rev. *H
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CYW43362
go immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition
or the timer load-decrement sequence.
During each clock cycle, the PMU sequencer performs the following actions:
1.
Computes the required resource set based on requests and the resource dependency table.
2.
Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource
and inverts the ResourceState bit.
3.
Compares the request with the current resource status and determines which resources must be enabled or disabled.
4.
Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents.
5.
Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.
2.5 Low-Power Shutdown
The CYW43362 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other device
in the system, remain operational. When WLAN is not needed, the WLAN core can be put in reset by asserting WL_RST_N (logic
LOW). VDDIO_RF and VDDIO remain powered while VIO and VBAT are both present, allowing the CYW43362 to be effectively off
while keeping the I/O pins powered. During a low-power shut-down state, provided VIO continues to be supplied to the CYW43362,
most outputs are tristated and most inputs are disabled. Input voltages must remain within the limits defined for normal operation.
This is done to prevent current paths or create loading on any digital signals in the system, enabling the CYW43362 to be a fully integrated embedded device that takes full advantage of the lowest power-saving modes.
Two signals on the CYW43362, the system clock input (OSCIN) and sleep clock input (EXT_SLEEP_CLK), are designed to be highimpedance inputs that do not load down the driving signal even if the CYW43362 does not have VDDIO power applied to it. When
the CYW43362 is powered on from this state, it is the same as a normal power-up, and the device does not contain any information
about its state from before it was powered down.
2.6 CBUCK Regulator Features
The CBUCK regulator has several features that help make the CYW43362 ideal for mobile devices. First, the regulator uses 3.2
MHz as its PWM switching frequency for Buck regulation. This high frequency allows the use of small passive components for the
switcher's external circuit, thereby saving PCB space in the design. In addition, the CBUCK regulator has three modes of operation:
PWM mode for low-ripple output and for fast transient response and extended load ranges, Burst Mode for lower currents, and Low
Power Burst Mode for higher efficiency when the load current is very low (Low Power Burst mode is not available for external
devices).
The CBUCK supports external SMPS request to allow flexibility of supplying 1.8V to CYW43362, BCM2076, and other external
devices when EXT_SMPS_REQ is asserted high. It also supports low ripple PWM mode (7 mVpp typical) for noise-sensitive applications when EXT_PWM_REQ is asserted high. A 100 µs wait/settling time from the assertion of EXT_PWM_REQ high before
increasing the load current allows the internal integrator precharging to complete. This is not a requirement, but is preferred.
Table 2 lists the mode the CBUCK operates in (Burst or PWM), based on various external control signals and internal CBUCK mode
register settings.
Table 2. CBUCK Operating Mode Selection
WL_RST_L
EXT_SMPS_REQ
EXT_PWM_REQ
Internal CBUCK Mode
Required
CBUCK Mode
0
0
X
X
Off
0
1
0
X
BURST
0
1
1
X
PWM
1
0
X
BURST
BURST
1
0
X
PWM
PWM
1
1
0
BURST
BURST
1
1
0
PWM
PWM
1
1
1
X
PWM
Document No. 002-14779 Rev. *H
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CYW43362
For detailed CBUCK performance specifications, see Core Buck Regulator on page 39.
3. Frequency References
An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. No software settings are
required to differentiate between the two. In addition, a low-power oscillator (LPO) is provided for lower power mode timing.
3.1 Crystal Interface and Clock Generation
The CYW43362 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator, including all external components, is shown in Figure 4. Consult the reference schematics for the latest configuration.
Figure 4. Recommended Oscillator Configuration
C
OSCIN
12 – 27 pF
C
OSCOUT
12 – 27 pF
R
Note: Resistor value determined by crystal drive
level. See reference schematics for details.
The CYW43362 uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing. This enables it to
operate using numerous frequency references. This may either be an external source such as a TCXO or a crystal interfaced directly
to the CYW43362.
The default frequency reference setting is a 26 MHz crystal or TCXO. The signal requirements and characteristics for the crystal
interface are shown in Table 3 on page 10.
Note: Although the fractional-N synthesizer can support many reference frequencies, frequencies other than the default require
support to be added in the driver, plus additional extensive system testing. Contact Cypress for further details.
3.2 TCXO
As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the Phase
Noise requirements listed in Table 3 on page 10. When the clock is provided by an external TCXO, there are two possible connection methods, as shown in Figure 5 and Figure 6:
1.
If the TCXO is dedicated to driving the CYW43362, it should be connected to the OSC_IN pin through an external 1000 pF
coupling capacitor, as shown in Figure 5. The internal clock buffer connected to this pin will be turned OFF when the CYW43362
goes into sleep mode. When the clock buffer turns ON and OFF, there will be a small impedance variation up to ±15%. Power
must be supplied to the WRF_XTAL_VDD1P2 pin.
2.
An alternative is to DC-couple the TCXO to the WRF_TCXO_IN pin, as shown in Figure 6. Use this method when the same TCXO
is shared with other devices and a change in the input impedance is not acceptable because it may cause a frequency shift that
cannot be tolerated by the other device sharing the TCXO. This pin is connected to a clock buffer powered from
WRF_TCXO_VDD3P3. If the power supply to this buffer is always on (even in sleep mode), the clock buffer is always on, thereby
ensuring a constant input impedance in all states of the device. The maximum current drawn from WRF_TCXO_VDD3P3 is
approximately 500 µA.
Document No. 002-14779 Rev. *H
Page 9 of 51
CYW43362
Figure 5. Recommended Circuit to Use with an External Dedicated TCXO
1000 pF
TCXO
OSCIN
NC
OSCOUT
WRF_TCXO_IN
WRF_TCXO_VDD3P3
Figure 6. Recommended Circuit to Use with an External Shared TCXO
To other devices
TCXO
WRF_TCXO_IN
Connect to a supply (1.7V to 3.3V)
that is powered up or down with the
external TCXO clock.
WRF_TCXO_VDD3P3
OSCIN
OSCOUT
NC
Table 3. Crystal Oscillator and External Clock Requirements and Performance
External Frequency
Reference
Crystal
Parameter
Conditions/Notes
Min
Typ
Max
Min
Frequency
–
Between 12 MHz and 52 MHza
Crystal load capacitance
–
–
12
–
ESR
–
–
–
60
Input Impedance
(OSCIN)b
Resistive
Typ
Max
Units
pF
Ω
30k
100k
–
Ω
pF
Capacitive
–
–
7.5
Resistive
30k
100k
–
Ω
Capacitive
–
–
4
pF
AC-coupled analog signal
400
–
1200
mVp-p
OSCIN input low level
DC-coupled digital signal
0
–
0.2
V
OSCIN input high level
DC-coupled digital signal
1.0
–
1.36
V
400
–
TCXO_
VDDd
mVp-p
–20
–
20
ppm
Input Impedance
(WRF_TCXO_IN)
OSCIN input voltage
WRF_TCXO_IN input voltage DC-coupled analog signalc
Frequency tolerance
Initial + over temperature
–
Document No. 002-14779 Rev. *H
–20
–
20
Page 10 of 51
CYW43362
Table 3. Crystal Oscillator and External Clock Requirements and Performance (Cont.)
External Frequency
Reference
Crystal
Parameter
Conditions/Notes
Min
Typ
Max
Min
Typ
Max
Units
Duty cycle
26 MHz clock
40
50
60
%
Phase Noisee, f
(IEEE 802.11 b/g)
26 MHz clock at 1 kHz offset
–
–
–119
dBc/Hz
26 MHz clock at 10 kHz offset
–
–
–129
dBc/Hz
26 MHz clock at 100 kHz offset
–
–
–134
dBc/Hz
26 MHz clock at 1 MHz offset
–
–
–139
dBc/Hz
26 MHz clock at 1 kHz offset
–
–
–124
dBc/Hz
26 MHz clock at 10 kHz offset
–
–
–134
dBc/Hz
26 MHz clock at 100 kHz offset
–
–
–139
dBc/Hz
26 MHz clock at 1 MHz offset
–
–
–144
dBc/Hz
Phase Noisee, f
(IEEE 802.11n, 2.4 GHz)
a.
The frequency step size is approximately 80 Hz. The CYW43362 does not auto-detect the reference clock frequency; the frequency is specified in the
software/NVRAM file.
b.
The internal clock buffer connected to this pin will be turned off when the CYW43362 goes into Sleep mode. When the clock buffer turns on and off, there
will be a small impedance variation up to ±15%.
c.
This input has an internal DC blocking capacitor, so do not include an external DC blocking capacitor.
d.
The maximum allowable voltage swing for the WRF_TCXO_IN input is equal to the WRF_TCX0_VDD3P3 supply voltage range, which is 1.7V to 3.3V.
e.
For a clock reference other than 26 MHz, 20 × log10(f/26) dB should be added to the limits, where f = the reference clock frequency in MHz.
f.
If the selected clock has a flat phase-noise response above 100 kHz, then it is acceptable to subtract 1 dB from all 1 kHz, 10 kHz, and 100 kHz values
shown, and ignore the 1 MHz requirement.
3.3 External 32.768 kHz Low-Power Oscillator
The CYW43362 uses a secondary low-frequency sleep clock for low-power mode timing. Either the internal low-precision LPO or an
external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process,
voltage, and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a
small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons.
Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in
Table 4.
Note: The CYW43362 will auto-detect the LPO clock. If it senses a clock on the EXT_SLEEP_CLK pin, it will use that clock. If it
doesn't sense a clock, it will use its own internal LPO.
■
To use the internal LPO: Tie EXT_SLEEP_CLK to ground. Do not leave this pin floating. To use an external LPO: Connect the external 32.768 kHz clock to EXT_SLEEP_CLK.
Document No. 002-14779 Rev. *H
Page 11 of 51
CYW43362
Table 4. External 32.768 kHz Low-Power Oscillator Specifications
Specification
Symbol
Parameter
Condition/Notes
Minimum
Typical
Maximum
Units
Fr
Frequency
–
–
32768
–
Hz
f/fr
Frequency tolerance
At 25°C
–30
–
+30
ppm
–20°C 1.9 µF
–
7
20
mVpp
PWM load step transient
voltage error
VBAT = 2.7V to 4.8V,
current step = 150 to 400 mA,
1 µsec rise-time based on 0402, 6.3V,
X5R, and 4.7 µFc ceramic capacitor.
–
100
200
mV
PWM line step
transient voltage error
VBAT step from 2.3 to 2.7V,
10 µsec rise-time,
fixed 500 mA load based on 0402, 6.3V,
X5R, and 4.7 µFb ceramic capacitor.
–
50
100
mV
PWM load regulationa
VBAT = 2.7V to 4.8V,
10 mA to 500 mA load.
Inductor DCR < 137.5 mΩ
–
–
+30
mV
PWM line regulationa
VBAT = 2.7V to 4.8V,
500 mA load.
Inductor DCR < 137.5 mΩ
–
–
+10
mV
Burst mode ripple voltage, static Load < 30 mA.
Measure with 20 MHz BW limit.
–
–
80
mVpp
30 mA < Load < 200 mA.
Measure with 20 MHz BW limit.
–
–
200
mVpp
Burst mode load step transient
voltage error
VBAT = 2.7V to 4.8V,
current step 10 to 200 mA,
1 µsec rise-time based on 0402, 6.3V,
X5R, and 4.7 µFb ceramic capacitor.
–
60
120
mV
Burst mode line step transient
voltage error
VBAT step from 2.3V to 2.7V,
10 µsec rise-time, fixed 200 mA load based on 0402, 6.3V,
X5R, and 4.7 µFb ceramic capacitor.
–
50
100
mV
Burst mode load regulation
VBAT = 2.7V to 4.8V,
10 mA to 200 mA load
–
35
50
mV
Input voltage 2.7 to 4.8V, 200 mA load
–
44
70
mV
Peak PWM mode efficiency
200 mA load current
30 mA load current
80
60
90
–
%
%
Burst mode efficiency
5 mA load current
70
80
–
%
Burst line regulation
d
Document No. 002-14779 Rev. *H
Page 39 of 51
CYW43362
Table 18. Core Buck Regulator (Cont.)
Minimum
Typical
Maximum
Units
Start-up time from
power down
Specification
–
–
1350
1500
µs
Burst to PWM mode
transient voltage error
Ensure load current < 200 mA during
a mode change
–
–
160
mV
External inductor
See preferred inductor list
–
1.5
–
µH
External output capacitor
Ceramic, X5R, 0402, Cap-ESR < 4 mΩ
ESL < 700 pH at 3.2 MHz, ±20%, 6.3V
–
4.7
–
µF
External input
capacitor
For SR_VDDBAT1 pins,
ceramic, X5R, 0603, Cap-ESR < 4 mΩ
at 3.2 MHz, ±10%, 6.3V
–
4.7
–
µF
Input supply voltage
ramp-up time
0 to 4.3V
40
–
–
µs
a.
Notes
The maximum continuous supply voltage is 4.8V. Brief spikes above this 4.8V can be tolerated. Specifically, voltages as high as 5.5V for up to 10 seconds
cumulative duration over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds cumulative duration over the lifetime of the
device are allowed.
b.
These are not load or line step transient tests.
c.
More capacitance can be used to reduce the transient error at the output.
d.
VBAT < 4.3V. Inductor DCR < 137.5 mΩ, ACR < 1Ω.
An efficiency plot for the CBUCK regulator is shown in Figure 17. The plot shows typical performance for nominal process silicon,
Vout = 1.8V, VBAT = 3.6V, and temperature = 25°C.
Figure 17. CBUCK Efficiency
100
90
Power Efficiency in %
80
70
60
50
40
PWM mode
Burst mode
30
20
10
0
0.1
1
10
100
1000
Load in mA
Document No. 002-14779 Rev. *H
Page 40 of 51
CYW43362
12.2 3.3V LDO (LDO3P3)
Table 19. 3.3V LDO (LDO3P3)
Specification
Notes
Input supply voltage
–
Output current
–
Output voltage, Vo
Step size 100 mV.
Default = 3.3V.
Dropout voltage
Output voltage DC accuracy
Quiescent current
No load
Line regulation
Vin from (Vo + 0.2V) to 4.8V,
maximum load
Load regulation
Leakage current
Minimum
Typical
Maximum
Units
2.3
3.6
4.8a
Volts
–
–
40
mA
2.4
3.3
3.4
Volts
At max load
–
–
200
mV
Include line/load
regulation.
–5
–
+5
%
–
8
17
µA
–0.2
–
+0.2
%Vo/V
Load from 1 mA to 40 mA
–
0.02
0.05
%Vo/mA
Power-down mode
–
–
5
µA
PSRR
VBAT 3.6V, Vo = 2.5V,
Co = 1 µF, max load,
100 Hz to 1 MHz
20
–
–
dB
Start-up time
From the rising edge of VIO as
the chip powers up from a full power down
(that is, band gap off)
–
1200
1400
µs
LDO turn-on time
LDO turn-on time
when rest of chip is up
–
–
100
µs
In-rush current during turn-on
From its output capacitor in fully discharged
state
–
–
135
mA
External output capacitor, Co
Ceramic, X5R, 0402,
(ESR: 30 mΩ–200 mΩ),
±10%, 10V
–
1
–
µF
External input capacitor
For SR_VDDBAT2 pin (shared
with Band gap) Ceramic, X5R, 0603, (ESR:
30 mΩ–200 mΩ), ±10%, 10V
–
1
–
µF
a.
The maximum continuous supply voltage is 4.8V. Brief spikes above this 4.8V can be tolerated. Specifically, voltages as high as 5.5V for up to 10 seconds
cumulative duration over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds cumulative duration over the lifetime of the
device are allowed.
12.3 CLDO
Table 20. CLDO
Notes
Minimum
Typical
Maximum
Units
Input supply voltage, Vin
Specification
Min = 1.25 + 0.2V = 1.45V.
Dropout voltage requirement must be met
under max load.
1.45
1.5
2.0
Volts
Output current
–
Output voltage, Vo
Programmable in 25 mV
steps
Dropout voltage
Output voltage DC accuracy
Quiescent current
No-load
Line regulation
Vin from (Vo + 0.2V) to 2V,
max load
Load regulation
Load from 1 mA to 150 mA
Leakage current
Power-down
Document No. 002-14779 Rev. *H
–
–
150
mA
1.075
1.2
1.325
Volts
At max load
–
–
200
mV
Include line/load regulation
Vin > Vo + 0.2V
–4
–
+4
%
–
10
15
µA
–0.2
–
+0.2
%Vo/V
–
0.02
0.05
%Vo/mA
–
–
10
µA
Page 41 of 51
CYW43362
Table 20. CLDO
Specification
Minimum
Typical
Maximum
Units
@1 kHz, Vin 1.5V,
Co = 1–2.2 µF
20
40
–
dB
Start-up time
From full-chip power downa
–
1250
1400
µs
LDO turn-on time
LDO turn-on time when
rest of chip is up
–
–
180
µs
In-rush current during turn-on
From its output capacitor in fully
discharged state
–
–
150
mA
External output capacitor, Co
(nominal values)
Ceramic, X5R, 0402,
(ESR: 30 mΩ–200 mΩ), ±10%, 10V
–
2.2
–
µF
External input capacitor
(nominal values)
Only use an external
input cap at VDD_LDO
pin if it is not supplied
from CBUCK output.
Ceramic, X5R, 0402, (ESR: 30 mΩ–
200 mΩ), ±10%, 10V
–
1
2.2
µF
PSRR
a.
Notes
With CBUCK soft-starting concurrently.
12.4 LNLDO1
Table 21. LNLDO1
Specification
Notes
Input supply voltage, Vin
Min = 1.25 + 0.2V = 1.45V
Dropout voltage requirement must be
met under max load.
Output current
–
Output voltage, Vo
Programmable in 25 mV
steps
Dropout voltage
Output voltage DC accuracy
Quiescent current
No-load
Line regulation
Vin from (Vo+0.2V) to 2V,
max load
Load regulation
Leakage current
Minimum
Typical
Maximum
Units
1.45
1.5
2.0
Volts
–
–
150
mA
1.075
1.2
1.325
Volts
At max load
–
–
200
mV
Include line/load regulation
Vin > Vo+0.2V
–4
–
+4
%
–
31
44
µA
–0.2
–
+0.2
%Vo/V
Load from 1 mA to 150 mA
–
0.02
0.05
%Vo/mA
Power-down
–
–
10
µA
Output noise
@30 kHz, 60 mA load
Co = 2.2 µF
@100 kHz, 60 mA load
Co = 2.2 µF
–
–
60
30
nV/rt Hz
nV/rt Hz
PSRR
@1 kHz, Vin 1.5V, Co = 2.2 µF
20
50
–
dB
LDO turn-on time
LDO turn-on time when
rest of chip is up
–
–
180
µs
In-rush current during turn-on
From its output capacitor in fully
discharged state
–
–
150
mA
External output capacitor, Co
(nominal values)
Ceramic, X5R, 0402,
(ESR: 30 mΩ–200 mΩ),
±10%, 10V
–
2.2
–
µF
Note: Recommended inductor for CBUCK: 1.5 µH ± 20%.
Murata® LQM21PN1R5MC0 2.0 × 1.25 × 0.55 mm DCR = 0.26Ω ± 25%.
Murata LQM2MPN1R5NG0 2.0 × 1.60 × 1.00 mm DCR = 0.11Ω ± 25%.
Document No. 002-14779 Rev. *H
Page 42 of 51
CYW43362
13. System Power Con sumption
Note: Table 22 shows typical values.
Power consumption referenced to VBAT @ 3.6V, 20°C, VDDIO = 1.8V, CBUCK out = 1.5V.
Table 22. System Power Consumption
WLAN Operational Modes
Total (Ivbat)
OFF1
11 µA
2
40 µA
OFF
IDLE
185 µA
200 µA
SLEEP5
Rx (Listen)
3
52 mA
4
59 mA
Rx (Active)
1.9 mA
Power Save6, 9
Tx CCK (11 Mbps at 18.5 dBm)7, 11
320 mA
8, 11
270 mA
10, 11
260 mA
Tx OFDM (54 Mbps at 15.5 dBm)
Tx OFDM (65 Mbps at 14.5 dBm)
Note 1: WL_RST_N = Low, VDDIO is not present
Note 2: WL_RST_N = Low, VDDIO is present
Note 3: Carrier Sense (CCA) when no carrier present
Note 4: Carrier Sense (CS) detect/Packet Rx
Note 5: Intra-beacon Sleep
Note 6: Beacon Interval = 102.4 ms, DTIM = 1, Beacon duration = 1 ms @1 Mbps.
Integrated Sleep + wakeup + Beacon Rx current over 1 DTIM interval.
Note 7: CCK power at chip port. Duty cycle is 100%. Includes PA contribution at 3.6V.
Note 8: OFDM power at chip port. Duty cycle is 100%. Includes PA contribution at 3.6V.
Note 9: In WLAN power-saving mode, the following blocks are powered down: Crystal oscillator, Baseband PLL, AFE, RF PLL, Radio
Note 10: OFDM power at chip port is 16 dBm, duty cycle is 100%, includes PA contribution at 3.6V.
The above blocks are turned ON in the required order with sufficient time for them to settle. This sequencing is done by the PMU controller that controls
the settling time for each of the blocks. It also has information to determine the order in which the blocks should be turned ON. The settling times and
the dependency order are programmable in the PMU controller. The default CLK settling time is set to 8 ms at power-up. It can be reduced after
power-up.
Note 11: Absolute junction temperature limits maintained through active thermal monitoring and dynamic Tx duty cycle limiting.
Document No. 002-14779 Rev. *H
Page 43 of 51
CYW43362
14. Interface Ti ming and AC Characteristics
Note: Values in this document are design goals and are subject to change based on the results of device characterization.
Unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in
Table 11 on page 32 and Table 13 on page 33. Functional operation outside of these limits is not guaranteed.
14.1 SDIO Default Mode Timing
SDIO default mode timing is shown by the combination of Figure 18 and Table 23 on page 44.
Figure 18. SDIO Bus Timing (Default Mode)
fPP
tWL
tWH
SDIO_CLK
tTHL
tTLH
tISU
tIH
Input
Output
tODLY
tODLY
(max)
(min)
Table 23. SDIO Bus Timing a Parameters (Default Mode)
Parameter
Symbol
Minimum
Typical
Maximum
Unit
SDIO CLK (All values are referred to minimum VIH and maximum VILb)
Frequency—Data Transfer mode
fPP
0
–
25
MHz
Frequency—Identification mode
fOD
0
–
400
kHz
Clock low time
tWL
10
–
–
ns
Clock high time
tWH
10
–
–
ns
Clock rise time
tTLH
–
–
10
ns
Clock fall time
tTHL
–
–
10
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
tISU
5
–
–
ns
Input hold time
tIH
5
–
–
ns
–
14
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time—Data Transfer mode
Document No. 002-14779 Rev. *H
tODLY
0
Page 44 of 51
CYW43362
Table 23. SDIO Bus Timing a Parameters (Default Mode)
Parameter
Symbol
Output delay time—Identification mode
Minimum
tODLY
a.
Timing is based on CL 40 pF load on CMD and Data.
b.
min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.
0
Typical
–
Maximum
50
Unit
ns
14.2 SDIO High-Speed Mode Timing
SDIO high-speed mode timing is shown by the combination of Figure 19 and Table 24.
Figure 19. SDIO Bus Timing (High-Speed Mode)
fPP
tWL
tWH
50% VDD
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tOH
Table 24. SDIO Bus Timing a Parameters (High-Speed Mode)
T
Parameter
Symbol
Minimum
Typical
Maximum
Unit
SDIO CLK (all values are referred to minimum VIH and maximum VILb)
Frequency – Data Transfer Mode
Frequency – Identification Mode
Clock low time
Clock high time
Clock rise time
Clock fall time
fPP
fOD
tWL
tWH
tTLH
tTHL
0
0
7
7
–
–
–
–
–
–
–
–
50
400
–
–
3
3
MHz
kHz
ns
ns
ns
ns
tISU
tIH
6
2
–
–
–
–
ns
ns
tODLY
tOH
CL
–
2.5
–
–
–
–
14
–
40
ns
ns
pF
Inputs: CMD, DAT (referenced to CLK)
Input setup Time
Input hold Time
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode
Output hold time
Total system capacitance (each line)
a.
Timing is based on CL 40pF load on CMD and Data.
b.
min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO.
Document No. 002-14779 Rev. *H
Page 45 of 51
CYW43362
14.3 JTAG Timing
Table 25. JTAG Timing Characteristics
Period
Output
Maximum
Output
Minimum
TCK
125 ns
–
–
–
–
TDI
–
–
–
20 ns
0 ns
TMS
–
–
–
20 ns
0 ns
TDO
–
100 ns
0 ns
–
–
250 ns
–
–
–
–
Signal Name
JTAG_TRST
Document No. 002-14779 Rev. *H
Setup
Hold
Page 46 of 51
CYW43362
15. Package Information
15.1 Package Thermal Characteristics
Table 26. Package Thermal Characteristicsa
Characteristic
Value in Still Air
JA (°C/W)
JB (°C/W)
JC (°C/W)
44.88
JT (°C/W)
0.04
1.20
0.20
JB (°C/W)
14.21
Maximum Junction Temperature Tj (°C)
125
Maximum Power Dissipation (W)
1.2
b
a.
No heat sink, TA = 70°C. This is an estimate based on a 4-layer PCB that conforms to EIA/JESD51–7 (101.6 mm x 114.3 mm x 1.6 mm) and P = 1.2W
continuous dissipation.
b.
Absolute junction temperature limits maintained through active thermal monitoring and dynamic Tx duty cycle limiting.
15.1.1 Junction Temperature Estimation and PSI Versus Thetajc
Package thermal characterization parameter PSI-JT (JT) yields a better estimation of actual junction temperature (TJ) versus using
the junction-to-case thermal resistance parameter Theta-JC (JC). The reason for this is JC assumes that all the power is dissipated
through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom and sides of
the package. JT takes into account power dissipated through the top, bottom, and sides of the package. The equation for calculating the device junction temperature is as follows:
TJ = TT + P JT
Where:
■
TJ = junction temperature at steady-state condition, °C
■
TT = package case top center temperature at steady-state condition, °C
■
P = device power dissipation, Watts
JT = package thermal characteristics (no airflow), °C/W
■
Document No. 002-14779 Rev. *H
Page 47 of 51
CYW43362
16. Mechanical Info rmation
Figure 20. 69-Ball WLBGA Mechanical Information
Document No. 002-14779 Rev. *H
Page 48 of 51
CYW43362
17. Ordering Information
Part Number
BCM43362KUBG
Package
Description
69-ball WLBGA halogen-free package
(4.52 mm x 2.92 mm, 0.40 pitch)
Single-band IEEE 802.11b/g/n
2.4 GHz WLAN
Operating
Ambient
Temperature
–30°C to +85°C
Note: Add a “T” to the end of the part number to specify “Tape and Reel”.
18. References
The references in this section may be used in conjunction with this document.
Document (or Item) Name
Number
Source
Cypress Items
CYW43362 reference board schematics
Document No. 002-14779 Rev. *H
–
Cypress Representative
Page 49 of 51
CYW43362
Document History Page
Document Title: CYW43362 Single-Chip IEEE 802.11™ b/g/n MAC/Baseband/Radio
Document Number: 002-14779
Revision
ECN
Orig. of
Change
**
–
–
07/15/2010 43362-DS100-R
Initial release
*A
–
–
02/17/2011 43362-DS101-R
Updated: • LPO clock to LPO sleep clock throughout the document. • Figure3:
“Power Topology,” onpage 15. • “TCXO” on page20. • Table2:“Crystal Oscillator and External Clock Requirements and Performance,” on page21. •
“External 32.768 kHz Low-Power Oscillator” on page22. • Table3:“External
32.768 kHz Low-Power Oscillator Specifications,” on page22. •
Table8:“WLBGA Signal Descriptions,” on page49. • Table9:“BCM43362
During Reset and After Reset or During Sleep,” on page55. •
Table12:“Environmental Ratings,” on page59. • Table13:“ESD Specifications,”
on page59. • Table14:“Recommended Operating Conditions and DC Characteristics,” on page60. • Table16:“WLAN 2.4 GHz Receiver Performance Specifications,” on page62. • Table17:“WLAN 2.4 GHz Transmitter Performance
Specifications,” on page65. • Table18:“General Spurious Emissions Specifications,” on page67. • Table19:“Core Buck Regulator,” on page68. •
Table20:“3.3V LDO (LDO3P3),” on page71. • Table21:“CLDO,” on page72. •
Table22:“LNLDO1,” on page73.
*B
–
–
03/28/2011 43362-DS102-R
Updated: • Table11:“Absolute Maximum Ratings,” on page62. •
Table14:“Recommended Operating Conditions and DC Characteristics,” on
page64. • Table19:“Core Buck Regulator,” on page73. • Table20:“3.3V LDO
(LDO3P3),” on page76.
*C
–
–
09/01/2011 43362-DS103-R
Updated: • Changed maximum battery voltage range from 5.5V to 4.8V. •
“Low-Power Shutdown” on page20. • Table8:“WLBGA Signal Descriptions,”
on page53. • Table13:“ESD Specifications,” on page63. • Table16:“WLAN 2.4
GHz Receiver Performance Specifications,” on page67. • Table17:“WLAN 2.4
GHz Transmitter Performance Specifications,” on page70. • Table18:“General
Spurious Emissions Specifications,” on page72. • Table19:“Core Buck
Regulator,” on page73. • Table20:“3.3V LDO (LDO3P3),” on page76. •
Table23:“System Power Consumption,” on page79.
*D
–
–
02/17/2012 43362-DS104-R
Updated: • Table23:“System Power Consumption,” on page79 Deleted: •
Support for Short GI mode in Tx and Rx
*E
–
–
04/07/2014 43362-DS105-R
Updated: • IEEE 802.15.2 support for Zigbee and BT Smart on page 1. •
Coexistence Interfaces for Zigbee and BT Smart on page 11. Deleted: •
CCXv(2, 3, 4, 5) Proprietary Protocols on page 11.
*F
–
–
02/13/2015 43362-DS106-R
Updated: • Removed “Preliminary” from the document type.
*G
5444083
UTSV
09/30/2016 Migrated to Cypress template format
Added Cypress part numbering scheme
*H
5675324
UTSV
03/30/2017 Updated with Cypress new logo
SPI/gSPI related sections are removed from this document.
Document No. 002-14779 Rev. *H
Submission
Date
Description of Change
Page 50 of 51
CYW43362
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© Cypress Semiconductor Corporation, 2010-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document No. 002-14779 Rev. *H
Revised March 30, 2017
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