CYW4343WKWBGT

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CYW4343W Single-Chip 802.11 b/g/n MAC/Baseband/Radio with Bluetooth 4.1 CYW4343W Single-Chip 802.11 b/g/n MAC/Baseband/Radio with Bluetooth 4.1 The Cypress CYW4343W is a highly integrated single-chip solution and offers the lowest RBOM in the industry for wearables, Internet of Things (IoT) gateways, home automation, and a wide range of other portable devices. The chip includes a 2.4 GHz WLAN IEEE 802.11 b/g/n MAC/baseband/radio and Bluetooth 4.1 support. In addition, it integrates a power amplifier (PA) that meets the output power requirements of most handheld systems, a low-noise amplifier (LNA) for best-in-class receiver sensitivity, and an internal transmit/receive (iTR) RF switch, further reducing the overall solution cost and printed circuit board area. The WLAN host interface supports SPI (gSPI)[1] and SDIO v2.0 modes, providing a raw data transfer rate up to 200 Mbps when operating in 4-bit mode at a 50 MHz bus frequency. An independent, high-speed UART is provided for the Bluetooth host interface. Using advanced design techniques and process technology to reduce active and idle power, the CYW4343W is designed to address the needs of highly mobile devices that require minimal power consumption and compact size. It includes a power management unit that simplifies the system power topology and allows for operation directly from a rechargeable mobile platform battery while maximizing battery life. The CYW4343W implements the world’s most advanced Enhanced Collaborative Coexistence algorithms and hardware mechanisms, allowing for an extremely collaborative WLAN and Bluetooth coexistence. Cypress Part Numbering Scheme Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number. Table 1. Mapping Table for Part Number between Broadcom and Cypress Broadcom Part Number Cypress Part Number BCM4343W CYW4343W BCM4343WKUBG CYW4343WKUBG Features IEEE 802.11x Key Features ■ OneDriver™ software architecture for easy migration from existing embedded WLAN and Bluetooth devices as well as to future devices. ■ Single-band 2.4 GHz IEEE 802.11b/g/n. ■ Support for 2.4 GHz TurboQAM® data rates (256-QAM) and 20 MHz channel bandwidth. ■ Integrated iTR switch supports a single 2.4 GHz antenna shared between WLAN and Bluetooth. ■ Complies with Bluetooth Core Specification Version 4.1 with provisions for supporting future specifications. ■ Supports explicit IEEE 802.11n transmit beamforming ■ Bluetooth Class 1 or Class 2 transmitter operation. ■ Tx and Rx Low-density Parity Check (LDPC) support for improved range and power efficiency. ■ Supports extended Synchronous Connections (eSCO), for enhanced voice quality by allowing for retransmission of dropped packets. ■ Adaptive Frequency Hopping (AFH) for reducing radio frequency interference. ■ Interface support — Host Controller Interface (HCI) using a high-speed UART interface and PCM for audio data. ■ Low-power consumption improves battery life of handheld devices. ■ Supports multiple simultaneous Advanced Audio Distribution Profiles (A2DP) for stereo sound. ■ Automatic frequency detection for standard crystal and TCXO values. ■ Supports standard SDIO v2.0 and gSPI[1] host interfaces. ■ Supports Space-Time Block Coding (STBC) in the receiver. ■ Integrated ARM Cortex-M3 processor and on-chip memory for complete WLAN subsystem functionality, minimizing the need to wake up the applications processor for standard WLAN functions. This allows for further minimization of power consumption, while maintaining the ability to field-upgrade with future features. On-chip memory includes 512 KB SRAM and 640 KB ROM. Bluetooth Features Note 1. SPI availability may depend on module design. Check with the module manufacturer to confirm. Cypress Semiconductor Corporation Document Number: 002-14797 Rev. *J • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 18, 2020 CYW4343W General Features ■ Supports a battery voltage range from 3.0V to 4.8V with an internal switching regulator. ■ Programmable dynamic power management. ■ 4 Kbit One-Time Programmable (OTP) memory for storing board parameters. ■ Can be routed on low-cost 1 x 1 PCB stack-ups. ■ 74-ball[4343W+43CS4343W1]74-ball 63-ball WLBGA package (4.87 mm × 2.87 mm, 0.4 mm pitch). ■ 153-bump WLCSP package (115 μm bump diameter, 180 μm bump pitch). ■ Security: ❐ WPA and WPA2 (Personal) support for powerful encryption and authentication. ❐ AES in WLAN hardware for faster data encryption and IEEE 802.11i compatibility. ❐ Reference WLAN subsystem provides Cisco Compatible Extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0). ❐ Reference WLAN subsystem provides Wi–Fi Protected Setup (WPS). ■ Worldwide regulatory support: Global products supported with worldwide homologated design. Figure 1. CYW4343W System Block Diagram VDDIO VBAT WL_REG_ON WLAN Host I/F WL_IRQ SDIO/SPI 2.4 GHz WLAN + Bluetooth TX/RX CLK_REQ BT_REG_ON PCM Bluetooth Host I/F BPF CYW4343W BT_DEV_WAKE BT_HOST_WAKE UART Document Number: 002-14797 Rev. *J Page 2 of 109 CYW4343W Contents 1. Overview..................................................................... 5 1.1 Overview ............................................................. 5 1.2 Features .............................................................. 6 1.3 Standards Compliance ....................................... 7 2. Power Supplies and Power Management................ 8 2.1 Power Supply Topology ...................................... 8 2.2 CYW4343W PMU Features ................................ 8 2.3 WLAN Power Management .............................. 11 2.4 PMU Sequencing .............................................. 11 2.5 Power-Off Shutdown ......................................... 12 2.6 Power-Up/Power-Down/Reset Circuits ............. 12 3. Frequency References ............................................ 13 3.1 Crystal Interface and Clock Generation ............ 13 3.2 TCXO ................................................................ 13 3.3 External 32.768 kHz Low-Power Oscillator ...... 15 4. WLAN System Interfaces ........................................ 16 4.1 SDIO v2.0 ......................................................... 16 4.2 Generic SPI Mode ............................................ 17 4.3 SPI Protocol ...................................................... 18 4.4 gSPI Host-Device Handshake .......................... 21 5. Wireless LAN MAC and PHY .................................. 24 5.1 MAC Features ................................................... 24 5.2 PHY Description ............................................... 26 6. WLAN Radio Subsystem......................................... 28 6.1 Receive Path .................................................... 29 6.2 Transmit Path ................................................... 29 6.3 Calibration ......................................................... 29 7. Bluetooth Subsystem Overview............................. 30 7.1 Features ............................................................ 30 7.2 Bluetooth Radio ................................................ 31 8. Bluetooth Baseband Core ...................................... 32 8.1 Bluetooth 4.1 Features ..................................... 32 8.2 Link Control Layer ............................................. 32 8.3 Test Mode Support ........................................... 33 8.4 Bluetooth Power Management Unit .................. 33 8.5 BBC Power Management ................................. 35 8.6 Packet Loss Concealment ................................ 35 8.7 Adaptive Frequency Hopping ........................... 36 8.8 Advanced Bluetooth/WLAN Coexistence ......... 36 8.9 Fast Connection (Interlaced Page and Inquiry Scans) ................................................... 36 9. Microprocessor and Memory Unit for Bluetooth.. 37 9.1 RAM, ROM, and Patch Memory ....................... 37 9.2 Reset ................................................................ 37 10. Bluetooth Peripheral Transport Unit ..................... 38 10.1 PCM Interface ................................................... 38 10.2 UART Interface ................................................. 43 10.3 I2S Interface ...................................................... 44 11. CPU and Global Functions ..................................... 47 11.1 WLAN CPU and Memory Subsystem ............... 47 11.2 One-Time Programmable Memory ................... 47 11.3 GPIO Interface .................................................. 47 11.4 External Coexistence Interface ......................... 47 11.5 JTAG Interface ................................................. 49 11.6 UART Interface ................................................ 49 Document Number: 002-14797 Rev. *J 12. WLAN Software Architecture .................................. 50 12.1 Host Software Architecture ................................50 12.2 Device Software Architecture ............................50 12.3 Remote Downloader ..........................................50 12.4 Wireless Configuration Utility .............................50 13. Pinout and Signal Descriptions .............................. 51 13.1 Ball Map .............................................................51 13.2 WLBGA Ball List in Ball Number Order with X-Y Coordinates .................................................53 13.3 WLCSP Bump List in Bump Order with X-Y Coordinates .................................................55 13.4 WLBGA Ball List Ordered By Ball Name ...........60 13.5 WLCSP Bump List Ordered By Name ...............61 13.6 Signal Descriptions ............................................63 13.7 WLAN GPIO Signals and Strapping Options .....71 13.8 Chip Debug Options ..........................................71 13.9 I/O States ...........................................................72 14. DC Characteristics ................................................... 75 14.1 Absolute Maximum Ratings ...............................75 14.2 Environmental Ratings ......................................75 14.3 Electrostatic Discharge Specifications ...............76 14.4 Recommended Operating Conditions and DC Characteristics .............................................76 15. WLAN RF Specifications.......................................... 78 15.1 2.4 GHz Band General RF Specifications .........78 15.2 WLAN 2.4 GHz Receiver Performance Specifications .....................................................79 15.3 WLAN 2.4 GHz Transmitter Performance Specifications .....................................................82 15.4 General Spurious Emissions Specifications ......83 16. Bluetooth RF Specifications.................................... 84 17. Internal Regulator Electrical Specifications .......... 90 17.1 Core Buck Switching Regulator .........................90 17.2 3.3V LDO (LDO3P3) ..........................................91 17.3 CLDO .................................................................92 17.4 LNLDO ...............................................................93 18. System Power Consumption................................... 94 18.1 WLAN Current Consumption .............................94 18.2 Bluetooth Current Consumption ........................95 19. Interface Timing and AC Characteristics ............... 96 19.1 SDIO Default Mode Timing ................................96 19.2 SDIO High-Speed Mode Timing ........................97 19.3 JTAG Timing ......................................................98 20. Power-Up Sequence and Timing............................. 99 20.1 Sequencing of Reset and Regulator Control Signals ..................................99 21. Package Information .............................................. 102 21.1 Package Thermal Characteristics ....................102 22. Mechanical Information ......................................... 103 23. Ordering Information.............................................. 107 24. Additional Information ........................................... 107 24.1 Acronyms and Abbreviations ...........................107 24.2 IoT Resources .................................................107 Document History Page ............................................... 108 Sales, Solutions, and Legal Information .................... 109 Page 3 of 109 CYW4343W Worldwide Sales and Design Support ..................... 109 Products .................................................................. 109 PSoC® Solutions ..................................................... 109 Document Number: 002-14797 Rev. *J Cypress Developer Community ............................... 109 Technical Support ................................................... 109 Page 4 of 109 CYW4343W 1. Overview 1.1 Overview The CYW4343W provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE 802.11 b/g/n. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. The CYW4343W is designed to address the needs of highly mobile devices that require minimal power consumption and reliable operation. Figure 2 shows the interconnection of all the major physical blocks in the CYW4343W and their associated external interfaces, which are described in greater detail in subsequent sections. SDP ETM Co rte x M 3 JTAG* Figure 2. CYW4343W Block Diagram D ebug AHB AHB Bus Matrix B u ffe r APU DM A G P IO Ctrl B u s A rb A R M IP JT A G s u p p o r t e d o v e r S D IO o r B T P C M S D IO / g S P I gSPI ARM CM 3 O TP W ake/ a x CC to re lx SWleiM ep W iM a x Co e x. B T -W L A N ECI B T C lo c k C o n t r o l S le e p t im e K e e p in g LP O C lo c k M anage m ent PM U Ctrl PM U XO B u ffe r 2.4 G H z PA S h a red LN A BPF POR W LAN BT_REG_ON VREGs VBAT PTU XTAL JT A G * MAC IF PLL G P IO UART S u p p o rt e d o v e r S D IO o r B T P C M UART IEEE 802.11a/b/g/n ROM BT PHY G P IO G P IO Backplane I/O Port Control I S/PCM RAM Pow er S u p p ly S le e p C L K XTAL W L_ R EG _ O N W DT 2 LNPPHY B u ffe r SW R EG LD O x2 LP O X TA L O SC. PO R PM U Co ntro l S D IO JTAG* R X/TX Radio Digital Common and D ig it a l M od. LCU D ig it a l I/ O S W T im e r PA B lu e R F In t e r fa c e D ebug UART In t e r C t rl D ig it a l D em od. & B it Sync B T C lo c k / Hopper P atch W D T im e r RF Radio M odem RAM ROM APB 2.4 GHz BPL UART AH B to A PB B r id g e * V ia G P I O c o n f ig u r a t io n , J T A G is s u p p o r t e d o v e r S D I O o r B T P C M Document Number: 002-14797 Rev. *J Page 5 of 109 CYW4343W 1.2 Features The CYW4343W supports the following WLAN and Bluetooth features: ■ IEEE 802.11b/g/n single-band radio with an internal power amplifier, LNA, and T/R switch ■ Bluetooth v4.1 with integrated Class 1 PA ■ Concurrent Bluetooth, and WLAN operation ■ On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality ■ Simultaneous BT/WLAN reception with a single antenna ■ WLAN host interface options: ❐ SDIO v2.0, including default and high-speed timing. ■ BT UART (up to 4 Mbps) host digital interface that can be used concurrently with the above WLAN host interfaces. ■ ECI—enhanced coexistence support, which coordinates BT SCO transmissions around WLAN receptions. ■ I2S/PCM for BT audio ■ HCI high-speed UART (H4 and H5) transport support ■ Wideband speech support (16 bits, 16 kHz sampling PCM, through I2S and PCM interfaces) ■ Bluetooth SmartAudio® technology improves voice and music quality to headsets. ■ Bluetooth low power inquiry and page scan ■ Bluetooth Low Energy (BLE) support ■ Bluetooth Packet Loss Concealment (PLC) Document Number: 002-14797 Rev. *J Page 6 of 109 CYW4343W 1.3 Standards Compliance The CYW4343W supports the following standards: ■ Bluetooth 2.1 + EDR ■ Bluetooth 3.0 ■ Bluetooth 4.1 (Bluetooth Low Energy) ■ IEEE 802.11n—Handheld Device Class (Section 11) ■ IEEE 802.11b ■ IEEE 802.11g ■ IEEE 802.11d ■ IEEE 802.11h ■ IEEE 802.11i The CYW4343W will support the following future drafts/standards: ■ IEEE 802.11r — Fast Roaming (between APs) ■ IEEE 802.11k — Resource Management ■ IEEE 802.11w — Secure Management Frames ■ IEEE 802.11 Extensions: ■ IEEE 802.11e QoS Enhancements (as per the WMM® specification is already supported) ■ IEEE 802.11i MAC Enhancements ■ IEEE 802.11r Fast Roaming Support ■ IEEE 802.11k Radio Resource Measurement The CYW4343W supports the following security features and proprietary protocols: ■ Security: ❐ WEP ™ ❐ WPA Personal ™ ❐ WPA2 Personal ❐ WMM ❐ WMM-PS (U-APSD) ❐ WMM-SA ❐ WAPI ❐ AES (Hardware Accelerator) ❐ TKIP (host-computed) ❐ CKIP (SW Support) ■ Proprietary Protocols: ❐ CCXv2 ❐ CCXv3 ❐ CCXv4 ❐ CCXv5 ■ IEEE 802.15.2 Coexistence Compliance — on silicon solution compliant with IEEE 3-wire requirements. Document Number: 002-14797 Rev. *J Page 7 of 109 CYW4343W 2. Power Supplies and Power Management 2.1 Power Supply Topology One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW4343W. All regulators are programmable via the PMU. These blocks simplify power supply design for Bluetooth and WLAN functions in embedded designs. A single VBAT (3.0V to 4.8V DC maximum) and VDDIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in the CYW4343W. Two control signals, BT_REG_ON and WL_REG_ON, are used to power up the regulators and take the respective circuit blocks out of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO can be turned on and off based on the dynamic demands of the digital baseband. The CYW4343W allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO regulators. When in this state, LPLDO1 provides the CYW4343W with all required voltage, further reducing leakage currents. Note: VBAT should be connected to the LDO_VDDBAT5V and SR_VDDBAT5V pins of the device. Note: VDDIO should be connected to the SYS_VDDIO and WCC_VDDIO pins of the device. 2.2 CYW4343W PMU Features The PMU supports the following: ■ VBAT to 1.35Vout (170 mA nominal, 370 mA maximum) Core-Buck (CBUCK) switching regulator ■ VBAT to 3.3Vout (250 mA nominal, 450 mA maximum 800 mA peak maximum) LDO3P3 ■ 1.35V to 1.2Vout (100 mA nominal, 150 mA maximum) LNLDO ■ 1.35V to 1.2Vout (80 mA nominal, 200 mA maximum) CLDO with bypass mode for deep sleep ■ Additional internal LDOs (not externally accessible) ■ PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode. ■ PMU input supplies automatic sensing and fast switching to support A4WP operations. Figure 3 and Figure 4 show the typical power topology of the CYW4343W. Document Number: 002-14797 Rev. *J Page 8 of 109 CYW4343W Figure 3. Typical Power Topology (1 of 2) SR _ V D D B A T 5V VBAT CYW4343W W L R F — T X M ixer an d P A (n o t all v ersio n s) M ini P M U 1 .2V VBAT: O p e ratio n al: 3 .0 — 4 .8 V Pe rfo rm an ce : 3 .0 — 4 .8 V A b so lu te M axim u m : 5 .5 V V D D IO O p e ratio n al: 1 .8 — 3 .3 V V D D 1 P35 In te rna l V C O LD O 8 0 m A (N M O S) 1 .2 V W L R F— LO G EN In te rn a l R X LD O 1 0 m A (N M O S) 1 .2 V W L R F— R X LN A In te rna l A D C LD O 1 0 m A (N M O S) 1 .2 V W L R F— A D C R E F In te rn a l TX LD O 8 0 m A (P M O S) 1 .2 V W L R F— TX In te rna l A F E LD O 8 0 m A (N M O S) 1 .2 V 1 .35 V In t_ S R _ V B A T (32 0 m A ) SW 1 VBAT C o re B u ck R e gu la to r P e a k: 3 70 m A A vg: 1 70 m A SR _ V LX GND W C C _ V D D IO M in i P M U is p la ce d in W L ra d io 2 .2 u H 0 60 3 LD O _V D D _ 1P 5 SR _ V B A T 5V SR_PVSS 4.7 uF 04 02 LN LD O (1 00 m A ) 1 .2 V 2 .2 uF 04 02 LP LD O 1 (5 m A ) (40 m A ) 600 @ 10 0 M H z V O U T _LN LD O PM U_VSS W C C _ V D D IO W L R F— A F E a n d T IA W LR F _ X TA L_ VD D1P2 W L R F— X T A L 0.1 uF 02 01 1.1 V W LA N /B T/C LB/ To p, A lw a ys O n SY S_ V D D IO S YS_ V D D IO W P T _ 1P 8 (40 m A ) V S EL1 VD DC1 (40 m A ) W PT_1P8 o _ w pt_ re se tb W L_ R EG _ O N B T _ R EG _ O N 10 m A a ve ra ge, > 10 m A a t sta rt-u p W L R F— R F P LL P F D a nd M M D W P T LD O (4 0 m A ) 1 .3 V C L LD O P e a k: 2 00 m A A vg: 8 0 m A (B ypa ss in de e p sle e p ) 1 .3V , 1.2V , o r 0.95V (A V S ) V O U T _ C LD O W L O TP VD DC2 2 .2 uF 04 02 o _ w l_ re s e tb o _ b t_ re se tb Su p p ly b all W L D igita l a n d P H Y W L V D D M (S R O M s & A O S) S u p p ly b u m p /p ad Po w e r sw itch BT VDDM G ro u n d b all G ro u n d b u m p /p ad N o p o w e r sw itch B T /W L A N re se t b alls Exte rn al to ch ip N o d e d icate d p o w e r sw itch , b u t in te rn al p o w e rd o w n m o d e s an d b lo ck -sp e cific p o w e r sw itch e s Document Number: 002-14797 Rev. *J B T D igita l Page 9 of 109 CYW4343W Figure 4. Typical Power Topology (2 of 2) CYW4343W 6.4 mA 1.8V, 2.5V, and 3.3V VBAT LDO_ VDDBAT5V WL BBPLL/DFLL WL OTP 3.3V LDO3P3 with Back-Power VOUT_3P3 Protection 4.7 uF (Peak 450-800 mA 200 mA Average) 3.3V 0402 WPT_3P3 SW2 Peak: 92 mA Average: 75 mA Resistance: 1 ohm 480 to 800 mA WLRF_PA_VDD WL RF—PA (2.4 GHz) 1 uF 0201 2.5V Cap-less LNLDO (10 mA) 22 ohm 6.4 mA WL RF—ADC, AFE, LOGEN, LNA, NMOS Mini-PMU LDOs Placed inside WL Radio BT_PAVDD Peak: 70 mA Average: 15 mA BT Class 1 PA 1 uF 0201 Power switch External to chip No power switch Supply ball No dedicated power switch, but internal powerdown modes and block-specific power switches Document Number: 002-14797 Rev. *J Page 10 of 109 CYW4343W 2.3 WLAN Power Management The CYW4343W has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the CYW4343W integrated RAM is a high volatile memory with dynamic clock control. The dominant supply current consumed by the RAM is leakage current only. Additionally, the CYW4343W includes an advanced WLAN power management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW4343W into various power management states appropriate to the operating environment and the activities that are being performed. The power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power-up sequences are fully programmable. Configurable, free-running counters (running at the 32.768 kHz LPO clock) in the PMU sequencer are used to turn on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock speeds are used wherever possible. The CYW4343W WLAN power states are described as follows: ■ Active mode— All WLAN blocks in the CYW4343W are powered up and fully functional with active carrier sensing and frame transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer. ■ Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW4343W remains powered up in an IDLE state. All main clocks (PLL, crystal oscillator) are shut down to reduce active power to the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current. ■ Deep-sleep mode—Most of the chip, including analog and digital domains, and most of the regulators are powered off. Logic states in the digital core are saved and preserved to retention memory in the always-on domain before the digital core is powered off. To avoid lengthy hardware reinitialization, the logic states in the digital core are restored to their pre-deep-sleep settings when a wakeup event is triggered by an external interrupt, a host resume through the SDIO bus, or by the PMU timers. ■ Power-down mode—The CYW4343W is effectively powered off by shutting down all internal regulators. The chip is brought out of this mode by external logic re-enabling the internal regulators. 2.4 PMU Sequencing The PMU sequencer is used to minimize system power consumption. It enables and disables various system resources based on a computation of required resources and a table that describes the relationship between resources and the time required to enable and disable them. Resource requests can derive from several sources: clock requests from cores, the minimum resources defined in the ResourceMin register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of resources required to produce the requested clocks. Each resource is in one of the following four states: ■ enabled ■ disabled ■ transition_on ■ transition_off The timer value is 0 when the resource is enabled or disabled and nonzero during state transition. The timer is loaded with the time_on or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. During each clock cycle, the PMU sequencer performs the following actions: ■ Computes the required resource set based on requests and the resource dependency table. ■ Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource and inverts the ResourceState bit. ■ Compares the request with the current resource status and determines which resources must be enabled or disabled. ■ Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents. ■ Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled. Document Number: 002-14797 Rev. *J Page 11 of 109 CYW4343W 2.5 Power-Off Shutdown The CYW4343W provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices in the system, remain operational. When the CYW4343W is not needed in the system, VDDIO_RF and VDDC are shut down while VDDIO remains powered. This allows the CYW4343W to be effectively off while keeping the I/O pins powered so that they do not draw extra current from any other devices connected to the I/O. During a low-power shutdown state, provided VDDIO remains applied to the CYW4343W, all outputs are tristated, and most input signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system, and enables the CYW4343W to be fully integrated in an embedded device and to take full advantage of the lowest power-savings modes. When the CYW4343W is powered on from this state, it is the same as a normal power-up, and the device does not retain any information about its state from before it was powered down. 2.6 Power-Up/Power-Down/Reset Circuits The CYW4343W has two signals (see Table 2) that enable or disable the Bluetooth and WLAN circuits and the internal regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see Power-Up Sequence and Timing. Table 2. Power-Up/Power-Down/Reset Control Signals Signal Description WL_REG_ON This signal is used by the PMU (with BT_REG_ON) to power-up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the internal CYW4343W regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming. BT_REG_ON This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal CYW4343W regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has an internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming. Document Number: 002-14797 Rev. *J Page 12 of 109 CYW4343W 3. Frequency References An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. No software settings are required to differentiate between the two. In addition, a low-power oscillator (LPO) is provided for lower power mode timing. 3.1 Crystal Interface and Clock Generation The CYW4343W can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator, including all external components, is shown in Figure 5. Consult the reference schematics for the latest configuration. Figure 5. Recommended Oscillator Configuration C WLRF_XTAL_XOP 12 – 27 pF C WLRF_XTAL_XON 12 – 27 pF R Note: Resistor value determined by crystal drive level. See reference schematics for details. The CYW4343W uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing so that it can operate using numerous frequency references. The frequency reference can be an external source such as a TCXO or a crystal interfaced directly to the CYW4343W. The default frequency reference setting is a 37.4 MHz crystal or TCXO. The signal requirements and characteristics for the crystal interface are shown in Table 3. Note: Although the fractional-N synthesizer can support many reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. Contact Cypress for further details. 3.2 TCXO As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the phase noise requirements listed in Table 3. If the TCXO is dedicated to driving the CYW4343W, it should be connected to the WLRF_XTAL_XOP pin through an external capacitor with value ranges from 200 pF to 1000 pF as shown in Figure 6. Figure 6. Recommended Circuit to Use with an External Dedicated TCXO 200 pF – 1000 pF TCXO WLRF_XTAL_XOP NC Document Number: 002-14797 Rev. *J WLRF_XTAL_XON Page 13 of 109 CYW4343W Table 3. Crystal Oscillator and External Clock Requirements and Performance Parameter External Frequency Reference Crystal Conditions/Notes Min. Typ. a Max. Min. Typ. Max. Units – – – – MHz Frequency – – 37.4 Crystal load capacitance – – 12 – – – – pF ESR – – – 60 – – – Ω Drive level External crystal must be able to tolerate this drive level. 200 – – – – – μW Resistive – – – 10k 100k – Ω Capacitive – – – – – 7 pF – 1260 mVp-p Input Impedance (WLRF_XTAL_XOP) WLRF_XTAL_XOP input voltage b – – – 400 WLRF_XTAL_XOP input low DC-coupled digital signal level – – – 0 – 0.2 V WLRF_XTAL_XOP input high DC-coupled digital signal level – – – 1.0 – 1.26 V –20 – 20 –20 – 20 ppm – – – 40 50 60 % AC-coupled analog signal Frequency tolerance Initial + over temperature – Duty cycle 37.4 MHz clock Phase Noise (IEEE 802.11 b/g) 37.4 MHz clock at 10 kHz offset – – – – – –129 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –136 dBc/Hz Phase Noisec, d, e (IEEE 802.11n, 2.4 GHz) 37.4 MHz clock at 10 kHz offset – – – – – –134 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –141 dBc/Hz c, d, e c, d, e Phase Noise (256-QAM) 37.4 MHz clock at 10 kHz offset – – – – – –140 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –147 dBc/Hz a. The frequency step size is approximately 80 Hz. The CYW4343W does not auto-detect the reference clock frequency; the frequency is specified in the software and/or NVRAM file. b. To use 256-QAM, a 800 mV minimum voltage is required. c. For a clock reference other than 37.4 MHz, 20 × log10(f/37.4) dB should be added to the limits, where f = the reference clock frequency in MHz. d. Phase noise is assumed flat above 100 kHz. e. The CYW4343W supports a 26 MHz reference clock sharing option. See the phase noise requirement in the table. Document Number: 002-14797 Rev. *J Page 14 of 109 CYW4343W 3.3 External 32.768 kHz Low-Power Oscillator The CYW4343W uses a secondary low-frequency sleep clock for low-power mode timing. Either the internal low-precision LPO or an external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process, voltage, and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons. Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in Table 4. Note: The CYW4343W will auto-detect the LPO clock. If it senses a clock on the EXT_SLEEP_CLK pin, it will use that clock. If it doesn't sense a clock, it will use its own internal LPO. ■ To use the internal LPO: Tie EXT_SLEEP_CLK to ground. Do not leave this pin floating. ■ To use an external LPO: Connect the external 32.768 kHz clock to EXT_SLEEP_CLK. Table 4. External 32.768 kHz Sleep-Clock Specifications Parameter Nominal input frequency Frequency accuracy Duty cycle Input signal amplitude Signal type Input impedancea Clock jitter LPO Clock Units 32.768 kHz ±200 ppm 30–70 % 200–3300 mV, p-p Square wave or sine wave – >100 kΩ