CYW4356XKWBGT

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CYW4356/CG8674 ADVANCE Single-Chip 5G WiFi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 5.0 The Cypress CYW4356 is a complete dual-band (2.4 GHz and 5 GHz) 5G WiFi 2 × 2 MIMO MAC/PHY/Radio System-on-a-Chip. This Wi-Fi single-chip device provides a high level of integration with dual-stream IEEE 802.11ac MAC/baseband/radio, Bluetooth 5.0. Additionally, it supports wireless charging. In IEEE 802.11ac mode, the WLAN operation supports rates of MCS0–MCS9 (up to 256 QAM) in 20 MHz, 40 MHz, and 80 MHz channels for data rates up to 867 Mbps. In addition, all the rates specified in IEEE 802.11a/ b/g/n are supported. Included on-chip are 2.4 GHz and 5 GHz transmit power amplifiers and receive low noise amplifiers. For the WLAN section, several alternative host interface options are included: an SDIO v3.0 interface that can operate in 4b or 1b modes, and a PCIe v3.0 compliant interface running at Gen1 speeds. For the Bluetooth section, host interface options of a high-speed 4-wire UART and USB 2.0 full-speed (12 Mbps) are provided. The CYW4356 uses advanced design techniques and process technology to reduce active and idle power, and includes an embedded power management unit that simplifies the system power topology. In addition, the CYW4356 implements highly sophisticated enhanced collaborative coexistence hardware mechanisms and algorithms that ensure that WLAN and Bluetooth collaboration is optimized for maximum performance. Coexistence support for external radios (such as LTE cellular and GPS) is provided via an external interface. As a result, enhanced overall quality for simultaneous voice, video, and data transmission on a handheld system is achieved. This data sheet provides details on the functional, operational, and electrical characteristics for the Cypress CYW4356. It is intended for hardware design, application, and OEM engineers. Cypress Part Numbering Scheme Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number. Table 1. Mapping Table for Part Number between Broadcom and Cypress Broadcom Part Number Cypress Part Number BCM4356 CYW4356 BCM4330 CYW4330 BCM4356XKWBG CYW4356XKWBG CG8674AAT (BCM4356XKUBGT) CG8674BAT (CYW4356XKUBGT) CG8674AA (BCM4356XKUBG) CG8674BA (CYW4356XKUBG) Figure 1. Functional Block Diagram ‘ VIO VBAT WL_REG_ON WLAN  Host I/F PCIe SDIO 5G WLAN T/R Switch Ant1 Diplexer External  Coexistence I/F COEX 2G WLAN T/R Switch 5G WLAN T/R Switch CLK_REQ BT_REG_ON CYW4356 USB 2.0 I2S Bluetooth Host I/F  PCM Ant0 Diplexer UART 2G WLAN Tx 2.G WL/BT Rx 3PST Switch BT_DEV_WAKE BT_HOST_WAKE Cypress Semiconductor Corporation Document Number: 002-20538 Rev. *B • 198 Champion Court BT Tx • San Jose, CA 95134-1709 • 408-943-2600 Revised Friday, July 27, 2018 ADVANCE CYW4356/CG8674 Features IEEE 802.11X Key Features ■ Internal fractional nPLL allows support for a wide range of reference clock frequencies. ■ Supports IEEE 802.15.2 external coexistence interface to optimize bandwidth utilization with other co-located wireless technologies such as LTE or GPS. ■ IEEE 802.11ac Draft compliant. ■ Dual-stream spatial multiplexing up to 867 Mbps data rate. ■ Supports 20, 40, and 80 MHz channels with optional SGI (256 QAM modulation). ■ Supports standard SDIO v3.0 (up to SDR104 mode at 208 MHz, 4-bit and 1-bit) host interfaces. ■ Full IEEE 802.11a/b/g/n legacy compatibility with enhanced performance. ■ Backward compatible with SDIO v2.0 host interfaces. ■ TX and RX low-density parity check (LDPC) support for improved range and power efficiency. ■ PCIe mode complies with PCI Express base specification revision 3.0 for ×1 lane and power management running at Gen1 speeds. ■ Supports IEEE 802.11ac/n beamforming. ■ Supports Active State Power Management (ASPM). ■ On-chip power amplifiers and low-noise amplifiers for both bands. ■ ■ Supports various RF front-end architectures including: ❐ Two antennas with one each dedicated to Bluetooth and WLAN. ❐ Two antennas with WLAN diversity and a shared Bluetooth antenna. Integrated ARMCR4 processor with tightly coupled memory for complete WLAN subsystem functionality, minimizing the need to wake up the applications processor for standard WLAN functions. This allows for further minimization of power consumption, while maintaining the ability to field upgrade with future features. On-chip memory includes 768 KB SRAM and 640 KB ROM. ■ Shared Bluetooth and WLAN receive signal path eliminates the need for an external power splitter while maintaining excellent sensitivity for both Bluetooth and WLAN. ■ OneDriver™ software architecture for easy migration from existing embedded WLAN and Bluetooth devices as well as future devices. ■ Supports A4WP wireless charging with the BCM59350. ■ Interface support, host controller interface (HCI) using a USB or high-speed UART interface and PCM for audio data. ■ USB 2.0 full-speed (12 Mbps) supported for Bluetooth. ■ Low power consumption improves battery life of handheld devices. ■ Supports multiple simultaneous Advanced Audio Distribution Profiles (A2DP) for stereo sound. ■ Automatic frequency detection for standard crystal and TCXO values. ■ Security: ❐ WPA and WPA2 (Personal) support for powerful encryption and authentication ❐ AES and TKIP in hardware for faster data encryption and IEEE 802.11i compatibility ❐ Reference WLAN subsystem provides Cisco Compatible Extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0) ❐ Reference WLAN subsystem provides Wi-Fi Protected Setup (WPS) ■ Worldwide regulatory support: Global products supported with worldwide homologated design. Bluetooth Key Features ■ Qualified for Bluetooth Core Specification 5.0: ❐ QDID: 115131 ❐ Declaration ID: D038396 ■ Supports Basic Rate (BR), Enhanced Data Rate (EDR) and Bluetooth Low Energy (BLE) ■ Bluetooth Class 1 or Class 2 transmitter operation. ■ Supports extended synchronous connections (eSCO), for enhanced voice quality by allowing for retransmission of dropped packets. ■ Adaptive frequency hopping (AFH) for reducing radio frequency interference. General Features ■ Supports battery range from 3.0V to 5.25V supplies with internal switching regulator ■ Programmable dynamic power management ■ 484 bytes of user-accessible OTP for storing board parameters ■ GPIOs: 11 in WLBGA, 16 in WLCSP ■ Package options: ❐ 192-ball WLBGA (4.87 mm × 7.67 mm, 0.4 mm pitch ❐ 395-bump WLCSP (4.87 mm × 7.67 mm, 0.2 mm pitch) Document Number: 002-20538 Rev. *B Page 2 of 144 ADVANCE CYW4356/CG8674 Contents 1. Overview ........................................................................ 5 1.1 Overview ............................................................... 5 1.2 Features ................................................................ 7 1.3 Standards Compliance .......................................... 8 2. Power Supplies and Power Management ................... 9 2.1 Power Supply Topology ........................................ 9 2.2 CYW4356/CG8674 PMU Features ....................... 9 2.3 WLAN Power Management ................................. 11 2.4 PMU Sequencing ................................................ 11 2.5 Power-Off Shutdown ........................................... 12 2.6 Power-Up/Power-Down/Reset Circuits ............... 12 2.7 Wireless Charging ............................................... 12 3. Frequency References ............................................... 15 3.1 Crystal Interface and Clock Generation .............. 15 3.2 External Frequency Reference ............................ 15 3.3 External 32.768 kHz Low-Power Oscillator ......... 17 4. Bluetooth Subsystem Overview ................................ 18 4.1 Features .............................................................. 18 4.2 Bluetooth Radio ................................................... 19 5. Bluetooth Baseband Core ......................................... 20 5.1 Bluetooth 4.1 Features ........................................ 20 5.2 Bluetooth 5.0/4.2 ................................................. 20 5.3 Link Control Layer ............................................... 21 5.4 Test Mode Support .............................................. 21 5.5 Bluetooth Power Management Unit ..................... 22 5.6 Adaptive Frequency Hopping .............................. 25 5.7 Advanced Bluetooth/WLAN Coexistence ............ 25 5.8 Fast Connection (Interlaced Page and Inquiry Scans) 25 6. Microprocessor and Memory Unit for Bluetooth ..... 26 6.1 RAM, ROM, and Patch Memory .......................... 26 6.2 Reset ................................................................... 26 7. Bluetooth Peripheral Transport Unit ........................ 27 7.1 SPI Interface ........................................................ 27 7.2 SPI/UART Transport Detection ........................... 27 7.3 PCM Interface ..................................................... 27 7.4 USB Interface ...................................................... 34 7.5 UART Interface .................................................... 36 7.6 I2S Interface ........................................................ 37 7.7 External Coexistence Interface ........................... 40 7.8 UART Interface .................................................... 41 7.9 JTAG Interface .................................................... 41 7.10 SPROM Interface .............................................. 41 8. WLAN Host Interfaces ................................................ 42 8.1 SDIO v3.0 ............................................................ 42 8.2 PCI Express Interface ......................................... 44 9. Wireless LAN MAC and PHY ..................................... 46 9.1 IEEE 802.11ac Draft MAC ................................... 46 9.2 IEEE 802.11ac Draft PHY ................................... 48 10. WLAN Radio Subsystem ......................................... 50 10.1 Receiver Path .................................................... 52 10.2 Transmit Path .................................................... 52 10.3 Calibration ......................................................... 52 11. Pin Information ......................................................... 53 Document Number: 002-20538 Rev. *B 11.1 Ball Maps ........................................................... 53 11.2 Pin Lists ............................................................. 54 11.3 Signal Descriptions ............................................ 70 11.4 WLAN/BT GPIO Signals and Strapping Options 84 11.5 GPIO Alternative Signal Functions .................... 85 11.6 I/O States .......................................................... 87 12. DC Characteristics ................................................... 90 12.1 Absolute Maximum Ratings ............................... 90 12.2 Environmental Ratings ...................................... 90 12.3 Electrostatic Discharge Specifications .............. 90 12.4 Recommended Operating Conditions and DC Characteristics ................................................... 91 13. Bluetooth RF Specifications .................................... 92 14. WLAN RF Specifications .......................................... 98 14.1 Introduction ........................................................ 98 14.2 2.4 GHz Band General RF Specifications ......... 98 14.3 WLAN 2.4 GHz Receiver Performance Specifications ..................................................... 99 14.4 WLAN 2.4 GHz Transmitter Performance Specifications .................................................. 104 14.5 WLAN 5 GHz Receiver Performance Specifications ................................................... 106 14.6 WLAN 5 GHz Transmitter Performance Specifications ................................................... 112 15. Internal Regulator Electrical Specifications ........ 113 15.1 Core Buck Switching Regulator ....................... 113 15.2 3.3V LDO (LDO3P3) ....................................... 114 15.3 3.3V LDO (LDO3P3_B) ................................... 115 15.4 2.5V LDO (BTLDO2P5) ................................... 116 15.5 CLDO .............................................................. 117 15.6 LNLDO ............................................................ 118 16. System Power Consumption ................................. 119 16.1 WLAN Current Consumption ........................... 119 16.2 Bluetooth Current Consumption ...................... 121 17. Interface Timing and AC Characteristics ............. 122 17.1 SDIO Timing .................................................... 122 17.2 PCI Express Interface Parameters .................. 130 17.3 JTAG Timing ................................................... 131 18. Power-Up Sequence and Timing ........................... 132 18.1 Sequencing of Reset and Regulator Control Signals ............................................................. 132 19. Package Information .............................................. 137 19.1 Package Thermal Characteristics ................... 137 19.2 Junction Temperature Estimation and PSIJT Versus ThetaJC ..............................................................137 19.3 Environmental Characteristics ......................... 137 20. Mechanical Information ......................................... 138 21. Ordering Information .............................................. 142 22. Additional Information ........................................... 142 22.1 Acronyms and Abbreviations ........................... 142 22.2 References ...................................................... 142 23. IoT Resources ......................................................... 142 Document History ........................................................ 143 Sales, Solutions, and Legal Information ................... 144 Page 3 of 144 ADVANCE CYW4356/CG8674 1. Overview 1.1 Overview The Cypress CYW4356/CG8674 single-chip device provides the highest level of integration for an IoT or Embedded system, with integrated IEEE 802.11 a/b/g/n/ac MAC/baseband/radio, Bluetooth 5.0 and Alliance for Wireless Power (A4WP) support. The wireless charging feature works in collaboration with the Wireless Power Transfer (WPT) BCM59350 front-end IC. It provides a small formfactor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. Comprehensive power management circuitry and software ensure the system can meet the needs of highly mobile devices that require minimal power consumption and reliable operation. Figure 2 shows the interconnect of all the major physical blocks in the CYW4356/CG8674 and their associated external interfaces, which are described in greater detail in the following sections. Table 2. Device Options and Features Feature WLBGA WLCSP Package ball count 192 pins 395 bumps PCIe Yes Yes USB2.0 (Bluetooth) Yes Yes I2S Multiplexed onto six parallel Flash pins No GPIO 11 16 SDIO 3.0 Yes Yes WPT (BSC, GPIO) Yes Yes SPROM Yes Yes Document Number: 002-20538 Rev. *B Page 5 of 144 ADVANCE CYW4356/CG8674 Figure 2. CYW4356/CG8674 Block Diagram CYW4356 JTAG WLAN BT XTAL OSC RAM ROM APB Patch WD Timer Inter Ctrl SW Timer DMA OTP Bus Arb GPIO AHB SLIMBus RAM Debug UART ROM BT RF BT PHY CLB I2S/PCM1 802.11abgn SMPS Control GNSS LNA ANT  Control BT Control Clock Sleep Clock  PMU Timer Management Wake/Sleep Control LPO PMU  Controller XO  Buffer BT‐WLAN ECI POR UART JTAG JTAG I2S/PCM2 GPIO GPIO UART 2X2 LCNXNPHY BT Digital IO IO Port Control MEIF OTP ARM AXI BACKPLANE GPIO Ctrl XTAL POR AHB2 APB  Bridge JTAG AHB Bus Matrix PTU UART/USB Power Supply LDO LPO AHB Power SW REG Radio CORE0 CORE1 2.4 GHz 5 GHz 2.4 GHz 5 GHz WPT PMU Controller SDIO ETM JTAG SDP Cortex M3 BSC, GPIO *SDIO or *PCIe 2.0  PCIe Debug 5 GHz IPA BPF LNA 2.4 GHz IPA Diplexer BPF LNA 5 GHz IPA BPF LNA 2.4 GHz IPA Diplexer BPF Shared LNA BT RX BT TX XTAL Document Number: 002-20538 Rev. *B VBAT VREG POR EXT LNA RF Switch Control Page 6 of 146 ADVANCE CYW4356/CG8674 1.2 Features The CYW4356/CG8674 supports the following features: ■ IEEE 802.11a/b/g/n/ac dual-band 2x2 MIMO radio with virtual-simultaneous dual-band operation ■ Bluetooth 5.0 with integrated Class 1 PA ■ Concurrent Bluetooth, and WLAN operation ■ On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality ■ Single- and dual-antenna support ❐ Single antenna with shared LNA ❐ Simultaneous BT/WLAN receive with single antenna ■ WLAN host interface options: ❐ SDIO v3.0 (1 bit/4 bit)—up to 208 MHz clock rate in SDR104 mode ❐ PCIe v3.0 for x1 lane and power management, running at Gen 1 speeds ■ BT host digital interface (can be used concurrently with above interfaces): ❐ UART (up to 4 Mbps) ■ BT supports full-speed USB 2.0-compliant interface ■ ECI—enhanced coexistence support, ability to coordinate BT SCO transmissions around WLAN receives ■ I2S/PCM for BT audio ■ HCI high-speed UART (H4, H4+, H5) transport support ■ Wideband speech support (16 bits linear data, MSB first, left justified at 4K samples/s for transparent air coding, both through I2S and PCM interface) ■ Bluetooth SmartAudio® technology improves voice and music quality to headsets ■ Bluetooth low power inquiry and page scan ■ Bluetooth Low Energy (BLE) support ■ Bluetooth Packet Loss Concealment (PLC) ■ Bluetooth Wideband Speech (WBS) ■ Audio rate-matching algorithms ■ Multiple simultaneous A2DP audio stream ■ A4WP support Document Number: 002-20538 Rev. *B Page 7 of 144 ADVANCE CYW4356/CG8674 1.3 Standards Compliance The CYW4356/CG8674 supports the following standards: ■ Bluetooth 5.0 with Basic Rate (BR), Enhanced Data Rate (EDR) and Bluetooth Low Energy (BLE) ■ IEEE802.11ac mandatory and optional requirements for 20 MHz, 40 MHz, and 80 MHz channels ■ IEEE 802.11n—Handheld Device Class (Section 11) ■ IEEE 802.11a ■ IEEE 802.11b ■ IEEE 802.11g ■ IEEE 802.11d ■ IEEE 802.11h ■ IEEE 802.11i ■ Security: ❐ WEP ❐ WPA Personal ❐ WPA2 Personal ❐ WMM ❐ WMM-PS (U-APSD) ❐ WMM-SA ❐ AES (Hardware Accelerator) ❐ TKIP (HW Accelerator) ❐ CKIP (SW Support) ■ Proprietary Protocols: ❐ CCXv2 ❐ CCXv3 ❐ CCXv4 ❐ CCXv5 ■ IEEE 802.15.2 Coexistence Compliance—on silicon solution compliant with IEEE 3 wire requirements The CYW4356/CG8674 will support the following future drafts/standards: ■ IEEE 802.11w—Secure Management Frames ■ A4WP Wireless Power Transfer System Baseline System Specification V1.0 ■ IEEE 802.11 Extensions: ❐ IEEE 802.11e QoS Enhancements (In accordance with the WMM specification, QoS is already supported.) ❐ IEEE 802.11h 5 GHz Extensions ❐ IEEE 802.11i MAC Enhancements ❐ IEEE 802.11k Radio Resource Measurement Document Number: 002-20538 Rev. *B Page 8 of 144 ADVANCE CYW4356/CG8674 2. Power Supplies and Power Management 2.1 Power Supply Topology One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW4356/CG8674. All regulators are programmable via the PMU. These blocks simplify power supply design for Bluetooth functions in embedded designs. A single VBAT (3.0V to 5.25V DC max.) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in the CYW4356/CG8674. Two control signals, BT_REG_ON and WL_REG_ON, are used to power-up the regulators and take the respective section out of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO may be turned off/on based on the dynamic demands of the digital baseband. The CYW4356/CG8674 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO regulators. When in this state, LPLDO1 (which is a low-power linear regulator supplied by the system VIO supply) provides the CYW4356/CG8674 with all the voltages it requires, further reducing leakage currents. 2.2 CYW4356/CG8674 PMU Features ■ VBAT to 1.35Vout (600 mA maximum) Core-Buck (CBUCK) switching regulator ■ VBAT to 3.3Vout (600 mA maximum) LDO3P3 ■ VBAT to 3.3Vout (150 mA maximum) LDO3P3_B ■ VBAT to 2.5V out (70 mA maximum) BTLDO2P5 ■ 1.35V to 1.2Vout (150 mA maximum) LNLDO ■ 1.35V to 1.2Vout (300 mA maximum) CLDO with bypass mode for deep-sleep ■ Additional internal LDOs (not externally accessible) Figure 3 illustrates the typical power topology for the CYW4356/CG8674. The shaded areas are internal to the CYW4356/CG8674. Document Number: 002-20538 Rev. *B Page 9 of 144 ADVANCE CYW4356/CG8674 Figure 3. Typical Power Topology for the CYW4356/CG8674 Internal LNLDO Internal LNLDO Internal VCOLDO Internal LNLDO XTAL LDO 30 mA 1.2V WL RF – AFE 1.2V WL RF – TX (2.4 GHz, 5 GHz) 1.2V WL RF – LOGEN (2.4 GHz, 5 GHz) 1.2V WL RF – RX/LNA (2.4 GHz, 5 GHz) 1.2V WL RF – XTAL WL RF – RFPLL PFD/MMD LNLDO Max. 150 mA 1.2V BT RF DFE/DFLL WL_REG_ON PCIE PLL/RXTX BT_REG_ON Core Buck  Regulator CBUCK Mx. 600 mA VBAT WLAN BBPLL/DFLL 1.35V WLAN/BT/CLB/Top, Always‐on WL OTP VDDIO LPLDO1 3 mA 1.1V CLDO Max. 300 mA (Bypass in deep  sleep) WL PHY 1.2V–1.1V WL DIGITAL BT DIGITAL WL/BT SRAMs BTLDO2P5 Max. 70 mA 2.5V BT CLASS 1 PA WL RF‐PA (2.4 GHz, 5 GHz) LDO3P3 Max. 600 mA WL PAD (2.4 GHz, 5 GHz) 3.3V VDDIO_RF 3.3V Internal LNLDO Internal LNLDO Document Number: 002-20538 Rev. *B 2.5V LDO3P3_B Max. 150 mA 2.5V WL OTP 3.3V WL RF – VCO WL RF – CP Page 10 of 146 ADVANCE CYW4356/CG8674 2.3 WLAN Power Management The CYW4356/CG8674 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the CYW4356/CG8674 integrated RAM is a high Vt memory with dynamic clock control. The dominant supply current consumed by the RAM is leakage current only. Additionally, the CYW4356/CG8674 includes an advanced WLAN power management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW4356/CG8674 into various power management states appropriate to the current environment and activities that are being performed. The power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power up sequences are fully programmable. Configurable, free-running counters (running at 32.768 kHz LPO clock) in the PMU sequencer are used to turn on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock speeds are used wherever possible. The CYW4356/CG8674 WLAN power states are described as follows: ■ Active mode— All WLAN blocks in the CYW4356/CG8674 are powered up and fully functional with active carrier sensing and frame transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer. ■ Deep-sleep mode—Most of the chip including both analog and digital domains and most of the regulators are powered off. All main clocks (PLL, crystal oscillator, or TCXO) are shut down to reduce active power to the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active mode. Logic states in the digital core are saved and preserved into a retention memory in the always-ON domain before the digital core is powered off. Upon a wake-up event triggered by the PMU timers, an external interrupt or a host resumes through the SDIO bus and logic states in the digital core are restored to their pre-deep-sleep settings to avoid lengthy HW reinitialization. In Deep-sleep mode, the primary source of power consumption is leakage current. ■ Power-down mode—The CYW4356/CG8674 is effectively powered off by shutting down all internal regulators. The chip is brought out of this mode by external logic reenabling the internal regulators. 2.4 PMU Sequencing The PMU sequencer is responsible for minimizing system power consumption. It enables and disables various system resources based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Resource requests may come from several sources: clock requests from cores, the minimum resources defined in the ResourceMin register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of resources required to produce the requested clocks. Each resource is in one of four states: enabled, disabled, transition_on, and transition_off and has a timer that contains 0 when the resource is enabled or disabled and a non-zero value in the transition states. The timer is loaded with the time_on or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is 0, the resource can go immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can go immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. During each clock cycle, the PMU sequencer performs the following actions: ■ Computes the required resource set based on requests and the resource dependency table. ■ Decrements all timers whose values are non zero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource and inverts the ResourceState bit. ■ Compares the request with the current resource status and determines which resources must be enabled or disabled. ■ Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered up dependents. ■ Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled. Document Number: 002-20538 Rev. *B Page 11 of 144 ADVANCE CYW4356/CG8674 2.5 Power-Off Shutdown The CYW4356/CG8674 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices in the system, remain operational. When the CYW4356/CG8674 is not needed in the system, VDDIO_RF and VDDC are shut down while VBAT and VDDIO remain powered. This allows the CYW4356/CG8674 to be effectively off while keeping the I/O pins powered so that they do not draw extra current from any other devices connected to the I/O. During a low-power shut-down state, provided VDDIO remains applied to the CYW4356/CG8674, all outputs are tristated, and most inputs signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system, and enables the CYW4356/CG8674 to be fully integrated in an embedded device and take full advantage of the lowest power-savings modes. When the CYW4356/CG8674 is powered on from this state, it is the same as a normal power-up and the device does not retain any information about its state from before it was powered down. 2.6 Power-Up/Power-Down/Reset Circuits The CYW4356/CG8674 has two signals (see Table 3) that enable or disable the Bluetooth and WLAN circuits and the internal regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see Section 18. Power-Up Sequence and Timing. Table 3. Power-Up/Power-Down/Reset Control Signals Signal Description WL_REG_ON This signal is used by the PMU (with BT_REG_ON) to power up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the internal CYW4356/CG8674 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. BT_REG_ON This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal CYW4356/CG8674 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. 2.7 Wireless Charging The CYW4356/CG8674 combo IC is designed for paired operation with the BCM59350 wireless power transfer front-end chip. Working together, the two chips form a power receiver unit (PRU) that is compliant with the Alliance for Wireless Power specification (A4WP). High-level functional block diagram for wireless charging is provided in Figure 4. The power transmit unit (PTU) resides in the charging pad while the power receive unit is integrated into the mobile device. The charging process begins as the mobile device is placed onto the charging pad. The power is transferred from PTU to PRU through the TX and RX coils by means of magnetic induction. The Bluetooth control link handles communications, i.e., handshaking, between them. PTU is a BLE client, which gets performance data from the BLE server (PRU) in order to adapt its power to the mobile's need. Figure 4. High-Level Functional Block Diagram for Wireless Charging Power Transmit Unit (PTU) Power Receiver Unit (PRU) USB VBUS Detect VBUCK WPT Transmit WPT Tx Coil Resonator Wireless Power  Transfer WPT Rx Coil Resonator BCM59350 WPT  Front End WPT Control BLE BT Antenna Bluetooth Control  Link Document Number: 002-20538 Rev. *B BT Antenna Power Switch Battery PMU GPIO WPT 1.8/3.3 System power CYW4356 Bluetooth Low‐Energy (BLE) Charger System control i/f Application  Processor Page 12 of 144 ADVANCE CYW4356/CG8674 Further details on the PRU are depicted in Figure 5. It shows both ICs along with a power switch, charger, power management IC, and the application processor (system). Figure 5. Power Receiver Unit Switch kept always ON unless disabled by 59350 USB  connector VBUS DP DM GND VRECT cntl filter VBUS  sense 59350 VRECT VRECT VIN_BUCK VBUS detect AUXLDO Register  controlled input select WPC /PMA coil Vrect_low Vrect_high 20V  LDO VBUCK AUXLDO VRECT comparator 1.8V VSRC PWR MGR POR OTP A4WP coil RECT control VLDO VLDO VRECT VBUCK IBUCK FieldCLK Charger / OTG Buck cntl 1.2A CLK GEN CHGsrc FB PMIC System interface VBUCK_FB VBUCK ADC Tjunc Tntc VRECT WPC / PMA controller Control  Logic both LDOs ON (FIELD_S) VBUCK 1V8 LDO 3V3 LDO 100 mA 100 mA Register  controlled LDO input  select SYSVDDIO (1.8V) VBAT (2.9V‐4.5V) Pre‐OVP Z‐Tune BSC, INTb, GPIO NTC ADC bias in GPIO GPIO 1V8 1p8 SPDT VBAT SPDT VDDO Digtest VDD5otp VSRC INTb SCL SDA Test pins  BSC INTb VDDIO VBAT WPT interface PMU BLE antenna Logical OR  BLE subsys POR WLAN‐BLE combo Document Number: 002-20538 Rev. *B POR Internal  pwr System interfaces (SDIO, PCIe, LPO, GPIO) BT_REG_ON WL_REG_ON Page 13 of 146 ADVANCE CYW4356/CG8674 Figure 6 shows pin-to-pin connections between the CYW4356/CG8674 and BCM59350, which consist of the following: ■ Two Broadcom Serial Control (BSC)1 data and clock lines. ■ Two DC power supply lines. ■ One interrupt (INTb) to the WLAN chip. ■ One GPIO line, which is passed through an OR gate along with another signal from the application processor AP. This is for BT_REG_ON function, as illustrated in Figure 6. Figure 6. BCM59350 and CYW4356/CG8674 Interface BCM59350 CYW4356 3V3LDO VBAT 1V8LDO VDDIO SCL SDA INTb GPIO AP BT_GPIO_5 BT_GPIO_4 BT_GPIO_3 BT_REG_ON BT_GPIO_2 1. The Broadcom Serial Control bus is a proprietary bus compliant with the Philips I2C bus/interface. Document Number: 002-20538 Rev. *B Page 14 of 144 ADVANCE CYW4356/CG8674 3. Frequency References An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency reference may be used. In addition, a low-power oscillator (LPO) is provided for lower power mode timing. 3.1 Crystal Interface and Clock Generation The CYW4356/CG8674 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator including all external components is shown in Figure 7. Consult the reference schematics for the latest configuration. Figure 7. Recommended Oscillator Configuration C* W R F _X TA L _IN 3 7 .4  M H z C* X o h m s* W R F _X TA L _O U T * V alu e s d e te rm in e d  b y crystal  d rive  le ve l. Se e  re fe re n ce   sch e m atics fo r d e tails .  A fractional-N synthesizer in the CYW4356/CG8674 generates the radio frequencies, clocks, and data/packet timing, enabling it to operate using a wide selection of frequency references. For SDIO and PCIe WLAN host applications, the recommended default frequency reference is a 37.4 MHz crystal. For PCIe applications, see Table 4 for details on alternatives for the external frequency reference. The signal characteristics for the crystal oscillator interface are also listed in Table 4. Note: Although the fractional-N synthesizer can support alternative reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. Contact Cypress for further details. 3.2 External Frequency Reference For operation in SDIO mode only, an alternative to a crystal (an external precision frequency reference) can be used. The recommended default frequency is 52 MHz ±10 ppm, and it must meet the phase noise requirements listed in Table 4. If used, the external clock should be connected to the WRF_XTAL_IN pin through an external 1000 pF coupling capacitor, as shown in Figure 8. The internal clock buffer connected to this pin will be turned OFF when the CYW4356/CG8674 goes into sleep mode. When the clock buffer turns ON and OFF there will be a small impedance variation. Power must be supplied to the WRF_XTAL_VDD1P5 pin. Figure 8. Recommended Circuit to Use with an External Reference Clock 1000 pF Reference  Clock WRF_XTAL_IN NC Document Number: 002-20538 Rev. *B WRF_XTAL_OUT Page 15 of 144 ADVANCE CYW4356/CG8674 Table 4. Crystal Oscillator and External Clock—Requirements and Performance Parameter Min. Frequency External Frequency Referenceb, c Crystala Conditions/Notes Typ. Max. Min. Typ. Max. Units 2.4G and 5G bands: IEEE 802.11ac 35 operation, SDIO3.0, and PCIe WLAN interfaces 37.4 – – 52 – MHz 2.4G and 5G bands, IEEE 802.11ac – operation, PCIe interface alternative frequency 40 – – – – MHz 5G band: IEEE 802.11n operation only 19 – 52 35 – 52 MHz 2.4G band: IEEE 802.11n operation, and both bands legacy 802.11a/b/g operation only Ranges between 19 MHz and 52 MHzd, e Frequency tolerance over the lifetime of the equipment, including temperaturef Without trimming –20 – 20 –20 – 20 ppm Crystal load capacitance – – 12 – – – – pF ESR – – – 60 – – – Ω Drive level External crystal must be able to tolerate this drive level. 200 – – – – – μW Input impedance (WRF_XTAL_IN) Resistive – – – 30 100 – kΩ Capacitive – – 7.5 – – 7.5 pF WRF_XTAL_IN Input low level DC-coupled digital signal – – – 0 – 0.2 V WRF_XTAL_IN Input high level DC-coupled digital signal – – – 1.0 – 1.26 V WRF_XTAL_IN input voltage (see Figure 8) AC-coupled analog signal – – – 400 – 1200 mVp-p Duty cycle 37.4 MHz clock – – – 40 50 60 % g Phase Noise (IEEE 802.11b/g) 37.4 MHz clock at 10 kHz offset – – – – – –129 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –136 dBc/Hz Phase Noiseg (IEEE 802.11a) 37.4 MHz clock at 10 kHz offset – – – – – –137 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –144 dBc/Hz Phase Noiseg (IEEE 802.11n, 2.4 GHz) 37.4 MHz clock at 10 kHz offset – – – – – –134 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –141 dBc/Hz Phase Noiseg,h (IEEE 802.11n, 5 GHz) 37.4 MHz clock at 10 kHz offset – – – – – –142 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –149 dBc/Hz Phase Noiseg (IEEE 802.11ac, 5 GHz) 37.4 MHz clock at 10 kHz offset – – – – – –150 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –157 dBc/Hz a. (Crystal) Use WRF_XTAL_IN and WRF_XTAL_OUT. b. See External Frequency Reference for alternate connection methods. c. For a clock reference other than 37.4 MHz, 20 × log10(f/ 37.4) dB should be added to the limits, where f = the reference clock frequency in MHz. d. BT_TM6 should be tied low for a 52 MHz clock reference. For other frequencies, BT_TM6 should be tied high. Note that 52 MHz is not an auto–detected frequency using the LPO clock. e. The frequency step size is approximately 80 Hz resolution. f. It is the responsibility of the equipment designer to select oscillator components that comply with these specifications. g. Assumes that external clock has a flat phase noise response above 100 kHz. h. If the reference clock frequency is 100k Ω 0.35T tHC > 0.35T V H = 2.0V SCK V L = 0.8V thtr > 0 totr < 0.8T SD and WS T = Clock period Ttr = Minimum allowed clock period for transmitter T = Ttr * tRC is only relevant for transmitters in slave mode. Figure 22. I2S Receiver Timing T tLC > 0.35T tHC > 0.35 VH = 2.0V SCK VL = 0.8V tsr > 0.2T thr > 0 SD and WS T = Clock period Tr = Minimum allowed clock period for transmitter T > Tr Document Number: 002-20538 Rev. *B Page 39 of 144 ADVANCE CYW4356/CG8674 7.7 External Coexistence Interface An external handshake interface is available to enable signaling between the device and an external co-located wireless device, such as GPS, LTE, or UWB, to manage wireless medium sharing for optimal performance. Figure 27 and Figure 24 show the LTE coexistence interface (including UART) for each CYW4356/CG8674 package type. See Table 27 for further details on multiplexed signals, such as the GPIO pins. See Table 16 for the UART baud rate. Figure 23. Cypress GCI Mode LTE Coexistence Interface SECI_OUT WLAN SECI_IN UART_IN UART_OUT GCI BT CYW4356 LTE/IC Notes:   OR’ing to generate ISM_RX_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by  setting the GPIO mask registers appropriately.  SECI_OUT and SECI_IN are multiplexed on the GPIOs. Figure 24. Legacy 3-Wire LTE Coexistence Interface GCI_GPIO_2 WLAN WCN_PRIORITY GCI_GPIO_1 GCI MWS_RX, LTE_PRIORITY GCI_GPIO_0 LTE_FRAME_SYNC BT CYW4356 LTE/IC Note: OR’ing to generate WCN_PRIORITY FOR ERCX_TXCONF or BT_RX_PRIORITY is achieved by  setting the GPIO mask registers appropriately. Document Number: 002-20538 Rev. *B Page 40 of 144 ADVANCE CYW4356/CG8674 7.8 UART Interface One 2-wire UART interface can be enabled by software as an alternate function on GPIO pins. Refer to Table 27. Provided primarily for debugging during development, this UART enables the CYW4356/CG8674 to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It is compatible with the industry standard 16550 UART, and provides a FIFO size of 64 × 8 in each direction. 7.9 JTAG Interface The CYW4356/CG8674 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary debug and characterization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs. Refer to Table 27 for JTAG pin assignments. 7.10 SPROM Interface Various hardware configuration parameters may be stored in an external SPROM instead of the OTP. The SPROM is read by system software after device reset. In addition, depending on the board design, customer-specific parameters may be stored in SPROM. The four SPROM control signals —SPROM_CS, SPROM_CLK, SPROM_MI, and SPROM_MO are multiplexed on the SDIO interface (see Table 27 for additional details). By default, the SPROM interface supports 2 Kbit serial SPROMs, and it can also support 4 Kbit and 16 Kbit serial SPROMs by using the appropriate strapping option. Document Number: 002-20538 Rev. *B Page 41 of 144 ADVANCE CYW4356/CG8674 8. WLAN Host Interfaces 8.1 SDIO v3.0 All three package options of the CYW4356/CG8674 WLAN section provide support for SDIO version 3.0, including the new UHS-I modes: ■ DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling). ■ HS: High-speed up to 50 MHz (3.3V signaling). ■ SDR12: SDR up to 25 MHz (1.8V signaling). ■ SDR25: SDR up to 50 MHz (1.8V signaling). ■ SDR50: SDR up to 100 MHz (1.8V signaling). ■ SDR104: SDR up to 208 MHz (1.8V signaling) ■ DDR50: DDR up to 50 MHz (1.8V signaling). Note: The CYW4356/CG8674 is backward compatible with SDIO v2.0 host interfaces. The SDIO interface also has the ability to map the interrupt signal on to a GPIO pin for applications requiring an interrupt different from the one provided by the SDIO interface. The ability to force control of the gated clocks from within the device is also provided. SDIO mode is enabled by strapping options. Refer to Table 24 WLAN GPIO Functions and Strapping Options. The following three functions are supported: ■ Function 0 Standard SDIO function (max. BlockSize/ByteCount = 32B) ■ Function 1 Backplane Function to access the internal system-on-chip (SoC) address space (max. BlockSize/ByteCount = 64B) ■ Function 2 WLAN Function for efficient WLAN packet transfer through DMA (max. BlockSize/ByteCount = 512B) 8.1.1 SDIO Pins Table 18. SDIO Pin Descriptions SD 4-Bit Mode DATA0 SD 1-Bit Mode Data line 0 DATA Data line DATA1 Data line 1 or Interrupt IRQ Interrupt DATA2 Data line 2 or Read Wait RW Read Wait DATA3 Data line 3 N/C Not used CLK Clock CLK Clock CMD Command line CMD Command line Figure 25. Signal Connections to SDIO Host (SD 4-Bit Mode) CLK SD Host CMD CYW4356 DAT[3:0] Document Number: 002-20538 Rev. *B Page 42 of 144 ADVANCE CYW4356/CG8674 Figure 26. Signal Connections to SDIO Host (SD 1-Bit Mode) CLK CMD SD Host DATA CYW4356 IRQ RW Note: Per Section 6 of the SDIO specification, pull-ups in the 10 kΩ to 100 kΩ range are required on the four DATA lines and the CMD line. This requirement must be met during all operating states either through the use of external pull-up resistors or through proper programming of the SDIO host’s internal pull-ups. Document Number: 002-20538 Rev. *B Page 43 of 144 ADVANCE CYW4356/CG8674 8.2 PCI Express Interface The PCI Express (PCIe) core on the CYW4356/CG8674 is a high-performance serial I/O interconnect that is protocol compliant and electrically compatible with the PCI Express Base Specification v3.0 running at Gen1 speeds. This core contains all the necessary blocks, including logical and electrical functional subblocks to perform PCIe functionality and maintain high-speed links, using existing PCI system configuration software implementations without modification. Organization of the PCIe core is in logical layers: Transaction Layer, Data Link Layer, and Physical Layer, as shown in Figure 27. A configuration or link management block is provided for enumerating the PCIe configuration space and supporting generation and reception of System Management Messages by communicating with PCIe layers. Each layer is partitioned into dedicated transmit and receive units that allow point-to-point communication between the host and CYW4356/CG8674 device. The transmit side processes outbound packets whereas the receive side processes inbound packets. Packets are formed and generated in the Transaction and Data Link Layer for transmission onto the high-speed links and onto the receiving device. A header is added at the beginning to indicate the packet type and any other optional fields. Figure 27. PCI Express Layer Model HW/SW Interface HW/SW Interface Transaction Layer Transaction Layer Data Link Layer Data Link Layer Physical Layer Physical Layer Logical Subblock Logical Subblock Electrical Subblock Electrical Subblock TX RX TX RX 8.2.1 Transaction Layer Interface The PCIe core employs a packet-based protocol to transfer data between the host and CYW4356/CG8674 device, delivering new levels of performance and features. The upper layer of the PCIe is the Transaction Layer. The Transaction layer is primarily responsible for assembly and disassembly of Transaction Layer Packets (TLPs). TLP structure contains header, data payload, and End-to-End CRC (ECRC) fields, which are used to communicate transactions, such as read and write requests and other events. A pipelined full split-transaction protocol is implemented in this layer to maximize efficient communication between devices with creditbased flow control of TLP, which eliminates wasted link bandwidth due to retries. 8.2.2 Data Link Layer The data link layer serves as an intermediate stage between the transaction layer and the physical layer. Its primary responsibility is to provide reliable, efficient mechanism for the exchange of TLPs between two directly connected components on the link. Services provided by the data link layer include data exchange, initialization, error detection and correction, and retry services. Data Link Layer Packets (DLLPs) are generated and consumed by the data link layer. DLLPs are the mechanism used to transfer link management information between data link layers of the two directly connected components on the link, including TLP acknowledgement, power management, and flow control. Document Number: 002-20538 Rev. *B Page 44 of 144 ADVANCE CYW4356/CG8674 8.2.3 Physical Layer The physical layer of the PCIe provides a handshake mechanism between the data link layer and the high-speed signaling used for Link data interchange. This layer is divided into the logical and electrical functional subblocks. Both subblocks have dedicated transmit and receive units that allow for point-to-point communication between the host and CYW4356/CG8674 device. The transmit section prepares outgoing information passed from the data link layer for transmission, and the receiver section identifies and prepares received information before passing it to the data link layer. This process involves link initialization, configuration, scrambler, and data conversion into a specific format. 8.2.4 Logical Subblock The logical sub block primary functions are to prepare outgoing data from the data link layer for transmission and identify received data before passing it to the data link layer. 8.2.5 Scrambler/Descrambler This PCIe PHY component generates pseudo-random sequence for scrambling of data bytes and the idle sequence. On the transmit side, scrambling is applied to characters prior to the 8b/10b encoding. On the receive side, descrambling is applied to characters after 8b/10b decoding. Scrambling may be disabled in polling and recovery for testing and debugging purposes. 8.2.6 8B/10B Encoder/Decoder The PCIe core on the CYW4356/CG8674 uses an 8b/10b encoder/decoder scheme to provide DC balancing, synchronizing clock and data recovery, and error detection. The transmission code is specified in the ANSI X3.230-1994, clause 11 and in IEEE 802.3z, 36.2.4. Using this scheme, 8-bit data characters are treated as 3 bits and 5 bits mapped onto a 4-bit code group and a 6-bit code group, respectively. The control bit in conjunction with the data character is used to identify when to encode one of the twelve Special Symbols included in the 8b/10b transmission code. These code groups are concatenated to form a 10-bit symbol, which is then transmitted serially. Special Symbols are used for link management, frame TLPs, and DLLPs, allowing these packets to be quickly identified and easily distinguished. 8.2.7 Elastic FIFO An elastic FIFO is implemented in the receiver side to compensate for the differences between the transmit clock domain and the receive clock domain, with worse case clock frequency specified at 600 ppm tolerance. As a result, the transmit and receive clocks can shift one clock every 1666 clocks. In addition, the FIFO adaptively adjusts the elastic level based on the relative frequency difference of the write and read clock. This technique reduces the elastic FIFO size and the average receiver latency by half. 8.2.8 Electrical Subblock The high-speed signals utilize the Common Mode Logic (CML) signaling interface with on-chip termination and de-emphasis for bestin-class signal integrity. A de-emphasis technique is employed to reduce the effects of Intersymbol Interference (ISI) due to the interconnect by optimizing voltage and timing margins for worst case channel loss. This results in a maximally open “eye” at the detection point, thereby allowing the receiver to receive data with acceptable Bit-Error Rate (BER). To further minimize ISI, multiple bits of the same polarity that are output in succession are de-emphasized. Subsequent same bits are reduced by a factor of 3.5 dB in power. This amount is specified by PCIe to allow for maximum interoperability while minimizing the complexity of controlling the de-emphasis values. The high-speed interface requires AC coupling on the transmit side to eliminate the DC common mode voltage from the receiver. The range of AC capacitance allowed is 75 nF to 200 nF. 8.2.9 Configuration Space The PCIe function in the CYW4356/CG8674 implements the configuration space as defined in the PCI Express Base Specification v3.0. Document Number: 002-20538 Rev. *B Page 45 of 144 ADVANCE CYW4356/CG8674 9. Wireless LAN MAC and PHY 9.1 IEEE 802.11ac Draft MAC The CYW4356/CG8674 WLAN MAC is designed to support high-throughput operation with low-power consumption. It does so without compromising the Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In addition, several power saving modes have been implemented that allow the MAC to consume very little power while maintaining network-wide timing synchronization. The architecture diagram of the MAC is shown in Figure 28. The following sections provide an overview of the important modules in the MAC. Figure 28. WLAN MAC Architecture Embedded CPU Interface Host Registers, DMA Engines TX‐FIFO 32 KB PMQ RX‐FIFO 10 KB PSM PSM UCODE Memory IFS Backoff, BTCX WEP TKIP, AES, WAPI TSF SHM  BUS IHR  NAV BUS EXT‐ IHR TXE TX A‐MPDU RXE RX A‐MPDU Shared Memory 6 KB MAC‐PHY Interface The CYW4356/CG8674 WLAN media access controller (MAC) supports features specified in the IEEE 802.11 base standard, and amended by IEEE 802.11n. The key MAC features include: ■ Enhanced MAC for supporting IEEE 802.11ac Draft features ■ Transmission and reception of aggregated MPDUs (A-MPDU) for high throughput (HT) ■ Support for power management schemes, including WMM power-save, power-save multi-poll (PSMP) and multiphase PSMP operation ■ Support for immediate ACK and Block-ACK policies ■ Interframe space timing support, including RIFS ■ Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges ■ Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification ■ Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time (TBTT) generation in hardware ■ Hardware offload for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, WAPI, and support for key management ■ Support for coexistence with Bluetooth and other external radios ■ Programmable independent basic service set (IBSS) or infrastructure basic service set functionality ■ Statistics counters for MIB support Document Number: 002-20538 Rev. *B Page 46 of 144 ADVANCE CYW4356/CG8674 PSM The programmable state machine (PSM) is a micro-coded engine, which provides most of the low-level control to the hardware, to implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow control operations, which are predominant in implementations of communication protocols. The instruction set and fundamental operations are simple and general, which allows algorithms to be optimized until very late in the design process. It also allows for changes to the algorithms to track evolving IEEE 802.11 specifications. The PSM fetches instructions from the microcode memory. It uses the shared memory to obtain operands for instructions, as a data store, and to exchange data between both the host and the MAC data pipeline (via the SHM bus). The PSM also uses a scratchpad memory (similar to a register bank) to store frequently accessed and temporary variables. The PSM exercises fine-grained control over the hardware engines, by programming internal hardware registers (IHR). These IHRs are co-located with the hardware functions they control, and are accessed by the PSM via the IHR bus. The PSM fetches instructions from the microcode memory using an address determined by the program counter, instruction literal, or a program stack. For ALU operations the operands are obtained from shared memory, scratchpad, IHRs, or instruction literals, and the results are written into the shared memory, scratchpad, or IHRs. There are two basic branch instructions: conditional branches and ALU based branches. To better support the many decision points in the IEEE 802.11 algorithms, branches can depend on either a readily available signals from the hardware modules (branch condition signals are available to the PSM without polling the IHRs), or on the results of ALU operations. WEP The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform the encryption and decryption, and MIC computation and verification. The accelerators implement the following cipher algorithms: legacy WEP, WPA TKIP, WPA2 AESCCMP. The PSM determines, based on the frame type and association information, the appropriate cipher algorithm to be used. It supplies the keys to the hardware engines from an on-chip key table. The WEP interfaces with the TXE to encrypt and compute the MIC on transmit frames, and the RXE to decrypt and verify the MIC on receive frames. TXE The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit frames in the TXFIFO. It interfaces with WEP module to encrypt frames, and transfers the frames across the MAC-PHY interface at the appropriate time determined by the channel access mechanisms. The data received from the DMA engines are stored in transmit FIFOs. The MAC supports multiple logical queues to support traffic streams that have different QoS priority requirements. The PSM uses the channel access information from the IFS module to schedule a queue from which the next frame is transmitted. Once the frame is scheduled, the TXE hardware transmits the frame based on a precise timing trigger received from the IFS module. The TXE module also contains the hardware that allows the rapid assembly of MPDUs into an A-MPDU for transmission. The hardware module aggregates the encrypted MPDUs by adding appropriate headers and pad delimiters as needed. RXE The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMA engine to drain the received frames from the RXFIFO. It transfers bytes across the MAC-PHY interface and interfaces with the WEP module to decrypt frames. The decrypted data is stored in the RXFIFO. The RXE module contains programmable filters that are programmed by the PSM to accept or filter frames based on several criteria such as receiver address, BSSID, and certain frame types. The RXE module also contains the hardware required to detect A-MPDUs, parse the headers of the containers, and disaggregate them into component MPDUS. Document Number: 002-20538 Rev. *B Page 47 of 144 ADVANCE CYW4356/CG8674 IFS The IFS module contains the timers required to determine interframe space timing including RIFS timing. It also contains multiple backoff engines required to support prioritized access to the medium as specified by WMM. The interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These timers provide precise timing to the TXE to begin frame transmission. The TXE uses this information to send response frames or perform transmit frame-bursting (RIFS or SIFS separated, as within a TXOP). The backoff engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or pause the backoff counters. When the backoff counters reach 0, the TXE gets notified, so that it may commence frame transmission. In the event of multiple backoff counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies provided by the PSM. The IFS module also incorporates hardware that allows the MAC to enter a low-power state when operating under the IEEE power save mode. In this mode, the MAC is in a suspended state with its clock turned off. A sleep timer, whose count value is initialized by the PSM, runs on a slow clock and determines the duration over which the MAC remains in this suspended state. Once the timer expires the MAC is restored to its functional state. The PSM updates the TSF timer based on the sleep duration ensuring that the TSF is synchronized to the network. The IFS module also contains the PTA hardware that assists the PSM in Bluetooth coexistence functions. TSF The timing synchronization function (TSF) module maintains the TSF timer of the MAC. It also maintains the target beacon transmission time (TBTT). The TSF timer hardware, under the control of the PSM, is capable of adopting timestamps received from beacon and probe response frames in order to maintain synchronization with the network. The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer, such as uplink and downlink transmission times used in PSMP. NAV The network allocation vector (NAV) timer module is responsible for maintaining the NAV information conveyed through the duration field of MAC frames. This ensures that the MAC complies with the protection mechanisms specified in the standard. The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based on received frames. This timing information is provided to the IFS module, which uses it as a virtual carrier-sense indication. MAC-PHY Interface The MAC-PHY interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition, there is an programming interface, which can be controlled either by the host or the PSM to configure and control the PHY. 9.2 IEEE 802.11ac Draft PHY The CYW4356/CG8674 WLAN Digital PHY is designed to comply with IEEE 802.11ac Draft and IEEE 802.11a/b/g/n dual-stream specifications to provide wireless LAN connectivity supporting data rates from 1 Mbps to 866.7 Mbps for low-power, high-performance handheld applications. The PHY has been designed to work in the presence of interference, radio nonlinearity, and various other impairments. It incorporates optimized implementations of the filters, FFT and Viterbi decoder algorithms. Efficient algorithms have been designed to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition and tracking, channel estimation and tracking. The PHY receiver also contains a robust IEEE 802.11b demodulator. The PHY carrier sense has been tuned to provide high throughput for IEEE 802.11g/11b hybrid networks with Bluetooth coexistence. It has also been designed for sharing an antenna between WL and BT to support simultaneous RX-RX. The key PHY features include: ■ Programmable data rates from MCS0–15 in 20 MHz, 40 MHz, and 80 MHz channels, as specified in IEEE 802.11ac Draft ■ Supports Optional Short GI and Green Field modes in TX and RX ■ TX and RX LDPC for improved range and power efficiency ■ Beamforming support ■ All scrambling, encoding, forward error correction, and modulation in the transmit direction and inverse operations in the receive direction. ■ Supports IEEE 802.11h/k for worldwide operation ■ Advanced algorithms for low power, enhanced sensitivity, range, and reliability Document Number: 002-20538 Rev. *B Page 48 of 144 ADVANCE CYW4356/CG8674 ■ Algorithms to improve performance in presence of Bluetooth ■ Closed loop transmit power control ■ Digital RF chip calibration algorithms to handle CMOS RF chip non-idealities ■ On-the-fly channel frequency and transmit power selection ■ Supports per packet RX antenna diversity ■ Available per-packet channel quality and signal strength measurements ■ Designed to meet FCC and other worldwide regulatory requirements Figure 29. WLAN PHY Block Diagram CCK/DSSS  Demodulate Filters and  Radio Comp Frequency and  Timing Synch OFDM  Demodulate Radio Control  Block Carrier Sense, AGC,  and Rx FSM Buffers Viterbi Decoder Descramble  and Deframe MAC  Interface FFT/IFFT AFE  and  Radio Tx FSM Common Logic  Block Modulation  and Coding Frame and  Scramble Filters and Radio  Comp PA Comp Modulate/ Spread COEX Document Number: 002-20538 Rev. *B Page 49 of 144 ADVANCE CYW4356/CG8674 10. WLAN Radio Subsystem The CYW4356/CG8674 includes an integrated dual-band WLAN RF transceiver that has been optimized for use in 2.4 GHz and 5 GHz Wireless LAN systems. It has been designed to provide low-power, low-cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII bands. The transmit and receive sections include all on-chip filtering, mixing, and gain control functions. Sixteen RF control signals are available (eight per core) to drive external RF switches and support optional external power amplifiers and low-noise amplifiers for each band. See the reference board schematics for further details. A block diagram of the radio subsystem (core 0) is shown in Figure 30. Core 1, is identical to Core 0 without the Bluetooth blocks. Note that integrated on-chip baluns (not shown) convert the fully differential transmit and receive paths to single-ended signal pins. Document Number: 002-20538 Rev. *B Page 50 of 144 ADVANCE CYW4356/CG8674 Figure 30. Radio Functional Block Diagram (Core 0) WL DAC WL PA WL PAD WL PGA WL A‐PA WL A‐PAD WL A‐PGA WL TXLPF WL TX G‐Mixer WL DAC WL TXLPF WL TX A‐Mixer WL RX A‐Mixer Voltage  Regulators WLAN BB WL ADC WL A‐LNA11 WL A‐LNA12 WL RXLPF MUX WL ADC SLNA WL G‐LNA12 WL RXLPF WL RX G‐Mixer WL ATX CLB WL ARX WL GTX WL GRX WL LOGEN WL PLL Gm BT LNA GM Shared XO BT RX BT TX BT LOGEN BT PLL LPO/Ext LPO/RCAL BT ADC BT RXLPF BT ADC BT LNA Load BT RX Mixer BT RXLPF BT BB BT PA BT  BT DAC BT DAC BT TX Mixer Document Number: 002-20538 Rev. *B BT TXLPF Page 51 of 144 ADVANCE CYW4356/CG8674 10.1 Receiver Path The CYW4356/CG8674 has a wide dynamic range, direct conversion receiver that employs high order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band or the entire 5 GHz U-NII band. An on-chip low noise amplifier (LNA) in the 2.4 GHz path in core 0 is shared between the Bluetooth and WLAN receivers, whereas the 5 GHz receive path and the core 1 2.4 GHz receive path have dedicated on-chip LNAs. Control signals are available that can support the use of external LNAs for each band, which can increase the receive sensitivity by several dB. 10.2 Transmit Path Baseband data is modulated and upconverted to the 2.4 GHz ISM or 5 GHz U-NII bands, respectively. Linear on-chip power amplifiers are included, which are capable of delivering high output power while meeting IEEE 802.11ac and IEEE 802.11a/b/g/n specifications, and without the need for external PAs. When using the internal PAs, closed-loop output power control is completely integrated. 10.3 Calibration The CYW4356/CG8674 features dynamic and automatic on-chip calibration to continually compensate for temperature and process variations across components. These calibration routines are performed periodically in the course of normal radio operation. Examples of some of the automatic calibration algorithms are baseband filter calibration for optimum transmit and receive performance, and LOFT calibration for carrier leakage reduction. In addition, I/Q Calibration, R Calibration, and VCO Calibration are performed on-chip. No per-board calibration is required in manufacturing test, which helps to minimize the test time and cost in large volume production. Document Number: 002-20538 Rev. *B Page 52 of 144 ADVANCE CYW4356/CG8674 11. Pin Information 11.1 Ball Maps Figure 31 shows the WLBGA ball map. Figure 31. CYW4356/CG8674 A2 WLBGA BALL MAP; 12 × 18 Array; 192 Balls; Bottom View (Balls Facing Up) 12 11 10 9 8 7 6 5 4 3 2 A SR_PVSS SR_VLX WL_REG_ON SDIO_CMD SDIO_CLK BT_GPIO_5 BT_GPIO_2 PCIE_REFCLKN PCIE_REFCLKP PCIE_TDN PCIE_TDP B SR_VDDBATP5V SR_VDDBATA5V PMU_AVSS SDIO_DATA_0 SDIO_DATA_2 VDDC NC PCIE_PLL_AVSS PCIE_RXTX_AVSS PCIE_PLL_AVDD1P2 PCIE_RXTX_AVDD1 P2 PCIE_RDN B C LDO_VDD1P5 VOUT_CLDO VSSC SDIO_DATA_1 SDIO_DATA_3 NC NC PCIE_PME_L PCIE_PERST_L PCIE_TESTP PCIE_TESTN PCIE_RDP C D VOUT_BTLDO2P5 VOUT_LNLDO BT_REG_ON JTAG_SEL BT_GPIO_3 VSSC PCIE_CLKREQ_L VDDC VSSC E LDO_VDDBAT5V VOUT_LDO3P3_B VDDIO VDDC VDDIO_SD GPIO_7 GPIO_9 BT_USB_DN BT_VDDC F VOUT_3P3 GPIO_2 GPIO_1 GPIO_5 GPIO_6 GPIO_8 LPO_IN BT_USB_DP CLK_REQ G VSSC GPIO_0 VDDC GPIO_3 VSSC AVSS_BBPLL BT_I2S_DO BT_I2S_DI H GPIO_10 VDDIO_RF GPIO_4 J VDDC RF_SW_CTRL_9 RF_SW_CTRL_12 K RF_SW_CTRL_8 M RF_SW_CTRL_10 N WRF_XTAL_OUT P WRF_XTAL_IN VDDC RF_SW_CTRL_11 RF_SW_CTRL_14 WRF_XTAL_GND1P2 WRF_XTAL_VDD1P2 WRF_XTAL_VDD1P5 A D FM_AUDIOVDD1P2 FM_AOUT1 E FM_PLLVDD1P2 FM_AUDIOVSS FM_AOUT2 F VSSC FM_PLLVSS FM_VCOVSS FM_LNAVCOVDD1P 2 G BT_UART_RXD BT_PCM_OUT BT_VDDC FM_LNAVSS FM_RFIN H BT_I2S_CLK BT_UART_TXD BT_PCM_IN BT_HOST_WAKE BT_VCOVSS BT_VCOVDD1P2 J BT_VDDO BT_PCM_SYNC BT_UART_RTS_N BT_GPIO_4 BT_IFVDD1P2 BT_PLLVDD1P2 BT_LNAVDD1P2 K RF_SW_CTRL_15 VSSC BT_I2S_WS BT_UART_CTS_N BT_DEV_WAKE BT_PLLVSS BT_PAVSS BT_RF L RF_SW_CTRL_7 VDDC BT_PCM_CLK BT_VDDC VSSC BT_IFVSS BT_PAVDD2P5 M RF_SW_CTRL_1 RF_SW_CTRL_3 RF_SW_CTRL_4 RF_SW_CTRL_5 RF_SW_CTRL_6 AVDD_BBPLL VDDC RF_SW_CTRL_13 VSSC L 1 RF_SW_CTRL_2 WRF_AFE_GND1P2_ WRF_TX_GND1P2_ CORE0 CORE0 WRF_PA2G_VBAT_ WRF_RFOUT_2G_C GND3P3_CORE0 ORE0 N P R WRF_BUCK_GND1P WRF_BUCK_VDD1P 5_CORE1 5_CORE1 WRF_LOGEN_GND1 WRF_LOGENG_GND WRF_GPIO_OUT_C WRF_PADRV_VBAT WRF_PA2G_VBAT_ P2 1P2 ORE0 _VDD3P3_CORE0 GND3P3_CORE0 WRF_PA2G_VBAT_ VDD3P3_CORE0 R T WRF_RX5G_GND1P WRF_TSSI_A_CORE WRF_PADRV_VBAT WRF_PADRV_VBAT WRF_TX_GND1P2_ WRF_RX2G_GND1P WRF_PADRV_VBAT WRF_PA5G_VBAT_ WRF_MMD_GND1P2 WRF_MMD_VDD1P2 WRF_PFD_VDD1P2 2_CORE1 1 _GND3P3_CORE1 _VDD3P3_CORE1 CORE1 2_CORE1 _GND3P3_CORE0 GND3P3_CORE0 WRF_PA5G_VBAT_ VDD3P3_CORE0 T U WRF_LNA_5G_GND WRF_PA5G_VBAT_ 1P2_CORE1 GND3P3_CORE1 WRF_PA2G_VBAT_ WRF_LNA_2G_GND WRF_BUCK_VDD1P WRF_TSSI_A_CORE WRF_PA5G_VBAT_ WRF_RFOUT_5G_C WRF_VCO_GND1P2 WRF_PFD_GND1P2 GND3P3_CORE1 1P2_CORE1 5_CORE0 0 GND3P3_CORE0 ORE0 U V WRF_RFIN_5G_COR WRF_RFOUT_5G_C WRF_PA5G_VBAT_ E1 ORE1 VDD3P3_CORE1 12 11 WRF_GPIO_OUT_C WRF_AFE_GND1P2_ ORE1 CORE1 WRF_RX2G_GND1P WRF_LNA_2G_GND WRF_RFIN_2G_COR 2_CORE0 1P2_CORE0 E0 WRF_PA5G_VBAT_ GND3P3_CORE1 WRF_PA2G_VBAT_ GND3P3_CORE1 RF_SW_CTRL_0 WRF_PA2G_VBAT_ WRF_RFOUT_2G_C WRF_RFIN_2G_COR WRF_SYNTH_VBAT VDD3P3_CORE1 ORE1 E1 _VDD3P3 10 Document Number: 002-20538 Rev. *B 9 8 7 6 WRF_CP_GND1P2 5 WRF_BUCK_GND1P WRF_RX5G_GND1P WRF_LNA_5G_GND WRF_RFIN_5G_COR 5_CORE0 2_CORE0 1P2_CORE0 E0 4 3 2 V 1 Page 53 of 144 ADVANCE CYW4356/CG8674 11.2 Pin Lists Table 19. Pin List by Pin Number (192-Pin WLBGA Package) WLBGA Ball# Pin Name A10 WL_REG_ON A11 SR_VLX A12 SR_PVSS A2 PCIE_TDP0 A3 PCIE_TDN0 A4 PCIE_REFCLKP A5 PCIE_REFCLKN A6 BT_GPIO_2 A7 BT_GPIO_5 A8 SDIO_CLK A9 SDIO_CMD B1 PCIE_RDN0 B10 PMU_AVSS B11 SR_VDDBATA5V B12 SR_VDDBATP5V B2 PCIE_RXTX_AVDD1P2 B3 PCIE_PLL_AVDD1P2 B4 PCIE_RXTX_AVSS B5 PCIE_PLL_AVSS B6 NC B7 VDD/VDDC B8 SDIO_DATA_2 B9 SDIO_DATA_0 C1 PCIE_RDP0 C10 VSSC/VSS C11 VOUT_CLDO C12 LDO_VDD1P5 C2 PCIE_TESTN C3 PCIE_TESTP C4 PCIE_PERST_L C5 PCIE_PME_L C6 NC C7 NC C8 SDIO_DATA_3 C9 SDIO_DATA_1 D10 BT_REG_ON D11 VOUT_LNLDO D12 VOUT_BTLDO2P5 D3 VSSC/VSS D4 VDD/VDDC D5 PCIE_CLKREQ_L Document Number: 002-20538 Rev. *B Table 19. Pin List by Pin Number (192-Pin WLBGA Package) WLBGA Ball# Pin Name D6 VSSC/VSS D7 BT_GPIO_3 D9 JTAG_SEL E1 FM_AOUT1 E10 VDDIO E11 VOUT_LDO3P3_B E12 LDO_VDDBAT5V E2 FM_AUDIOVDD1P2 E4 BT_VDDC E5 BT_USB_DN E6 GPIO_9 E7 GPIO_7 E8 VDDIO_SD E9 VDD/VDDC F1 FM_AOUT2 F10 GPIO_1 F11 GPIO_2 F12 VOUT_3P3 F2 FM_AUDIOVSS F3 FM_PLLVDD1P2 F4 CLK_REQ F5 BT_USB_DP F6 LPO_IN F7 GPIO_8 F8 GPIO_6 F9 GPIO_5 G1 FM_LNAVCOVDD1P2 G10 VDD/VDDC G11 GPIO_0 G12 VSSC/VSS G2 FM_VCOVSS G3 FM_PLLVSS G4 VSSC/VSS G5 BT_I2S_DI G6 BT_I2S_DO G7 AVSS_BBPLL G8 VSSC/VSS G9 GPIO_3 H1 FM_RFIN H11 VDDIO_RF H12 GPIO_10 Page 54 of 144 ADVANCE Table 19. Pin List by Pin Number (192-Pin WLBGA Package) WLBGA Ball# Pin Name CYW4356/CG8674 Table 19. Pin List by Pin Number (192-Pin WLBGA Package) WLBGA Ball# Pin Name H2 FM_LNAVSS M6 BT_PCM_CLK H3 BT_VDDC M7 VDD/VDDC H4 BT_PCM_OUT M8 RF_SW_CTRL_7 H5 BT_UART_RXD N1 WRF_RFIN_2G_CORE0 H7 AVDD_BBPLL N10 WRF_XTAL_VDD1P2 H9 GPIO_4 N11 WRF_XTAL_GND1P2 J1 BT_VCOVDD1P2 N12 WRF_XTAL_OUT J11 RF_SW_CTRL_9 N2 WRF_LNA_2G_GND1P2_CORE0 J12 VDD/VDDC N3 WRF_RX2G_GND1P2_CORE0 J2 BT_VCOVSS N5 RF_SW_CTRL_4 J3 BT_HOST_WAKE N7 RF_SW_CTRL_3 J4 BT_PCM_IN N8 RF_SW_CTRL_1 J5 BT_UART_TXD P1 WRF_RFOUT_2G_CORE0 J6 BT_I2S_CLK P11 WRF_XTAL_VDD1P5 J8 VDD/VDDC P12 WRF_XTAL_IN J9 RF_SW_CTRL_12 P2 WRF_PA2G_VBAT_GND3P3_CORE0 K1 BT_LNAVDD1P2 P3 WRF_TX_GND1P2_CORE0 K10 RF_SW_CTRL_13 P4 WRF_AFE_GND1P2_CORE0 K12 RF_SW_CTRL_8 P5 RF_SW_CTRL_6 K2 BT_PLLVDD1P2 P7 RF_SW_CTRL_5 K3 BT_IFVDD1P2 P9 RF_SW_CTRL_2 K4 BT_GPIO_4 R1 WRF_PA2G_VBAT_VDD3P3_CORE0 K5 BT_UART_RTS_L R11 WRF_BUCK_VDD1P5_CORE1 K6 BT_PCM_SYNC R12 WRF_BUCK_GND1P5_CORE1 K7 BT_VDDIO R2 WRF_PA2G_VBAT_GND3P3_CORE0 L1 BT_RF R3 WRF_PADRV_VBAT_VDD3P3_CORE0 L10 VDD/VDDC R4 WRF_GPIO_OUT_CORE0 L11 VSSC/VSS R5 WRF_LOGENG_GND1P2 L2 BT_PAVSS R6 WRF_LOGEN_GND1P2 L3 BT_PLLVSS R7 RF_SW_CTRL_0 L4 BT_DEV_WAKE R8 WRF_AFE_GND1P2_CORE1 L5 BT_UART_CTS_L R9 WRF_GPIO_OUT_CORE1 L6 BT_I2S_WS T1 WRF_PA5G_VBAT_VDD3P3_CORE0 L7 VSSC/VSS T10 WRF_PADRV_VBAT_GND3P3_CORE1 L8 RF_SW_CTRL_15 T11 WRF_TSSI_A_CORE1 L9 RF_SW_CTRL_11 T12 WRF_RX5G_GND1P2_CORE1 M1 BT_PAVDD2P5 T2 WRF_PA5G_VBAT_GND3P3_CORE0 M10 RF_SW_CTRL_14 T3 WRF_PADRV_VBAT_GND3P3_CORE0 M12 RF_SW_CTRL_10 T4 WRF_PFD_VDD1P2 M3 BT_IFVSS T5 WRF_MMD_VDD1P2 M4 VSSC/VSS T6 WRF_MMD_GND1P2 M5 BT_VDDC T7 WRF_RX2G_GND1P2_CORE1 Document Number: 002-20538 Rev. *B Page 55 of 144 ADVANCE CYW4356/CG8674 Table 19. Pin List by Pin Number (192-Pin WLBGA Package) WLBGA Ball# Pin Name T8 WRF_TX_GND1P2_CORE1 T9 WRF_PADRV_VBAT_VDD3P3_CORE1 U1 WRF_RFOUT_5G_CORE0 U10 WRF_PA5G_VBAT_GND3P3_CORE1 U11 WRF_PA5G_VBAT_GND3P3_CORE1 U12 WRF_LNA_5G_GND1P2_CORE1 U2 WRF_PA5G_VBAT_GND3P3_CORE0 U3 WRF_TSSI_A_CORE0 U4 WRF_BUCK_VDD1P5_CORE0 U5 WRF_PFD_GND1P2 U6 WRF_VCO_GND1P2 U7 WRF_LNA_2G_GND1P2_CORE1 U8 WRF_PA2G_VBAT_GND3P3_CORE1 U9 WRF_PA2G_VBAT_GND3P3_CORE1 V1 WRF_RFIN_5G_CORE0 V10 WRF_PA5G_VBAT_VDD3P3_CORE1 V11 WRF_RFOUT_5G_CORE1 V12 WRF_RFIN_5G_CORE1 V2 WRF_LNA_5G_GND1P2_CORE0 V3 WRF_RX5G_GND1P2_CORE0 V4 WRF_BUCK_GND1P5_CORE0 V5 WRF_CP_GND1P2 V6 WRF_SYNTH_VBAT_VDD3P3 V7 WRF_RFIN_2G_CORE1 V8 WRF_RFOUT_2G_CORE1 V9 WRF_PA2G_VBAT_VDD3P3_CORE1 Document Number: 002-20538 Rev. *B Page 56 of 144 ADVANCE Table 20. Pin List by Pin Name (192-Pin WLBGA Package) Pin Name CYW4356/CG8674 Table 20. Pin List by Pin Name (192-Pin WLBGA Package) Pin Name WLBGA Ball# WLBGA Ball# AVDD_BBPLL H7 FM_LNAVCOVDD1P2 AVSS_BBPLL G7 FM_LNAVSS H2 BT_DEV_WAKE L4 FM_PLLVDD1P2 F3 BT_GPIO_2 A6 FM_PLLVSS G3 BT_GPIO_5 A7 FM_RFIN H1 BT_GPIO_3 D7 FM_VCOVSS G2 BT_GPIO_4 K4 GPIO_0 G11 BT_HOST_WAKE J3 GPIO_1 F10 BT_I2S_CLK J6 GPIO_10 H12 BT_I2S_DI G5 GPIO_2 F11 BT_I2S_DO G6 GPIO_3 G9 BT_I2S_WS L6 GPIO_4 H9 BT_IFVDD1P2 K3 GPIO_5 F9 BT_IFVSS M3 GPIO_6 F8 BT_LNAVDD1P2 K1 GPIO_7 E7 BT_PAVDD2P5 M1 GPIO_8 F7 BT_PAVSS L2 GPIO_9 E6 BT_PCM_CLK M6 JTAG_SEL D9 BT_PCM_IN J4 LDO_VDD1P5 C12 BT_PCM_OUT H4 LDO_VDDBAT5V E12 BT_PCM_SYNC K6 LPO_IN F6 BT_PLLVDD1P2 K2 NC B6 BT_PLLVSS L3 NC C7 BT_REG_ON D10 NC C6 BT_RF L1 PCIE_PME_L C5 BT_UART_CTS_L L5 PCIE_CLKREQ_L D5 BT_UART_RTS_L K5 PCIE_PERST_L C4 BT_UART_RXD H5 PCIE_PLL_AVDD1P2 B3 BT_UART_TXD J5 PCIE_PLL_AVSS B5 BT_USB_DN E5 PCIE_RDN0 B1 BT_USB_DP F5 PCIE_RDP0 C1 BT_VCOVDD1P2 J1 PCIE_REFCLKN A5 BT_VCOVSS J2 PCIE_REFCLKP A4 BT_VDDC E4 PCIE_RXTX_AVDD1P2 B2 BT_VDDC H3 PCIE_RXTX_AVSS B4 BT_VDDC M5 PCIE_TDN0 A3 BT_VDDIO K7 PCIE_TDP0 A2 CLK_REQ F4 PCIE_TESTN C2 FM_AOUT1 E1 PCIE_TESTP C3 FM_AOUT2 F1 PMU_AVSS B10 FM_AUDIOVDD1P2 E2 RF_SW_CTRL_0 R7 FM_AUDIOVSS F2 RF_SW_CTRL_1 N8 Document Number: 002-20538 Rev. *B G1 Page 57 of 144 ADVANCE Table 20. Pin List by Pin Name (192-Pin WLBGA Package) Pin Name CYW4356/CG8674 Table 20. Pin List by Pin Name (192-Pin WLBGA Package) WLBGA Ball# Pin Name WLBGA Ball# RF_SW_CTRL_10 M12 VSSC/VSS D6 RF_SW_CTRL_11 L9 VSSC/VSS G12 RF_SW_CTRL_12 J9 VSSC/VSS G4 RF_SW_CTRL_13 K10 VSSC/VSS G8 RF_SW_CTRL_14 M10 VSSC/VSS L11 RF_SW_CTRL_15 L8 VSSC/VSS L7 RF_SW_CTRL_2 P9 VSSC/VSS M4 RF_SW_CTRL_3 N7 WL_REG_ON A10 RF_SW_CTRL_4 N5 WRF_AFE_GND1P2_CORE0 P4 RF_SW_CTRL_5 P7 WRF_AFE_GND1P2_CORE1 R8 RF_SW_CTRL_6 P5 WRF_BUCK_GND1P5_CORE0 V4 RF_SW_CTRL_7 M8 WRF_BUCK_GND1P5_CORE1 R12 RF_SW_CTRL_8 K12 WRF_BUCK_VDD1P5_CORE0 U4 RF_SW_CTRL_9 J11 WRF_BUCK_VDD1P5_CORE1 R11 SDIO_CLK A8 WRF_CP_GND1P2 V5 SDIO_CMD A9 WRF_GPIO_OUT_CORE0 R4 SDIO_DATA_0 B9 WRF_GPIO_OUT_CORE1 R9 SDIO_DATA_1 C9 WRF_LNA_2G_GND1P2_CORE0 N2 SDIO_DATA_2 B8 WRF_LNA_2G_GND1P2_CORE1 U7 SDIO_DATA_3 C8 WRF_LNA_5G_GND1P2_CORE0 V2 SR_PVSS A12 WRF_LNA_5G_GND1P2_CORE1 U12 SR_VDDBATA5V B11 WRF_LOGEN_GND1P2 R6 SR_VDDBATP5V B12 WRF_LOGENG_GND1P2 R5 SR_VLX A11 WRF_MMD_GND1P2 T6 VDD/VDDC B7 WRF_MMD_VDD1P2 T5 VDD/VDDC D4 WRF_PA2G_VBAT_GND3P3_CORE0 P2 VDD/VDDC E9 WRF_PA2G_VBAT_GND3P3_CORE0 R2 VDD/VDDC G10 WRF_PA2G_VBAT_GND3P3_CORE1 U8 VDD/VDDC J12 WRF_PA2G_VBAT_GND3P3_CORE1 U9 VDD/VDDC J8 WRF_PA2G_VBAT_VDD3P3_CORE0 R1 VDD/VDDC L10 WRF_PA2G_VBAT_VDD3P3_CORE1 V9 VDD/VDDC M7 WRF_PA5G_VBAT_GND3P3_CORE0 T2 VDDIO E10 WRF_PA5G_VBAT_GND3P3_CORE0 U2 VDDIO_RF H11 WRF_PA5G_VBAT_GND3P3_CORE1 U10 VDDIO_SD E8 WRF_PA5G_VBAT_GND3P3_CORE1 U11 VOUT_3P3 F12 WRF_PA5G_VBAT_VDD3P3_CORE0 T1 VOUT_BTLDO2P5 D12 WRF_PA5G_VBAT_VDD3P3_CORE1 V10 VOUT_CLDO C11 WRF_PADRV_VBAT_GND3P3_CORE0 T3 VOUT_LDO3P3_B E11 WRF_PADRV_VBAT_GND3P3_CORE1 T10 VOUT_LNLDO D11 WRF_PADRV_VBAT_VDD3P3_CORE0 R3 VSSC/VSS C10 WRF_PADRV_VBAT_VDD3P3_CORE1 T9 VSSC/VSS D3 WRF_PFD_GND1P2 U5 Document Number: 002-20538 Rev. *B Page 58 of 144 ADVANCE CYW4356/CG8674 Table 20. Pin List by Pin Name (192-Pin WLBGA Package) Pin Name WLBGA Ball# WRF_PFD_VDD1P2 T4 WRF_RFIN_2G_CORE0 N1 WRF_RFIN_2G_CORE1 V7 WRF_RFIN_5G_CORE0 V1 WRF_RFIN_5G_CORE1 V12 WRF_RFOUT_2G_CORE0 P1 WRF_RFOUT_2G_CORE1 V8 WRF_RFOUT_5G_CORE0 U1 WRF_RFOUT_5G_CORE1 V11 WRF_RX2G_GND1P2_CORE0 N3 WRF_RX2G_GND1P2_CORE1 T7 WRF_RX5G_GND1P2_CORE0 V3 WRF_RX5G_GND1P2_CORE1 T12 WRF_SYNTH_VBAT_VDD3P3 V6 WRF_TSSI_A_CORE0 U3 WRF_TSSI_A_CORE1 T11 WRF_TX_GND1P2_CORE0 P3 WRF_TX_GND1P2_CORE1 T8 WRF_VCO_GND1P2 U6 WRF_XTAL_GND1P2 N11 WRF_XTAL_IN P12 WRF_XTAL_OUT N12 WRF_XTAL_VDD1P2 N10 WRF_XTAL_VDD1P5 P11 Document Number: 002-20538 Rev. *B Page 59 of 144 ADVANCE CYW4356/CG8674 Table 21. 395-Bump WLCSP Coordinates Coordinates (0,0 center of die) No. Net Name Bump Side X Top Side Y X Y 1 PCIE_RXTX_AVSS 2300.51 3659.87 –2300.51 3659.87 2 PCIE_PLL_AVSS 1966.81 3659.87 –1966.81 3659.87 3 PCIE_REFCLKP 1966.81 3434.87 –1966.81 3434.87 4 PCIE_REFCLKN 1800.31 3547.37 –1800.31 3547.37 5 PCIE_TDN0 2134.01 3547.37 –2134.01 3547.37 6 PCIE_TDP0 2134.01 3322.37 –2134.01 3322.37 7 PCIE_RXTX_AVDD1P2 2134.01 3068.53 –2134.01 3068.53 8 PCIE_RDP0 2300.51 3209.87 –2300.51 3209.87 9 PCIE_RDN0 2300.51 3434.87 –2300.51 3434.87 10 PCIE_PLL_AVSS 1966.81 3209.87 –1966.81 3209.87 11 PCIE_PLL_AVDD1P2 1800.31 3322.37 –1800.31 3322.37 12 NC 508.44 3481.00 –508.44 3481.00 13 NC 768.62 3062.57 –768.62 3062.57 14 NC 508.44 3281.00 –508.44 3281.00 15 NC 1177.22 3062.57 –1177.22 3062.57 16 NC 972.92 3062.57 –972.92 3062.57 17 NC 553.11 3681.00 –553.11 3681.00 18 NC 753.11 3681.00 –753.11 3681.00 19 NC 773.17 3481.00 –773.17 3481.00 20 NC 773.17 3281.00 –773.17 3281.00 21 NC 974.72 3481.00 –974.72 3481.00 22 NC 974.72 3281.00 –974.72 3281.00 23 NC 982.37 3681.00 –982.37 3681.00 24 NC 1176.88 3281.00 –1176.88 3281.00 25 NC 1176.88 3481.00 –1176.88 3481.00 26 NC 1186.67 3681.00 –1186.67 3681.00 27 NC 526.91 3062.57 –526.91 3062.57 28 NC 1177.22 2860.07 –1177.22 2860.07 29 NC 768.62 2860.07 –768.62 2860.07 30 GND 1601.79 3595.19 –1601.79 3595.19 31 NC 1601.79 2792.39 –1601.79 2792.39 32 GND 1401.09 3394.49 –1401.09 3394.49 33 NC 1601.79 3394.49 –1601.79 3394.49 34 GND 1601.79 2993.09 –1601.79 2993.09 35 NC 1601.79 3193.79 –1601.79 3193.79 36 GND 1401.09 2792.39 –1401.09 2792.39 37 GND 1401.09 3595.19 –1401.09 3595.19 38 NC 1401.09 2993.09 –1401.09 2993.09 39 GND 1401.09 3193.79 –1401.09 3193.79 Document Number: 002-20538 Rev. *B Page 60 of 144 ADVANCE CYW4356/CG8674 Table 21. 395-Bump WLCSP Coordinates (Cont.) Coordinates (0,0 center of die) No. Net Name Bump Side X Top Side Y X Y 40 BT_PAVSS 2217.95 –736.50 –2217.95 –736.50 41 BT_AGPIO 2017.95 –1298.03 –2017.95 –1298.03 42 BT_IFVDD1P2 1768.91 –1298.03 –1768.91 –1298.03 43 BT_IFVSS 1568.92 –1298.03 –1568.92 –1298.03 44 BT_LNAVDD1P2 2228.18 –392.72 –2228.18 –392.72 45 BT_LNAVSS 1843.60 –524.82 –1843.60 –524.82 46 BT_PAVDD2P5 2176.03 –1164.53 –2176.03 –1164.53 47 BT_PLLVDD1P2 1768.91 –223.55 –1768.91 –223.55 48 BT_PLLVSS 1568.92 –223.55 –1568.92 –223.55 49 BT_RF 2252.39 –936.50 –2252.39 –936.50 50 BT_VCOVDD1P2 2227.01 –189.65 –2227.01 –189.65 51 BT_VCOVSS 1967.62 –45.40 –1967.62 –45.40 52 FM_AUDIOVDD1P2 2044.00 931.81 –2044.00 931.81 53 FM_AUDIOAVSS 2044.00 1143.58 –2044.00 1143.58 54 FM_AOUT1 2244.00 1143.58 –2244.00 1143.58 55 FM_AOUT2 2244.00 931.81 –2244.00 931.81 56 FM_IFVDD1P2 1614.95 371.79 –1614.95 371.79 57 FM_IFVSS 1614.95 171.80 –1614.95 171.80 58 FM_PLLVSS 1793.21 871.61 –1793.21 871.61 59 FM_PLLVDD1P2 1686.40 695.87 –1686.40 695.87 60 FM_RFAUX 2273.40 68.08 –2273.40 68.08 61 FM_RFIN 2260.02 313.69 –2260.02 313.69 62 FM_LNAVDD1P2 2060.02 354.59 –2060.02 354.59 63 FM_LNAVSS 2060.02 154.59 –2060.02 154.59 64 FM_VCOVDD1P2 2273.40 731.81 –2273.40 731.81 65 FM_VCOVSS 2273.40 531.81 –2273.40 531.81 66 RF_SW_CTRL_0 –2202.33 –1494.00 2202.33 –1494.00 67 VDDC –661.10 –1355.99 661.10 –1355.99 68 VSSC 740.99 2052.00 –740.99 2052.00 69 VSSC –616.50 –408.01 616.50 –408.01 70 VSSC –459.00 –198.00 459.00 –198.00 71 VSSC –546.71 –1008.00 546.71 –1008.00 72 VSSC –546.71 –708.00 546.71 –708.00 73 VSSC –459.00 252.00 459.00 252.00 74 VDDC –661.10 –21.01 661.10 –21.01 75 VSSC 740.99 2352.00 –740.99 2352.00 76 VDDIO_SD –405.00 2299.50 405.00 2299.50 77 SDIO_DATA_1 –337.05 2531.57 337.05 2531.57 78 SDIO_CLK –337.05 2731.57 337.05 2731.57 79 SDIO_DATA_3 –337.05 2931.58 337.05 2931.58 Document Number: 002-20538 Rev. *B Page 61 of 144 ADVANCE CYW4356/CG8674 Table 21. 395-Bump WLCSP Coordinates (Cont.) Coordinates (0,0 center of die) No. Net Name Bump Side Top Side X Y X Y 80 SDIO_DATA_2 –337.05 3131.59 337.05 3131.59 81 SDIO_CMD –337.05 3331.59 337.05 3331.59 82 SDIO_DATA_0 –337.05 3531.60 337.05 3531.60 83 VSSC –316.50 –408.01 316.50 –408.01 84 VSSC –266.51 –1008.00 266.51 –1008.00 85 VSSC –266.51 –708.00 266.51 –708.00 86 RF_SW_CTRL_4 –2072.12 –1125.00 2072.12 –1125.00 87 VDDC –261.11 –21.01 261.11 –21.01 88 VSSC –259.00 1651.99 259.00 1651.99 89 VSSC –159.00 252.00 159.00 252.00 90 VSSC –159.00 552.00 159.00 552.00 91 VSSC –159.00 851.99 159.00 851.99 92 VSSC –159.00 1151.99 159.00 1151.99 93 VSSC –159.00 1451.99 159.00 1451.99 94 VSSC –159.00 2052.00 159.00 2052.00 95 VSSC –459.00 552.00 459.00 552.00 96 GND –67.05 2286.36 67.05 2286.36 97 GND –67.05 2486.57 67.05 2486.57 98 VDDC_98 –67.05 2686.57 67.05 2686.57 99 NC –67.05 2886.58 67.05 2886.58 100 NC –67.05 3086.59 67.05 3086.59 101 NC –67.05 3286.59 67.05 3286.59 102 VDDC_102 –67.05 3486.60 67.05 3486.60 103 VDDC –61.11 –1220.99 61.11 –1220.99 104 VSSC –61.11 –1008.00 61.11 –1008.00 105 VSSC –61.11 –708.00 61.11 –708.00 106 VSSC –61.11 –408.01 61.11 –408.01 107 VDDC –61.11 –21.01 61.11 –21.01 108 VDDC –61.11 1843.97 61.11 1843.97 109 VDDC 138.89 –1220.99 –138.89 –1220.99 110 VDDC 138.89 –1021.00 –138.89 –1021.00 111 VDDC 138.89 –821.00 –138.89 –821.00 112 VDDC –261.11 –1220.99 261.11 –1220.99 113 VDDC 138.89 –421.00 –138.89 –421.00 114 VDDC 138.89 –221.00 –138.89 –221.00 115 VDDC 138.89 –21.01 –138.89 –21.01 116 VSSC 140.99 252.00 –140.99 252.00 117 VSSC 140.99 552.00 –140.99 552.00 118 VSSC 140.99 851.99 –140.99 851.99 119 VSSC 140.99 1151.99 –140.99 1151.99 Document Number: 002-20538 Rev. *B Page 62 of 144 ADVANCE CYW4356/CG8674 Table 21. 395-Bump WLCSP Coordinates (Cont.) Coordinates (0,0 center of die) No. Net Name Bump Side Top Side X Y X Y 120 VSSC 140.99 1451.99 –140.99 1451.99 121 VSSC 140.99 1651.99 –140.99 1651.99 122 VSSC 140.99 2052.00 –140.99 2052.00 123 PACKAGEOPTION_4 140.99 2352.00 –140.99 2352.00 124 BT_VSSC 768.37 –1186.86 –768.37 –1186.86 125 BT_VSSC 816.40 21.84 –816.40 21.84 126 BT_VSSC 599.69 –715.49 –599.69 –715.49 127 VDDC 338.89 443.99 –338.89 443.99 128 VDDC 338.89 643.99 –338.89 643.99 129 VDDC 338.89 1843.97 –338.89 1843.97 130 VSSC –459.00 851.99 459.00 851.99 131 PACKAGEOPTION_2 440.99 2352.00 –440.99 2352.00 132 PACKAGEOPTION_3 440.99 2592.00 –440.99 2592.00 133 BT_VSSC 468.37 –1186.86 –468.37 –1186.86 134 VDDC 538.88 643.99 –538.88 643.99 135 VDDC 538.88 843.98 –538.88 843.98 136 VDDC 538.88 1043.98 –538.88 1043.98 137 VDDC 538.88 1243.98 –538.88 1243.98 138 VDDC 538.88 1443.98 –538.88 1443.98 139 VDDC 538.88 1643.98 –538.88 1643.98 140 VDDC 538.88 1843.97 –538.88 1843.97 141 BT_VDDC_ISO_1 601.19 –970.04 –601.19 –970.04 142 BT_VDDC_ISO_2 620.91 –500.07 –620.91 –500.07 143 AVDD_BBPLL 655.50 168.14 –655.50 168.14 144 AVSS_BBPLL 655.50 437.48 –655.50 437.48 145 BT_VDDC 1480.37 555.67 –1480.37 555.67 146 PACKAGEOPTION_1 740.99 2592.00 –740.99 2592.00 147 BT_VDDC 1480.37 780.66 –1480.37 780.66 148 BT_VDDIO 830.29 –445.06 –830.29 –445.06 149 BT_VDDIO 840.29 –724.53 –840.29 –724.53 150 BT_VDDIO 865.28 –245.06 –865.28 –245.06 151 BT_VDDIO 915.28 –973.39 –915.28 –973.39 152 PACKAGEOPTION_0 1040.99 2592.00 –1040.99 2592.00 153 BT_GPIO_5 1048.37 420.67 –1048.37 420.67 154 BT_GPIO_3 1048.37 620.67 –1048.37 620.67 155 BT_GPIO_2 1048.37 820.67 –1048.37 820.67 156 BT_I2S_DI 1444.06 1426.01 –1444.06 1426.01 157 BT_UART_TXD 1444.06 1643.00 –1444.06 1643.00 158 BT_I2S_WS 1143.51 1940.00 –1143.51 1940.00 159 LPO_IN 1143.51 2237.00 –1143.51 2237.00 Document Number: 002-20538 Rev. *B Page 63 of 144 ADVANCE CYW4356/CG8674 Table 21. 395-Bump WLCSP Coordinates (Cont.) Coordinates (0,0 center of die) No. Net Name Bump Side Top Side X Y X Y 160 OTP_VDD33 1348.51 2444.00 –1348.51 2444.00 161 BT_CLK_REQ 1644.06 1426.01 –1644.06 1426.01 162 BT_UART_RXD 1644.06 1643.00 –1644.06 1643.00 163 BT_PCM_SYNC 1343.51 1940.00 –1343.51 1940.00 164 BT_USB_DN 1343.51 2237.00 –1343.51 2237.00 165 PCIE_PME_L 1548.50 2444.00 –1548.50 2444.00 166 BT_TM1 1844.06 1346.00 –1844.06 1346.00 167 BT_I2S_CLK 1844.06 1643.00 –1844.06 1643.00 168 BT_GPIO_4 1543.51 1940.00 –1543.51 1940.00 169 BT_USB_DP 1543.51 2237.00 –1543.51 2237.00 170 BT_HOST_WAKE 2044.05 1346.00 –2044.05 1346.00 171 BT_I2S_DO 2044.05 1643.00 –2044.05 1643.00 172 BT_UART_CTS_N 1743.51 1940.00 –1743.51 1940.00 173 BT_PCM_IN 1743.51 2237.00 –1743.51 2237.00 174 PCIE_CLKREQ_L 1858.50 2534.00 –1858.50 2534.00 175 RF_SW_CTRL_1 –2002.32 –1494.00 2002.32 –1494.00 176 BT_DEV_WAKE 2244.05 1346.00 –2244.05 1346.00 177 BT_PCM_OUT 2244.05 1643.00 –2244.05 1643.00 178 BT_UART_RTS_N 1943.51 1940.00 –1943.51 1940.00 179 BT_PCM_CLK 1943.51 2237.00 –1943.51 2237.00 180 PERST_L 2058.50 2534.00 –2058.50 2534.00 181 RF_SW_CTRL_8 –1945.91 –806.00 1945.91 –806.00 182 GPIO_13 –2040.71 516.01 2040.71 516.01 183 RF_SW_CTRL_5 –1872.11 –1125.00 1872.11 –1125.00 184 RF_SW_CTRL_12 –1760.12 –327.01 1760.12 –327.01 185 GPIO_10 –1959.30 229.01 1959.30 229.01 186 RF_SW_CTRL_2 –1802.31 –1494.00 1802.31 –1494.00 187 RF_SW_CTRL_9 –1745.90 –806.00 1745.90 –806.00 188 GPIO_14 –1840.71 516.01 1840.71 516.01 189 GPIO_7 –1853.50 –18.00 1853.50 –18.00 190 RF_SW_CTRL_6 –1672.10 –1125.00 1672.10 –1125.00 191 RF_SW_CTRL_13 –1560.11 –327.01 1560.11 –327.01 192 GPIO_11 –1759.91 279.00 1759.91 279.00 193 RF_SW_CTRL_3 –1602.31 –1494.00 1602.31 –1494.00 194 RF_SW_CTRL_10 –1545.89 –806.00 1545.89 –806.00 195 GPIO_15 –1640.70 516.01 1640.70 516.01 196 GPIO_8 –1593.91 22.00 1593.91 22.00 197 RF_SW_CTRL_7 –1472.09 –1125.00 1472.09 –1125.00 198 RF_SW_CTRL_14 –1360.11 –327.01 1360.11 –327.01 199 GPIO_12 –1559.91 279.00 1559.91 279.00 Document Number: 002-20538 Rev. *B Page 64 of 144 ADVANCE CYW4356/CG8674 Table 21. 395-Bump WLCSP Coordinates (Cont.) Coordinates (0,0 center of die) No. Net Name Bump Side X Top Side Y X Y 200 VSSC –459.00 1151.99 459.00 1151.99 201 VSSC –459.00 1451.99 459.00 1451.99 202 RF_SW_CTRL_11 –1346.09 –756.00 1346.09 –756.00 203 VDDC –459.00 1651.99 459.00 1651.99 204 VDDC –1345.37 1017.54 1345.37 1017.54 205 GPIO_9 –1393.90 22.00 1393.90 22.00 206 VDDIO –1215.90 576.00 1215.90 576.00 207 RF_SW_CTRL_15 –1160.10 –327.01 1160.10 –327.01 208 VDDC –1261.10 1843.97 1261.10 1843.97 209 VDDC –1061.11 –1156.00 1061.11 –1156.00 210 VDDC –1061.11 –776.00 1061.11 –776.00 211 VDDC –1061.10 –1355.99 1061.10 –1355.99 212 VDDC_ISO_PHY –1402.10 –1494.00 1402.10 –1494.00 213 VDDC –1180.10 –587.00 1180.10 –587.00 214 VDDC_ISO_PHY –1151.11 –956.00 1151.11 –956.00 215 VDDC_ISO_DIG –1058.99 2052.00 1058.99 2052.00 216 VDDC_ISO_DIG –816.10 1843.97 816.10 1843.97 217 VSSC –459.00 2052.00 459.00 2052.00 218 GPIO_0 –996.05 2877.58 996.05 2877.58 219 GPIO_1 –996.05 3077.59 996.05 3077.59 220 GPIO_2 –996.05 3277.59 996.05 3277.59 221 GPIO_3 –996.05 3477.60 996.05 3477.60 222 VDDIO –990.90 576.00 990.90 576.00 223 VDDIO_RF –960.10 –117.00 960.10 –117.00 224 VDDC –1061.10 1843.97 1061.10 1843.97 225 VDDC_ISO_PHY –1061.10 843.98 1061.10 843.98 226 VDDC_ISO_PHY –1058.99 1151.99 1058.99 1151.99 227 VDDIO_RF –852.10 –387.00 852.10 –387.00 228 VDDC –461.11 –1355.99 461.11 –1355.99 229 GPIO_4 –769.05 3196.59 769.05 3196.59 230 VDDIO_PCIE –759.00 252.00 759.00 252.00 231 VDDIO –759.00 552.00 759.00 552.00 232 VSSC –1359.90 279.00 1359.90 279.00 233 VSSC –1319.39 2052.00 1319.39 2052.00 234 VSSC –1358.99 2302.00 1358.99 2302.00 235 VSSC –1351.11 –956.00 1351.11 –956.00 236 GPIO_6 –751.05 2996.59 751.05 2996.59 237 GPIO_5 –751.05 3396.60 751.05 3396.60 238 VDDIO_SD –745.50 2352.00 745.50 2352.00 239 JTAG_SEL –733.05 2796.58 733.05 2796.58 Document Number: 002-20538 Rev. *B Page 65 of 144 ADVANCE CYW4356/CG8674 Table 21. 395-Bump WLCSP Coordinates (Cont.) Coordinates (0,0 center of die) No. Net Name Bump Side Top Side X Y X Y 240 VDDC_ISO_PHY –729.00 –220.50 729.00 –220.50 241 VDDC –951.31 –956.00 951.31 –956.00 242 VDDC –861.10 –1355.99 861.10 –1355.99 243 VSSC –1440.90 576.00 1440.90 576.00 244 VSSC –1159.90 –98.00 1159.90 –98.00 245 VSSC –1159.90 279.00 1159.90 279.00 246 VDDC –616.10 1843.97 616.10 1843.97 247 WRF_SYNTH_VBAT_VDD3P3 75.91 –3598.00 –75.91 –3598.00 248 WRF_XTAL_GND1P2 –2003.12 –1834.98 2003.12 –1834.98 249 WRF_XTAL_VDD1P5 –2003.12 –2065.65 2003.12 –2065.65 250 WRF_VCO_GND1P2 251 WRF_XTAL_IN 252 WRF_LOGEN_GND1P2 253 WRF_XTAL_OUT 254 WRF_XTAL_VDD1P2 255 WRF_TX_GND1P2_CORE1 256 WRF_BUCK_GND1P5_CORE1 –2137.36 –2823.85 2137.36 –2823.85 257 WRF_RX5G_GND1P2_CORE1 –1968.14 –2944.01 1968.14 –2944.01 258 WRF_GPIO_OUT_CORE1 –877.08 –2398.01 877.08 –2398.01 259 WRF_RX2G_GND1P2_CORE1 –167.27 –2716.52 167.27 –2716.52 260 WRF_RFIN_5G_CORE1 –2253.44 –3538.14 2253.44 –3538.14 261 WRF_RFIN_2G_CORE1 –201.47 –3598.00 201.47 –3598.00 198.52 –3109.71 –198.52 –3109.71 –2205.82 –2065.65 2205.82 –2065.65 126.11 –2303.63 –126.11 –2303.63 –2205.82 –1818.42 2205.82 –1818.42 –1807.98 –1960.54 1807.98 –1960.54 –437.83 –2417.93 437.83 –2417.93 262 WRF_PFD_VDD1P2 901.40 –2994.96 –901.40 –2994.96 263 WRF_PFD_GND1P2 818.12 –3198.01 –818.12 –3198.01 264 WRF_PADRV_VBAT_VDD3P3_CORE1 –1090.70 –2792.61 1090.70 –2792.61 265 WRF_PADRV_VBAT_GND3P3_CORE1 –1401.46 –2798.01 1401.46 –2798.01 266 WRF_PA5G_VBAT_VDD3P3_CORE1 –1401.46 –3679.00 1401.46 –3679.00 267 WRF_AFE_GND1P2_CORE1 –631.56 –2293.35 631.56 –2293.35 268 WRF_PA5G_VBAT_GND3P3_CORE0 1825.51 –2798.01 –1825.51 –2798.01 269 WRF_PA5G_VBAT_VDD3P3_CORE0 2297.50 –2998.01 –2297.50 –2998.01 270 WRF_MMD_VDD1P2 692.41 –2994.96 –692.41 –2994.96 271 WRF_MMD_GND1P2 499.12 –2798.01 –499.12 –2798.01 272 WRF_PA2G_VBAT_GND3P3_CORE0 1744.51 –1940.22 –1744.51 –1940.22 273 WRF_LNA_5G_GND1P2_CORE0 1877.39 –3673.49 –1877.39 –3673.49 274 WRF_CP_GND1P2 539.26 –3598.00 –539.26 –3598.00 275 WRF_LNA_2G_GND1P2_CORE0 1798.51 –1598.02 –1798.51 –1598.02 276 WRF_TSSI_A_CORE1 –1839.15 –2716.77 1839.15 –2716.77 277 WRF_BUCK_VDD1P5_CORE0 1024.35 –3433.91 –1024.35 –3433.91 278 WRF_LOGENG_GND1P2 770.31 –2353.01 –770.31 –2353.01 279 WRF_RFOUT_2G_CORE1 –601.47 –3679.00 601.47 –3679.00 Document Number: 002-20538 Rev. *B Page 66 of 144 ADVANCE CYW4356/CG8674 Table 21. 395-Bump WLCSP Coordinates (Cont.) Coordinates (0,0 center of die) No. Net Name Bump Side Top Side X Y X Y 280 WRF_RFOUT_5G_CORE0 2288.50 –3198.01 –2288.50 –3198.01 281 WRF_AFE_GND1P2_CORE0 880.13 –2028.11 –880.13 –2028.11 282 WRF_LNA_2G_GND1P2_CORE1 –201.47 –3198.01 201.47 –3198.01 283 WRF_LNA_5G_GND1P2_CORE1 –2276.94 –3276.89 2276.94 –3276.89 284 WRF_PA2G_VBAT_GND3P3_CORE1 –543.68 –3144.01 543.68 –3144.01 285 WRF_PA2G_VBAT_VDD3P3_CORE1 –801.47 –3697.00 801.47 –3697.00 286 WRF_PA5G_VBAT_GND3P3_CORE1 –1801.46 –3225.01 1801.46 –3225.01 287 WRF_PA5G_VBAT_VDD3P3_CORE0 2279.50 –2798.01 –2279.50 –2798.01 288 WRF_PADRV_VBAT_GND3P3_CORE0 1398.51 –2798.01 –1398.51 –2798.01 289 WRF_PADRV_VBAT_VDD3P3_CORE0 1393.11 –2487.25 –1393.11 –2487.25 290 WRF_RFIN_2G_CORE0 2198.50 –1598.02 –2198.50 –1598.02 291 WRF_RX2G_GND1P2_CORE0 1317.02 –1563.82 –1317.02 –1563.82 292 WRF_RX5G_GND1P2_CORE0 1544.51 –3364.69 –1544.51 –3364.69 293 WRF_TX_GND1P2_CORE0 1018.43 –1834.38 –1018.43 –1834.38 294 WRF_TSSI_A_CORE0 1317.27 –3235.69 –1317.27 –3235.69 295 WRF_BUCK_GND1P5_CORE0 1424.35 –3533.90 –1424.35 –3533.90 296 WRF_BUCK_VDD1P5_CORE1 –2237.36 –2423.85 2237.36 –2423.85 297 WRF_GPIO_OUT_CORE0 998.51 –2273.63 –998.51 –2273.63 298 WRF_RFOUT_2G_CORE0 2279.50 –1998.02 –2279.50 –1998.02 299 WRF_RFOUT_5G_CORE1 –1801.46 –3688.00 1801.46 –3688.00 300 WRF_PA2G_VBAT_GND3P3_CORE0 1714.63 –2523.25 –1714.63 –2523.25 301 WRF_PA2G_VBAT_GND3P3_CORE1 –1126.70 –3114.13 1126.70 –3114.13 302 WRF_RFIN_5G_CORE0 2138.64 –3649.99 –2138.64 –3649.99 303 WRF_PA5G_VBAT_GND3P3_CORE0 1825.51 –3198.01 –1825.51 –3198.01 304 WRF_PA5G_VBAT_GND3P3_CORE1 –1401.46 –3225.01 1401.46 –3225.01 305 WRF_PA2G_VBAT_VDD3P3_CORE0 2279.50 –2398.01 –2279.50 –2398.01 306 WRF_PA2G_VBAT_VDD3P3_CORE0 2297.50 –2198.02 –2297.50 –2198.02 307 WRF_RX2G_GND1P2_CORE0 1488.79 –1700.51 –1488.79 –1700.51 308 WRF_BUCK_VDD1P5_CORE0 1024.35 –3633.90 –1024.35 –3633.90 309 WRF_BUCK_VDD1P5_CORE0 1224.35 –3633.90 –1224.35 –3633.90 310 WRF_BUCK_VDD1P5_CORE0 1224.35 –3433.91 –1224.35 –3433.91 311 WRF_BUCK_VDD1P5_CORE1 –2037.36 –2423.85 2037.36 –2423.85 312 WRF_BUCK_VDD1P5_CORE1 –2037.36 –2623.85 2037.36 –2623.85 313 WRF_BUCK_VDD1P5_CORE1 –2237.36 –2623.85 2237.36 –2623.85 314 WRF_PA5G_VBAT_VDD3P3_CORE1 –1601.46 –3697.00 1601.46 –3697.00 315 WRF_PA2G_VBAT_VDD3P3_CORE1 –1001.47 –3679.00 1001.47 –3679.00 316 WRF_LOGEN_GND1P2 317 WRF_RX2G_GND1P2_CORE1 318 WRF_CP_GND1P2 319 WL_REG_ON Document Number: 002-20538 Rev. *B 326.11 –2303.63 –326.11 –2303.63 –303.96 –2888.29 303.96 –2888.29 339.26 –3598.00 –339.26 –3598.00 –1710.77 3277.01 1710.77 3277.01 Page 67 of 144 ADVANCE CYW4356/CG8674 Table 21. 395-Bump WLCSP Coordinates (Cont.) Coordinates (0,0 center of die) No. Net Name Bump Side Top Side X Y X Y 320 BT_REG_ON –1569.35 1721.37 1569.35 1721.37 321 LDO_VDDBAT5V –1852.20 1721.37 1852.20 1721.37 322 LDO_VDDBAT5V –1852.20 1438.53 1852.20 1438.53 323 LDO_VDDBAT5V –1852.20 1155.69 1852.20 1155.69 324 VOUT_3P3 –1993.62 1297.11 1993.62 1297.11 325 VOUT_3P3 –2135.04 1155.69 2135.04 1155.69 326 VDDIO_PMU –1710.77 1297.11 1710.77 1297.11 327 LDO_VDDBAT5V –1852.20 872.84 1852.20 872.84 328 LDO_VDDBAT5V –2135.04 872.84 2135.04 872.84 329 LDO_VDDBAT5V –2276.46 1014.26 2276.46 1014.26 330 VOUT_3P3_SENSE –2276.46 1297.11 2276.46 1297.11 331 LDO_VDDBAT5V –1710.77 1862.79 1710.77 1862.79 332 VOUT_3P3 –1993.62 1579.95 1993.62 1579.95 333 VSSC –1569.35 1155.69 1569.35 1155.69 334 VSSC –1569.35 1438.53 1569.35 1438.53 335 PMU_AVSS –1569.35 2287.06 1569.35 2287.06 336 SR_VLX –1569.35 2852.74 1569.35 2852.74 337 SR_VLX –1569.35 3135.59 1569.35 3135.59 338 SR_PVSS –1852.20 3135.59 1852.20 3135.59 339 SR_VLX –1852.20 2852.74 1852.20 2852.74 340 SR_VDDBATA5V –1852.20 2569.90 1852.20 2569.90 341 VOUT_CLDO –1852.20 2287.06 1852.20 2287.06 342 LDO_VDD1P5 –1852.20 2004.21 1852.20 2004.21 343 LDO_VDDBAT5V –1993.62 1014.26 1993.62 1014.26 344 VOUT_3P3 –2135.04 1438.53 2135.04 1438.53 345 LDO_VDDBAT5V –2135.04 1721.37 2135.04 1721.37 346 VOUT_LDO3P3_B –2135.04 2004.21 2135.04 2004.21 347 LDO_VDD1P5 –2135.04 2287.06 2135.04 2287.06 348 SR_VDDBATP5V –2135.04 2569.90 2135.04 2569.90 349 SR_PVSS –2135.04 3135.59 2135.04 3135.59 350 VDDIO_PMU –1710.77 1579.95 1710.77 1579.95 351 VOUT_LNLDO –1710.77 2145.64 1710.77 2145.64 352 VOUT_CLDO –1710.77 2428.48 1710.77 2428.48 353 SR_VLX –1710.77 2711.32 1710.77 2711.32 354 SR_VLX –1710.77 2994.17 1710.77 2994.17 355 VOUT_LDO3P3_B –1993.62 1862.79 1993.62 1862.79 356 LDO_VDD1P5 –1993.62 2145.64 1993.62 2145.64 357 VOUT_CLDO –1993.62 2428.48 1993.62 2428.48 358 SR_VDDBATP5V –1993.62 2711.32 1993.62 2711.32 359 SR_VLX –1993.62 2994.17 1993.62 2994.17 Document Number: 002-20538 Rev. *B Page 68 of 144 ADVANCE CYW4356/CG8674 Table 21. 395-Bump WLCSP Coordinates (Cont.) Coordinates (0,0 center of die) No. Net Name Bump Side Top Side X Y X Y 360 SR_PVSS –1993.62 3277.01 1993.62 3277.01 361 VOUT_3P3 –2276.46 1862.79 2276.46 1862.79 362 VOUT_BTLDO2P5 –2276.46 2145.64 2276.46 2145.64 363 LDO_VDD1P5 –2276.46 2428.48 2276.46 2428.48 364 SR_PVSS –2276.46 3277.01 2276.46 3277.01 365 VOUT_3P3 –2276.46 1579.95 2276.46 1579.95 366 SR_VDDBATP5V –2276.46 2711.32 2276.46 2711.32 367 PCIE_TESTP 1800.31 3068.53 –1800.31 3068.53 368 PCIE_TESTN 1966.81 2956.03 –1966.81 2956.03 369 BT_VDDC 1480.37 1005.66 –1480.37 1005.66 370 BT_VDDC 1480.37 1225.66 –1480.37 1225.66 371 BT_VDDC 1408.19 248.05 –1408.19 248.05 372 BT_VDDC 1322.34 55.02 –1322.34 55.02 373 BT_VDDC 1060.28 –1186.86 –1060.28 –1186.86 374 BT_VDDC 666.40 –198.15 –666.40 –198.15 375 BT_VDDC 617.61 –1324.61 –617.61 –1324.61 376 BT_VSSC 338.89 –475.07 –338.89 –475.07 377 BT_VSSC 1040.28 –724.53 –1040.28 –724.53 378 BT_VSSC 1063.38 1020.66 –1063.38 1020.66 379 BT_VSSC 1063.38 1320.66 –1063.38 1320.66 380 BT_VSSC 1273.37 505.67 –1273.37 505.67 381 BT_VSSC 1273.37 705.66 –1273.37 705.66 382 BT_VSSC 1273.37 1005.66 –1273.37 1005.66 383 BT_VSSC 1273.37 1225.66 –1273.37 1225.66 384 VSSC 440.99 2052.00 –440.99 2052.00 385 VSSC –1293.24 –1317.60 1293.24 –1317.60 386 VSSC –1202.10 –1504.00 1202.10 –1504.00 387 VSSC –1058.99 1451.99 1058.99 1451.99 388 VSSC –1058.99 2302.00 1058.99 2302.00 389 VSSC –959.90 279.00 959.90 279.00 390 VSSC –759.00 851.99 759.00 851.99 391 VSSC –759.00 1151.99 759.00 1151.99 392 VSSC –759.00 1451.99 759.00 1451.99 393 VSSC –759.00 2052.00 759.00 2052.00 394 VSSC –746.31 –956.00 746.31 –956.00 395 VSSC –746.31 –756.00 746.31 –756.00 Document Number: 002-20538 Rev. *B Page 69 of 144 ADVANCE CYW4356/CG8674 11.3 Signal Descriptions The signal name, type, and description of each pin in the CYW4356/CG8674 is listed in Table 22 and Table 23. The symbols shown under Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any. Table 22. WLCSP Signal Descriptions Bump# Signal Name Type Description WLAN and Bluetooth Receive RF Signal Interface 290 WRF_RFIN_2G_CORE0 I 2.4 GHz Bluetooth and WLAN CORE0 receiver shared input 261 WRF_RFIN_2G_CORE1 I 2.4 GHz Bluetooth and WLAN CORE1 receiver shared input 302 WRF_RFIN_5G_CORE0 I 5 GHz WLAN CORE0 receiver input 260 WRF_RFIN_5G_CORE1 I 5 GHz WLAN CORE1 receiver input 298 WRF_RFOUT_2G_CORE0 O 2.4 GHz WLAN CORE0 PA output 279 WRF_RFOUT_2G_CORE1 O 2.4 GHz WLAN CORE1 PA output 280 WRF_RFOUT_5G_CORE0 O 5 GHz WLAN CORE0 PA output 299 WRF_RFOUT_5G_CORE1 O 5 GHz WLAN CORE1 PA output 294 WRF_TSSI_A_CORE0 I 5 GHz TSSI CORE0 input from an optional external power amplifier/power detector. 276 WRF_TSSI_A_CORE1 I 5 GHz TSSI CORE1 input from an optional external power amplifier/power detector. 297 WRF_GPIO_OUT_CORE0 I/O GPIO or 2.4 GHz TSSI CORE0 input from an optional external power amplifier/power detector 258 WRF_GPIO_OUT_CORE1 I/O GPIO or 2.4 GHz TSSI CORE1 input from an optional external power amplifier/power detector Programmable RF switch control lines. The control lines are programmable via the driver and NVRAM file. RF Switch Control Lines 66 RF_SW_CTRL_0 O 175 RF_SW_CTRL_1 O 186 RF_SW_CTRL_2 O 193 RF_SW_CTRL_3 O 86 RF_SW_CTRL_4 O 183 RF_SW_CTRL_5 O 190 RF_SW_CTRL_6 O 197 RF_SW_CTRL_7 O 181 RF_SW_CTRL_8 O 187 RF_SW_CTRL_9 O 194 RF_SW_CTRL_10 O 202 RF_SW_CTRL_11 O 184 RF_SW_CTRL_12 O 191 RF_SW_CTRL_13 O 198 RF_SW_CTRL_14 O 207 RF_SW_CTRL_15 O Document Number: 002-20538 Rev. *B Page 70 of 144 ADVANCE CYW4356/CG8674 Table 22. WLCSP Signal Descriptions (Cont.) Bump# Signal Name Type Description OD PCIe clock request signal which indicates when the REFCLK to the PCIe interface can be gated. 1 = the clock can be gated 0 = the clock is required I (PU) PCIe System Reset. This input is the PCIe reset as defined in the PCIe base specification version 1.1. WLAN PCI Express Interface 174 PCIE_CLKREQ_L 180 PCIE_PERST_L 9 PCIE_RDN0 I 8 PCIE_RDP0 I 4 PCIE_REFCLKN I 3 PCIE_REFCLKP I 5 PCIE_TDN0 O 6 PCIE_TDP0 O 165 PCIE_PME_L OD 367 PCIE_TESTP – 368 PCIE_TESTN – Receiver differential pair (×1 lane) PCIE Differential Clock inputs (negative and positive). 100 MHz differential. Transmitter differential pair (×1 lane) PCI power management event output. Used to request a change in the device or system power state. The assertion and deassertion of this signal is asynchronous to the PCIe reference clock. This signal has an open-drain output structure, as per the PCI Bus Local Bus Specification, revision 2.3. PCIe test pin WLAN SDIO Bus Interface These signals can support alternate functionality depending on package and host interface mode. See Table 27. 78 SDIO_CLK I 81 SDIO_CMD I/O SDIO command line 82 SDIO_DATA_0 I/O SDIO data line 0 77 SDIO_DATA_1 I/O SDIO data line 1 80 SDIO_DATA_2 I/O SDIO data line 2 79 SDIO_DATA_3 I/O SDIO data line 3 Document Number: 002-20538 Rev. *B SDIO clock input Page 71 of 144 ADVANCE CYW4356/CG8674 Table 22. WLCSP Signal Descriptions (Cont.) Bump# Signal Name Type Description WLAN GPIO Interface The GPIO signals can be multiplexed via software and the JTAG_SEL pin to support other functions. See Table 24 and Table 27 for additional details. 218 GPIO_0 I/O Programmable GPIO pins 219 GPIO_1 I/O 220 GPIO_2 I/O 221 GPIO_3 I/O 229 GPIO_4 I/O 237 GPIO_5 I/O 236 GPIO_6 I/O 189 GPIO_7 I/O 196 GPIO_8 I/O 205 GPIO_9 I/O 185 GPIO_10 I/O 192 GPIO_11 I/O 199 GPIO_12 I/O 182 GPIO_13 I/O 188 GPIO_14 I/O 195 GPIO_15 I/O 239 JTAG_SEL I/O 251 WRF_XTAL_IN I XTAL oscillator input 253 WRF_XTAL_OUT O XTAL oscillator output 159 LPO_IN I External sleep clock input (32.768 kHz) 161 CLK_REQ O Reference clock request (shared by BT and WLAN). If not used, this can be no-connect. JTAG Interface JTAG select: pull high to select the JTAG interface. If the JTAG interface is not used this pin may be left floating or connected to ground. Note: See Table 27 for the JTAG signal pins. Clocks Bluetooth/FM Transceivera 49 BT_RF O Bluetooth PA output 61 FM_RFIN I FM radio antenna port 60 FM_RFAUX I FM radio auxiliary antenna port 54 FM_AOUT1 O FM DAC output 1 55 FM_AOUT2 O FM DAC output 2 179 BT_PCM_CLK I/O PCM clock; can be master (output) or slave (input) 173 BT_PCM_IN Bluetooth PCM I PCM data input 177 BT_PCM_OUT O PCM data output 163 BT_PCM_SYNC I/O PCM sync; can be master (output) or slave (input). Document Number: 002-20538 Rev. *B Page 72 of 144 ADVANCE CYW4356/CG8674 Table 22. WLCSP Signal Descriptions (Cont.) Bump# Signal Name Type Description Bluetooth USB Interface 164 BT_USB_DN I/O USB (Host) data negative. Negative terminal of the USB transceiver. 169 BT_USB_DP I/O USB (Host) data positive. Positive terminal of the USB transceiver. Bluetooth UART 172 BT_UART_CTS_L I UART clear-to-send. Active-low clear-to-send signal for the HCI UART interface. 178 BT_UART_RTS_L O UART request-to-send. Active-low request-tosend signal for the HCI UART interface. BT LED control pin. 162 BT_UART_RXD I UART serial input. Serial data input for the HCI UART interface. 157 BT_UART_TXD O UART serial output. Serial data output for the HCI UART interface. 167 BT_I2S_CLK I/O I2S clock, can be master (output) or slave (input). 171 BT_I2S_DO I/O I2S data output 156 BT_I2S_DI I/O I2S data input 158 BT_I2S_WS I/O I2S WS; can be master (output) or slave (input). 155 BT_GPIO_2 I/O Bluetooth general-purpose I/O 154 BT_GPIO_3 I/O Bluetooth general-purpose I/O 168 BT_GPIO_4 I/O Bluetooth general-purpose I/O 153 BT_GPIO_5 I/O Bluetooth general-purpose I/O Bluetooth/FM I2S Bluetooth GPIOs Miscellaneous 319 WL_REG_ON I Used by PMU to power up or power down the internal CYW4356/CG8674 regulators used by the WLAN section. Also, when deasserted, this pin holds the WLAN section in reset. This pin has an internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming. 320 BT_REG_ON I Used by PMU to power up or power down the internal CYW4356/CG8674 regulators used by the Bluetooth section. Also, when deasserted, this pin holds the Bluetooth section in reset. This pin has an internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming. 176 BT_DEV_WAKE I/O Bluetooth DEV_WAKE 170 BT_HOST_WAKE I/O Bluetooth HOST_WAKE NC NC Do not connect these pins to anything. Leave them floating. 12–29, 99–101, 31, 33, 35, 38 Document Number: 002-20538 Rev. *B Page 73 of 144 ADVANCE CYW4356/CG8674 Table 22. WLCSP Signal Descriptions (Cont.) Bump# Signal Name Type Description Integrated Voltage Regulators 340 SR_VDDBATA5V I Quiet VBAT 348 SR_VDDBATP5V I Power VBAT 336 SR_VLX O Cbuck switching regulator output. Refer to Table 43 for details of the inductor and capacitor required on this output. 342 LDO_VDD1P5 I LNLDO input 327 LDO_VDDBAT5V I LDO VBAT. 249 WRF_XTAL_VDD1P5 I XTAL LDO input (1.35V) 254 WRF_XTAL_VDD1P2 O XTAL LDO output (1.2V) 351 VOUT_LNLDO O Output of LNLDO 341 VOUT_CLDO O Output of core LDO 362 VOUT_BTLDO2P5 O Output of BT LDO 346 VOUT_LDO3P3_B O Output of 3.3V LDO 324 VOUT_3P3 O LDO 3.3V output 330 VOUT_3P3_SENSE O Voltage sense pin for LDO 3.3V output Bluetooth Supplies 46 BT_PAVDD2P5 PWR Bluetooth PA power supply 44 BT_LNAVDD1P2 PWR Bluetooth LNA power supply 42 BT_IFVDD1P2 PWR Bluetooth IF block power supply 47 BT_PLLVDD1P2 PWR Bluetooth RF PLL power supply 50 BT_VCOVDD1P2 PWR Bluetooth RF power supply BT_VDDIO PWR Core supply 148, 149, 150,151 FM Transceiver Supplies a – FM_LNAVCOVDD1P2 PWR FM LNA and VCO 1.2V power supply 62 FM_LNAVDD1P2 PWR FM LNA 1.2V power supply 64 FM_VCOVDD1P2 PWR FM VCO 1.2V power supply 59 FM_PLLVDD1P2 PWR FM PLL 1.2V power supply 52 FM_AUDIOVDD1P2 PWR FM AUDIO power supply Document Number: 002-20538 Rev. *B Page 74 of 144 ADVANCE CYW4356/CG8674 Table 22. WLCSP Signal Descriptions (Cont.) Bump# Signal Name Type Description WLAN Supplies 277 WRF_BUCK_VDD1P5_CORE0 PWR Internal capacitor-less CORE0 LDO supply 296 WRF_BUCK_VDD1P5_CORE1 PWR Internal capacitor-less CORE1 LDO supply 262 WRF_SYNTH_VBAT_VDD3P3 PWR Synth VDD 3.3V supply 289 WRF_PADRV_VBAT_VDD3P3_CORE0 PWR CORE0 PA Driver VBAT supply 264 WRF_PADRV_VBAT_VDD3P3_CORE1 PWR CORE1 PA Driver VBAT supply 269 WRF_PA5G_VBAT_VDD3P3_CORE0 PWR 5 GHz CORE0 PA 3.3V VBAT supply 266 WRF_PA5G_VBAT_VDD3P3_CORE1 PWR 5 GHz CORE1 PA 3.3V VBAT supply 305 WRF_PA2G_VBAT_VDD3P3_CORE0 PWR 2 GHz CORE0 PA 3.3V VBAT supply 285 WRF_PA2G_VBAT_VDD3P3_CORE1 PWR 2 GHz CORE1 PA 3.3V VBAT supply 270 WRF_MMD_VDD1P2 PWR 1.2V supply 262 WRF_PFD_VDD1P2 PWR 1.2V supply OTP_VDD33 PWR OTP 3.3V supply 67, 74, 87, 103, 107–115, 127–129, 134–140, 203, 204, 208–211, 213, 224, 228, 241, 242, 246 VDDC PWR 1.2V core supply for WLAN 206, 222, 231 VDDIO PWR 1.8V–3.3V supply for WLAN. Must be directly connected to PMU_VDDIO and BT_VDDIO on the PCB. PWR 1.2V core supply for BT Miscellaneous Supplies 160 145, 147, 369– 375, BT_VDDC 326 VDDIO_PMU PWR 1.8V–3.3V supply for PMU controls. Must be directly connected to VDDIO and BT_VDDIO on the PCB. 76 VDDIO_SD PWR 1.8V–3.3V supply for SDIO pads and PCIe outof-band signals. 223 VDDIO_RF PWR IO supply for RF switch control pads (3.3V). 98 VDDC_98 PWR 1.2V supply from VOUT_CLDO (341, 352, 357). 102 VDDC_102 PWR 1.2V supply from VOUT_CLDO (341, 352, 357). 143 AVDD_BBPLL PWR Baseband PLL supply. 11 PCIE_PLL_AVDD1P2 PWR 1.2V supply for PCIe PLL. (This pin should be left unconnected (NC) for SDIO operation.) 7 PCIE_RXTX_AVDD1P2 PWR 1.2V supply for PCIE TX and RX. (This pin should be left unconnected (NC) for SDIO operation.) 230 VDDIO_PCIE PWR Supply the same voltage to this pin as that used for the PCIE out-of-band signals (that is, PCIE_PME_L). 250 WRF_VCO_GND1P2 GND VCO/LOGEN ground 281 WRF_AFE_GND1P2_CORE0 GND CORE0 AFE ground 267 WRF_AFE_GND1P2_CORE1 GND CORE1 AFE ground 295 WRF_BUCK_GND1P5_CORE0 GND Internal capacitor-less CORE0 LDO ground Ground Document Number: 002-20538 Rev. *B Page 75 of 144 ADVANCE CYW4356/CG8674 Table 22. WLCSP Signal Descriptions (Cont.) Bump# Signal Name Type Description 256 WRF_BUCK_GND1P5_CORE1 GND Internal capacitor-less CORE1 LDO ground 275 WRF_LNA_2G_GND1P2_CORE0 GND 2 GHz internal CORE0 LNA ground 282 WRF_LNA_2G_GND1P2_CORE1 GND 2 GHz internal CORE1 LNA ground 273 WRF_LNA_5G_GND1P2_CORE0 GND 5 GHz internal CORE0 LNA ground 283 WRF_LNA_5G_GND1P2_CORE1 GND 5 GHz internal CORE1 LNA ground 293 WRF_TX_GND1P2_CORE0 GND TX CORE0 ground 255 WRF_TX_GND1P2_CORE1 GND TX CORE1 ground 288 WRF_PADRV_VBAT_GND3P3_CORE0 GND PAD CORE0 ground 265 WRF_PADRV_VBAT_GND3P3_CORE1 GND PAD CORE1 ground 248 WRF_XTAL_GND1P2 GND XTAL ground 291, 307 WRF_RX2G_GND1P2_CORE0 GND RX 2GHz CORE0 ground 259, 317 WRF_RX2G_GND1P2_CORE1 GND RX 2GHz CORE1 ground 292 WRF_RX5G_GND1P2_CORE0 GND RX 5GHz CORE0 ground 257 WRF_RX5G_GND1P2_CORE1 GND RX 5GHz CORE1 ground WRF_LOGEN_GND1P2 GND LOGEN ground WRF_LOGENG_GND1P2 GND LOGEN ground 268, 030 WRF_PA5G_VBAT_GND3P3_CORE0 GND 5 GHz PA CORE0 ground 286, 304 WRF_PA5G_VBAT_GND3P3_CORE1 GND 5 GHz PA CORE1 ground 272, 300 WRF_PA2G_VBAT_GND3P3_CORE0 GND 2 GHz PA CORE0 ground 284, 301 WRF_PA2G_VBAT_GND3P3_CORE1 GND 2 GHz PA CORE1 ground 252, 316 278 271 WRF_MMD_GND1P2 GND Ground WRF_CP_GND1P2 GND Ground WRF_PFD_GND1P2 GND Ground 68–73, 75,83–85, 88–95, 104–106, 116–122, 130, 200, 201, 217, 232–235, 254–245, 333, 334, 384–395 VSSC GND Core ground for WLAN and BT 338, 349, 360, 364 SR_PVSS GND Power ground 274, 318 263 335 PMU_AVSS 30, 32, 34, 36, 37, 39, GND 96, 97 GND Quiet ground GND – 40 BT_PAVSS GND Bluetooth PA ground 43 BT_IFVSS GND Bluetooth IF block ground 48 BT_PLLVSS GND Bluetooth PLL ground 51 BT_VCOVSS GND Bluetooth VCO ground 65 FM_VCOVSS GND FM VCO ground 63 FM_LNAVSS GND FM LNA ground 58 FM_PLLVSS GND FM PLL ground 53 FM_AUDIOVSS GND FM AUDIO ground 144 AVSS_BBPLL GND Baseband PLL ground Document Number: 002-20538 Rev. *B Page 76 of 144 ADVANCE CYW4356/CG8674 Table 22. WLCSP Signal Descriptions (Cont.) Bump# Signal Name Type Description 10 PCIE_AVSS GND PCIe ground 1 PCIE_RXTX_AVSS GND PCIe ground 2 PCIE_PLL_AVSS GND PCIe ground RGND GND Ground BTRGND GND Ground 17, 18, 23, 26 – a. Note: Cypress does not support FM on CYW4356/CG8674 Table 23. WLBGA Signal Descriptions Ball# Signal Name Type Description WLAN and Bluetooth Receive RF Signal Interface N1 WRF_RFIN_2G_CORE0 I 2.4 GHz Bluetooth and WLAN CORE0 receiver shared input V7 WRF_RFIN_2G_CORE1 I 2.4 GHz Bluetooth and WLAN CORE1 receiver shared input V1 WRF_RFIN_5G_CORE0 I 5 GHz WLAN CORE0 receiver input V12 WRF_RFIN_5G_CORE1 I 5 GHz WLAN CORE1 receiver input P1 WRF_RFOUT_2G_CORE0 O 2.4 GHz WLAN CORE0 PA output V8 WRF_RFOUT_2G_CORE1 O 2.4 GHz WLAN CORE1 PA output U1 WRF_RFOUT_5G_CORE0 O 5 GHz WLAN CORE0 PA output V11 WRF_RFOUT_5G_CORE1 O 5 GHz WLAN CORE1 PA output U3 WRF_TSSI_A_CORE0 I 5 GHz TSSI CORE0 input from an optional external power amplifier/power detector. T11 WRF_TSSI_A_CORE1 I 5 GHz TSSI CORE1 input from an optional external power amplifier/power detector. R4 WRF_GPIO_OUT_CORE0 I/O GPIO or 2.4 GHz TSSI CORE0 input from an optional external power amplifier/power detector R9 WRF_GPIO_OUT_CORE1 I/O GPIO or 2.4 GHz TSSI CORE1 input from an optional external power amplifier/power detector Document Number: 002-20538 Rev. *B Page 77 of 144 ADVANCE CYW4356/CG8674 Table 23. WLBGA Signal Descriptions (Cont.) Ball# Signal Name Type Description RF Switch Control Lines R7 RF_SW_CTRL_0 N8 RF_SW_CTRL_1 O O P9 RF_SW_CTRL_2 O N7 RF_SW_CTRL_3 O N5 RF_SW_CTRL_4 O P7 RF_SW_CTRL_5 O P5 RF_SW_CTRL_6 O M8 RF_SW_CTRL_7 O K12 RF_SW_CTRL_8 O J11 RF_SW_CTRL_9 O M12 RF_SW_CTRL_10 O L9 RF_SW_CTRL_11 O J9 RF_SW_CTRL_12 O K10 RF_SW_CTRL_13 O M10 RF_SW_CTRL_14 O L8 RF_SW_CTRL_15 O Programmable RF switch control lines. The control lines are programmable via the driver and NVRAM file. WLAN PCI Express Interface D5 PCIE_CLKREQ_L C4 PCIE_PERST_L B1 PCIE_RDN0 OD PCIe clock request signal which indicates when the REFCLK to the PCIe interface can be gated. 1 = the clock can be gated 0 = the clock is required I (PU) PCIe System Reset. This input is the PCIe reset as defined in the PCIe base specification version 1.1. I C1 PCIE_RDP0 I A5 PCIE_REFCLKN I A4 PCIE_REFCLKP I A3 PCIE_TDN0 O A2 PCIE_TDP0 C5 PCIE_PME_L OD C3 PCIE_TESTP – C2 PCIE_TESTN – Receiver differential pair (×1 lane) PCIE Differential Clock inputs (negative and positive). 100 MHz differential. Transmitter differential pair (×1 lane) O PCI power management event output. Used to request a change in the device or system power state. The assertion and deassertion of this signal is asynchronous to the PCIe reference clock. This signal has an open-drain output structure, as per the PCI Bus Local Bus Specification, revision 2.3. PCIe test pin WLAN SDIO Bus Interface Note: These signals can support alternate functionality depending on package and host interface mode. See Table 27 for additional details. A8 SDIO_CLK I A9 SDIO_CMD I/O Document Number: 002-20538 Rev. *B SDIO clock input SDIO command line Page 78 of 144 ADVANCE CYW4356/CG8674 Table 23. WLBGA Signal Descriptions (Cont.) Ball# B9 Signal Name SDIO_DATA_0 Type I/O Description SDIO data line 0 C9 SDIO_DATA_1 I/O SDIO data line 1 B8 SDIO_DATA_2 I/O SDIO data line 2 C8 SDIO_DATA_3 I/O SDIO data line 3 WLAN GPIO Interface Note: The GPIO signals can be multiplexed via software and the JTAG_SEL pin to support other functions. See Table 24 and Table 27 for additional details. G11 GPIO_0 I/O F10 GPIO_1 I/O F11 GPIO_2 I/O G9 GPIO_3 I/O H9 GPIO_4 I/O F9 GPIO_5 I/O F8 GPIO_6 I/O E7 GPIO_7 I/O F7 GPIO_8 I/O E6 GPIO_9 I/O Programmable GPIO pins H12 GPIO_10 I/O – GPIO_11 I/O – GPIO_12 I/O – GPIO_13 I/O – GPIO_14 I/O – GPIO_15 I/O D9 JTAG_SEL I/O P12 WRF_XTAL_IN I XTAL oscillator input N12 WRF_XTAL_OUT O XTAL oscillator output JTAG Interface JTAG select: pull high to select the JTAG interface. If the JTAG interface is not used this pin may be left floating or connected to ground. See Table 27 for the JTAG signal pins. Clocks F6 LPO_IN I External sleep clock input (32.768 kHz) F4 CLK_REQ O Reference clock request (shared by BT and WLAN). If not used, this can be no-connect. Bluetooth/FM Transceiver a L1 BT_RF O Bluetooth PA output H1 FM_RFIN I FM radio antenna port – FM_RFAUX I FM radio auxiliary antenna port E1 FM_AOUT1 O FM DAC output 1 F1 FM_AOUT2 O FM DAC output 2 Document Number: 002-20538 Rev. *B Page 79 of 144 ADVANCE CYW4356/CG8674 Table 23. WLBGA Signal Descriptions (Cont.) Ball# Signal Name Type Description Bluetooth PCM M6 BT_PCM_CLK J4 BT_PCM_IN I/O I PCM data input PCM clock; can be master (output) or slave (input) H4 BT_PCM_OUT O PCM data output K6 BT_PCM_SYNC I/O PCM sync; can be master (output) or slave (input). Bluetooth USB Interface E5 BT_USB_DN I/O USB (Host) data negative. Negative terminal of the USB transceiver. F5 BT_USB_DP I/O USB (Host) data positive. Positive terminal of the USB transceiver. Bluetooth UART L5 BT_UART_CTS_L I UART clear-to-send. Active-low clear-to-send signal for the HCI UART interface. K5 BT_UART_RTS_L O UART request-to-send. Active-low request-to-send signal for the HCI UART interface. BT LED control pin. H5 BT_UART_RXD I UART serial input. Serial data input for the HCI UART interface. J5 BT_UART_TXD O UART serial output. Serial data output for the HCI UART interface. J6 BT_I2S_CLK I/O I2S clock, can be master (output) or slave (input). G6 BT_I2S_DO I/O I2S data output G5 BT_I2S_DI I/O I2S data input L6 BT_I2S_WS I/O I2S WS; can be master (output) or slave (input). Bluetooth/FM I2S a Bluetooth GPIO A6 BT_GPIO_2 I/O Bluetooth general-purpose I/O D7 BT_GPIO_3 I/O Bluetooth general-purpose I/O K4 BT_GPIO_4 I/O Bluetooth general-purpose I/O A7 BT_GPIO_5 I/O Bluetooth general-purpose I/O Miscellaneous A10 WL_REG_ON I Used by PMU to power up or power down the internal CYW4356/CG8674 regulators used by the WLAN section. Also, when deasserted, this pin holds the WLAN section in reset. This pin has an internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming. D10 BT_REG_ON I Used by PMU to power up or power down the internal CYW4356/CG8674 regulators used by the Bluetooth/FM section. Also, when deasserted, this pin holds the Bluetooth/FM section in reset. This pin has an internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming. L4 BT_DEV_WAKE I/O Bluetooth DEV_WAKE J3 BT_HOST_WAKE I/O Bluetooth HOST_WAKE Document Number: 002-20538 Rev. *B Page 80 of 144 ADVANCE CYW4356/CG8674 Table 23. WLBGA Signal Descriptions (Cont.) Ball# Signal Name Type Description Integrated Voltage Regulators B11 SR_VDDBATA5V I Quiet VBAT B12 SR_VDDBATP5V I Power VBAT A11 SR_VLX O Cbuck switching regulator output. Refer to Table 43 for details of the inductor and capacitor required on this output. C12 LDO_VDD1P5 I LNLDO input E12 LDO_VDDBAT5V I LDO VBAT. P11 WRF_XTAL_VDD1P5 I XTAL LDO input (1.35V) N10 WRF_XTAL_VDD1P2 O XTAL LDO output (1.2V) D11 VOUT_LNLDO O Output of LNLDO C11 VOUT_CLDO O Output of core LDO D12 VOUT_BTLDO2P5 O Output of BT LDO E11 VOUT_LDO3P3_B O Output of 3.3V LDO F12 VOUT_3P3 O LDO 3.3V output VOUT_3P3_SENSE O Voltage sense pin for LDO 3.3V output – Bluetooth Supplies M1 BT_PAVDD2P5 PWR Bluetooth PA power supply K1 BT_LNAVDD1P2 PWR Bluetooth LNA power supply K3 BT_IFVDD1P2 PWR Bluetooth IF block power supply K2 BT_PLLVDD1P2 PWR Bluetooth RF PLL power supply J1 BT_VCOVDD1P2 PWR Bluetooth RF power supply K7 BT_VDDIO PWR Core supply FM Transceiver Supplies G1 a FM_LNAVCOVDD1P2 PWR FM LNA and VCO 1.2V power supply – FM_LNAVDD1P2 PWR FM LNA 1.2V power supply – FM_VCOVDD1P2 PWR FM VCO 1.2V power supply F3 FM_PLLVDD1P2 PWR FM PLL 1.2V power supply E2 FM_AUDIOVDD1P2 PWR FM AUDIO power supply U4 WRF_BUCK_VDD1P5_CORE0 PWR Internal capacitor-less CORE0 LDO supply R11 WRF_BUCK_VDD1P5_CORE1 PWR Internal capacitor-less CORE1 LDO supply WLAN Supplies V6 WRF_SYNTH_VBAT_VDD3P3 PWR Synth VDD 3.3V supply R3 WRF_PADRV_VBAT_VDD3P3_CORE0 PWR CORE0 PA Driver VBAT supply T9 WRF_PADRV_VBAT_VDD3P3_CORE1 PWR CORE1 PA Driver VBAT supply T1 WRF_PA5G_VBAT_VDD3P3_CORE0 PWR 5 GHz CORE0 PA 3.3V VBAT supply V10 WRF_PA5G_VBAT_VDD3P3_CORE1 PWR 5 GHz CORE1 PA 3.3V VBAT supply R1 WRF_PA2G_VBAT_VDD3P3_CORE0 PWR 2 GHz CORE0 PA 3.3V VBAT supply V9 WRF_PA2G_VBAT_VDD3P3_CORE1 PWR 2 GHz CORE1 PA 3.3V VBAT supply T5 WRF_MMD_VDD1P2 PWR 1.2V supply T4 WRF_PFD_VDD1P2 PWR 1.2V supply Document Number: 002-20538 Rev. *B Page 81 of 144 ADVANCE CYW4356/CG8674 Table 23. WLBGA Signal Descriptions (Cont.) Ball# Signal Name Type Description Miscellaneous Supplies – OTP_VDD33 PWR OTP 3.3V supply PWR 1.2V core supply for WLAN VDDIO PWR 1.8V–3.3V supply for WLAN. Must be directly connected to PMU_VDDIO and BT_VDDIO on the PCB. BT_VDDC PWR 1.2V core supply for BT VDDIO_PMU PWR 1.8V–3.3V supply for PMU controls. Must be directly connected to VDDIO and BT_VDDIO on the PCB. E8 VDDIO_SD PWR 1.8V–3.3V supply for SDIO pads and PCIe out-of-band signals. H11 VDDIO_RF PWR IO supply for RF switch control pads (3.3V) H7 AVDD_BBPLL PWR Baseband PLL supply B3 PCIE_PLL_AVDD1P2 PWR 1.2V supply for PCIe PLL. (This pin should be left unconnected (NC) for SDIO operation.) B2 PCIE_RXTX_AVDD1P2 PWR 1.2V supply for PCIE TX and RX. (This pin should be left unconnected (NC) for SDIO operation.) U6 WRF_VCO_GND1P2 GND VCO/LOGEN ground P4 WRF_AFE_GND1P2_CORE0 GND CORE0 AFE ground R8 WRF_AFE_GND1P2_CORE1 GND CORE1 AFE ground B7, D4, E9, G10, J8, VDDC J12, L10, M7 E10 E4, H3, M5 – Ground V4 WRF_BUCK_GND1P5_CORE0 GND Internal capacitor-less CORE0 LDO ground R12 WRF_BUCK_GND1P5_CORE1 GND Internal capacitor-less CORE1 LDO ground N2 WRF_LNA_2G_GND1P2_CORE0 GND 2 GHz internal CORE0 LNA ground U7 WRF_LNA_2G_GND1P2_CORE1 GND 2 GHz internal CORE1 LNA ground V2 WRF_LNA_5G_GND1P2_CORE0 GND 5 GHz internal CORE0 LNA ground U12 WRF_LNA_5G_GND1P2_CORE1 GND 5 GHz internal CORE1 LNA ground P3 WRF_TX_GND1P2_CORE0 GND TX CORE0 ground T8 WRF_TX_GND1P2_CORE1 GND TX CORE1 ground T3 WRF_PADRV_VBAT_GND3P3_CORE0 GND PAD CORE0 ground T10 WRF_PADRV_VBAT_GND3P3_CORE1 GND PAD CORE1 ground N11 WRF_XTAL_GND1P2 GND XTAL ground N3 WRF_RX2G_GND1P2_CORE0 GND RX 2GHz CORE0 ground T7 WRF_RX2G_GND1P2_CORE1 GND RX 2GHz CORE1 ground V3 WRF_RX5G_GND1P2_CORE0 GND RX 5GHz CORE0 ground T12 WRF_RX5G_GND1P2_CORE1 GND RX 5GHz CORE1 ground R6 WRF_LOGEN_GND1P2 GND LOGEN ground WRF_LOGENG_GND1P2 GND LOGEN ground T2, U2 R5 WRF_PA5G_VBAT_GND3P3_CORE0 GND 5 GHz PA CORE0 ground U10, U11 WRF_PA5G_VBAT_GND3P3_CORE1 GND 5 GHz PA CORE1 ground P2, R2 WRF_PA2G_VBAT_GND3P3_CORE0 GND 2 GHz PA CORE0 ground U8, U9 WRF_PA2G_VBAT_GND3P3_CORE1 GND 2 GHz PA CORE1 ground Document Number: 002-20538 Rev. *B Page 82 of 144 ADVANCE CYW4356/CG8674 Table 23. WLBGA Signal Descriptions (Cont.) Ball# Signal Name Type Description T6 WRF_MMD_GND1P2 GND Ground V5 WRF_CP_GND1P2 GND Ground U5 WRF_PFD_GND1P2 GND Ground GND Core ground for WLAN and BT C10, D3, D6, G4, G8, VSSC G12, L7, L11, M4 A12 SR_PVSS GND Power ground B10 PMU_AVSS GND Quiet ground L2 BT_PAVSS GND Bluetooth PA ground M3 BT_IFVSS GND Bluetooth IF block ground L3 BT_PLLVSS GND Bluetooth PLL ground J2 BT_VCOVSS GND Bluetooth VCO ground a G2 FM_VCOVSS H2 FM_LNAVSS a G3 FM_PLLVSS a a GND FM VCO ground GND FM LNA ground GND FM PLL ground GND FM AUDIO ground F2 FM_AUDIOVSS G7 AVSS_BBPLL GND Baseband PLL ground PCIE_AVSS GND PCIe ground B4 PCIE_RXTX_AVSS GND PCIe ground B5 PCIE_PLL_AVSS GND PCIe ground – RGND GND Ground – BTRGND GND Ground – No Connect B6, C6, C7 NC NC No connect. Leave floating. a. Cypress does not support FM on CYW4356/CG8674. Document Number: 002-20538 Rev. *B Page 83 of 144 ADVANCE CYW4356/CG8674 11.4 WLAN/BT GPIO Signals and Strapping Options The pins listed in Table 24 and Table 25 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to GND, using a 10 kΩ resistor or less. Note: Refer to the reference board schematics for more information. Table 24. WLAN GPIO Functions and Strapping Options Pin Name Default Function Description GPIO_4 0 1: SPROM is present 0: SPROM is absent (default). Applicable in PCIe Host mode. In SDIO Host mode, sdioPadVddio is 3.3V while set to 1, and 1.8V while set to 0. GPIO_[10, 9, 8] [0,0,0] GPIO_12 1 Host interface selection: see Table 26. 1 = HTAvailable (default) 0 = ResourceModeInit is ALPAvailable. On PCBs, use a pull-down and tie to ALP clock mode. Table 25. BT GPIO Functions and Strapping Options Pin Name Default Function BT_GPIO4 0 Description 1: BT Serial Flash is present. 0: BT Serial Flash is absent (default) Table 26. GPIO_[10, 9, 8] Host Interface Selection GPIO_[10, 9, 8] Bit Setting WLAN Host Interface Mode Bluetooth Mode 000 SDIO BTUART or BTUSB; BT tPorts stand-alone. 010 Not used BTUART or BTUSB; BT tPorts stand-alone 011 PCIE BTUART or BTUSB; BT tPorts stand-alone Document Number: 002-20538 Rev. *B Page 84 of 144 ADVANCE CYW4356/CG8674 11.5 GPIO Alternative Signal Functions Note: For all new designs, use GPIO_6 for SECI_IN instead of GPIO_4. For existing designs, GPIO_4 can be still used for SECI_IN provided the strapping requirements discussed in “WLAN/BT GPIO Signals and Strapping Options” are fully satisfied. Table 27. GPIO Alternative Signal Functions Pin Names Test Mode FAST UART SPROM BSC 4 5 Miscellaneous-0 (JTAG_SEL = 1) GCI Miscellaneous-1 Miscellaneous-2 UART 7 8 9 3 PWDOG 10 Function Select 0 2 6 Additional Functionality GPIO_0 TEST_GPIO_0 FAST_UAR T _RX – BSC_CLK – GCI_GPIO_4 SDIO_SEP_I SDIO_SEP_I UART_DBG PWDOG NT NT _TX _GPIO_0 _OD WL_HOST_W AKE GPIO_1 TEST_GPIO_1 FAST_UAR T _TX – BSC _SDA RF_DISABLE_L GCI_GPIO_5 – – UART_DBG PWDOG _RX _GPIO_1 WL_DEV_WA KE GPIO_2 TEST_GPIO_2 FAST_UAR T _CTS_IN – N/A TCK GCI_GPIO_1 – – – – – GPIO_3 TEST_GPIO_3 FAST_UAR T _RTS_OUT – N/A TMS GCI_GPIO_0 – – – – – GPIO_4 TEST_GPIO_4 – – N/A TDI SECI_INa – – UART_DBG _RX – – GPIO_5 TEST_GPIO_5 – – N/A TDO SECI_OUT – – UART_DBG _TX – – GPIO_6 TEST_GPIO_6 – – N/A TRST_L GCI_GPIO_2 SECI_INa – – – – GPIO_7 TEST_GPIO_7 FAST_UAR SPROM_C T S _RTS_OUT BSC_SDA PMU_TEST_ GCI_GO PIO_3 – UART_DBG_TX – PWDOG _GPIO_2 WL_LED (For WLBGA) GPIO_8 TEST_GPIO_8 FAST_UAR SPROM_C T LK _CTS_IN BSC_CLK – – – –– – PWDOG _GPIO_3 – GPIO_9 TEST_GPIO_9 FAST_UAR T _RX – SECI_OUT PALDO_PD – – PWDOG _GPIO_4 – – GCI_GPIO_4 – – – PWDOG _GPIO_5 – GPIO_1 TEST_G0 PIO_10 SPROM_MI PALDO _PU FAST_UAR SPROM_M – T O _TX Document Number: 002-20538 Rev. *B – Page 85 of 146 ADVANCE CYW4356/CG8674 Table 27. GPIO Alternative Signal Functions (Cont.) Pin Names Test Mode FAST UART SPROM BSC 4 5 Miscellaneous-0 (JTAG_SEL = 1) GCI Miscellaneous-1 Miscellaneous-2 UART 7 8 9 3 PWDOG 10 Function Select 0 2 6 Additional Functionality GPIO_11 TEST_GPIO_11 FAST_UAR T_RX – PALDO _PU – GCI_GPIO_5 PALDO_PD – – – – GPIO_1 TEST_G2 PIO_12 FAST_UAR T _TX – – – GCI_GPIO_1 – – – – GPIO_1 TEST_G3 PIO_13 – – – – GCI_GPIO_0 – – – – – GPIO_1 TEST_G4 PIO_14 FAST_UAR T _RTS_OUT – – – GCI_GPIO_2 – – UART_DBG _RX – – GPIO_1 TEST_G5 PIO_15 FAST_UAR T_CTS_IN – – – GCI_GPIO_3 – – UART_DBG _TX – – Note: 1. GPIO_0 and WL_DEV_WAKE signals are selected by using software. 2. SDIO_PADVDDIO = 1 (not in straps table) is set to 3.3V by default for all packages. 3. GPIO_7 can be used as WL_LED in WLBGA package. a. For all new designs, use GPIO_6 for SECI_IN instead of GPIO_4. For existing designs, GPIO_4 can be still used for SECI_IN provided the strapping requirements discussed in “WLAN/ BT GPIO Signals and Strapping Options” are fully satisfied. Table 28 defines status for all CYW4356/CG8674 GPIOs based on the tristate test mode. Table 28. GPIO Status Vs. Test Modes Test Mode TRISTATE_IND Function Select 12 Status for All GPIOs Input disable TRISTATE_PDN 13 Pull down TRISTATE_PUP 14 Pull up TRISTATE 15 Tristate Document Number: 002-20538 Rev. *B Page 86 of 146 ADVANCE CYW4356/CG8674 11.6 I/O States The following notations are used in Table 29: ■ I: Input signal ■ O: Output signal ■ I/O: Input/Output signal ■ PU = Pulled up ■ PD = Pulled down ■ NoPull = Neither pulled up nor pulled down ■ Where applicable, the default value is shown in bold brackets (for example, [default value]) Table 29. I/O States Name WL_REG_ON I/O Keepera Active Mode Low Power State/Sleep (All Power Present) I N I: PD I: PD Pull-down can be disabled Pull-down can be disabled I/O Y Open drain or push-pull Programmable Active high BT_HOST_WAK I/O E Y I/O: PU, PD, NoPull Programmable BT_REG_ON CLK_REQ Power-downb (BT_REG_ON and WL_REG_ON Held Low) I: PD (of 200K) Out-of-Reset; (WL_REG_ON High Before SW Down- and BT_REG_ON = 0) Power Rail load (BT_REG_ON and VDDIOs Are High; WL_REG_ON Present High) I: PD (of 200K) I: PD (of 200K) – Open drain or push-pull High-Z, NoPull Programmable Active high Open drain Active high Open drain Active high BT_VDDIO I/O: PU, PD, NoPull Programmable I: PD I: PD High-Z, NoPull BT_DEV_WAKE BT_GPIO 5 BT_GPIO 4 I: Floating, but input disabled BT_GPIO 2, 3 BT_UART_CTS I BT_UART_RTS O Y I: NoPull; PU programmable I: NoPull O: NoPull O: NoPull BT_UART_RXD I I: PU I: NoPull BT_UART_TXD O O: NoPull O: NoPull SDIO Data I/O I/O: PU (SDIO Mode) I: PU (SDIO Mode) I: NoPull I: noPull SDIO CMD SDIO_CLK I N Document Number: 002-20538 Rev. *B I: PU I: PU High-Z, NoPull I: PU I: PU High-Z, NoPull I: PU (SDIO Mode) I: PU (SDIO Mode) I: NoPull I: NoPull VDDIO_SD Page 87 of 146 ADVANCE CYW4356/CG8674 Table 29. I/O States (Cont.) Name BT_PCM_CLK I/O I/O Keepera Y Active Mode I: NoPullc Low Power State/Sleep (All Power Present) I: NoPullc Power-downb (BT_REG_ON and WL_REG_ON Held Low) High-Z, NoPull Out-of-Reset; (WL_REG_ON High Before SW Down- and BT_REG_ON = 0) load (BT_REG_ON Power Rail and VDDIOs Are High; WL_REG_ON Present High) I: PD I: PD BT_VDDIO BT_PCM_IN BT_PCM_OUT BT_PCM_SYNC I: Floating, but input disabled BT_I2S_WS I: NoPulld I: NoPulld I/O: PU, PD, NoPull Programmable [NoPull] I/O: PU, PD, NoPull High-Z, NoPull Programmable [NoPull] I: NoPull I: NoPull I: PD I: PD I: PD BT_I2S_CLK BT_I2S_DI BT_I2S_DO GPIO_0 I/O Y GPIO_1 Y GPIO_2 Y GPIO_3 Y GPIO_4 Y I/O: PU, PD, NoPull Programmable [PD] I/O: PU, PD, NoPull Programmable [PD] GPIO_5 Y I/O: PU, PD, NoPull Programmable [PD] I/O: PU, PD, NoPull Programmable [PD] I/O: PU, PD, NoPull Programmable [NoPull] I/O: PU, PD, NoPull Programmable [NoPull] I: NoPull I: NoPull I/O: PU, PD, NoPulle I/O: PU, PD, NoPulle Ie Ie GPIO_6 Y GPIO_7 Y GPIO_8 Y GPIO_9 Y GPIO_10 Y I/O: PU, PD, NoPull Programmable [PD] I/O: PU, PD, NoPull Programmable [PD] I: PD I: PD GPIO_11 Y I/O: PU, PD, NoPull Programmable [NoPull] I/O: PU, PD, NoPull Programmable [NoPull] I: NoPull I: NoPull GPIO_12 Y I/O: PU, PD, NoPull Programmable [PU] I/O: PU, PD, NoPull Programmable [PU] I: PU I: PU I/O: PU, PD, NoPull Programmable [NoPull] I/O: PU, PD, NoPull Programmable [NoPull] I: NoPull I: NoPull GPIO_13 Y GPIO_14 Y GPIO_15 Y Document Number: 002-20538 Rev. *B VDDIO Page 88 of 146 ADVANCE CYW4356/CG8674 Table 29. I/O States (Cont.) Name RF_SW_CTRL_X I/O Keepera Y Active Mode O: NoPull Low Power State/Sleep (All Power Present) O: NoPull Power-downb (BT_REG_ON and WL_REG_ON Held Low) Out-of-Reset; (WL_REG_ON High Before SW Down- and BT_REG_ON = 0) load (BT_REG_ON Power Rail and VDDIOs Are High; WL_REG_ON Present High) O: NoPull : NoPull a. Keeper column: N = pad has no keeper. Y = pad has a keeper. Keeper is always active except in Power-down state. If there is no keeper, and it is an input and there is Nopull, then the pad should be driven to prevent leakage due to floating pad (for example, SDIO_CLK). b. In the Power-down state (xx_REG_ON=0): High-Z; NoPull => the pad is disabled because power is not supplied. c. Depending on whether the PCM interface is enabled and the configuration of PCM is in master or slave mode, it can be either input or output. d. Depending on whether the I2S interface is enabled and the configuration of I2S is in master or slave mode, it can be either input or output. e. For WLBGA these GPIOs have a PD in all states. For WLCSP these GPIOs have a PU in all states. Document Number: 002-20538 Rev. *B Page 89 of 146 ADVANCE CYW4356/CG8674 12. DC Characteristics 12.1 Absolute Maximum Ratings Caution! The absolute maximum ratings in Table 30 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. Table 30. Absolute Maximum Ratings Rating DC supply for VBAT and PA driver supplya DC supply voltage for digital I/O DC supply voltage for RF switch I/Os DC input supply voltage for CLDO and LNLDO Symbol Value Unit VBAT –0.5 to +6.0 V VDDIO –0.5 to 3.9 V VDDIO_RF –0.5 to 3.9 V – –0.5 to 1.575 V DC supply voltage for RF analog VDDRF –0.5 to 1.32 V DC supply voltage for core VDDC –0.5 to 1.32 V – –0.5 to 3.63 V WRF_TCXO_VDD Maximum undershoot voltage for I/Ob Vundershoot –0.5 V Maximum overshoot voltage for I/Ob Vovershoot VDDIO + 0.5 V Tj 125 °C Maximum junction temperature a. The maximum continuous voltage is 5.25V. Voltage transients up to 6.0V for up to 10 seconds, cumulative duration over the lifetime of the device, are allowed. Voltage transients as high as 5.5V for up to 250 seconds, cumulative duration over the lifetime of the device, are allowed. b. Duration not to exceed 25% of the duty cycle. 12.2 Environmental Ratings The environmental ratings are shown in Table 31. Table 31. Environmental Ratings Characteristic Value Units Conditions/Comments Ambient Temperature (TA) –30 to +85 °C Functional operationa Storage Temperature –40 to +125 °C – Relative Humidity Less than 60 % Storage Less than 85 % Operation a. Functionality is guaranteed but specifications require derating at extreme temperatures; see the specification tables for details. 12.3 Electrostatic Discharge Specifications Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. Always store the unused material in its antistatic packaging. Table 32. ESD Specifications Pin Type Symbol Condition ESD Rating Unit ESD, handling reference: NQY00083, Section 3.4, Group D9, Table B ESD_HAND_HBM Human body model contact 1K for WLBGA; discharge per 1.5K for WLCSP JEDEC EID/JESD22-A114 V CDM ESD_HAND_CDM Charged device model contact discharge per JEDEC EIA/JESD22-C101 V Document Number: 002-20538 Rev. *B 300 for WLBGA; 500 for WLCSP Page 90 of 144 ADVANCE CYW4356/CG8674 12.4 Recommended Operating Conditions and DC Characteristics Caution! Functional operation is not guaranteed outside of the limits shown in Table 33, and operation outside these limits for extended periods can adversely affect long-term reliability of the device. Table 33. Recommended Operating Conditions and DC Characteristics Parameter Symbol Value Minimum Typical Maximum Unit DC supply voltage for VBAT VBAT 3.0a – 5.25b V DC supply voltage for core VDD 1.14 1.2 1.26 V DC supply voltage for RF blocks in chip VDDRF 1.14 1.2 1.26 V DC supply voltage for TCXO input buffer WRF_TCXO_VDD 1.62 1.8 1.98 V DC supply voltage for digital I/O VDDIO, VDDIO_SD 1.62 – 3.63 V VDDIO_RF 3.13 3.3 3.46 V TSSI 0.15 – 0.95 V Vth_POR 0.4 – 0.7 V DC supply voltage for RF switch I/Os External TSSI input Internal POR threshold SDIO Interface I/O Pins and PCIe Out-of-band Signals PCIE_PERST_L, PCIE_PME_L, and PCIE_CLKREQ_L For VDDIO_SD = 1.8V: Input high voltage VIH 1.27 – – V Input low voltage VIL – – 0.58 V Output high voltage @ 2 mA VOH 1.40 – – V Output low voltage @ 2 mA VOL – – 0.45 V VIH 0.625 × VDDIO – – V For VDDIO_SD = 3.3V: Input high voltage VIL – – 0.25 × VDDIO V Output high voltage @ 2 mA Input low voltage VOH 0.75 × VDDIO – – V Output low voltage @ 2 mA VOL – – 0.125 × VDDIO V VIH 0.65 × VDDIO – – V Other Digital I/O Pins For VDDIO = 1.8V: Input high voltage VIL – – 0.35 × VDDIO V Output high voltage @ 2 mA Input low voltage VOH VDDIO – 0.45 – – V Output low voltage @ 2 mA VOL – – 0.45 V Input high voltage VIH 2.00 – – V Input low voltage VIL – – 0.80 V Output high voltage @ 2 mA VOH VDDIO – 0.4 – – V Output low Voltage @ 2 mA VOL – – 0.40 V Output high voltage @ 2 mA VOH VDDIO – 0.4 – – V Output low voltage @ 2 mA VOL – – 0.40 V Input capacitance CIN – – 5 pF For VDDIO = 3.3V: RF Switch Control Output Pinsc For VDDIO_RF = 3.3V: a. The CYW4356/CG8674 is functional across this range of voltages. Optimal RF performance specified in the data sheet, however, is guaranteed only for 3.13V < VBAT < 4.8V. Document Number: 002-20538 Rev. *B Page 91 of 144 ADVANCE CYW4356/CG8674 b. The maximum continuous voltage is 5.25V. Voltage transients up to 6.0V for up to 10 seconds, cumulative duration over the lifetime of the device, are allowed. Voltage transients as high as 5.5V for up to 250 seconds, cumulative duration over the lifetime of the device, are allowed. c. Programmable 2 mA to 16 mA drive strength. Default is 10 mA. 13. Bluetooth RF Specifications Unless otherwise stated, limit values apply for the conditions specified in Table 31 and Table 33. Typical values apply for an ambient temperature of +25°C. Figure 32. RF Port Location for Bluetooth Testing CYW4356 RF Switch (0.5 dB Insertion Loss) WLAN Tx Filter BT Tx WLAN/BT Rx Antenna  Port Chip Port RF Port Note: All Bluetooth specifications are measured at the chip port unless otherwise specified. Document Number: 002-20538 Rev. *B Page 92 of 144 ADVANCE CYW4356/CG8674 Table 34. Bluetooth Receiver RF Specifications Parameter Conditions Minimum Typical Maximum Unit 2480 MHz Note: The specifications in this table are measured at the chip port output unless otherwise specified. General Frequency range – RX sensitivity GFSK, 0.1% BER, 1 Mbps – –93.5 – dBm /4-DQPSK, 0.01% BER, 2 Mbps – –95.5 – dBm 8-DPSK, 0.01% BER, 3 Mbps 2402 – – –89.5 – dBm Input IP3 – –16 – – dBm Maximum input at antenna – – – –20 dBm – – –90.0 –80.0 dBm RX LO Leakage 2.4 GHz band Interference Performancea C/I co-channel GFSK, 0.1% BER – 8 11 dB C/I 1 MHz adjacent channel GFSK, 0.1% BER – –7 0 dB C/I 2 MHz adjacent channel GFSK, 0.1% BER – –38 –30 dB C/I  3 MHz adjacent channel GFSK, 0.1% BER – –56 –40 dB C/I image channel GFSK, 0.1% BER – –31 –9 dB C/I 1 MHz adjacent to image channel GFSK, 0.1% BER – –46 –20 dB C/I co-channel /4-DQPSK, 0.1% BER – 9 13 dB C/I 1 MHz adjacent channel /4-DQPSK, 0.1% BER – –11 0 dB C/I 2 MHz adjacent channel /4-DQPSK, 0.1% BER – –39 –30 dB C/I  3 MHz adjacent channel /4-DQPSK, 0.1% BER – –55 –40 dB C/I image channel /4-DQPSK, 0.1% BER – –23 –7 dB C/I 1 MHz adjacent to image channel /4-DQPSK, 0.1% BER – –43 –20 dB C/I co-channel 8-DPSK, 0.1% BER – 17 21 dB C/I 1 MHz adjacent channel 8-DPSK, 0.1% BER – –4 5 dB C/I 2 MHz adjacent channel 8-DPSK, 0.1% BER – –37 –25 dB C/I  3 MHz adjacent channel 8-DPSK, 0.1% BER – –53 –33 dB C/I Image channel 8-DPSK, 0.1% BER – –16 0 dB C/I 1 MHz adjacent to image channel 8-DPSK, 0.1% BER – –37 –13 dB Out-of-Band Blocking Performance (CW) 30–2000 MHz 0.1% BER – –10.0 – dBm 2000–2399 MHz 0.1% BER – –27 – dBm 2498–3000 MHz 0.1% BER – –27 – dBm 3000 MHz–12.75 GHz 0.1% BER – –10.0 – dBm – –13.5 – dBm Out-of-Band Blocking Performance, Modulated Interferer GFSK (1 Mbps)b 698–716 MHz WCDMA 776–849 MHz WCDMA – –13.8 – dBm 824–849 MHz GSM850 – –13.5 – dBm 824–849 MHz WCDMA – –14.3 – dBm 880–915 MHz E-GSM – –13.1 – dBm 880–915 MHz WCDMA – –13.1 – dBm Document Number: 002-20538 Rev. *B Page 93 of 144 ADVANCE CYW4356/CG8674 Table 34. Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit 1710–1785 MHz GSM1800 – –18.1 – dBm 1710–1785 MHz WCDMA – –17.4 – dBm 1850–1910 MHz GSM1900 – –19.4 – dBm 1850–1910 MHz WCDMA – –18.8 – dBm 1880–1920 MHz TD-SCDMA – –19.7 – dBm 1920–1980 MHz WCDMA – –19.6 – dBm 2010–2025 MHz TD–SCDMA – –20.4 – dBm 2500–2570 MHz WCDMA – –20.4 – dBm 2500–2570 MHzc Band 7 – –30.5 – dBm 2300–2400 MHzd Band 40 – –34.0 – dBm MHze Band 38 – –30.8 – dBm XGP Band – –29.5 – dBm WCDMA – –9.8 – dBm 776–794 MHz WCDMA – –9.7 – dBm 824–849 MHz GSM850 – –10.7 – dBm 824–849 MHz WCDMA – –11.4 – dBm 880–915 MHz E-GSM – –10.4 – dBm 880–915 MHz WCDMA – –10.2 – dBm 1710–1785 MHz GSM1800 – –15.8 – dBm 1710–1785 MHz WCDMA – –15.4 – dBm 1850–1910 MHz GSM1900 – –16.6 – dBm 2570–2620 2545–2575 MHzf /4-DPSK (2 Mbps)b 698–716 MHz 1850–1910 MHz WCDMA – –16.4 – dBm 1880–1920 MHz TD-SCDMA – –17.9 – dBm 1920–1980 MHz WCDMA – –16.8 – dBm 2010–2025 MHz TD-SCDMA – –18.6 – dBm 2500–2570 MHz WCDMA – –20.4 – dBm 2500–2570 MHzc Band 7 – –31.9 – dBm 2300–2400 MHzd Band 40 – –35.3 – dBm 2570–2620 MHze Band 38 – –31.8 – dBm XGP Band – –31.1 – dBm 698–716 MHz WCDMA – –12.6 – dBm 776–794 MHz WCDMA – –12.6 – dBm 824–849 MHz GSM850 – –12.7 – dBm 824–849 MHz WCDMA – –13.7 – dBm 880–915 MHz E-GSM – –12.8 – dBm 880–915 MHz WCDMA – –12.6 – dBm 1710–1785 MHz GSM1800 – –18.1 – dBm 1710–1785 MHz WCDMA – –17.4 – dBm 1850–1910 MHz GSM1900 – –19.1 – dBm 1850–1910 MHz WCDMA – –18.6 – dBm 2545–2575 MHzf 8-DPSK (3 Mbps)b Document Number: 002-20538 Rev. *B Page 94 of 144 ADVANCE CYW4356/CG8674 Table 34. Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit 1880–1920 MHz TD-SCDMA – –19.3 – dBm 1920–1980 MHz WCDMA – –18.9 – dBm 2010–2025 MHz TD-SCDMA – –20.4 – dBm 2500–2570 MHz WCDMA – –21.4 – dBm 2500–2570 MHzc Band 7 – –31.0 – dBm 2300–2400 MHzd Band 40 – –34.5 – dBm MHze Band 38 – –31.2 – dBm XGP Band – –30.0 – dBm – –95 –62 dBm 2570–2620 2545–2575 MHzf Spurious Emissions 30 MHz–1 GHz 1–12.75 GHz – –70 –47 dBm 851–894 MHz – –147 – dBm/Hz 925–960 MHz – –147 – dBm/Hz 1805–1880 MHz – –147 – dBm/Hz 1930–1990 MHz – –147 – dBm/Hz 2110–2170 MHz – –147 – dBm/Hz a. The maximum value represents the actual Bluetooth specification required for Bluetooth qualification as defined in the v5.0 specification. b. Bluetooth reference level for the wanted signal at the Bluetooth Chip port = at 3 dB desense for each data rate. c. Interferer: 2560 MHz, BW=10 MHz; measured at 2480 MHz. d. Interferer: 2360 MHz, BW=10 MHz; measured at 2402 MHz. e. Interferer: 2380 MHz, BW=10 MHz; measured at 2480 MHz. f. Interferer: 2355 MHz, BW=10 MHz; measured at 2480 MHz. Document Number: 002-20538 Rev. *B Page 95 of 144 ADVANCE CYW4356/CG8674 Table 35. Bluetooth Transmitter RF Specifications Parameter Conditions Minimum Typical Maximum Unit Note: The specifications in this table are measured at the Chip port output unless otherwise specified. General Frequency range 2402 – 2480 MHz Basic rate (GFSK) TX power at Bluetooth – 13.0 – dBm QPSK TX power at Bluetooth – 10.0 – dBm 8PSK TX power at Bluetooth – 10.0 – dBm Power control step 2 4 8 dB – – 0.93 1 MHz M – N = the frequency range for which the spurious emission is measured relative to the transmit center frequency. – –38 –26.0 dBc – –31 –20.0 dBm – –43 –40.0 dBm 30 MHz to 1 GHz – – – –36.0 b,c dBm 1 GHz to 12.75 GHz – – – –30.0 b,d,e dBm Output power is with TCA and TSSI enabled. GFSK In-Band Spurious Emissions –20 dBc BW EDR In-Band Spurious Emissions 1.0 MHz < |M – N| < 1.5 MHz 1.5 MHz < |M – N| < 2.5 MHz |M – N|  2.5 MHza Out-of-Band Spurious Emissions 1.8 GHz to 1.9 GHz – – – –47.0 dBm 5.15 GHz to 5.3 GHz – – – –47.0 dBm – – –103 – dBm 65–108 MHz FM RX – –147 – dBm/Hz 776–794 MHz CDMA2000 – –147 – dBm/Hz 869–960 MHz cdmaOne, GSM850 – –147 – dBm/Hz 925–960 MHz E-GSM – –147 – dBm/Hz 1570–1580 MHz GPS – –146 – dBm/Hz 1805–1880 MHz GSM1800 – –145 – dBm/Hz 1930–1990 MHz GSM1900, cdmaOne, WCDMA – –144 – dBm/Hz 2110–2170 MHz WCDMA – –141 – dBm/Hz 2500–2570 MHz Band 7 – –140 – dBm 2300–2400 MHz Band 40 – –140 – dBm 2570–2620 MHz Band 38 – –140 – dBm 2545–2575 MHz XGP Band – –140 – dBm GPS Band Spurious Emissions Spurious emissions Out-of-Band Noise Floorf a. The typical number is measured at ±3 MHz offset. b. The maximum value represents the value required for Bluetooth qualification as defined in the v5.0 specification. c. The spurious emissions during Idle mode are the same as specified in Table 35. d. Specified at the Bluetooth Antenna port. e. Meets this specification using a front-end band-pass filter. f. Transmitted power in cellular and FM bands at the Bluetooth Antenna port. See Figure 32 for location of the port. Document Number: 002-20538 Rev. *B Page 96 of 144 ADVANCE CYW4356/CG8674 Table 36. Local Oscillator Performance Parameter Minimum Typical Maximum Unit Lock time – 72 – µs Initial carrier frequency tolerance – ±25 ±75 kHz DH1 packet – ±8 ±25 kHz DH3 packet – ±8 ±40 kHz DH5 packet – ±8 ±40 kHz Drift rate – 5 20 kHz/50 µs 00001111 sequence in payloada 140 155 175 kHz payloadb 115 140 – kHz – 1 – MHz Typical Maximum Unit 2480 MHz LO Performance Frequency Drift Frequency Deviation 10101010 sequence in Channel spacing a. This pattern represents an average deviation in payload. b. Pattern represents the maximum deviation in payload for 99.9% of all frequency deviations. Table 37. BLE RF Specifications Parameter Conditions Minimum Frequency range – 2402 RX sensea GFSK, 0.1% BER, 1 Mbps – –95.5 – dBm TX powerb – – 8.5 – dBm Mod Char: delta F1 average – 225 255 275 kHz Mod Char: delta F2 max.c – 99.9 – – % Mod Char: ratio – 0.8 0.95 – % a. Dirty TX is On. b. BLE TX power can be increased to compensate for front-end losses such as BPF, duplexer, switch, etc.). The output is capped at 12 dBm out. The BLE TX power at the antenna port cannot exceed the 10 dBm specification limit. c. At least 99.9% of all delta F2 max. frequency values recorded over 10 packets must be greater than 185 kHz. Document Number: 002-20538 Rev. *B Page 97 of 144 ADVANCE CYW4356/CG8674 14. WLAN RF Specifications 14.1 Introduction The CYW4356/CG8674 includes an integrated dual-band direct conversion radio that supports the 2.4 GHz and the 5 GHz bands. This section describes the RF characteristics of the 2.4 GHz and 5 GHz radios. Unless otherwise stated, limit values apply for the conditions specified inTable 31 and Table 33. Typical values apply for an ambient temperature +25°C. Figure 33. Port Locations (Applies to 2.4 GHz and 5 GHz) CYW4356 RF Switch (0.5 dB Insertion Loss) WLAN Tx Filter BT Tx WLAN/BT Rx Antenna  Port Chip Port RF Port 14.2 2.4 GHz Band General RF Specifications Table 38. 2.4 GHz Band General RF Specifications Item Condition Minimum Typical Maximum Unit TX/RX switch time Including TX ramp down – – 5 µs RX/TX switch time Including TX ramp up – – 2 µs Power-up and power-down ramp time DSSS/CCK modulations – – 100 mA VBAT = 3.6V 2.8 4 5.2 MHz PWM output current – – – 600 mA Output current limit – 1400 Output voltage range Programmable, 30 mV steps Default = 1.35V – 1.2 1.35 1.5 mA V PWM output voltage DC accuracy Includes load and line regulation. Forced PWM mode –4 – 4 % PWM ripple voltage, static Measure with 20 MHz bandwidth limit. Static Load. Max. ripple based on VBAT = 3.6V, Vout = 1.35V, Fsw = 4 MHz, 2.2 μH inductor L > 1.05 μH, Cap + Board total-ESR < 20 mΩ, Cout > 1.9 μF, ESL 1.35V, Co= 2.2 μF, Vo = 1.2V 20 – – dB LDO Turn-on Time LDO turn-on time when rest of chip is up External Output Capacitor, Co Total ESR (trace/capacitor): 5 mΩ–240 mΩ External Input Capacitor Only use an external input capacitor at the VDD_LDO pin if it is not supplied from CBUCK output. Total ESR (trace/capacitor): 30 mΩ–200 mΩ – 140 180 μs 0.5a 2.2 4.7 μF – 1 2.2 μF a. Minimum capacitor value refers to the residual capacitor value after taking into account the part–to–part tolerance, DC–bias, temperature, and aging. Document Number: 002-20538 Rev. *B Page 118 of 144 ADVANCE CYW4356/CG8674 16. System Power Consumption Note: Unless otherwise stated, these values apply for the conditions specified in Table 33. 16.1 WLAN Current Consumption The WLAN current consumption measurements are shown in Table 49. All values in Table 49 are with the Bluetooth core in reset (that is, Bluetooth is OFF). . Table 49. Typical WLAN Power Consumption Bandwidth (MHz) Mode Band (GHz) Vbat = 3.6V mA Vio = 1.8V μAa Sleep Modes OFFb – – 0.003 36 Sleepc – – 0.005 260 d IEEE power save, DTIM 1 1 RX core 20 2.4 1.2 260 IEEE power save, DTIM 3 1 RX cored 20 2.4 0.4 260 IEEE power save, DTIM 1 1 RX cored 20 5 1.2 260 cored 20 5 0.4 260 IEEE power save, DTIM 1 1 RX cored 40 5 1.5 260 cored 40 5 0.5 260 IEEE power save, DTIM 1 1 RX cored 80 5 2.0 260 cored 80 5 0.7 260 CCK 1 chaine 20 2.4 450 60 MCS8, Nss 1, HT20, SGIf, g, h 20 2.4 330 60 f, g, h MCS8, Nss 2, HT20, SGI 20 2.4 610 60 MCS7, SGIf, g, i 20 5 310 60 MCS15, SGIf, g, i 20 5 620 60 MCS7f, g, i 40 5 340 60 MCS9, Nss 1, SGIf, g, j 40 5 300 60 SGIf, g, j 40 5 590 60 MCS9, Nss 1, SGIf, g, j 80 5 330 60 MCS9, Nss 2, SGIf, g, j 80 5 610 60 1 Mbps, 1 RX core 20 2.4 65 60 1 Mbps, 2 RX cores 20 2.4 87 60 MCS7, HT20 1 RX corek 20 2.4 69 60 IEEE power save, DTIM 3 1 RX IEEE power save, DTIM 3 1 RX IEEE power save, DTIM 3 1 RX Active Modes Transmit MCS9, Nss 2, Receive k 20 2.4 92 60 MCS15, HT20k 20 2.4 96 60 CRS 1 RX corel 20 2.4 66 60 20 2.4 86 60 20 5 84 60 MCS7, HT20 2 RX cores CRS 2 RX coresl Receive MCS7, SGI 1 RX corek k 20 5 111 60 Receiver MCS15, SGIk 20 5 116 60 CRS 1 RX corel 20 5 79 60 20 5 103 60 40 5 101 60 Receive MCS7, SGI 2 RX cores CRS 2 RX coresl Receive MCS 7, SGI 1 RX corek Document Number: 002-20538 Rev. *B Page 119 of 144 ADVANCE CYW4356/CG8674 Table 49. Typical WLAN Power Consumption (Cont.) Bandwidth (MHz) Mode Band (GHz) Vbat = 3.6V mA Vio = 1.8V μAa Receive MCS 7, SGI 2 RX coresk 40 5 140 60 Receive MCS 15, SGIk 40 5 151 60 CRS 1 RX corel 40 5 93 60 coresl 40 5 128 60 Receive MCS9, Nss 1, SGIk 80 5 136 60 CRS 2 RX Receive MCS9, Nss 1, SGI 2 RX coresk 80 5 189 60 Receive MCS9, Nss 2, SGIk 80 5 205 60 corel 80 5 117 60 80 5 172 60 CRS 1 RX CRS 2 RX coresl a. Specified with all pins idle (not switching) and not driving any loads. b. WL_REG_ON and BT_REG_ON low. c. Idle, not associated, or inter-beacon. d. Beacon Interval = 102.4 ms. Beacon duration = 1 ms @1 Mbps. Average current over three DTIM intervals. e. Output power per core at RF port = 21 dBm f. Duty cycle is 100%. g. Measured using packet engine test mode. h. Output power per core at RF port = 17 dBm. i. Output power per core at RF port = 17.5 dBm. j. Output power per core at RF port = 14 dBm. k. Duty cycle is 100%. Carrier sense (CS) detect/packet receive. l. Carrier sense (CCA) when no carrier is present. Document Number: 002-20538 Rev. *B Page 120 of 144 ADVANCE CYW4356/CG8674 16.2 Bluetooth Current Consumption The Bluetooth current consumption measurements are shown in Table 50. Note: ■ The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in Table 50. ■ The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm. Table 50. Bluetooth Current Consumption VBAT (VBAT = 3.6V) Typical VDDIO (VDDIO = 1.8V) Typical Units 13 198 µA 0.217 0.197 mA 440 194 µA 500 ms Sniff Master 0.168 0.195 mA 500 ms Sniff Slave 0.124 0.190 mA DM1/DH1 Master 25.3 0.024 mA DM3/DH3 Master 30.6 0.035 mA DM5/DH5 Master 31.4 0.037 mA 3DH5 Master 29.2 0.094 mA SCO HV3 Master 11.45 0.089 mA HV3 + Sniff + Scana 11.7 0.090 mA Operating Mode Sleep Standard 1.28s Inquiry Scan P and I Scanb BLE Scanb BLE Scan 10 ms 244 196 µA 21.34 0.013 mA BLE Adv—Unconnectable 1.00 sec 67 199 µA BLE Adv—Unconnectable 1.28 sec 55 199 µA BLE Adv—Unconnectable 2.00 sec 58 199 µA BLE Connected 7.5 ms 3.95 0.013 mA BLE Connected 1 sec. 57 198 µA BLE Connected 1.28 sec. 52 197 µA a. At maximum class 1 TX power, 500 ms sniff, four attempts (slave), P = 1.28s, and I = 2.56s. b. No devices present. A 1.28 second interval with a scan window of 11.25 ms. Document Number: 002-20538 Rev. *B Page 121 of 144 ADVANCE CYW4356/CG8674 17. Interface Timing and AC Characteristics 17.1 SDIO Timing 17.1.1 SDIO Default Mode Timing SDIO default mode timing is shown by the combination of Figure 34 and Table 51. Figure 34. SDIO Bus Timing (Default Mode) fPP tWL tWH SDIO_CLK tTHL tTLH tISU tIH Input Output Document Number: 002-20538 Rev. *B tODLY tODLY (max) (min) Page 122 of 144 ADVANCE CYW4356/CG8674 Table 51. SDIO Bus Timinga Parameters (Default Mode) Parameter Symbol SDIO CLK (All values are referred to minimum VIH and maximum Frequency – Data Transfer mode Minimum Typical Maximum Unit 0 – 25 MHz VILb) fPP Frequency – Identification mode fOD 0 – 400 kHz Clock low time tWL 10 – – ns Clock high time tWH 10 – – ns Clock rise time tTLH – – 10 ns Clock low time tTHL – – 10 ns Input setup time tISU 5 – – ns Input hold time tIH 5 – – ns Output delay time – Data Transfer mode tODLY 0 – 14 ns Output delay time – Identification mode tODLY 0 – 50 ns Inputs: CMD, DAT (referenced to CLK) Outputs: CMD, DAT (referenced to CLK) a. Timing is based on CL ≤ 40pF load on CMD and Data. b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO. 17.1.2 SDIO High-Speed Mode Timing SDIO high-speed mode timing is shown by the combination of Figure 35 and Table 52. Figure 35. SDIO Bus Timing (High-Speed Mode) fPP tWL tWH 50% VDD SDIO_CLK tTHL tISU tTLH tIH Input Output tODLY Document Number: 002-20538 Rev. *B tOH Page 123 of 144 ADVANCE CYW4356/CG8674 Table 52. SDIO Bus Timinga Parameters (High-Speed Mode) Parameter Symbol Minimum Typical Maximum Unit fPP 0 – 50 MHz Frequency – Identification Mode fOD 0 – 400 kHz Clock low time tWL 7 – – ns Clock high time tWH 7 – – ns Clock rise time tTLH – – 3 ns Clock low time tTHL – – 3 ns Input setup Time tISU 6 – – ns Input hold Time tIH 2 – – ns tODLY – – 14 ns Output hold time tOH 2.5 – – ns Total system capacitance (each line) CL – – 40 pF SDIO CLK (all values are referred to minimum VIH and maximum Frequency – Data Transfer Mode VILb) Inputs: CMD, DAT (referenced to CLK) Outputs: CMD, DAT (referenced to CLK) Output delay time – Data Transfer Mode a. Timing is based on CL ≤ 40pF load on CMD and Data. b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO. 17.1.3 SDIO Bus Timing Specifications in SDR Modes Clock Timing Figure 36. SDIO Clock Timing (SDR Modes) tCLK SDIO_CLK tCR tCF tCR Table 53. SDIO Bus Clock Timing Parameters (SDR Modes) Parameter – Symbol Minimum Maximum Unit 40 – ns SDR12 mode 20 – ns SDR25 mode 10 – ns SDR50 mode tCLK Comments 4.8 – ns SDR104 mode – tCR, tCF – 0.2 × tCLK ns tCR, tCF < 2.00 ns (max.) @100 MHz, CCARD = 10 pF tCR, tCF < 0.96 ns (max.) @208 MHz, CCARD = 10 pF Clock duty – 30 70 % – Document Number: 002-20538 Rev. *B Page 124 of 144 ADVANCE CYW4356/CG8674 Device Input Timing Figure 37. SDIO Bus Input Timing (SDR Modes) SDIO_CLK tIS tIH CMD input DAT[3:0] input Table 54. SDIO Bus Input Timing Parameters (SDR Modes) Symbol Minimum Maximum Unit Comments tIS 1.4 – ns CCARD = 10 pF, VCT = 0.975V tIH 0.80 – ns CCARD = 5 pF, VCT = 0.975V tIS 3.00 – ns CCARD = 10 pF, VCT = 0.975V tIH 0.80 – ns CCARD = 5 pF, VCT = 0.975V SDR104 Mode SDR50 Mode Document Number: 002-20538 Rev. *B Page 125 of 144 ADVANCE CYW4356/CG8674 Device Output Timing Figure 38. SDIO Bus Output Timing (SDR Modes up to 100 MHz) tCLK SDIO_CLK tODLY tOH CMD input DAT[3:0] input Table 55. SDIO Bus Output Timing Parameters (SDR Modes up to 100 MHz) Symbol Minimum Maximum Unit Comments tODLY – 7.5 ns tCLK ≥ 10 ns CL= 30 pF using driver type B for SDR50 tODLY – 14.0 ns tCLK ≥ 20 ns CL= 40 pF using for SDR12, SDR25 1.5 – ns Hold time at the tODLY (min.) CL= 15 pF tOH Document Number: 002-20538 Rev. *B Page 126 of 144 ADVANCE CYW4356/CG8674 Figure 39. SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz) tCLK SDIO_CLK tOP tODW CMD input DAT[3:0] input Table 56. SDIO Bus Output Timing Parameters (SDR Modes 100 MHz to 208 MHz) Symbol Minimum Maximum Unit 0 2 UI ΔtOP –350 +1550 ps Delay variation due to temp change after tuning tODW 0.60 – UI tODW=2.88 ns @208 MHz tOP Comments Card output phase ■ ΔtOP = +1550 ps for junction temperature of ΔtOP = 90 degrees during operation ■ ΔtOP = –350 ps for junction temperature of ΔtOP = –20 degrees during operation ■ ΔtOP = +2600 ps for junction temperature of ΔtOP = –20 to +125 degrees during operation Document Number: 002-20538 Rev. *B Page 127 of 144 ADVANCE CYW4356/CG8674 Figure 40. ΔtOP Consideration for Variable Data Window (SDR 104 Mode) Data valid window Sampling point after tuning ȴtOP = 1550 ps Data valid window ȴtOP = –350 ps Sampling point after card junction heating by +90°C from tuning temperature Data valid window Sampling point after card junction cooling by –20°C from tuning temperature 17.1.4 SDIO Bus Timing Specifications in DDR50 Mode Figure 41. SDIO Clock Timing (DDR50 Mode) tCLK SDIO_CLK tCR tCF tCR Table 57. SDIO Bus Clock Timing Parameters (DDR50 Mode) Minimum Maximum Unit – Parameter tCLK Symbol 20 – ns DDR50 mode – tCR,tCF – 0.2 × tCLK ns tCR, tCF < 4.00 ns (max.) @50 MHz, CCARD = 10 pF Clock duty – 45 55 % – Document Number: 002-20538 Rev. *B Comments Page 128 of 144 ADVANCE CYW4356/CG8674 Data Timing, DDR50 Mode Figure 42. SDIO Data Timing (DDR50 Mode) FPP SDIO_CLK tISU2x DAT[3:0]  input Invalid tIH2x tISU2x Data Invalid tIH2x Data Invalid tODLY2x (max) DAT[3:0]  output Data Invalid tODLY2x (max) tODLY2x  tODLY2x  (min) (min) Data Available timing  window for card  output transition Data In DDR50 mode, DAT[3:0] lines are sampled on both edges of  the clock (not applicable for CMD line) Data Available timing  window for host to  sample data from card Table 58. SDIO Bus Timing Parameters (DDR50 Mode) Parameter Symbol Minimum Maximum Unit Comments Input CMD Input setup time tISU 6 – ns CCARD < 10pF (1 Card) Input hold time tIH 0.8 – ns CCARD < 10pF (1 Card) Output delay time tODLY – 13.7 ns CCARD < 30pF (1 Card) Output hold time tOH 1.5 – ns CCARD < 15pF (1 Card) Output CMD Input DAT Input setup time tISU2x 3 – ns CCARD < 10pF (1 Card) Input hold time tIH2x 0.8 – ns CCARD < 10pF (1 Card) Output delay time tODLY2x – 7.5 ns CCARD < 25pF (1 Card) Output hold time tODLY2x 1.5 – ns CCARD < 15pF (1 Card) Output DAT Document Number: 002-20538 Rev. *B Page 129 of 144 ADVANCE CYW4356/CG8674 17.2 PCI Express Interface Parameters Table 59. PCI Express Interface Parameters Parameter Symbol Comments Minimum Typical Maximum Unit Generala Baud rate BPS – Reference clock peak-to-peak differential amplitudeb Vref LVPECL – 5 – Gbaud 0.95 – – V Differential termination ZRX-DIFF-DC Differential termination 80 100 120 Ω DC impedance ZRX-DC DC common-mode impedance 40 50 60 Ω Powered down termination (POS) ZRX-HIGH-IMP-DC-POS Power-down or RESET high impedance 100k – – Ω Powered down termination (NEG) ZRX-HIGH-IMP-DC-NEG Power-down or RESET high impedance 1k – – Ω Input voltage VRX-DIFFp-p AC coupled, differential p-p 175 – – mV Jitter tolerance TRX-EYE Minimum receiver eye width 0.4 – – UI Differential return loss RLRX-DIFF Differential return loss 10 – – dB Common-mode return loss RLRX-CM Common-mode return loss 6 – – dB Unexpected electrical idle enter TRX-IDEL-DET-DIFFdetect threshold integration time ENTERTIME An unexpected electrical idle must be recognized no longer than this time to signal an unexpected idle condition. – – 10 ms Signal detect threshold VRX-IDLE-DET-DIFFp-p Electrical idle detect threshold 65 – 175 mV Output voltage VTX-DIFFp-p Differential p-p, programmable in 16 steps 0.8 – 1200 mV Output voltage rise time VTX-RISE 20% to 80% 0.125 (2.5 GT/s) 0.15 (5 GT/s) – – UI Output voltage fall time VTX-FALL 80% to 20% 0.125 (2.5 GT/s) 0.15 (5 GT/s) – – UI RX detection voltage swing VTX-RCV-DETECT The amount of voltage change allowed during receiver detection. – – 600 mV TX AC peak common-mode voltage (5 GT/s) VTX-CM-AC-PP TX AC common mode voltage (5 GT/s) – – 100 mV TX AC peak common-mode voltage (2.5 GT/s) VTX-CM-AC-P TX AC common mode voltage (2.5 GT/s) – – 20 mV Receiver Transmitter Document Number: 002-20538 Rev. *B Page 130 of 144 ADVANCE CYW4356/CG8674 Table 59. PCI Express Interface Parameters (Cont.) Parameter Symbol Comments Minimum Typical Maximum Unit 0 – 100 mV Absolute delta of DC common- VTX-CM-DC-LINE-DELTA DC offset between D+ model voltage between D+ and and DD- 0 – 25 mV Electrical idle differential peak output voltage VTX-IDLE-DIFF-AC-p Peak-to-peak voltage 0 – 20 mV TX short circuit current ITX-SHORT Current limit when TX output is shorted to ground. – – 90 mA DC differential TX termination ZTX-DIFF-DC Low impedance defined during signaling (parameter is captured for 5.0 GHz by RLTX-DIFF) 80 – 120 Ω Differential return loss RLTX-DIFF Differential return loss 10 (min.) for 0.05: 1.25 GHz – – dB Common-mode return loss RLTX-CM Common-mode return loss 6 – – dB TX eye width TTX-EYE Minimum TX eye width 0.75 – – UI Absolute delta of DC common- VTX-CM-DC-ACTIVEmodel voltage during L0 and IDLE-DELTA electrical idle Absolute delta of DC common-model voltage during L0 and electrical idle. a. For out-of-band PCIe signal specifications, refer to Table 33. b. The reference clock inputs comply with the requirements of the PCI Express CEM v2.0 Specification (see References). 17.3 JTAG Timing Table 60. JTAG Timing Characteristics Period Output Maximum Output Minimum TCK 125 ns – – – – TDI – – – 20 ns 0 ns TMS – – – 20 ns 0 ns TDO – 100 ns 0 ns – – 250 ns – – – – Signal Name JTAG_TRST Document Number: 002-20538 Rev. *B Setup Hold Page 131 of 144 ADVANCE CYW4356/CG8674 18. Power-Up Sequence and Timing 18.1 Sequencing of Reset and Regulator Control Signals The CYW4356/CG8674 has two signals that allow the host to control power consumption by enabling or disabling the Bluetooth, WLAN, and internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the signals for various operational states (see Figure 43, Figure 44, and Figure 45 and Figure 46). The timing values indicated are minimum required values; longer delays are also acceptable. 18.1.1 Description of Control Signals ■ WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the internal CYW4356/CG8674 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low the WLAN section is in reset. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. ■ BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal CYW4356/CG8674 regulators. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this pin is low and WL_REG_ON is high, the BT section is in reset. Note: ■ For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 ms time delay between consecutive toggles (where both signals have been driven low). This is to allow time for the CBUCK regulator to discharge. If this delay is not followed, then there may be a VDDIO in-rush current on the order of 36 mA during the next PMU cold start. ■ The CYW4356/CG8674 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold. Wait at least 150 ms after VDDC and VDDIO are available before initiating SDIO accesses. ■ VBAT should not rise 10%–90% faster than 40 microseconds. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. 18.1.2 Control Signal Timing Diagrams Figure 43. WLAN = ON, Bluetooth = ON 32.678 kHz  Sleep Clock VBAT* 90% of VH VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds.  2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high  before VBAT is high. Document Number: 002-20538 Rev. *B Page 132 of 144 ADVANCE CYW4356/CG8674 Figure 44. WLAN = OFF, Bluetooth = OFF 32.678 kHz  Sleep Clock VBAT* VDDIO WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds.  2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. Figure 45. WLAN = ON, Bluetooth = OFF 32.678 kHz  Sleep Clock VBAT* 90% of VH VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds.  2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. Document Number: 002-20538 Rev. *B Page 133 of 144 ADVANCE CYW4356/CG8674 Figure 46. WLAN = OFF, Bluetooth = ON 32.678 kHz  Sleep Clock VBAT* 90% of VH VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds.  2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high . Document Number: 002-20538 Rev. *B Page 134 of 144 ADVANCE CYW4356/CG8674 18.1.3 Power-up Sequences Figure 47 shows the WLAN boot-up sequence from power-up to firmware download. Figure 47. WLAN Boot-Up Sequence VBAT* VDDIO WL_REG_ON