CYW4390DKWBG

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com ADVANCE CYW4390 WICED™ Wi-Fi IEEE 802.11 b/g/n SoC with Embedded Application Processor The Cypress CYW4390 is a single-chip device that provides the highest level of integration for applications targeting the Internet of Things and provides a complete embedded wireless system solution included in a system-on-a-chip (SOC). The CYW4390 device supports all the rates specified in the IEEE 802.11 b/g/n specifications. Included on-chip are an ARM Cortex-based applications processor, single stream IEEE 802.11n MAC/baseband/radio, a 2.4 GHz transmit power amplifier (PA), and a receive low-noise amplifier (LNA). It also supports optional antenna diversity for improved RF performance in difficult environments. CYW4390 is an optimized SoC targeting embedded applications in the industrial and medical sensor, home appliances and, generally, internet-of-things space. Using advanced design techniques and process technology to reduce active and idle power, the CYW4390 is designed to address the needs of embedded devices that require minimal power consumption and compact size. It includes a power management unit which simplifies the system power topology and allows for direct operation from a battery for battery powered applications while maximizing battery life. Cypress Part Numbering Scheme Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number. Table 1. Mapping Table for Part Number between Broadcom and Cypress Broadcom Part Number Cypress Part Number BCM4390 CYW4390 BCM4390DKWBG CYW4390DKWBG BCM4390DKWBGT CYW4390DKWBGT Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and other terms used in Cypress documents, go to http://www.cypress.com/glossary. Features General Features ■ Supports battery voltage range from 3.0V to 5.25V supplies with internal switching regulator. ■ Programmable dynamic power management ■ 6k-bit OTP for storing board parameters ■ Package options: 286 bump WLCSP (4.87 mm x 5.413 mm; 0.2 mm pitch) ■ Supports IEEE 802.15.2 external coexistence interface to optimize bandwidth utilization with other co-located wireless technologies such as Bluetooth, LTE, GPS, or WiMAX. ■ Integrated ARMCR4™ processor with tightly coupled memory for complete WLAN subsystem functionality, minimizing the need to wake up the applications processor for standard WLAN functions (to further minimize power consumption while maintaining the ability to upgrade to future features in the field) ■ Software architecture supported by standard WICED SDK to allow easy migration from existing discrete MCU designs and to future devices Key IEEE 802.11x Features ■ IEEE 802.11n compliant ■ Single-stream spatial multiplexing up to 72 Mbps data rate ■ Supports 20 MHz channels with optional SGI. ■ Full IEEE 802.11 b/g legacy compatibility with enhanced performance ■ Tx and Rx low-density parity check (LDPC) support for improved range and power efficiency ■ On-chip power and low-noise amplifiers. ■ Internal fractional nPLL allows support for a wide range of reference clock frequencies. Cypress Semiconductor Corporation Document Number: 002-15055 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 21, 2017 ADVANCE ■ Security support: ❐ WPA™ and WPA2™ (Personal) support for powerful encryption and authentication ❐ AES and TKIP in hardware for faster data encryption and IEEE 802.11i compatibility CYW4390 Reference WLAN subsystem provides Cisco® Compatible Extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0) ❐ Supports Wi-Fi Protected Setup and Wi-Fi Easy-Setup ❐ ■ Worldwide regulatory support: Global products supported with worldwide homologated design ■ 448 KB RAM for application code and data execution Application Processor Features ■ ARM Cortex-M3 32-bit RISC processor Figure 1. Functional Block Diagram VIO VBAT CYW 4390 W L_REG_ON W LAN  System  I/F W L_JTAG W L_GPIO 2.4 GHz W LAN Tx 2.4 GHz W LAN T/R  Switch CLK_REQ UART Application  CPU Host I/F  SPI Flash I2 S 37.4 M Hz XTAL Apps_GPIO IoT Resources Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates. Customers can acquire technical documentation and software from the Cypress Support Community website (http://community.cypress.com/). Document Number: 002-15055 Rev. *E Page 2 of 64 ADVANCE CYW4390 Contents 1. Overview ........................................................................ 4 1.1 Overview ............................................................... 4 1.2 Features ................................................................ 4 1.3 Standards Compliance .......................................... 5 2. Power Supplies and Power Management ................... 6 2.1 CYW4390 PMU Features ...................................... 6 2.2 Power Supply Topology ........................................ 6 2.3 Power Management .............................................. 8 2.4 PMU Sequencing .................................................. 8 2.5 Power-Off Shutdown ............................................. 9 2.6 Power-Up/Power-Down/Reset Circuits ................. 9 3. Frequency References ............................................... 10 3.1 Crystal Interface and Clock Generation .............. 10 3.2 External Frequency Reference ............................ 10 3.3 External 32.768 KHz Low-Power Oscillator ........ 12 4. Applications Microprocessor and Memory Unit ...... 13 4.1 Reset ................................................................... 13 5. Applications Microprocessor Subsystem External Interfaces ..................................................... 14 5.1 Introduction .......................................................... 14 5.2 SPI Flash Interface .............................................. 16 5.3 UART Interfaces .................................................. 16 5.4 I2S Interface ........................................................ 17 5.5 General Purpose Input and Output ..................... 18 5.6 I2C ....................................................................... 18 6. WLAN Global Functions ............................................ 19 6.1 WLAN CPU and Memory Subsystem .................. 19 6.2 One-Time Programmable Memory ...................... 19 6.3 UART Interface .................................................... 19 6.4 JTAG Interfaces .................................................. 19 6.5 Boot Sequence .................................................... 20 7. Wireless LAN MAC and PHY ..................................... 21 7.1 IEEE 802.11n MAC ............................................. 21 7.2 IEEE 802.11n PHY .............................................. 24 8. WLAN Radio Subsystem ............................................ 26 8.1 Receiver Path ...................................................... 26 8.2 Transmit Path ...................................................... 26 8.3 Calibration ........................................................... 26 9. Pinout and Signal Descriptions ................................ 27 Document Number: 002-15055 Rev. *E 9.1 Ball Maps ............................................................. 27 9.2 Pin Lists ............................................................... 28 9.3 Signal Descriptions .............................................. 36 9.4 I/O States ............................................................ 40 10. DC Characteristics ................................................... 42 10.1 Absolute Maximum Ratings ............................... 42 10.2 Environmental Ratings ...................................... 42 10.3 Electrostatic Discharge Specifications .............. 43 10.4 Recommended Operating Conditions and DC Characteristics ............................................ 44 11. WLAN RF Specifications .......................................... 45 11.1 Introduction ........................................................ 45 11.2 2.4 GHz Band General RF Specifications ......... 45 11.3 WLAN 2.4 GHz Receiver Performance Specifications ................................................... 46 11.4 WLAN 2.4 GHz Transmitter Performance Specifications ................................................... 48 11.5 General Spurious Emissions Specifications ...... 49 12. Internal Regulator Electrical Specifications .......... 50 12.1 Core Buck Switching Regulator ......................... 50 12.2 3.3V LDO (LDO3P3) ......................................... 51 12.3 CLDO ................................................................ 52 12.4 LNLDO .............................................................. 53 13. System Power Consumption ................................... 54 13.1 WLAN Current Consumption ............................. 55 13.2 JTAG Timing ..................................................... 55 14. Power-Up Sequence and Timing ............................. 56 14.1 Sequencing of Reset and Regulator Control Signals ................................................. 56 15. Package Information ................................................ 59 15.1 Package Thermal Characteristics ..................... 59 15.2 Junction Temperature Estimation and PSIJT Versus THETAJC .................................... 59 15.3 Environmental Characteristics ........................... 59 16. Mechanical Information ........................................... 60 17. Ordering Information ................................................ 62 Document History .......................................................... 63 Sales, Solutions, and Legal Information ...................... 64 Page 3 of 64 ADVANCE CYW4390 1. Overview 1.1 Overview The Cypress CYW4390 is a single-chip device that provides the highest level of integration for an embedded system-on-a-chip with integrated IEEE 802.11 b/g/n MAC/baseband/radio and a separate ARM-Cortex M3 applications processor. It provides a small formfactor solution with minimal external components to drive down cost for mass volumes and allows for an embedded system with flexibility in size, form, and function. Comprehensive power management circuitry and software ensure the system can meet the needs of highly embedded systems that require minimal power consumption and reliable operation. Figure 2 shows the interconnect of all the major physical blocks in the CYW4390 and their associated external interfaces, which are described in greater detail in the following sections. Figure 2. Block Diagram and IO SPI (Flash) CYW4390 GPIO_B[0:11] RF Tx 2‐Wire UART4 RF Rx 2x4‐Wire UART1/2 2‐Wire UART3 2 ARM Cortex‐M3 48 MHz WLAN Core 802.11n 448 KB  RAM 1x1 2.4 GHz IS GPIO_A[0:11] 2 IC Tx/Rx Switch Control Antenna Diversity SPI Master/Slave 3V3 JTAG GND WAKE RESET_N 1.2 Features The CYW4390 supports the following features: ■ ARM Cortex-M3 clocked at 48 MHz ■ 448 KB of SRAM available for the applications processor ■ Two high-speed 4-wire UART interfaces with operation up to 4 Mbps ■ Two low-speed 2-wire UART interfaces ■ One generic SPI master/slave interface with operation up to 24 MHz ■ One SPI master interface for serial flash ■ One I2C interface ■ One I2S interface ■ 24 x GPIOs (12 dedicated,12 with alternate functions) ■ IEEE 802.11 b/g/n 1x1 2.4 GHz radio ■ Single- and dual-antenna support Document Number: 002-15055 Rev. *E Page 4 of 64 ADVANCE CYW4390 1.3 Standards Compliance The CYW4390 supports the following standards: ■ IEEE 802.11n ■ IEEE 802.11b ■ IEEE 802.11g ■ IEEE 802.11d ■ IEEE 802.11h ■ IEEE 802.11i ■ Security: ❐ WEP ❐ WPA™ Personal ❐ WPA2™ Personal ❐ WMM ❐ WMM-PS (U-APSD) ❐ WMM-SA ❐ AES (hardware accelerator) ❐ TKIP (hardware accelerator) ❐ CKIP (software support) Proprietary Protocols: ❐ CCXv2 ❐ CCXv3 ❐ CCXv4 ❐ CCXv5 ❐ WFAEC The CYW4390 supports the following additional standards: ■ ■ IEEE 802.11r—fast roaming (between APs) ■ IEEE 802.11w—secure management frames ■ IEEE 802.11 Extensions: ❐ IEEE 802.11e QoS enhancements (as per the WMM® specification is already supported) ❐ IEEE 802.11i MAC enhancements ❐ IEEE 802.11k radio resource measurement Document Number: 002-15055 Rev. *E Page 5 of 64 ADVANCE CYW4390 2. Power Supplies and Power Management 2.1 CYW4390 PMU Features ■ VBAT to 1.35Vout (275 mA nominal, 600 mA maximum) Core-Buck (CBUCK) switching regulator ■ VBAT to 3.3Vout (200 mA nominal, 450 mA maximum) LDO3P3 ■ 1.35V to 1.2Vout (100 mA nominal, 150 mA maximum) LNLDO ■ 1.35V to 1.2out (175 mA nominal, 300 mA maximum) CLDO with bypass mode for deep sleep ■ Additional internal LDOs (not externally accessible) 2.2 Power Supply Topology One buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW4390. All regulators are programmable via the PMU. These blocks simplify power supply design for embedded designs. A single VBAT (3.0V to 5.25V DC max) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in the CYW4390. Two control signals, APPS_REG_ON and WL_REG_ON, are used to power-up the regulators and take the respective core out of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only when both APPS_REG_ON and WL_REG_ON are deasserted. The applications processor can drive WL_REG_ON internally when the pin is externally tied to ground. The CLDO and LNLDO may be turned off/on based on the dynamic demands of the application. The CYW4390 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO regulators. When in this state, LPLDO1 and LPLDO2 (which are low-power linear regulators that are supplied by the system VIO supply) provide the CYW4390 with all the voltages it requires, further reducing leakage currents. Figure 3 shows the regulators and a typical power topology. Document Number: 002-15055 Rev. *E Page 6 of 64 ADVANCE CYW4390 Figure 3. Typical Power Topology Areas with hatching are off‐chip CYW4390 Internal LNLDO 1.2V WL RF – AFE Internal LNLDO 1.2V WL RF – TX (2.4 GHz) Internal VCOLDO 1.2V WL RF – LOGEN (2.4 GHz) Internal LNLDO 1.2V WL RF – RX/LNA (2.4 GHz) XTAL LDO 1.2V LNLDO 1.2V (80 mA) (80 mA) (80 mA) (80 mA) WL_REG_ON APPS_REG_ON VBAT Core Buck  Regulator CBUCK Off‐chip area 1.35V Peak 600 mA Average 275 mA (30 mA) (10 mA) WL RF – XTAL WL RF – RFPLL PFD/MMD APPS ANALOG Off‐chip area WLAN BBPLL/DFLL WLAN/APPS CPU/CLB/Top  (Always on) WL OTP VDDIO LPDO1 (3 mA) WL PHY CLDO 1.1V Peak 300 mA Average 175 mA (Bypass in deep‐sleep) WL DIGITAL 1.2—1.1V APPS CPU DIGITAL WL/APPS CPU SRAMs VDDIO MEMLPLDO (3 mA) 0.9V WL PA/PAD (2.4 GHz) VDDIO_RF WL OTP 3.3V VBAT LDO3P3 Peak 800–450 mA Average 200 mA 3.3V Internal  LNLDO 2.5V WL RF – VCO Internal  LNLDO 2.5V WL RF – CP (25 mA) (8 mA) Document Number: 002-15055 Rev. *E Page 7 of 64 ADVANCE CYW4390 2.3 Power Management The CYW4390 has been designed with the stringent power consumption requirements of embedded devices in mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the CYW4390 integrated RAM is a high Vt memory with dynamic clock control. The dominant supply current consumed by the RAM is leakage current only. The CYW4390 also includes an advanced WLAN power management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW4390 into various power management states appropriate to the current environment and activities that are being performed. The power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power up sequences are fully programmable. Configurable, free-running counters (running at 32.768 kHz LPO clock) in the PMU sequencer are used to turn on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock speeds are used wherever possible. The CYW4390 WLAN-specific power states are described as follows: ■ Active mode— All WLAN blocks in the CYW4390 are powered up and fully functional with active carrier sensing and frame transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer. ■ Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the WLAN portion of the CYW4390 remains powered up in an IDLE state. All main clocks (PLL, crystal oscillator or TCXO) are shut down to reduce active power to the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active mode. In Doze mode, the primary power consumed by the WLAN core is due to leakage current. ■ Deep-sleep mode—Most of the chip including both analog and digital domains and most of the regulators are powered off. Logic states in the digital core are saved and preserved into a retention memory in the always-ON domain before the digital core is powered off. Upon a wake-up event triggered by the PMU timers or an external interrupt, logic states in the digital core are restored to their pre-deep-sleep settings to avoid lengthy HW reinitialization. ■ Power-down mode—The CYW4390 is effectively powered off by shutting down all internal regulators. The chip is brought out of this mode by external logic re-enabling the internal regulators. The CYW4390 application processor subsystem can be independently powered on or off at the system level in the power-down mode. In addition it is also possible to keep the application processor in active mode while the WLAN blocks are in Doze or Deep-Sleep. 2.4 PMU Sequencing The PMU sequencer is responsible for minimizing system power consumption. It enables and disables various system resources based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Resource requests may come from several sources: clock requests from cores, the minimum resources defined in the ResourceMin register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of resources required to produce the requested clocks. Each resource is in one of four states: enabled, disabled, transition_on, and transition_off and has a timer that contains 0 when the resource is enabled or disabled and a non-zero value in the transition states. The timer is loaded with the time_on or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is 0, the resource can go immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can go immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. During each clock cycle, the PMU sequencer performs the following actions: ■ Computes the required resource set based on requests and the resource dependency table. ■ Decrements all timers whose values are non zero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource and inverts the ResourceState bit. ■ Compares the request with the current resource status and determines which resources must be enabled or disabled. ■ Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered up dependents. ■ Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled. Document Number: 002-15055 Rev. *E Page 8 of 64 ADVANCE CYW4390 2.5 Power-Off Shutdown The CYW4390 provides a low-power shutdown feature that allows the device to be turned off. When the CYW4390 is not needed in the system, VDDIO_RF and VDDC are shut down while VDDIO remains powered. This allows the CYW4390 to be effectively off while keeping the I/O pins powered so that they do not draw extra current from any other devices connected to the I/O. During a low-power shut-down state, provided VDDIO remains applied to the CYW4390, all outputs are tristated, and most inputs signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system, and enables the CYW4390 to be fully integrated in an embedded device and take full advantage of the lowest power-savings modes. When the CYW4390 is powered on from this state, it is the same as a normal power-up and the device does not retain any information about its state from before it was powered down. 2.6 Power-Up/Power-Down/Reset Circuits The CYW4390 has two signals (see Table 2) that enable or disable the application CPU and WLAN subsystems and the internal regulator blocks, allowing external system circuitry to control power consumption. For timing diagrams of these signals and the required power-up sequences, see Power-Up Sequence and Timing on page 56. Table 2. Power-Up/Power-Down/Reset Control Signals Signal Description WL_REG_ON This signal is used by the PMU (with APPS_REG_ON) to power up the WLAN section. It is also OR-gated with the APPS_REG_ON input to control the internal CYW4390 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If APPS_REG_ON and WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming. APPS_REG_ON This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal CYW4390 regulators. If APPS_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has an internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming. Document Number: 002-15055 Rev. *E Page 9 of 64 ADVANCE CYW4390 3. Frequency References An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency reference may be used. In addition, a low-power oscillator (LPO) is provided for lower power mode timing. 3.1 Crystal Interface and Clock Generation The CYW4390 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator including all external components is shown in Figure 4. Consult the reference schematics for the latest configuration. Figure 4. Recommended Oscillator Configuration C WRF_XTAL_IN 12–27 pF 37.4 MHz C X ohms* WRF_XTAL_OUT 12–27 pF * Resistor value  determined by crystal  drive level. See reference  schematics for details.  A fractional-N synthesizer in the CYW4390 generates the radio frequencies, clocks, and data/packet timing, enabling it to operate using a wide selection of frequency references. The recommended default frequency reference is a 37.4 MHz crystal. The signal characteristics for the crystal interface are listed in Table 3 on page 11. Note: Although the fractional-N synthesizer can support alternative reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. Contact Cypress for further details. 3.2 External Frequency Reference As an alternative to a crystal, an external precision frequency reference can be used, provided that it meets the Phase Noise requirements listed in Table 3. If used, the external clock should be connected to the WRF_XTAL_IN pin through an external 1000 pF coupling capacitor, as shown in Figure 5. The internal clock buffer connected to this pin will be turned OFF when the CYW4390 goes into sleep mode. When the clock buffer turns ON and OFF there will be a small impedance variation. Power must be supplied to the WRF_XTAL_BUCK_VDD1P5 pin. Figure 5. Recommended Circuit to Use with an External Reference Clock 1000 pF Reference  Clock WRF_XTAL_IN NC Document Number: 002-15055 Rev. *E WRF_XTAL_OUT Page 10 of 64 ADVANCE CYW4390 Table 3. Crystal Oscillator and External Clock – Requirements and Performance Parameter Min Frequency IEEE 802.11 b/g/n operation Frequency tolerance over the lifetime of the equipment, including temperaturee Without trimming External Frequency Referenceb c Crystala Conditions/Notes Typ Max Min Typ Max Units Between 19 MHz and 52 MHzd –20 – 20 –20 – 20 ppm – – 12 – – – – pF – – – 60 – – – Ω 200 – – – – – µW Resistive – – – 30K 100K – Ω Capacitive – – 7.5 – – 7.5 pF WRF_XTAL_IN Input low level DC-coupled digital signal – – – 0 – 0.2 V WRF_XTAL_IN Input high level DC-coupled digital signal – – – 1.0 – 1.26 V WRF_XTAL_IN input voltage (see Figure 5) AC-coupled analog signal – – – 400 – 1200 mVp-p Duty cycle 37.4 MHz clock – – – 40 50 60 % Phase Noisef (IEEE 802.11b/g) 37.4 MHz clock at 10 kHz offset – – – – – –129 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –136 dBc/Hz 37.4 MHz clock at 10 kHz offset – – – – – –134 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –141 dBc/Hz Crystal load capacitance ESR External crystal must be able to tolerate this drive level. Drive level Input impedance (WRF_XTAL_IN) f Phase Noise (IEEE 802.11n, 2.4 GHz) a. b. c. d. e. f. (Crystal) Use WRF_XTAL_IN and WRF_XTAL_OUT. See External Frequency Reference on page 10 for alternative connection methods. For a clock reference other than 37.4 MHz, 20 × log10(f/ 37.4) dB should be added to the limits, where f = the reference clock frequency in MHz. The frequency step size is approximately 80 Hz resolution. It is the responsibility of the equipment designer to select oscillator components that comply with these specifications. Assumes that external clock has a flat phase noise response above 100 kHz. Document Number: 002-15055 Rev. *E Page 11 of 64 ADVANCE CYW4390 3.3 External 32.768 KHz Low-Power Oscillator The CYW4390 uses a secondary low frequency clock for low-power-mode timing. Either the internal low-precision LPO or an external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process, voltage, and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons. Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in Figure 4 on page 12. The external 32.768 kHz crystal provides: ■ A real-time clock for the apps core ■ Accurate timing for the WLAN power-save modes Table 4. External 32.768 kHz Sleep Clock Specifications Parameter Nominal input frequency LPO Clock Units 32.768 kHz Frequency accuracy ±100 ppm Duty cycle 30–70 % 200–1800 mV, p-p Input signal amplitude Signal type Input impedancea Clock jitter (during initial start-up) Square-wave or sine-wave – >100K