CYWB0125ABX-FDXI

ADVANCE INFORMATION West Bridge Antioch™ West Bridge® Antioch™ CYWB012X Family ® Features ■ ■ SLIM® architecture, allowing simultaneous and independent data paths between processor and USB, and between USB and mass storage High speed USB at 480 Mbps ❐ USB 2.0 compliant ❐ Integrated USB 2.0 transceiver, smart Serial Interface Engine ❐ 16 programmable endpoints Mass storage device support ❐ MMC/MMC+/SD ❐ NAND Flash: × 8 or × 16, SLC ❐ Full NAND management (ECC, wear-leveling) Memory-mapped interface to main processor DMA slave support Ultra low power, 1.8 V core operation Small footprint, 6 × 6 mm VFBGA and WLCSP Selectable clock input frequencies ❐ 19.2 MHz, 24 MHz, 48 MHz Expanded mass storage device support ❐ MMC/MMC+/SD ❐ CE-ATA for micro-HDD ❐ NAND Flash: × 8 or × 16, SLC ❐ Full NAND management (ECC, wear-leveling) Expanded selectable clock input frequencies ❐ 19.2 MHz, 24 MHz, 26 MHz, 48 MHz ■ ■ ■ ■ Applications ■ ■ ■ ■ ■ Cellular Phones Portable Media Players Personal Digital Assistants Digital Cameras Portable Video Recorder ■ ■ ■ ■ Logic Block Diagram West Bridge Antioch Control Registers 8051 MCU P High-Speed USB 2.0 XCVR Access Control Processor Interface U SLIMTM Mass Storage Interface SD/MMC/CE-ATA NAND S Cypress Semiconductor Corporation Document #: 001-05898 Rev.*C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 14, 2011 [+] Feedback ADVANCE INFORMATION CYWB012X Family Description West Bridge® Antioch™ is a peripheral mass storage controller that enhances a processor system with flexible mass storage support and high speed USB connectivity. Antioch has three different ports that enable connections among a main processor (P-Port), one or more mass storage devices (S-Port), and a USB host (U-Port). Antioch’s unique SLIM architecture allows these three ports to interact simultaneously and independently of each other. This offers connectivity from USB to Storage (typically used for PC high speed data download), from USB to Processor (used for synchronization operations), and from Processor to Storage. Connected as a slave to a main processor, Antioch adds support for high speed USB and mass storage access including MMC, MMC+, SDIO, CE-ATA, SLC and MLC NAND. Antioch further enables new usage models by allowing USB to directly connect to a storage device independent of the main processor. Antioch is primarily targeted at handsets, to enable high speed connectivity to a PC through USB, and support for the latest mass storage devices. Antioch can, for instance, enable a multimedia phone to support HDD or NAND MLC storage, with the ability to download multimedia data at high speed from a PC directly to the storage device. actual reading and writing of the NAND, along with its required protocols, including Single Level Cell (SLC) and Multi-Level Cell (MLC) NAND. It performs standard NAND management functions such as ECC and wear leveling. Processor Interface (P-Port) Communication with the external processor is realized through a dedicated processor interface. This interface supports both synchronous and asynchronous SRAM-mapped memory accesses. This ensures straightforward electrical communications with the processor, which may also have other devices connected on a shared memory bus. The memory address is decoded to access any of the multiple endpoint buffers inside Antioch. These endpoints serve as buffers for data between each pair of ports, for example, between the processor port and the USB port. The processor writes and reads into these buffers via the memory interface. Access to these buffers is controlled by either using a DMA protocol or an interrupt to the main processor. These two modes are configurable by the external processor. As a DMA slave, Antioch generates a DMA request signal to signify to the main processor that a specific buffer is ready to be read from or written to. The external processor monitors this signal and polls Antioch for the specific buffers ready for read or write. It then performs the appropriate read or write operations on the buffer through the processor interface. This way, the external processor only deals with the buffers to access a multitude of storage devices connected to Antioch. In the Interrupt mode, Antioch communicates important buffer status changes to the external processor using an interrupt signal. The external processor then polls Antioch for the specific buffers ready for read or write, and it performs the appropriate read or write operations via the processor interface. SLIM Architecture The Simultaneous Link to Independent Multimedia (SLIM) architecture allows three interfaces (P-port, S-port, and U-port) to connect to one another independent of each other. With this architecture, connecting the device using Antioch to a PC through USB does not disturb any of the functions of the device, which can still access mass storage, at the same time the PC is synchronizing with the main processor. The SLIM architecture enables new usage models, in which a PC can access a mass storage device independent of the main processor, or enumerate access to both the mass storage and the main processor at the same time. In a handset, this enables to use the phone as a thumb drive or download media files to the phone while still having full functionality available on the phone. It also allows using the same phone as a modem to connect the PC to the web. Configuration The West Bridge Antioch device includes configuration and status registers that are accessible as memory-mapped registers through the processor interface. The configuration registers allow the system to specify certain behavior of Antioch. For example, it can mask certain status registers from raising an interrupt. The status registers convey various status of Antioch, such as the addresses of buffers for read operations. Mass Storage Support (S-Port) The S-Port can be configured in two different modes, either simultaneously supporting an SDIO/MMC+/CE-ATA port and a × 8 NAND port, or supporting a unique × 16 NAND access port. Antioch, as part of its mass storage management functions, can fully manage a NAND device. An embedded 8051 manages the Packaging The West Bridge Antioch is available in two packaging options: As a bare die or in a 6 × 6 mm, 100-pin very fine-pitch ball grid array (VFBGA). As a 100-pin VFBGA, it consumes a small amount of space and allows for easy debug and connections to the other devices in the system. Document #: 001-05898 Rev.*C Page 2 of 9 [+] Feedback ADVANCE INFORMATION CYWB012X Family Pin List Pin Name CLK CE# A[7:0] DQ[15:0] ADV# OE# WE# INT# DRQ# DACK# SDIO and 8-bit NAND Configuration SD_D[7:0] SD_CLK SD_CMD SD_POW SD_WP S-Port NAND_IO[7:0] NAND_CLE NAND_ALE NAND_CE# NAND_RE# NAND_WE# NAND_WP# NAND_R/B# NAND_CE2# D+ D– UVALID XTALIN XTALOUT RESET# RESETOUT GPIO[1:0] WAKEUP XTALSLC[1:0] NANDCFG TEST[2:0] PVDDQ SNVDDQ UVDDQ SSVDDQ GVDDQ AVDDQ XVDDQ VDD VDD33 UVSSQ AVSSQ VGND I/O I I I I/O I I I O O I 16-bit NAND Configuration NAND_IO[15:8] N/A N/A N/A N/A NAND_IO[7:0] NAND_CLE NAND_ALE NAND_CE# NAND_RE# NAND_WE# NAND_WP# NAND_R/B# NAND_CE2# Pin Description Clock Chip Select Address Bus Data Bus Address Valid Output Enable Write Enable Interrupt Request DMA Request DMA Acknowledgement Standby – – – Z – – – Z Z – Reset – – – Z – – – Z Z – Power Domain PVDDQ VGND P-Port I/O O I/O O I I/O O O O O O O I O I/O/Z I/O/Z O I O I O I/O I I I I Power Power Power Power Power Power Power Power Power Power Power Power U-Port Others Config Power SD Data bus/NAND Upper I/O bus SD Clock SD Command SD Power Control GPIO (SD Write Protection Microswitch) NAND Lower I/O bus CMD Latch Enable Address Latch Enable Chip Enable Read Enable Write Enable Write Protect Ready/Busy Chip Enable 2 USB D+ USB D– External USB Switch Control Crystal/Clock IN Crystal Out RESET RESET OUT General Input/Output Wake Up Signal Clock Select 0 and 1 S Port Configuration Test Configuration Processor interface VDD NAND VDD USB VDD SDIO VDD Miscellaneous I/O VDD Analog VDD Crystal VDD Core VDD Power Seq Control 3.3 V USB GND Analog GND Core GND Z Z Z Z – Z Z Z Z Z Z Z – Z Z Z Low – Z – Z Z – – – – – – – – – – – – – – – – Z Z Z Z – Z Z Z Z Z Z Z – Z Z Z Low – Z – Low Z – – – – – – – – – – – – – – – – SSVDDQ VGND SNVDDQ VGND UVDDQ UVSSQ XVDDQ VGND GVDDQ VGND Document #: 001-05898 Rev.*C Page 3 of 9 [+] Feedback ADVANCE INFORMATION CYWB012X Family VDD33: In CYWB0124AB, the pin is no-connect internally. However, to migrate to CYWB0224AB, it must be connected to the highest supply to the device. This supply must always be connected. If USB is used, then VDD33 must be connected to nominal 3.3 V (because 3.3 V is required for USB). VDD33 must be constantly supplied in CYWB0224AB. Figure 1. 100-pin VFBGA Package Top View Top View 1 A ADV# 2 WE # 3 INT# 4 DRQ# 5 D+ 6 D7 UVALID 8 XTALIN 9 AVSSQ 10 VDD33 A B DQ[1] DQ[0] OE# DACK# UVDDQ UVSSQ XVDDQ XTALOUT AVDDQ RESETOUT B C DQ[4] DQ[3] DQ[2] XTALSLC[0] XTALSLC[1] NANDCFG WAKEUP TEST[1] GPIO[1] RESET# C D DQ[7] DQ[6] DQ[5] PVDDQ VDD GVDDQ TEST[0] GPIO[0] SD_D[1] SD_D[0] D E DQ[10] DQ[9] DQ[8] VGND VGND VGND VGND TEST[2] SD_D[3] SD_D[2] E F DQ[13] DQ[12] DQ[11] VGND VGND VGND VDD SD_CLK SD_D[5] SD_D[4] F G CE# DQ[15] DQ[14] VDD VDD VDD VDD SD_CMD SD_D[7] SD_D[6] G H A[5] A[6] A[7] PVDDQ SNVDDQ NAND_WE# SSVDDQ SD_POW NAND_IO[2] SD_WP H J A[3] CLK A[4] NAND_R/B# NAND_CE# NAND_ALE NAND_WP# NAND_IO[5] NAND_IO[3] NAND_IO[0] J K A[0] 1 A[1] 2 A[2] 3 NAND_RE# 4 NAND_CE2# 5 NAND_CLE 6 NAND_IO[7] 7 NAND_IO[6] 8 NAND_IO[4] 9 NAND_IO[1] 10 K Document #: 001-05898 Rev.*C Page 4 of 9 [+] Feedback ADVANCE INFORMATION CYWB012X Family Ordering Information Ordering Code Turbo-MTP Enabled Package Type Available Clock Input Frequencies (MHz) CYWB0124AB-BVXI CYWB0125AB-BVXI CYWB0124ABX-FDXI CYWB0125ABX-FDXI No Yes No Yes 100 VFBGA (Pb-free) 100 VFBGA (Pb-free) WLCSP (Pb-free) WLCSP (Pb-free) 19.2, 24, 26, 48 19.2, 24, 26, 48 19.2, 24, 26, 48 19.2, 24, 26, 48 This table contains advance information. Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY WB 012 X AB X - XX X I Temperature Range: I = Industrial Pb-free Package Type: XX = BV or FD BV = 100-ball VFBGA FD = WLCSP X = CSP; blank = BGA A generation Turbo MTP is enabled: X = 4 or 5 4 = No; 5 = Yes Antioch Bridge Family: West Bridge Company ID: CY = Cypress Document #: 001-05898 Rev.*C Page 5 of 9 [+] Feedback ADVANCE INFORMATION CYWB012X Family Package Diagram Figure 2. 100-pin VFBGA (6 × 6 × 1.0 mm) BZ100A 51-85209 *D Document #: 001-05898 Rev.*C Page 6 of 9 [+] Feedback ADVANCE INFORMATION CYWB012X Family Acronyms Acronym Description Document Conventions Units of Measure Symbol Unit of Measure DMA ECC HDD I/O MTP MMC PLL SLIM SLC USB VFBGA WLCSP CE-ATA direct memory access error correction codes hard disk drive input/output media transfer protocol multimedia card phase locked loop simultaneous link to independent media single level cell universal serial bus very fine-pitch ball grid array wafer level chip scale package consumer electronics-advanced technology attachment Mbps MHz mm V Mega bytes per second Mega Hertz milli meter Volts Document #: 001-05898 Rev.*C Page 7 of 9 [+] Feedback ADVANCE INFORMATION CYWB012X Family Document History Page Document Title: CYWB012X Family, West Bridge® Antioch™ Document Number: 001-05898 Rev. ECN No. Orig. of Change Submission Date Description of Change ** *A *B *C 410919 460471 2763925 3282406 QJL QJL, RUY OGC/AESA VSO See ECN See ECN 09/15/09 06/14/2011 New release Updated pin table, pin diagram Added Ordering Information table Added Ordering Code Definitions. Updated Package Diagram. Added Acronyms and Units of Measure. Updated in new template. Document #: 001-05898 Rev.*C Page 8 of 9 [+] Feedback ADVANCE INFORMATION Sales, Solutions, and Legal Information Worldwide Sales and Design Support CYWB012X Family Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-05898 Rev.*C Revised June 14, 2011 Page 9 of 9 West Bridge and SLIM are registered trademarks and Antioch is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback