CYWUSB6953_10

CYRF69103 Programmable Radio on Chip Low Power 1. PRoC™ LP Features ■ Single Device, Two Functions ❐ 8-bit Flash based MCU function and 2.4 GHz radio transceiver function in a single device. Flash Based Microcontroller Function ❐ M8C based 8-bit CPU, optimized for Human Interface Devices (HID) applications ❐ 256 Bytes of SRAM ❐ 8 Kbytes of Flash memory with EEPROM emulation ❐ In-System reprogrammable ❐ CPU speed up to 12 MHz ❐ 16-bit free running timer ❐ Low power wakeup timer ❐ 12-bit Programmable Interval Timer with interrupts ❐ Watchdog timer Industry leading 2.4 GHz Radio Transceiver Function ❐ Operates in the unlicensed worldwide Industrial, Scientific, and Medical (ISM) band (2.4 GHz to 2.483 GHz) ❐ DSSS data rates of up to 250 Kbps ❐ GFSK data rate of 1 Mbps ❐ –97 dBm receive sensitivity ■ Programmable output power up to +4 dBm Auto Transaction Sequencer (ATS) ❐ Framing CRC and Auto ACK ❐ Received Signal Strength Indication (RSSI) ❐ Automatic Gain Control (AGC) ❐ ❐ ■ Component Reduction ❐ Integrated 1.8V boost converter ❐ GPIOs that require no external components ❐ Operates off a single crystal Flexible I/O ❐ 2 mA source current on all GPIO pins. Configurable 8 mA or 50 mA/pin current sink on designated pins ❐ Each GPIO pin supports high impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs, and CMOS output ❐ Maskable interrupts on all I/O pins Operating Voltage from 1.8V to 3.6V DC Operating Temperature from 0 to 70°C Pb-free 40-Pin QFN Package Advanced Development Tools based on Cypress’s PSoC® Tools ■ ■ ■ ■ ■ ■ 2. Logic Block Diagram 47µF MOSI SCK nSS VCC 470nF VCC 10 µF VBat1 VBat0 VDD_MICRO RST L/D VBat2 VCC1 VCC2 VCC3 Vdd 470 nF VReg VIO RFp RFn RFbias Microcontroller Function P0_1,3,4,7 4 P1_0:2,6:7 5 P2_0:1 GND 2 P1.5/MOSI P1.4/SCK P1.3/nSS Radio Function IRQ/GPIO MISO/GPIO XOUT/GPIO PACTL/GPIO RESV GND Xtal ..... 12 MHz ....... Cypress Semiconductor Corporation Document #: 001-07611 Rev *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 26, 2010 [+] Feedback GND CYRF69103 3. Contents PRoC™ LP Features......................................................... 1 Logic Block Diagram........................................................ 1 Contents ............................................................................ 2 Applications ...................................................................... 3 Functional Description..................................................... 3 Functional Overview ......................................................... 3 2.4 GHz Radio Function .............................................. 3 Data Transmission Modes........................................... 3 Microcontroller Function .............................................. 3 Backward Compatibility ............................................... 4 DDR Mode................................................................... 4 SDR Mode.................................................................. 5 Pinouts .............................................................................. 6 Functional Block Overview.............................................. 7 2.4 GHz Radio............................................................. 7 Frequency Synthesizer................................................ 7 Baseband and Framer................................................. 7 Packet Buffers and Radio Configuration Registers ..... 8 Auto Transaction Sequencer (ATS) ............................ 8 Interrupts ..................................................................... 9 Clocks.......................................................................... 9 GPIO Interface ............................................................ 9 Power On Reset/Low Voltage Detect.......................... 9 Timers ......................................................................... 9 Power Management .................................................... 9 Low Noise Amplifier (LNA) and Received Signal Strength Indication (RSSI) ............................... 11 SPI Interface.................................................................... 11 3-Wire SPI Interface .................................................. 11 4-Wire SPI Interface .................................................. 11 SPI Communication and Transactions ...................... 12 SPI I/O Voltage References ...................................... 12 SPI Connects to External Devices ............................ 12 CPU Architecture............................................................ 12 CPU Registers........................................................... 13 Flags Register ........................................................... 13 Accumulator Register ................................................ 13 Index Register ........................................................... 14 Stack Pointer Register............................................... 14 CPU Program Counter High Register ....................... 14 CPU Program Counter Low Register ........................ 14 Addressing Modes .......................................................... 15 Source Immediate ..................................................... 15 Source Direct ............................................................. 15 Source Indexed ......................................................... 15 Destination Direct ...................................................... 15 Destination Indexed................................................... 16 Destination Direct Source Immediate........................ 16 Destination Indexed Source Immediate ..................... 16 Destination Direct Source Direct ............................... 16 Source Indirect Post Increment ................................. 17 Destination Indirect Post Increment .......................... 17 Instruction Set Summary ............................................... 18 Memory Organization ................................................. 19 Flash Program Memory Organization ....................... 19 Data Memory Organization ....................................... 20 Flash.......................................................................... 20 SROM........................................................................ 20 SROM Function Descriptions .................................... 21 Clocking .......................................................................... 24 SROM Table Read Description ................................. 25 Clock Architecture Description .................................. 26 CPU Clock During Sleep Mode ................................. 30 Reset................................................................................. 31 Power On Reset ........................................................ 32 Watchdog Timer Reset.............................................. 32 Sleep Mode...................................................................... 32 Sleep Sequence ........................................................ 32 Low Power in Sleep Mode......................................... 33 Wakeup Sequence .................................................... 33 Low Voltage Detect Control........................................... 35 POR Compare State ................................................. 36 ECO Trim Register .................................................... 36 General Purpose I/O Ports............................................. 37 Port Data Registers ................................................... 37 GPIO Port Configuration ........................................... 38 GPIO Configurations for Low Power Mode ............... 43 Serial Peripheral Interface (SPI)................................ 44 SPI Data Register...................................................... 45 SPI Configure Register.............................................. 45 SPI Interface Pins...................................................... 47 Timer Registers .............................................................. 47 Registers ................................................................... 47 Interrupt Controller......................................................... 50 Architectural Description ............................................ 50 Interrupt Processing .................................................. 51 Interrupt Latency ....................................................... 51 Interrupt Registers..................................................... 51 Microcontroller Function Register Summary ............. 55 Radio Function Register Summary............................... 57 Absolute Maximum Ratings .......................................... 58 DC Characteristics (T = 25×C) ....................................... 58 AC Characteristics ........................................................ 60 RF Characteristics.......................................................... 64 Ordering Information...................................................... 66 Package Handling........................................................... 66 Package Diagram............................................................ 66 Document History Page ................................................. 67 Sales, Solutions, and Legal Information ...................... 68 Worldwide Sales and Design Support....................... 68 Document #: 001-07611 Rev *F Page 2 of 68 [+] Feedback CYRF69103 4. Applications The CYRF69103 PRoC LP is targeted for the following applications: ■ The radio meets requirements: ■ the following worldwide regulatory Wireless HID devices: ❐ Mice ❐ Remote Controls ❐ Presenter tools ❐ Barcode scanners ❐ POS terminal General purpose wireless applications: ❐ Industrial applications ❐ Home automation ❐ White goods ❐ Consumer electronics ❐ Toys Europe: ❐ ETSI EN 301 489-1 V1.4.1 ❐ ETSI EN 300 328-1 V1.3.1 North America: ❐ FCC CFR 47 Part 15 Japan: ❐ ARIB STD-T66 ■ ■ ■ 6.2 Data Transmission Modes The radio supports four different data transmission modes: ■ ■ ■ ■ In GFSK mode, data is transmitted at 1 Mbps, without any DSSS In 8DR mode, 1 byte is encoded in each PN code symbol transmitted In DDR mode, 2 bits are encoded in each PN code symbol transmitted In SDR mode, a single bit is encoded in each PN code symbol transmitted 5. Functional Description PRoC LP devices are integrated radio and microcontroller functions in the same package to provide a dual-role single-chip solution. Communication between the microcontroller and the radio is through the radio’s SPI interface. 6. Functional Overview The CYRF69103 is a complete Radio System-on-Chip device, providing a complete RF system solution with a single device and a few discrete components. The CYRF69103 is designed to implement low cost wireless systems operating in the worldwide 2.4 GHz Industrial, Scientific, and Medical (ISM) frequency band (2.400 GHz to 2.4835 GHz). Both 64-chip and 32-chip data PN codes are supported. The four data transmission modes apply to the data after the Start of Packet (SOP). In particular, the packet length, data and CRC are all sent in the same mode. 6.3 Microcontroller Function The MCU function is an 8-bit Flash-programmable microcontroller. The instruction set is optimized specifically for HID and a variety of other embedded applications. The MCU function has up to 8 Kbytes of Flash for user’s code and up to 256 bytes of RAM for stack space and user variables. In addition, the MCU function includes a Watchdog timer, a vectored interrupt controller, a 16-bit Free Running Timer, and 12-bit Programmable Interrupt Timer. The microcontroller has 15 GPIO pins grouped into multiple ports. With the exception of the four radio function GPIOs, each GPIO port supports high impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs and CMOS output. Up to two pins support programmable drive strength of up to 50 mA. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port 0. GPIO Port 0 has two dedicated pins that have independent interrupt vectors (P0.3 - P0.4). The microcontroller features an internal oscillator. The PRoC LP includes a Watchdog timer, a vectored interrupt controller, a 12-bit programmable interval timer with configurable 1 ms interrupt and a 16-bit free running timer. In addition, the CYRF69103 IC has a Power Management Unit (PMU), which enables direct connection of the device to any battery voltage in the range 1.8V to 3.6V. The PMU conditions the battery voltage to provide the supply voltages required by the device and may supply external devices. 6.1 2.4 GHz Radio Function The SoC contains a 2.4 GHz 1 Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), and SPI interface for data transfer and device configuration. The radio supports 98 discrete 1 MHz channels (regulations may limit the use of some of these channels in certain jurisdictions). In DSSS modes the baseband performs DSSS spreading/despreading, while in GFSK Mode (1 Mb/s - GFSK) the baseband performs Start of Frame (SOF), End of Frame (EOF) detection, and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge (ACK) handshake packets whenever a valid packet is received. When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates, except SDR, enabling the implementation of mixed-rate systems in which different devices use different data rates. This also enables the implementation of dynamic data rate systems, which use high data rates at shorter distances and/or in a low moderate interference environment, and change to lower data rates at longer distances and/or in high interference environments. Document #: 001-07611 Rev *F Page 3 of 68 [+] Feedback CYRF69103 6.4 Backward Compatibility The CYRF69103 IC is fully interoperable with the main modes of the first generation Cypress radios namely the CYWUSB6934 -LS and CYWWUSB6935-LR devices. The 62.5 kbps mode is supported by selecting 32 chip DDR mode. Similarly, the 15.675 kbps mode is supported by selecting 64 chip SDR mode In this method, a suitably configured CYRF69103 IC device may transmit data to or receive data from a first generation device, or both. Backwards compatibility requires disabling the SOP, length, and CRC16 fields. This section provides the different configurations of the registers and firmware that enable a new generation radio to communicate with a first generation radio. There are two possible modes: SDR and DDR mode (8-DR and GFSK modes are not present in the first generation radio). The second generation radio must be initialized using the RadioInitAPI of the LP radio driver and then the following registers’ bits need to be configured to the given Byte values. Essentially, the following deactivates the added features of the second generation radio and takes it down to the level of the first generation radio. The data format, data rates, and the PN codes used are recognizable by the first generation radio. 6.5 DDR Mode Table 6-1. DDR Mode Register TX_CFG_ADR RX_CFG_ADR Value 0X16 0X4B 32 chip PN Code, DDR, PA = 6 AGC is enabled. LNA and attenuator are disabled. Fast turnaround is disabled, the device uses high side receive injection and Hi-Lo is disabled. Overwrite to receive buffer is enabled and the RX buffer is configured to receive eight bytes maximum. AutoACK is disabled. Forcing end state is disabled. The device is configured to transition to Idle mode after a Receive or Transmit. ACK timeout is set to 128 µs. All SOP and framing features are disabled. Disable LEN_EN=0 if EOP is needed. Disable Transmit CRC-16. The receiver rejects packets with a zero seed. The Rx CRC-16 Checker is disabled and the receiver accepts bad packets that do not match the seed in CRC_seed registers. This helps in communication with the first generation radio that does not have CRC capabilities. Set ALL SLOW. When set, the synthesizer settle time for all channels is the same as the slow channels in the first generation radio. Sets the number of allowed corrupted bits to 3. Sets the number of consecutive symbols for non-correlation to detect end of packet. AAAA are the two preamble bytes. Any other byte can also be written into the preamble register file. Recommended counts of the preamble bytes to be sent must be >4. Description XACT_CFG_ADR FRAMING_CFG_ADR TX_OVERRIDE_ADR RX_OVERRIDE_ADR 0X05 0X00 0X04 0X14 ANALOG_CTRL_ADR DATA32_THOLD_ADR EOP_CTRL_ADR PREAMBLE_ADR 0X01 0X03 0x01 0xAAAA05 Document #: 001-07611 Rev *F Page 4 of 68 [+] Feedback CYRF69103 6.6 SDR Mode Table 6-2. SDR Mode Register TX_CFG_ADR RX_CFG_ADR Value 0X3E 0X4B Description 64 chip PN code, SDR mode, PA = 6 AGC is enabled. LNA and attenuator are disabled. Fast turnaround is disabled, the device uses high side receive injection and Hi-Lo is disabled. Overwrite to receive buffer is enabled and RX buffer is configured to receive eight bytes maximum. Enables RXOW to allow new packets to be loaded into the receive buffer. This also enables the VALID bit which is used by the first generation radio’s error correction firmware. AutoACK is disabled. Forcing end state is disabled. The device is configured to transition to Idle mode after Receive or Transmit. ACK timeout is set to 128 µs. All SOP and framing features are disabled. Disable LEN_EN=0 if EOP is needed. Disable Transmit CRC-16. The receiver rejects packets with a zero seed. The RX CRC-16 checker is disabled and the receiver accepts bad packets that do not match the seed in the CRC_seed registers. This helps in communication with the first generation radio that does not have CRC capabilities. Set ALL SLOW. When set, the synthesizer settle time for all channels is the same as the slow channels in the first generation radio, for manual ACK consistency Sets the number of allowed corrupted bits to 7 which is close to the recommended 12% value. Sets the number of consecutive symbols for non-correlation to detect end of packet. AAAA are the two preamble bytes. Any other byte can also be written into the preamble register file. Recommended counts of the preamble bytes to be sent must be >8. XACT_CFG_ADR FRAMING_CFG_ADR TX_OVERRIDE_ADR RX_OVERRIDE_ADR 0X05 0X00 0X04 0X14 ANALOG_CTRL_ADR 0X01 DATA64_THOLD_ADR EOP_CTRL_ADR PREAMBLE_ADR 0X07 0xA1 0xAAAA09 Document #: 001-07611 Rev *F Page 5 of 68 [+] Feedback CYRF69103 7. Pinouts Figure 7-1. Pin Diagram PACTL / GPIO 31 VDD_1.8 36 VBAT0 39 VREG 40 P1.7 35 P0.7 38 P1.6 32 RST 34 L/D 37 Corner tabs VIO 33 P0.4 XTAL VCC P0.3 P0.1 VBAT1 VCC P2.1 VBAT2 1 2 3 4 5 6 7 8 9 * E-PAD Bottom Side 30 XOUT / GPIO 29 MISO / GPIO CYRF69103 WirelessUSB LP 28 P1.5 / MOSI 27 IRQ / GPIO 26 P1.4 / SCK 25 P1.3 / SS 24 P1.2 23 VDD_Micro 22 P1.1 21 P1.0 RFBIAS 10 11 RFP 12 GND 13 RFN 14 NC 15 P2.0 16 VCC 17 NC 18 NC 19 RESV 20 NC Table 7-1. Pin Definitions Pin 1 2 3, 7, 16 4 5 6 8 9 10 11 12 13 14, 17, 18, 20 15 19 21 22 23 24 25 26 27 28 29 30 Name P0.4 XTAL VCC P0.3 P0.1 Vbat1 P2.1 Vbat2 RFbias RFp GND RFn NC P2.0 RESV P1.0 P1.1 VDD_micro P1.2 P1.3 / nSS P1.4 / SCK IRQ P1.5 / MOSI MISO XOUT GPIO Reserved. Must connect to GND GPIO GPIO MCU supply connected to pin 40, max CPU 12 MHz GPIO Slave Select SPI Clock Radio Function Interrupt output, configure High, Low or as Radio GPIO MOSI pin from microcontroller function to radio function 3-wire SPI mode configured as Radio GPIO. In 4-wire SPI mode sends data to MCU function Buffered CLK, PACTL_n or Radio GPIO Page 6 of 68 Individually configured GPIO 12 MHz crystal 2.4V to 3.6V supply. Connected to pin 40 (0.047 μF bypass) Individually configured GPIO Individually configured GPIO Connect to 1.8V to 3.6V power supply, through 47 ohm series/1 μF shunt C GPIO. Port 2 Bit 1 Connected to1.8V to 3.6V main power supply, through 0.047 μF bypass C RF pin voltage reference Differential RF to or from antenna GND Differential RF to or from antenna Description Document #: 001-07611 Rev *F [+] Feedback CYRF69103 Table 7-1. Pin Definitions (continued) Pin 31 32 33 34 35 36 37 38 39 40 41 42 Name PACTL P1.6 VIO RST P1.7 VDD1.8 L/D P0.7 Vbat0 VREG E-pad Corner Tabs Control for external PA or Radio GPIO GPIO 1.8V to 3.6V to main power supply rail for Radio I/O Radio Reset. Connected to pin 40 with 0.47 μF. Must have a RST=HIGH event the very first time power is applied to the radio otherwise the state of the radio control registers is unknown GPIO Regulated logic bypass. Connected to 0.47 μF to GND Inductor/Diode connection for Boost. When Internal PMU is not being used connect L/D to GND. GPIO Connected to1.8V to 3.6V main power supply, through 0.047 μF bypass C Boost regulator output voltage feedback Must be connected to ground Do Not connect corner tabs Description 8. Functional Block Overview All the blocks that make up the PRoC LP are presented in this section. 8.3 Baseband and Framer The baseband and framer blocks provide the DSSS encoding and decoding, SOP generation and reception and CRC16 generation and checking, and EOP detection and length field. 8.3.1 Data Transmission Modes and Data Rates The SoC supports four different data transmission modes: ■ ■ ■ 8.1 2.4 GHz Radio The radio transceiver is a dual conversion low IF architecture optimized for power and range/robustness. The radio employs channel matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides up to +4 dBm transmit power, with an output power control range of 34 dB in seven steps. The supply current of the device is reduced as the RF output power is reduced. Table 8-1. Internal PA Output Power Step Table PA Setting 7 6 5 4 3 2 1 0 Typical Output Power (dBm) +4 0 –5 –10 –15 –20 –25 –30 In GFSK mode, data is transmitted at 1 Mbps, without any DSSS. In 8DR mode, 8 bits are encoded in each DATA_CODE_ADR derived code symbol transmitted. In DDR mode, 2 bits are encoded in each DATA_CODE_ADR derived code symbol transmitted (as in the CYWUSB6934 DDR mode). In SDR mode, 1 bit is encoded in each DATA_CODE_ADR derived code symbol transmitted (as in the CYWUSB6934 standard modes). ■ Both 64-chip and 32-chip DATA_CODE_ADR codes are supported. The four data transmission modes apply to the data after the SOP. In particular the length, data, and CRC16 are all sent in the same mode. In general, lower data rates reduces packet error rate in any given environment. The CYRF69103 IC supports the following data rates: ■ ■ ■ ■ ■ ■ 1000 kbps (GFSK) 250 kbps (32-chip 8DR) 125 kbps (64-chip 8DR) 62.5 kbps (32-chip DDR) 31.25 kbps (64-chip DDR) 15.625 kbps (64-chip SDR) 8.2 Frequency Synthesizer Before transmission or reception may commence, it is necessary for the frequency synthesizer to settle. The settling time varies depending on channel; 25 fast channels are provided with a maximum settling time of 100 μs. The “fast channels” ( 3 MHz) Channel Selectivity C/I > 3 MHz Out-of-Band Blocking 30 MHz–12.75 MHz[19] Intermodulation Receive Spurious Emission 800 MHz 1.6 GHz 3.2 GHz Transmitter (T = 25°C, VCC = 3.0V, fOSC = 12.000 MHz) Maximum RF Transmit Power Maximum RF Transmit Power Maximum RF Transmit Power Maximum RF Transmit Power RF Power Control Range RF Power Range Control Step Size Frequency Deviation Min Frequency Deviation Max Error Vector Magnitude (FSK error) Occupied Bandwidth BER 1E-3 CER 1E-3 BER 1E-3, ALL SLOW = 1 Notes 19. Exceptions F/3 & 5C/3. 20. When using an external switching regulator to power the radio, care must be taken to keep the switching frequency well away from the IF frequency of 1MHz. Document #: 001-07611 Rev *F Page 64 of 68 [+] Feedback CYRF69103 Table 26-1. Radio Parameters (continued) Parameter Description Transmit Spurious Emission (PA = 7) In-band Spurious Second Channel Power (±2 MHz) In-band Spurious Third Channel Power (>3 MHz) Non-Harmonically Related Spurs (8.000 GHz) Non-Harmonically Related Spurs (1.6 GHz) Non-Harmonically Related Spurs (3.2 GHz) Harmonic Spurs (Second Harmonic) Harmonic Spurs (Third Harmonic) Fourth and Greater Harmonics Power Management (Crystal PN# eCERA GF-1200008) Crystal Start to 10ppm Crystal Start to IRQ Synth Settle Synth Settle Synth Settle Link Turnaround Time Link Turnaround Time Link Turnaround Time Link Turnaround Time Max. packet length XSIRQ EN = 1 Slow channels Medium channels Fast channels GFSK 250 kbps 125 kbps