FM16W08
64-Kbit (8 K × 8) Wide Voltage Bytewide
F-RAM Memory
64-Kbit (8 K × 8) Wide Voltage Bytewide F-RAM Memory
Features
■
64-Kbit ferroelectric random access memory (F-RAM) logically
organized as 8 K × 8
14
❐ High-endurance 100 trillion (10 ) read/writes
❐ 151-year data retention (see the Data Retention and
Endurance table)
❐ NoDelay™ writes
❐ Advanced high-reliability ferroelectric process
■
SRAM and EEPROM compatible
❐ Industry-standard 8 K × 8 SRAM and EEPROM pinout
❐ 70-ns access time, 130-ns cycle time
■
Superior to battery-backed SRAM modules
❐ No battery concerns
❐ Monolithic reliability
❐ True surface mount solution, no rework steps
❐ Superior for moisture, shock, and vibration
❐ Resistant to negative voltage undershoots
■
■
Low power consumption
❐ Active current 12 mA (max)
❐ Standby current 20 A (typ)
■
Industrial temperature: –40 C to +85 C
■
28-pin small outline integrated circuit (SOIC) package
■
Restriction of hazardous substances (RoHS) compliant
Functional Overview
The FM16W08 is a 8 K × 8 nonvolatile memory that reads and
writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM16W08 operation is similar to that of other RAM devices
and therefore, it can be used as a drop-in replacement for a
standard SRAM in a system. Minimum read and write cycle times
are equal. The F-RAM memory is nonvolatile due to its unique
ferroelectric memory process. These features make the
FM16W08 ideal for nonvolatile memory applications requiring
frequent or rapid writes.
The device is available in a 28-pin SOIC surface mount package.
Device specifications are guaranteed over the industrial
temperature range –40 °C to +85 °C.
Wide voltage operation: VDD = 2.7 V to 5.5 V
For a complete list of related documentation, click here.
A12-0
Address Latch and Decoder
Logic Block Diagram
A 12-0
8Kx8
F-RAM Array
CE
WE
Control
Logic
I/O Latch & Bus Driver
DQ 7-0
OE
Cypress Semiconductor Corporation
Document Number: 001-86210 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 8, 2015
FM16W08
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
Memory Architecture ................................................... 4
Memory Operation ....................................................... 4
Read Operation ........................................................... 4
Write Operation ........................................................... 4
Pre-charge Operation .................................................. 4
Endurance ......................................................................... 4
F-RAM Design Considerations ........................................ 5
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
DC Electrical Characteristics .......................................... 7
Data Retention and Endurance ....................................... 7
Capacitance ...................................................................... 8
Thermal Resistance .......................................................... 8
AC Test Conditions .......................................................... 8
AC Switching Characteristics ......................................... 9
SRAM Read Cycle ...................................................... 9
Document Number: 001-86210 Rev. *F
SRAM Write Cycle ..................................................... 10
Power Cycle Timing ....................................................... 12
Functional Truth Table ................................................... 13
Ordering Information ...................................................... 14
Ordering Code Definitions ......................................... 14
Package Diagram ............................................................ 15
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
Page 2 of 18
FM16W08
Pinout
Figure 1. 28-pin SOIC pinout
NC
A12
A7
1
28
VDD
2
3
27
26
WE
NC
A6
4
5
25
24
23
A8
22
21
OE
A10
20
CE
DQ7
A5
A4
A3
6
7
28-pin SOIC
(x 8)
A2
A1
8
9
Top view
(not to scale)
A0
10
11
19
18
12
13
17
16
14
15
DQ0
DQ1
DQ2
VSS
A9
A11
DQ6
DQ5
DQ4
DQ3
Pin Definitions
Pin Name
I/O Type
A12–A0
Input
DQ7–DQ0
Description
Address inputs: The 13 address lines select one of 8,192 bytes in the F-RAM array.
Input/Output Data I/O Lines: 8-bit bidirectional data bus for accessing the F-RAM array.
WE
Input
Write Enable: A write cycle begins when WE is asserted. Asserting WE LOW causes the FM16W08 to
write the contents of the data bus to the address location latched by the falling edge of CE.
CE
Input
Chip Enable: The device is selected when CE is LOW. Asserting CE LOW causes the address to be
latched internally. Address changes that occur after CE goes LOW will be ignored until the next falling
edge occurs.
OE
Input
Output Enable: When OE is LOW, the FM16W08 drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
VSS
Ground
VDD
NC
Ground for the device. Must be connected to the ground of the system.
Power supply Power supply input to the device.
No connect
No connect. This pin is not connected to the die.
Document Number: 001-86210 Rev. *F
Page 3 of 18
FM16W08
Device Operation
The FM16W08 is a bytewide F-RAM memory logically organized
as 8,192 × 8 and accessed using an industry-standard parallel
interface. All data written to the part is immediately nonvolatile
with no delay. Functional operation of the F-RAM memory is the
same as SRAM type devices, except the FM16W08 requires a
falling edge of CE to start each memory cycle. See the
Functional Truth Table on page 13 for a complete description of
read and write modes.
Memory Architecture
Users access 8,192 memory locations, each with 8 data bits
through a parallel interface. The complete 13-bit address
specifies each of the 8,192 bytes uniquely. The F-RAM array is
organized as 1024 rows of 8-bytes each. This row segmentation
has no effect on operation, however the user can group data into
blocks by its endurance characteristics as explained in the
Endurance section.
The cycle time is the same for read and write memory
operations. This simplifies memory controller logic and timing
circuits. Likewise the access time is the same for read and write
memory operations. When CE is deasserted HIGH, a pre-charge
operation begins, and is required of every memory cycle. Thus
unlike SRAM, the access and cycle times are not equal. Writes
occur immediately at the end of the access with no delay. Unlike
an EEPROM, it is not necessary to poll the device for a ready
condition since writes occur at bus speed.
It is the user’s responsibility to ensure that VDD remains within
datasheet tolerances to prevent incorrect operation. Also proper
voltage level and timing relationships between VDD and CE must
be maintained during power-up and power-down events. See
“Power Cycle Timing” on page 12.
Memory Operation
The FM16W08 is designed to operate in a manner similar to
other bytewide memory products. For users familiar with
BBSRAM, the performance is comparable but the bytewide
interface operates in a slightly different manner as described
below. For users familiar with EEPROM, the differences result
from the higher write performance of F-RAM technology
including NoDelay writes and much higher write endurance.
Read Operation
A read operation begins on the falling edge of CE. At this time,
the address bits are latched and a memory cycle is initiated.
Once started, a full memory cycle must be completed internally
even if CE goes inactive. Data becomes available on the bus
after the access time is met.
After the address has been latched, the address value may be
changed upon satisfying the hold time parameter. Unlike an
SRAM, changing address values will have no effect on the
memory operation after the address is latched.
The FM16W08 will drive the data bus when OE is asserted LOW
and the memory access time is met. If OE is asserted after the
memory access time is met, the data bus will be driven with valid
Document Number: 001-86210 Rev. *F
data. If OE is asserted before completing the memory access,
the data bus will not be driven until valid data is available. This
feature minimizes supply current in the system by eliminating
transients caused by invalid data being driven to the bus. When
OE is deasserted HIGH, the data bus will remain in a HI-Z state.
Write Operation
In the FM16W08, writes occur in the same interval as reads. The
FM16W08 supports both CE and WE controlled write cycles. In
both cases, the address is latched on the falling edge of CE.
In a CE-controlled write, the WE signal is asserted before
beginning the memory cycle. That is, WE is LOW when the
device is activated with the chip enable. In this case, the device
begins the memory cycle as a write. The FM16W08 will not drive
the data bus regardless of the state of OE.
In a WE-controlled write, the memory cycle begins on the falling
edge of CE. The WE signal falls after the falling edge of CE.
Therefore, the memory cycle begins as a read. The data bus will
be driven according to the state of OE until WE falls. The CE and
WE controlled write timing cases are shown in the page 11 and
page 12.
Write access to the array begins asynchronously after the
memory cycle is initiated. The write access terminates on the
rising edge of WE or CE, whichever comes first. A valid write
operation requires the user to meet the access time specification
before deasserting WE or CE. The data setup time indicates the
interval during which data cannot change before the end of the
write access.
Unlike other nonvolatile memory technologies, there is no write
delay with F-RAM. Because the read and write access times of
the underlying memory are the same, the user experiences no
delay through the bus. The entire memory operation occurs in a
single bus cycle. Therefore, any operation including read or write
can occur immediately following a write. Data polling, a
technique used with EEPROMs to determine if a write is
complete, is unnecessary.
Pre-charge Operation
The pre-charge operation is an internal condition in which the
memory state is prepared for a new access. All memory cycles
consist of a memory access and a pre-charge. Pre-charge is
user-initiated by driving the CE signal HIGH. It must remain
HIGH for at least the minimum pre-charge time, tPC.
The user determines the beginning of this operation since a
pre-charge will not begin until CE rises. However, the device has
a maximum CE LOW time specification that must be satisfied.
Endurance
Internally, a F-RAM operates with a read and restore
mechanism. Therefore, each read and write cycle involves a
change of state. The memory architecture is based on an array
of rows and columns. Each read or write access causes an
endurance cycle for an entire row. In the FM16W08, a row is 64
bits wide. Every 8-byte boundary marks the beginning of a new
row. Endurance can be optimized by ensuring frequently
Page 4 of 18
FM16W08
falling edge of CE, users cannot ground it as they might with
SRAM.
accessed data is located in different rows. Regardless, F-RAM
offers substantially higher write endurance than other nonvolatile
memories. The rated endurance limit of 1014 cycles will allow
150,000 accesses per second to the same row for over 20 years.
Users who are modifying existing designs to use F-RAM should
examine the memory controller for timing compatibility of
address and control pins. Each memory access must be
qualified with a LOW transition of CE. In many cases, this is the
only change required. An example of the signal relationships is
shown in Figure 2 below. Also shown is a common SRAM signal
relationship that will not work for the FM16W08.
F-RAM Design Considerations
When designing with F-RAM for the first time, users of SRAM will
recognize a few minor differences. First, bytewide F-RAM
memories latch each address on the falling edge of chip enable.
This allows the address bus to change after starting the memory
access. Since every access latches the memory address on the
The reason for CE to strobe for each address is twofold: it latches
the new address and creates the necessary pre-charge period
while CE is HIGH.
Figure 2. Chip Enable and Memory Address Relationships
Valid Strobing of CE
CE
F-RAM
Signaling
Address
A1
A2
Data
D1
D2
Invalid Strobing of CE
CE
SRAM
Signaling
Address
A1
Data
A second design consideration relates to the level of VDD during
operation. Battery-backed SRAMs are forced to monitor VDD in
order to switch to battery backup. They typically block user
access below a certain VDD level in order to prevent loading the
battery with current demand from an active SRAM. The user can
be abruptly cut off from access to the nonvolatile memory in a
power down situation with no warning or indication.
F-RAM memories do not need this system overhead. The
memory will not block access at any VDD level that complies with
the specified operating range. The user should take measures to
prevent the processor from accessing memory when VDD is
out-of-tolerance. The common design practice of holding a
processor in reset during power-down may be sufficient. It is
recommended that chip enable is pulled HIGH and allowed to
track VDD during power-up and power-down cycles. It is the
user’s responsibility to ensure that chip enable is HIGH to
prevent accesses below VDD min. (2.7 V).
A2
D1
D2
tristates during the reset condition. The pull-up resistor value
should be chosen to ensure the CE pin tracks VDD to a high
enough value, so that the current drawn when CE is LOW is not
an issue.
Figure 3. Use of Pull-up Resistor on CE
VDD
FM16W08
CE
WE
MCU / MPU
OE
A 12-0
DQ 7-0
Figure 3 shows a pull-up resistor on CE, which will keep the pin
HIGH during power cycles, assuming the MCU / MPU pin
Document Number: 001-86210 Rev. *F
Page 5 of 18
FM16W08
Note that if CE is tied to ground, the user must be sure WE is not
LOW at power-up or power-down events. If the chip is enabled
and WE is LOW during power cycles, data will be corrupted.
Figure 4 shows a pull-up resistor on WE, which will keep the pin
HIGH during power cycles, assuming the MCU / MPU pin
tristates during the reset condition. The pull-up resistor value
should be chosen to ensure the WE pin tracks VDD to a high
enough value, so that the current drawn when WE is LOW is not
an issue.
Figure 4. Use of Pull-up Resistor on WE
VDD
FM16W08
CE
WE
MCU / MPU
OE
A 12-0
DQ 7-0
Document Number: 001-86210 Rev. *F
Page 6 of 18
FM16W08
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –55 C to +125 C
Maximum accumulated storage time
At 125 °C ambient temperature ................................. 1000 h
At 85 °C ambient temperature ................................ 10 Years
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 C
DC output current (1 output at a time, 1s duration) .... 15 mA
Static discharge voltage
Human Body Model (AEC-Q100-002 Rev. E) ............ 4 kV
Charged Device Model (AEC-Q100-011 Rev. B) .. 1.25 kV
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Machine Model (AEC-Q100-003 Rev. E) ................. 300 V
Supply voltage on VDD relative to VSS ........–1.0 V to + 7.0 V
Latch-up current ................................................... > 140 mA
Voltage applied to outputs
in High Z state .................................... –0.5 V to VDD + 0.5 V
Operating Range
Range
Input voltage .......... –1.0 V to + 7.0 V and VIN < VDD + 1.0 V
Industrial
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Ambient Temperature (TA)
VDD
–40 C to +85 C
2.7 V to 5.5 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min
Typ [1]
Max
Unit
2.7
3.3
5.5
V
VDD
Power supply voltage
IDD
VDD supply current
VDD = 5.5 V, CE cycling at min. cycle time. All
inputs toggling at CMOS levels
(0.2 V or VDD – 0.2 V), all DQ pins unloaded.
–
–
12
mA
ISB
Standby current
VDD = 5.5 V, CE at VIH, All other pins are static
and at CMOS levels (0.2 V or VDD – 0.2 V)
–
20
50
µA
ILI
Input leakage current
VIN between VDD and VSS
–
–
+1
µA
ILO
Output leakage current
VOUT between VDD and VSS
–
–
+1
µA
VIH
Input HIGH voltage
0.7 × VDD
–
VDD + 0.3
V
VIL
Input LOW voltage
– 0.3
–
0.3 × VDD
V
VOH1
Output HIGH voltage
IOH = –1.0 mA, VDD > 2.7 V
2.4
–
–
V
VOH2
Output HIGH voltage
IOH = –100 µA
VDD – 0.2
–
–
V
VOL1
Output LOW voltage
IOL = 2 mA, VDD > 2.7 V
–
–
0.4
V
VOL2
Output LOW voltage
IOL = 150 µA
–
–
0.2
V
Data Retention and Endurance
Parameter
TDR
NVC
Description
Data retention
Endurance
Test condition
At +85 C
Min
Max
Unit
10
–
Years
At +75 C
38
–
At +65 C
151
–
Over operating temperature
1014
–
Cycles
Note
1. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.
Document Number: 001-86210 Rev. *F
Page 7 of 18
FM16W08
Capacitance
Parameter
Description
Test Conditions
CI/O
Input/Output capacitance (DQ)
CIN
Input capacitance
TA = 25 C, f = 1 MHz, VDD = VDD(Typ)
Max
Unit
8
pF
6
pF
Thermal Resistance
Description
Parameter
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
28-pin SOIC
Unit
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, in accordance with EIA/JESD51.
58
C/W
26
C/W
AC Test Conditions
Input pulse levels .................................10% and 90% of VDD
Input rise and fall times (10%–90%) ........................... < 5 ns
Input and output timing reference levels ................... 0.5 VDD
Output load capacitance ............................................. 100 pF
Figure 5. AC Test Loads
919
5.5 V
R1
OUTPUT
CL
100 pF
Document Number: 001-86210 Rev. *F
R2
497
Page 8 of 18
FM16W08
AC Switching Characteristics
Over the Operating Range
Parameters [2]
Cypress
Parameter
VDD = 2.7 V to 3.0 V
Description
Alt Parameter
VDD = 3.0 V to 5.5 V
Min
Max
Min
Max
Unit
SRAM Read Cycle
tCE
tACE
Chip enable access time
–
80
–
70
ns
tCA
–
Chip enable active time
80
–
70
–
ns
tRC
–
Read cycle time
145
–
130
–
ns
tPC
–
Pre-charge time
65
–
60
–
ns
tAS
tSA
Address setup time
0
–
0
–
ns
tAH
tHA
Address hold time
15
–
15
–
ns
tOE
tDOE
Output enable access time
–
15
–
12
ns
tHZ[3, 4]
tHZCE
Chip Enable to output HI-Z
–
15
–
15
ns
tOHZ[3, 4]
tHZOE
Output enable HIGH to output HI-Z
–
15
–
15
ns
Notes
2. Test conditions assume a signal transition time of 5 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 10% and 90% of VDD, output loading of the
specified IOL/IOH and load capacitance shown in AC Test Conditions on page 8.
3. tHZ and tOHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
4. This parameter is characterized but not 100% tested.
Document Number: 001-86210 Rev. *F
Page 9 of 18
FM16W08
AC Switching Characteristics (continued)
Over the Operating Range
Parameters [2]
Cypress
Parameter
VDD = 2.7 V to 3.0 V
Description
Alt Parameter
VDD = 3.0 V to 5.5 V
Min
Max
Min
Max
Unit
SRAM Write Cycle
tWC
tWC
Write cycle time
145
–
130
–
ns
tCA
–
Chip enable active time
80
–
70
–
ns
tCW
tSCE
Chip enable to write enable HIGH
80
–
70
–
ns
tPC
–
Pre-charge time
65
–
60
–
ns
tWP
tPWE
Write enable pulse width
50
–
40
–
ns
tAS
tSA
Address setup time
0
–
0
–
ns
tAH
tHA
Address hold time
15
–
15
–
ns
tDS
tSD
Data input setup time
40
–
30
–
ns
tHD
Data input hold time
0
–
0
–
ns
tHZWE
Write enable LOW to output HI-Z
–
15
–
15
ns
tWX[6]
–
Write enable HIGH to output driven
10
–
10
–
ns
tHZ[5]
–
Chip enable to output HI-Z
–
15
–
15
ns
tWS[7]
tWH[7]
–
Write enable to CE LOW setup time
0
–
0
–
ns
–
Write enable to CE HIGH hold time
0
–
0
–
ns
tDH
tWZ
[5, 6]
Notes
5. tWZ and tHZ is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
6. This parameter is characterized but not 100% tested.
7. The relationship between CE and WE determines if a CE or WE controlled write occurs.
Document Number: 001-86210 Rev. *F
Page 10 of 18
FM16W08
Figure 6. Read Cycle Timing
tRC
tCA
tPC
CE
tAH
tAS
A12-0
tOE
OE
tOHZ
DQ7-0
tCE
tHZ
Figure 7. Write Cycle Timing 1 (CE Controlled)
tWC
tCA
tPC
CE
tAS
tAH
A12-0
tWS
tWH
WE
OE
tDS
tDH
DQ 7-0
Document Number: 001-86210 Rev. *F
Page 11 of 18
FM16W08
Figure 8. Write Cycle Timing 2 (WE Controlled)
tWC
tCA
tPC
tC W
CE
tAH
tAS
A12-0
tWS
tWH
tWP
WE
OE
tWZ
tWX
DQ7-0 (out)
tDH
tDS
DQ7-0 (in)
Power Cycle Timing
Over the Operating Range
Parameter
tPU
tPD
tVR
[8]
tVF[8]
Description
Min
Max
Unit
Power-up (after VDD min. is reached) to first access time
10
–
ms
Last write (WE HIGH) to power down time
0
–
µs
VDD power-up ramp rate
30
–
µs/V
VDD power-down ramp rate
30
–
µs/V
Figure 9. Power Cycle Timing
VDD
VDD min
VDD min
t VR
t VF
t PU
t PD
Access Allowed
VIH (min)
VIL (max)
Note
8. Slope measured at any point on the VDD waveform.
Document Number: 001-86210 Rev. *F
Page 12 of 18
FM16W08
Functional Truth Table
Operation [9, 10]
CE
WE
H
X
Standby/Pre-charge
↓
X
Latch Address (and begin write if WE = LOW)
L
H
Read
L
↓
Write
Notes
9. H = Logic HIGH, L = Logic LOW, V = Valid Data, X = Don't Care, ↓ = toggle LOW, ↑ = toggle HIGH.
10. The OE pin controls only the DQ output buffers.
Document Number: 001-86210 Rev. *F
Page 13 of 18
FM16W08
Ordering Information
Package Diagram
Ordering Code
Package Type
FM16W08-SG
51-85026
28-pin SOIC
FM16W08-SGTR
51-85026
28-pin SOIC
Operating
Range
Industrial
All the above parts are Pb-free.
Ordering Code Definitions
FM 16 W
08
-
SG TR
Option:
blank = Standard; TR = Tape and Reel
Package Type:
SG = 28-pin SOIC
I/O Width: × 8
Voltage: 2.7 V to 5.5 V
64-kbit Parallel F-RAM
Cypress
Document Number: 001-86210 Rev. *F
Page 14 of 18
FM16W08
Package Diagram
Figure 10. 28-pin SOIC Package Outline, 51-85026
51-85026 *H
Document Number: 001-86210 Rev. *F
Page 15 of 18
FM16W08
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CPU
Central Processing Unit
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
JEDEC
Joint Electron Devices Engineering Council
Hz
hertz
JESD
JEDEC Standards
kHz
kilohertz
EIA
Electronic Industries Alliance
k
kilohm
F-RAM
Ferroelectric Random Access Memory
MHz
megahertz
I/O
Input/Output
A
microampere
MCU
Microcontroller Unit
F
microfarad
MPU
Microprocessor Unit
s
microsecond
RoHS
Restriction of Hazardous Substances
mA
milliampere
R/W
Read and Write
ms
millisecond
SOIC
Small Outline Integrated Circuit
M
megaohm
ns
nanosecond
SRAM
Static Random Access Memory
ohm
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-86210 Rev. *F
Symbol
Unit of Measure
Page 16 of 18
FM16W08
Document History Page
Document Title: FM16W08, 64-Kbit (8 K × 8) Wide Voltage Bytewide F-RAM Memory
Document Number: 001-86210
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
3912933
GVCH
02/25/2013
New spec
*A
4000965
GVCH
05/15/2013
Added Appendix A - Errata for FM16W08
*B
4045491
GVCH
06/30/2013
All errata items are fixed and the errata is removed.
*C
4274813
GVCH
03/10/2014
Converted to Cypress standard format
Changed datasheet status from “Preliminary” to “Final”.
Replaced A14-A0 with A12-A0 in all instances across the document.
Updated Maximum Ratings:
- Removed Moisture Sensitivity Level (MSL)
- Added junction temperature and latch up current
Updated Data Retention and Endurance.
Added Thermal Resistance.
Removed Package Marking Scheme (top mark)
*D
4562106
GVCH
11/05/2014
Added related documentation hyperlink in page 1.
Updated package diagram 51-85026 to current version.
*E
4591214
GVCH
12/09/2014
Fixed typo:
Changed title of Figure 6 from “Read Cycle Timing 1” to “Read Cycle Timing”.
Changed title of Figure 7 from “Read Cycle Timing 2 (CE Controlled)” to
“Write Cycle Timing 1 (CE Controlled)”.
*F
4881509
ZSK / PSR
09/08/2015
Updated Maximum Ratings:
Removed “Maximum junction temperature”.
Added “Maximum accumulated storage time”.
Added “Ambient temperature with power applied”.
Updated to new template.
Document Number: 001-86210 Rev. *F
Description of Change
Page 17 of 18
FM16W08
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© Cypress Semiconductor Corporation, 2013-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
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Document Number: 001-86210 Rev. *F
Revised September 8, 2015
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