FM24V02A-GTR

FM24V02A 256-Kbit (32K × 8) Serial (I2C) F-RAM 256-Kbit (32K × 8) Serial (I2C) F-RAM Features ■ Functional Description 256-Kbit ferroelectric random access memory (F-RAM) logically organized as 32K × 8 14 ❐ High-endurance 100 trillion (10 ) read/writes ❐ 151-year data retention (See the Data Retention and Endurance table) ❐ NoDelay™ writes ❐ Advanced high-reliability ferroelectric process 2 ■ Fast two-wire serial interface (I C) [1] ❐ Up to 3.4-MHz frequency ❐ Direct hardware replacement for serial EEPROM ❐ Supports legacy timings for 100 kHz and 400 kHz ■ Device ID ❐ Manufacturer ID and Product ID ■ Low power consumption ❐ 175-A active current at 100 kHz ❐ 150-A standby current ❐ 8-A sleep mode current ■ Low-voltage operation: VDD = 2.0 V to 3.6 V ■ Industrial temperature: –40 C to +85 C ■ 8-pin small outline integrated circuit (SOIC) package ■ Restriction of hazardous substances (RoHS) compliant The FM24V02A is a 256-Kbit nonvolatile memory employing an advanced ferroelectric process. An F-RAM is nonvolatile and performs reads and writes similar to a RAM. It provides reliable data retention for 151 years while eliminating the complexities, overhead, and system-level reliability problems caused by EEPROM and other nonvolatile memories. Unlike EEPROM, the FM24V02A performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte is successfully transferred to the device. The next bus cycle can commence without the need for data polling. In addition, the product offers substantial write endurance compared with other nonvolatile memories. F-RAM also exhibits much lower power during writes than EEPROM because write operations do not require an internally elevated power supply voltage for write circuits. The FM24V02A is capable of supporting 1014 read/write cycles, or 100 million times more write cycles than EEPROM. These capabilities make the FM24V02A ideal for nonvolatile memory applications, requiring frequent or rapid writes. Examples range from data logging, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writing with less overhead for the system. The FM24V02A provides substantial benefits to users of serial EEPROM as a hardware drop-in replacement. The device incorporates a read-only Device ID that allows the host to determine the manufacturer, product density, and product revision. The device specifications are guaranteed over an industrial temperature range of –40 C to +85 C. For a complete list of related resources, click here. Logic Block Diagram Counter Address Latch 15 32 K x 8 F-RAM Array 8 Serial to Parallel Converter SDA Data Latch 8 8 SCL Device ID and Manufacturer ID Control Logic WP A0-A2 Note 1. The FM24V02A does not meet the NXP I2C specification in the Fast-mode Plus (Fm+, 1 MHz) for IOL and in the High Speed Mode (Hs-mode, 3.4 MHz) for Vhys. Refer to the DC Electrical Characteristics table for more details. Cypress Semiconductor Corporation Document Number: 001-90839 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 11, 2017 FM24V02A Contents Pinout ................................................................................ 3 Pin Definitions .................................................................. 3 Functional Overview ........................................................ 4 Memory Architecture ........................................................ 4 Two-wire Interface ............................................................ 4 STOP Condition (P) ..................................................... 5 START Condition (S) ................................................... 5 Data/Address Transfer ................................................ 5 Acknowledge / No-Acknowledge ................................. 5 High Speed Mode (Hs-mode) ...................................... 6 Slave Device Address ................................................. 6 Addressing Overview .................................................. 6 Data Transfer .............................................................. 7 Memory Operation ............................................................ 7 Write Operation ........................................................... 7 Read Operation ........................................................... 8 Sleep Mode ................................................................. 9 Device ID ......................................................................... 10 Maximum Ratings ........................................................... 11 Operating Range ............................................................. 11 DC Electrical Characteristics ........................................ 11 Document Number: 001-90839 Rev. *I Data Retention and Endurance ..................................... 12 Capacitance .................................................................... 12 Thermal Resistance ........................................................ 12 AC Test Loads and Waveforms ..................................... 12 AC Test Conditions ........................................................ 12 AC Switching Characteristics ....................................... 13 Power Cycle Timing ....................................................... 14 Ordering Information ...................................................... 15 Ordering Code Definitions ......................................... 15 Package Diagram ............................................................ 16 Acronyms ........................................................................ 17 Document Conventions ................................................. 17 Units of Measure ....................................................... 17 Document History Page ................................................. 18 Sales, Solutions, and Legal Information ...................... 19 Worldwide Sales and Design Support ....................... 19 Products .................................................................... 19 PSoC®Solutions ....................................................... 19 Cypress Developer Community ................................. 19 Technical Support ..................................................... 19 Page 2 of 19 FM24V02A Pinout Figure 1. 8-pin SOIC Pinout A0 1 A1 2 A2 3 VSS 4 Top View not to scale 8 VDD 7 WP 6 SCL 5 SDA Pin Definitions Pin Name I/O Type Description A0-A2 Input Device Select Address 0-2. These pins are used to select one of up to eight devices of the same type on the same two-wire bus. To select the device, the address value on the three pins must match the corresponding bits contained in the slave address. The address pins are pulled down internally. SDA Input/Output Serial Data Address. This is a bidirectional pin for the two-wire interface. It is open-drain and is intended to be wire-AND'd with other devices on the two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the output driver includes slope control for falling edges. An external pull-up resistor is required. SCL Input Serial Clock. The serial clock pin for the two-wire interface. Data is clocked out of the part on the falling edge, and into the device on the rising edge. The SCL input also incorporates a Schmitt trigger input for noise immunity. WP Input Write Protect. When tied to VDD, addresses in the entire memory map will be write-protected. When WP is connected to ground, all addresses are write enabled. This pin is pulled down internally. VSS Power supply Ground for the device. Must be connected to the ground of the system. VDD Power supply Power supply input to the device. Document Number: 001-90839 Rev. *I Page 3 of 19 FM24V02A Functional Overview Two-wire Interface The FM24V02A is a serial F-RAM memory. The memory array is logically organized as 32,768 × 8 bits and is accessed using a two-wire (I2C) interface. The functional operation of the F-RAM is similar to serial EEPROM. The major difference between the FM24V02A and a serial EEPROM with the same pinout is the F-RAM's superior write performance, high endurance, and low power consumption. The FM24V02A employs a bidirectional two-wire bus protocol using few pins or board space. Figure 2 illustrates a typical system configuration using the FM24V02A in a microcontroller-based system. The two-wire bus is familiar to many users but is described in this section. By convention, any device that is sending data to the bus is the transmitter while the target device for this data is the receiver. The device that is controlling the bus is the master. The master is responsible for generating the clock signal for all operations. Any device on the bus that is being controlled is a slave. The FM24V02A is always a slave device. Memory Architecture When accessing the FM24V02A, the user addresses 32K locations of eight data bits each. These eight data bits are shifted in or out serially. The addresses are accessed using the two-wire protocol, which includes a slave address (to distinguish other non-memory devices) and a two-byte address. The upper MSB bit of the address range is 'don't care' value. The complete address of 15 bits specifies each byte address uniquely. The bus protocol is controlled by transition states in the SDA and SCL signals. There are four conditions including START, STOP, data bit, or acknowledge. Figure 3 and Figure 4 on page 5 illustrate the signal conditions that specify the four states. Detailed timing diagrams are shown in the electrical specifications section. The access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the two-wire bus. Unlike a serial EEPROM, it is not necessary to poll the device for a ready condition because writes occur at bus speed. By the time a new bus transaction can be shifted into the device, a write operation is complete. This is explained in more detail in Memory Operation on page 7. The FM24V02A does not meet the NXP I2C specification in the Fast-mode Plus (Fm+, 1 MHz) for IOL and in the High Speed Mode (Hs-mode, 3.4 MHz) for Vhys. Refer to the DC Electrical Characteristics table for more details. Figure 2. System Configuration Using Serial (I2C) F-RAM V DD RPmin = (VDD - VOLmax) / IOL RPmax = tr / (0.8473 * Cb) SDA Microcontroller SCL V DD V DD A0 A1 A2 SCL A0 SCL A0 SCL SDA A1 SDA A1 SDA WP A2 WP FM24V02A #0 Document Number: 001-90839 Rev. *I A2 WP FM24V02A FM24V02A #1 #7 Page 4 of 19 FM24V02A STOP Condition (P) START Condition (S) A STOP condition is indicated when the bus master drives SDA from LOW to HIGH while the SCL signal is HIGH. All operations using the FM24V02A should end with a STOP condition. If an operation is in progress when a STOP is asserted, the operation will be aborted. The master must have control of SDA (not a memory read) in order to assert a STOP condition. A START condition is indicated when the bus master drives SDA from HIGH to LOW while the SCL signal is HIGH. All commands should be preceded by a START condition. An operation in progress can be aborted by asserting a START condition at any time. Aborting an operation using the START condition will ready the FM24V02A for a new operation. If during operation the power supply drops below the specified VDD minimum, the system should issue a START condition prior to performing another operation. Figure 3. START and STOP Conditions full pagewidth SDA SDA SCL SCL S P STOP Condition START Condition Figure 4. Data Transfer on the I2C Bus handbook, full pagewidth P SDA Acknowledgement signal from slave MSB SCL S 1 2 7 8 9 ACK START condition Byte complete Data/Address Transfer All data transfers (including addresses) take place while the SCL signal is HIGH. Except under the three conditions described above, the SDA signal should not change while SCL is HIGH. Acknowledge / No-Acknowledge The acknowledge takes place after the 8th data bit has been transferred in any transaction. During this state the transmitter should release the SDA bus to allow the receiver to drive it. The receiver drives the SDA signal LOW to acknowledge receipt of the byte. If the receiver does not drive SDA LOW, the condition is a no-acknowledge and the operation is aborted. 1 Acknowledgement signal from receiver 2 3 4-8 9 ACK S S or P STOP or START condition The second and most common reason is that the receiver does not acknowledge to deliberately end an operation. For example, during a read operation, the FM24V02A will continue to place data on the bus as long as the receiver sends acknowledges (and clocks). When a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. If the receiver acknowledges the last byte, this causes the FM24V02A to attempt to drive the bus on the next clock while the master is sending a new command such as STOP. The receiver will fail to acknowledge for two distinct reasons, the first being that a byte transfer fails. In this case, the no-acknowledge ceases the current operation so that the part can be addressed again. This allows the last byte to be recovered in the event of a communication error. Document Number: 001-90839 Rev. *I Page 5 of 19 FM24V02A Figure 5. Acknowledge on the I2C Bus handbook, full pagewidth DATA OUTPUT BY MASTER No Acknowledge DATA OUTPUT BY SLAVE Acknowledge SCL FROM MASTER 1 2 8 9 S Clock pulse for acknowledgement START Condition High Speed Mode (Hs-mode) The FM24V02A supports a 3.4-MHz high-speed mode. A master code (00001XXXb) must be issued to place the device into the high-speed mode. Communication between master and slave will then be enabled for speeds up to 3.4-MHz. A STOP condition will exit Hs-mode. Single- and multiple-byte reads and writes are supported. Figure 6. Data Transfer Format in Hs-mode handbook, full pagewidth Hs-mode F/S-mode S 1 S MASTER CODE SLAVE ADD. R/W 0 F/S-mode DATA A /1 P n (bytes+ ack.) Acknowledge or No Acknowledge No Acknowledge Hs-mode continues S SLAVE ADD. Slave Device Address Addressing Overview The first byte that the FM24V02A expects after a START condition is the slave address. As shown in Figure 7, the slave address contains the device type or slave ID, the device select address bits, and a bit that specifies if the transaction is a read or a write. After the FM24V02A (as receiver) acknowledges the slave address, the master can place the memory address on the bus for a write operation. The address requires two bytes. The complete 15-bit address is latched internally. Each access causes the latched address value to be incremented automatically. The current address is the value that is held in the latch; either a newly written value or the address following the last access. The current address will be held for as long as power remains or until a new value is written. Reads always use the current address. A random read address can be loaded by beginning a write operation as explained below. Bits 7-4 are the device type (slave ID) and should be set to 1010b for the FM24V02A. These bits allow other function types to reside on the two-wire bus within an identical address range. Bits 3-1 are the device select address bits. They must match the corresponding value on the external address pins to select the device. Up to eight FM24V02A devices can reside on the same two-wire bus by assigning a different address to each. Bit 0 is the read/write bit (R/W). R/W = ‘1’ indicates a read operation and R/W = ‘0’ indicates a write operation. Figure 7. Memory Slave Device Address MSB handbook, halfpage 1 LSB 0 1 0 A2 Slave ID Document Number: 001-90839 Rev. *I A1 After transmission of each data byte, just prior to the acknowledge, the FM24V02A increments the internal address latch. This allows the next sequential byte to be accessed with no additional addressing. After the last address (7FFFh) is reached, the address latch will roll over to 0000h. There is no limit to the number of bytes that can be accessed with a single read or write operation. A0 R/W Device Select Page 6 of 19 FM24V02A Data Transfer Unlike other nonvolatile memory technologies, there is no effective write delay with F-RAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory cycle occurs in less time than a single bus clock. Therefore, any operation including read or write can occur immediately following a write. Acknowledge polling, a technique used with EEPROMs to determine if a write is complete is unnecessary and will always return a ready condition. After the address bytes have been transmitted, data transfer between the bus master and the FM24V02A can begin. For a read operation the FM24V02A will place 8 data bits on the bus then wait for an acknowledge from the master. If the acknowledge occurs, the FM24V02A will transfer the next sequential byte. If the acknowledge is not sent, the FM24V02A will end the read operation. For a write operation, the FM24V02A will accept 8 data bits from the master then sends an acknowledge. All data transfer occurs MSB (most significant bit) first. Internally, an actual memory write occurs after the 8th data bit is transferred. It will be complete before the acknowledge is sent. Therefore, if the user desires to abort a write without altering the memory contents, this should be done using START or STOP condition prior to the 8th data bit. The FM24V02A uses no page buffering. Memory Operation The FM24V02A is designed to operate in a manner very similar to other two-wire interface memory products. The major differences result from the higher performance write capability of F-RAM technology. These improvements result in some differences between the FM24V02A and a similar configuration EEPROM during writes. The complete operation for both writes and reads is explained below. The memory array can be write-protected using the WP pin. Setting the WP pin to a HIGH condition (VDD) will write-protect all addresses. The FM24V02A will not acknowledge data bytes that are written to protected addresses. In addition, the address counter will not increment if writes are attempted to these addresses. Setting WP to a LOW state (VSS) will disable the write protect. WP is pulled down internally. Write Operation Figure 8 and Figure 9 illustrate a single-byte and multiple-byte write cycles in Fast-mode Plus (Fm+). Figure 10 illustrates a single-byte write cycles in Hs mode. All writes begin with a slave address, then a memory address. The bus master indicates a write operation by setting the LSB of the slave address (R/W bit) to a '0'. After addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. Any number of sequential bytes may be written. If the end of the address range is reached internally, the address counter will wrap from 7FFFh to 0000h. Figure 8. Single-Byte Write By Master Start S Stop Address & Data Slave Address 0 A Address MSB By F-RAM A Address LSB A Data Byte A P Acknowledge Figure 9. Multi-Byte Write Start Stop Address & Data By Master S Slave Address 0 A By F-RAM Document Number: 001-90839 Rev. *I Address MSB A Address LSB A Data Byte A Data Byte A P Acknowledge Page 7 of 19 FM24V02A Figure 10. Hs-Mode Byte Write Start Start & Enter Hs-mode Hs-mode command By Master S 0 0 0 0 1 X X By F-RAM 1 X S Stop & Exit Hs-mode Address & Data Slave Address 0 A Address MSB No Acknowledge A Address LSB A Data Byte A P Acknowledge Read Operation There are two basic types of read operations. They are current address read and selective address read. In a current address read, the FM24V02A uses the internal address latch to supply the address. In a selective read, the user performs a procedure to set the address to a specific value. Current Address & Sequential Read As mentioned above the FM24V02A uses an internal latch to supply the address for a read operation. A current address read uses the existing value in the address latch as a starting place for the read operation. The system reads from the address immediately following that of the last operation. To perform a current address read, the bus master supplies a slave address with the LSB set to a '1'. This indicates that a read operation is requested. After receiving the complete slave address, the FM24V02A will begin shifting out data from the current address on the next clock. The current address is the value held in the internal address latch. Note Each time the bus master acknowledges a byte, this indicates that the FM24V02A should read out the next sequential byte. There are four ways to properly terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM24V02A attempts to read out additional data onto the bus. The four valid methods are: 1. The bus master issues a no-acknowledge in the 9th clock cycle and a STOP in the 10th clock cycle. This is illustrated in the diagrams below. This is preferred. 2. The bus master issues a no-acknowledge in the 9th clock cycle and a START in the 10th. 3. The bus master issues a STOP in the 9th clock cycle. 4. The bus master issues a START in the 9th clock cycle. If the internal address reaches 7FFFh, it will wrap around to 0000h on the next read cycle. Figure 11 and Figure 12 show the proper operation for current address reads. Beginning with the current address, the bus master can read any number of bytes. Thus, a sequential read is simply a current address read with multiple byte transfers. After each byte the internal address counter will be incremented. Figure 11. Current Address Read Start By Master No Acknowledge Address Stop S Slave Address By F-RAM 1 A Acknowledge Data Byte 1 P Data Figure 12. Sequential Read By Master Start Address No Acknowledge Acknowledge Stop S Slave Address By F-RAM Document Number: 001-90839 Rev. *I 1 A Acknowledge Data Byte A Data Byte 1 P Data Page 8 of 19 FM24V02A Figure 13. Hs-Mode Current Address Read Start S 0 0 0 0 1 X No Acknowledge Start & Enter Hs-mode Address Hs-mode command By Master X 1 X By F-RAM S Slave Address 1 A No Acknowledge Selective (Random) Read There is a simple technique that allows a user to select a random address location as the starting point for a read operation. This involves using the first three bytes of a write operation to set the internal address followed by subsequent read operations. To perform a selective read, the bus master sends out the slave address with the LSB (R/W) set to 0. Stop & Exit Hs-mode Data Byte Acknowledge 1 P Data This specifies a write operation. According to the write protocol, the bus master then sends the address bytes that are loaded into the internal address latch. After the FM24V02A acknowledges the address, the bus master issues a START condition. This simultaneously aborts the write operation and allows the read command to be issued with the slave address LSB set to a '1'. The operation is now a current address read. Figure 14. Selective (Random) Read Start Address By Master Start No Acknowledge Address Stop S Slave Address 0 A Address MSB A Address LSB By F-RAM A S Slave Address 1 A Data Byte Data Acknowledge Sleep Mode A low power mode called Sleep Mode is implemented on the FM24V02A device. The device will enter this low power state when the Sleep command 86h is clocked-in. Sleep Mode entry can be entered as follows: 1. The master sends a START command. 2. The master sends Reserved Slave ID 0xF8. 3. The FM24V02A sends an ACK. 4. The master sends the I2C-bus slave address of the slave device it needs to identify. The last bit is a 'Don't care' value (R/W bit). Only one device must acknowledge this byte (the one that has the I2C-bus slave address). 5. The FM24V02A sends an ACK. 1 P 6. The master sends a Re-START command. 7. The master sends Reserved Slave ID 0x86. 8. The FM24V02A sends an ACK. 9. The master sends STOP to ensure the device enters sleep mode. Once in sleep mode, the device draws IZZ current, but the device continues to monitor the I2C pins. Once the master sends a Slave Address that the FM24V02A identifies, it will "wakeup" and be ready for normal operation within tREC (400-s max.). As an alternative method of determining when the device is ready, the master can send read or write commands and look for an ACK. While the device is waking up, it will NACK the master until it is ready. Figure 15. Sleep Mode Entry Start Address By Master S By F-RAM Document Number: 001-90839 Rev. *I Rsvd Slave ID (F8) A Start Slave Address X A S Address Rsvd Slave ID (86) Stop A P Acknowledge Page 9 of 19 FM24V02A Device ID The FM24V02A device incorporates a means of identifying the device by providing three bytes of data, which are manufacturer, product ID, and die revision. The Device ID is read-only. It can be accessed as follows: 1. The master sends a START command. 6. The master sends a Re-START command. 2. The master sends Reserved Slave ID 0xF8. 7. The master sends Reserved Slave ID 0xF9. 3. The FM24V02A sends an ACK. 8. The FM24V02A sends an ACK. 4. The master sends the I2C-bus slave address of the slave 9. The Device ID Read can be done, starting with the 12 device it needs to identify. The last bit is a 'Don't care' value manufacturer bits, followed by the 9 part identification bits, (R/W bit). Only one device must acknowledge this byte (the and then the 3 die revision bits. one that has the I2C-bus slave address). 10.The master ends the Device ID read sequence by NACKing 5. The FM24V02A sends an ACK. the last byte, thus resetting the slave device state machine and allowing the master to send the STOP command. Note The reading of the Device ID can be stopped anytime by sending a NACK command. Table 1. Device ID Device ID Description 23–12 (12 bits) Device ID (3 bytes) 11–8 (4 bits) 2–0 (3 bits) Product ID Manufacturer ID 004201h 7–3 (5 bits) 000000000100 Density Variation Die Rev 0010 00000 001 Note Product ID bits 0 and 4 are reserved. Figure 16. Read Device ID Start Address By Master Start No Acknowledge Acknowledge Address Stop S Rsvd Slave ID (F8) A Slave Address By F-RAM Document Number: 001-90839 Rev. *I A S Acknowledge Rsvd Slave ID (F9) A Data Byte A Data Byte A Data Byte 1 P Data Page 10 of 19 FM24V02A Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –55 C to +125 C Maximum accumulated storage time At 125 °C ambient temperature ................................. 1000 h At 85 °C ambient temperature ................................ 10 Years Ambient temperature with power applied ................................... –55 °C to +125 °C Supply voltage on VDD relative to VSS .........–1.0 V to +4.5 V Input voltage* ......... –1.0 V to + 4.5 V and VIN < VDD + 1.0 V Package power dissipation capability (TA = 25 °C) ................................................. 1.0 W Surface mount lead soldering temperature (3 seconds) ......................................... +260 C Electrostatic discharge voltage Human Body Model (JEDEC Std JESD22-A114-B) .............. 2 kV Charged Device Model (JEDEC Std JESD22-C101-A) ........ 500 V Latch-up current .................................................... > 140 mA * Exception: The “VIN < VDD + 1.0 V” restriction does not apply to the SCL and SDA inputs. Operating Range DC voltage applied to outputs in HI-Z state ........................................ –0.5 V to VDD + 0.5 V Range Ambient Temperature (TA) VDD Industrial –40 C to +85 C 2.0 V to 3.6 V Transient voltage (< 20 ns) on any pin to ground potential ................. –2.0 V to VDD + 2.0 V DC Electrical Characteristics Over the Operating Range Parameter Description VDD Power supply IDD Average VDD current Test Conditions SCL toggling between VDD – 0.2 V and VSS, other inputs VSS or VDD – 0.2 V. fSCL = 100 kHz Min Typ [2] 2.0 3.3 3.6 V – – 175 A Max Unit fSCL = 1 MHz – – 400 A fSCL = 3.4 MHz – – 1000 A ISB VDD standby current SCL = SDA = VDD. All other inputs VSS or VDD. Stop command issued. – 90 150 A IZZ Sleep mode current SCL = SDA = VDD. All other inputs VSS or VDD. Stop command issued. – 5 8 A ILI Input leakage current (Except WP and A2-A0) VSS < VIN < VDD –1 – +1 A –1 – +100 A Input leakage current (for WP and A2-A0) ILO Output leakage current –1 – +1 A VIH Input HIGH voltage (SDL, SDA) 0.7 × VDD – VDD(max) + 0.3 V Input HIGH voltage (WP, A2-A0) 0.7 × VDD – VDD + 0.3 V – 0.3 – 0.3 × VDD V IOL = 3 mA – – 0.4 V IOL = 6 mA – – 0.6 V For VIN = VIL(Max) 50 – – k VIL Input LOW voltage VOL[3] Output LOW voltage Rin [4] Input resistance (WP, A2-A0) VSS < VOUT < VDD For VIN = VIH(Min) Vhys[5] Hysteresis of Schmitt Trigger inputs 1 – – M fSCL = 100 kHz, 400 kHz, 1 MHz 0.05 × VDD – – V fSCL = 3.4 MHz 0.06 × VDD – – V Notes 2. Typical values are at 25 °C, VDD = VDD(typ). Not 100% tested. 3. The FM24V02A does not meet the NXP I2C specification in the Fast-mode Plus (Fm+, 1 MHz) for IOL of 20 mA at a VOL of 0.4 V. 4. The input pull-down circuit is strong (50 k) when the input voltage is below VIL and weak (1 M) when the input voltage is above VIH. 5. The FM24V02A does not meet the NXP I2C specification in the High Speed Mode (Hs-mode, 3.4 MHz) for Vhys of 0.1 × VDD. Document Number: 001-90839 Rev. *I Page 11 of 19 FM24V02A Data Retention and Endurance Parameter TDR NVC Description Test condition TA = 85 C Data retention Endurance Min Max Unit 10 – Years TA = 75 C 38 – TA = 65 C 151 – Over operating temperature 1014 – Cycles Capacitance Parameter [6] Description pin Test Conditions capacitance TA = 25 C, f = 1 MHz, VDD = VDD(typ) CIO Input/Output (SDA) CI Input pin capacitance Max Unit 8 pF 6 pF Thermal Resistance Description Parameter [6] Thermal resistance JA (junction to ambient) Thermal resistance JC (junction to case) Test Conditions 8-pin SOIC Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 146 C/W 48 C/W AC Test Loads and Waveforms Figure 17. AC Test Loads and Waveforms 3.0 V 867  OUTPUT 100 pF AC Test Conditions Input pulse levels .................................10% and 90% of VDD Input rise and fall times .................................................10 ns Input and output timing reference levels ................0.5 × VDD Output load capacitance ............................................ 100 pF Note 6. These parameters are guaranteed by design and are not tested. Document Number: 001-90839 Rev. *I Page 12 of 19 FM24V02A AC Switching Characteristics Over the Operating Range Alt. Parameter[7] Parameter Fast-Mode Plus (Fm+) [9] Description Hs-Mode[9] Unit Min Max Min Max – 1.0 – 3.4 MHz fSCL[8] SCL clock frequency tSU; STA Start condition setup for repeated Start 260 – 160 – ns tHD;STA Start condition hold time 260 – 160 – ns tLOW Clock LOW period 500 – 160 – ns tHIGH Clock HIGH period 260 – 60 – ns tSU;DAT tSU;DATA Data in setup 50 – 10 – ns tHD;DAT tHD;DATA Data in hold 0 – 0 70 ns Data output hold (from SCL at VIL) 0 – 0 – ns tR[10] tr Input rise time – 120 10 80 ns tF[10] tf Input fall time 20 * (VDD / 5.5 V) 120 10 80 ns 260 – 160 – ns tDH STOP condition setup tSU;STO SCL LOW to SDA Data Out Valid – 450 – 130 ns tVD;ACK tVD;DATA ACK output valid time – 450 – 130 ns tOF[10] Output fall time from VIH min to VILmax 20 * (VDD / 5.5 V) 120 – 80 ns tBUF Bus free before new transmission 500 – 300 – ns tSP Noise suppression time constant on SCL, SDA 0 50 – 5 ns tAA Figure 18. Read Bus Timing Diagram tR ` tF tHIGH tSP tLOW tSP SCL tSU:SDA 1/fSCL tBUF tHD:DAT tSU:DAT SDA tDH tAA Stop Start Start Acknowledge Figure 19. Write Bus Timing Diagram tHD:DAT SCL tHD:STA tSU:STO tSU:DAT tAA SDA Start Stop Start Acknowledge Notes 7. Test conditions assume signal transition time of 10 ns or less, timing reference levels of VDD/2, input pulse levels of 0 to VDD(typ), and output loading of the specified IOL and 100 pF load capacitance shown in Figure 17. 8. The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to fSCL(max). 9. Bus Load (Cb) considerations; Cb < 550 pF for I2C clock frequency (SCL) 1 MHz; Cb < 100 pF for SCL at 3.4 MHz. 10. These parameters are guaranteed by design and are not tested. Document Number: 001-90839 Rev. *I Page 13 of 19 FM24V02A Power Cycle Timing Over the Operating Range Parameter Description Min Max Unit 250 – μs tPU Power-up VDD(min) to first access (START condition) tPD Last access (STOP condition) to power-down (VDD(min)) 0 – µs tVR [11, 12] VDD power-up ramp rate 50 – µs/V tVF [11, 12] VDD power-down ramp rate 100 – µs/V tREC Recovery time from sleep mode – 400 µs VDD ~ ~ Figure 20. Power Cycle Timing VDD(min) tVR SDA I2 C START tVF tPD ~ ~ tPU VDD(min) I2 C STOP Notes 11. Slope measured at any point on the VDD waveform. 12. These parameters are guaranteed by design and are not tested. Document Number: 001-90839 Rev. *I Page 14 of 19 FM24V02A Ordering Information Package Diagram Ordering Code Package Type FM24V02A-G 51-85066 8-pin SOIC FM24V02A-GTR 51-85066 8-pin SOIC Operating Range Industrial All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions FM 24 V 02 A - G X Option: X = blank or TR blank = Standard; TR = Tape and Reel Package Type: G = 8-pin SOIC Device revision: A Density: 02 = 256-Kbit Voltage: V = 2.0 V to 3.6 V I2C F-RAM Cypress Document Number: 001-90839 Rev. *I Page 15 of 19 FM24V02A Package Diagram Figure 21. 8-pin SOIC (150 Mils) Package Outline, 51-85066 51-85066 *H Document Number: 001-90839 Rev. *I Page 16 of 19 FM24V02A Acronyms Acronym Document Conventions Description Units of Measure ACK Acknowledge CMOS Complementary Metal Oxide Semiconductor °C degree Celsius EIA Electronic Industries Alliance I2C Hz hertz Inter-Integrated Circuit Kb 1024 bit I/O Input/Output kHz kilohertz JEDEC Joint Electron Devices Engineering Council k kilohm LSB Least Significant Bit MHz megahertz MSB Most Significant Bit M megaohm NACK No Acknowledge A microampere RoHS Restriction of Hazardous Substances s microsecond R/W Read/Write mA milliampere SCL Serial Clock Line ms millisecond SDA Serial Data Access ns nanosecond SOIC Small Outline Integrated Circuit  ohm WP Write Protect % percent pF picofarad V volt W watt Document Number: 001-90839 Rev. *I Symbol Unit of Measure Page 17 of 19 FM24V02A Document History Page Document Title: FM24V02A, 256-Kbit (32K × 8) Serial (I2C) F-RAM Document Number: 001-90839 Rev. ECN No. Orig. of Change Submission Date ** 4266205 GVCH 01/29/2014 New data sheet. *A 4390913 GVCH 06/20/2014 Changed status from Advance to Preliminary. Maximum Ratings: Electrostatic Discharge Voltage Removed machine model. DC Electrical Characteristics: Added ISB and IZZ typical value. Changed VIH value from VDD+ 0.5 V to VDD(max) + 0.3 V for SDA, SCL and VDD(max) + 0.3 V for WP, A2-A0. Removed VOL2 parameter spec and renamed VOL1 as VOL parameter spec. Added VOL = 0.6 V at 6 mA. Changed VIL min value from – 0.5 V to – 0.3 V. Added Vhys parameter spec. Updated Capacitance. AC Switching Characteristics: Added tOF, tBUF, tAA, tVD;ACK value for 3.4 MHz. Removed footnote 7. *B 4512788 GVCH 09/24/2014 Added footnote 3 for the difference in IOL with respect to I2C specification. *C 4571858 GVCH 11/18/2014 Changed Vhys spec value from 0.1 × VDD to 0.05 × VDD for 3.4 MHz frequency. Added footnote 5 for the difference in Vhys with respect to I2C specification. *D 4596783 GVCH 12/17/2014 Added footnote 1 for the difference in IOL and Vhys with respect to NXP I2C specification. Two-wire Interface: Added description for the difference in IOL and Vhys with respect to NXP I2C specification. Changed Vhys spec value from 0.05 × VDD to 0.06 × VDD for 3.4 MHz frequency Updated footnote 3. Updated footnote 5 for the difference in Vhys with respect to NXP I2C specification. Updated to new template. *E 4651363 ZSK 02/10/2015 Changed status from Preliminary to Final. Updated Functional Description: Added “For a complete list of related resources, click here.” at the end. Updated Package Diagram: spec 51-85066 – Changed revision from *F to *G. *F 4874478 ZSK / PSR 08/06/2015 Updated Maximum Ratings: Removed “Maximum junction temperature”. Added “Maximum accumulated storage time”. Added “Ambient temperature with power applied”. *G 5085665 GVCH 01/14/2016 Updated Ordering Information: Updated part numbers. Updated Package Diagram: spec 51-85066 – Changed revision from *G to *H. *H 5452467 ZSK 09/28/2016 Updated Power Cycle Timing: Changed minimum value of tPU parameter from 1 ms to 250 μs. Updated to new template. *I 5734131 AESATMP7 05/11/2017 Updated Cypress Logo and Copyright. Document Number: 001-90839 Rev. *I Description of Change Page 18 of 19 FM24V02A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC®Solutions Products ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Internet of Things Lighting & Power Control cypress.com/iot cypress.com/powerpsoc Memory PSoC Touch Sensing USB Controllers Wireless/RF PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Cypress Developer Community Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/memory cypress.com/psoc cypress.com/touch cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. 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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-90839 Rev. *I Revised May 11, 2017 Page 19 of 19