FM25V20A (PDIP)
2-Mbit (256 K × 8) Serial (SPI) F-RAM
FM25V20A (PDIP), 2-Mbit (256 K X 8) Serial (SPI) F-RAM
Features
Functional Overview
■
2-Mbit ferroelectric random access memory (F-RAM) logically
organized as 256 K × 8
14
❐ High-endurance 100 trillion (10 ) read/writes
❐ 151-year data retention (See the Data Retention and Endurance table)
❐ NoDelay™ writes
❐ Advanced high-reliability ferroelectric process
The FM25V20A is a 2-Mbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 151 years
while eliminating the complexities, overhead, and system-level
reliability problems caused by serial flash, EEPROM, and other
nonvolatile memories.
■
Very fast SPI
❐ Up to 25-MHz frequency
❐ Direct hardware replacement for serial flash and EEPROM
❐ Supports SPI mode 0 (0, 0) and mode 3 (1, 1)
■
Sophisticated write protection scheme
❐ Hardware protection using the Write Protect (WP) pin
❐ Software protection using Write Disable instruction
❐ Software block protection for 1/4, 1/2, or entire array
Unlike serial flash and EEPROM, the FM25V20A performs write
operations at bus speed. No write delays are incurred. Data is
written to the memory array immediately after each byte is
successfully transferred to the device. The next bus cycle can
commence without the need for data polling. In addition, the
product offers substantial write endurance compared with other
nonvolatile memories. The FM25V20A is capable of supporting
1014 read/write cycles, or 100 million times more write cycles
than EEPROM.
■
Device ID
❐ Manufacturer ID and Product ID
■
Low power consumption
❐ 300 µA active current at 1 MHz
❐ 120 µA (typ) standby current
❐ 3 µA sleep mode current
■
Low-voltage operation: VDD = 2.0 V to 3.6 V
■
Industrial temperature: –40 C to +85 C
■
8-pin plastic dual in-line (PDIP) package
■
Restriction of hazardous substances (RoHS) compliant
These capabilities make the FM25V20A ideal for nonvolatile
memory applications, requiring frequent or rapid writes.
Examples range from data collection, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of serial flash or EEPROM can cause data loss.
The FM25V20A provides substantial benefits to users of serial
EEPROM or flash as a hardware drop-in replacement. The
FM25V20A uses the high-speed SPI bus, which enhances the
high-speed write capability of F-RAM technology. The device
incorporates a read-only Device ID that allows the host to
determine the manufacturer, product density, and product
revision. The device specifications are guaranteed over an
industrial temperature range of –40 C to +85 C.
Logic Block Diagram
WP
Instruction Decoder
Clock Generator
Control Logic
Write Protect
CS
SCK
256 K x 8
FRAM Array
Instruction Register
Address Register
Counter
18
SI
8
Data I/O Register
SO
3
Nonvolatile Status
Register
Cypress Semiconductor Corporation
Document Number: 001-90311 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 15, 2019
FM25V20A
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Overview ............................................................................ 4
Memory Architecture ................................................... 4
Serial Peripheral Interface – SPI Bus .......................... 4
SPI Overview ............................................................... 4
SPI Modes ................................................................... 5
Power Up to First Access ............................................ 5
Command Structure .................................................... 6
WREN - Set Write Enable Latch ................................. 6
WRDI - Reset Write Enable Latch ............................... 6
Status Register and Write Protection ............................. 7
RDSR - Read Status Register ..................................... 7
WRSR - Write Status Register .................................... 7
Memory Operation ............................................................ 9
Write Operation ........................................................... 9
Read Operation ........................................................... 9
Fast Read Operation ................................................... 9
Sleep Mode ............................................................... 10
Device ID ................................................................... 10
Endurance ................................................................. 11
Document Number: 001-90311 Rev. *C
Maximum Ratings ........................................................... 12
Operating Range ............................................................. 12
DC Electrical Characteristics ........................................ 12
Data Retention and Endurance ..................................... 13
Capacitance .................................................................... 13
Thermal Resistance ........................................................ 13
AC Test Conditions ........................................................ 13
AC Switching Characteristics ....................................... 14
Power Cycle Timing ....................................................... 15
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagrams .......................................................... 17
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC® Solutions ...................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Page 2 of 20
FM25V20A
Pinout
Figure 1. 8-pin PDIP Pinout
CS
1
8
VDD
SO
2
7
DNU
HOLD
WP
3
6
SCK
VSS
4
5
SI
Pin Definitions
Pin Name
I/O Type
Description
CS
Input
Chip Select. This active LOW input activates the device. When HIGH, the device enters low-power
standby mode, ignores other inputs, and the output is tristated. When LOW, the device internally
activates the SCK signal. A falling edge on CS must occur before every opcode.
SCK
Input
Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge
and outputs occur on the falling edge. Because the device is synchronous, the clock frequency may
be any value between 0 and 25 MHz and may be interrupted at any time.
SI [1]
Input
Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of SCK
and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications.
SO [1]
Output
Serial Output. This is the data output pin. It is driven during a read and remains tristated at all other
times. Data transitions are driven on the falling edge of the serial clock.
WP
Input
Write Protect. This Active LOW pin prevents write operation to the Status Register when WPEN is
set to ‘1’. This is critical because other write protection features are controlled through the Status
Register. A complete explanation of write protection is provided in Status Register and Write Protection
on page 7. This pin must be tied to VDD if not used.
DNU
Do Not Use Do Not Use. Either leave this pin floating (not connected on the board) or tie to VDD.
VSS
Power Supply Ground for the device. Must be connected to the ground of the system.
VDD
Power Supply Power supply input to the device.
Note
1. SI may be connected to SO for a single pin data interface.
Document Number: 001-90311 Rev. *C
Page 3 of 20
FM25V20A
Overview
SPI Master
The FM25V20A is a serial F-RAM memory. The memory array is
logically organized as 262,144 × 8 bits and is accessed using an
industry-standard SPI bus. The functional operation of the
F-RAM is similar to serial flash and serial EEPROMs. The major
difference between the FM25V20A and a serial flash or
EEPROM with the same pinout is the F-RAM's superior write
performance, high endurance, and low power consumption.
The SPI master device controls the operations on a SPI bus. An
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
of the operations must be initiated by the master activating a
slave device by pulling the CS pin of the slave LOW. The master
also generates the SCK and all the data transmission on SI and
SO lines are synchronized with this clock.
Memory Architecture
SPI Slave
When accessing the FM25V20A, the user addresses 256K
locations of eight data bits each. These eight data bits are shifted
in or out serially. The addresses are accessed using the SPI
protocol, which includes a chip select (to permit multiple devices
on the bus), an opcode, and a three-byte address. The upper 6
bits of the address range are 'don't care' values. The complete
address of 18 bits specifies each byte address uniquely.
Most functions of the FM25V20A are either controlled by the SPI
interface or handled by on-board circuitry. The access time for
the memory operation is essentially zero, beyond the time
needed for the serial protocol. That is, the memory is read or
written at the speed of the SPI bus. Unlike a serial flash or
EEPROM, it is not necessary to poll the device for a ready
condition because writes occur at bus speed. By the time a new
bus transaction can be shifted into the device, a write operation
is complete. This is explained in more detail in the interface
section.
Serial Peripheral Interface – SPI Bus
The FM25V20A is a SPI slave device and operates at speeds up
to 25 MHz. This high-speed serial bus provides high-performance serial communication to a SPI master. Many common
microcontrollers have hardware SPI ports allowing a direct
interface. It is quite simple to emulate the port using ordinary port
pins for microcontrollers that do not. The FM25V20A operates in
SPI Mode 0 and 3.
SPI Overview
The SPI is a four-pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO), and Serial Clock (SCK) pins.
The SPI is a synchronous serial interface, which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on the SPI bus is activated using the CS
pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. This device supports SPI modes 0 and 3. In
both of these modes, data is clocked into the F-RAM on the rising
edge of SCK starting from the first rising edge after CS goes
active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated, the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms in the SPI protocol are as follows:
Document Number: 001-90311 Rev. *C
The SPI slave device is activated by the master through the Chip
Select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. An SPI slave never initiates a communication on the SPI
bus and acts only on the instruction from the master.
The FM25V20A operates as an SPI slave and may share the SPI
bus with other SPI slave devices.
Chip Select (CS)
To select any slave device, the master needs to pull down the
corresponding CS pin. Any instruction can be issued to a slave
device only while the CS pin is LOW. When the device is not
selected, data through the SI pin is ignored and the serial output
pin (SO) remains in a high-impedance state.
Note A new instruction must begin with the falling edge of CS.
Therefore, only one opcode can be issued for each active Chip
Select cycle.
Serial Clock (SCK)
The Serial Clock is generated by the SPI master and the communication is synchronized with this clock after CS goes LOW.
The FM25V20A enables SPI modes 0 and 3 for data communication. In both of these modes, the inputs are latched by the
slave device on the rising edge of SCK and outputs are issued
on the falling edge. Therefore, the first rising edge of SCK
signifies the arrival of the first bit (MSB) of a SPI instruction on
the SI pin. Further, all data inputs and outputs are synchronized
with SCK.
Data Transmission (SI/SO)
The SPI data bus consists of two lines, SI and SO, for serial data
communication. SI is also referred to as Master Out Slave In
(MOSI) and SO is referred to as Master In Slave Out (MISO). The
master issues instructions to the slave through the SI pin, while
the slave responds through the SO pin. Multiple slave devices
may share the SI and SO lines as described earlier.
The FM25V20A has two separate pins for SI and SO, which can
be connected with the master as shown in Figure 2.
For a microcontroller that has no dedicated SPI bus, a
general-purpose port may be used. To reduce hardware
resources on the controller, it is possible to connect the two data
pins (SI, SO) together and tie off (HIGH) the WP pin. Figure 3
shows such a configuration, which uses only three pins.
Page 4 of 20
FM25V20A
Most Significant Bit (MSB)
SPI Modes
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.
FM25V20A may be driven by a microcontroller with its SPI
peripheral running in either of the following two modes:
The 2-Mbit serial F-RAM requires a 3-byte address for any read
or write operation. Because the address is only 18 bits, the first
six bits, which are fed in are ignored by the device. Although
these six bits are ‘don’t care’, Cypress recommends that these
bits be set to 0s to enable seamless transition to higher memory
densities.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
FM25V20A uses the standard opcodes for memory accesses.
■
SPI Mode 0 (CPOL = 0, CPHA = 0)
■
SPI Mode 3 (CPOL = 1, CPHA = 1)
For both these modes, the input data is latched in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a HIGH state (in mode 3), the first
rising edge after the clock toggles is considered. The output data
is available on the falling edge of SCK.
The two SPI modes are shown in Figure 4 and Figure 5. The
status of the clock when the bus master is not transferring data is:
■
SCK remains at 0 for Mode 0
Invalid Opcode
■
SCK remains at 1 for Mode 3
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin until the
next falling edge of CS, and the SO pin remains tristated.
The device detects the SPI mode from the status of the SCK pin
when the device is selected by bringing the CS pin LOW. If the
SCK pin is LOW when the device is selected, SPI Mode 0 is
assumed and if the SCK pin is HIGH, it works in SPI Mode 3.
Status Register
FM25V20A has an 8-bit Status Register. The bits in the Status
Register are used to configure the device. These bits are
described in Table 3 on page 7.
Figure 2. System Configuration with SPI Port
Figure 4. SPI Mode 0
CS
0
SI
SCK
SI
SO
SCK
FM25V20A
SI
2
3
5
4
6
7
SCK
SCK
MOSI
MISO
SPI Hostcontroller
or
SPI Master
1
7
6
5
4
3
2
1
0
MSB
SO
LSB
FM25V20A
Figure 5. SPI Mode 3
CS
WP
CS
WP
CS
CS1
WP1
0
CS2
WP2
1
2
3
4
5
6
7
SCK
Figure 3. System Configuration without SPI Port
SI
7
6
5
MSB
4
3
2
1
0
LSB
P1.0
P1.1
Power Up to First Access
SPI Hostcontroller
or
SPI Master
SCK
SI
SO
FM25V20A
CS
The FM25V20 is not accessible for a tPU time after power-up.
Users must comply with the timing parameter, tPU, which is the
minimum time from VDD (min) to the first CS LOW.
WP
P1.2
Document Number: 001-90311 Rev. *C
Page 5 of 20
FM25V20A
Command Structure
Figure 6. WREN Bus Configuration
There are nine commands, called opcodes, that can be issued
by the bus master to the FM25V20A. They are listed in Table 1.
These opcodes control the functions performed by the memory.
Description
0
1
2
3
4
5
6
7
SCK
Table 1. Opcode Commands
Name
CS
Opcode
SI
0
0
0
0
0
1
1
0
WREN
Set write enable latch
0000 0110b
WRDI
Reset write enable latch
0000 0100b
RDSR
Read Status Register
0000 0101b
WRSR
Write Status Register
0000 0001b
WRDI - Reset Write Enable Latch
READ
Read memory data
0000 0011b
FSTRD
Fast read memory data
0000 1011b
WRITE
Write memory data
0000 0010b
SLEEP
Enter sleep mode
1011 1001b
The WRDI command disables all write activity by clearing the
Write Enable Latch. The user can verify that writes are disabled
by reading the WEL bit in the Status Register and verifying that
WEL is equal to ‘0’. Figure 7 illustrates the WRDI command bus
configuration.
RDID
Read device ID
1001 1111b
Figure 7. WRDI Bus Configuration
WREN - Set Write Enable Latch
The FM25V20A will power up with writes disabled. The WREN
command must be issued before any write operation. Sending
the WREN opcode allows the user to issue subsequent opcodes
for write operations. These include writing the Status Register
(WRSR) and writing the memory (WRITE).
Sending the WREN opcode causes the internal Write Enable
Latch to be set. A flag bit in the Status Register, called WEL,
indicates the state of the latch. WEL = 1 indicates that writes are
permitted. Attempting to write the WEL bit in the Status Register
has no effect on the state of this bit – only the WREN opcode can
set this bit. The WEL bit will be automatically cleared on the rising
edge of CS following a WRDI, a WRSR, or a WRITE operation.
This prevents further writes to the Status Register or the F-RAM
array without another WREN command. Figure 6 illustrates the
WREN command bus configuration.
Document Number: 001-90311 Rev. *C
HI-Z
SO
CS
0
1
2
3
4
5
6
7
SCK
SI
SO
0
0
0
0
0
1
0
0
HI-Z
Page 6 of 20
FM25V20A
Status Register and Write Protection
The write protection features of the FM25V20A are multi-tiered and are enabled through the status register. The Status Register is
organized as follows. (The default value shipped from the factory for WEL, BP0, BP1, bits 4–5, WPEN is ‘0’, and for bit 6 is ‘1’).
Table 2. Status Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN (0)
X (1)
X (0)
X (0)
BP1 (0)
BP0 (0)
WEL (0)
X (0)
Table 3. Status Register Bit Definition
Bit
Definition
Description
Bit 0
Don’t care
Bit 1 (WEL)
Write Enable
This bit is non-writable and always returns ‘0’ upon read.
Bit 2 (BP0)
Block Protect bit ‘0’
Used for block protection. For details, see Table 4.
Bit 3 (BP1)
Block Protect bit ‘1’
Used for block protection. For details, see Table 4.
Bit 4-5
Don’t care
These bits are non-writable and always return ‘0’ upon read.
Bit 6
Don’t care
This bit is non-writable and always returns ‘1’ upon read.
WEL indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up.
WEL = 1 --> Write enabled
WEL = 0 --> Write disabled
Bit 7 (WPEN) Write Protect Enable bit Used to enable the function of Write Protect Pin (WP). For details, see Table 5.
Bits 0 and 4-5 are fixed at ‘0’ and bit 6 is fixed at ‘1’; none of these
bits can be modified. Note that bit 0 (“Ready or Write in progress”
bit in serial flash and EEPROM) is unnecessary, as the F-RAM
writes in real-time and is never busy, so it reads out as a ‘0’. An
exception to this is when the device is waking up from sleep
mode, which is described in Sleep Mode on page 10. The BP1
and BP0 control the software write-protection features and are
nonvolatile bits. The WEL flag indicates the state of the Write
Enable Latch. Attempting to directly write the WEL bit in the
Status Register has no effect on its state. This bit is internally set
and cleared via the WREN and WRDI commands, respectively.
BP1 and BP0 are memory block write protection bits. They
specify portions of memory that are write-protected as shown in
Table 4.
Table 4. Block Memory Write Protection
BP1
BP0
Protected Address Range
0
0
None
0
1
30000h to 3FFFFh (upper 1/4)
1
0
20000h to 3FFFFh (upper 1/2)
1
1
00000h to 3FFFFh (all)
The BP1 and BP0 bits and the Write Enable Latch are the only
mechanisms that protect the memory from writes. The remaining
write protection features protect inadvertent changes to the block
protect bits.
The write protect enable bit (WPEN) in the Status Register
controls the effect of the hardware write protect (WP) pin. When
the WPEN bit is set to '0', the status of the WP pin is ignored.
When the WPEN bit is set to '1', a LOW on the WP pin inhibits a
write to the Status Register. Thus the Status Register is
write-protected only when WPEN = 1 and WP = 0.
Document Number: 001-90311 Rev. *C
Table 5 summarizes the write protection conditions.
Table 5. Write Protection
WEL WPEN WP
Protected Unprotected
Blocks
Blocks
Status
Register
Protected
Protected
Protected
0
X
X
1
0
X
Protected
Unprotected
Unprotected
1
1
0
Protected
Unprotected
Protected
1
1
1
Protected
Unprotected
Unprotected
RDSR - Read Status Register
The RDSR command allows the bus master to verify the
contents of the Status Register. Reading the status register
provides information about the current state of the
write-protection features. Following the RDSR opcode, the
FM25V20A will return one byte with the contents of the Status
Register.
WRSR - Write Status Register
The WRSR command allows the SPI bus master to write into the
Status Register and change the write protect configuration by
setting the WPEN, BP0 and BP1 bits as required. Before issuing
a WRSR command, the WP pin must be HIGH or inactive. Note
that on the FM25V20A, WP only prevents writing to the Status
Register, not the memory array. Before sending the WRSR
command, the user must send a WREN command to enable
writes. Executing a WRSR command is a write operation and
therefore, clears the Write Enable Latch.
Page 7 of 20
FM25V20A
Figure 8. RDSR Bus Configuration
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Opcode
0
SI
0
0
0
0
1
0
1
Data
HI-Z
SO
0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
Figure 9. WRSR Bus Configuration (WREN not shown)
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Data
Opcode
SI
0
SO
Document Number: 001-90311 Rev. *C
0
0
0
0
0
0
1 D7 X
MSB
X
X D3 D2 X
X
LSB
HI-Z
Page 8 of 20
FM25V20A
Memory Operation
Read Operation
After the falling edge of CS, the bus master can issue a READ
opcode. Following the READ command is a three-byte address
containing the 18-bit address (A17-A0) of the first byte of the
read operation. The upper six bits of the address are ignored.
After the opcode and address are issued, the device drives out
the read data on the next eight clocks. The SI input is ignored
during read data bytes. Subsequent bytes are data bytes, which
are read out sequentially. Addresses are incremented internally
as long as the bus master continues to issue clocks and CS is
LOW. If the last address of 3FFFFh is reached, the counter will
roll over to 00000h. Data is read MSB first. The rising edge of CS
terminates a read operation and tristates the SO pin. A read
operation is shown in Figure 11.
The SPI interface, which is capable of a high clock frequency,
highlights the fast write capability of the F-RAM technology.
Unlike serial flash and EEPROMs, the FM25V20A can perform
sequential writes at bus speed. No page register is needed and
any number of sequential writes may be performed.
Write Operation
All writes to the memory begin with a WREN opcode with CS
being asserted and deasserted. The next opcode is WRITE. The
WRITE opcode is followed by a three-byte address containing
the 18-bit address (A17-A0) of the first data byte to be written into
the memory. The upper six bits of the three-byte address are
ignored. Subsequent bytes are data bytes, which are written
sequentially. Addresses are incremented internally as long as
the bus master continues to issue clocks and keeps CS LOW. If
the last address of 3FFFFh is reached, the counter will roll over
to 00000h. Data is written MSB first. The rising edge of CS terminates a write operation. A write operation is shown in Figure 10.
Fast Read Operation
The FM25V20A supports a FAST READ opcode (0Bh) that is
provided for code compatibility with serial flash devices. The
FAST READ opcode is followed by a three-byte address
containing the 18-bit address (A17-A0) of the first byte of the
read operation and then a dummy byte. The dummy byte inserts
a read latency of 8-clock cycle. The fast read operation is
otherwise the same as an ordinary read operation except that it
requires an additional dummy byte. After receiving opcode,
address, and a dummy byte, the FM25V20A starts driving its SO
line with data bytes, with MSB first, and continues transmitting
as long as the device is selected and the clock is available. In
case of bulk read, the internal address counter is incremented
automatically, and after the last address 3FFFFh is reached, the
counter rolls over to 00000h. When the device is driving data on
its SO line, any transition on its SI line is ignored. The rising edge
of CS terminates a fast read operation and tristates the SO pin.
A Fast Read operation is shown in Figure 12.
Note When a burst write reaches a protected block address, the
automatic address increment stops and all the subsequent data
bytes received for write will be ignored by the device.
EEPROMs use page buffers to increase their write throughput.
This compensates for the technology's inherently slow write
operations. F-RAM memories do not have page buffers because
each byte is written to the F-RAM array immediately after it is
clocked in (after the eighth clock). This allows any number of
bytes to be written without page buffer delays.
Note If the power is lost in the middle of the write operation, only
the last completed byte will be written.
Figure 10. Memory Write (WREN not shown) Operation
CS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
Opcode
SI
0
0
0
0
0
7
~
~ ~
~
0
SCK
20 21 22 23 0
1
18-bit Address
0
1
0
X
X
X
X
X
X A17 A16
MSB
2
3
4
5
6
7
Data
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
LSB MSB
LSB
HI-Z
SO
Figure 11. Memory Read Operation
CS
1
2
3
4
5
6
7
0
1
2
3
4
SCK
Opcode
SI
0
0
0
0
0
5
6
7
~
~ ~
~
0
20 21 22 23 0
1
2
3
4
5
6
7
18-bit Address
0
1
1
X
X
X
MSB
SO
HI-Z
X
X
X A17 A16
A3 A2 A1 A0
LSB
Data
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Document Number: 001-90311 Rev. *C
LSB
Page 9 of 20
FM25V20A
Figure 12. Fast Read Operation
CS
1
2
3
4
5 6
7
0
1
2
3
4
5
6
7
~
~ ~
~
0
SCK
Opcode
SI
0
0
0
0
1
20 21 22 23 24 25 26 27 28 29 30 31 0
18-bit Address
0
1 1
X X
X
MSB
X
X X
3 4
X
5
6
7
X X X
LSB
Data
HI-Z
SO
2
Dummy Byte
A3 A2 A1 A0 X
X X A17 A16
X
1
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
Sleep Mode
A low-power sleep mode is implemented on the FM25V20 device. The device will enter the low-power state when the SLEEP opcode
B9h is clocked in and a rising edge of CS is applied. When in sleep mode, the SCK and SI pins are ignored and SO will be HI-Z, but
the device continues to monitor the CS pin. On the next falling edge of CS, the device will return to normal operation within tREC time.
The SO pin remains in a HI-Z state during the wakeup period. The device does not necessarily respond to an opcode within the
wakeup period. To start the wakeup procedure, the controller may send a “dummy” read, for example, and wait the remaining tREC time.
Figure 13. Sleep Mode Operation
Enters Sleep Mode
t REC Recovers from Sleep Mode
CS
0
1
2
3
4
5
6
t SU
7
SCK
SI
1
0
1
1
1
0
0
VALID IN
1
HI-Z
SO
Device ID
The FM25V20A device can be interrogated for its manufacturer, product identification, and die revision. The RDID opcode 9Fh allows
the user to read the manufacturer ID and product ID, both of which are read-only bytes. The JEDEC-assigned manufacturer ID places
the Cypress (Ramtron) identifier in bank 7; therefore, there are six bytes of the continuation code 7Fh followed by the single byte C2h.
There are two bytes of product ID, which includes a family code, a density code, a sub code, and the product revision code.
Table 6. Device ID
Device ID Description
71–16
(56 bits)
Device ID
(9 bytes)
Manufacturer ID
7F7F7F7F7F7FC22508h
0111111101111111011111110111
1111011111110111111111000010
Document Number: 001-90311 Rev. *C
15–13
(3 bits)
12–8
(5 bits)
7–6
(2 bits)
5–3
(3 bits)
2–0
(3 bits)
Product ID
Family
Density
Sub
Rev
Rsvd
001
00101
00
001
000
Page 10 of 20
FM25V20A
Figure 14. Read Device ID
CS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
~
~
0
SCK
Opcode
1
0
0 1
1
1
1
HI-Z
SO
1
D7 D6 D5 D4 D3 D2 D1 D0
~
~
SI
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
9-Byte Device ID
Endurance
The FM25V20A devices are capable of being accessed at least 1014 times, reads or writes. An F-RAM memory operates with a read
and restore mechanism. Therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array.
The F-RAM architecture is based on an array of rows and columns of 32K rows of 64-bits each. The entire row is internally accessed
once, whether a single byte or all eight bytes are read or written. Each byte in the row is counted only once in an endurance calculation.
Table 7 shows endurance calculations for a 64-byte repeating loop, which includes an opcode, a starting address, and a sequential
64-byte data stream. This causes each byte to experience one endurance cycle through the loop. F-RAM read and write endurance
is virtually unlimited even at a 25-MHz clock rate.
Table 7. Time to Reach Endurance Limit for Repeating 64-byte Loop
SCK Freq (MHz)
Endurance Cycles/sec
Endurance Cycles/year
Years to Reach Limit
25
45,950
1.45 × 1012
69.1
18,380
11
172.7
11
345.4
10
5
Document Number: 001-90311 Rev. *C
9,190
5.79 × 10
2.90 × 10
Page 11 of 20
FM25V20A
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Storage temperature ................................ –55 C to +125 C
Surface mount lead soldering
temperature (3 seconds) ......................................... +260 C
Maximum accumulated storage time
At 125 °C ambient temperature ................................. 1000 h
At 85 °C ambient temperature ................................ 10 Years
Ambient temperature
with power applied ................................... –55 °C to +125 °C
DC output current
(1 output at a time, 1s duration) .................................. 15 mA
Electrostatic Discharge Voltage Human Body
Supply voltage on VDD relative to VSS .........–1.0 V to +4.5 V
Model (JEDEC Std JESD22-A114-B) ........................... 4 kV
Charged Device Model
Input voltage ........... –1.0 V to +4.5 V and VIN < VDD + 1.0 V
(JEDEC Std JESD22-C101-A) .................................. 1.25 kV
DC voltage applied to outputs
in High-Z state .................................... –0.5 V to VDD + 0.5 V
Latch-up current .................................................... > 140 mA
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VDD + 2.0 V
Operating Range
Range
Ambient Temperature (TA)
VDD
Industrial
–40 C to +85 C
2.0 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min
Typ[2]
Max
Unit
VDD
Power supply
–
2.0
3.3
3.6
V
IDD
VDD supply current
SCK toggling between
VDD – 0.2 V and VSS,
other inputs
VSS or VDD – 0.2 V. SO = Open
fSCK = 1 MHz
–
–
0.30
mA
fSCK = 25 MHz
–
1.3
2
mA
CS = VDD.
All other inputs VSS or VDD.
TA = 25 C
–
100
150
µA
TA = 85 C
–
–
250
µA
CS = VDD.
All other inputs VSS or VDD.
TA = 25 C
–
3
5
µA
TA = 85 C
–
–
8
µA
–
–
±1
µA
–
–
±1
µA
0.7 × VDD
–
VDD + 0.3
V
– 0.3
–
0.3 × VDD
V
ISB
IZZ
VDD standby current
Sleep mode current
ILI
Input leakage current
ILO
VIH
Output leakage current VSS < VOUT < VDD
Input HIGH voltage
–
VSS < VIN < VDD
VIL
Input LOW voltage
–
VOH1
Output HIGH voltage
IOH = –1 mA, VDD = 2.7 V
VOH2
Output HIGH voltage
IOH = –100 µA
2.4
–
–
V
VDD – 0.2
–
–
V
VOL1
Output LOW voltage
IOL = 2 mA, VDD = 2.7 V
–
–
0.4
V
VOL2
Output LOW voltage
IOL = 150 µA
–
–
0.2
V
Note
2. Typical values are at 25 °C, VDD = VDD(typ). Not 100% tested.
Document Number: 001-90311 Rev. *C
Page 12 of 20
FM25V20A
Data Retention and Endurance
Parameter
TDR
NVC
Description
Data retention
Endurance
Test condition
Min
Max
Unit
TA = 85 C
10
–
Years
TA = 75 C
38
–
Years
TA = 65 C
151
–
Years
Over operating temperature
1014
–
Cycles
Capacitance
Parameter[3]
Description
CO
Output pin capacitance (SO)
CI
Input pin capacitance
Test Conditions
Max
Unit
8
pF
6
pF
Test Conditions
8-pin PDIP
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per EIA /
JESD51.
56
C/W
43
C/W
TA = 25 C, f = 1 MHz, VDD = VDD(typ)
Thermal Resistance
Parameter
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Conditions
Input pulse levels .................................10% and 90% of VDD
Input rise and fall times ...................................................3 ns
Input and output timing reference levels ................0.5 × VDD
Output load capacitance .............................................. 30 pF
Note
3. This parameter is characterized and not 100% tested.
Document Number: 001-90311 Rev. *C
Page 13 of 20
FM25V20A
AC Switching Characteristics
Over the Operating Range
Parameters[4]
Cypress
Parameter
VDD = 2.0 V to 3.6 V
Description
Alt. Parameter
Min
Max
Unit
fSCK
–
SCK clock frequency
0
25
MHz
tCH
–
Clock HIGH time
18
–
ns
tCL
–
Clock LOW time
18
–
ns
tCSU
tCSS
Chip select setup
12
–
ns
tCSH
tCSH
Chip select hold
12
–
ns
tOD[5, 6]
tHZCS
Output disable time
–
20
ns
tODV
tCO
Output data valid time
–
16
ns
tOH
–
Output hold time
0
–
ns
tD
–
Deselect time
60
–
ns
tR[6, 7]
–
Data in rise time
–
50
ns
tF[6, 7]
–
Data in fall time
–
50
ns
tSU
tSD
Data setup time
8
–
ns
tH
tHD
Data hold time
8
–
ns
Figure 15. Synchronous Data Timing (Mode 0)
tD
CS
tCSU
tCH
tCL
tCSH
SCK
tSU
SI
tH
VALID IN
VALID IN
VALID IN
tODV
SO
HI-Z
tOH
tOD
HI-Z
Notes
4. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 10% to 90% of VDD, and output loading of
the specified IOL/IOH and 30 pF load capacitance shown in AC Test Conditions on page 13.
5. tOD and tHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
6. Characterized but not 100% tested in production.
7. Rise and fall times measured between 10% and 90% of waveform.
Document Number: 001-90311 Rev. *C
Page 14 of 20
FM25V20A
Power Cycle Timing
Over the Operating Range
Parameter
Description
Min
Max
Unit
tPU
Power-up VDD(min) to first access (CS LOW)
1
–
ms
tPD
Last access (CS HIGH) to power-down (VDD(min))
0
–
µs
tVR[8]
VDD power-up ramp rate
50
–
µs/V
tVF[8]
VDD power-down ramp rate
100
–
µs/V
tREC[9]
Recovery time from sleep mode
–
450
µs
VDD
~
~
Figure 16. Power Cycle Timing
VDD(min)
tVR
CS
tVF
tPD
~
~
tPU
VDD(min)
Notes
8. Slope measured at any point on the VDD waveform.
9. Guaranteed by design. Refer to Figure 13 for sleep mode recovery timing.
Document Number: 001-90311 Rev. *C
Page 15 of 20
FM25V20A
Ordering Information
Ordering Code
FM25V20A-PG
Package Diagram
51-85075
Package Type
8-pin PDIP
Operating Range
Industrial
All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
FM 25
V
20
A - PG TR
Option: XX = blank or TR
blank = Standard; TR = Tape and Reel
Package Type:
PG = 8-pin PDIP
Die Revision: A
Density: 20 = 2-Mbit
Voltage: V = 2.0 V to 3.6 V
SPI F-RAM
Cypress
Document Number: 001-90311 Rev. *C
Page 16 of 20
FM25V20A
Package Diagrams
Figure 17. 8-pin PDIP (300 Mils) Package Outline, 51-85075
51-85075 *D
Document Number: 001-90311 Rev. *C
Page 17 of 20
FM25V20A
Acronyms
Document Conventions
Table 8. Acronyms Used in this Document
Acronym
Description
Units of Measure
Table 9. Units of Measure
CPHA
Clock Phase
Symbol
CPOL
Clock Polarity
°C
degree Celsius
EEPROM
Electrically Erasable Programmable Read-Only
Memory
Hz
hertz
EIA
Electronic Industries Alliance
kHz
kilohertz
F-RAM
Ferroelectric Random Access Memory
k
kilohm
I/O
Input/Output
JEDEC
Joint Electron Devices Engineering Council
JESD
JEDEC Standards
LSB
Least Significant Bit
MSB
Most Significant Bit
PDIP
Plastic Dual In-line Package
RoHS
Restriction of Hazardous Substances
SPI
Serial Peripheral Interface
Document Number: 001-90311 Rev. *C
Unit of Measure
Mbit
megabit
MHz
megahertz
µA
microampere
µF
microfarad
µs
microsecond
mA
milliampere
ms
millisecond
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 18 of 20
FM25V20A
Document History Page
Document Title: FM25V20A (PDIP), 2-Mbit (256 K × 8) Serial (SPI) F-RAM
Document Number: 001-90311
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
4209374
GVCH
01/22/2014
New data sheet.
*A
4372701
GVCH
06/02/2014
Changed status from Preliminary to Final.
Updated Maximum Ratings:
Changed “Human Body Model” from 2 kV to 4 kV under Electrostatic Discharge
Voltage.
Changed “Charged Device Model” from 500 V to 1.25 kV under Electrostatic
Discharge Voltage.
Removed “Machine Model” under Electrostatic Discharge Voltage.
Updated Ordering Information:
Removed FM25V20A-PGES part number.
*B
4878813
ZSK / PSR
08/10/2015
Updated Maximum Ratings:
Removed “Maximum junction temperature”.
Added “Maximum accumulated storage time”.
Added “Ambient temperature with power applied”.
Updated Package Diagrams:
spec 51-85075 – Changed revision from *C to *D.
Updated to new template.
*C
6570676
GVCH
05/15/2019
Removed HOLD pin function related information:
Logic Block Diagram: Removed HOLD pin.
Pinout (Figure 1): Updated Pin 7 from HOLD to DNU.
Pin Definitions:
Removed HOLD related information from SO pin definition.
Removed HOLD pin definition and added DNU pin definition.
Figure 2 and Figure 3: Removed HOLD pin connection.
Data Transmission (SI/SO): Removed HOLD pin related operation.
Page 9: Removed HOLD Pin Operation.
AC Switching Characteristics: Removed HOLD pin timings.
Removed HOLD pin timing (Figure 16).
Updated Copyright information.
Document Number: 001-90311 Rev. *C
Page 19 of 20
FM25V20A
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2014-2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves
all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If
the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal,
non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software
solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through
resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified)
to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, "Security
Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device"
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.s in the
United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-90311 Rev. *C
Revised May 15, 2019
Page 20 of 20
工商网监
湘ICP备2023018690号
