FULLFLEX

FullFlex FullFlexTM Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features ■ ■ Functional Description The FullFlex™ dual port SRAM families consist of 2-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual port static RAMs that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports are provided, enabling simultaneous access to the array. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports operate independently with 72-bit bus widths and each port is independently configured for two pipelined stages. Each port is also configured to operate in pipelined or flow through mode. The advanced features include the following: ■ True dual port memory enables simultaneous access to the shared array from each port Synchronous pipelined operation with single data rate (SDR) operation on each port ❐ SDR interface at 200 MHz ❐ Up to 28.8 Gb/s bandwidth (200 MHz × 72-bit × 2 ports) Selectable pipelined or flow-through mode 1.5 V or 1.8 V core power supply Commercial and Industrial temperature IEEE 1149.1 JTAG boundary scan Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36 and × 18) packages FullFlex72 family ❐ 36-Mbit: 512 K × 72 (CYD36S72V18) ❐ 18-Mbit: 256 K × 72 (CYD18S72V18) ❐ 9-Mbit: 128 K × 72 (CYD09S72V18) FullFlex36 family ❐ 36-Mbit: 1 M × 36 (CYD36S36V18) ❐ 18-Mbit: 512 K × 36 (CYD18S36V18) ❐ 9-Mbit: 256 K × 36 (CYD09S36V18) ❐ 2-Mbit: 64 K × 36 (CYD02S36V18) FullFlex18 family ❐ 36-Mbit: 2 M × 18 (CYD36S18V18) ❐ 18-Mbit: 1 M × 18 (CYD18S18V18) ❐ 9-Mbit: 512 K × 18 (CYD09S18V18) Built in deterministic access control to manage address collisions ❐ Deterministic flag output upon collision detection ❐ Collision detection on back-to-back clock cycles ❐ First busy address readback Advanced features for improved high speed data transfer and flexibility ❐ Variable impedance matching (VIM) ❐ Echo clocks ❐ Selectable LVTTL (3.3 V), Extended HSTL (1.4 V to 1.9 V), 1.8 V LVCMOS, or 2.5 V LVCMOS IO on each port ❐ Burst counters for sequential memory access ❐ Mailbox with interrupt flags for message passing ❐ Dual chip enables for easy depth expansion ■ ■ ■ ■ ■ ■ Built in deterministic access control to manage address collisions during simultaneous access to the same memory location Variable Impedance Matching (VIM) to improve data transmission by matching the output driver impedance to the line impedance Echo clocks to improve data transfer ■ ■ ■ To reduce the static power consumption, chip enables power down the internal circuitry. The number of latency cycles before a change in CE0 or CE1 enables or disables the databus matches the number of cycles of read latency selected for the device. For a valid write or read to occur, activate both chip enable inputs on a port. Each port contains an optional burst counter on the input address register. After externally loading the counter with the initial address, the counter increments the address internally. Additional device features include a mask register and a mirror register to control counter increments and wrap around. The counter interrupt (CNTINT) flags notify the host that the counter reaches maximum count value on the next clock cycle. The host reads the burst counter internal address, mask register address, and busy address on the address lines. The host also loads the counter with the address stored in the mirror register by using the retransmit functionality. Mailbox interrupt flags are used for message passing, and JTAG boundary scan and asynchronous Master Reset (MRST) are also available. The Logic Block Diagram on page 2 shows these features. The FullFlex72 is offered in a 484-ball plastic BGA package. The FullFlex36 and FullFlex18 are available in 256-ball fine pitch BGA package except the 36-Mbit devices which are offered in 484-ball plastic BGA package. ■ ■ ■ Cypress Semiconductor Corporation Document Number: 38-06082 Rev. *K • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 31, 2011 [+] Feedback FullFlex Logic Block Diagram The Logic Block Diagram for FullFlex72, FullFlex36, and FullFlex18 family follows: [1, 2, 3] FTSELL CQENL PORTSTD[1:0]L CONFIG Block CONFIG Block FTSELR CQENR PORTSTD[1:0]R DQ[71:0]L BE [7:0]L CE0L CE1L OEL R/WL CQ1L CQ1L CQ0L CQ0L IO Control IO Control DQ [71:0]R BE [7:0]R CE0R CE1R OER R/WR CQ1R CQ1R CQ0R CQ0R Dual Port Array BUSYL A [20:0]L CNT/MSKL ADSL CNTENL CNTRSTL RETL CNTINTL CL WRPL Collision Detection Logic BUSYR A [20:0]R CNT/MSKR ADSR CNTENR CNTRSTR RETR CNTINTR CR WRPR Address & Counter Logic Address & Counter Logic Mailboxes INTL INTR JTAG TRST TMS TDI TDO TCK ZQ0R ZQ1R MRST READYR LowSPDR ZQ0L ZQ1L READYL LowSPDL RESET LOGIC Notes 1. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits. The CYD02S36V18 has 16 address bits. 2. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines. 3. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte enables. Document Number: 38-06082 Rev. *K Page 2 of 52 [+] Feedback FullFlex Contents Selection Guide ................................................................ 9 Pin Definitions .................................................................. 9 Selectable IO Standard ............................................. 11 Clocking ..................................................................... 11 Selectable Pipelined or Flow through Mode .............. 11 DLL ............................................................................ 11 Echo Clocking ........................................................... 11 Deterministic Access Control .................................... 11 Variable Impedance Matching ....................................... 12 Address Counter and Mask Register Operations ...... 13 Counter Load Operation ............................................ 13 Mask Load Operation ................................................ 13 Counter Readback Operation .................................... 13 Mask Readback Operation ........................................ 13 Counter Reset Operation .......................................... 13 Mask Reset Operation ............................................... 13 Increment Operation .................................................. 15 Hold Operation .......................................................... 15 Retransmit ................................................................. 15 Counter Interrupt ....................................................... 15 Counting by Two ....................................................... 15 Counting by Four ....................................................... 15 Mailbox Interrupts ...................................................... 15 Master Reset ............................................................. 18 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 18 Maximum Ratings ........................................................... 19 Operating Range ............................................................. 19 Power Supply Requirements ......................................... 19 Electrical Characteristics ............................................... 19 Electrical Characteristics ............................................... 21 Electrical Characteristics ............................................... 24 AC Test Load and Waveforms ....................................... 25 Switching Characteristics .............................................. 26 Switching Waveforms .................................................... 29 Ordering Information ...................................................... 43 512 K × 72 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S72V18 Dual Port SRAM ...................................... 43 256 K × 72 (18-Mbit) 1.8 V/1.5 V Synchronous CYD18S72V18 Dual Port SRAM ...................................... 43 128 K × 72 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S72V18 Dual Port SRAM ...................................... 43 1024 K × 36 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S36V18 Dual Port SRAM ...................................... 43 512 K × 36 (18-Mbit) 1.8 V/1.5 V Synchronous CYD18S36V18 Dual Port SRAM ...................................... 43 256 K × 36 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S36V18 Dual Port SRAM ...................................... 44 64 K × 36 (2-Mbit) 1.8 V or 1.5 V Synchronous CYD02S36V18 Dual Port SRAM ...................................... 44 2048 K × 18 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S18V18 Dual Port SRAM ...................................... 45 1024 K × 18 (18-Mbit) 1.8 V/1.5 V Synchronous CYD18S18V18 Dual Port SRAM ...................................... 45 512 K × 18 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S18V18 Dual Port SRAM ...................................... 45 Ordering Code Definitions ......................................... 45 Package Diagrams .......................................................... 46 Acronyms ........................................................................ 48 Document Conventions ................................................. 48 Units of Measure ....................................................... 48 Document History Page ................................................. 49 Sales, Solutions, and Legal Information ...................... 52 Worldwide Sales and Design Support ....................... 52 Products .................................................................... 52 PSoC Solutions ......................................................... 52 Document Number: 38-06082 Rev. *K Page 3 of 52 [+] Feedback FullFlex Figure 1. FullFlex72 SDR 484-ball BGA Pinout (Top View) 1 A 2 3 DQ59L 4 5 6 DQ51L DQ52L DQ53L CQ1L 7 DQ48L DQ49L DQ50L CQ1L 8 DQ45L DQ46L DQ47L VSS 9 DQ42L DQ43L DQ44L 10 DQ39L DQ40L DQ41L 11 12 13 DQ39R DQ40R DQ41R 14 DQ42R DQ43R DQ44R 15 16 17 18 19 20 DQ59R DQ60R VSS VSS 21 DQ61R 22 DNU DNU DQ61L DQ57L DQ54L DQ58L DQ55L VSS VSS VSS CE0L BE4L BE5L BE6L BE7L OEL BE3L BE2L BE1L BE0L DQ56L VSS VSS DQ36L DQ36R DQ37L DQ37R DQ38L DQ38R DQ45R DQ48R DQ51R DQ54R DQ57R DQ46R DQ49R DQ52R DQ55R DQ58R DQ47R DQ50R DQ53R DQ56R DNU CQ1R CQ1R VSS DNU VSS VSS VSS B DQ63L DQ62L DQ60L C DQ65L DQ64L D DQ67L DQ66L VSS VSS DQ62R DQ63R DQ64R DQ65R DQ66R DQ67R LOWSPDL PORTSTD0L ZQ0L[4] BUSYL CNTINTL PORTSTD1L E DQ69L DQ68L VDDIOL F DQ71L DQ70L G H J K L M N P A0L A2L A4L A6L A8L A10L A12L A14L A1L A3L A5L A7L A9L A11L A13L CE1L RETL WRPL READYL ZQ1L[4, 5] CL VSS ADSL VDDIOL VDDIOL VDDIOL VDDIOL VDDIOL VTTL VTTL VTTL VDDIOR VDDIOR VDDIOR VDDIOR VDDIOR DQ68R DQ69R CE1R RETR WRPR READYR DQ70R DQ71R A1R A3R A5R A7R A9R A11R A13R A15R A0R A2R A4R A6R A8R A10R A12R A14R VDDIOL VDDIOL VDDIOL VDDIOL VDDIOL VDDIOL VDDIOL VREFL VDDIOL VDDIOL VDDIOL VDDIOL VTTL VTTL VTTL VCORE VCORE VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VCORE VCORE VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VDDIOR VDDIOR VDDIOR VDDIOR VDDIOR CE0R VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VREFR VDDIOR VDDIOR BE4R VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR BE5R VDDIOR VDDIOR BE6R VCORE VDDIOR BE7R ZQ1R[4, 5] VCORE VCORE VCORE VTTL VTTL VTTL OER BE3R BE2R CR VSS ADSR VDDIOL VCORE VDDIOL VDDIOL VDDIOL VDDIOL A15L CNT/MSKL VDDIOR VDDIOR BE1R CNT/MSKR VDDIOR VDDIOR BE0R INTR R A16L[8] A17L[7] CNTENL CNTENR A17R[7] A16R[8] CNTRSTR T A18L[6] DNU CNTRSTL INTL U DQ35L DQ34L R/WL VDDIOL VDDIOL VREFL VREFR VDDIOR VDDIOR DNU A18R[6] CQENL VDDIOL VDDIOL VDDIOL VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR VDDIOR VDDIOR VDDIOR CQENR TRST VSS VDDIOR R/WR DQ34R DQ35R V DQ33L DQ32L FTSELL W DQ31L DQ30L Y DQ29L DQ28L VSS VSS DNU VSS DQ20L VDDIOL VDDIOL VDDIOL VDDIOL CQ0L DQ17L DQ16L DQ15L CQ0L DQ14L DQ13L DQ12L DNU DQ11L DQ10L DQ9L PORTSTD1R VTTL VTTL VDDIOR VDDIOR VDDIOR VDDIOR VDDIOR PORTSTD0R FTSELR DQ32R DQ33R TDO TCK DQ24R DQ23R DQ30R DQ31R DQ28R DQ29R DQ26R DQ27R DQ25R DNU MRST VSS CNTINTR BUSYR ZQ0R[4] DQ5L DQ4L DQ3L DQ2L DQ1L DQ0L DQ2R DQ1R DQ0R LOWSPDR VSS DQ11R CQ0R CQ0R TDI TMS DQ8L DQ7L DQ6L DQ5R DQ4R DQ3R DQ8R DQ7R DQ6R DQ14R DQ17R DQ20R AA DQ27L DQ26L DQ24L AB DNU DQ25L DQ23L DQ22L DQ19L DQ21L DQ18L DQ10R DQ13R DQ16R DQ19R DQ22R DQ9R DQ12R DQ15R DQ18R DQ21R Notes 4. Leave this ball unconnected to disable VIM. 5. This ball is applicable only for 36-Mbit and DNU for 18-Mbit and lower densities. 6. Leave this Ball unconnected for CYD18S72V18 and CYD09S72V18. 7. Leave this Ball unconnected for CYD09S72V18. 8. Leave this Ball unconnected for CYD04S72V18. Document Number: 38-06082 Rev. *K Page 4 of 52 [+] Feedback FullFlex Figure 2. FullFlex36 SDR 484-ball BGA Pinout (Top View)[9] 1 2 3 DNU DNU VSS VSS 4 DNU DNU VSS VSS VSS CE0L BE2L BE3L DNU DNU OEL DNU DNU BE1L BE0L INTL 5 DNU DNU DNU VSS VSS 6 DQ33L DQ34L DQ35L CQ1L 7 DQ30L DQ31L DQ32L CQ1L 8 DQ27L DQ28L DQ29L VSS 9 DQ24L DQ25L DQ26L 10 DQ21L DQ22L DQ23L 11 DQ18L DQ19L DQ20L 12 DQ18R DQ19R DQ20R 13 DQ21R DQ22R DQ23R CNTINTL VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VDDIOL PORTSTD0R 14 DQ24R DQ25R DQ26R PORTSTD1L 15 16 17 18 DNU DNU DNU VSS DNU 19 DNU DNU VSS VSS VSS CE0R BE2R BE3R DNU DNU OER DNU DNU BE1R BE0R INTR 20 DNU DNU VSS VSS 21 22 A DNU DNU B DNU DNU C DNU DNU D DNU DNU DQ27R DQ30R DQ33R DQ28R DQ31R DQ34R DQ29R DQ32R DQ35R DNU CQ1R CQ1R DNU DNU DNU DNU DNU DNU DNU DNU LOWSPDL PORTSTD0L ZQ0L[10] BUSYL E DNU DNU VDDIOL F DNU DNU G H J K L A0L A2L A4L A6L A8L A1L A3L CE1L RETL WRPL VDDIOL VDDIOR VDDIOR VDDIOR VDDIOR VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL VTTL VTTL VDDIOL VDDIOL VDDIOL VDDIOL VDDIOR DNU DNU CE1R RETR WRPR DNU DNU A1R A0R A3R A2R VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR VDDIOL VDDIOL VREFL VDDIOL VDDIOL VDDIOL VDDIOL VTTL VTTL VTTL VCORE VCORE VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOL VDDIOL VDDIOL VDDIOR VDDIOR VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VREFR VDDIOR VDDIOR VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR VDDIOR VDDIOR VCORE VDDIOR VCORE VCORE VCORE VTTL VTTL VTTL A5L READYL A7L ZQ1L[10] A9L CL VSS ADSL CNT/MSKL READYR A5R A4R ZQ1R[10] A7R A6R CR VSS ADSR A9R A8R A11R A10R A13R A12R M A10L A11L N A12L A13L P A14L A15L VDDIOL VCORE VDDIOL VDDIOL VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR VDDIOR CNT/MSKR A15R A14R R A16L A17L CNTENL T A18L A19L U DNU DNU CNTRSTL CNTENR A17R A16R CNTRSTR A19R A18R VDDIOL VDDIOL VREFL VREFR VDDIOR VDDIOR R/WL CQENL VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR DNU VSS DNU DNU DNU VDDIOR VDDIOR VDDIOR VDDIOR CQ0L DQ17L DQ16L DQ15L CQ0L DQ14L DQ13L DQ12L DNU DQ11L DQ10L DQ9L PORTSTD1R VCORE VCORE VTTL VTTL VDDIOL VDDIOL VDDIOL VDDIOR VDDIOR CQENR VDDIOL VDDIOL VDDIOL VDDIOR LOWSPDR R/WR DNU DNU V DNU DNU FTSELL VDDIOL W DNU DNU Y DNU DNU AA DNU DNU AB DNU DNU VSS VSS DNU DNU MRST VSS DNU DNU TRST VSS DNU DNU DNU VDDIOR FTSELR DNU DNU TDI TMS DNU DNU TDO TCK DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU CNTINTR BUSYR ZQ0R[10] DQ5L DQ4L DQ3L DQ2L DQ1L DQ0L DQ2R DQ1R DQ0R VSS DQ11R CQ0R CQ0R DQ8L DQ7L DQ6L DQ5R DQ4R DQ3R DQ8R DQ7R DQ6R DQ14R DQ17R DQ10R DQ13R DQ16R DQ9R DQ12R DQ15R Notes 9. Use this pinout only for device CYD36S36V18 of the FullFlex36 family. 10. Leave this ball unconnected to disable VIM. Document Number: 38-06082 Rev. *K Page 5 of 52 [+] Feedback FullFlex Figure 3. FullFlex18 SDR 484-ball BGA Pinout (Top View)[11] 1 2 3 DNU DNU VSS VSS 4 DNU DNU VSS VSS VSS CE0L BE1L DNU DNU DNU OEL DNU DNU DNU BE0L INTL 5 DNU DNU DNU VSS VSS 6 DNU DNU DNU CQ1L 7 DNU DNU DNU CQ1L 8 DNU DNU DNU VSS 9 DQ15L DQ16L DQ17L 10 DQ12L DQ13L DQ14L 11 DQ9L DQ10L DQ11L 12 DQ9R DQ10R DQ11R 13 DQ12R DQ13R DQ14R CNTINTL VTTL VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VDDIOL PORTSTD0R 14 DQ15R DQ16R DQ17R PORTSTD1L 15 DNU DNU DNU DNU 16 DNU DNU DNU CQ1R 17 DNU DNU DNU CQ1R 18 DNU DNU DNU VSS DNU 19 DNU DNU VSS VSS VSS CE0R BE1R DNU DNU DNU OER DNU DNU DNU BE0R INTR 20 DNU DNU VSS VSS 21 22 A DNU DNU B DNU DNU C DNU DNU D DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU LOWSPDL PORTSTD0L ZQ0L[12] BUSYL E DNU DNU VDDIOL F DNU DNU G H J K L A0L A2L A4L A6L A8L A1L A3L A5L A7L A9L CE1L RETL WRPL READYL ZQ1L[12] CL VSS ADSL CNT/MSKL VDDIOL VDDIOR VDDIOR VDDIOR VDDIOR VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VTTL VTTL VTTL VDDIOL VDDIOL VDDIOL VDDIOL VDDIOR DNU DNU CE1R RETR WRPR DNU DNU A1R A0R A3R A2R VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR VDDIOL VDDIOL VREFL VDDIOL VDDIOL VDDIOL VDDIOL VTTL VTTL VTTL VCORE VCORE VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCORE VCORE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIOL VDDIOL VDDIOL VDDIOR VDDIOR VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VREFR VDDIOR VDDIOR VSS VSS VSS VSS VSS VSS VSS VSS VDDIOR VDDIOR VDDIOR VDDIOR VCORE VDDIOR VCORE VCORE VCORE VTTL VTTL VTTL READYR A5R A4R ZQ1R[12] A7R A6R CR VSS ADSR A9R A8R A11R A10R A13R A12R M A10L A11L N A12L A13L P A14L A15L VDDIOL VCORE VDDIOL VDDIOL VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR VDDIOR CNT/MSKR A15R A14R R A16L A17L CNTENL T A18L A19L CNTRSTL U A20L DNU R/WL CNTENR A17R A16R CNTRSTR A19R A18R VDDIOL VDDIOL VREFL VREFR VDDIOR VDDIOR CQENL VDDIOL VDDIOL VDDIOR VDDIOR VDDIOR DNU VSS DNU DNU DNU VDDIOR VDDIOR VDDIOR VDDIOR CQ0L DNU DNU DNU CQ0L DNU DNU DNU DNU DNU DNU DNU PORTSTD1R VCORE VCORE VTTL VTTL VDDIOL VDDIOL VDDIOL VDDIOR VDDIOR CQENR VDDIOL VDDIOL VDDIOL VDDIOR LOWSPDR R/WR DNU A20R V DNU DNU FTSELL VDDIOL W DNU DNU Y DNU DNU AA DNU DNU AB DNU DNU VSS VSS DNU DNU MRST VSS DNU DNU TRST VSS DNU DNU DNU VDDIOR FTSELR DNU DNU TDI TMS DNU DNU TDO TCK DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU CNTINTR BUSYR ZQ0R[12] DQ5L DQ4L DQ3L DQ2L DQ1L DQ0L DQ2R DQ1R DQ0R VSS DNU DNU DNU CQ0R DNU DNU DNU CQ0R DNU DNU DNU DQ8L DQ7L DQ6L DQ5R DQ4R DQ3R DQ8R DQ7R DQ6R Notes 11. Use this pinout only for device CYD36S18V18 of the FullFlex18 family. 12. Leave this ball unconnected to disable VIM. Document Number: 38-06082 Rev. *K Page 6 of 52 [+] Feedback FullFlex Figure 4. FullFlex36 SDR 256-ball BGA (Top View) 1 A B C D E F G H J K L M N P R T DQ32L DQ33L DQ34L A0L A2L A4L A6L A8L A10L A12L A14L A16L[16] A18L[14] DQ16L DQ15L DQ14L 2 DQ30L DQ31L DQ35L A1L A3L A5L A7L A9L A11L A13L A15L A17L[15] DNU DQ17L DQ13L DQ12L 3 DQ28L DQ29L RETL WRPL CE0L CNTINTL BUSYL CL VSS OEL ADSL R/WL CNT/MSKL CNTENL DQ11L DQ10L 4 DQ26L DQ27L INTL VREFL CE1L BE3L BE2L VTTL PORTSTD1L BE1L BE0L CQENL VREFL CNTRSTL DQ9L DQ8L 5 DQ24L DQ25L CQ1L FTSELL VDDIOL VDDIOL ZQ0L[13] VCORE VCORE VDDIOL VDDIOL VDDIOL PORTSTD0L CQ0L DQ7L DQ6L 6 DQ22L DQ23L CQ1L LOWSPDL VDDIOL VSS VSS VSS VSS VSS VSS VDDIOL READYL CQ0L DQ5L DQ4L 7 DQ20L DQ21L DNU VSS VDDIOL VSS VSS VSS VSS VSS VSS VDDIOL DNU TCK DQ3L DQ2L 8 DQ18L DQ19L TRST VTTL VCORE VSS VSS VSS VSS VSS VSS VCORE VTTL TMS DQ1L DQ0L 9 DQ18R DQ19R MRST VTTL VCORE VSS VSS VSS VSS VSS VSS VCORE VTTL TDO DQ1R DQ0R 10 DQ20R DQ21R ZQ0R[13] VSS VDDIOR VSS VSS VSS VSS VSS VSS VDDIOR DNU TDI DQ3R DQ2R 11 DQ22R DQ23R CQ1R LOWSPDR VDDIOR VSS VSS VSS VSS VSS VSS VDDIOR 12 DQ24R DQ25R CQ1R FTSELR VDDIOR VDDIOR VDDIOR VCORE VCORE VDDIOR VDDIOR VDDIOR 13 DQ26R DQ27R INTR VREFR CE1R BE3R BE2R VTTL PORTSTD1R BE1R BE0R CQENR VREFR CNTRSTR DQ9R DQ8R 14 DQ28R DQ29R RETR WRPR CE0R CNTINTR BUSYR CR VSS OER ADSR R/WR CNT/MSKR CNTENR DQ11R DQ10R 15 DQ30R DQ31R DQ35R A1R A3R A5R A7R A9R A11R A13R A15R A17R[15] DNU DQ17R DQ13R DQ12R 16 DQ32R DQ33R DQ34R A0R A2R A4R A6R A8R A10R A12R A14R A16R[16] A18R[14] DQ16R DQ15R DQ14R READYR PORTSTD0R CQ0R DQ5R DQ4R CQ0R DQ7R DQ6R Notes 13. Leave this ball unconnected to disable VIM. 14. Leave this ball unconnected for CYD09S36V18 and CYD02S36V18. 15. Leave this ball unconnected for CYD02S36V18. 16. Leave this ball unconnected for CYD02S36V18. Document Number: 38-06082 Rev. *K Page 7 of 52 [+] Feedback FullFlex Figure 5. FullFlex18 SDR 256-ball BGA (Top View) 1 A B C D E F G H J K L M N P R T DNU DNU DNU A0L A2L A4L A6L A8L A10L A12L A14L A16L A18L[19] DNU DNU DNU 2 DNU DNU DNU A1L A3L A5L A7L A9L A11L A13L A15L A17L A19L[18] DNU DNU DNU 3 DNU DNU RETL WRPL CE0L CNTINTL BUSYL CL VSS OEL ADSL R/WL CNT/MSKL CNTENL DNU DNU 4 DQ17L DNU INTL VREFL CE1L DNU DNU VTTL PORTSTD1L BE1L BE0L CQENL VREFL CNTRSTL DNU DQ8L 5 DQ16L DQ15L CQ1L FTSELL VDDIOL VDDIOL ZQ0L[17] VCORE VCORE VDDIOL VDDIOL VDDIOL PORTSTD0L CQ0L DQ6L DQ7L 6 DQ13L DQ14L CQ1L LOWSPDL VDDIOL VSS VSS VSS VSS VSS VSS VDDIOL READYL CQ0L DQ5L DQ4L 7 DQ12L DQ11L DNU VSS VDDIOL VSS VSS VSS VSS VSS VSS VDDIOL DNU TCK DQ2L DQ3L 8 DQ9L DQ10L TRST VTTL VCORE VSS VSS VSS VSS VSS VSS VCORE VTTL TMS DQ1L DQ0L 9 DQ9R DQ10R MRST VTTL VCORE VSS VSS VSS VSS VSS VSS VCORE VTTL TDO DQ1R DQ0R 10 DQ12R DQ11R ZQ0R[17] VSS VDDIOR VSS VSS VSS VSS VSS VSS VDDIOR DNU TDI DQ2R DQ3R 11 DQ13R DQ14R CQ1R LOWSPDR VDDIOR VSS VSS VSS VSS VSS VSS VDDIOR READYR CQ0R DQ5R DQ4R 12 DQ16R DQ15R CQ1R FTSELR VDDIOR VDDIOR VDDIOR VCORE VCORE VDDIOR VDDIOR VDDIOR PORTSTD0R CQ0R DQ6R DQ7R 13 DQ17R DNU INTR VREFR CE1R DNU DNU VTTL PORTSTD1R BE1R BE0R CQENR VREFR CNTRSTR DNU DQ8R 14 DNU DNU RETR WRPR CE0R CNTINTR BUSYR CR VSS OER ADSR R/WR CNT/MSKR CNTENR DNU DNU 15 DNU DNU DNU A1R A3R A5R A7R A9R A11R A13R A15R A17R A19R[18] DNU DNU DNU 16 DNU DNU DNU A0R A2R A4R A6R A8R A10R A12R A14R A16R A18R[19] DNU DNU DNU Notes 17. Leave this ball unconnected to disable VIM. 18. Leave this ball unconnected for CYD09S18V18. 19. Leave this ball unconnected for CYD04S18V18. Document Number: 38-06082 Rev. *K Page 8 of 52 [+] Feedback FullFlex Selection Guide Parameter fMAX[21] Maximum access time (clock to data) Typical operating current ICC Typical standby current for ISB3 (both ports CMOS level) -200 200 3.3 800 [20] -167 167 4.0 700 [20] Unit MHz ns mA mA 210[20] 210[20] Pin Definitions Left Port A[20:0]L DQ[71:0]L BE[7:0]L BUSYL CL CE0L CE1L CQENL CQ0L CQ0L Right Port A[20:0]R DQ[71:0]R BE[7:0]R BUSYR CR CE0R CE1R CQENR CQ0R CQ0R Address inputs. [22] Description Data bus input and output.[23] Byte select inputs.[24] Asserting these signals enables read and write operations to the corresponding bytes of the memory array. Port busy output. When there is an address match and both chip enables are active for both ports, an external BUSY signal is asserted on the fifth clock cycles from when the collision occurs. Clock signal. Maximum clock input rate is fMAX. Active LOW chip enable input. Active HIGH chip enable input. Echo clock enable input. Assert HIGH to enable echo clocking on respective port. Echo clock signal output for DQ[35:0] for FullFlex72 devices. Echo clock signal output for DQ[17:0] for FullFlex36 devices. Echo clock signal output for DQ[8:0] for FullFlex18 devices. Inverted echo clock signal output for DQ[35:0] for FullFlex72 devices. Inverted echo clock signal output for DQ[17:0] for FullFlex36 devices. Inverted echo clock signal output for DQ[8:0] for FullFlex18 devices. Echo clock signal output for DQ[71:36] for FullFlex72 devices. Echo clock signal output for DQ[35:18] for FullFlex36 devices. Echo clock signal output for DQ[17:9] for FullFlex18 devices. Inverted echo clock signal output for DQ[71:36] for FullFlex72 devices. Inverted echo clock signal output for DQ[35:18] for FullFlex36 devices. Inverted echo clock signal output for DQ[17:9] for FullFlex18 devices. VIM output impedance matching input.[25] To use, connect a calibrating resistor between ZQ and ground. The resistor must be five times larger than the intended line impedance driven by the dual port. Assert HIGH or leave DNU to disable VIM. Output enable input. This asynchronous signal must be asserted LOW to enable the DQ data pins during read operations. Mailbox interrupt flag output. The mailbox permits communications between ports. The upper two memory locations are used for message passing. INTL is asserted LOW when the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of its mailbox. Port low speed select input. Assert this pin LOW to disable the DLL. In flow through mode, this pin needs to be asserted low. CQ1L CQ1L CQ1R CQ1R ZQ[1:0]L ZQ[1:0]R OEL INTL OER INTR LowSPDL LowSPDR Notes 20. For 18 Mbit x72 commercial configuration only, refer to Electrical Characteristics on page 19 for complete information. 21. SDR mode with two pipelined stages. 22. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits. The CYD02S36V18 has 16 address bits. 23. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines. 24. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte enables. 25. The pin ZQ[1] is applicable only for 36 Mbit devices. This pin is DNU for 18 Mbit and lower density devices. Document Number: 38-06082 Rev. *K Page 9 of 52 [+] Feedback FullFlex Pin Definitions (continued) Left Port PORTSTD[1:0]L [26] Right Port PORTSTD[1:0]R [26] Description Port clock/Address/Control/Data/Echo clock/I/O standard select input. Assert these pins LOW/LOW for LVTTL, LOW/HIGH for HSTL, HIGH/LOW for 2.5 V LVCMOS, and HIGH/HIGH for 1.8 V LVCMOS, respectively. These pins are driven by VTTL referenced levels. Read/Write enable input. Assert this pin LOW to write to, or HIGH to read from the dual port memory array. Port DLL ready output. This signal is asserted LOW when the DLL and variable impedance matching circuits complete calibration. This is a wired OR capable output. Port counter/Mask select input. Counter control input. Port counter address load strobe input. Counter control input. Port counter enable input. Counter control input. Port counter reset input. Counter control input. Port counter interrupt output. This pin is asserted LOW one cycle before the unmasked portion of the counter is incremented to all “1s”. Port counter wrap input. When the burst counter reaches the maximum count, on the next counter increment WRP is set LOW to load the unmasked counter bits to 0. It is set HIGH to load the counter with the value stored in the mirror register. Port counter retransmit input. Assert this pin LOW to reload the initial address for repeated access to the same segment of memory. Port external HSTL IO reference input. This pin is left DNU when HSTL is not used. Port data IO power supply. Port flow through mode select input. Assert this pin LOW to select flow through mode. Assert this pin HIGH to select Pipelined mode. Master reset input. MRST is an asynchronous input signal and affects both ports. Asserting MRST LOW performs all of the reset functions as described in the text. A MRST operation is required at power up. This pin is driven by a VDDIOL referenced signal. JTAG test mode select input. It controls the advance of JTAG TAP state machine. State machine transitions occur on the rising edge of TCK. Operation for LVTTL or 2.5 V LVCMOS. JTAG test data input. Data on the TDI input is shifted serially into selected registers. Operation for LVTTL or 2.5 V LVCMOS. JTAG reset input. Operation for LVTTL or 2.5 V LVCMOS. JTAG test clock input. Operation for LVTTL or 2.5 V LVCMOS. JTAG test data output. TDO transitions occur on the falling edge of TCK. TDO is normally tri-stated except when captured data is shifted out of the JTAG TAP. Operation for LVTTL or 2.5 V LVCMOS. Ground inputs. Device core power supply. LVTTL power supply. R/WL READYL CNT/MSKL ADSL CNTENL CNTRSTL CNTINTL WRPL R/WR READYR CNT/MSKR ADSR CNTENR CNTRSTR CNTINTR WRPR RETL VREFL VDDIOL FTSELL MRST RETR VREFR VDDIOR FTSELR TMS TDI TRST TCK TDO VSS VCORE VTTL Note 26. PORTSTD[1:0]L and PORTSTD[1:0]R have internal pull-down resistors. Document Number: 38-06082 Rev. *K Page 10 of 52 [+] Feedback FullFlex Selectable IO Standard The FullFlex device families offer the option to choose one of the four port standards for the device. Each port independently selects standards from single ended HSTL class I, single ended LVTTL, 2.5 V LVCMOS, or 1.8 V LVCMOS. The selection of the standard is determined by the PORTSTD pins for each port. These pins must be connected to an LVTTL power suppy. This determines the input clock, address, control, data, and Echo clock standard for each port as shown in Table 1. Table 1. Port Standard Selection PORTSTD1 VSS VSS VTTL VTTL PORTSTD0 VSS VTTL VSS VTTL I/O Standard LVTTL HSTL 2.5 V LVCMOS 1.8 V LVCMOS LowSPD pins are used to reset the DLLs for a single port independent of all other circuitry. MRST is used to reset all DLLs on the chip. For more information on DLL lock and reset time, see Master Reset on page 18. Echo Clocking As the speed of data increases, on-board delays caused by parasitics make it extremely difficult to provide accurate clock trees. To counter this problem, the FullFlex families incorporate Echo Clocks. Echo Clocks are enabled on a per port basis. The dual port receives input clocks that are used to clock in the address and control signals for a read operation. The dual port retransmits the input clocks relative to the data output. The buffered clocks are provided on the CQ1/CQ1 and CQ0/CQ0 outputs. Each port has a pair of Echo clocks. Each clock is associated with half the data bits. The output clock matches the corresponding ports IO configuration. To enable echo clock outputs, tie CQEN HIGH. To disable echo clock outputs, tie CQEN LOW. Figure 6. SDR Echo Clock Delay Input Clock Data Out Echo Clock Clocking Separate clocks synchronize the operations on each port. Each port has one clock input C. In this mode, all the transactions on the address, control, and data are on the C rising edge. All transactions on the address, control, data input, output, and byte enables occur on the C rising edge. Table 2. Data Pin Assignment BE Pin Name BE[7] BE[6] BE[5] BE[4] BE[3] BE[2] BE[1] BE[0] Data Pin Name DQ[71:63] DQ[62:54] DQ[53:45] DQ[44:36] DQ[35:27] DQ[26:18] DQ[17:9] DQ[8:0] Echo Clock Deterministic Access Control Deterministic Access Control is provided for ease of design. The circuitry detects when both ports access the same location and provides an external BUSY flag to the port on which data is corrupted. The collision detection logic saves the address in conflict (Busy Address) to a readable register. In the case of multiple collisions, the first busy address is written to the busy address register. If both ports access the same location at the same time and only one port is doing a write, if tCCS is met, then the data written to and read from the address is valid data. For example, if the right port is reading and the left port is writing and the left ports clock meets tCCS, then the data read from the address by the right port is the old data. In the same case, if the right ports clock meets tCCS, then the data read out of the address from the right port is the new data. In the above case, if tCCS is violated by the either ports clock with respect to the other port and the right port gets the external BUSY flag, the data from the right port is corrupted. Table 3 on page 12 shows the tCCS timing that must be met to guarantee the data. Table 4 on page 12 shows that, in the case of the left port writing and the right port reading, when an external BUSY flag is asserted on the right port, the data read out of the device is not guaranteed. The value in the busy address register is read back to the address lines. The required input control signals for this function are shown in Table 7 on page 14. The value in the busy address register is read out to the address lines tCA after the same amount of latency as a data read operation. After an initial address match, the BUSY flag is asserted and the address under contention is saved in the busy address register. All the following Page 11 of 52 Selectable Pipelined or Flow through Mode To meet data rate and throughput requirements, the FullFlex families offer selectable pipelined or flow through mode. Echo clocks are not supported in flow through mode and the DLL must be disabled. Flow through mode is selected by the FTSEL pin. Strapping this pin HIGH selects pipelined mode. Strapping this pin LOW selects flow through mode. DLL The FullFlex familes of devices have an on-chip DLL. Enabling the DLL reduces the clock to data valid (tCD) time enabling more setup time for the receiving device. In flow through mode, the DLL must be disabled. This is selectable by strapping LowSPD low. Whenever the operating frequency is altered beyond the Clock Input Cycle to Cycle Jitter specification, reset the DLL, followed by 1024 clocks before any valid operation. Document Number: 38-06082 Rev. *K [+] Feedback FullFlex address matches enable to generate the BUSY flag. However, none of the addresses are saved into the busy address register. When a busy readback is performed, the address of the first Table 3. tCCS Timing for All Operating Modes Port A—Early Arriving Port Mode SDR Active Edge C Port B—Late Arriving Port Mode SDR Active Edge C tCCS C Rise to Opposite C Rise Setup Time for Non Corrupt Data match that happens at least two clocks cycles after the busy readback is saved into the busy address register. Unit ns tCYC(min) – 0.5 Table 4. Deterministic Access Control Logic Left Port Read Write Right Port Read Read Left Clock X > tCCS 0 < tCCS 0 Read Write > tCCS 0 < tCCS 0 Write Write 0 0 > tCCS Right Clock X 0 > tCCS 0 < tCCS 0 > tCCS 0 < tCCS > –tCCS & < tCCS > tCCS 0 BUSYL H H H H H H H H H H L H L L L H BUSYR H H H H L H L H H H H H H L H L Description No collision Read OLD data Read NEW data Read OLD data Data not guaranteed Read NEW data Data Not guaranteed Read NEW data Read OLD data Read NEW data Data Not guaranteed Read OLD data Data not guaranteed Array data corrupted Array stores right port data Array stores left port data Variable Impedance Matching Each port contains a variable impedance matching circuit to set the impedance of the IO driver to match the impedance of the on-board traces. The impedance is set for all outputs except JTAG and is done by port. To take advantage of the VIM feature, connect a calibrating resistor (RQ) that is five times the value of the intended line impedance from the ZQ[1:0][27] pin to VSS. The output impedance is then adjusted to account for drifts in supply voltage and temperature every 1024 clock cycles. If a port’s clock is suspended, the VIM circuit retains its last setting until the clock is restarted. On restart, it then resumes periodic adjustment. In the case of a significant change in device temperature or supply voltage, recalibration happens every 1024 clock cycles. A master reset initializes the VIM circuitry. Table 5 shows the VIM parameters and Table 6 describes the VIM operation modes. To disable VIM, connect the ZQ pin to VDDIO of the relative supply for the IOs before a Master Reset. Table 5. Variable Impedance Matching Parameters Parameter RQ value Output impedance Reset time Update time Min 100 20 – – Max 275 55 1024 1024 Unit   Cycles Cycles Tolerance ±2% ±15% – – Table 6. Variable Impedance Matching Operation RQ Connection Output Configuration 100 –275  to VSS Output driver impedance = RQ/5 ± 15% at Vout = VDDIO/2 ZQto VDDIO VIM disabled. Rout < 20 at Vout = VDDIO/2 Note 27. The pin ZQ[1] is applicable only for 36 Mbit devices. This pin is DNU for 18 Mbit and lower density devices. Document Number: 38-06082 Rev. *K Page 12 of 52 [+] Feedback FullFlex Address Counter and Mask Register Operations [28] Each port of the FullFlex family contains a programmable burst address counter. The burst counter contains four registers: a counter register, a mask register, a mirror register, and a busy address register. The counter register contains the address used to access the RAM array. It is changed only by the master reset (MRST), counter reset, counter load, retransmit, and counter increment operations. The mask register value affects the counter increment and counter reset operations by preventing the corresponding bits of the counter register from changing. It also affects the counter interrupt output (CNTINT). The mask register is only changed by mask reset, mask load, and MRST. The mask load operation loads the value of the address bus into the mask register. The mask register defines the counting range of the counter register. The mask register is divided into two or three consecutive regions. Zero or more 0s define the masked region and one or more 1s define the unmasked portion of the counter register. The counter register may be divided up to three regions. The region containing the least significant bits must be no more than two 0s. Bits one and zero may be 10 respectively, masking the least significant counter bit and causing the counter to increment by two instead of one. If bits one and zero are 00, the two least significant bits are masked and the counter increments by four instead of one. For example, in the case of a 256 K × 72 configuration, a mask register value of 003FC divides the mask register into three regions. With bit 0 being the least significant bit and bit 17 being the most significant bit, the two least significant bits are masked, the next eight bits are unmasked, and the remaining bits are masked. The mirror register reloads a counter register on retransmit operations (see Retransmit on page 15) and wrap functions (see Counter Interrupt on page 15 below). The last value loaded into the counter register is stored in the mirror register. The mirror register is only changed by master reset (MRST), counter reset, and counter load. Table 7 on page 14 summarizes the operations of these registers and the required input control signals. All signals except MRST are synchronized to the ports clock. Counter Load Operation [28] For both non-burst and burst read or write accesses, the external address is loaded through counter load operation as shown in Table 7 on page 14. The address counter and mirror registers are loaded with the address value presented on the address lines. This value ranges from 0 to 1FFFFF. Mask Load Operation [28] The mask register is loaded with the address value presented on the address bus. This value ranges from 0 to 1FFFFF though not all values permit correct increment operations. Permitted values are in the form of 2n–1, 2n–2, or 2n–4. The counter register is only segmented up to three regions. From the most significant bit to the least significant bit, permitted values have zero or more 0s, one or more 1s, and the least significant two bits are 11, 10, or 00. Thus 1FFFFE, 07FFFF, and 003FFC are permitted values but 02FFFF, 003FFA, and 07FFE4 are not. Counter Readback Operation The internal value of the counter register is read out on the address lines. The address is valid tCA after the selected number of latency cycles configured by FTSEL. The data bus (DQ) is tri-stated on the cycle that the address is presented on the address lines. Figure 7 on page 16 shows a block diagram of this logic. Mask Readback Operation The internal value of the mask register is read out on the address lines. The address is valid tCA after the selected number of latency cycles configured by FTSEL. The data bus (DQ) is tri-stated on the cycle that the address is presented on the address lines. Figure 7 on page 16 shows a block diagram of the operation. Counter Reset Operation All unmasked bits of the counter and mirror registers are reset to ‘0’. All masked bits remain unchanged. A mask reset followed by a counter reset resets the counter and mirror registers to 00000. Mask Reset Operation The mask register is reset to all 1s, that unmasks every bit of the burst counter. Note 28. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits. The CYD02S36V18 has 16 address bits. Document Number: 38-06082 Rev. *K Page 13 of 52 [+] Feedback FullFlex Table 7. Burst Counter and Mask Register Control Operations The burst counter and mask register control operation for any port follows. [29, 30] C X MRST L H H H CNTRST CNT/MSK CNTEN ADS RET X L L H X H L H X X X L X X X L X X X X Operation Master reset Counter reset Mask reset Description Reset address counter to all 0s, mask register to all 1s, and busy address to all 0s. Reset counter and mirror unmasked portion to all 0s. Reset mask register to all 1s. Counter load for Load burst counter and mirror with external burst/external address address value presented on address lines. load for non-burst Mask load Retransmit Counter increment Counter hold Counter readback Mask readback Busy readback Reserved Reserved Reserved Reserved Reserved Load mask register with value presented on the address lines. Load counter with value in the mirror register. Internally increment address counter value. Constantly hold the address value for multiple clock cycles. Read out counter internal value on address lines. Read out mask register value on address lines. H H H H H H H H H H H H H H H H H H H H H H H H L H H H H L L L L L H H L L L H H H H L H H H H L H H H L L H H L H L H X L H H H H L X L H L L address Read out first busy address after last busy address readback. Notes 29. “X” = Don’t Care, “H” = HIGH, “L” = LOW. 30. Counter operation and mask register operation is independent of chip enables. Document Number: 38-06082 Rev. *K Page 14 of 52 [+] Feedback FullFlex Increment Operation[31] After the address counter is initially loaded with an external address, the counter can internally increment the address value and address the entire memory array. Only the unmasked bits of the counter register are incremented. For a counter bit to change, the corresponding bit in the mask register must be 1. If the two least significant bits of the mask register are 11, the burst counter increments by one. If the two least significant bits are 10, the burst counter increments by two, and if they are 00, the burst counter increments by four. If all unmasked counter bits are incremented to 1 and WRP is deasserted, the next increment l wraps the counter back to the initially loaded value. The cycle before the increment that results in all unmasked counter bits to become 1s, a counter interrupt flag (CNTINT) is asserted if the counter is incremented again. This increment causes the counter to reach its maximum value and the next increment returns the counter register to its initial value that was stored in the mirror register if WRP is deasserted. If WRP is asserted, the unmasked portion of the counter is filled with 0 instead. The example shown in Figure 8 on page 17 shows an example of the CYDD36S18V18 device with the mask register loaded with a mask value of 00007F unmasking the seven least significant bits. Setting the mask register to this value enables the counter to access the entire memory space. The address counter is then loaded with an initial value of 000005 assuming WRP is deasserted. The masked bits, the seventh address through the twenty-first address, do not increment in an increment operation. The counter address starts at address 000005 and increments its internal address value until it reaches the mask register value of 00007F. The counter wraps around the memory block to location 000005 at the next count. CNTINT is issued when the counter reaches the maximum –1 count. mirror register stores the address counter value last loaded. While RET is asserted low, the counter continues to wrap back to the value in the mirror register independent of the state of WRP. Counter Interrupt The counter interrupt (CNTINT) is asserted LOW one clock cycle before an increment operation that results in the unmasked portion of the counter register being all 1s. It is deasserted by counter reset, counter load, counter increment, mask reset, mask load, and MRST. Counting by Two When the two least significant bits of the mask register are 10, the counter increments by two. Counting by Four When the two least significant bits of the mask register are 00, the counter increments by four. Mailbox Interrupts Use the upper two memory locations for message passing and permit communications between ports. Table 8 on page 17 shows the interrupt operation for both ports. The highest memory location is the mailbox for the right port and the maximum address – 1 is the mailbox for the left port. When one port writes to the other port’s mailbox, the INT flag of the port that the mailbox belongs to is asserted LOW. The INT flag remains asserted until the mailbox location is read by the other port. When a port reads its mailbox, the INT flag is deasserted high after one cycle of latency with respect to the input clock of the port to which the mailbox belongs and is independent of OE. As shown in Table 8 on page 17, to set the INTR flag, a write operation by the left port to address 1FFFFF asserts INTR LOW. A valid read of the 1FFFFF location by the right port resets INTR HIGH after one cycle of latency with respect to the right port’s clock. You must activate at least one byte enable to set or reset the mailbox interrupt. Hold Operation The value of all three registers is constantly maintained unchanged for an unlimited number of clock cycles. This operation is useful in applications where wait states are needed or when address is available a few cycles ahead of data in a shared bus interface. Retransmit Retransmit enables repeated access to the same block of memory without the need to reload the initial address. An internal Note 31. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits. The CYD02S36V18 has 16 address bits. Document Number: 38-06082 Rev. *K Page 15 of 52 [+] Feedback FullFlex Figure 7. Counter, Mask, and Mirror Logic Block Diagram Figure 7 shows the counter, mask, and mirror logic block diagram. [32] CNT/MSK CNTEN A CNTRST RET MRST A Mask Register Counter/ Address Register C RAM Array Decode Logic Address Decode From Address Lines 20 Load/Increment Mirror 1 1 0 Counter To Readback and Address Decode 20 From Mask Register 20 Increment Logic Wrap 0 From Mask From Counter 20 20 20 +1 +2 +4 Bit 0 and 1 1 0 1 0 Wrap Detect Wrap 20 To Counter Note 32. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits. The CYD02S36V18 has 16 address bits. Document Number: 38-06082 Rev. *K Page 16 of 52 [+] Feedback FullFlex Figure 8. Programmable Counter-Mask Register Operation with WRP deasserted Figure 8 shows the programmable counter-mask operation with WRP deasserted. [36, 38] CNTINT Example: Load Counter-Mask H Register = 00007F 0 0 0s 0 11 1 1 11 1 Mask Register LSB 220 219 6 5 4 32 1 0 27 2 2 2 2 2 2 2 Masked Address Load Address Counter = 000005 H XX 220 219 Max Address Value Max + 1 Address Value L XX 220 219 H XX 220 219 Xs Xs Xs Unmasked Address 00 0 0 10 1 X 6 5 4 32 1 0 27 2 2 2 2 2 2 2 X 111 1 1 1 1 Address Counter LSB 6 5 4 32 1 0 27 2 2 2 2 2 2 2 X 0 00 0 10 1 6 5 4 32 1 0 27 2 2 2 2 2 2 2 Table 8. Interrupt Operation Example Table 8 shows the interrupt operation example. [33, 34, 35, 37, 38] Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag Left Port R/WL L X X H CEL L X X L A0L–20L Max Address X X Max Address–1 INTL X X L H R/WR X H L X CER X L L X Right Port A0R–20R X Max Address Max Address–1 X INTR L H X X Notes 33. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single read operation, CE only needs to be asserted once at the rising edge of the C and is deasserted after that. Data is out after the following C edge and is tri-stated after the next C edge. 34. OE is “Don’t Care” for mailbox operation. 35. At least one of BE0, BE1, BE2, BE3, BE4, BE5, BE6, or BE7 must be LOW. 36. The “X” in this diagram represents the counter’s upper bits. 37. “X” = Don’t Care, “H” = HIGH, “L” = LOW. 38. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits. The CYD02S36V18 has 16 address bits. Document Number: 38-06082 Rev. *K Page 17 of 52 [+] Feedback FullFlex Master Reset The FullFlex family of Dual Ports undergoes a complete reset when MRST is asserted. MRST must be driven by VDDIOL referenced levels. The MRST is asserted asynchronously to the clocks and must remain asserted for at least tRS. When asserted MRST deasserts READY, initializes the internal burst counters, internal mirror registers, and internal busy addresses to zero. It also initializes the internal mask register to all 1s. All mailbox interrupts (INT), busy address outputs (BUSY), and burst counter interrupts (CNTINT) are deasserted upon master reset. Additionally, do not release MRST until all power supplies including VREF are fully ramped and all port clocks and mode select inputs (LOWSPD, ZQ, CQEN, FTSEL, and PORTSTD) are valid and stable. This begins calibration of the DLL and VIM circuits. READY is asserted within 1024 clock cycles. READY is a wired OR capable output with a strong pull up and weak pull down. Up to four outputs may be connected together. For faster pull down of the signal, connect a 250 Ohm resistor to VSS. If the DLL and VIM circuits are disabled for a port, the port is operational within five clock cycles. However, the READY is asserted within 160 clock cycles. one output connection required by the test logic defined by the standard. Table 9. JTAG IDCODE Register Definitions Part Number CYD36S72V18 CYD36S36V18 CYD36S18V18 CYD18S72V18 CYD18S36V18 CYD18S18V18 CYD09S72V18 CYD09S36V18 CYD09S18V18 CYD02S36V18 Configuration 512 K × 72 1024 K × 36 2048 K × 18 256 K × 72 512 K × 36 1024 K × 18 128 K × 72 256 K × 36 512 K × 18 64 K × 36 Value 0C026069h (×2) 0C023069h 0C024069h 0C025069h 0C026069h 0C027069h 0C028069h 0C029069h 0C02A069h 0C030069h IEEE 1149.1 Serial Boundary Scan (JTAG) The FullFlex families incorporate an IEEE 1149.1 serial boundary scan test access port (TAP). The TAP operates using JEDEC-standard 3.3 V or 2.5 V IO logic levels depending on the VTTL power supply. It is composed of four input connections and Table 10. Scan Registers Sizes Register Name Instruction Bypass Identification Boundary Scan Bit Size 4 1 32 n[39] Table 11. Instruction Identification Codes Instruction EXTEST BYPASS IDCODE HIGHZ CLAMP SAMPLE/PRELOAD RESERVED Code 0000 1111 1011 0111 0100 1000 All other codes Description Captures the input and output ring contents. Places the BSR between the TDI and TDO. Places the BYR between TDI and TDO. Loads the IDR with the vendor ID code and places the register between TDI and TDO. Places BYR between TDI and TDO. Forces all FullFlex72 and FullFlex36 output drivers to a High Z state. Controls boundary to 1 or 0. Places BYR between TDI and TDO. Captures the input and output ring contents. Places BSR between TDI and TDO. Other combinations are reserved. Do not use other than the mentioned combinations. Note 39. Details of the boundary scan length is found in the BSDL file for the device. Document Number: 38-06082 Rev. *K Page 18 of 52 [+] Feedback FullFlex Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage temperature............................... –65 °C to + 150 °C Ambient temperature with power applied .......................................... –55 °C to + 125 °C Supply voltage to ground potential ..............–0.5 V to + 4.1 V DC voltage applied to outputs in high Z State ...................... –0.5 V to VDDIO + 0.5 V DC input voltage ............................... –0.5 V to VDDIO + 0.5 V Output current into outputs (LOW) ............................. 20 mA Static discharge voltage........................................... > 2200 V (JEDEC JESD8-6, JESD8-B) Latch-up current ..................................................... > 200 mA LVTTL VDDIO 2.5 V LVCMOS VDDIO HSTL VDDIO 1.8 V LVCMOS VDDIO 3.3 V VTTL 2.5 V VTTL HSTL VREF Operating Range Range Commercial Industrial Ambient Temperature 0 °C to +70 °C –40 °C to +85 °C VCORE 1.8 V  100 mV 1.5 V 80 mV 1.8 V  100 mV 1.5 V 80 mV Power Supply Requirements Min 3.0 V 2.3 V 1.4 V 1.7 V 3.0 V 2.3 V 0.68 V Typ 3.3 V 2.5 V 1.5 V 1.8 V 3.3 V 2.5 V 0.75 V Max 3.6 V 2.7 V 1.9 V 1.9 V 3.6 V 2.7 V 0.95 V Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH voltage (VDDIO = Min, IOH = –8 mA) (VDDIO = Min, IOH = –4 mA) (VDDIO = Min, IOH = –4 mA) (VDDIO = Min, IOH = –6 mA) (VDDIO = Min, IOH = –4 mA) VOL Output HIGH voltage (VDDIO = Min, IOL = 8 mA) (VDDIO = Min, IOL = 4 mA) (VDDIO = Min, IOL = 4 mA) (VDDIO = Min, IOL = 6 mA) (VDDIO = Min, IOL = 4 mA) VIH Input HIGH voltage Configuration LVTTL HSTL (DC)[41] HSTL (AC)[41] 2.5 V LVCMOS 1.8 V LVCMOS LVTTL HSTL(DC)[41] HSTL (AC) [41] All Speed Bins Min 2.4[40] VDDIO – 0.4[40] VDDIO – 0.5[40] 1.7[40] VDDIO – 0.45[40] – – – – – 2 VREF + 0.1 1.7 0.65 × VDDIO –0.3 –0.3 – – Typ – – – – – – – – – – – – – – – – – – 0.8 VREF – 0.1 0.7 0.35 × VDDIO Max – – – – – 0.4 [40] Unit V V V V V V V V V V V V V V V V V V 0.4[40] 0.5[40] 0.7[40] 0.45[40] VDDIO + 0.3 VDDIO + 0.3 2.5 V LVCMOS 1.8 V LVCMOS LVTTL HSTL(DC)[41] 2.5 V LVCMOS 1.8 V LVCMOS VIL Input LOW voltage LVTTL HSTL(DC)[41] 2.5 V LVCMOS 1.8 V LVCMOS Notes 40. These parameters are met with VIM disabled. 41. The DC specifications are measured under steady state conditions. The AC specifications are measured while switching at speed. AC VIH/VIL in HSTL mode are measured with 1 V/ns input edge rates. Document Number: 38-06082 Rev. *K Page 19 of 52 [+] Feedback FullFlex Electrical Characteristics (continued) Over the Operating Range Parameter READY VOH Description Output HIGH voltage (VDDIO = Min, IOH = –24 mA) (VDDIO = Min, IOH = –12 mA) (VDDIO = Min, IOH = –12 mA) (VDDIO = Min, IOH = –15 mA) (VDDIO = Min, IOH = –12 mA) READY VOL Output HIGH voltage (VDDIO = Min, IO = 0.12 mA) (VDDIO = Min, IOL = 0.12 mA) (VDDIO = Min, IOL = 0.12 mA) (VDDIO = Min, IOL = 0.15 mA) (VDDIO = Min, IOL = 0.08 mA) IOZ IIX1 IIX2 IIX3 Output leakage current Input leakage current except TDI, TMS, MRST, PORTSTD Input leakage current TDI, TMS, MRST Input leakage current PORTSTD Configuration LVTTL HSTL(DC)[43] HSTL (AC) [43] All Speed Bins Min 2.7[42] VDDIO – 0.4[42] VDDIO – 0.5[42] 2.0 [42] Unit Max – – – – – 0.4[42] 0.4[42] 0.5[42] 0.7[42] 0.45[42] 10 10 10 300 V V V V V V V V V V A A A A Typ – – – – – – – – – – – – – – 2.5 V LVCMOS 1.8 V LVCMOS LVTTL HSTL(DC)[43] HSTL (AC)[43] 2.5 V LVCMOS 1.8 V LVCMOS VDDIO – 0.45[42] – – – – – –10 –10 –300 –10 Notes 42. These parameters are met with VIM disabled. 43. The DC specifications are measured under steady state conditions. The AC specifications are measured while switching at speed. AC VIH/VIL in HSTL mode are measured with 1 V/ns input edge rates. Document Number: 38-06082 Rev. *K Page 20 of 52 [+] Feedback FullFlex Electrical Characteristics Over the Operating Range Parameter ICC Description Operating current (VCORE = Max, IOUT = 0 mA) outputs disabled Configuration 512 K × 72 Commercial Industrial 1024 K × 36 Commercial Industrial 2048 K × 18 Commercial Industrial 256 K × 72 512 K × 36 Commercial Industrial Commercial Industrial 1024 K × 18 Commercial Industrial 128 K × 72 256 K × 36 512 K × 18 64 K × 36 Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial -200 Typ 1440 – 1180 – 1130 – 800 820 640 670 610 640 640 660 540 550 550 570 – – Max 1800 – 1500 – 1430 – 980 1030 800 860 770 830 790 830 640 670 660 690 – – Typ 1280 1330 1050 1110 1000 1060 700 730 570 590 540 570 560 580 470 490 480 500 – – -167 Max 1620 1730 1350 1470 1290 1410 880 930 720 780 690 750 700 740 570 600 580 610 – – Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Document Number: 38-06082 Rev. *K Page 21 of 52 [+] Feedback FullFlex Electrical Characteristics (continued) Over the Operating Range Parameter ISB1 Description Standby current (both ports TTL Level) CEL and CER  VIH, f = fMAX Configuration 512 K × 72 Commercial Industrial 1024 K × 36 Commercial Industrial 2048 K × 18 Commercial Industrial 256 K × 72 512 K × 36 Commercial Industrial Commercial Industrial 1024 K × 18 Commercial Industrial 128 K × 72 256 K × 36 512 K × 18 64 K × 36 Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial -200 Typ 1000 – 910 – 890 – 500 530 460 480 450 470 400 420 380 390 390 410 – – Max 1250 – 1140 – 1110 – 630 680 570 630 560 610 490 540 440 470 460 480 – – Typ 920 970 820 880 810 860 460 490 410 440 410 430 360 380 340 360 350 370 – – -167 Max 1160 1260 1050 1160 1030 1140 580 630 530 580 520 570 450 490 400 430 410 440 – – Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Document Number: 38-06082 Rev. *K Page 22 of 52 [+] Feedback FullFlex Electrical Characteristics (continued) Over the Operating Range Parameter ISB2 Description Standby current (one port TTL or CMOS level) CEL | CER  VIH, f = fMAX Configuration 512 K × 72 Commercial Industrial 1024 K × 36 Commercial Industrial 2048 K × 18 Commercial Industrial 256 K × 72 512 K × 36 Commercial Industrial Commercial Industrial 1024 K × 18 Commercial Industrial 128 K × 72 256 K × 36 512 K × 18 64 K × 36 Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial -200 Typ 1300 – 1090 – 1040 – 650 680 550 570 520 550 520 550 460 480 460 480 – – Max 1570 – 1330 – 1270 – 790 840 670 730 640 690 630 670 530 560 530 560 – – Typ 1160 1210 980 1030 930 980 580 610 490 520 470 490 460 480 400 430 410 430 – – -167 Max 1410 1520 1210 1330 1160 1270 710 760 610 670 580 640 560 610 470 500 480 510 – – Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Document Number: 38-06082 Rev. *K Page 23 of 52 [+] Feedback FullFlex Electrical Characteristics Over the Operating Range Parameter ISB3 Description Standby current (both ports CMOS level) CEL and CER  VCORE – 0.2 V, f = 0 Configuration 512 K × 72 1024 K × 36 2048 K × 18 256 K × 72 512 K × 36 1024 K × 18 128 K × 72 256 K × 36 512 K × 18 Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Table 12. Capacitance Signals CYD18S72V18 CYD09S72V18 CYD18S36V18 CYD09S36V18 CYD02S36V18 OE BE, DQ All other signals 12 pF 10 pF 10 pF CYD18S18V18 CYD09S18V18 Packages CYD36S72V18 CYD36S36V18 CYD36S18V18 All Speed Bins Typ 410 460 410 460 410 460 210 230 210 230 210 230 150 170 150 170 150 170 Max 590 700 590 700 590 700 300 350 300 350 300 350 200 220 200 220 200 220 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 12 pF 18 pF 10 pF 20 pF 16 pF 16 pF 20 pF 30 pF 16 pF Document Number: 38-06082 Rev. *K Page 24 of 52 [+] Feedback FullFlex AC Test Load and Waveforms Figure 9. Output Test Load for LVTTL/CMOS VTH = 1.5V for LVTTL VTH = 50% VDDIO for 2.5V CMOS VTH = 50% VDDIO for 1.8V CMOS VREF = NC 50 Ohm Test Point READY ZQ RQ=250 Ohm C = 10pF 50 Ohm VTH VREF Output R=250 Ohm Device under test Figure 10. Output Test Load for HSTL VTH = 50% VDDIO VREF = 0.75V VREF Output R=250 Ohm READY ZQ Device under test RQ=250 Ohm Test Point VTH C= 10pF for SDR 50 Ohm 50 Ohm Figure 11. HSTL Input Waveform Document Number: 38-06082 Rev. *K Page 25 of 52 [+] Feedback FullFlex Switching Characteristics Over the Operating Range Table 13. SDR Mode, Signals Affected by DLL Description Parameter Min tCD2[49] tCCQ[49] tCKHZ2 [44, 49] DLL ON (LOWSPD=1)[46] -200 Max 3.30[45, 48] 3.30 [48] 3.30 [45, 48] DLL OFF (LOWSPD=0)[46] Max 4.00[45, 48] 4.00[48] 4.00 [45, 48] -167 Min – 1.00 1.00 1.00 Min – 1.00 1.00 1.00 Max 6.00[45, 48] 6.00[48] 6.00 [45, 48] Unit ns ns ns ns C rise to DQ valid for pipelined mode C rise to CQ rise C rise to DQ output high Z in pipelined mode – 1.00 1.00 1.00 tCKLZ2[44, 49] C rise to DQ output low Z in pipelined mode Table 14. SDR Mode Parameter fMAX (PIPELINED) fMAX (FLOW THROUGH) tCYC (PIPELINED) Description – – – -200 Min 100 – 5.00[48] 13.00[48] 45 1.50[45, 48] 1.75[45, 48] 0.5 1.50 [45, 47, 48] -167 Max 200 77 10.00 – 55 – – – – – – 4.40[45, 48] – 1.70 Min 100 – 6.00[48] 15.00[48] 45 1.70[45, 48] 1.95[45, 48] 0.5 [45, 47, 48] Max 167 66.7 10.00 – 55 – Unit MHz MHz ns ns % ns ns Maximum operating frequency for pipelined mode Maximum operating frequency for flow through mode C clock cycle time for pipelined mode tCYC (FLOW X C clock cycle time for flow through mode THROUGH) tCKD tSD C clock duty time Data input setup time to C HSTL rise 1.8 V LVCMOS 2.5 V LVCMOS 3.3 V LVTTL tHD[47] tSAC Data input hold time after C rise Address and control input HSTL setup time to C rise 1.8 V L VCMOS 2.5 V LVCMOS 3.3 V LVTTL tHAC[47] tOE tOLZ[44] Address and control input hold time after C rise Output enable to data valid OE to low Z – – – – 5.00[45, 48] – ns ns ns ns ns ns 1.75[45, 47, 48] 0.50 – 1.00 1.95[45, 47, 48] 0.60 – 1.00 Notes 44. Parameters specified with the load capacitance in Figure 9 on page 25 and Figure 10 on page 25. 45. For the x18 devices, add 200 ps to this parameter in Table 14. 46. Test conditions assume a signal transition time of 2 V/ns. 47. Add 300 ps to this timing for 36M devices. 48. Add 15% to this parameter if a VCORE of 1.5 V is used. 49. This parameter assumes input clock cycle to cycle jitter of ± 0ps. Document Number: 38-06082 Rev. *K Page 26 of 52 [+] Feedback FullFlex Table 14. SDR Mode (continued) Parameter tOHZ[50] tCD1 tCA1 tCA2 tDC tJIT tCQHQV[53] [53] Description OE to high Z C rise to DQ valid for flow through mode (LowSPD = 0) C rise to address readback valid for flow through mode C rise to address readback valid for pipelined mode DQ output hold after C rise Clock input cycle to cycle jitter Echo clock (CQ) high to output valid HSTL 1.8 V LVCMOS 2.5 V LVCMOS 3.3 V LVTTL -200 Min 1.00 – – – 1.00 – – – –0.70 –0.85 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 0.50 0.50 1.00 Max 4.40[51, 52] 9.00[51, 52] 9.00[52] 5.00 – +/- 200 0.70[51] 0.80[51] – – 9.00[51, 52] – – 9.00[52] 5.00[52] – 3.30[52] 3.30[52] 7.00[52] 7.00[52] 3.30[52] [52] -167 Min 1.00 – – – 1.00 – – – –0.80 –0.95 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 0.50 0.50 1.00 Max 5.00[51, 52] 11.00[51, 52] 11.00[52] 6.00[52] – +/- 200 0.80[51] 0.90[51] – – 11.00[51, 52] – – 11.00[52] 6.00[52] – 4.00[52] 4.00[52] 8.00[52] 8.00[52] 4.00[52] Unit ns ns ns ns ns ps ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCQHQX[53] Echo clock (CQ) high to output hold HSTL 1.8 V LVCMOS 2.5 V LVCMOS 3.3 V LVTTL tCKHZ1[50] tCKLZ1[50] tAC tCKHZA1[50] tCKHZA2[50] tCKLZA[50] tSCINT tRCINT tSINT tRINT tBSY C rise to DQ output high Z in flow through mode C rise to DQ output low Z in flow through mode Address output hold after C rise C rise to address output high Z for flow through mode C rise to address output high Z for pipelined mode C rise to address output low Z C rise to CNTINT low C rise to CNTINT high C rise to INT low C rise to INT high C rise to BUSY valid Notes 50. Parameters specified with the load capacitance in Figure 9 on page 25 and Figure 10 on page 25. 51. For the x18 devices, add 200 ps to this parameter in Table 14. 52. Add 15% to this parameter if a VCORE of 1.5 V is used. 53. This parameter assumes input clock cycle to cycle jitter of ± 0ps. Document Number: 38-06082 Rev. *K Page 27 of 52 [+] Feedback FullFlex Table 15. Master Reset Timing Parameter tPUP tRS tRSR tRSF tRDY[54] tCORDY[55] Power-up time Master reset pulse width Master reset recovery time Master reset to outputs inactive/Hi Z Master reset release to port ready C rise to port ready Description -200 Min 1 5 5 – – – Max – – – 15 1024 9.5[56] Min 1 5 5 – – – -167 Max – – – 18 1024 11[56] Unit ms cycles cycles ns cycles ns Table 16. JTAG Timing Parameter fJTAG tTCYC tTH tTL tTMSS tTMSH tTDIS tTDIH tTDOV tTDOX tJXZ tJZX tJZX . Description JTAG TAP controller frequency TCK cycle time TCK high time TCK low time TMS setup to TCK rise TMS hold to TCK rise TDI setup to TCK rise TDI hold to TCK rise TCK low to TDO valid TCK low to TDO invalid TCK low to TDO high Z TCK low to TDO active TCK low to TDO active -200 Min – 50 20 20 10 10 10 10 – 0 – – – Max 20 – – – – – – – 10 – 15 15 15 Min – 50 20 20 10 10 10 10 – 0 – – – -167 Max 20 – – – – – – – 10 – 15 15 15 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns Notes 54. READY is a wired OR capable output with a weak pull-down. For a decreased falling delay, connect a 250- resistor to VSS. 55. Add this propagation delay after tRDY for all Master Reset Operations. 56. Add 15% to this parameter if a VCORE of 1.5 V is used. Document Number: 38-06082 Rev. *K Page 28 of 52 [+] Feedback FullFlex Switching Waveforms Figure 12. JTAG Timing tTH Test Clock TCK Test Mode Select TMS tTDIS Test Data-In TDI Test Data-Out TDO tTL tTMSS tTCYC tTMSH tTDIH tTDOX tTDOV Figure 13. Master Reset [57] VCORE tPUP MRST C tRS ~ ~ ~ tRDY tCORDY READY All Address & Data All Other Inputs tRSF ~ ~ tRSR ~ Note 57. READY is a wired OR capable output with a weak pull-down. For a decreased falling delay, connect a 250- resistor to VSS. Document Number: 38-06082 Rev. *K Page 29 of 52 [+] Feedback FullFlex Switching Waveforms (continued) Figure 14. READ Cycle for Pipelined Mode tCYC C CE OE tSAC R/W tHAC A An An+1 An+2 An+3 An+4 An+5 An+6 2 Pipelined stages DQ DQx-1 DQx tDC DQn DQn+1 DQn+2 DQn+3 DQn+4 tCD2 Figure 15. WRITE Cycle for Pipelined and Flow through Modes tCYC C CE R/W A An An+1 An+2 An+3 An+4 An+5 An+6 2 Pipelined stages DQ DQn DQn+1 DQn+2 DQn+3 DQn+4 DQn+5 DQn+6 tSD tHD Document Number: 38-06082 Rev. *K Page 30 of 52 [+] Feedback FullFlex Switching Waveforms (continued) Figure 16. READ with Address Counter Advance for Pipelined Mode tCYC C A An Internal Address An An+1 An+2 An+3 ADS CNTEN DQ DQx-1 DQx DQn DQn+1 DQn+2 DQn+3 Figure 17. READ with Address Counter Advance for Flow through Mode tC Y C C tS A C tH A C A An ADS t S AC t H AC C NT E N tCD1 DQ DQx tD C DQ n DQn + 1 DQn + 2 DQ n + 3 DQn + 4 R EA D E XT E R N A L A D D R E SS R E AD W IT H C O U N TE R C O U N T ER H O L D R EA D W IT H C O U N T E R Document Number: 38-06082 Rev. *K Page 31 of 52 [+] Feedback FullFlex Switching Waveforms (continued) Figure 18. Port-to-Port WRITE–READ for Pipelined Mode Left Port CL AL tCYC An R/WL DQL DQn tCCS tCYC An Right Port CR AR R/WR tSAC tHAC DQR DQn tCD2 tCYC tDC Figure 19. Chip Enable READ for Pipelined Mode C CE0 CE1 R/W tSAC tHAC A An An+1 An+2 An+3 An+4 An+5 An+6 DQ tCD2 DQn tDC tCKLZ2 DQn+3 Document Number: 38-06082 Rev. *K Page 32 of 52 [+] Feedback FullFlex Switching Waveforms (continued) Figure 20. OE Controlled WRITE for Pipelined Mode tCYC C A Ax+1 Ax+2 Ax+3 An An+1 An+2 An+3 R/W OE tOHZ DQx+1 DQ DQx-1 DQx DQn DQn+1 DQn+2 DQn+3 Figure 21. OE Controlled WRITE for Flow through Mode tCYC C A Ax+1 Ax+2 Ax+3 An An+1 An+2 An+3 R/W OE tOHZ DQx+2 DQ DQx DQx+1 DQn DQn+1 DQn+2 DQn+3 Document Number: 38-06082 Rev. *K Page 33 of 52 [+] Feedback FullFlex Switching Waveforms (continued) Figure 22. Byte-Enable READ for Pipelined Mode tCYC C A R/W BE7 BE6 BE5 BE4 BE3 BE2 BE1 BE0 tCKLZ2 t DQn+1(63:71) CKHZ2 DQn+1(54:62) DQn+2(45:53) DQn+2(36:44) DQn+1(27:35) An An+1 An+2 An+3 DQ63:71 DQ54:62 DQ45:53 DQ36:44 DQ27:35 DQ18:26 DQ9:17 DQ0:8 DQn+2(18:26) DQn+3(9:17) DQn+3(0:8) Document Number: 38-06082 Rev. *K Page 34 of 52 [+] Feedback FullFlex Switching Waveforms (continued) Figure 23. Port-to-Port WRITE-to-READ for Flow through Mode CL R /W L tS A C AL M A TC H tS D DQL V A LID tC C S CR tCD1 R /W R tS A C AR M A TC H tH A C NO MATCH tH A C NO MATCH tH D tC D 1 DQR tD C VA LID tDC V A L ID Document Number: 38-06082 Rev. *K Page 35 of 52 [+] Feedback FullFlex Switching Waveforms (continued) Figure 24. Busy Address Readback for Pipelined and Flow through Modes, CNT/MSK = RET = LOW[58] tCYC C Internal Amatch+2 Address BUSY Amatch+3 Amatch+4 ~ ~ ~ ~ ~ ~ tCA2 CNTEN ADS External Address Pipelined External Address Flow through Amatch tAC ~ tCA1 Figure 25. Read Cycle for Flow through Mode t CY C Amatch tAC C CE 0 t SA C CE 1 t H AC B En R /W t S AC A An tC D 1 DQ t C KLZ 1 OE tO E t H AC An + 1 tD C DQn DQn + 1 tO H Z t O LZ An + 2 An + 3 t C KH Z 1 DQn + 2 tD C Note 58. Amatch is the matching address that is reported on the address bus of the losing port. The counter operation selected for reporting the address is “Busy Address Readback.” Document Number: 38-06082 Rev. *K Page 36 of 52 [+] Feedback FullFlex Switching Waveforms (continued) Figure 26. READ-to-WRITE for Pipelined Mode (OE = VIL)[59, 60, 61] tCYC C Ax tCL tCH A An tSAC tHAC An+1 An+2 tSAC tHAC R/W tCKLZ2 DQx-2 tCD2 DQ DQx-1 tDC DQx tCKHZ2 DQn DQn+1 DQn+2 tSD tHD Figure 27. READ-to-WRITE for Pipelined Mode (OE Controlled)[62, 63] tCYC C A Ax Ax+1 tSAC tHAC Ax+2 An An+1 An+2 An+3 R/W OE DQx tOHZ tSD tHD DQ DQx-2 DQx-1 DQn DQn+1 DQn+2 DQn+3 Notes 59. When OE = VIL, the last read operation is enabled to complete before the DQ bus is tri-stated and the user is enabled to drive write data. 60. Two dummy writes are issued to accomplish bus turnaround. The third instruction is the first valid write. 61. Chip enable or all byte enables are held inactive during the two dummy writes to avoid data corruption. 62. OE is deasserted and tOHZ enabled to elapse before the first write operation is issued. 63. Any write scheduled to complete after OE is deasserted is pre-empted. Document Number: 38-06082 Rev. *K Page 37 of 52 [+] Feedback FullFlex Switching Waveforms (continued) Figure 28. Read-to-Write-to-Read for Flow through Mode (OE = LOW) t CYC C t SAC t HAC CE0 CE 1 B En t SAC t HAC R/W A An An + 1 An + 2 An + 2 t SD tH D An + 3 An + 4 DQ IN t C D1 D Q O UT DQ n tD C READ NO P DQn + 2 t CD1 DQn + 1 t CKHZ1 t CKLZ1 tD C W RITE R EAD t C D1 t CD1 DQ n + 3 Document Number: 38-06082 Rev. *K Page 38 of 52 [+] Feedback FullFlex Switching Waveforms (continued) Figure 29. Read-to-Write-to-Read for Flow through Mode (OE Controlled) t C YC C t SA C t H AC CE0 CE1 BEn t SA C t H A C R /W A An An + 1 tS D An + 2 tH D An + 3 An + 4 An + 5 D Q IN tC D 1 D Q OUT DQn tO H Z OE tD C DQn + 2 DQn + 3 tO E tC D 1 tC D 1 DQn + 4 t C KLZ 1 tD C READ W R IT E R EA D Document Number: 38-06082 Rev. *K Page 39 of 52 [+] Feedback FullFlex Switching Waveforms (continued) Figure 30. BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow through Modes, Clock Timing Violates tCCS. (Flag Both Ports) Port A C A R/W BUSY tBSY < tCCS tBSY Port B C A R/W BUSY tBSY tBSY Figure 31. BUSY Timing, WRITE-WRITE Collision for Pipelined and Flow through Modes, Clock Timing Meets tCCS. (Flag Losing Port) Losing Port C A R/W tccs BUSY tBSY tBSY Winning Port C A R/W BUSY Document Number: 38-06082 Rev. *K Page 40 of 52 Match [+] Feedback FullFlex Switching Waveforms (continued) Figure 32. Read with Echo Clock for Pipelined Mode (CQEN = HIGH) C tSAC R/W tHAC A An An+1 An+2 An+3 An+4 An+5 An+6 CQ0 CQ0 CQ1 tCCQ CQ1 tCQHQV DQ DQx-1 DQx DQn DQn+1 tCQHQX DQn+2 DQn+3 DQn+4 Document Number: 38-06082 Rev. *K Page 41 of 52 [+] Feedback FullFlex Switching Waveforms (continued) Figure 33. Mailbox Interrupt Output tCYC CL AMAX AL R/WL DQL INTR tSINT tRINT CR AR AMAX R/WR DQR DQMAX Document Number: 38-06082 Rev. *K Page 42 of 52 [+] Feedback FullFlex Ordering Information 512 K × 72 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S72V18 Dual Port SRAM Speed (MHz) 200 167 Ordering Code CYD36S72V18-200BGXC CYD36S72V18-167BGXI Package Diagram Package Type Operating Range Industrial 001-07825 484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free) Commercial 001-07825 484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free) 256 K × 72 (18-Mbit) 1.8 V/1.5 V Synchronous CYD18S72V18 Dual Port SRAM Speed (MHz) 200 200 167 167 167 Ordering Code CYD18S72V18-200BGXI CYD18S72V18-200BGI CYD18S72V18-167BGXC CYD18S72V18-167BGC CYD18S72V18-167BGI Package Diagram Package Type Operating Range Industrial Industrial Commercial Industrial 51-85218 484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch (Pb-free) 51-85218 484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch 51-85218 484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch 51-85218 484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch 51-85218 484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch (Pb-free) Commercial 128 K × 72 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S72V18 Dual Port SRAM Speed (MHz) 200 167 Ordering Code CYD09S72V18-200BGXI CYD09S72V18-167BBXC Package Diagram Package Type Operating Range Industrial 51-85218 484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch (Pb-free) 51-85218 484-ball Ball Grid Array 23 mm × 23 mm with 1.0 mm pitch (Pb-free) Commercial 1024 K × 36 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S36V18 Dual Port SRAM Speed (MHz) 200 167 167 Ordering Code CYD36S36V18-200BGXC CYD36S36V18-167BGXC CYD36S36V18-167BGXI Package Diagram Package Type Operating Range 001-07825 484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free) Commercial 001-07825 484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free) Commercial 001-07825 484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free) Industrial 512 K × 36 (18-Mbit) 1.8 V/1.5 V Synchronous CYD18S36V18 Dual Port SRAM Speed (MHz) 200 167 Ordering Code CYD18S36V18-200BBAXI CYD18S36V18-167BBAI Package Diagram Package Type Operating Range Industrial Industrial 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch Document Number: 38-06082 Rev. *K Page 43 of 52 [+] Feedback FullFlex Ordering Information (continued) 256 K × 36 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S36V18 Dual Port SRAM Speed (MHz) 200 200 167 Ordering Code CYD09S36V18-200BBXC CYD09S36V18-200BBXI CYD09S36V18-167BBXC Package Diagram Package Type Operating Range Industrial 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) Commercial 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) Commercial 64 K × 36 (2-Mbit) 1.8 V or 1.5 V Synchronous CYD02S36V18 Dual Port SRAM Speed (MHz) 200 Ordering Code CYD02S36V18-200BBC Package Diagram Package Type Operating Range Commercial 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch Document Number: 38-06082 Rev. *K Page 44 of 52 [+] Feedback FullFlex Ordering Information (continued) 2048 K × 18 (36-Mbit) 1.8 V/1.5 V Synchronous CYD36S18V18 Dual Port SRAM Speed (MHz) 200 167 167 Ordering Code CYD36S18V18-200BGXC CYD36S18V18-167BGXC CYD36S18V18-167BGXI Package Diagram Package Type Operating Range 001-07825 484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free) Commercial 001-07825 484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free) Commercial 001-07825 484-ball Ball Grid Array 27 mm × 27 mm with 1.0 mm pitch (Pb-free) Industrial 1024 K × 18 (18-Mbit) 1.8 V/1.5 V Synchronous CYD18S18V18 Dual Port SRAM Speed MHz) 200 200 167 Ordering Code CYD18S18V18-200BBAXI CYD18S18V18-200BBAXC CYD18S18V18-167BBAXI Package Diagram Package Type Operating Range Industrial Industrial 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) Commercial 512 K × 18 (9-Mbit) 1.8 V/1.5 V Synchronous CYD09S18V18 Dual Port SRAM Speed (MHz) 200 200 167 Ordering Code CYD09S18V18-200BBXC CYD09S18V18-200BBXI CYD09S18V18-167BBXI Package Diagram Package Type Operating Range Industrial Industrial 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) Commercial 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) 51-85108 256-ball Ball Grid Array 17 mm × 17 mm with 1.0 mm pitch (Pb-free) Ordering Code Definitions CY DXX SXX V18 - XXX XXXX X Temperature Range: X = C or I C = Commercial; I = Industrial Package Type: (XXXX = BG or BB or BBA or BGX or BBX or BBAX) BG, BB, BBA = Ball Grid Array BGX, BBX, BBAX = Ball Grid Array (Pb-free) Speed Grade: XXX = 167 MHz / 200 MHz V18 = 1.8 V SXX = Data Width DXX = Density in Mb CY = Cypress Document Number: 38-06082 Rev. *K Page 45 of 52 [+] Feedback FullFlex Package Diagrams Figure 34. 256-ball FPBGA (17 × 17 mm), 51-85108 51-85108 *H Document Number: 38-06082 Rev. *K Page 46 of 52 [+] Feedback FullFlex Package Diagrams Figure 35. 484-ball PBGA (23 mm × 23 mm × 2.03 mm), 51-85218 51-85218 *A Document Number: 38-06082 Rev. *K Page 47 of 52 [+] Feedback FullFlex Package Diagrams Figure 36. 484-ball PBGA (27 mm × 27 mm × 2.33 mm), 001-07825 001-07825 *A Acronyms Acronym BGA CMOS DLL FPBGA HSTL I/O SDR SRAM TCK TDI TDO TMS VIM ball grid array complementary metal oxide semiconductor delay lock loop fine pitch ball gird array high speed transceiver logic input/output single data rate static random access memory test clock test data in test data out test mode select variable impedance matching Description Document Conventions Units of Measure Symbol °C MHz µA mA ms mV ns pF V W degree Celcius Mega Hertz micro Amperes milli Amperes milli seconds milli Volts nano seconds pico Farad Volts Watts Unit of Measure Document Number: 38-06082 Rev. *K Page 48 of 52 [+] Feedback FullFlex Document History Page Document Title: FullFlex™ Synchronous SDR Dual Port SRAM Document Number: 38-06082 REV. ** *A *B ECN NO. 302411 334036 395800 Submission Date See ECN See ECN See ECN Orig. of Change YDT YDT SPN New data sheet Corrected typo on page 1 Reproduced PDF file to fix formatting errors Added statement about no echo clocks for flow through mode Updated electrical characteristics Added note 16 and 17 (1.5 V timing) Added note 33 (timing for x18 devices) Updated input edge rate (note 34) Updated table 5 on deterministic access control logic Added description of busy readback in deterministic access control section Changed dummy write descriptions Updated ZQ pins connection details Updated note 24, B0 to BE0 Added power supply requirements to MRST and VC_SEL Added note 4 (VIM disable) Updated supply voltage to ground potential to 4.1 V Updated parameters on table 15 Updated and added parameters to table 16 Updated x72 pinout to SDR only pinout Updated 484 PBGA pin diagram Updated the pin definition of MRST Updated the pin definition of VC_SEL Updated READY description to include Wired OR note Updated master reset to include wired OR note for READY Updated minimum VOH value for the 1.8 V LVCMOS configuration Updated electrical characteristics to include IOH and IOL values Updated electrical characteristics to include READY Added IIX3 Updated maximum input capacitance Added Notes 33 and 34Removed Notes 15 and 17 Updated Pin Definitions for CQ0, CQ0, CQ1, and CQ1 Removed -100 Speed bin from Table.1 Selection Guide Changed voltage name from VDDQ to VDDIO Changed voltage name from VDD to VCORE Moved the Mailbox Interrupt Timing Diagram to be the final timing diagram Updated the Package Type for the CYD36S18V18 parts Updated the Package Type for the CYD36S18V18 parts Updated the Package Type for the CYD18S18V18 parts Updated the Package Type for the CYD18S36V18 parts Included the Package Diagram for the 256-Ball FBGA (19 x 19 mm) BW256 Included an OE Controlled Write for Flow through Mode Switching Waveform Included a Read with Echo Clock Switching Waveform Updated Figure 5 and Figure 6 Updated Electrical Characteristics for READY VOH and READY V Updated Electrical Characteristics for VOH and VOL for the -167 and -133 speeds Included a Unit column for Table 5 Removed Switching Characteristic tCA from chart Included tOHZ in Switching Waveform OE Controlled Write for Pipelined Mode Included tCKLZ2 in Waveform Read-to-Write-to-Read for Flow through Mode Description of Change Document Number: 38-06082 Rev. *K Page 49 of 52 [+] Feedback FullFlex Document History Page (continued) Document Title: FullFlex™ Synchronous SDR Dual Port SRAM Document Number: 38-06082 REV. *C ECN NO. 402238 Submission Date SEE ECN Orig. of Change KGH Description of Change Updated AC Test Load and Waveforms Included FullFlex36 SDR 484-Ball BGA Pinout (Top View) Included FullFlex18 SDR 484-Ball BGA Pinout (Top View) Included Timing Parameter tCORDY Changed ordering information with Pb-free part numbers Removed VC_SEL Added IO and core voltage adders Removed references to bin drop for LVTTL/2.5 V LVCMOS and 1.5 V core modes Updated Cin and Cout Updated ICC, ISB1, ISB2 and ISB3 tables Updated busy address read back timing diagram Added HTSL input waveform Removed HSTL (AC) from DC tables Added 484-ball 27 mmx27 mmx2.33 mm PBGA package Changed VOL of 1.8 V LVCMOS to 0.45 V Updated tRSF VREF is DNU when HSTL is not used Formatted pin description table Changed VDDIO pins for 36M x 36 and 36M x 18 pinouts Changed 36Mx72 JTAG IDCODE DLL Change, added Clock Input Cycle to Cycle Jitter Modified DLL description Changed Input Capacitance Table Changed tCCS number Added note 31 change all NC to DNU corrected switching waveform for (CQEN = High) from both Pipeline and Flow through mode to only pipeline mode Modified master reset description Modified switching characteristics tables, extracted signals effected by the DLL into one table and combine all other signals into one table updated package name Added footnote for tHD, tHAC and tSAC changed note 26 description *D 458131 SEE ECN YDT *E 470031 SEE ECN YDT *F 500001 SEE ECN YDT *G 627539 SEE ECN QSL Document Number: 38-06082 Rev. *K Page 50 of 52 [+] Feedback FullFlex Document History Page (continued) Document Title: FullFlex™ Synchronous SDR Dual Port SRAM Document Number: 38-06082 REV. *H ECN NO. 2505003 Submission Date See ECN Orig. of Change VKN/ AESA Description of Change Modified footnote #1 Removed 250 MHz speed bin Added 2-Mbit part and it’s related information Changed ball name ZQ1 to DNU for 18M and lesser density devices Added 256-Ball (17 x 17 mm) BGA package for 18M Made PORTSTD[1:0] left and right pins driven only by LVTTL reference level For 1.8V LVCMOS level, Changed VIH(min) from 1.26V to 0.65 times VDDIO and Changed VIL(max) from 0.36V to 0.35 times VDDIO Changed tHD, tHAC specs for 36M from 0.6 ns/0.7 ns to 0.8 ns (See footnote# 32) Updated Ordering Information table Modified “Counter Load Operation” section on page 12 and in Table7. on page 13. Corrected typo in Table 14. by making LowSPD = 0 for tCD1 spec in the description. Modified figure 16. on page 30. Removed inactive parts from Ordering Information. Updated Packaging Information. Corrected “ Counter Interrupt operation” Section in Page 14 of the datasheet Updated ordering information with the parts, CYD02S36V18-200BBC and CYD36S72V18-167BGI. Updated Ordering Information and added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits. Updated Electrical Characteristics on page 21 (Removed 133 MHz speed bin). Updated Switching Characteristics on page 26 (Removed 133 MHz speed bin). Removed information for 4Mb devices. Updated Ordering Information. *I 2898491 07/01/2010 RAME *J 2995098 07/28/2010 RAME *K 3267210 05/26/2011 ADMU Document Number: 38-06082 Rev. *K Page 51 of 52 [+] Feedback FullFlex Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2005-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-06082 Rev. *K Revised May 31, 2011 Page 52 of 52 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback