IBIS4-1300_09

IBIS4-1300 1.3 MPxl Rolling Shutter CMOS Image Sensor Features • • • • • • • • • • • • • • • • • SXGA resolution: 1280 x 1024 pixels High sensitivity 20 µV/eHigh fill factor 60% Quantum efficiency > 50% between 500 and 700 nm. 20 noise electrons = 50 noise photons Dynamic range: 69 dB (2750:1) in single slope operation Extended dynamic range mode (80…100 dB) in double slope integration On-chip 10 bit, 10 mega Samples/s ADC Programmable gain & offset output amplifier 4:1 sub sampling viewfinder mode (320x256 pixels) Electronic shutter 7 x 7 µm2 pixels Low fixed pattern noise (1% Vsat p/p) Low dark current: 344 pA/cm2 (1055 electrons/s, 1 minute auto saturation) RGB or monochrome Digital (ADC) gamma correction Overview The IBIS4-1300 is a digital CMOS active pixel image sensor with SXGA format. Due to a patented pixel configuration a 60% fill factor and 50% quantum efficiency are obtained. This is combined with an on-chip double sampling technique to cancel fixed pattern noise. Part Number Part Number CYII4SC1300AA-QSC CYII4SM1300AA-QDC Package Glass lid LCC LCC S8612 D263 RGB/B&W RGB Bayer pattern B&W Cypress Semiconductor Corporation Document Number: 38-05707 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 2, 2007 IBIS4-1300 TABLE OF CONTENTS Overview ............................................................................................................................. 1 Features .............................................................................................................................. 1 Part Number ........................................................................................................................ 1 Architecture of the image sensor.......................................................................................... 4 Image sensor core - focal plane array ...................................................................................... 5 Output amplifier ........................................................................................................................ 11 Analog to digital converter ........................................................................................................ 17 ADC timing ............................................................................................................................... 18 Operation of the image sensor ............................................................................................ 20 Set configuration & pulse timing ............................................................................................... 20 Illumination control ................................................................................................................... 26 "Double slope" or "High-dynamic range" mode ........................................................................ 27 Electrical parameters ............................................................................................................... 28 Pin configuration .................................................................................................................. 29 Pin list ....................................................................................................................................... 29 Bonding pad geometry for the IBIS4-1300 ............................................................................... 31 Package .............................................................................................................................. 33 Cover glass .............................................................................................................................. 33 Ordering Information ........................................................................................................... 35 FAQ ..................................................................................................................................... 35 Temperature dependence of dark signal ................................................................................. 35 Useful range of "double slope" ................................................................................................. 35 Skipping rows or columns ........................................................................................................ 36 Disclaimer ............................................................................................................................ 36 Document History Page ...................................................................................................... 37 LIST OF FIGURES Block diagram ................................................................................................................................... 4 Architecture of the image sensor core .............................................................................................. 4 Pixel selection - principle .................................................................................................................. 5 Spectral response * fill factor of the IBIS4-1300 pixels ..................................................................... 7 Near infrared spectral response ....................................................................................................... 8 IBIS4-1300 response curve - two pixels - lowest gain setting (0000) ............................................... 9 Output amplifier architecture ............................................................................................................. 12 Offset adjustment: fast offset adjustment mode ............................................................................... 13 Slow offset adjustment mode ............................................................................................................ 13 Output amplifier DC gain .................................................................................................................. 15 Output amplifier bandwidth for different gain settings ....................................................................... 16 Typical transfer characteristic of the output amplifier (no clipping, Voffset = 2 V, input signal during offset adjustment is 1.2 V) ........................................................................................................................... 16 Suggested circuit for high and low references of DAC ..................................................................... 17 Document Number: 38-05707 Rev. *B Page 2 of 37 IBIS4-1300 ADC timing ........................................................................................................................................ 18 Linear and non-linear ADC conversion characteristic ....................................................................... 19 Typical operation mode (readout of a frame) .................................................................................... 20 Timing of Y shift registers (for row selection) .................................................................................... 22 End-of-scan pulse ............................................................................................................................. 22 Timing constraints for row readout initialization (blanking time) ....................................................... 23 Pulse on 'CALIB_F'& 'UNITYGAIN' to be given once per frame, or on CALIB_S once per line ....... 24 Timing of X shift register and pixels read-out ................................................................................... 25 Pixel timing ....................................................................................................................................... 25 Pulse sequence used in IBIS4 breadboard v. jan 2000 .................................................................... 26 Schematic representation of the curtain type electronic shutter ....................................................... 26 response curve of the pixels in dual slope integration ...................................................................... 27 Linear long exposure time ................................................................................................................ 27 Linear short exposure time ............................................................................................................... 28 Double slope integration ................................................................................................................... 28 Pin layout and package, top view ..................................................................................................... 33 Transmission characteristics of the BG39 glass used as NIR cut-off filter for the FUGA1000 color image sensors .............................................................................................................................................. 34 Transmission characteristics of the D263 glass used as protective cover for the IBIS4-1300 monochrome image sensors .................................................................................................................................... 34 LIST OF TABLES Optical & electrical characteristics .................................................................................................... 5 Calculation of sensitivity in [V/lx.s]..................................................................................................... 8 Pins of the image sensor core .......................................................................................................... 10 Summary of output amplifier specifications ...................................................................................... 11 Pins involved in output amplifier circuitry .......................................................................................... 14 DC gain of output amplifier for different gain settings ....................................................................... 15 ADC specifications ............................................................................................................................ 17 Pins of the ADC ................................................................................................................................ 18 Co-ordinate of the row or column selected by the Y/X shift registers after a # clock periods in viewfinder mode and full image mode ................................................................................................................. 21 Timing constraints on row initialization pulses sequence ................................................................. 23 FillFactory and Cypress part numbers .............................................................................................. 35 Document Number: 38-05707 Rev. *B Page 3 of 37 IBIS4-1300 Architecture of the image sensor Block diagram 1280 x 1024 pixel array 10 bit ADC output amplifier The IBIS4-1300 is an SXGA CMOS image sensor. The chip is composed of 3 modules: an image sensor core, a programmable gain output amplifier, and an on-chip 10 bit ADC. Figure 1. Architecture of the image sensor core Y readout shift register Readout row pointer 1286 x 1030 pixels Clock_YR Clock_YL Sync_YL Column amplifiers X shift register Sync_YR Clock_X Document Number: 38-05707 Rev. *B Sync_X Reset row pointer Pixel array Y reset shift register Page 4 of 37 IBIS4-1300 Image sensor core - focal plane array Figure 1. shows the architecture of the image sensor core. The core of the sensor is the pixel array with 1280 x 1024 (SXGA) active pixels. The name 'active pixels' refers to the amplifying element in each pixel. This type of pixels offer a high light sensitivity combined with low temporal noise. The actual array size is 1286 x 1030 including the 6 dummy pixels in X and Y. Although the dummy pixels fall outside the SXGA format, their information can be used e.g. for color filter array interpolation. Figure 2. Pixel selection - principle Y readout shift register X shift register Next to the pixel array there are two Y shift registers, and one X shift register with the column amplifiers. The shift registers act as pointers to a certain row or column. The Y readout shift register accesses the row (line) of pixels that is currently readout. The X shift register selects a particular pixel of this row. The second Y shift register is used to point at the row of pixels that is reset. The delay between both Y row pointers determines the integration time -thus realizing the electronic shutter. A clock and a synchronization pulse control the shift registers. On every clock pulse, the pointer shifts one row/column Table 1. optical & electrical characteristics Pixel characteristics Pixel structure Photodiode Pixel size Resolution Pixel rate with on-chip ADC Frame rate with on-chip ADC Document Number: 38-05707 Rev. *B further. A sync pulse is used to reset and initialize the shift registers to their first position. The smart column amplifiers compensate the offset variations between individual pixels. To do so, they need a specific pulse pattern on specific control signals before the start of the row readout. Table 1. summarizes the optical and electrical characteristics of the image sensor. Some specifications are influenced by the output amplifier gain setting (e.g. temporal noise, conversion factor,...). Therefore, all specifications are referred to an output amplifier gain equal to 1. 3-transistor active pixel High fill factor photodiode 7 x 7 µm2 1286 x 1030 pixels SXGA plus 6 dummy rows & columns Nominal 10 MHz (note 1) (note 2) About 7 full frames/s at nominal speed Page 5 of 37 IBIS4-1300 Table 1. optical & electrical characteristics Pixel characteristics Frame rate with analog output Up to 23 full frames per second (see table1.1) Table 1.1: In this table you find achievable values using the analog output X pixelsY pixels # # 1286 1030 1286 1030 1286 1030 1286 1030 1286 512 X Freq Hz 1,00E+07 2,00E+07 3,00E+07 3,75E+07 3,75E+07 X Clock X Blanking sec sec 1,00E-07 6,25E-06 5,00E-08 6,25E-06 3,33E-08 6,25E-06 2,67E-08 6,25E-06 2,67E-08 6,25E-06 line time sec 0,000134850 0,000070550 0,000049117 0,000040543 0,000040543 frame time frame rate sec per sec 0,138895500 7,20 0,072666500 13,76 0,050590167 19,77 0,041759633 23,95 0,020758187 48,17 pixel rate pixel rate freq sec Hz 1,049E-07 9536522 5,486E-08 18228207 3,819E-08 26182559 3,153E-08 31719148 3,153E-08 31719148 Note 1. The pixel rate can be boosted to 37.5 MHz. This requires a few measures. • increase the analog bandwidth by halving the resistor on pin Nbias_oamp • increase the ADC speed by the resistors related to the ADC speed (nbiasana1, nbiasana2, pbiasencload) • experimentally fine tune the relative occurrence of the ADC clock relative to the X-pixel clock. Note 2. The pure digital scan speed in X and Y direction is roughly 50 MHz. This is the maximum speed for skipping rows and columns. Light sensitivity & detection Spectral sensitivity range Spectral response * fill factor Quantum efficiency * fill factor Fill factor Charge-to-voltage conversion gain Output signal amplitude Full well charge [electrons] Noise equivalent flux at focal plane (700 nm) Sensitivity MTF @ Nyquist frequency Optical cross talk Image quality Temporal noise (dark, short integration time) Dynamic range (analog output, before ADC conversion) Dark current 20 noise electrons = 50 peak noise photons (*) 400 µV RMS 2750:1 69 dB 344 pA/cm2 @ 21ºC 19 mV/s 1055 electrons/s Typically 15% RMS of dark current level. 9.6 mV peak-to-peak 1-2 mV RMS 10% peak-to-peak @ ½ of saturation signal Page 6 of 37 400 - 1000 nm 0.165 A/W @ 700 nm > 30% between 500 & 700 nm 60% 20 µV/e1.2 V IBIS4-1300: about 90000 saturation, 50000 linear range 1.1e-4 lx*s (at focal plane) 6.3 e-7 s.W/m2 7 V/lx.s 1260 V.m2/W.s 0.4-0.5 @ 450 nm 0.25-0.35 @ 650 nm 10% to 1st neighbor 2% to 2nd neighbor Dark current non-uniformity Fixed pattern noise (dark, short integration time) Photo-response non-uniformity (PRNU) Document Number: 38-05707 Rev. *B IBIS4-1300 Table 1. optical & electrical characteristics Pixel characteristics Yield criteria Anti-blooming Smear No missing columns nor rows Less than 100 missing pixels, clusters= 105 Absent (*) peak noise photons are defined as (noise electrons) / (FF*peak QE) Features & general specifications Electronic shutter Viewfinder mode Digital output Color filter array Die size Package Supply voltage Power supply feed trough (dVout/dVdd) Power dissipation (continuous operation, 10 MHz, ADC outputs loaded) Light sensitivity Figure 3. Spectral response * fill factor of the IBIS4-1300 pixels Rolling curtain type Increment = line time = 135 us 4 x sub-sampling (320 x 256 pixels) 10 bit Primary colors (Red, Green, Blue) RGB diagonal stripe pattern or Bayer pattern 10.30 x 9.30 mm2 84 pins LCC chip carrier 0.460 inch cavity 5 V stabilized (e.g. from a 7805 regulator) < 0.3 for low-frequencies (< 1 MHz) < 0.05 for high frequencies (> 1 MHz) Min. 50 mA, Typ. 70 mA, Max. 90 mA 0.2 0.18 0.16 Response [A/W] 30% 40% 20% 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 400 500 600 700 800 900 10% 1000 Wavelength [nm] Document Number: 38-05707 Rev. *B Page 7 of 37 IBIS4-1300 Figure 3. shows the spectral response characteristic. The curve is measured directly on the pixels. It includes effects of non-sensitive areas in the pixel, e.g. interconnection lines. The sensor is light sensitive between 400 and 1000 nm. The peak QE * FF is more than 30% between 500 and 700 nm. In view of a fill factor of 60%, the QE is thus larger than 50% between 500 and 700 nm. Figure 4. Near infrared spectral response 1.00E+00 800 850 900 950 Wavelength [nm] 1000 1050 50% QE 1100 1.00E-01 10% QE Spectral Response (* FF) [A/W] Pixel array plain diode 1.00E-02 1% QE IBIS4 Near-IR spectral response 1.00E-03 calculation of sensitivity in [V/lx.s] Pixel area A Fill factor FF Spectral response SR FF*SR Pixel capacitance Ceff Sensitivity = FF*SR*Ceff/A Conversion to lux: 1W/m2 = Sensitivity in lux units: 49 E-12 m2 60% 0.22 A/W (average) 0.13 A/W (average over wavelength) 5E-15 F 1.27E+3 [V.W/s.m2] About 180 lux, visible light only About 70 lux, including Near Infrared 7.08 [V/lx.s] visible light only 18 [V/lx.s] if near IR included. Document Number: 38-05707 Rev. *B Page 8 of 37 IBIS4-1300 Color sensitivity 2.00E+05 1.80E+05 1.60E+05 1.40E+05 1.20E+05 1.00E+05 Ibis4b 8.00E+04 B&W curve: glass window RGB curves: BG39 IR cut off 6.00E+04 4.00E+04 2.00E+04 Wavelength [nm] 0.00E+00 400 500 600 700 800 900 1000 Charge conversion - Conversion of electrons in an output signal Figure 5. IBIS4-1300 response curve - two pixels - lowest gain setting (0000) 1,2 Output signal [V] 1 0,8 0,6 0,4 0,2 0 0 20000 40000 60000 80000 # electrons 100000 Document Number: 38-05707 Rev. *B Page 9 of 37 IBIS4-1300 Figure 5. shows the pixel response curve in linear response mode. This curve is the relation between the electrons detected in the pixel and the output signal. This curve was measured with light of 600 nm, with an integration time of 138.75 ms (10 MHz pixel rate), at minimal gain setting 0000. The resulting voltage/electron curve is independent of these parameters. The conversion gain is 18 uV/electron for this gain setting. Note that the upper part of the curve (near saturation) is actually a logarithmic response, similar to the FUGA1000 Table 2. Pins of the image sensor core Digital controls SYNC_YR\ CLK_YR EOS_YR\ SYNC_X\ CLK_X EOS_X\ SYNC_YL\ CLK_YL EOS_YL\ SHY SIN SELECT 5 6 7 28 29 8 36 37 38 30 35 40 sensor. The level of saturation can be adjusted by the voltage on GND-AB. However note also that this logarithmic part of the response is not FPN corrected by the on-chip offset correction circuitry. The signal swing (and thus the dynamic range) is extended by increasing the VDD_RESET (pins 59/79) to 5.5 V. This is mode of operation is not further documented. Table 2. shows the pins of the IC that are related to the image sensor core, describing their functionality. Reset right Y shift register (low active, 0 = sync) Clock right Y shift register (shifts on falling edge) (output) low 1st CLK_YR pulse after last row (low active) Reset X shift register (low active, 0 = sync) Clock X shift register (shifts on falling edge) (output) Low 1st CLK_X pulse after last active column (low active) Reset left Y shift register (low active, 0 = sync) Clock left Y shift register (shifts on falling edge) Low 1st CLK_YL pulse after last row Parallel Y track & hold (1 = hold, 0 = track) apply pulse pattern - see sensor timing diagram Column amplifier calibration pulse 1 = calibrate - see sensor timing diagram Selects row indicated by left/right shift register high active (1= select row) Apply 5 V DC for normal operation Resets row indicated by left/right shift register high active (1 = reset) Apply pulse pattern - see timing diagram Use left or right register for SELECT and RESET 1 = left / 0 = right - see sensor timing Activate viewfinder mode (1:4 sub sampling = 320 x 256 pixels) high active, 1 = sub sampling RESET L/R\ SUBSMPL Reference voltages DCCON DCREF NBIASARRAY PBIAS2 PBIAS XMUX_NBIAS 41 80 84 31 32 1 2 3 4 Control voltage for the DCREF voltage generation Connect to ground by default Reference voltage (output), to be decoupled to GND Should be about 1.2V, can be adjusted by DCCON 1 MegaOhm to VDD and decouple to ground by 100 nF capacitor 1 MegaOhm to ground and decouple to VDD by 100 nF capacitor 1 MegaOhm to ground and decouple to VDD by 100 nF capacitor 100K to VDD and decouple to ground by 100 nF capacitor Document Number: 38-05707 Rev. *B Page 10 of 37 IBIS4-1300 Table 2. Pins of the image sensor core Digital controls GND_AB 54 Anti-blooming drain control voltage • Default: connect to ground. The anti blooming is operational but not maximal. • Apply about 1 V DC for improved anti-blooming Power & ground VDD_RESETL VDD_RESETR VDD_ARRAY VDD 59 79 55 11 34 53 77 10 33 52 78 Power supply for left reset line drivers apply 5 V DC (default) or about 4…4.5 V for dual slope mode Power supply for right (default) reset line drivers 5 V DC Power supply for the pixel array 5 V DC Power supply of image sensor core & output amplifier 5 V DC GND Ground of image sensor core & output amplifier Output amplifier The output amplifier stage is user-programmable for gain and offset level. Gain and offset are controlled by 4-bit wide words. Gain settings are on an exponential scale. Offset is controlled by a 4-bit wide DAC, which selects the offset voltage between 2 reference voltages (Vhigh_dac & Vlow_dac) on a linear scale. Table 3. Summary of output amplifier specifications Min. Gain Output signal range Bandwidth (40 pF load) Output slew rate (40 pF load) 1.2 (gain setting 0) 1V 12 MHz (gain setting 15) 40 V/ µs The offset setting is independent of the gain setting. The gain setting is independent of amplifier bandwidth. The amplifier is designed to match the specifications like the output of the imager array. This signal has a data rate of 10 MHz and is located between 1.2 and 2.4 V. Table 3. summarizes the specifications of the amplifier. Typ 2.7 (setting 4) Max 16 (setting 15) 4.5 V 22 MHz (gain setting 0...8) 50 V/µs 33 MHz (gain setting 0) 80 V/µs The range of the output stage input is between 1 and 4 V. A lowest gain the sensor outputs a signal in between 1.2 and 2.2 V, which fits into the input range of the amplifier. The range of the output signal is between 1 and 4.5 V, dependent on the gain and offset settings of the amplifier. This range should fit to the input range of the ADC, external or internal. The on-chip ADC range is between 2 and 4 V. A minimal gain setting of "3" seems necessary for the internal ADC, and the offset voltage should be set to the low-reference voltage of the ADC. Document Number: 38-05707 Rev. *B Page 11 of 37 IBIS4-1300 Figure 6. output amplifier architecture pixel array extin sel_extin A Clip + 1 gain [0..3] unity gain 1.1.1.1.1 Vhigh_dac offset [0..3] Vlow_dac Figure 6. shows the architecture of the output amplifier. First of all, there is a multiplexer which selects either the imager core signal or an external pin EXTIN as the input of the amplifier. EXTIN can be used for evaluation, or to feed alternative data to the output. SEL_EXTIN controls this switch. Then, the signal is fed to the first amplifier stage. This stage has an adjustable gain, controlled by a 4-bit word ('gc_bit0...3'). Then, the upper level of the signal must be clipped in some situations (clipping sometimes is necessary when the imager signal is highly saturated, which affects the calibration level. This is visible as black banding at the right side of bright objects in the scene). In order to do this, a voltage should be applied to the 'Clip' pin. The signal is clipped if it is higher than Vclip - Vth,pmos, where Vth,pmos is the PMOS threshold voltage and is typically -1 V. If clipping is not necessary, 5 V should be applied to 'Clip'. After this, the offset level is added. This offset level is set by a DAC, controlled by a 4-bit word (DAC_bit0...3). The offset level can be calibrated in two modes: fast offset adjustment or slow offset adjustment. This is controlled by 'calib_s' and 'calib_f'. The slow adjustment yields a somewhat cleaner image. After this, the signal is buffered by a unity feedback amplifier and it leaves the chip. This 2nd amplifier stage determines the maximal readout speed, i.e. the bandwidth and the slew rate Calib_f Calib_s D A C of the output signal. The whole amplifier chain is designed for a data rate of 10 Mpix/s (@ 40 pF). (It is up to the experimenter to increase this speed by reducing the various setting resistors) Table 4. shows the IBIS4-1300 pins used by the output amplifier with a short functional description. Power and ground lines are shared between the output amplifier and the image sensor. Output amplifier offset level adjustment The purpose of this adjustment is to bring the pixel voltage range as good as possible within the ADC range. The offset level of the output signal is controlled by a 4-bit resistive DAC. This DAC selects the offset level on a linear scale between 2 reference voltages. These reference voltages are applied to Vlow_dac and Vhigh_dac. This offset level is adjusted during the calibration phase. During this phase, the amplifier input should be constant and refers to the 'zero' signal situation. The IBIS4-1300 outputs a dark reference signal after a row has been read out completely. This signal can be used as the 'zero signal' reference. Alternatively one can apply an external reference on pin EXTIN, which is applied to the output amplifier when SEL_EXTIN is 1. Offset adjustment can be done during row or frame blanking time. Document Number: 38-05707 Rev. *B Page 12 of 37 IBIS4-1300 Figure 7. offset adjustment: fast offset adjustment mode min. 500 ns calib_f stable input dark signal unitygain > 100 ns >0 There are 2 modes of offset calibration for the output amplifier: slow and fast adjustment. Figure 7. shows the timing and signal waveforms for fast offset adjustment mode. Closing both 'calib_f' and 'unitygain' operates it. After 'calib_f' is opened again, the offset level is adjusted to the desired value in a single cycle. The signal applied to the output amplifier should be stable just before and during the adjustment phase. The same is true for the DAC output. The signal applied to the output amplifier can be either: • The signal generated by the electrical dark reference in the imager core itself, i.e. the pixels named "dark" inFigure 20. • Apply the reference from outside on the pin EXTIN, controlled by SEL_EXTIN. If this fast offset adjustment is used, it should be done once each frame, before the readout of the frame starts, e.g. during the blanking time of the first line. Figure 8. slow offset adjustment mode min. 100 ns calib_s stable input dark signal min 100 ns Figure 8. shows the timing and signal waveforms for slow offset adjustment mode. It is operated by pulsing 'calib_s'. The amplifier input signal must be stable and refer to 'dark' signal at the moment when calib_s goes low. The offset is slowly adjusted with a time constant of about 100 of these pulses. One pulse is then generated during each row blanking time. The baseline is to use the fast calibration once per image. The slow calibration is intended as alternative if, for very slow readout, the offset drifts during the image. Document Number: 38-05707 Rev. *B Page 13 of 37 IBIS4-1300 Table 4. Pins involved in output amplifier circuitry Name Analog signals Extin Output Digital Controls Sel_extin gc_bit0 gc_bit1 gc_bit2 gc_bit3 unitygain calib_s 9 17 18 19 20 21 16 1 = output amplifier in unity feedback mode 0 = output amplifier gain controlled by gc_bit0...3 Slow (or incremental) output offset level adjustment (calibration of output amplifier). Offset adjustment converges after about 100 pulses on calib_s Amplifier input should refer to a 'zero signal' at the moment of the 1->0 transition on calib_s 0 = connect to capacitor (of stage 2) and in- (of stage 1) 1 = connect to DAC output (of stage 2) and out (of stage1) Fast (=in 1 cycle) output offset level adjustment (calibration of output amplifier) Offset level is adjusted when both calib_f and unitygain are high Amplifier input should refer to 'zero signal' when calib_f is high 1 = connect DAC output to offset of capacitor 0 = DAC output disconnected LSB Control bits for output offset level adjustment Between Vlow_dac (0000) & Vhigh_dac (1111) MSB 1 = external input pin (extin) is applied at the input of the amplifier 0 = output amplifier is connected to the image sensor array LSB Control bits for output amplifier gain setting Gain adjustment between 1.2 (0000) & 16X (1111) MSB 12 13 External input of the output amplifier Active if Sel_extin = 1 Analog output signal To be connected to the input of the ADC (in_adc, pin 73) No. Function calib_f 22 dac_b0 dac_b1 dac_b2 dac_b3 Reference voltages Vlow_dac Vhigh_dac 26 25 24 23 14 15 Low and high references for offset control DAC of the analog output. The range of this resistive division DAC should be about 1V to 2.5V. If the range is not OK, one will notice that it is not possible to adjust the output voltage to the appropriate level of the ADC. As the internal division resistor is about 1.3 Kohm, we suggest to tie Vlow_dac with 1K to GND and Vhigh_dac with 2K7 to VDD. Output amplifier speed/power. Connect with 100 K to VDD and decouple with 100 nF to GND. This setting yields 10 MHz nominal pixel rate. Lowering the resistance does increasing this rate. Voltage that can be used to clip the output signal Clips output if output signal > 'Vclip - Vth, PMOS' with Vth,PMOS=-1V Default: 5 V (no clipping) Page 14 of 37 Nbias_oamp 27 Clip 83 Document Number: 38-05707 Rev. *B IBIS4-1300 Output amplifier gain control Figure 9. output amplifier DC gain 20,00 18,00 16,00 14,00 DC gain (< 1MHz) y=1.074*2 0.246*x 12,00 10,00 8,00 6,00 4,00 2,00 0,00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 gain setting Table 5. DC gain of output amplifier for different gain settings gain setting 0000 0001 0010 0011 0100 0101 0110 0111 DC gain (