IBIS5-B-1300

IBIS5-B-1300 CYII5FM1300AB 1.3 MP CMOS Image Sensor Description The IBIS5-B-1300 is a solid state CMOS image sensor that integrates the functionality of complete analog image acquisition, digitizer, and digital signal processing system on a single chip. This 1.3-mega pixel (1280 x 1024) CMOS active pixel sensor dedicated to industrial vision applications features both rolling and snapshot (or global) shutter. Full frame readout time is 36 ms (max. 27.5 fps), and readout speed are boosted by windowed region of interest (ROI) readout. Another feature includes the double and multiples slope functionality to capture high dynamic range scenes. The sensor is available in a Monochrome version or Bayer (RGB) patterned color filter array. User programmable row and column start/stop positions allow windowing down to a 2x1 pixel window for digital zoom. Sub sampling or viewfinder mode reduces resolution while maintaining the constant field of view and an increased frame rate. An on-chip analog signal pipeline processes the analog video output of the pixel array. Double sampling (DS) eliminates the fixed pattern noise. The programmable gain and offset amplifier maps the signal swing to the ADC input range. A 10-bit ADC converts the analog data to a 10-bit digital word stream. The sensor uses a 2-wire, I2C™-compatible interface, a 3-wire serial parallel (SPI) interface, or a 16-bit parallel interface. It operates with a 3.3V power supply and requires only one master clock for operation up to 40 MHz. It is housed in an 84-pin ceramic LCC package. Table 1. Key Performance Parameters Parameter Typical Value 1280 (H) x 1024 (V) 6.7 µm x 6.7 µm 2/3 inch Snapshot (global) shutter rolling shutter 40 MPS / 40 MHz 27 fps (1280 x 1024) 106 fps (640 x 480) 10-bit, on-chip 715 V.m2/W.s 8.40 V/lux.s 64 dB 62.500 e– 40 e– 7.22 mV/s Multiple slope Analog: 3.0V–4.5V Digital: 3.3V I/O: 3.3V 175 mW –30°C to +65°C Mono RGB Bayer pattern 84-pins LCC Active pixels Pixel size Optical format Shutter type Maximum data rate / master clock Frame rate ADC resolution Sensitivity (@ 650 nm) S/N ratio Full well charge Temporal noise Dark current High dynamic range Supply voltage Applications n n n n Machine vision Inspection Robotics Traffic monitoring Power consumption Operating temperature Color filter array Packaging IBIS5-B-1300 Cypress Semiconductor Corporation Document #: 38-05710 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 27, 2007 IBIS5-B-1300 CYII5FM1300AB Architecture and Operation This section presents detailed information about the most important sensor blocks. Floor Plan Figure 1. Block Diagram of the IBIS5-B-1300 Image Sensor Sensor Imager core Reset C Y-right addressing Sample Select Pixel Y-left addressing Column output Pixel core Sequencer Column amplifiers Analog multiplexer Output amplifier System clock 40 MHz External connection X-addressing ADC Figure 1 shows the architecture of the IBIS5-B-1300 image sensor. It consists basically of a pixel array, one X- and two Y-addressing registers for the readout in X- and Y-direction, column amplifiers that correct for the fixed pattern noise, an analog multiplexer, and an analog output amplifier. Use the left Y-addressing register for readout operation. Use the right Y-addressing register for reset of pixel rows. In multiple slope synchronous shutter mode, the right Y-addressing register resets the whole pixel core with a lowered reset voltage. In rolling curtain shutter mode, use the right Y-addressing register for the reset pointer in single and double slope operation to reset one pixel row. The on-chip sequencer generates most of the signals for the image core. Some basic signals (like start/stop integration, line and frame sync signals, and others.) are generated externally. A 10-bit ADC is implemented on chip but electrically isolated from the image core. You must route the analog pixel output to the analog ADC input on the outside. Architecture The pixel architecture used in the IBIS5-B-1300 is a 4-transistor pixel as shown in Figure 2. Implement the pixel using the high fill factor technique as patented by Cypress (US patent No. 6,225,670 and others). The 4T-pixel features a snapshot shutter but can also emulate the 3T-pixel by continuously closing sampling switch M2. Using M4 as a global sample transistor for all pixels enables the snapshot shutter mode. Due to this pixel architecture, integration during read out is not possible in synchronous shutter mode. Figure 2. Architecture of the 4T-pixel M1 reset C M2 sample M3 mux M4 column output Pixel A description of the pixel architecture and the color filter array follows. Document #: 38-05710 Rev. *C Page 2 of 40 IBIS5-B-1300 CYII5FM1300AB Color Filter Array The IBIS5-B-1300 is also processed with a Bayer RGB color pattern. Pixel (0,0) has a green filter and is situated on a green-blue row. Green1 and green2 have a slightly different spectral response due to cross talk from neighboring pixels. Green1 pixels are located on a blue-green row, green2 pixels are located on a green-red row. Figure 4 shows the response of the color filter array as function of the wavelength. Note that this response curve includes the optical cross talk of the pixels. Figure 3. Color Filter Arrangement on the Pixels Red Green2 7).” on page 13), this requires a minimum pixel rate of nearly 40 MHz. The final bandwidth of the column amplifiers, output stage, and others is determined by external bias resistors. With a nominal pixel rate of 40 MHz, a full frame rate of a little more than 27 frames per second is obtained. The frame period of the IBIS5-B-1300 sensor depends on the shutter type. Rolling Shutter => Frame period = (Nr. Lines * (RBT + pixel period * Nr. Pixels)) with: Nr. Lines Nr. Pixels RBT Pixel period Number of lines read out each frame (Y) Number of pixels read out each line (X) Row blanking time = 3.5 µs (typical) 1/40 MHz = 25 ns Green1 Blue Example Read out time of the full resolution at nominal speed (40-MHz pixel rate): Red Green2 Red Green2 => Frame period = (1024 * (3.5 µs + 25 ns * 1280)) = 36.4 ms => 27.5 fps Snapshot shutter => Frame period = Tint + Tread out = Tint + (Nr. Lines * (RBT + pixel period * Nr. Pixels)) with: Tint Nr. Lines Nr. Pixels RBT Pixel period Green1 Blue Green1 Blue Pixel 0,0 Frame Rate The pixel rate for this sensor is high enough to support a frame rate of >100 Hz for a window size of 640 x 480 pixels (VGA format). Taking into account a row blanking time of 3.5 µs (as baseline, see also “Internal clock granularities (bits 4, 5, 6 and Integration (exposure) time Number of lines read out each frame (Y) Number of pixels read out each line (X) Row blanking time = 3.5 µs (typical) 1/40 MHz = 25 ns Figure 4. Color Filter Response Wavelength (nm) Document #: 38-05710 Rev. *C Page 3 of 40 IBIS5-B-1300 CYII5FM1300AB Example Read out time of the full resolution at nominal speed (40 MHz pixel rate) with an integration time of 1 ms: Image Core Operation Image Core Operation and Signalling Figure 5 is a functional representation of the image core without sub-sampling and column/row swapping circuits. Most of the signals involved are not available from the outside because they are generated by the X-sequencer and SS-sequencer blocks. The integration of the pixels is controlled by internal signals such as reset, sample, and hold which are generated by the on-chip SS-sequencer that is controlled with the external signals SS_START and SS_STOP. Reading out the pixel array starts by applying a Y_START together with a Y_CLOCK signal; internally this is followed by a calibration sequence to calibrate the output amplifiers (during the row blanking time). Signals necessary to do this calibration are generated by the on-chip X-sequencer. This calibration sequence takes typically 3.5 µs and is necessary to remove ‘Fixed Pattern Noise’ of the pixels and of the column amplifiers themselves by means of a double sampling technique. After the row blanking time, the pixels are fed to the output amplifier. The pixel rate is equal to the SYS_CLOCK frequency. Image Core Supply Considerations The image sensor has several supply voltages: VDDH is the voltage that controls the sample switches. Do not apply a higher voltage than this to the chip. The VDDR_LEFT voltage is the highest (nominal) reset voltage of the pixel core. => Frame period = 1 ms + (1024 * (3.5 µs + 25 ns * 1280)) = 37.4 ms => 26.8 fps Region-Of-Interest (ROI) Read Out Windowing is easily achieved by uploading the starting point of the X- and Y-shift registers in the sensor registers using the various interfaces. This downloaded starting point initiates the shift register in the X- and Y-direction triggered by the Y_START (initiates the Y-shift register) and the Y_CLK (initiates the X-shift register) pulse. The minimum step size for the x-address is two (only even start addresses are chosen) and one for the Y-address (every line is addressable). The frame rate increases almost linearly when fewer pixels are read out. Table 2 gives an overview of the achievable frame rates (in rolling shutter mode) with various ROI dimensions. Table 2. Frame Rate vs. Resolution Frame Frame Rate Readout Time [frames/s] [ms] Comment Image Resolution (X*Y) 1280 x 1024 640 x 480 100 x 100 27 100 1657 36 10 0.6 Full resolution. ROI read out. ROI read out. Figure 5. Image Core Vddreset VDDR_LEFT VDDH SAMPLE RESET HOLD VDDR_RIGHT Pixel row Y-left addressing Y_START Y_CLOCK Pixel A Pixel column Pixel B Y-right addressing Y_START Y_CLOCK VDDC Column amplifiers Read-pointer Output amplifier BUS_A BUS_B X addressing PXL_OUT SYS_CLOCK Document #: 38-05710 Rev. *C Page 4 of 40 IBIS5-B-1300 CYII5FM1300AB The VDDR_RIGHT voltage is generated from the VDDR_LEFT voltage using a circuit that is programmed with the KNEEPOINT_LSB/MSB bits in the sequencer register (see also “Pixel reset knee-point for multiple slope operation (bits 8, 9, and 10).” on page 14). You can disconnect the VDDR_RIGHT pin from the circuit and apply an external voltage to supply the multiple slope reset voltage by setting the VDDR_RIGHT_EXT bit in the SEQUENCER register. When no external voltage is applied (recommended), connect the VDDR_RIGHT pin to a capacitor (recommended value = 1µF). VDDC is the pixel core supply. VDDA is the image core and periphery analog supply. VDDD is the image core and periphery digital supply. Note that the IBIS5-B-1300 image sensor has no on-chip power rejection circuitry. As a consequence all variations on the analog supply voltages can contribute to random variations (noise) on the analog pixel signal, which is seen as random noise in the image. During the camera design, take precautions to supply the sensor with very stable supply voltages to avoid this additional noise. The pixel array (VDDR_LEFT, VDDH and VDDC) analog supplies are especially vulnerable to this. Snapshot Shutter Supply Considerations The recommended supply voltage settings listed in Table 3 are used when the IBIS5-B-1300 sensor is in snapshot shutter mode only. Table 3. Snapshot Shutter Recommended Supply Settings Description Typ Unit Dual Shutter Supply Considerations If you analyze the supply settings listed in Table 3, you can see some fixed column non-uniformities (FPN) when operating in rolling shutter mode. If a dual shutter mode (both rolling and snapshot shutter) is required during operation, you must apply the supply settings listed in Table 4 to achieve the best possible image quality. Table 4. Dual Shutter Recommended Supply Settings Description Typ Unit Parameter VDDH VDDR_LEFT VDDC VDDA VDDD GNDA GNDD GND_AB Voltage on HOLD switches. Highest reset voltage. Pixel core voltage. Analog supply voltage of the image core. Digital supply voltage of the image core. Analog ground. Digital ground. Anti-blooming ground. +4.5 +4.5 +3.0 +3.3 +3.3 0 0 0 V V V V V V V V Image Core Biasing Signals Table 5 summarizes the biasing signals required to drive the IBIS5-A-1300. For optimizations reasons, with respect to speed and power dissipation of all internal blocks, several biasing resistors are needed. Each biasing signal determines the operation of a corresponding module in the sense that it controls the speed and power dissipation. The tolerance on the DC-level of the bias levels can vary ±150 mV due to process variations. Parameter VDDH VDDR_LEFT VDDC VDDA VDDD GNDA GNDD GND_AB Table 5. Voltage on HOLD switches. Highest reset voltage. Pixel core voltage. Analog supply voltage of the image core. Digital supply voltage of the image core. Analog ground. Digital ground. Anti-blooming ground. Overview of Bias Signals +4.5 +4.5 +3.3 +3.3 +3.3 0 0 0 V V V V V V V V Signal Comment Related module DC-Level DEC_CMD DAC_VHIGH DAC_VLOW AMP_CMD COL_CMD PC_CMD ADC_CMD ADC_VHIGH ADC_VLOW Connect to VDDA with R = 50 kΩ and decouple to GNDA with C = 100 nF. Decoder stage. Connect to VDDA with R = 0Ω. Connect to GNDA with R = 0Ω. High level of DAC. Low level of DAC. 1.0V 3.3V 0.0V 1.2V 1.0V 1.1V 1.0V 2.7V 1.8V Connect to VDDA with R = 50 kΩ and decouple to GNDA with C = 100 nF. Output amplifier stage. Connect to VDDA with R = 50 kΩ and decouple to GNDA with C = 100 nF. Columns amplifiers stage. Connect to VDDA with R = 25 kΩ and decouple to GNDA with C = 100 nF. Pre-charge of column busses. Connect to VDDA with R = 50 kΩ and decouple to GNDA with C = 100 nF. Analog stage of ADC. Connect to VDDA with R = 360Ω and decouple to GNDA with C = 100 nF. High level of ADC. Connect to GNDA with R = 1200Ω and decouple to GNDA with C = 100 nF. Low level of ADC. Document #: 38-05710 Rev. *C Page 5 of 40 IBIS5-B-1300 CYII5FM1300AB X-Addressing Because of the high pixel rate, the X-shift register selects two columns at a time for readout, so it runs at half the system clock speed. All even columns are connected to bus A; all odd columns to bus B. In the output amplifier, bus A and bus B are combined into one stream of pixel data at system clock speed. At the end of the row blanking time, the X_SYNC switch is closed while all other switches are open and the decoder output is fed to the register. The decoder loads a logical one in one of the registers and a logical zero in the rest. This defines the starting point of the window in the X direction. As soon as the X_SYNC signal is released, the register starts shifting from the start position. When no sub-sampling is required, X_SUB is inactive. The pointer in the shift-register moves one bit at a time. When sub-sampling is enabled, X_SUB is activated. The shift register moves two bits at a time. Taking into account that every register selects two columns, hence two pixels sub-sampling results in the pattern ’XXOOXXOO’ when eight pixels are considered. Suppose the columns are numbered from left to right starting with 0 (zero) and sub-sampling is enabled: If columns 1 and 2, 5 and 6, 9 and 10 … are swapped using the SWAP_12 switches, a normal sub-sampling pattern of ’XOXOXOXO’ is obtained. If columns 3 and 4, 7 and 8, 11 and 12 … are swapped using the SWAP_30 switches, the pattern is ’OXOXOXOX’. If both the SWAP_12 and SWAP_30 switches are closed, pattern ’OOXXOOXX’ is obtained. Because every register addresses two columns at a time, the addressable pixels range in sub-sample mode is from zero to half the maximum number of pixels in a row (only even values). For instance: 0, 2, 4, 6, 8… 638. Table 6. X–Sub-sample Patterns X_SWAP12 X_SWAP30 Sub-Sample Pattern X_SUB 0 1 1 1 1 0 0 1 0 1 0 0 0 1 1 XXXXXXXX XXOOXXOO XOXOXOXO OXOXOXOX OOXXOOXX Y-addressing For symmetry reasons, the sub-sampling modes in the Y-direction are the same as in X-direction. Table 7. Y–Sub-Sample Patterns Y_SWAP12 Y_SWAP30 Sub-Sample Pattern 0 0 XXXXXXXX 0 0 XXOOXXOO 1 0 XOXOXOXO 0 1 OXOXOXOX 1 1 OOXXOOXX Y_SUB 0 1 1 1 1 Figure 6. Column Structure COL(i) COL(i+2) COL(i+1) COL(i+3) X_SWAP30 X_SWAP12 Column amplifiers A BUS_A BUS_B Reg(n) SYS_CLOCK 1/2 B A B A B Reg(n+1) Reg(n+2) Output amplifier X_SUB X_SYNC DEC(n+1) DEC(n+2) Document #: 38-05710 Rev. *C Page 6 of 40 IBIS5-B-1300 CYII5FM1300AB Figure 7. Row Structure Y_SYNC Y_SUB Y_SWAP12 Y_SWAP30 Reg(n) DEC(n+1) DEC(n+2) DEC(n+3) DEC(n+4) Reg(n+1) Reg(n+2) Reg(n+3) Reg(n+4) SRH SRH SRH SRH ROW(n+1) ROW (n+2) ROW(n+3) ROW (n+4) In normal mode, the pointer for the pixel row is shifted one at a time. When sub-sampling is enabled, Y_SYNC is activated. The Y-shift register shifts 2 succeeding bits and skips the 2 next bits. This results in pattern ’XXOOXXOO’. Activating Y_SWAP12 results in pattern ’XOXOXOXO’. Activating Y_SWAP30 results in pattern ’OXOXOXOX’. Activating both Y_SWAP12 and Y_SWAP30 results in pattern ’OOXXOOXX’. The addressable pixel range when Y-sub sampling is enabled is: 0–1, 4–5, 8–9, 12–13, … 1020–1021 corrected pixel value. This pixel value is fed to the first amplifier stage which has an adjustable gain, controlled by a 4-bit word (’GAIN [0…3]’). After this, a unity feedback amplifier buffers the signal and the signal leaves the chip. This second amplifier stage determines the maximal readout speed, that is, the bandwidth and the slew rate of the output signal. The whole amplifier chain is designed for a data rate of 40 Mpix/s (@20 pF). Output Amplifier Gain Control The output amplifier gain is controlled by a 4-bit word set in the AMPLIFIER register (see section “Amplifier Register (6:0)” on page 15). An overview of the gain settings is given in Table 8. Table 8. Overview Gain Settings DC Gain 1.37 1.62 1.96 2.33 2.76 3.50 4.25 5.20 Bits 1000 1001 1010 1011 1100 1101 1110 1111 DC Gain 6.25 7.89 9.21 11.00 11.37 11.84 12.32 12.42 Bits 0000 0001 0010 0011 0100 0101 0110 0111 Output Amplifier Architecture and Settings The output amplifier stage is user programmable for gain and offset level. Gain is controlled by 4-bit wide word; offset by a 7-bit wide word. Gain settings are on an exponential scale. Offset is controlled by a 7-bit wide DAC, which selects the offset voltage between two reference voltages (DAC_VHIGH and DAC_VLOW) on a linear scale. The amplifier is designed to match the specifications of the imager array output. This signal has a data rate of 40 MHz and is located between 1.17V and 2.95V. The output impedance of the amplifier is 260Ω. The output signal has a range between 1.17V and 2.95V, depending on the gain and offset settings of the amplifier. At unity gain and with a mid-range offset value, the amplifier outputs a signal in between 1.59V (light) and 2.70V (dark). This analog range must fit to the input range of the ADC, external or internal. The output swing in unity gain is approximately 1.11V and maximum 1.78V at the highest gain settings. Figure 8 on page 8 shows the architecture of the output amplifier. The odd and even column amplifiers sample both pixel and reset value to perform a double sampling FPN correction. You can adjust two different offsets using the on-chip DAC (7 bit): DAC_FINE and DAC_RAW. DAC_FINE is used to tune the difference between odd and even columns; DAC_RAW is used to add a general (both even and odd columns) to the FPN Document #: 38-05710 Rev. *C Setting of the DAC Reference Voltage In the output amplifier, the offset is trimmed by loading registers DACRAW_REG and DACFINE_REG. DAC_RAW is used to adjust the offset of the output amplifier and DAC_FINE is used to tune the offset between the even and odd columns. These registers are inputs for two DACs (see Figure 9 on page 8) that operate on the same resistor that is connected between pins DAC_VHIGH and DAC_VLOW. The range of the DAC is defined using a resistive division with RVHIGH, RDAC and RVLOW. The internal resistor RDAC has a value of approximately 7.88 kΩ. The recommend resistor values for both DAC_VLOW and DAC_VHIGH are 0Ω. Page 7 of 40 IBIS5-B-1300 CYII5FM1300AB Figure 8. Output Structure odd S R S R + + A 1 PXL_OUT even DAC_FINE GAIN [0…3] unity gain DAC_VHIGH DAC_FINE [6:0] DAC_RAW [6:0] DAC_VLOW DAC_RAW Figure 9. In- and External DAC Connections Analog to Digital Converter The IBIS5-B-1300 has a 10-bit flash analog digital converter running nominally at 40 Msamples/s. The ADC is electrically separated from the image sensor. Tie the input of the ADC (ADC_IN; pin 69) externally to the output (PXL_OUT1; pin 28) of the output amplifier. Table 9. ADC Specifications RDAC_VHIGH DAC_VHIGH = 3.3V RDAC DAC_VLOW = 0V external internal 7.88 kΩ internal external RDAC_VLOW Input range Quantization Nominal data rate DNL (linear conversion mode) INL (linear conversion mode) Input capacitance Power dissipation @ 40 MHz Conversion law ADC Timing 1–3V[1] 10 Bits 40 Msamples/s Typ. < 0.5 LSB Typ. < 3 LSB < 20 pF Typ. 45 mA * 3.3V = 150 mW Linear / Gamma-corrected At the rising edge of SYS_CLOCK, the next pixel is fed to the input of the output amplifier. Due to internal delays of the SYS_CLOCK signal, it takes approximately 20 ns before the output amplifier outputs the analog value of the pixel as shown in Figure 10 on page 9. The ADC converts the pixel data on the rising edge of the ADC_CLOCK, but it takes two clock cycles before this pixel data is at the output of the ADC. Figure 10 shows this pipeline delay. Note 1. The internal ADC range is typically 100 mV lower then the external applied ADC_VHIGH and ADC_VLOW voltages due to voltage drops over parasitic internal resistors Document #: 38-05710 Rev. *C Page 8 of 40 IBIS5-B-1300 CYII5FM1300AB Figure 10. ADC Timing Due to these delays, it is advisable that a variable phase difference is foreseen between the ADC_CLOCK and the SYS_CLOCK to tune the optimal sample moment of the ADC. Setting of the ADC Reference Voltages Figure 11. In- and External ADC Connections Non-linear and Linear Conversion Mode—’gamma’ Correction Figure 12 on page 10 shows the ADC transfer characteristic. The non-linear (exponential) ADC conversion is intended for gamma-correction of the images. It increases contrast in dark areas and reduces contrast in bright areas. The non-linear transfer function is given by: a*x + b*x Vin = ADC_VHIGH + ( ADC_VHIGH – ADC_VLOW ) * ---------------------------------------------a*1023 + b*1023 2 2 With: RADC_VHIGH ADC_VHIGH ~ 2.7V RADC ADC_VLOW ~ 1.8V external RADC_VLOW external internal a=5 b = 0.027 x = digital output code Electronic Shutter Types The IBIS5-B-1300 has two different shutter types: a rolling (curtain) shutter and a snapshot (synchronous) shutter. Rolling (Curtain) Shutter The name is due to the fact that the effect is similar to a curtain shutter of a SLR film camera. Although it is a pure electronic operation, the shutter seems to slide over the image. A rolling shutter is easy and elegant to implement in a CMOS sensor. Notice that in Figure 13 on page 10, there are two Y-shift registers. One of them points to the row that is currently being read out. The other shift register points to the row that is currently being reset. Both pointers are shifted by the same Y-clock and move over the focal plane. The integration time is set by the delay between both pointers. Figure 13 on page 10 graphically displays the relative shift of the integration times for different lines during the rolling shutter operation. Each line is read and reset in a sequential way. The integration time is the same for all lines, but is shifted in time. You can vary the integration time through the INT_TIME register (in number of lines). This indicates that all pixels are light sensitive at another period of time, and can cause some blurring if a fast moving object is captured. When the sensor is set to rolling shutter mode, make certain to hold the input SS_START and SS_STOP low. The internal resistor RADC has a value of approximately 585Ω. This results in the following values for the external resistors: Resistor Value (O) RADC_VHIGH RADC RADC_VLOW 360 585 1200 Note that the recommended ADC resistor values yield in a conversion of the full analog output swing at unity gain (VDARK_ANALOG < ADC_VHIGH and VLIGHT_ANALOG > ADC_VLOW). The values of the resistors depend on the value of RADC. To assure proper working of the ADC, make certain the voltage difference between ADC_VLOW and ADC_VHIGH is at least 1.0V. Document #: 38-05710 Rev. *C Page 9 of 40 IBIS5-B-1300 CYII5FM1300AB Figure 12. Linear and Non-linear ADC Conversion Characteristic Figure 13. Rolling Shutter Operation x Reset line Read line y x y R eset sequence L ine number T ime axis Frame time Integration time Document #: 38-05710 Rev. *C Page 10 of 40 IBIS5-B-1300 CYII5FM1300AB Figure 14. Synchronous Shutter Operation Line number COMMON SAMPLE&HOLD Flash could occur here COMMON RESET Time axis Integration time Snapshot (Synchronous) Shutter A synchronous (global, snapshot) shutter solves the inconvenience found in the rolling shutter. Light integration takes place on all pixels in parallel, although subsequent readout is sequential. Figure 14 shows the integration and read out sequence for the synchronous shutter. All pixels are light sensitive at the same period of time. The whole pixel core is reset simultaneously and after the integration time all pixel values are sampled together on the storage node inside each pixel. The pixel core is read out line by line after integration. Note that the integration and read out cycle is carry-out in serial; that causes that no integration is possible during read out. During synchronous shutter mode, the input pins SS_START and SS_STOP are used to start and stop the synchronous shutter. Burst Readout time Most of these signals are generated on-chip by the sequencer that uses only a few control signals. Make certain that these control signals are generated by the external system: n n n SYS_CLOCK (X-clock) defines the pixel rate Y_START pulse indicates the start of a new frame read out Y_CLOCK selects a new row and starts the row blanking sequence, including the synchronization and loading of the X-register SS_START and SS_STOP control the integration period in snapshot shutter mode. n The relative position of the pulses is determined by a number of data bits that are uploaded in internal registers through the serial or parallel interface. Internal Registers Table 10 on page 12 shows a list of the internal registers with a short description. In the next section, the registers are explained in more detail. Sequencer Figure 5 on page 4 shows a number of control signals that are needed to operate the sensor in a particular sub-sampling mode with a certain integration time, output amplifier gain, and so on. Document #: 38-05710 Rev. *C Page 11 of 40 IBIS5-B-1300 CYII5FM1300AB Table 10. Internal Registers Register Bit Name Description 0 (0000) 11:0 0 1 2 3 4 5 6 7 8 9 10 11 SEQUENCER register SHUTTER_TYPE FRAME_CAL_MODE LINE_CAL_MODE CONT_CHARGE GRAN_X_SEQ_LSB GRAN_X_SEQ_MSB GRAN_SS_SEQ_LSB GRAN_SS_SEQ_MSB KNEEPOINT_LSB KNEEPOINT_MSB KNEEPOINT_ENABLE VDDR_RIGHT_EXT NROF_PIXELS NROF_LINES INT_TIME X_REG YL_REG YR_REG IMAGE CORE register TEST_EVEN TEST_ODD X_SUBSAMPLE X_SWAP12 X_SWAP30 Y_SUBSAMPLE Y_SWAP12 Y_SWAP30 AMPLIFIER register GAIN GAIN GAIN GAIN UNITY DUAL_OUT STANDBY Default value : ’000011000100’ 1 = rolling shutter 0 = synchronous shutter 0 = fast 1 = slow 0 = fast 1 = slow 1 = ’Continuous’ precharge enabled Granularity of the X sequencer clock Granularity of the SS sequencer clock Sets reset voltage for multiple slope operation 1 = Enables multiple slope operation in synchronous shutter mode 1 = Disables circuit that generates VDDR_RIGHT voltage; this allows the application of an external voltage Number of pixels to count (maximum 1280/2) Default value : ’001001111111’ Number of lines to count Default value : ’001111111111’ Integration time Default value : ’111111111111’ X start position (maximum 1280/2) Default value : ’00000000000’ Y-left start position Default value : ’00000000000’ Y-right start position Default value : ’00000000000’ Default value : ’00000000’ Test even columns Test odd columns Enable sub-sampling in X-direction Swap columns 1-2, 5-6, … Swap columns 3-4, 7-8, … Enable sub-sampling in Y-direction Swap rows 1-2, 5-6, … Swap rows 3-4, 7-8, … Default value : ’1010000’ Output amplifier gain setting 1 (0001) 2 (0010) 3 (0011) 4 (0100) 5 (0101) 6 (0110) 7 (0111) 11:0 11:0 11:0 10:0 10:0 10:0 7:0 0 1 2 3 4 5 6 7 8 (1000) 6:0 0 1 2 3 4 5 6 1 = Amplifier in unity gain mode 1 = Activates second output 0 = Amplifier in standby mode Document #: 38-05710 Rev. *C Page 12 of 40 IBIS5-B-1300 CYII5FM1300AB Table 10. Internal Registers (continued) Register Bit Name Description 9 (1001) 10 (1010) 11 (1011) 6:0 6:0 2:0 0 1 2 DACRAW_REG DACFINE_REG ADC register TRISTATE_OUT GAMMA BIT_INV Reserved Reserved Reserved Reserved Amplifier DAC raw offset Default value : ’1000000’ Amplifier DAC fine offset Default value : ’1000000’ Default value : ’011’ 0 = Output bus in tri-state 0 = Gamma-correction on 1 = Bit inversion on output bus 12 (1100) 13 (1101) 14 (1110) 15 (1111) Detailed Description of the Internal Registers Sequencer register (7:0) 1. Shutter type (bit 0). The IBIS5-B-1300 image sensor has two shutter types: 0 = synchronous shutter. 1 = rolling shutter. 2. Output amplifier calibration (bits 1 and 2). Bits FRAME_CAL_MODE and LINE_CAL_MODE define the calibration mode of the output amplifier. During every row-blanking period, a calibration is done of the output amplifier. There are two calibration modes. The FAST mode (= 0) forces a calibration in one cycle but is not so accurate and suffers from KTC noise. The SLOW mode (= 1) only makes incremental adjustments and is noise free. Approximately 200 or more ’slow’ calibrations have the same effect as one ’fast’ calibration. Different calibration modes are set at the beginning of the frame (FRAME_CAL_MODE bit) and for every subsequent line that is read (LINE_CAL_MODE bit). The Y_START input defines the beginning of a frame, Y_CLOCK defines the beginning of a new row. 3. Continuous charge (bit 3). Some applications may require the use continuous charging of the pixel columns instead of a pre-charge on every line sample operation. Setting bit CONT_CHARGE to ’1’ activates this function. The resistor connected to pin PC_CMD controls the current level on every pixel column. 4. Internal clock granularities (bits 4, 5, 6 and 7). The system clock is divided several times on-chip. Half the system clock rate clocks the X-shift-register that controls the column/pixel readout. Odd and even pixel columns are switched to two separate buses. In the output amplifier the Note 2. Using a SYS_CLOCK of 40 MHz (25 ns period). pixel signals on the two buses are combined into one pixel stream at the same frequency as SYS_CLOCK. Use the bits GRAN_SS_SEQ_MSB (bit 7) and GRAN_SS_SEQ_LSB (bit 6) to program the clock that drives the ’snapshot’ or synchronous shutter sequencer. This way the integration time in synchronous shutter mode is a multiple of 32, 64, 128, or 256 times the system clock period. To overcome global reset issues, use the longest SS granularity (bits 6 and 7 set to '1'). Table 11. SS Sequencer Clock Granularities GRAN_SS_SEQ_MSB/ LSB SS-Sequencer Clock Integration Time Step[2] 00 01 10 11 32 x SYS_CLOCK 64 x SYS_CLOCK 128 x SYS_CLOCK 256 x SYS_CLOCK 800 ns 1.6 µs 3.2 µs 6.4 µs The clock that drives the X-sequencer is a multiple of 4, 8, 16, or 32 times the system clock. Clocking the X-sequencer at a slower rate (longer row blanking time; pixel read out speed is always equal to the SYSTEM_CLOCK) results in more signal swing for the same light conditions. Table 12. X Sequencer Clock Granularities GRAN_X_SEQ_MSB/ LSB X-Sequencer Clock Row Blanking Time[2] 00 01 10 11 4 x SYS_CLOCK 8 x SYS_CLOCK 16 x SYS_CLOCK 32 x SYS_CLOCK 3.5 µs 7 µs 14 µs 28 µs Document #: 38-05710 Rev. *C Page 13 of 40 IBIS5-B-1300 CYII5FM1300AB 5. Pixel reset knee-point for multiple slope operation (bits 8, 9, and 10). In normal (single slope) mode the pixel reset is controlled from the left side of the image core using the voltage applied on pin VDDR_LEFT as pixel reset voltage. In multiple slope operation, apply one or more variable pixel reset voltages. Bits KNEE_POINT_MSB and KNEE_POINT_LSB select the on chip-generated pixel reset voltage. Bit KNEE_POINT_ENABLE set to ’1’ switches control to the right side of the image core so the pixel reset voltage (VDDR_RIGHT), selected by bits KNEE_POINT_MSB/LSB, is used. Use bit KNEE_POINT_ENABLE only for multiple slope operation in synchronous shutter mode. In rolling shutter mode, use only the bits KNEE_POINT_MSB/LSB to select the second knee-point in dual slope operation. The actual knee-point depends on VDDH, VDDR_LEFT and VDDC applied to the sensor. Table 13. Multiple Slope Register Settings KNEE_POINT MSB/LSB ENABLE Pixel Reset Voltage Knee-point (V)VDDR_RIGHT (V) ROF_LINES Register (11:0) After the internal yl_sync is generated (start of the frame readout with Y_START), the line counter increases with each Y_CLOCK pulse until it reaches the value loaded in the NROF_LINES register and generates a LAST_LINE pulse. INT_TIME Register (11:0) Use the INT_TIME register to set the integration time of the electronic shutter. The interpretation of the INT_TIME depends on the chosen shutter type (rolling or synchronous). 1. Synchronous shutter. After the SS_START pulse is applied an internal counter counts the number of SS granulated clock cycles until it reaches the value loaded in the INT_TIME register and generates a TIME_OUT pulse. Use this TIME_OUT pulse to generate the SS_STOP pulse to stop the integration. When the INT_TIME register is used, the maximum integration time is: TINT_MAX = 212 * 256 (maximum granularity) * (40 MHZ) – 1 = 26.2 ms. You can increase this maximum time if you use an external counter to trigger SS_STOP. Ten is the minimal value that you can load into the INT_TIME register (see also “Internal clock granularities (bits 4, 5, 6 and 7).” on page 13). 2. Rolling shutter. When the Y_START pulse is applied (start of the frame readout), the sequencer generates the yl_sync pulse for the left Y-shift register (read out Y-shift register). This loads the left Y-shift register with the pointer loaded in YL_REG register. At each Y_CLOCK pulse, the pointer shifts to the next row and the integration time counter increases until it reaches the value loaded in the INT_TIME register. At that moment, the sequencer generates the yr_sync pulse for the right Y-shift register; it loads the right Y-shift register (reset Y-shift register) with the pointer loaded in YR_REG register (see Figure 15). The integration time counter is reset when the sync for the left Y-shift register is asserted. Both shift registers keep moving until the next sync is asserted (it generates the Y_START for the left Y-shift register and the sync for the right Y-shift register when the integration time counter reaches the INT_TIME value). Treg_int Difference between the left and right pointer = value set in the INT_TIME register (number of lines). The actual integration time is given by: Tint Integration time [# lines] = NROF_LINES register – INT_TIME register. 00 01 10 11 0 or 1 1 1 1 VDDR_LEFT VDDR_LEFT – 0.76 VDDR_LEFT – 1.52 VDDR_LEFT – 2.28 0 + 0.76 + 1.52 + 2.28 6. External Pixel Reset Voltage for Multiple Slope (bit 11) Setting bit VDDR_RIGHT_EXT to ’1’ disables the circuit that generates the variable pixel reset voltage and uses the voltage externally applied to pin VDDR_RIGHT as the double/multiple slope reset voltage. Setting bit VDDR_RIGHT_EXT to ’0’ allows you to monitor the variable pixel reset voltage (used for multiple slope operation) on pin VDDR_RIGHT. NROF_PIXELS Register (11:0) After the internal x_sync is generated (start of the pixel readout of a particular row), the PIXEL_VALID signal goes high. The PIXEL_VALID signal goes low when the pixel counter reaches the value loaded in the NROF_PIXEL register. Due to the fact that two pixels are read at the same clock cycle, you must divide this number by 2 (NROF_PIXELS = (width of ROI / 2) – 1). Figure 15. Synchronization of the Shift Registers in Rolling Shutter Mode Sync of left shift-register Sync of right shift-register Last line, followed by sync of left shift-register Sync Tint Line n Treg_int Document #: 38-05710 Rev. *C Page 14 of 40 IBIS5-B-1300 CYII5FM1300AB X_REG Register (10:0) The X_REG register determines the start position of the window in the X-direction. In this direction, there are 640 possible starting positions (two pixels are addressed at the same time in one clock cycle). If sub sampling is enabled, only the even pixels are set as starting position (for instance: 0, 2, 4, 6, 8… 638). YL_REG (10:0) and YR_REG (10:0) The YL_REG and YR_REG registers determine the start position of the window in the Y-direction. In this direction, there are 1024 possible starting positions. In rolling shutter mode the YL_REG register sets the start position of the read (left) pointer and the YR_REG sets the start position of the reset (right) pointer. For both shutter types YL_REG is always equal to YR_REG. Image Core Register (7:0) Bits 1:0 of the IMAGE_CORE register define the test mode of the image core. Setting 00 is the default and normal operation mode. In case the bit is set to ‘1’, the odd (bit 1) or even (bit 0) columns are tight to the reset level. If the internal ADC is used, bits 0 and 1 are used to create test pattern to test the sample moment of the ADC. If the ADC sample moment is not chosen correctly, the created test pattern is not black-white-black-etc. (IMAGE_CORE register set at 1 or 2) or black-black-white-white-black-black (IMAGE_CORE register set at 9) but grey shadings if the sensor is saturated. Bits 7:2 of the IMAGE_CORE register define the sub-sampling mode in the X-direction (bits 4:2) and in the Y-direction (bits 7:5). The sub-sampling modes and corresponding bit setting are given in Table 6 on page 6 and Table 7 on page 6. Amplifier Register (6:0) 1. GAIN (bits 3:0) The gain bits determine the gain setting of the output amplifier. They are only effective if UNITY = 0. The gains and corresponding bit setting are given in Table 8 on page 7. 2. UNITY (bit 4) In case UNITY = 1, the gain setting of GAIN is bypassed and the gain amplifier is put in unity feedback. 3. DUAL_OUT (bit 5) If DUAL_OUT = 1, the two output amplifiers are active. If DUAL_OUT = 0, the signals from the two buses are multiplexed to output PXL_OUT1 which connects to ADC_IN. The gain amplifier and output driver of the second path are put in standby. 4. STANDBY If STANDBY = 0, the complete output amplifier is put in standby. For normal use, set STANDBY to ‘1’. DAC_RAW Register (6:0) and DAC_FINE (6:0) Register These registers determine the black reference level at the output of the output amplifier. Bit setting 1111111 for the DAC_RAW register gives the highest offset voltage. Bit setting 0000000 for the DAC_RAW register gives the lowest offset voltage. Ideally, if the two output paths have no offset mismatch, the DAC_FINE register is set to 1000000. Deviation from this value is used to compensate the internal mismatch (see “Output Amplifier” on page 7). ADC Register (2:0) 1. TRISTATE_OUT (bit 0) In case TRISTATE = 0, the ADC_D outputs are in tri-state mode. TRISTATE = 1 for normal operation mode. 2. GAMMA (bit 1) If GAMMA is set to ‘1’, the ADC input to output conversion is linear; otherwise the conversion follows a 'gamma' law (more contrast in dark parts of the window, lower contrast in the bright parts). 3. BIT_INV (bit 2) If BIT_INV = 1, 0000000000 is the conversion of the lowest possible input voltage, otherwise the bits are inverted. Data Interfaces Two different data interfaces are implemented. They are selected using pins IF_MODE (pin 12) and SER_MODE (pin 6). Table 14. Serial and Parallel Interface Selection IF_MODE SER_MODE Selected interface 1 0 0 Parallel Interface X 1 0 Parallel Serial 3 Wire Serial 2 Wire. The parallel interface uses a 16-bit parallel input (P_DATA (15:0)) to upload new register values. Asserting P_WRITE loads the parallel data into the internal register of the IBIS5-B-1300 where it is decoded. (See Figure 16. P_DATA (15:12) address bits REG_ADDR (3:0); P_DATA (11:0) data bits REG_DATA (11:0)). Figure 16. Parallel Interface Timing Document #: 38-05710 Rev. *C Page 15 of 40 IBIS5-B-1300 CYII5FM1300AB Figure 17. Serial 3-Wire Interface Timing Serial 3-Wire Interface The serial 3-wire interface (or serial-to-parallel Interface) uses a serial input to shift the data in the register buffer. When the complete data word is shifted into the register buffer the data word is loaded into the internal register where it is decoded. (See Figure 17. S_DATA (15:12) address bits REG_ADDR (3:0); S_DATA (11:0) data bits REG_DATA (11:0). When S_EN is asserted the parallel data is loaded into the internal registers of the IBIS5-A-1300. The maximum tested frequency of S_DATA is 2.5 MHz.) Serial 2-Wire Interface The serial 2-wire interface is a unidirectional interface (you can only write register values to the sensor; you cannot read anything out). Therefore, the R/W_N bit (bit 8) is ignored internally. An acknowledge pulse is asserted each time a data word is received successfully. The maximum tested frequency of S_DATA is 2.5 MHz. (See Figure 18. S_DATA (15:12) address bits REG_ADDR (3:0); S_DATA (11:0) data bits REG_DATA (11:0)). Figure 18. Serial 2-Wire Interface Timing S_CLK S_DATA Start 1-7 8 9 1-7 8 9 1-7 8 9 SI2 R/ Ack address W_N Data(15:8) Ack Data(7:0) Ack Stop REG_LOAD (internal) Document #: 38-05710 Rev. *C Page 16 of 40 IBIS5-B-1300 CYII5FM1300AB Timing Diagrams Timing Requirements There are six control signals that operate the image sensor: • SS_START • SS_STOP • Y_CLOCK • Y_START • X_LOAD • SYS_CLOCK The external system generates these control signals with following time constraints to SYS_CLOCK (rising edge = active edge): TSETUP >7.5 ns THOLD > 7.5 ns It is important that these signals are free of any glitches. Figure 19 shows a recommended schematic for generating the basic signals and to avoid any timing problems. Figure 19. Recommended Schematic for Generating Basic Signals SS_START SS_STOP Y_CLOCK Y_START X_LOAD Synchronous Shutter: Single Slope Integration SS_START and SS_STOP must change on the falling edge of the SYS_CLOCK (Tsetup and Thold > 7.5 ns). Make certain that the pulse width of both signals is a minimum of 1 SYS_CLOCK cycle. As long as SS_START or SS_STOP are asserted, the sequencer stays in a suspended state. (See Figure 21.) T1—Time counted by the integration timer until the value of INT_TIME register is reached. The integration timer is clocked by the granulated SS-sequencer clock. T2—TIME_OUT signal stays SS-sequencer clock period. high for one granulated T3—There are no constraints for this time. Use the TIME_OUT signal to trigger the SS_STOP pin (or use an external counter to trigger SS_STOP); you cannot tie both signals together. T4—During this time, the SS-sequencer applies the control signals to reset the image core and start integration. This takes four granulated SS-sequencer clock periods. The integration time counter starts counting at the first rising edge after the falling edge of SS_START. T5—The SS-sequencer puts the image core in a readable state. It takes two granulated SS-sequencer clock periods. Tint—The ’real’ integration or exposure time. FF SYS_CLOCK_N SYS_CLOCK Figure 20. Relative Timing of the 5 Sequencer Control Signal Figure 21. Synchronous Shutter: Single Slope Integration Document #: 38-05710 Rev. *C Page 17 of 40 IBIS5-B-1300 CYII5FM1300AB Figure 22. Synchronous Shutter: Pixel Read Out Synchronous Shutter: Pixel Readout Basic Operation Y_START and Y_CLOCK must change on the falling edge of the SYS_CLOCK (Tsetup and Thold > 7.5 ns). Make certain that the pulse width is a minimum of one clock cycle for Y_CLOCK and three clock cycles for Y_START. As long as Y_CLOCK is applied, the sequencer stays in a suspended state. (See Figure 22.) T1—Row blanking time: During this period, the X-sequencer generates the control signals to sample the pixel signal and pixel reset levels (double sampling fpn-correction), and starts the readout of one line. The row blanking time depends on the granularity of the X-sequencer clock (see Table 15). Table 15. Row Blanking Time as Function of X-Sequencer Granularity Granularity NGRAN T1(µs) GRAN_X_SEQ = 35 x NGRAN x TSYS_CLOCK MSB/LSB T2—Pixels counted by pixel counter until the value of NROF_PIXELS register is reached. PIXEL_VALID goes high when the internal X_SYNC signal is generated, in other words when the readout of the pixels is started. PIXEL_VALID goes low when the pixel counter reaches the value loaded in the NROF_PIXELS register (after a complete row read out). T3—LAST_LINE goes high when the line counter reaches the value loaded in the NROF_LINES register and stays high for one line period (until the next falling edge of Y-CLOCK). On Y_START the left Y-shift-register of the image core is loaded with the YL-pointer that is loaded in to register YL_REG. Pixel Output The pixel signal at the PXL_OUT1 output becomes valid after five SYS_CLOCK cycles when the internal X_SYNC (= start of PIXEL_VALID output or external X_LOAD pulse) pulse is asserted. (See Figure 23.) T1—Row blanking time (see Table 15). T2—5 SYS_CLOCK cycles. T3—Time for new X-pointer position upload in X_REG register (see “Windowing in X-direction” on page 20 for more details). x4 x8 x 16 x 32 140 x TSYS_CLOCK = 3.5 280 x TSYS_CLOCK = 7.0 560 x TSYS_CLOCK = 14.0 1120 x TSYS_CLOCK = 28.0 00 01 10 11 Figure 23. Pixel Output Document #: 38-05710 Rev. *C Page 18 of 40 IBIS5-B-1300 CYII5FM1300AB Synchronous Shutter: Multiple Slope Integration Figure 24. Multiple Slope Integration Use up to four different pixel reset voltages during multiple slope operation in synchronous shutter mode. This is done by uploading new values to register bits KNEEPOINT_MSB/LSB/ENABLE before a new SS_START pulse is applied. Set bit KNEEPOINT_ENABLE high to do a pixel reset with a lower voltage. Set bits KNEEPOINT_MSB/LSB/ENABLE back to ‘0’ before the SS_STOP pulse is applied. Every time an SS_START pulse is applied, the integration time counter is reset. Table 16. Multiple Slope Register Settings Kneepoint MSB/LSB Enable Upload the register after time Tstable, otherwise, the change affects the SS-sequencer resulting in a bad pixel reset. Tstable depends on the granularity of the SS-sequencer clock (see Table 17). Table 17. Tstable for Different Granularity Settings Granularity Tstable (µs) NGRAN = 5 x NGRAN x TSYS_CLOCK GRAN_SS_SEQ MSB/LSB x 32 x 64 x 128 x 256 160 x TSYS_CLOCK = 4 320 x TSYS_CLOCK = 8 640 x TSYS_CLOCK = 16 1280 x TSYS_CLOCK = 32 00 01 10 11 Initial Setup 1st Register Upload 2nd Register Upload 3th Register Upload 4th Register Upload 00 01 10 11 00 0 1 1 1 0 Tupload depends on the interface mode used to upload the registers. Table 18. Tupload for Different Interface Modes Interface Mode Tupload (µs) Parallel Serial 3-wire 1 8 Document #: 38-05710 Rev. *C Page 19 of 40 IBIS5-B-1300 CYII5FM1300AB Rolling Shutter Operation Figure 25. Rolling Shutter Operation The integration of the light in the image sensor is done during readout of the other lines. The only difference with synchronous shutter is that the TIME_OUT pin is used to indicate when the Y_SYNC pulse for the right Y-shift-register (reset Y-shift register) is generated. This loads the right Y-shift-register with the pointer loaded in register YR_REG. The Y_SYNC pulse for the left Y-shift register (read Y-shift register) is generated with Y_START. The INT_TIME register defines how many lines to count before the Y_SYNC of the right Y-shift-register is generated, hence defining the integration time. See also “INT_TIME Register (11:0)” on page 14 for a detailed description of the rolling shutter operation. Tint Integration time [# lines] = register(NROF_LINES) – register(INT_TIME) Note For normal operation the values of the YL_REG and YR_REG registers are equal. Windowing in X-direction An X_LOAD pulse overrides the internal X_SYNC signal, loading a new X-pointer (stored in the X_REG register) into the X-shift-register. The X_LOAD pulse has to appear on the falling edge of SYS_CLOCK and has to remain high for two SYS_CLOCK cycles overlapping two rising edges of SYS_CLOCK. The new X-pointer is loaded on one of the two rising edges of SYS_CLOCK. The available time to upload the register is Tload; it is defined from the previous register load to the rising edge of X_LOAD. It depends on the settling time of the register and the X-decoder. The actual time to load the register itself depends on the interface mode that is used. The parallel interface is the fastest. Table 19. Tload for Different Interfaces Interface Mode Tload (µs) Parallel interface Serial 3 Wire 1 16 (about 40 SYS_CLOCK cycles) (at 2.5 MHz data rate) Figure 26. Windowing in the X-Direction Document #: 38-05710 Rev. *C Page 20 of 40 IBIS5-B-1300 CYII5FM1300AB Windowing in Y-direction Figure 27. Windowing in the Y-Direction Reapply the Y_START pulse after loading a new Y-pointer value into the YL_REG and YR_REG registers to load a new Y-pointer into the Y-shift-register. Every time a Y_START pulse appears, a frame calibration of the output amplifier occurs. After power on of the image sensor, apply SYS_RESET for a minimum of five SYS_CLOCK periods to ensure a proper reset of the on-chip sequencer and timing circuitry. All internal registers are set to ‘0’ after SYS_RESET is applied. Since all the IBIS5-B-1300 control signals are active high, apply a low level (before SYS_RESET occurs) to these pins at start up to avoid latch up. Initialization (Start-Up Behavior) To avoid any high current consumption at start-up, apply the SYS_CLOCK signal as soon as possible after or even before power on of the image sensor. Document #: 38-05710 Rev. *C Page 21 of 40 IBIS5-B-1300 CYII5FM1300AB Pin List The IBIS5-B-1300 image sensor is packaged in a leadless ceramic carrier (LCC package). Table 20 lists all the pins and their functions. There are 84 pins total. Table 20. Pin List[3, 4, 5] Pin Pin Name Pin Type Pin Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 P_DATA P_WR S_CLK S_DATA S_EN SER_MODE VDDC VDDA GNDA GNDD VDDD IF_MODE DEC_CMD Y_START Y_CLOCK LAST_LINE X_LOAD SYS_CLOCK PXL_VALID SS_START SS_STOP TIME_OUT Input Input Input Input Input Input Supply Supply Ground Ground Supply Input Input Input Input Output Input Input Output Input Input Output Digital input. Data parallel interface. Digital input (active high). Parallel write. Digital input. Clock signal of serial interface. Digital input/output. Data of serial interface. Digital input (active low). Enable of serial 3-wire interface. Digital input. Serial mode enable (1 = Enable serial 3-wire, 0 = Enable serial 2-wire). Analog supply voltage. Supply voltage of the pixel core [3.3V]. Analog supply voltage. Analog supply voltage of the image sensor [3.3V]. Analog ground. Analog ground of the image sensor. Digital ground. Digital ground of the image sensor. Digital supply voltage. Digital supply voltage of the image sensor [3.3V]. Digital input. Interface mode (1 = parallel; 0 = serial). Analog input. Biasing of decoder stage. Connect to VDDA with R = 50 kΩ and decouple with C = 100 nF to GNDA. Digital input (active high). Start frame read out. Digital input (active high). Line clock. Digital output. Generates a high level when the last line is read out. Digital input (active high). Loads new X-position during read out. Digital input. System (pixel) clock (40 MHz). Digital output. Generates high level during pixel read out. Digital input (active high). Start synchronous shutter operation. Digital input (active high). Stop synchronous shutter operation. Digital output. Synchronous shutter: pulse when timeout reached. It is used to trigger SS_STOP; do not tie both signals together. Rolling shutter: pulse when second Y-sync appears. Digital input (active high). Global system reset. Digital input (active high). Enables electrical black in output amplifier. Digital output. Diagnostic end-of-scan of X-register. Analog reference input. Biasing of DAC for output dark level. Use this to set the output range of DAC. Default: Connect to VDDA with R = 0Ω. Analog reference input. Biasing of DAC for output dark level. Use this to set the output range of DAC. Default: Connect to GND A with R = 0Ω. Analog output. Analog pixel output 1. 23 24 25 26 SYS_RESET EL_BLACK EOSX DAC_VHIGH Input Input Output Input 27 DAC_VLOW Input 28 PXL_OUT1 Output Notes 3. You can connect all pins with the same name together. 4. All digital input are active high (unless mentioned otherwise). 5. Tie all digital inputs that are not used to GND (inactive level). Document #: 38-05710 Rev. *C Page 22 of 40 IBIS5-B-1300 CYII5FM1300AB Table 20. Pin List[3, 4, 5] (continued) Pin Pin Name Pin Type Pin Description 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PXL_OUT2 AMP_CMD COL_CMD PC_CMD VDDD GNDD GNDA VDDA VDDC P_DATA P_DATA P_DATA P_DATA P_DATA P_DATA P_DATA P_DATA SI2_ADDR SI2_ADDR SI2_ADDR SI2_ADDR SI2_ADDR GNDAB VDDR_RIGHT ADC_VLOW ADC_GNDA ADC_VDDA ADC_GNDD ADC_VDDD ADC_CLOCK ADC_OUT ADC_OUT ADC_OUT ADC_OUT ADC_OUT ADC_OUT Output Input Input Input Supply Ground Ground Supply Supply Input Input Input Input Input Input Input Input Input Input Input Input Input Supply Supply Input Ground Supply Ground Supply Input Output Output Output Output Output Output Analog output. Analog pixel output 2. Leave not connected if not used. Analog input. Biasing of the output amplifier. Connect to VDDA with R = 50 kΩ and decouple with C = 100 nF to GNDA. Analog input. Biasing of the column amplifiers. Connect to VDDA with R = 50 kΩ and decouple with C = 100 nF to GNDA. Analog input. Pre-charge bias. Connect to VDDA with R = 25 kΩ and decouple with C = 100 nF to GNDA. Digital supply. Digital supply voltage of the image sensor [3.3V]. Digital ground. Digital ground of the image sensor. Analog ground. Analog ground of the image sensor. Analog supply voltage. Analog supply voltage of the image sensor [3.3V]. Analog supply voltage. Supply voltage of the pixel core [3.3V]. Digital input. Data parallel interface (LSB). Digital input. Data parallel interface. Digital input. Data parallel interface. Digital input. Data parallel interface. Digital input. Data parallel interface. Digital input. Data parallel interface. Digital input. Data parallel interface. Digital input. Data parallel interface. Digital input. Sets I2C address. Digital input. Sets I2C address. Digital input. Sets I2C address. Digital input. Sets I2C address. Digital input. Sets I2C address. Analog supply voltage. Anti-blooming ground. Analog supply voltage. Variable reset voltage (multiple slope operation). Decouple with 1 µF to GNDA. Analog reference input. ADC low reference voltage.Default: Connect to GNDA with R = 1200Ω and decouple with C = 100 nF to GNDA. Analog ground. ADC analog ground. Analog supply voltage. ADC analog supply voltage [3.3V]. Digital ground. ADC digital ground. Digital supply voltage. ADC digital supply voltage [3.3V]. Digital input. ADC clock (40 MHz). Digital output. ADC data output (MSB). Digital output. ADC data output. Digital output. ADC data output. Digital output. ADC data output. Digital output. ADC data output. Digital output. ADC data output. Document #: 38-05710 Rev. *C Page 23 of 40 IBIS5-B-1300 CYII5FM1300AB Table 20. Pin List[3, 4, 5] (continued) Pin Pin Name Pin Type Pin Description 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 ADC_OUT ADC_OUT ADC_OUT ADC_OUT ADC_IN ADC_CMD ADC_VDDD ADC_GNDA ADC_GNDD ADC_VDDA ADC_VHIGH VDDR_LEFT VDDH P_DATA P_DATA P_DATA P_DATA P_DATA P_DATA P_DATA Output Output Output Output Input Input Supply Ground Ground Supply Input Supply Supply Input Input Input Input Input Input Input Digital output. ADC data output. Digital output. ADC data output. Digital output. ADC data output. Digital output. ADC data output (LSB). Analog input. ADC analog input. Analog input. Biasing of the input stage of the ADC. Connect to ADC_VDDA with R = 50 kΩ and decouple with C = 100 nF to ADC_GNDA. Digital supply voltage. ADC digital supply voltage [3.3V]. Analog ground. ADC analog ground. Digital ground. ADC digital ground. Analog supply voltage. ADC analog supply voltage [3.3V]. Analog reference input. ADC high reference volt age.Default: Connect to VDDA with R = 360Ω and decouple with C = 100 nF to GNDA. Analog supply voltage. High reset level [4.5V]. Analog supply voltage. High supply voltage for HOLD switches in the image core [4.5V] Digital input. Data parallel interface (MSB). Digital input. Data parallel interface. Digital input. Data parallel interface. Digital input. Data parallel interface. Digital input. Data parallel interface. Digital input. Data parallel interface. Digital input. Data parallel interface. Document #: 38-05710 Rev. *C Page 24 of 40 IBIS5-B-1300 CYII5FM1300AB Specifications General Specifications. Table 21. General Specifications Parameter Specification Remarks Electro-Optical Specifications Overview Table 22. Electro-Optical Specifications Parameter Specification Remarks Pixel architecture 4T-pixel High fill factor square pixels (based on the high fill factor active pixel sensor technology of Cypress). Patents pending. The resolution and pixel size results in a 2/3" optical format. Using a 40 MHz system clock. • Continuous imaging. • Triggered global shutter with integration and readout separate in time. FPN (local) PRNU (local) Conversion gain Output signal amplitude Saturation charge Sensitivity (peak)