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THIS SPEC IS OBSOLETE
Spec No:
Spec Title:
002-08364
MB39C015 2CH DC/DC CONVERTER IC WITH
PFM/PWM SYNCHRONOUS RECTIFICATION
Replaced by: NONE
MB39C015
2 ch DC/DC Converter IC with
PFM/PWM Synchronous Rectification
Description
The MB39C015 is a current mode type 2-channel DC/DC converter IC built-in voltage detection, synchronous rectifier, and down
conversion support. The device is integrated with a switching FET, oscillator, error amplifier, PWM control circuit, reference voltage
source, and voltage detection circuit.
External inductor and decoupling capacitor are needed only for the external component.
As combining with external parts enables a DC/DC converter with a compact and high load response characteristic, this is suitable
as the built-in power supply for such as mobile phone/PDA, DVDs, and HDDs.
Features
■
High efficiency
: 96% (Max)
■
Output current (DC/DC)
: 800 mA/ch (Max)
■
Input voltage range
: 2.5 V to 5.5 V
■
Operating frequency
: 2.0 MHz (Typ)
■
No flyback diode needed
■
Low dropout operation
■
Built-in high-precision reference voltage generator : 1.30 V ± 2%
■
Consumption current in shutdown mode
: 1 µA or less
■
Built-in switching FET
: P-ch MOS 0.3 Ω (Typ) N-ch MOS 0.2 Ω (Typ)
■
High speed for input and load transient response in the current mode
■
Over temperature protection
■
Packaged in a compact package
: For 100% on duty
: QFN-24
Applications
■
Flash ROMs
■
MP3 players
■
Electronic dictionary devices
■
Surveillance cameras
■
Portable GPS navigators
■
DVD drives
■
IP phones
■
Network hubs
■
Mobile phones etc.
Cypress Semiconductor Corporation
Document Number: 002-08364 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 10, 2018
MB39C015
Contents
Description ............................................................................. 1
Features .................................................................................. 1
Applications ........................................................................... 1
Contents ................................................................................. 2
1. Pin Assignment ................................................................ 3
2. Pin Descriptions ............................................................... 4
3. I/O Pin Equivalent Circuit Diagram ................................. 5
4. Block Diagram .................................................................. 6
5. Function of Each Block .................................................... 8
6. Absolute Maximum Ratings .......................................... 10
7. Recommended Operating Conditions .......................... 11
8. Electrical Characteristics ............................................... 12
9. Test Circuit For Measuring Typical Operating
Characteristics ................................................................. 14
10. Application Notes ......................................................... 15
10.1 Selection of Components ...................................... 15
Document Number: 002-08364 Rev. *D
10.2 Output Voltage Setting ......................................... 16
10.3 About Conversion Efficiency ................................. 16
10.4 Power Dissipation and Heat Considerations ......... 17
10.5 XPOR Threshold Voltage Setting [VPORH,
VPORL] ....................................................................... 18
10.6 Transient Response .............................................. 19
10.7 Board Layout, Design Example ............................. 20
11. Example Of Standard Operation Characteristics ...... 21
12. Application Circuit Examples ...................................... 29
13. Application Circuit Examples ...................................... 30
14. Usage Precautions ....................................................... 32
15. Ordering Information .................................................... 32
16. RoHS Compliance Information .................................... 32
17. Package Dimension ...................................................... 33
Document History ................................................................ 34
Sales, Solutions, and Legal Information ........................... 35
Page 2 of 35
MB39C015
1. Pin Assignment
(Top View)
LX2 DGND2 DGND2 DGND1 DGND1 LX1
18
17
16
15
14
13
DVDD2
19
12
DVDD1
DVDD2
20
11
DVDD1
OUT2
21
10
OUT1
MODE2
22
9
MODE1
VREFIN2
23
8
VREFIN1
XPOR
24
7
VDET
1
2
CTLP
CTL2
3
CTL1
4
AGND
5
6
AVDD
VREF
(WNN024)
Document Number: 002-08364 Rev. *D
Page 3 of 35
MB39C015
2. Pin Descriptions
Pin No.
Pin Name
I/O
1
CTLP
I
Voltage detection circuit block control input pin.
(L : Voltage detection function stop, H : Normal operation)
2/3
CTL2/CTL1
I
DC/DC converter block control input pin.
(L : Shut down, H : Normal operation)
4
AGND
–
Control block ground pin.
5
AVDD
–
Control block power supply pin.
6
VREF
O
Reference voltage output pin.
7
VDET
I
Voltage detection input pin.
8/23
VREFIN1/VREFIN2
I
Error amplifier (Error Amp) non-inverted input pin.
9/22
MODE1/MODE2
I
Use pin at L level or leave open.
10/21
OUT1/OUT2
I
Output voltage feedback pin.
11, 12/
19, 20
DVDD1/DVDD2
–
Drive block power supply pin.
13/18
LX1/LX2
O
Inductor connection output pin.
High impedance during shut down.
14, 15/
16, 17
DGND1/DGND2
–
Drive block ground pin.
24
XPOR
O
VDET circuit output pin.
Connected to an N-ch MOS open drain circuit.
Document Number: 002-08364 Rev. *D
Description
Page 4 of 35
MB39C015
3. I/O Pin Equivalent Circuit Diagram
VDD
VDD
∗
LX1, LX2
VREF
∗
GND
GND
VDD
∗
∗
VREFIN1,
VREFIN2,
VDET
OUT1, OUT2
∗
∗
GND
VDD
CTL1, CTL2, CTLP
∗
GND
VDD
XPOR
∗
MODE1,
MODE2
∗
GND
∗
GND
Document Number: 002-08364 Rev. *D
* : ESD Protection device
Page 5 of 35
MB39C015
4. Block Diagram
VIN
AVDD
DVDD1
11, 12
5
CTL1
DVDD2
19, 20
3
ON/OFF
OUT1
10
×3
−
ERR
Amplifier
DVDD1
+
IOUT
Comparator
VREFIN1
8
DAC
PWM
LX1
13
Logic
VOUT1
Control
MODE1
9
GND
VIN
VIN
CTLP
VDET
VREF
CTL2
OUT2
1
7
−
ON/OFF
24
XPOR
1.30 V
6
+
VREF
2
21
ON/OFF
×3
−
ERR
Amplifier
DVDD2
+
IOUT
Comparator
VREFIN2
23
PWM
LX2
18
Logic
MODE2
22
GND
Control
4
AGND
Document Number: 002-08364 Rev. *D
VOUT2
14, 15
DGND1
16, 17
DGND2
Page 6 of 35
MB39C015
■
Current Mode
❐ Original voltage mode type :
Stabilize the output voltage by comparing two items below and on-duty control.
• Voltage (VC) obtained through negative feedback of the output voltage by Error Amp
• Reference triangular wave (VTRI)
❐ Current mode type :
Instead of the triangular wave (VTRI), the voltage (VIDET) obtained through I-V conversion of the sum of currents that flow in the
oscillator (rectangular wave generation circuit) and SW FET is used.
Stabilize the output voltage by comparing two items below and on-duty control.
• Voltage (VC) obtained through negative feedback of the output voltage by Error Amp
• Voltage (VIDET) obtained through I-V conversion of the sum of current that flow in the oscillator (rectangular wave generation
circuit) and SW FET
Voltage mode type model
Current mode type model
VIN
VIN
Oscillator
Vc
−
VTRI
+
Vc
S
+
R
VIDET
Vc
−
Q
SR-FF
VIDET
VTRI
Vc
ton
toff
toff
ton
Note : The above models illustrate the general operation and an actual operation will be preferred in the IC.
Document Number: 002-08364 Rev. *D
Page 7 of 35
MB39C015
5. Function of Each Block
■
PWM Logic Control Circuit
The built-in P-ch and N-ch MOS FETs are controlled for synchronization rectification according to the frequency (2.0 MHz) oscillated
from the built-in oscillator (square wave oscillation circuit).
■
IOUT Comparator Circuit
This circuit detects the current (ILX) which flows to the external inductor from the built-in P-ch MOS FET. By comparing VIDET obtained
through I-V conversion of peak current IPK of ILX with the Error Amp output, the built-in P-ch MOS FET is turned off via the PWM Logic
Control circuit.
■
Error Amp Phase Compensation Circuit
This circuit compares the output voltage to reference voltages such as VREF. This IC has a built-in phase compensation circuit that
is designed to optimize the operation of this IC.This needs neither to be considered nor addition of a phase compensation circuit and
an external phase compensation device.
■
VREF Circuit
A high accuracy reference voltage is generated with BGR (bandgap reference) circuit. The output voltage is 1.30 V (Typ).
■
Voltage Detection (VDET) Circuit
The voltage detection circuit monitors the voltage at the VDET pin. Normally, use the XPOR pin through pull-up with an external
resistor. When the VDET pin voltage reaches 0.6 V, it reaches the H level.
Timing Chart Example : (XPOR Pin Pulled Up to VIN)
VIN
VUVLO
CTLP
VTHHPR
VTHLPR
VDET
XPOR
VUVLO : UVLO threshold voltage
VTHHPR, VTHLPR : XPOR threshold voltage
■
Protection Circuit
This IC has a built-in over-temperature protection circuit. The over-temperature protection circuit turns off both N-ch and P-ch switching
FETs when the junction temperature reaches + 135 °C . When the junction temperature comes down to + 110 °C , the switching FET
is returned to the normal operation. Since the PWM control circuit of this IC is in the control method in current mode, the current peak
value is also monitored and controlled as required.
Document Number: 002-08364 Rev. *D
Page 8 of 35
MB39C015
■
Function Table
Input
MODE
CTL1
Shutdown mode
Operating mode
CTL2
Output
CTLP
L
CH1 Function
CH2 Function
VDET
Function
Stopped
H
L
L
Operation
Stopped
Stopped
L
H
L
Stopped
Operation
Stopped
L
L
H
Stopped
Stopped
Operation
H
H
L
Operation
Operation
Stopped
L
H
H
Stopped
Operation
Operation
H
L
H
Operation
Stopped
Operation
H
Document Number: 002-08364 Rev. *D
VREF
Function
Outputs 1.3 V
Operation
Page 9 of 35
MB39C015
6. Absolute Maximum Ratings
Parameter
Symbol
Condition
Power supply voltage
VDD
AVDD = DVDD1 = DVDD2
Signal input voltage
VISIG
OUT1/OUT2 pins
CTLP, CTL1/CTL2,
MODE1/MODE2 pins
VREFIN1/VREFIN2 pins
VDET pin
XPOR pull-up voltage
VIXPOR
XPOR pin
Rating
Unit
Min
Max
−0.3
−0.3
−0.3
+6.0
VDD + 0.3
VDD + 0.3
−0.3
−0.3
−0.3
−0.3
VDD + 0.3
V
V
VDD + 0.3
+6.0
VDD + 0.3
V
LX voltage
VLX
LX1/LX2 pins
LX Peak current
IPK
ILX1/ILX2
–
1.8
Power dissipation
PD
Ta ≤ +25 °C
–
3125* , * , *
–
1563* , * , *
–
1250*1, *2, *3
–
625* , * , *
Ta = +85 °C
Operating ambient
temperature
Storage temperature
A
1
2
1
1
V
2
2
mW
3
4
mW
4
Ta
–
−40
+85
°C
TSTG
–
−55
+125
°C
*1
: Power dissipation value between + 25 °C and + 85 °C is obtained by connecting these two points with straight line.
*2
: When mounted on a four-layer epoxy board of 11.7 cm × 8.4 cm
*3
: Connection at exposure pad with thermal via. (Thermal via 9 holes)
*4
: Connection at exposure pad, without a thermal via.
Notes:
• The use of negative voltages below − 0.3 V to the AGND, DGND1, and DGND2 pin may create parasitic
transistors on LSI lines, which can cause abnormal operation.
• This device can be damaged if the LX1 pin and LX2 pin are short-circuited to AVDD and DVDD1/DVDD2,
or AGND and DGND1/DGND2.
WARNING:
Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-08364 Rev. *D
Page 10 of 35
MB39C015
7. Recommended Operating Conditions
Parameter
Power supply voltage
VREFIN voltage
CTL voltage
Symbol
VDD
ILX
VREF output current
IROUT
Value
Unit
Min
Typ
Max
2.5
3.7
5.5
V
0.15
–
1.30
V
CTLP, CTL1, CTL2
0
–
5.0
V
ILX1/ILX2
–
–
800
mA
2.5 V ≤ AVDD = DVDD1 = DVDD2 <
3.0 V
–
–
0.5
mA
3.0 V ≤ AVDD = DVDD1 = DVDD2 ≤
5.5 V
–
–
1
AVDD = DVDD1 = DVDD2
VREFIN
VCTL
LX current
Condition
–
XPOR current
IPOR
–
–
–
1
mA
Inductor value
L
–
–
2.2
–
µH
Note :
The output current from this device has a situation to decrease if the power supply voltage (VIN) and the DC/DC converter output
voltage (VOUT) differ only by a small amount. This is a result of slope compensation and will not damage this device.
WARNING:
The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Document Number: 002-08364 Rev. *D
Page 11 of 35
MB39C015
8. Electrical Characteristics
(Ta = +25 °C , AVDD = DVDD1 = DVDD2 = 3.7 V, VOUT1/VOUT2 setting value = 2.5 V, MODE1/MODE2 = 0 V)
Value
SymParameter
Pin No.
Condition
Unit
bol
Min
Typ
Max
DC/DC
converter
block
Protection
circuit block
Voltage
detection
circuit block
Input current
IREFIN
8, 23
VREFIN = 0.15 V to 1.3 V
− 100
0
+ 100
nA
Output voltage
VOUT
10, 21
VREFIN = 0.833 V,
OUT = −100 mA
2.45
2.50
2.55
V
Input stability
LINE
2.5 V ≤ AVDD = DVDD1 =
DVDD2 ≤ 5.5 V*1
–
–
10
mV
Load stability
LOAD
–
–
10
mV
OUT pin input
impedance
ROUT
−100 mA ≥ OUT ≥
−800 mA
OUT = 2.0 V
0.6
1.0
1.5
MΩ
Output shorted to GND
0.9
1.2
1.7
A
1.6
2.0
2.4
MHz
–
45
80
µs
–
− 10*
–
mV
LX Peak current
Oscillation
frequency
IPK
13, 18
fosc
–
C1/C2 = 4.7 µF, OUT =
0 A, OUT1/OUT2 : 0 → 90%
VOUT
Rise delay time
tPG
2, 3,
10, 21
SW NMOS-FET
OFF voltage
VNOFF
13, 18
SW PMOS-FET ON
resistance
RONP
LX1/LX2 = −100 mA
–
0.30
0.48
Ω
SW NMOS-FET ON
resistance
RONN
LX1/LX2 = −100 mA
–
0.20
0.42
Ω
LX leak current
ILEAKM
0 ≤ LX ≤ VDD*2
–
VDD = 5.5 V, 0 ≤ LX ≤ VDD*
+ 135*
+ 8.0
+ 16.0
+ 160*
µA
ILEAKH
− 1.0
− 2.0
+ 120*
+ 95*
+ 110*
+ 125*
°C
2.17
2.30
2.43
V
2.03
2.15
2.27
V
–
0.08
0.15
0.25
V
–
575
600
625
mV
558
583
608
mV
–
17
–
mV
XPOR = 25 µA
–
–
0.1
V
XPOR = 5.5 V
–
–
1.0
µA
Overheating
protection (Junction
Temp.)
TOTPH
UVLO threshold
voltage
VTHHUV
UVLO
hysteresis width
VHYSUV
XPOR threshold
voltage
VTHHPR
XPOR
hysteresis width
VHYSPR
–
2
–
–
TOTPL
VTHLUV
5, 11,
12, 19, 20
–
7
VTHLPR
XPOR output
voltage
VOL
XPOR output
current
IOH
–
24
–
µA
°C
* : Standard design value
Document Number: 002-08364 Rev. *D
Page 12 of 35
MB39C015
(Ta = +25 °C , AVDD = DVDD1 = DVDD2 = 3.7 V, VOUT1/VOUT2 setting value = 2.5 V, MODE1/MODE2 = 0 V)
Value
Parameter
Symbol
Pin No.
Condition
Unit
Min
Typ
Max
Control block
Reference
voltage block
CTL threshold
voltage
VTHHCT
–
0.55
0.95
1.45
V
–
0.40
0.80
1.30
V
–
–
1.0
µA
1.274
1.300
1.326
V
VREF = −1.0 mA
–
–
20
mV
IVDD1
CTLP/CTL1/CTL2 = 0 V
State of all circuits OFF*3
–
–
1.0
µA
IVDD1H
CTLP/CTL1/CTL2 = 0 V,
VDD = 5.5 V
State of all circuits OFF*3
–
–
1.0
µA
IVDD31
1. CTLP = 0 V, CTL1 = 3.7 V,
CTL2 = 0 V
2. CTLP = 0 V, CTL1 = 0 V,
CTL2 = 3.7 V
OUT = 0 A
–
3.5
10
mA
CTLP = 0 V, CTL1/CTL2 =
3.7 V, OUT = 0 A
–
7.0
20.0
mA
VTHLCT
CTL pin
input current
IICTL
VREF voltage
VREF
VREF Load
stability
Shut down
power supply
current
Power supply current
(DC/DC mode)
1, 2, 3
0 V ≤ CTLP/CTL1/CTL2 ≤
3.7 V
6
LOADREF
General
IVDD32
5, 11,
12, 19,
20
VREF = 0 mA
Power supply current
(voltage detection
mode)
IVDD5
CTLP = 3.7 V,
CTL1/CTL2 = 0 V,
–
15
24
µA
Power-on
invalid current
IVDD
1. CTL1 = 3.7 V, CTL2 = 0 V
2. CTL1 = 0 V, CTL2 = 3.7 V
VOUT1/VOUT2 = 90%
OUT = 0 A*4
–
1000
2000
µA
*1 : The minimum value of AVDD = DVDD1 = DVDD2 is the 2.5 V or VOUT setting value + 0.6 V, whichever is higher.
*2 : The + leak at the LX1 pin and LX2 pin includes the current of the internal circuit.
*3 : Sum of the current flowing into the AVDD, the DVDD1, and the DVDD2 pins.
*4 : Current consumption based on 100% ON-duty (High side FET in full ON state). The SW FET gate drive current is not included
because the device is in full ON state (no switching operation). Also the load current is not included.
Document Number: 002-08364 Rev. *D
Page 13 of 35
MB39C015
9. Test Circuit For Measuring Typical Operating Characteristics
MB39C015
VDD
VDD
SW
CTL1/CTL2
C2
4.7 μF
R1
1 MΩ
AVDD
MODE1/MODE2
R3-1
20 kΩ
R3-2
150 kΩ
R4
300 kΩ
VIN
DVDD1/DVDD2
R5
510 kΩ
R6
100 kΩ
C6
0.1 μF
VREF
LX1/LX2
VDET
OUT1/OUT2
C3
4.7 μF
L1
2.2 μH
VOUT1/
VOUT2
IOUT
C1
4.7 μF
DGND1/DGND2
VREFIN1/VREFIN2
AGND
GND
Output voltage = VREFIN × 3.01
Component
Specification
Vendor
Part Number
R1
1 MΩ
KOA
RK73G1JTTD D 1 MΩ
R3-1
R3-2
20 kΩ
150 kΩ
SSM
SSM
RR0816-203-D
RR0816-154-D
R4
300 kΩ
SSM
RR0816-304-D
R5
510 kΩ
KOA
RK73G1JTTD D 510 kΩ
R6
100 kΩ
SSM
RR0816-104-D
C1
4.7 µF
TDK
C2012JB1A475K
C2
4.7 µF
TDK
C2012JB1A475K
C3
0.1 µF
TDK
C1608JB1E104K
C6
0.1 µF
TDK
C1608JB1H104K
L1
2.2 µH
TDK
VLF4012AT-2R2M
Remarks
VOUT1/VOUT2 = 2.5 V
Setting
For adjusting slow start time
Note : These components are recommended based on the operating tests authorized.
TDK : TDK Corporation
SSM : SUSUMU Co., Ltd
KOA : KOA Corporation
Document Number: 002-08364 Rev. *D
Page 14 of 35
MB39C015
10. Application Notes
10.1 Selection of Components
■
Selection of an External Inductor
Basically it dose not need to design inductor. This IC is designed to operate efficiently with a 2.2 µH inductor.
The inductor should be rated for a saturation current higher than the LX peak current value during normal operating conditions, and
should have a minimal DC resistance. (100 mΩ or less is recommended.)
LX peak current value IPK is obtained by the following formula.
IPK = IOUT +
VIN − VOUT
L
×
D
fosc
×
1
2
L
: External inductor value
IOUT
: Load current
VIN
: Power supply voltage
VOUT
: Output setting voltage
D
: ON-duty to be switched ( = VOUT/VIN)
fosc
: Switching frequency (2.0 MHz)
= IOUT +
(VIN − VOUT) × VOUT
2 × L × fosc × VIN
ex) When VIN = 3.7 V, VOUT = 2.5 V, IOUT = 0.8 A, L = 2.2 µH, fosc = 2.0 MHz
The maximum peak current value IPK;
IPK = IOUT +
■
(VIN − VOUT) × VOUT
2 × L × fosc × VIN
= 0.8 A +
(3.7 V − 2.5 V) × 2.5 V
2 × 2.2 µH × 2.0 MHz × 3.7 V
≈ 0.89 A
I/O Capacitor Selection
❐ Select a low equivalent series resistance (ESR) for the VDD input capacitor to suppress dissipation from ripple currents.
❐
Also select a low equivalent series resistance (ESR) for the output capacitor. The variation in the inductor current causes ripple
currents on the output capacitor which, in turn, causes ripple voltages an output equal to the amount of variation multiplied by the
ESR value. The output capacitor value has a significant impact on the operating stability of the device when used as a DC/DC
converter. Therefore, Cypress generally recommends a 4.7 µF capacitor, or a larger capacitor value can be used if ripple voltages
are not suitable. If the VIN/VOUT voltage difference is within 0.6 V, the use of a 10 µF output capacitor value is recommended.
❐
Types of capacitors
Ceramic capacitors are effective for reducing the ESR and afford smaller DC/DC converter circuit. However, power supply functions
as a heat generator, therefore avoid to use capacitor with the F-temperature rating ( − 80% to + 20%).Cypress recommends
capacitors with the B-temperature rating ( ± 10% to ± 20%). Normal electrolytic capacitors are not recommended due to their
high ESR.Tantalum capacitor will reduce ESR, however, it is dangerous to use because it turns into short mode when damaged.
If you insist on using a tantalum capacitor, Cypress recommends the type with an internal fuse.
Document Number: 002-08364 Rev. *D
Page 15 of 35
MB39C015
10.2 Output Voltage Setting
The output voltage VOUT (VOUT1 or VOUT2) of this IC is defined by the voltage input to VREFIN (VREFIN1 or VREFIN2) . Supply the
voltage for inputting to VREFIN from an external power supply, or set the VREF output by dividing it with resistors.
The output voltage when the VREFIN voltage is set by dividing the VREF voltage with resistors is shown in the following formula.
VOUT = 3.01 × VREFIN, VREFIN =
R2
R1 + R2
× VREF
(VREF = 1.30 V)
MB39C015
VREF
VREF
R1
VREFIN
VREFIN
R2
Note :
Refer to “ Application Circuit Examples” for the an example of this circuit.
Although the output voltage is defined according to the dividing ratio of resistance, select the resistance value so that the current
flowing through the resistance does not exceed the VREF current rating (1 mA) .
10.3 About Conversion Efficiency
The conversion efficiency can be improved by reducing the loss of the DC/DC converter circuit.
The total loss (PLOSS) of the DC/DC converter is roughly divided as follows :
PLOSS = PCONT + PSW + PC
PCONT : Control system circuit loss (The power used for this IC to operate, including the gate driving power for internal SW FETs)
PSW
: Switching loss (The loss caused during switching of the IC's internal SW FETs)
PC
: Continuity loss (The loss caused when currents flow through the IC's internal SW FETs and external circuits )
Document Number: 002-08364 Rev. *D
Page 16 of 35
MB39C015
The IC's control circuit loss (PCONT) is extremely small, less than 100 mW (with no load).
As the IC contains FETs which can switch faster with less power, the continuity loss (PC) is more predominant as the loss during heavyload operation than the control circuit loss (PCONT) and switching loss (PSW) .
Furthermore, the continuity loss (PC) is divided roughly into the loss by internal SW FET ON-resistance and by external inductor series
resistance.
PC = IOUT2 × (RDC + D × RONP + (1 - D) × RONN)
D
: Switching ON-duty cycle ( = VOUT / VIN)
RONP
: Internal P-ch SW FET ON resistance
RONN
: Internal N-ch SW FET ON resistance
RDC
: External inductor series resistance
IOUT
: Load current
The above formula indicates that it is important to reduce RDC as much as possible to improve efficiency by selecting
components.
10.4 Power Dissipation and Heat Considerations
The IC is so efficient that no consideration is required in most cases. However, if the IC is used at a low power supply voltage, heavy
load, high output voltage, or high temperature, it requires further consideration for higher efficiency.
The internal loss (P) is roughly obtained from the following formula :
P = IOUT2 × (D × RONP + (1 - D) × RONN)
D
: Switching ON-duty cycle ( = VOUT / VIN)
RONP
: Internal P-ch SW FET ON resistance
RONN
: Internal N-ch SW FET ON resistance
IOUT
: Output current
The loss expressed by the above formula is mainly continuity loss. The internal loss includes the switching loss and the control circuit
loss as well but they are so small compared to the continuity loss they can be ignored.
In this IC with RONP greater than RONN, the larger the on-duty cycle, the greater the loss.
When assuming VIN = 3.7 V, Ta = + 70 °C , for example, RONP = 0.36 Ω and RONN = 0.30 Ω according to the graph “MOS FET
ON resistance vs. Operating ambient temperature”. The IC's internal loss P is 123 mW at VOUT = 2.5 V and IOUT = 0.6 A. According
to the graph “Power dissipation vs. Operating ambient temperature”, the power dissipation at an operating ambient temperature Ta
of + 70 °C is 300 mW and the internal loss is smaller than the power dissipation.
Document Number: 002-08364 Rev. *D
Page 17 of 35
MB39C015
10.5 XPOR Threshold Voltage Setting [VPORH, VPORL]
Set the detection voltage by applying voltage to the VDET pin via an external resistor calculated according to this formula.
VPORH =
VPORL =
R3 + R4
R4
R3 + R4
R4
× VTHHPR
× VTHLPR
VTHHPR = 0.600 V
VTHLPR = 0.583 V
Example for setting detection voltage to 3.7 V
R3 = 510 kΩ
R4 = 100 kΩ
VPORH =
VPORL =
510 kΩ + 100 kΩ
100 kΩ
510 kΩ + 100 kΩ
100 kΩ
× 0.600 = 3.66 ≈ 3.7 [V]
× 0.583 = 3.56 ≈ 3.6 [V]
VIN
MB39C015
AVDD
R3
1 MΩ
VDET
R4
Document Number: 002-08364 Rev. *D
XPOR
XPOR
Page 18 of 35
MB39C015
10.6 Transient Response
Normally, IOUT is suddenly changed while VIN and VOUT are maintained constant, responsiveness including the response time and
overshoot/undershoot voltage is checked. As this IC has built-in Error Amp with an optimized design, it shows good transient response
characteristics. However, if ringing upon sudden change of the load is high due to the operating conditions, add capacitor C6 (e.g.
0.1 µF). (Since this capacitor C6 changes the start time, check the start waveform as well.) This action is not required for DAC input.
MB39C015
VREF
VREF
R1
VREFIN
VREFIN1/
VREFIN2
R2
Document Number: 002-08364 Rev. *D
C6
Page 19 of 35
MB39C015
10.7 Board Layout, Design Example
The board layout needs to be designed to ensure the stable operation of this IC.
Follow the procedure below for designing the layout.
• Arrange the input capacitor (Cin) as close as possible to both the VDD and GND pins. Make a through hole (TH) near the pins
of this capacitor if the board has planes for power and GND.
• Large AC currents flow between this IC and the input capacitor (Cin), output capacitor (Co), and external inductor (L). Group
these components as close as possible to this IC to reduce the overall loop area occupied by this group. Also try to mount these
components on the same surface and arrange wiring without through hole wiring. Use thick, short, and straight routes to wire
the net (The layout by planes is recommended.).
• Arrange a bypass capacitor for AVDD as close as possible to both the AVDD and AGND pins. Make a through hole (TH) near
the pins of this capacitor if the board has planes for power and GND.
• The feedback wiring to the OUT should be wired from the voltage output pin closest to the output capacitor (Co). The OUT pin
is extremely sensitive and should thus be kept wired away from the LX1 and pin LX2 pin of this IC as far as possible.
• If applying voltage to the VREFIN1/VREFIN2 pins through dividing resistors, arrange the resistors so that the wiring can be kept
as short as possible. Also arrange them so that the GND pin of VREFIN1/VREFIN2 resistor is close to the IC's AGND pin.
Further, provide a GND exclusively for the control line so that the resistor can be connected via a path that does not carry current.
If installing a bypass capacitor for the VREFIN, put it close to the VREFIN pin.
• If applying voltage to the VDET pin through dividing resistors, arrange the resistors so that the wiring can be kept as short as
possible. Also arrange so that the GND pin of the VDET resistor is close to the IC's AGND pin. Further, provide a GND exclusively
for the control line so that the resistor can be connected via a path that does not carry current.
• Try to make a GND plane on the surface to which this IC will be mounted. For efficient heat dissipation when using the QFN-24
package, Cypress recommends providing a thermal via in the footprint of the thermal pad.
■
Example of Arranging IC SW System Parts
Co
L
VIN
Co
L
GND
Cin
Cin
VIN
Feedback line
1pin
Feedback line
GND
VIN
AVDD bypass capacitor
■
Notes for Circuit Design
The switching operation of this IC works by monitoring and controlling the peak current which, incidentally, serves as a form of shortcircuit protection. However, do not leave the output short-circuited for long periods of time. If the output is short-circuited where VIN <
2.9 V, the current limit value (peak current to the inductor) tends to rise. Leaving in the short-circuit state, the temperature of this IC
will continue rising and activate the thermal protection.
Once the thermal protection stops the output, the temperature of the IC will go down and operation will be restarted, after which the
output will repeat the starting and stopping.
Although this effect will not destroy the IC, the thermal exposure to the IC over prolonged hours may affect the peripherals surrounding
it.
Document Number: 002-08364 Rev. *D
Page 20 of 35
MB39C015
11. Example Of Standard Operation Characteristics
(Shown below is an example of characteristics for connection according to “Test Circuit For Measuring Typical Operating
Characteristics”.)
Characteristics CH1
Conversion efficiency vs. Load current
Conversion efficiency vs. Load current
100
100
VIN = 3.0 V
80
70
VIN = 4.2 V
60
50
VIN = 5.0 V
40
30
20
Ta = +25 °C
VOUT = 2.5 V
10
0
Conversion efficiency η (%)
Conversion efficiency η (%)
VIN = 3.7 V
90
90
70
10
100
VIN = 3.0 V
VIN = 4.2 V
60
50
VIN = 5.0 V
40
30
20
0
1
VIN = 3.7 V
80
Ta = +25 °C
VOUT = 1.2 V
10
1000
1
10
100
1000
Load current IOUT (mA)
Load current IOUT (mA)
Conversion efficiency vs. Load current
Conversion efficiency vs. Load current
100
100
VIN = 3.7 V
90
Conversion efficiency η (%)
Conversion efficiency η (%)
■
VIN = 3.0 V
80
70
VIN = 4.2 V
60
50
VIN = 5.0 V
40
30
20
Ta = +25 °C
VOUT = 1.8 V
10
0
1
10
100
Load current IOUT (mA)
Document Number: 002-08364 Rev. *D
VIN = 3.7 V
90
80
VIN = 4.2 V
70
60
VIN = 5.0 V
50
40
30
20
Ta = +25 °C
VOUT = 3.3 V
10
1000
0
1
10
100
1000
Load current IOUT (mA)
Page 21 of 35
MB39C015
Output voltage vs. Load current
Output voltage vs. Input voltage
2.60
Output voltage VOUT (V)
2.58
2.56
2.54
IOUT = 0 A
2.52
2.50
2.48
2.46
IOUT = 100 mA
2.44
2.60
Ta = +25 °C
VIN = 3.7 V
VOUT = 2.5 V setting
2.58
Output voltage VOUT (V)
Ta = +25 °C
VOUT = 2.5 V setting
2.42
2.56
2.54
2.52
2.50
2.48
2.46
2.44
2.42
2.40
2.40
2.0
3.0
4.0
5.0
6.0
0
200
Input voltage VIN (V)
800
Reference voltage vs. Operating
ambient temperature
1.40
1.40
Ta = +25 °C
VOUT = 2.5 V
1.36
1.34
IOUT = 0 A
1.32
1.30
1.28
1.26
IOUT = 100 mA
1.24
VIN = 3.7 V
VOUT = 2.5 V
IOUT = 0 V
1.38
Reference voltage VREF (V)
1.38
Reference voltage VREF (V)
600
Load current IOUT (mA)
Reference voltage vs. Input voltage
1.36
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.22
1.20
2.0
400
1.20
3.0
4.0
5.0
Input voltage VIN (V)
Document Number: 002-08364 Rev. *D
6.0
−50
0
+50
+100
Operating ambient temperature Ta ( °C )
Page 22 of 35
MB39C015
Input current vs. Operating ambient
temperature
10
10
9
9
8
8
Input current IIN (mA)
Input current IIN (mA)
Input current vs. Input voltage
7
6
5
4
3
2
Ta = +25 °C
VOUT = 2.5 V
1
3.0
4.0
5.0
Ta = +25 °C
VOUT = 1.8 V
IOUT = 100 mA
2.2
2.1
2.0
1.9
1.8
1.7
1.6
4.0
5.0
Input voltage VIN (V)
Document Number: 002-08364 Rev. *D
3
2
VIN = 3.7 V
VOUT = 2.5 V
0
+50
+100
Oscillation frequency vs. Operating
ambient temperature
Oscillation frequency fOSC (MHz)
Oscillation frequency fOSC (MHz)
2.4
3.0
4
Operating ambient temperature Ta ( °C )
Oscillation frequency vs. Input voltage
2.0
5
0
−50
6.0
Input voltage VIN (V)
2.3
6
1
0
2.0
7
6.0
2.4
VIN = 3.7 V
VOUT = 2.5 V
IOUT = 100 mA
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
−50
0
+50
+100
Operating ambient temperature Ta ( °C )
Page 23 of 35
MB39C015
MOS FET ON resistance RON (Ω)
MOS FET ON resistance vs.
Input voltage
0.6
0.5
P-ch
0.4
0.3
0.2
N-ch
0.1
Ta = +25 °C
0
2.0
3.0
4.0
5.0
6.0
Input voltage VIN (V)
N-ch MOS FET ON resistance vs.
Operating ambient temperature
N-ch MOS FET ON resistance RONN (Ω)
P-ch MOS FET ON resistance RONP (Ω)
P-ch MOS FET ON resistance vs.
Operating ambient temperature
0.6
0.5
VIN = 3.7 V
0.4
0.3
0.2
VIN = 5.5 V
0.1
0
−50
0
+50
+100
Operating ambient temperature Ta ( °C )
Document Number: 002-08364 Rev. *D
0.6
0.5
0.4
VIN = 3.7 V
0.3
0.2
VIN = 5.5 V
0.1
0
−50
0
+50
+100
Operating ambient temperature Ta ( °C )
Page 24 of 35
MB39C015
CTL threshold voltage VTH vs. Input voltage
XPOR output voltage VXPOR vs. Input voltage
6.0
1.2
XPOR output voltage VXPOR (V)
CTL threshold voltage VTH (V)
1.4
VTHHCT
1.0
VTHLCT
0.8
0.6
Ta = +25 °C
VOUT = 2.5 V
0.4
VTHHCT : Circuit OFF → ON
VTHLCT : Circuit ON → OFF
0.2
Ta = +25 °C
VPORH = 3.7 V setting
5.0
4.0
3.0
2.0
VXPORL
1.0
0.0
0.0
2.0
3.0
4.0
5.0
2.0
6.0
3.0
Input voltage VIN (V)
5.0
6.0
Power dissipation vs. Operating
ambient temperature
(without thermal via)
3500
Power dissipation PD (mW)
3500
Power dissipation PD (mW)
4.0
Input voltage VIN (V)
Power dissipation vs. Operating
ambient temperature
(with thermal via)
3125
3000
2500
2000
1500
VXPORH
1250
1000
500
3000
2500
2000
1563
1500
1000
625
500
0
−50
0
+50
+85
+100
Operating ambient temperature Ta ( °C )
Document Number: 002-08364 Rev. *D
0
−50
0
+50
+85
+100
Operating ambient temperature Ta ( °C )
Page 25 of 35
MB39C015
■
Switching Waveforms
VOUT : 20 mV/div
VLX : 2.0 V/div
ILX : 500 mA/div
1 µs/div
Document Number: 002-08364 Rev. *D
Ta = +25 °C
VIN = 3.7 V
VOUT = 2.5 V
IOUT = 800 mA
Page 26 of 35
MB39C015
■
Startup Waveform
VCTL : 5.0 V/div
ILX : 500 mA/div
Ta = +25 °C
VIN = 3.7 V
VOUT = 2.5 V
IOUT = 0 A
VREFIN capacitor value =
0.1 µF
VOUT : 1.0 V/div
10 ms/div
VCTL : 2.0 V/div
ILX : 500 mA/div
Ta = +25 °C
VIN = 3.7 V
VOUT = 2.5 V
IOUT = 0 A
VOUT : 1.0 V/div
10 μs/div
Document Number: 002-08364 Rev. *D
No VREFIN capacitor
Page 27 of 35
MB39C015
■
Output Waveforms at Sudden Load Changes (0 mA ↔ 800 mA)
IOUT = 0 mA
IOUT = 800 mA
IOUT = 0 mA
VOUT : 100 mV/div
Ta = +25 °C
VIN = 3.7 V
VOUT = 2.5 V
10 μs/div
■
VREFIN capacitor value
0.1 µF
=
Output Waveforms at Sudden Load Changes (100 mA ↔ 800 mA)
IOUT = 100 mA
IOUT = 800 mA
IOUT = 100 mA
VOUT : 100 mV/div
Ta = +25 °C
VIN = 3.7 V
VOUT = 2.5 V
10 μs/div
Document Number: 002-08364 Rev. *D
VREFIN capacitor value
0.1 µF
=
Page 28 of 35
MB39C015
12. Application Circuit Examples
■
Application Circuit Example 1
❐ An external voltage is input to the reference voltage external input (VREFIN1, VREFIN2) , and the VOUT voltage is set to 3.01 times
the VOUT setting gain.
DVDD1 11
12
3 CTL1
CPU
R7
DGND1 14
15
1 MΩ
DVDD2 19
20
8 VREFIN1
DAC1
C3
4.7 μF
VIN
C4
4.7 μF
DGND2 16
17
AVDD
5
C5
0.1 μF
2 CTL2
AGND
R8
4
1 MΩ
MB39C015
DAC2
L1
2.2 μH
23 VREFIN2
LX1 13
VOUT1
C1
4.7 μF
9 MODE1
OUT1 10
APLI1
L2
2.2 μH
22 MODE2
VOUT2
LX2 18
6 VREF
OUT2 21
C2
4.7 μF
APLI2
7 VDET
1 CTLP
Document Number: 002-08364 Rev. *D
XPOR 24
VOUT = 3.01 × VREFIN
Page 29 of 35
MB39C015
■
Application Circuit Example 2
❐ The voltage of VREF pin is input to the reference voltage external input (VREFIN1, VREFIN2) by dividing resistors. The VOUT1
voltage is set to 2.5 V and VOUT2 voltage is set to 1.8 V.
DVDD1 11
12
3 CTL1
CPU
R7
DGND1 14
15
1 MΩ
R1 170 kΩ
( 20 kΩ + 150 kΩ )
DVDD2 19
20
8 VREFIN1
R2
C3
4.7 μF
VIN
C4
4.7 μF
DGND2 16
17
300 kΩ
AVDD
5
C5
0.1 μF
2 CTL2
AGND
4
R8
1 MΩ
MB39C015
L1
2.2 μH
VOUT1
LX1 13
R5 352 kΩ
( 22 kΩ + 330 kΩ )
C1
4.7 μF
23 VREFIN2
OUT1 10
R6
APLI1
300 kΩ
6 VREF
9 MODE1
22 MODE2
1 CTLP
L2
2.2 μH
VOUT2
LX2 18
C2
4.7 μF
OUT2 21
APLI2
XPOR 24
VOUT1 = 3.01 × VREFIN1
VREFIN1 =
R2
× VREF
R1 + R2
(VREF = 1.30 V)
Document Number: 002-08364 Rev. *D
VOUT1 = 3.01 ×
300 kΩ
× 1.30 V = 2.5 V
170 kΩ + 300 kΩ
VOUT12 = 3.01 ×
300 kΩ
× 1.30 V = 1.8 V
352 kΩ + 300 kΩ
Page 30 of 35
MB39C015
■
Application Circuit Example Components List
Component
Item
L1
L2
Inductor
Inductor
Part Number
Specification
Package
Vendor
VLF4012AT-2R2M
2.2 µH, RDC = 76 mΩ
SMD
TDK
MIPW3226D2R2M
2.2 µH, RDC = 100 mΩ
SMD
FDK
VLF4012AT-2R2M
2.2 µH, RDC = 76 mΩ
SMD
TDK
MIPW3226D2R2M
2.2 µH, RDC = 100 mΩ
SMD
FDK
C1
Ceramic capacitor
C2012JB1A475K
4.7 µF (10 V)
2012
TDK
C2
Ceramic capacitor
C2012JB1A475K
4.7 µF (10 V)
2012
TDK
C3
Ceramic capacitor
C2012JB1A475K
4.7 µF (10 V)
2012
TDK
C4
Ceramic capacitor
C2012JB1A475K
4.7 µF (10 V)
2012
TDK
C5
Ceramic capacitor
C1608JB1E104K
0.1 µF (50 V)
2012
TDK
R1
Resistor
RK73G1JTTD D 20 kΩ
RK73G1JTTD D 150 kΩ
20 kΩ
150 kΩ
1608
1608
KOA
KOA
R2
Resistor
RK73G1JTTD D 300 kΩ
300 kΩ
1608
KOA
R5
Resistor
RK73G1JTTD D 22 kΩ
RK73G1JTTD D 330 kΩ
22 kΩ
330 kΩ
1608
1608
KOA
KOA
R6
Resistor
RK73G1JTTD D 300 kΩ
300 kΩ
1608
KOA
R7
Resistor
RK73G1JTTD D 1 MΩ
1 MΩ ± 0.5%
1608
KOA
R8
Resistor
RK73G1JTTD D 1 MΩ
1 MΩ ± 0.5%
1608
KOA
TDK : TDK Corporation
FDK : FDK Corporation
KOA : KOA Corporation
Document Number: 002-08364 Rev. *D
Page 31 of 35
MB39C015
13. Usage Precautions
1. Do not Configure the IC Over the Maximum Ratings
If the lC is used over the maximum ratings, the LSl may be permanently damaged.It is preferable for the device to normally operate
within the recommended usage conditions. Usage outside of these conditions adversely affect the reliability of the LSI.
2. Use the Devices Within Recommended Operating Conditions
The recommended operating conditions are the conditions under which the LSl is guaranteed to operate.The electrical ratings are
guaranteed when the device is used within the recommended operating conditions and under the conditions stated for each item.
3. Printed Circuit Board Ground Lines Should be Set up With Consideration for Common Impedance
4. Take Appropriate Static Electricity Measures
• Containers for semiconductor materials should have anti-static protection or be made of conductive material.
• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
• Work platforms, tools, and instruments should be properly grounded.
• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.
5. Do not Apply Negative Voltages
The use of negative voltages below −0.3 V may create parasitic transistors on LSI lines, which can cause abnormal operation.
14. Ordering Information
Part Number
Package
Remarks
MB39C015WQN
24-pin plastic QFN
(WNN024)
Exposed PAD
15. RoHS Compliance Information
The LSI products of Cypress with “E1” are compliant with RoHS Directive, and has observed the standard of lead, cadmium, mercury,
hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated diphenyl ethers (PBDE).
A product whose part number has trailing characters “E1” is RoHS compliant.
Document Number: 002-08364 Rev. *D
Page 32 of 35
MB39C015
16. Package Dimension
Package Code: WNN024
0.15
D2
A
D
C A B
13
18
0.10 C
2X
(ND-1)× e
E
0.15
19
12
C A B
E2
5
7
9
INDEX MARK
8
6
1
L
B
TOP VIEW
24
b
e
0.05
0.20
C A B
C
4
0.10 C
2X
BOTTOM VIEW
0.20 C
A
0.05 C
A1
C
SEATING PLANE
9
SIDE VIEW
DIMENSIONS
SYMBOL
MIN.
NOM.
0.80
A
A1
0.05
0.00
D
4.00 BSC
E
4.00 BSC
b
0.20
0.25
D2
2.60 BSC
E2
2.60 BSC
e
0.50 BSC
c
0.35 REF
L
MAX.
0.35
0.40
0.30
NOTE
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCINC CONFORMS TO ASME Y14.5-1994.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINAL HAS
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL. THE
DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
5. ND REFER TO THE NUMBER OF TERMINALS ON D OR E SIDE.
6. MAX. PACKAGE WARPAGE IS 0.05mm.
7. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS.
8. PIN #1 ID ON TOP WILL BE LOCATED WITHIN INDICATED ZONE.
9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT
SINK SLUG AS WELL AS THE TERMINALS.
0.45
10. JEDEC SPECIFICATION NO. REF : N/A
002-15158 Rev. **
Document Number: 002-08364 Rev. *D
Page 33 of 35
MB39C015
Document History
Document Title: MB39C015 2 ch DC/DC Converter IC with PFM/PWM Synchronous Rectification
Document Number: 002-08364
ECN
Orig. of
Change
Submission
Date
**
–
TAOA
07/16/2008
Initial release
*A
5148534
TAOA
03/01/2016
Migrated Spansion Datasheet from DS04-27254-3E to Cypress format
Revision
Description of Change
5633427
HIXT
02/17/2019
Updated Pin Assignment:
Change the package name from LCC-24P-M10 to WNN024
Updated Ordering Information:
Change the package name from LCC-24P-M10 to WNN024
Deleted “Marking Format (Lead Free Version)”
Deleted “Labeling Sample (Lead Free Version)”
Deleted “Evaluation Board Specification”
Deleted “EV Board Ordering Information”
Updated Package Dimension: Updated to Cypress format
*C
5763669
MASG
06/06/2017
Adapted Cypress new logo.
*D
6405849
YOST
12/10/2018
Obsoleted.
*B
Document Number: 002-08364 Rev. *D
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MB39C015
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© Cypress Semiconductor Corporation, 2008-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
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modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
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the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-08364 Rev. *D
Revised December 10, 2018
Page 35 of 35
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