MB88151APNF-G-100-JNERE1

CY88151A Spread Spectrum Clock Generator CY88151A is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. It corresponds to both of the center spread which modulates frequency in modulation off as Middle Centered and down spread which modulates so as not to exceed frequency in modulation off. Features CY88151A-100 (Multiply-by-1) CY88151A-200 (Multiply-by-2) Input frequency/ Output frequency 16.6 MHz to 33.4 MHz/ 16.6 MHz to 33.4 MHz 16.6 MHz to 33.4 MHz/ 33.2 MHz to 66.8 MHz Modulation clock cycle-cycle jitter Less than100 ps Less than 100 ps ■ Modulation rate :  0.5,  1.5 (Center spread),  1.0,  3.0 (Down spread) ■ Equipped with oscillation circuit : Range of oscillation 16.6 MHz to 33.4 MHz ■ Modulation clock output Duty : 40 to 60 ■ Low current consumption by CMOS process : 5 mA (24 MHz : Typ-sample, no load) ■ Power supply voltage : 3.3 V  0.3 V ■ Operating temperature : ■ Package : SOP 8-pin  40 C to  85 C Cypress Semiconductor Corporation Document Number: 002-08311 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 13, 2018 CY88151A Contents PRODUCT LINEUP ...................................................................... 3 ELECTRICAL CHARACTERISTICS ............................................... 12 PIN ASSIGNMENT ........................................................................ 3 OUTPUT CLOCK DUTY CYCLE (TDCC = TB/TA) ....................... 15 PIN DESCRIPTION ...................................................................... 3 INPUT FREQUENCY (FIN = 1/TIN) ............................................. 15 I/O CIRCUIT TYPE ...................................................................... 4 OUTPUT SLEW RATE (SR) ...................................................... 15 CYCLE-CYCLE JITTER (TJC = | TN - TN+1 |) ............................ 16 HANDLING DEVICES ................................................................... 6 PREVENTING LATCH-UP ...................................................... 6 HANDLING UNUSED PINS ..................................................... 6 THE ATTENTION WHEN THE EXTERNAL CLOCK IS USED .......... 6 POWER SUPPLY PINS .......................................................... 6 OSCILLATION CIRCUIT ......................................................... 6 INTERCONNECTION CIRCUIT EXAMPLE ...................................... 21 BLOCK DIAGRAM ....................................................................... 7 SPECTRUM EXAMPLE CHARACTERISTICS .................................. 22 MODULATION WAVEFORM ........................................................ 17 LOCK-UP TIME ........................................................................ 18 OSCILLATION CIRCUIT ............................................................. 20 PIN SETTING ............................................................................. 8 ORDERING INFORMATION ......................................................... 23 ABSOLUTE MAXIMUM RATINGS ................................................ 10 PACKAGE DIMENSION .............................................................. 24 DOCUMENT HISTORY ............................................................... 25 SALES, SOLUTIONS, AND LEGAL INFORMATION ........................ 26 RECOMMENDED OPERATING CONDITIONS ................................. 11 Document Number: 002-08311 Rev. *C Page 2 of 26 CY88151A 1. Product Lineup CY88151A has five kinds of multiplication type. Product Input Frequency Range CY88151A-100 16.6 MHz to 33.4 MHz CY88151A-200 Multiplier Ratio Output Frequency Range Multiply-by-1 16.6 MHz to 33.4 MHz Multiply-by-2 33.2 MHz to 66.8 MHz 2. Pin Assignment TOP VIEW XIN 1 8 XOUT VSS 2 7 VDD CY88151A SEL0 3 6 ENS/XPD SEL1 4 5 CKOUT SOB008 3. Pin Description Pin Name I/O Pin No. XIN I 1 Description Resonator connection pin/clock input pin VSS  2 GND pin SEL0 I 3 Modulation rate setting pin SEL1 I 4 Modulation rate setting pin CKOUT O 5 Modulated clock output pin ENS/XPD I 6 Modulation enable setting pin (with pull-up resistance)/ Power down pin (with pull-up resistor)* VDD  7 Power supply voltage pin XOUT O 8 Resonator connection pin * : XPD  800 k pull-up resistor at “L” Document Number: 002-08311 Rev. *C Page 3 of 26 CY88151A 4. I/O Circuit Type Pin Circuit Type SEL0, SEL1 Remarks CMOS hysteresis input ENS 50 kΩ XPD ■ With 50 k pull-up resistors ■ CMOS hysteresis input ■ With 50 k resistors 50 kΩ 800 kΩ  800 k pull-up Note : If “L” is input to XPD, 50 k pull-up resistor is disconnected. ■ CMOS hysteresis input (Continued) Document Number: 002-08311 Rev. *C Page 4 of 26 CY88151A (Continued) Pin Circuit Type CKOUT Remarks ■ CMOS output ■ IOL  4 mA Note : For XIN and XOUT pins, refer to “Oscillation Circuit”. Document Number: 002-08311 Rev. *C Page 5 of 26 CY88151A 5. Handling Devices 5.1 Preventing Latch-up A latch-up can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an input or output pin or (b) a voltage higher than the rating is applied between VDD pin and VSS pin. The latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the maximum rating. 5.2 Handling Unused Pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or pull-down resistor. Unused output pin should be opened. 5.3 The Attention when the External Clock is Used Input the clock to XIN pin, and XOUT pin should be opened when you use the external clock. Please pay attention so that an overshoot and an undershoot do not occur to an input clock of XIN pin. 5.4 Power Supply Pins Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source. We recommend connecting electrolytic capacitor (about 10 F) and the ceramic capacitor (about 0.01 F) in parallel between VSS pin and VDD pin near the device, as a bypass capacitor. 5.5 Oscillation Circuit Noise near the XIN and XOUT pins may cause the device to malfunction. Design printed circuit boards so that electric wiring of XIN or XOUT pin and the resonator do not intersect other wiring. Design the printed circuit board that surrounds the XIN and XOUT pins with ground. Document Number: 002-08311 Rev. *C Page 6 of 26 CY88151A 6. Block Diagram VDD Modulation rate setting SEL1 Modulation rate setting SEL0 PLL block Modulation enable setting/ Modulation clock output Power down setting ENS/XPD CKOUT Reference clock XOUT Rf = 1 MΩ XIN VSS 1 − M Phase compare Reference clock 1 − N Charge pump V/I conversion IDAC Modulation clock output Loop filter 1 − L ICO Modulation logic CY88151A PLL block Modulation rate setting/ Modulation enable setting A glitchless IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing EMI. Document Number: 002-08311 Rev. *C Page 7 of 26 CY88151A 7. Pin Setting When changing the pin setting, the stabilization wait time for the modulation clock is required. The stabilization wait time for the modulation clock take the maximum value of “Electrical Characteristics AC Characteristics Lock-up time”. ENS Modulation Enable Setting (CY88151A-100/200) ENS Modulation L No modulation H Modulation Note : Spectrum does not spread when “L” is set to ENS. The clock with low jitter can be obtained. Because of ENS has Pull-up resistance, spectrum spread when “H” is set to it or open the terminal. SEL0, SEL1 Modulation Rate Setting SEL1 SEL0 Modulation Rate Modulation Type L L  1.5 Center spread L H  0.5 Center spread H L  1.0 Down spread H H  3.0 Down spread Note : The modulation rate can be changed at the level of the terminal. Document Number: 002-08311 Rev. *C Page 8 of 26 CY88151A ■ Center Spread Spectrum is spread (modulated) by centering on the frequency in modulation off. Modulation width 3.0 Radiation level −1.5% +1.5% Frequency Frequency in modulation off Center spread example of  1.5 modulation rate ■ Down Spread Spectrum is spread (modulated) below the frequency in modulation off. Radiation level Modulation width 3.0 −3.0% Frequency Frequency in modulation off Down spread example of  3.0 modulation rate Document Number: 002-08311 Rev. *C Page 9 of 26 CY88151A 8. Absolute Maximum Ratings Parameter Power supply voltage* Rating Symbol VDD Input voltage* VI Output voltage* VO Storage temperature TST Operation junction temperature TJ Output current IO Overshoot VIOVER Undershoot VIUNDER Unit Min Max  0.5 VSS  0.5 VSS  0.5  55  40  14  VSS1.0 (tUNDER  50 ns)  4.0 VDD  0.5 VDD  0.5  125  125  14 VDD  1.0 (tOVER  50 ns)  V V V C C mA V V * : The parameter is based on VSS  0.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Overshoot/Undershoot tUNDER  50 ns VIOVER  VDD  1.0 V VDD Input pin VSS tOVER  50 ns Document Number: 002-08311 Rev. *C VIUNDER  VSS  1.0 V Page 10 of 26 CY88151A 9. Recommended Operating Conditions (VSS  0.0 V) Parameter Symbol Pin Conditions Power supply voltage VDD VDD “H” level input voltage VIH “L” level input voltage VIL XIN, SEL0, SEL1, ENS Input clock duty cycle tDCI Operating temperature Ta WARNING: Value Unit Min Typ Max  3.0 3.3 3.6 V  VDD × 0.8  VDD  0.3 V  VSS  VDD × 0.2 V XIN 16.6 MHz to 33.4 MHz 40 50 60     40   85 C The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Input clock duty cycle (tDCI  tb/ta) ta tb XIN Document Number: 002-08311 Rev. *C 1.5 V Page 11 of 26 CY88151A 10. Electrical Characteristics ■ DC Characteristics (Ta   40 °C to  85 °C, VDD  3.3 V  0.3 V, VSS  0.0 V) Parameter Power supply current Symbol Pin Conditions ICC VDD VOH Output voltage CKOUT VOL Value Unit Min Typ Max No load capacitance at output 24 MHz CY88151A-100  5.0 7.0 mA “H” level output, IOH   4 mA VDD  0.5  VDD V “L” level output, IOL  4 mA VSS  0.4 V ZO CKOUT 16.6 MHz to 66.8 MHz  45   Input capacitance CIN XIN, SEL0, SEL1, ENS Ta   25 C, VDD  VI  0.0 V, f  1 MHz   16 pF Load capacitance CL CKOUT 16.6 MHz to 66.8 MHz   15 pF RPUE ENS VIL  0.0 V 25 50 200 RPUP XPD VIL  0.0 V 500 800 1200 Output impedance Input pull-up resistance Document Number: 002-08311 Rev. *C k Page 12 of 26 CY88151A ■ AC Characteristics Parameter (Ta   40 °C to  85 °C, VDD  3.3 V  0.3 V, VSS  0.0 V) Symbol Pin Conditions Oscillation frequency fx XIN, XOUT Input frequency fin XIN Output frequency fOUT CKOUT Value Unit Min Typ Max Fundamental oscillation 8.3  33.4 MHz External clock input (multiply-by-1, 2) 16.6  33.4 MHz CY88151A-100 (Multiply by 1) 16.6  33.4 CY88151A-200 (Multiply by 2) 33.2  66.8 MHz Output slew rate SR CKOUT 0.4 V to 2.4 V Load capacitance 15 pF 0.4  4.0 V/ns Output clock duty cycle tDCC CKOUT 1.5 V 40  60  fMOD (nMOD) CKOUT fin/2200 (2200) fin/1900 (1900) fin/1600 (1600) kHz (clks) tLK CKOUT  2 5 ms   100 ps-rms Modulation period (Number of input clocks per modulation) Lock-up time Cycle-cycle jitter tJC CKOUT CY88151A-100, CY88151A-200 16.6 MHz to 66.8 MHz CY88151A-100 CY88151A-200 No load capacitance, Ta   25 C, VDD  3.3 V Note : The modulation clock stabilization wait time is required after the power is turned on, the IC recovers from power saving, or after FREQ (frequency range) or ENS (modulation ON/OFF) setting is changed. For the modulation clock stabilization wait time, assign the maximum value for lock-up time. Document Number: 002-08311 Rev. *C Page 13 of 26 CY88151A fOUT (Output frequency) Modulation waveform t fMOD (Min) Clock time nMOD (Max) fMOD (Max) Clock time nMOD (Min) t CY88151A contains the modulation period to realize the efficient EMI reduction. The modulation period fMOD depends on the input frequency and changes between fMOD (Min) and fMOD (Max) . Furthermore, the average value of fMOD equals the typical value of the electrical characteristics. Document Number: 002-08311 Rev. *C Page 14 of 26 CY88151A 11. Output Clock Duty Cycle (tDCC  tb/ta) ta tb 1.5 V CKOUT 12. Input Frequency (fin  1/tin) tin 0.8 VDD XIN 13. Output Slew Rate (SR) 2.4 V 0.4 V CKOUT tr tf Note : SR  (2.4  0.4) /tr, SR  (2.4  0.4) /tf Document Number: 002-08311 Rev. *C Page 15 of 26 CY88151A 14. Cycle-cycle Jitter (tJC  | tn  tn1 |) CKOUT tn tn+1 Note : Cycle-cycle jitter is defined the difference between a certain cycle and immediately after (or, immediately before) . Document Number: 002-08311 Rev. *C Page 16 of 26 CY88151A 15. Modulation Waveform ■ 1.5 modulation rate, Example of center spread CKOUT Output frequency + 1.5 % Frequency at modulation OFF Time − 1.5 % fMOD ■ 1.0 modulation rate, Example of down spread CKOUT Output frequency Frequency at modulation OFF Time − 0.5 % − 1.0 % fMOD Document Number: 002-08311 Rev. *C Page 17 of 26 CY88151A 16. Lock-up Time 3.0 V VDD Internal clock stabilization wait time XIN Setting pin SEL0, SEL1, ENS VIH tLK (lock-up time ) CKOUT If the setting pin is fixed at the “H” or “L” level, the maximum time after the power is turned on until the set clock signal is output from CKOUT pin is (the stabilization wait time of input clock to XIN pin)  (the lock-up time “tLK”). For the input clock stabilization time, check the characteristics of the resonator or oscillator used. XIN ENS VIH VIL tLK (lock-up time ) tLK (lock-up time ) CKOUT For modulation enable control using the ENS pin during normal operation, the set clock signal is output from CKOUT pin at most the lock-up time (tLK) after the level at the ENS pin is determined. Note : When the pin setting is changed, the CKOUT pin output clock stabilization time is required. Until the output clock signal becomes stable, the output frequency, output clock duty cycle, modulation period, and cycle-cycle jitter cannot be guaranteed. It is therefore advisable to perform processing such as cancelling a reset of the device at the succeeding stage after the lock-up time. Document Number: 002-08311 Rev. *C Page 18 of 26 CY88151A XIN Internal clock stabilization wait time XPD tLK (lock-up time) CKOUT When the power down is controlled by XPD pin, the desired clock is obtained after the pin is set to H level until the maximum lockup time tLK is elapsed. Document Number: 002-08311 Rev. *C Page 19 of 26 CY88151A 17. Oscillation Circuit The figure below shows the connection example about general resonator. The oscillation circuit has the built-in resistance (Rf). The value of capacity (C1 and C2) is required adjusting to the most suitable value of individual resonator. The most suitable value is different by individual resonator. Please refer to the resonator manufacturer which you use for the most suitable value. Input the clock to XIN pin, and do not connect anything with XOUT pin if you use the external clock (you do not use the resonator). ■ When using the resonator CY88151A LSI Internal Rf (1 MΩ) XIN Pin XOUT Pin CY88151A LSI External C2 C1 ■ When using an external clock CY88151A LSI Internal Rf (1 MΩ) XIN Pin External clock XOUT Pin CY88151A LSI External OPEN Note : Note that a jitter characteristic of an input clock may cause an affect a cycle-cycle jitter characteristic. Document Number: 002-08311 Rev. *C Page 20 of 26 CY88151A 18. Interconnection Circuit Example C2 C1 Xtal 1 8 7 2 CY88151A SEL0 3 6 4 5 + ENS R1 SEL1 C4 C1, C2 C3 C4 R1 C3 : Oscillation stabilization capacitance (refer to “Oscillation Circuit”.) : Capacitor of 10 F or higher : Capacitor about 0.01 F (connect a capacitor of good high frequency property (ex. laminated ceramic capacitor) to close to this device.) : Impedance matching resistor for board pattern Document Number: 002-08311 Rev. *C Page 21 of 26 CY88151A 19. Spectrum Example Characteristics The condition of the examples of the characteristic is shown as follows : Input frequency  20 MHz (Output frequency  20 MHz : Using CY88151A-100 (Multiply-by-1)), Power - supply voltage  3.3 V, None load capacity, Modulation rate   1.5 (center spread). Spectrum analyzer HP4396B is connected with CKOUT. The result of the measurement with RBW  1 kHz (ATT use for  6dB). CH B Spectrum 10 dB /REF 0 dBm No modulation 6.54 dBm 1.5 modulation 24.45 dBm Avg 4 VBW 1 kHZ RBW# 1 kHZ CENTER 20 MHZ Document Number: 002-08311 Rev. *C ATT 6 dB SWP 2.505 s SPAN 4 MHZ Page 22 of 26 CY88151A 20. Ordering Information Part Number Input Frequency Range CY88151APNF-G-100-JNE1 CY88151APNF-G-200-JNE1 CY88151APNF-G-100-JNEFE1 CY88151APNF-G-200-JNEFE1 CY88151APNF-G-100-JNERE1 CY88151APNF-G-200-JNERE1 16.6 MHz to 33.4 MHz 16.6 MHz to 33.4 MHz 16.6 MHz to 33.4 MHz Multiplier Ratio Output Frequency Range Multiplyby-1 16.6 MHz to 33.4 MHz Multiplyby-2 33.2 MHz to 66.8 MHz Multiplyby-1 16.6 MHz to 33.4 MHz Multiplyby-2 33.2 MHz to 66.8 MHz Multiplyby-1 16.6 MHz to 33.4 MHz Multiplyby-2 33.2 MHz to 66.8 MHz Package Remarks 8-pin plastic SOP (SOB008) Emboss taping (EF type) Emboss taping (ER type) Ordering Code Definitions CY88151APNF -G -200 -JN ERE1 Pb (lead)-free Package Tape and real: (EF: Forward, ER: Reverse) Tube (No Notation) Factory location: (JN: w/f=Japan, Assemble=China) Product line up Reliability Grade: G = 100 ppm Part number: CY88151APNF Document Number: 002-08311 Rev. *C Page 23 of 26 CY88151A 21. Package Dimension 0.44 0.52 L 0.45 0.60 0.75 L 2 0.25 BSC 1.27 BSC. h 0.40 BSC. 2  756 21 ( 2 1' , $17 /$$ 35 ' , * /8 1 * ,( , 7 +) $7 1 ( 2 6*& 1 , ( ( +'* 78$ /. 0 & 2 & ; 5($ 3 )<  ' 1 ( &2: 1%2 $' 7( 6*< , '$7 , .9 / & $$$ &3& , 1  7 ( 5+2  ( 7 7 91 1( ( 2 0 +7 ( 71 , & 6 $21 3$ ' +   (7 1 16( , (/  ) (:$ '20 / 6 5 ( , (   + +  $77                e   1 , 3  $  1 ' (( +7 7$ &  7 , 1' (1 , 6 ($ 5( 35 $ 7  2; 1( ' 6 1 ,  , 7  , (  + ) /7 1   / , $+ 17 2, ,: 7  3' 2( 7 6 $ ,  & ( 52 / 8 7( $% (7  )6 8 5 (0 ) 05 ( $, +) , &7 1 6 , ( +' 7,       1.05 REF Page 24 of 26 Document Number: 002-08311 Rev. *C 002-15856 Rev.** 11. JEDEC SPECIFICATION NO. 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