MB88151A
Spread Spectrum Clock Generator
MB88151A is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can
be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. It corresponds to both of
the center spread which modulates frequency in modulation off as Middle Centered and down spread which modulates so as not to
exceed frequency in modulation off.
Features
MB88151A100/101
(multiply-by-1)
MB88151A200/201
(multiply-by-2)
MB88151A400/401
(multiply-by-4)
MB88151A500/501
(multiply-by-1/2)
MB88151A800/801
(multiply-by-8)
Input
frequency/
Output
frequency
16.6 MHz to 33.4
MHz/
16.6 MHz to 33.4
MHz
16.6 MHz to 33.4
MHz/
33.2 MHz to 66.8
MHz
16.6 MHz to 33.4
MHz/
66.4 MHz to 133.6
MHz
16.6 MHz to 33.4
MHz/
8.3 MHz to 16.7 MHz
8.3 MHz to 16.7 MHz
66.4 MHz to 133.6
MHz
Modulation
clock
cycle-cycle
jitter
Less than100 ps
Less than 100 ps
Less than 150 ps
Less than 200 ps
Less than 150 ps
■
Modulation rate : 0.5, 1.5 (Center spread), 1.0, 3.0 (Down spread)
■
Equipped with oscillation circuit : Range of oscillation 8.3 MHz to 33.4 MHz
■
Modulation clock output Duty : 40 to 60
■
Low current consumption by CMOS process : 5 mA (24 MHz : Typ-sample, no load)
■
Power supply voltage : 3.3 V 0.3 V
■
Operating temperature :
■
Package : SOP 8-pin
40 C to 85 C
Cypress Semiconductor Corporation
Document Number: 002-08311 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 30, 2016
MB88151A
Contents
Product Lineup ................................................................. 3
Pin Assignment ................................................................ 3
Pin Description ................................................................. 3
I/O Circuit Type ................................................................. 4
Handling Devices .............................................................. 6
Preventing Latch-up .................................................... 6
Handling unused pins .................................................. 6
The attention when the external clock is used ............ 6
Power supply pins ....................................................... 6
Oscillation circuit ......................................................... 6
Block Diagram .................................................................. 7
Pin Setting ......................................................................... 8
Absolute Maximum Ratings .......................................... 10
Recommended Operating Conditions .......................... 11
Document Number: 002-08311 Rev. *A
Electrical Characteristics ............................................... 12
Output Clock Duty Cycle (tdcc tb/ta) ....................... 15
Input Frequency (fin 1/tin) ......................................... 15
Output Slew Rate (SR) .................................................. 15
Cycle-cycle Jitter (tjc | tn tn1 |) ........................... 16
Modulation Waveform .................................................... 17
Lock-up Time .................................................................. 18
Oscillation Circuit ........................................................... 20
Interconnection Circuit Example .................................. 21
Spectrum Example Characteristics .............................. 22
Ordering Information ............................. 23
Package Dimension ........................................................ 24
Document History ........................................................... 25
Sales, Solutions, and Legal Information .......................26
Page 2 of 26
MB88151A
1. Product Lineup
MB88151A has five kinds of multiplication type.
Product
Input frequency range
MB88151A-100/101
MB88151A-200/201
16.6 MHz to 33.4 MHz
MB88151A-400/401
MB88151A-500/501
MB88151A-800/801
8.3 MHz to 16.7 MHz
Multiplier ratio
Output frequency range
Multiply-by-1
16.6 MHz to 33.4 MHz
Multiply-by-2
33.2 MHz to 66.8 MHz
Multiply-by-4
66.4 MHz to 133.6 MHz
Multiply-by-1/2
8.3 MHz to 16.7 MHz
Multiply-by-8
66.4 MHz to 133.6 MHz
2. Pin Assignment
TOP VIEW
XIN 1
8 XOUT
VSS 2
7 VDD
MB88151A
SEL0 3
6 ENS/XPD
SEL1 4
5 CKOUT
FPT-8P-M02
3. Pin Description
Pin name
I/O
Pin no.
Description
XIN
I
1
Resonator connection pin/clock input pin
VSS
2
GND pin
SEL0
I
3
Modulation rate setting pin
SEL1
I
4
Modulation rate setting pin
CKOUT
O
5
Modulated clock output pin
ENS/XPD
I
6
Modulation enable setting pin (with pull-up resistance)/
Power down pin (with pull-up resistor)*
VDD
7
Power supply voltage pin
XOUT
O
8
Resonator connection pin
* : XPD 800 k pull-up resistor at “L”
Document Number: 002-08311 Rev. *A
Page 3 of 26
MB88151A
4. I/O Circuit Type
Pin
Circuit type
SEL0,
SEL1
Remarks
CMOS hysteresis input
ENS
50 kΩ
XPD
■
With 50 k pull-up resistors
■
CMOS hysteresis input
■
With 50 k
resistors
50 kΩ
800 kΩ
800 k pull-up
Note : If “L” is input to XPD, 50 k
pull-up resistor is disconnected.
■
CMOS hysteresis input
(Continued)
Document Number: 002-08311 Rev. *A
Page 4 of 26
MB88151A
(Continued)
Pin
Circuit type
CKOUT
Remarks
■
CMOS output
■
IOL 4 mA
Note : For XIN and XOUT pins, refer to “Oscillation Circuit”.
Document Number: 002-08311 Rev. *A
Page 5 of 26
MB88151A
5. Handling Devices
5.1 Preventing Latch-up
A latch-up can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an input or output pin or
(b) a voltage higher than the rating is applied between VDD pin and VSS pin. The latch-up, if it occurs, significantly increases the power
supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the
maximum rating.
5.2 Handling unused pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or
pull-down resistor.
Unused output pin should be opened.
5.3 The attention when the external clock is used
Input the clock to XIN pin, and XOUT pin should be opened when you use the external clock.
Please pay attention so that an overshoot and an undershoot do not occur to an input clock of XIN pin.
5.4 Power supply pins
Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source.
We recommend connecting electrolytic capacitor (about 10 F) and the ceramic capacitor (about 0.01 F) in parallel between VSS
pin and VDD pin near the device, as a bypass capacitor.
5.5 Oscillation circuit
Noise near the XIN and XOUT pins may cause the device to malfunction. Design printed circuit boards so that electric wiring of XIN
or XOUT pin and the resonator do not intersect other wiring.
Design the printed circuit board that surrounds the XIN and XOUT pins with ground.
Document Number: 002-08311 Rev. *A
Page 6 of 26
MB88151A
6. Block Diagram
VDD
Modulation rate
setting
SEL1
Modulation rate
setting
SEL0
PLL block
Modulation enable setting/
Modulation
clock output
Power down setting
ENS/XPD
CKOUT
Reference clock
XOUT
Rf = 1 MΩ
XIN
VSS
1
−
M
Phase
compare
Reference clock
1
−
N
Charge
pump
V/I
conversion
IDAC
Modulation clock
output
Loop filter
1
−
L
ICO
Modulation logic
MB88151A PLL block
Modulation
rate setting/
Modulation
enable setting
A glitchless IDAC (current output D/A converter) provides precise modulation, thereby
dramatically reducing EMI.
Document Number: 002-08311 Rev. *A
Page 7 of 26
MB88151A
7. Pin Setting
When changing the pin setting, the stabilization wait time for the modulation clock is required. The stabilization wait time for the
modulation clock take the maximum value of “Electrical Characteristics AC Characteristics Lock-up time”.
ENS modulation enable setting (MB88151A-100/200/400/500/800)
ENS
Modulation
L
No modulation
H
Modulation
Note : Spectrum does not spread when “L” is set to ENS. The clock with low jitter can be obtained. Because of ENS has Pull-up
resistance, spectrum spread when “H” is set to it or open the terminal.
XPD Power down setting (MB88151A-101/201/401/501/801)
XPD
Status
L
Power down Status
H
Operating status
Note : CKOUT of output pins are fixed to “L” output during power down.
SEL0, SEL1 Modulation rate setting
SEL1
SEL0
Modulation rate
Modulation type
L
L
1.5
Center spread
L
H
0.5
Center spread
H
L
1.0
Down spread
H
H
3.0
Down spread
Note : The modulation rate can be changed at the level of the terminal.
Document Number: 002-08311 Rev. *A
Page 8 of 26
MB88151A
■
Center spread
Spectrum is spread (modulated) by centering on the frequency in modulation off.
Modulation width 3.0
Radiation level
−1.5%
+1.5%
Frequency
Frequency in modulation off
Center spread example of 1.5 modulation rate
■
Down spread
Spectrum is spread (modulated) below the frequency in modulation off.
Radiation level
Modulation width 3.0
−3.0%
Frequency
Frequency in modulation off
Down spread example of 3.0 modulation rate
Document Number: 002-08311 Rev. *A
Page 9 of 26
MB88151A
8. Absolute Maximum Ratings
Parameter
Power supply voltage*
Rating
Symbol
VDD
Input voltage*
VI
Output voltage*
VO
Storage temperature
TST
Operation junction temperature
TJ
Output current
IO
Overshoot
VIOVER
Undershoot
VIUNDER
Unit
Min
Max
0.5
VSS 0.5
VSS 0.5
55
40
14
VSS1.0 (tUNDER 50 ns)
4.0
VDD 0.5
VDD 0.5
125
125
14
VDD 1.0 (tOVER 50 ns)
V
V
V
C
C
mA
V
V
* : The parameter is based on VSS 0.0 V.
WARNING:
Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Overshoot/Undershoot
tUNDER 50 ns
VIOVER VDD 1.0 V
VDD
Input pin
VSS
tOVER 50 ns
Document Number: 002-08311 Rev. *A
VIUNDER VSS 1.0 V
Page 10 of 26
MB88151A
9. Recommended Operating Conditions
(VSS 0.0 V)
Parameter
Symbol
Pin
Conditions
Power supply voltage
VDD
VDD
“H” level input voltage
VIH
“L” level input voltage
VIL
XIN,
SEL0,
SEL1,
ENS
Input clock
duty cycle
tDCI
Operating temperature
Ta
WARNING:
Value
Unit
Min
Typ
Max
3.0
3.3
3.6
V
VDD × 0.8
VDD 0.3
V
VSS
VDD × 0.2
V
XIN
8.3 MHz to
33.4 MHz
40
50
60
40
85
C
The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Input clock duty cycle (tDCI tb/ta)
ta
tb
XIN
Document Number: 002-08311 Rev. *A
1.5 V
Page 11 of 26
MB88151A
10. Electrical Characteristics
■
DC Characteristics
(Ta 40 °C to 85 °C, VDD 3.3 V 0.3 V, VSS 0.0 V)
Parameter
Power supply current
Symbol
ICC
Pin
Conditions
VDD
VOH
CKOUT
Output voltage
VOL
Output impedance
Input capacitance
Load capacitance
Input pull-up resistance
Value
Unit
Min
Typ
Max
No load capacitance at
output 24 MHz
MB88151A-100
5.0
7.0
mA
At power down
MB88151A-101
10
A
“H” level output,
IOH 4 mA
VDD 0.5
VDD
V
“L” level output,
IOL 4 mA
VSS
0.4
V
ZO
CKOUT
8.3 MHz to 133.6 MHz
45
CIN
XIN,
SEL0,
SEL1,
ENS
Ta 25 C,
VDD VI 0.0 V,
f 1 MHz
16
pF
8.3 MHz to 66.8 MHz
15
66.8 MHz to 100 MHz
10
100 MHz to 133.6 MHz
7
CL
CKOUT
pF
RPUE
ENS
VIL 0.0 V
25
50
200
RPUP
XPD
VIL 0.0 V
500
800
1200
Document Number: 002-08311 Rev. *A
k
Page 12 of 26
MB88151A
■
AC Characteristics
Parameter
Oscillation frequency
Input frequency
Output frequency
(Ta 40 °C to 85 °C, VDD 3.3 V 0.3 V, VSS 0.0 V)
Symbol
Pin
Conditions
fx
XIN,
XOUT
XIN
fin
fOUT
CKOUT
Value
Min
Typ
Max
Fundamental
oscillation
8.3
33.4
External clock input
(multiply-by-1, 2, 4,
divided by 2)
16.6
33.4
External clock input
(multiply-by-8)
8.3
16.7
MB88151A-100/101
(Multiply by 1)
16.6
33.4
MB88151A-200/201
(Multiply by 2)
33.2
66.8
MB88151A-400/401
(Multiply by 4)
66.4
133.6
MB88151A-500/501
(2-frequency division)
8.3
16.7
MB88151A-800/801
(multiply-by-8)
66.4
133.6
Unit
MHz
MHz
MHz
Output slew rate
SR
CKOUT
0.4 V to 2.4 V
Load capacitance 15 pF
0.4
4.0
V/ns
Output clock duty cycle
tDCC
CKOUT
1.5 V
40
60
MB88151A-100/101,
MB88151A-200/201,
MB88151A-400/401,
MB88151A-500/501
fin/2200
(2200)
fin/1900
(1900)
fin/1600
(1600)
kHz
(clks)
MB88151A-800/801
fin/880
(880)
fin/760
(760)
fin/640
(640)
kHz
(clks)
8.3 MHz to 80 MHz
2
5
80 MHz to 133.6 MHz
3
8
MB88151A-100/101,
MB88151A-200/201
No load capacitance,
Ta 25 C, VDD 3.3 V
100
MB88151A-400/401,
MB88151A-800/801
No load capacitance,
Ta 25 C, VDD 3.3 V
150
MB88151A-500/501
No load capacitance,
Ta 25 C, VDD 3.3 V
200
Modulation period
(Number of input clocks
per modulation)
Lock-up time
Cycle-cycle jitter
fMOD
(nMOD)
tLK
tJC
CKOUT
CKOUT
CKOUT
ms
ps-rms
Note : The modulation clock stabilization wait time is required after the power is turned on, the IC recovers from power saving, or after
FREQ (frequency range) or ENS (modulation ON/OFF) setting is changed. For the modulation clock stabilization wait time,
assign the maximum value for lock-up time.
Document Number: 002-08311 Rev. *A
Page 13 of 26
MB88151A
fOUT (Output frequency)
Modulation waveform
t
fMOD (Min)
Clock time
nMOD (Max)
fMOD (Max)
Clock time
nMOD (Min)
t
MB88151A contains the modulation period to realize the efficient EMI reduction.
The modulation period fMOD depends on the input frequency and changes between fMOD (Min) and fMOD (Max) .
Furthermore, the average value of fMOD equals the typical value of the electrical characteristics.
Document Number: 002-08311 Rev. *A
Page 14 of 26
MB88151A
11. Output Clock Duty Cycle (tDCC tb/ta)
ta
tb
1.5 V
CKOUT
12. Input Frequency (fin 1/tin)
tin
0.8 VDD
XIN
13. Output Slew Rate (SR)
2.4 V
0.4 V
CKOUT
tr
tf
Note : SR (2.4 0.4) /tr, SR (2.4 0.4) /tf
Document Number: 002-08311 Rev. *A
Page 15 of 26
MB88151A
14. Cycle-cycle Jitter (tJC | tn tn1 |)
CKOUT
tn
tn+1
Note : Cycle-cycle jitter is defined the difference between a certain cycle and immediately after
(or, immediately before) .
Document Number: 002-08311 Rev. *A
Page 16 of 26
MB88151A
15. Modulation Waveform
■
1.5 modulation rate, Example of center spread
CKOUT
Output frequency
+ 1.5 %
Frequency at modulation OFF
Time
− 1.5 %
fMOD
■
1.0 modulation rate, Example of down spread
CKOUT
Output frequency
Frequency at modulation OFF
Time
− 0.5 %
− 1.0 %
fMOD
Document Number: 002-08311 Rev. *A
Page 17 of 26
MB88151A
16. Lock-up Time
3.0 V
VDD
Internal clock
stabilization wait time
XIN
Setting pin
SEL0,
SEL1,
ENS
VIH
tLK
(lock-up time )
CKOUT
If the setting pin is fixed at the “H” or “L” level, the maximum time after the power is turned on until the set clock signal is output from
CKOUT pin is (the stabilization wait time of input clock to XIN pin) (the lock-up time “tLK”). For the input clock stabilization time,
check the characteristics of the resonator or oscillator used.
XIN
ENS
VIH
VIL
tLK
(lock-up time )
tLK
(lock-up time )
CKOUT
For modulation enable control using the ENS pin during normal operation, the set clock signal is output from
CKOUT pin at most the lock-up time (tLK) after the level at the ENS pin is determined.
Note : When the pin setting is changed, the CKOUT pin output clock stabilization time is required. Until the output clock signal becomes
stable, the output frequency, output clock duty cycle, modulation period, and cycle-cycle jitter cannot be guaranteed. It is
therefore advisable to perform processing such as cancelling a reset of the device at the succeeding stage after the lock-up time.
Document Number: 002-08311 Rev. *A
Page 18 of 26
MB88151A
XIN
Internal clock
stabilization wait time
XPD
tLK
(lock-up time)
CKOUT
When the power down is controlled by XPD pin, the desired clock is obtained after the pin is set to H level until the maximum lockup time tLK is elapsed.
Document Number: 002-08311 Rev. *A
Page 19 of 26
MB88151A
17. Oscillation Circuit
The figure below shows the connection example about general resonator. The oscillation circuit has the built-in resistance (Rf). The
value of capacity (C1 and C2) is required adjusting to the most suitable value of individual resonator.
The most suitable value is different by individual resonator. Please refer to the resonator manufacturer which you use for the most
suitable value.
Input the clock to XIN pin, and do not connect anything with XOUT pin if you use the external clock (you do not use the resonator).
■
When using the resonator
MB88151A LSI Internal
Rf (1 MΩ)
XIN Pin
XOUT Pin
MB88151A LSI External
C2
C1
■
When using an external clock
MB88151A LSI Internal
Rf (1 MΩ)
XIN Pin
External clock
XOUT Pin
MB88151A LSI External
OPEN
Note : Note that a jitter characteristic of an input clock may cause an affect a cycle-cycle jitter characteristic.
Document Number: 002-08311 Rev. *A
Page 20 of 26
MB88151A
18. Interconnection Circuit Example
C2
C1
Xtal
1
8
2
7
MB88151A
SEL0
3
6
4
5
+
ENS
R1
SEL1
C4
C1, C2
C3
C4
R1
C3
: Oscillation stabilization capacitance (refer to “Oscillation Circuit”.)
: Capacitor of 10 F or higher
: Capacitor about 0.01 F (connect a capacitor of good high frequency
property (ex. laminated ceramic capacitor) to close to this device.)
: Impedance matching resistor for board pattern
Document Number: 002-08311 Rev. *A
Page 21 of 26
MB88151A
19. Spectrum Example Characteristics
The condition of the examples of the characteristic is shown as follows : Input frequency 20 MHz (Output frequency 20 MHz :
Using MB88151A-100 (Multiply-by-1)), Power - supply voltage 3.3 V, None load capacity,
Modulation rate 1.5 (center spread).
Spectrum analyzer HP4396B is connected with CKOUT. The result of the measurement with RBW 1 kHz
(ATT use for 6dB).
CH B Spectrum
10 dB /REF 0 dBm
No modulation
6.54 dBm
1.5 modulation
24.45 dBm
Avg
4
VBW 1 kHZ
RBW# 1 kHZ
CENTER 20 MHZ
Document Number: 002-08311 Rev. *A
ATT 6 dB
SWP 2.505 s
SPAN 4 MHZ
Page 22 of 26
MB88151A
20. Ordering Information
Multiplier
ratio
Output frequency
range
Multiplyby-1
16.6 MHz to 33.4 MHz
Multiplyby-2
33.2 MHz to 66.8 MHz
Multiplyby-4
66.4 MHz to 133.6 MHz
Multiplyby-1/2
8.3 MHz to 16.7 MHz
Multiplyby-8
66.4 MHz to 133.6 MHz
MB88151APNF-G-100-JNEFE1
MB88151APNF-G-101-JNEFE1
Multiplyby-1
16.6 MHz to 33.4 MHz
MB88151APNF-G-200-JNEFE1
MB88151APNF-G-201-JNEFE1
Multiplyby-2
33.2 MHz to 66.8 MHz
Multiplyby-4
66.4 MHz to 133.6 MHz
Multiplyby-1/2
8.3 MHz to 16.7 MHz
Multiplyby-8
66.4 MHz to 133.6 MHz
MB88151APNF-G-100-JNERE1
MB88151APNF-G-101-JNERE1
Multiplyby-1
16.6 MHz to 33.4 MHz
MB88151APNF-G-200-JNERE1
MB88151APNF-G-201-JNERE1
Multiplyby-2
33.2 MHz to 66.8 MHz
Multiplyby-4
66.4 MHz to 133.6 MHz
Multiplyby-1/2
8.3 MHz to 16.7 MHz
Multiplyby-8
66.4 MHz to 133.6 MHz
Part number
Input frequency
range
MB88151APNF-G-100-JNE1
MB88151APNF-G-101-JNE1
MB88151APNF-G-200-JNE1
MB88151APNF-G-201-JNE1
MB88151APNF-G-400-JNE1
MB88151APNF-G-401-JNE1
16.6 MHz to
33.4 MHz
MB88151APNF-G-500-JNE1
MB88151APNF-G-501-JNE1
MB88151APNF-G-800-JNE1
MB88151APNF-G-801-JNE1
MB88151APNF-G-400-JNEFE1
MB88151APNF-G-401-JNEFE1
8.3 MHz to
16.7 MHz
16.6 MHz to
33.4 MHz
MB88151APNF-G-500-JNEFE1
MB88151APNF-G-501-JNEFE1
MB88151APNF-G-800-JNEFE1
MB88151APNF-G-801-JNEFE1
MB88151APNF-G-400-JNERE1
MB88151APNF-G-401-JNERE1
8.3 MHz to
16.7 MHz
16.6 MHz to
33.4 MHz
MB88151APNF-G-500-JNERE1
MB88151APNF-G-501-JNERE1
MB88151APNF-G-800-JNERE1
MB88151APNF-G-801-JNERE1
Document Number: 002-08311 Rev. *A
8.3 MHz to
16.7 MHz
Package
Remarks
8-pin plastic
SOP
(FPT-8P-M02)
Emboss
taping
(EF type)
Emboss
taping
(ER type)
Page 23 of 26
MB88151A
21. Package Dimension
8-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
3.9 × 5.05 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.75 mm MAX
Weight
0.06 g
(FPT-8P-M02)
8-pin plastic SOP
(FPT-8P-M02)
+0.25
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
+.010
+0.03
*1 5.05 –0.20 .199 –.008
0.22 –0.07
+.001
.009 –.003
8
5
*2 3.90±0.30 6.00±0.40
(.154±.012) (.236±.016)
Details of "A" part
45˚
1.55±0.20
(Mounting height)
(.061±.008)
0.25(.010)
0.40(.016)
1
"A"
4
1.27(.050)
0.44±0.08
(.017±.003)
0.13(.005)
0~8˚
M
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.15±0.10
(.006±.004)
(Stand off)
0.10(.004)
©2002-2008
FUJITSU MICROELECTRONICS LIMITED F08004S-c-4-8
C
2002 FUJITSU LIMITED F08004S-c-4-7
Document Number: 002-08311 Rev. *A
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Page 24 of 26
MB88151A
Document History
Spansion Publication Number: DS04-29127-3E
Document Title: MB88151A Spread Spectrum Clock Generator
Document Number: 002-08311
ECN
Orig. of
Change
Submission
Date
**
–
TAOA
06/29/2009
Initial Release
*A
5569547
TAOA
12/30/2016
Updated to Cypress Template
Revision
Document Number: 002-08311 Rev. *A
Description of Change
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MB88151A
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Lighting & Power Control
Memory
cypress.com/iot
cypress.com/powerpsoc
cypress.com/memory
PSoC
Cypress Developer Community
Forums | WICED IoT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
Touch Sensing
cypress.com/touch
USB Controllers
Wireless/RF
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/usb
cypress.com/wireless
26
© Cypress Semiconductor Corporation, 2007-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-08311 Rev. *A
Revised December 30, 2016
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