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company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
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Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
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The following document contains information on Cypress products. The document has the series
name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will
offer these products to new and existing customers with the series name, product name, and
ordering part number with the prefix “CY”.
How to Check the Ordering Part Number
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4. Download the Affected Parts List file, which has details of all changes
For More Information
Please contact your local sales office for additional information about Cypress products and
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About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to www.cypress.com.
MB90350E Series
F2MC-16LX16-bit Microcontrollers
The MB90350E series, loaded 1 channel FULL-CAN* interface and Flash ROM, is general-purpose Cypress 16-bit microcontroller
designing for automotive and industrial applications. Its main feature is the on-board CAN interface, which conforms to CAN standard
Version2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal
full CAN approach.
The power supply (3 V) is supplied to the MCU core from an internal regulator circuit. This creates a major advantage in terms of EMI
and power consumption.
The PLL clock multiplication circuit provides an internal 42 ns instruction execution time from an external 4 MHz clock. Also, the clock
supervisor function can monitor main clock and sub clock independently.
As the peripheral resources, the unit features a 4-channel Output Compare Unit, 6-channel Input Capture Unit, 2 separate 16-bit
free-run timers, 2-channel LIN-UART and 15-channel 8/10-bit A/D converter built-in.
: Controller Area Network (CAN) - License of Robert Bosch GmbH
Features
Clock
Powerful interrupt function
■
Built-in PLL clock frequency multiplication circuit
■
Powerful 8-level, 34-condition interrupt feature
■
Selection of machine clocks (PLL clocks) is allowed among
frequency division by two on oscillation clock, and multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation
clock, 4 MHz to 24 MHz).
■
Up to 8 channels external interrupts are supported.
■
Operation by sub clock (up to 50 kHz : 100 kHz oscillation clock
divided by two) is allowed (devices without S-suffix only) .
■
Extended intelligent I/O service function (EI2OS): up to 16
channels
■
Minimum execution time of instruction : 42 ns (when operating
with 4-MHz oscillation clock, and 6-time
multiplied PLL clock).
■
DMA: up to 16 channels
■
Built-in clock modulation circuit
16 Mbytes CPU memory space
24-bit internal addressing
Instruction system best suited to controller
■
Wide choice of data types (bit, byte, word, and long word)
■
Wide choice of addressing modes (23 types)
■
Enhanced multiply-divide instructions with sign and RETI
instructions
Automatic data transfer function independent of
CPU
Low power consumption (standby) mode
■
Sleep mode (a mode that stops CPU operating clock)
■
Main timer mode (a timebase timer mode switched from the
main clock mode)
■
PLL timer mode (a timebase timer mode switched from the PLL
clock mode)
■
Watch mode (a mode that operates sub clock and watch timer
only)
■
Stop mode (a mode that stops oscillation clock and sub clock)
■
CPU intermittent operation mode
Clock supervisor (MB90x356x and MB90x357x
only)
Process
Main clock or sub clock is monitored independently.
I/O port
Enhanced high-precision computing with 32-bit
accumulator
Instruction system compatible with high-level
language (C language) and multitask
■
Employing system stack pointer
■
Enhanced various pointer indirect instructions
■
Barrel shift instructions
CMOS technology
■
Sub clock pin (X0A, X1A)
Increased processing speed
■
Yes (using the external oscillation) : devices without S-suffix
■
No (using the sub clock mode at internal CR oscillation) :
devices with S-suffix
Timer
4-byte instruction queue
■
Cypress Semiconductor Corporation
Document Number: 002-04493 Rev. *A
General-purpose input/output port (CMOS output)
49 ports (devices without S-suffix : devices that correspond to
sub clock)
51 ports (devices with S-suffix : devices that do not correspond
to sub clock)
•
198 Champion Court
Timebase timer, watch timer, watchdog timer : 1 channel
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 7, 2016
MB90350E Series
■
8/16-bit PPG timer : 8-bit 10 channels or 16-bit 6 channels
■
16-bit reload timer : 2 channels (only Evaluation products has
4 channels)
■
16- bit input/output timer
- 16-bit free-run timer : 2 channels (FRT0 : ICU0/1, FRT1 :
ICU4/5/6/7, OCU4/5/6/7)
- 16- bit input capture: (ICU) : 6 channels
- 16-bit output compare : (OCU) : 4 channels
FULL-CAN interface: 1 channel
■
Compliant with CAN standard Version2.0 Part A and Part B
■
16 message buffers are built-in
■
CAN wake-up function
Address matching detection (Program patch)
function
■
Capable of changing input voltage level for port
■
Automotive/CMOS-Schmitt (initial level is Automotive in single
chip mode)
■
TTL level (corresponds to external bus pins only, initial level of
these pins is TTL in external bus mode)
Low voltage/CPU operation detection reset
(devices with T-suffix)
■
■
LIN-UART: 2 channels
■
Equipped with full-duplex double buffer
■
Clock-asynchronous or clock-synchronous serial transmission
is available.
I2C interface: 1 channel
■
8
channels,
CAN
Module for activation of extended intelligent I/O service (EI2OS),
DMA, and generation of external interrupt by external input.
Delay interrupt generator module
■
Resolution is selectable between 8-bit and 10-bit.
■
Activation by external trigger input is allowed.
■
Conversion time : 3 s (at 24 MHz machine clock, including
sampling time)
Document Number: 002-04493 Rev. *A
Resets automatically when program is runaway and counter is
not cleared within interval time
(approx. 262 ms : external 4 MHz)
Erase/write and read can be executed in the different bank
(Upper Bank/Lower Bank) at the same time.
Supported TA 125C
The maximum operating frequency is 24 MHz* : (at TA
125C) .
Flash security function
■
Generates interrupt request for task switching.
8/10-bit A/D converter: 15 channels
Detects low voltage (4.0 V 0.3 V) and resets automatically
Dual operation Flash memory (only devices 128
Kbytes Flash memory)
Up to 400 kbps transfer rate
DTP/External interrupt:
wakeup: 1 channel
Address matching detection for 6 address pointers.
Protects the content of Flash memory
(MB90F352x, MB90F357x only)
External bus interface
■
4 Mbytes external memory space
MB90F351E(S), MB90F351TE(S), MB90F352E(S),
MB90F352TE(S) : External bus Interface can not be used in
internal vector mode. It can be used only in external vector
mode.
* : If used exceeding TA 105 C, be sure to contact Cypress
for reliability limitations.
Page 2 of 84
MB90350E Series
Contents
Product Lineup1 (Without Clock supervisor function) 4
Product Lineup 2 (With Clock supervisor function) ..... 7
Packages and Product Correspondence ..................... 12
Pin Assignments ............................................................ 13
Pin Description ............................................................... 14
I/O Circuit Type ............................................................... 19
Handling Devices ............................................................ 22
Block Diagrams .............................................................. 27
Memory Map .................................................................... 33
I/O Map ............................................................................ 34
CAN Controllers .............................................................. 42
Interrupt Factors, Interrupt Vectors, Interrupt
Control Register ............................................................. 50
Electrical Characteristics ............................................... 51
Absolute Maximum Ratings ....................................... 51
Recommended Operating Conditions ....................... 53
DC Characteristics .................................................... 54
AC Characteristics ..................................................... 59
Clock Timing .............................................................. 59
Document Number: 002-04493 Rev. *A
Reset Standby Input .................................................. 62
Power On Reset ........................................................ 63
Clock Output Timing .................................................. 63
Bus Timing (Read) .................................................... 64
Bus Timing (Write) ..................................................... 66
Ready Input Timing ................................................... 67
Hold Timing ............................................................... 68
LIN-UART2/3 ............................................................. 69
Trigger Input Timing .................................................. 73
Timer Related Resource Input Timing ....................... 74
Timer Related Resource Output Timing .................... 74
I2C Timing ................................................................. 75
A/D Converter ............................................................ 76
Definition of A/D Converter Terms ........................... 80
Flash Memory Program/Erase Characteristics .......... 82
Ordering Information ..................................................... 83
Package Dimensions ...................................................... 85
Major Changes ............................................................... 87
Page 3 of 84
MB90350E Series
1. Product Lineup1 (Without Clock supervisor function)
■
Flash memory products
Part Number
Parameter
MB90F351E
MB90F352E
MB90F351TE
MB90F352TE
MB90F351ES
MB90F352ES
Type
Flash memory products
CPU
F2MC-16LX CPU
MB90F351TES
MB90F352TES
System clock
PLL clock multiplication circuit ( 1, 2, 3, 4, 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL 6)
ROM
64 Kbytes Flash memory : MB90F351E(S), MB90F351TE(S)
128 Kbytes Dual operation Flash memory (Erase/write and read can be operated at the same time) :
MB90F352E(S), MB90F352TE(S)
RAM
4 Kbytes
Emulator-specific power
supply*
Sub clock pin
(X0A, X1A)
(Max 100 kHz)
Yes
No
Clock supervisor
Low voltage/CPU
operation detection
reset
Operating voltage
No
No
Yes
No
Yes
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter/Flash programming
4.5 V to 5.5 V : at using external bus
Operating
temperature
40C to 125C
Package
LQFP-64
2 channels
LIN-UART
Wide range of baud rate settings using a dedicated baud rate generator (reload timer)
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C (400 kbps)
1 channel
15 channels
A/D converter
10-bit or 8-bit resolution
Conversion time : Min 3 s includes sample time (per one channel)
16-bit reload timer
(2 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys Machine clock frequency)
Supports External Event Count function.
Free-run Timer 0 (clock input FRCK0) corresponds to ICU0/1.
Free-run Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU4/5/6/7.
16-bit Free-run timer
(2 channels)
16-bit output
compare
Signals an interrupt when overflowing.
Supports Timer Clear when it matches Output Compare (ch.0, ch.4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys Machine clock frequency)
4 channels
Signals an interrupt when 16-bit free-run Timer matches with output compare registers.
A pair of compare registers can be used to generate an output signal.
(Continued)
Document Number: 002-04493 Rev. *A
Page 4 of 84
MB90350E Series
(Continued)
Part Number
Parameter
16-bit Input capture
8/16-bit
programmable pulse generator
MB90F351E
MB90F352E
MB90F351TE
MB90F352TE
MB90F351ES
MB90F352ES
MB90F351TES
MB90F352TES
6 channels
Retains 16-bit free-run timer value by (rising edge, falling edge or rising & falling edge) , signals an interrupt.
6 channels (16-bit)/10 channels (8-bit)
8-bit reload counters 12
8-bit reload registers for L pulse width 12
8-bit reload registers for H pulse width12
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler 8-bit reload counter.
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 s@fosc 4 MHz
(fsys Machine clock frequency, fosc Oscillation clock frequency)
1 channel
CAN interface
Compliant with CAN standard Version2.0 Part A and Part B.
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
16 prioritized message buffers for data and ID
Supports multiple messages.
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps.
8 channels
External interrupt
Can be used rising edge, falling edge, starting up by “H”/“L” level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA.
D/A converter
I/O ports
Virtually all external pins can be used as general purpose I/O port.
All push-pull outputs
Bit-wise settable as input/output or peripheral signal
Settable as CMOS schmitt trigger/ automotive inputs
TTL input level settable for external bus (only for external bus pin)
Flash memory
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10000 times
Data retention time : 20 years
Boot block configuration
Erase can be performed on each block.
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash (MB90F352E(S) and MB90F352TE(S) only)
Corresponding
evaluation name
*:
MB90V340E-102
MB90V340E-101
It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
Document Number: 002-04493 Rev. *A
Page 5 of 84
MB90350E Series
MASK ROM products/Evaluation products
Part Number
MB90351E
MB90351TE
MB90352E
MB90352TE
Parameter
■
Type
MB90351ES
MB90352ES
MB90351TES
MB90352TES
MB90V340E-1 MB90V340E-1
01
02
MASK ROM products
Evaluation products
F2MC-16LX CPU
CPU
System clock
PLL clock multiplication circuit (1, 2, 3, 4, 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL 6)
ROM
MASK ROM
64 Kbytes :
128 Kbytes :
MB90351E(S), MB90351TE(S)
MB90352E(S), MB90352TE(S)
RAM
Emulator-specific power
supply*
Sub clock pin
(X0A, X1A)
(Max 100 kHz)
4 Kbytes
30 Kbytes
Yes
Yes
No
Clock supervisor
Low voltage/CPU
operation detection
reset
Operating
voltage range
No
No
Yes
No
Yes
No
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter
4.5 V to 5.5 V : at using external bus
5 V 10
40C to 125C
Package
LQFP-64
PGA-299
2 channels
5 channels
Wide range of baud rate settings using a dedicated baud rate generator (reload timer)
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C (400 kbps)
1 channel
2 channels
15 channels
24 channels
A/D converter
10-bit or 8-bit resolution
Conversion time : Min 3 s includes sample time (per one channel)
16-bit reload timer
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys Machine clock frequency)
Supports External Event Count function.
2 channels
16-bit free-run timer
(2 channels)
Yes
No
Operating
temperature range
LIN-UART
External
Free-run Timer 0 (clock input FRCK0) corresponds to
ICU0/1.
Free-run Timer 1 (clock input FRCK1) corresponds to
ICU4/5/6/7, OCU4/5/6/7.
4 channels
Free-run Timer 0
corresponds to ICU0/1/2/3,
OCU0/1/2/3.
Free-run Timer 1
corresponds to ICU4/5/6/7,
OCU4/5/6/7.
Signals an interrupt when overflowing.
Supports Timer Clear when it matches Output Compare (ch.0, ch.4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys Machine clock frequency)
(Continued)
Document Number: 002-04493 Rev. *A
Page 6 of 84
MB90350E Series
(Continued)
Part Number
Parameter
16-bit output
compare
16-bit input capture
8/16-bit
programmable pulse generator
MB90351E
MB90352E
MB90351TE
MB90352TE
MB90351ES
MB90352ES
MB90351TES MB90V340E-1 MB90V340E-1
MB90352TES
01
02
4 channels
8 channels
Signals an interrupt when 16-bit free-run Timer matches output compare registers.
A pair of compare registers can be used to generate an output signal.
6 channels
8 channels
Retains 16-bit free-run timer value by (rising edge, falling edge, or the both edges), signals an interrupt.
6 channels (16-bit)/10 channels (8-bit)
8-bit reload counters 12
8-bit reload registers for L pulse width12
8-bit reload registers for H pulse width12
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler 8-bit reload counter.
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 s@fosc 4 MHz
(fsys Machine clock frequency, fosc Oscillation clock frequency)
1 channel
CAN interface
3 channels
Compliant with CAN standard Version 2.0 Part A and Part B.
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
16 prioritized message buffers for data and ID
Supports multiple messages.
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps.
8 channels
External interrupt
*:
2 channels
Virtually all external pins can be used as general purpose I/O port.
All push-pull outputs
Bit-wise settable as input/output or peripheral signal
Settable as CMOS schmitt trigger/ automotive inputs
TTL input level settable for external bus (only for external bus pin)
Flash memory
Corresponding
evaluation name
16 channels
Can be used rising edge, falling edge, starting up by “H”/“L” level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA.
D/A converter
I/O ports
8 channels (16-bit)/
16 channels (8-bit)
8-bit reload counters 16
8-bit reload registers for
L pulse width 16
8-bit reload registers for
H pulse width 16
MB90V340E-102
MB90V340E-101
It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
Document Number: 002-04493 Rev. *A
Page 7 of 84
MB90350E Series
2. Product Lineup 2 (With Clock supervisor function)
■
Flash memory products
Part Number
Parameter
MB90F356E
MB90F357E
MB90F356TE
MB90F357TE
MB90F356ES
MB90F357ES
Type
Flash memory products
CPU
F2MC-16LX CPU
MB90F356TES
MB90F357TES
System clock
On-chip PLL clock multiplier (1, 2, 3, 4, 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL 6)
ROM
64 Kbytes Flash memory : MB90F356E(S), MB90F356TE(S)
128 Kbytes Dual operation Flash memory (Erase/write and read can be operated at the
same time) : MB90F357E(S), MB90F357TE(S)
RAM
4 Kbytes
Emulator-specific power
supply*
Sub clock pin
(X0A, X1A)
Yes
No
Clock supervisor
Low voltage/CPU
operation detection
reset
Operating
voltage range
Yes
No
Yes
No
Yes
3.5 V to 5.5 V : at normal operating (not using A/D converter)
3.5 V to 5.5 V : at using A/D converter/Flash programming
3.5 V to 5.5 V : at using external bus
Operating
temperature range
40C to 125C
Package
LQFP-64
2 channels
LIN-UART
Wide range of baud rate settings using a dedicated baud rate generator (reload timer)
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C (400 kbps)
1 channel
15 channels
A/D converter
10-bit or 8-bit resolution
Conversion time : Min 3 s includes sample time (per one channel)
16-bit reload timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys Machine clock frequency)
Supports External Event Count function.
Free-run Timer 0 (clock input FRCK0) corresponds to ICU 0/1.
Free-run Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7.
16-bit free-run timer
(2 channels)
16-bit output
compare
Signals an interrupt when overflowing.
Supports Timer Clear when a match with Output Compare (Channel 0, 4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys Machine clock frequency)
4 channels
Signals an interrupt when 16-bit free-run Timer matches with output compare registers.
A pair of compare registers can be used to generate an output signal.
Document Number: 002-04493 Rev. *A
Page 8 of 84
MB90350E Series
(Continued)
Part Number
Parameter
16-bit input capture
8/16-bit
programmable pulse generator
MB90F356E
MB90F357E
MB90F356TE
MB90F357TE
MB90F356ES
MB90F357ES
MB90F356TES
MB90F357TES
6 channels
Retains 16-bit free-run timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.
6 channels (16-bit)/10 channels (8-bit)
8-bit reload counters 12
8-bit reload registers for L pulse width12
8-bit reload registers for H pulse width12
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler 8-bit reload counter.
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 s@fosc 4 MHz
(fsys Machine clock frequency, fosc Oscillation clock frequency)
1 channel
CAN interface
Conforms to CAN Specification Version 2.0 Part A and B.
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID
Supports multiple messages.
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps.
8 channels
External interrupt
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA.
D/A converter
I/O ports
Virtually all external pins can be used as general purpose I/O port.
All push-pull outputs
Bit-wise settable as input/output or peripheral module signal
Settable as CMOS schmitt trigger/ automotive inputs
TTL input level settable for external bus (only for external bus pin)
Flash memory
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10000 times
Data retention time : 20 years
Boot block configuration
Erase can be performed on each block.
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash (MB90F357x only)
Corresponding EVA name
*:
MB90V340E-104
MB90V340E-103
It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
Document Number: 002-04493 Rev. *A
Page 9 of 84
MB90350E Series
MASK ROM products/Evaluation products
Part Number
MB90356E
MB90356TE
MB90357E
MB90357TE
Parameter
■
MB90356ES
MB90357ES
MB90356TES
MB90357TES
MB90V340E-1 MB90V340E-1
03
04
F2MC-16LX CPU
CPU
System clock
On-chip PLL clock multiplier (1, 2, 3, 4, 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL 6)
ROM
MASK ROM
64 Kbytes
128 Kbytes
:MB90356E(S), MB90356TE(S)
:MB90357E(S), MB90357TE(S)
RAM
Emulator-specific power
supply*
Sub clock pin
(X0A, X1A)
4 Kbytes
30 Kbytes
Yes
Yes
No
Clock supervisor
Low voltage/CPU
operation detection
reset
Operating
voltage range
No
No
Yes
No
Yes
No
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter
4.5 V to 5.5 V : at using external bus
Package
5 V 10%
40C to 125C
LQFP-64
PGA-299
2 channels
5 channels
Wide range of baud rate settings using a dedicated baud rate generator (reload timer)
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
I2C (400 kbps)
1 channel
2 channels
15 channels
24 channels
A/D converter
10-bit or 8-bit resolution
Conversion time : Min 3 s includes sample time (per one channel)
16-bit reload timer
(4 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys Machine clock frequency)
Supports External Event Count function.
16-bit free-run timer
(2 channels)
Yes
Yes
Operating
temperature range
LIN-UART
External
Free-run Timer 0 (clock input FRCK0) corresponds to
ICU 0/1.
Free-run Timer 1 (clock input FRCK1) corresponds to
ICU 4/5/6/7, OCU 4/5/6/7.
Free-run Timer 0
corresponds to ICU 0/1/2/3,
OCU 0/1/2/3.
Free-run Timer 1
corresponds to ICU 4/5/6/7,
OCU 4/5/6/7.
Signals an interrupt when overflowing.
Supports Timer Clear when a match with Output Compare (Channel 0, 4) .
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys Machine clock frequency)
(Continued)
Document Number: 002-04493 Rev. *A
Page 10 of 84
MB90350E Series
(Continued)
Part Number
Parameter
16-bit output
compare
MB90356E
MB90357E
MB90356TE
MB90357TE
MB90356ES
MB90357ES
MB90356TES MB90V340E-1 MB90V340E-1
MB90357TES
03
04
4 channels
8 channels
Signals an interrupt when 16-bit free-run Timer matches with output compare registers.
A pair of compare registers can be used to generate an output signal.
6 channels
16-bit input capture
8/16-bit
programmable pulse generator
8 channels
Retains 16-bit free-run timer value by (rising edge, falling edge or rising & falling edge),
signals an interrupt.
6 channels (16-bit)/10 channels (8-bit)
8-bit reload counters12
8-bit reload registers for L pulse width 12
8-bit reload registers for H pulse width 12
8 channels (16-bit)/
16 channels (8-bit)
8-bit reload counters16
8-bit reload registers for
L pulse width16
8-bit reload registers for
H pulse width16
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler 8-bit reload counter.
Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 s@fosc 4 MHz
(fsys Machine clock frequency, fosc Oscillation clock frequency)
1 channel
CAN interface
3 channels
Conforms to CAN Specification Version 2.0 Part A and B.
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID
Supports multiple messages.
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps.
8 channels
External interrupt
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
extended intelligent I/O services (EI2OS) and DMA.
D/A converter
I/O ports
*:
2 channels
Virtually all external pins can be used as general purpose I/O port.
All push-pull outputs
Bit-wise settable as input/output or peripheral module signal
Settable as CMOS schmitt trigger/ automotive inputs
TTL input level settable for external bus (only for external bus pin)
Flash memory
Corresponding EVA name
16 channels
MB90V340E-104
MB90V340E-103
It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
Document Number: 002-04493 Rev. *A
Page 11 of 84
MB90350E Series
3. Packages and Product Correspondence
Package
MB90V340E-101
MB90V340E-102
MB90V340E-103
MB90V340E-104
MB90351E (S) , MB90351TE (S)
MB90F351E (S) , MB90F351TE (S)
MB90352E (S) , MB90352TE (S)
MB90F352E (S) , MB90F352TE (S)
MB90356E (S) , MB90356TE (S)
MB90F356E (S) , MB90F356TE (S)
MB90357E (S) , MB90357TE (S)
MB90F357E (S) , MB90F357TE (S)
PGA-299C-A01
FPT-64P-M23
(12.0 mm
, 0.65 mm pitch)
FPT-64P-M24
(10.0 mm
, 0.50 mm pitch)
: Yes, : No
Note : Refer to “Package Dimensions” for detail of each package.
Document Number: 002-04493 Rev. *A
Page 12 of 84
MB90350E Series
4. Pin Assignments
■
MB90351E (S) , MB90351TE (S) , MB90F351E (S) , MB90F351TE (S) , MB90352E (S) , MB90352TE (S) ,
MB90F352E (S) , MB90F352TE (S) , MB90356E (S) , MB90356TE (S) , MB90F356E (S) , MB90F356TE (S) ,
MB90357E (S) , MB90357TE (S) , MB90F357E (S) , MB90F357TE (S)
P11/AD09/TOT1
P12/AD10/SIN3/INT11R
P13/AD11/SOT3
P14/AD12/SCK3
P15/AD13
P17/AD15
P16/AD14
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
P24/A20/IN0
RST
X1
X0
Vss
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Vcc
49
32
P10/AD08/TIN1
C
50
31
P07/AD07/INT15
P25/A21/IN1/ADTG
51
30
P06/AD06/INT14
P44/SDA0/FRCK0
52
29
P05/AD05/INT13
P45/SCL0/FRCK1
53
28
P04/AD04/INT12
P30/ALE/IN4
54
27
P03/AD03/INT11
P31/RD/IN5
55
26
P02/AD02/INT10
P32/WRL/WR/INT10R
56
25
P01/AD01/INT9
P33/WRH
57
24
P00/AD00/INT8
P34/HRQ/OUT4
58
23
MD0
P35/HAK/OUT5
59
22
MD1
P36/RDY/OUT6
60
21
MD2
P37/CLK/OUT7
61
20
P41/X1A*
P60/AN0
62
19
P40/X0A*
P61/AN1
63
18
Vss
AVcc
64
17
P43/IN7/TX1
P42/IN6/RX1/INT9R
P56/AN14
P55/AN13
P53/AN11/TIN3
P54/AN12/TOT3
P52/AN10/SCK2
P51/AN9/SOT2
P50/AN8/SIN2
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
AVss
AVRH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(FPT-64P-M23, FPT-64P-M24)
* : Devices without S-suffix : X0A, X1A
Devices with S-suffix
: P40, P41
Document Number: 002-04493 Rev. *A
Page 13 of 84
MB90350E Series
5. Pin Description
Pin No.
Pin name
46
X1
47
X0
45
RST
I/O
Circuit
type*
A
E
P62 to P67
PPG4 (5) , 6 (7) , 8
(9) , A (B) ,
C (D) , E (F)
10
AN8
Analog input pins for A/D converter
Output pins for PPGs
General purpose I/O port
O
Serial data input pin for UART2
P51
General purpose I/O port
AN9
I
AN10
General purpose I/O port
I
SCK2
General purpose I/O port
I
TIN3
AN12
General purpose I/O port
I
TOT3
14, 15
P55, P56
AN13, AN14
IN6
RX1
I
F
Analog input pins for A/D converter
Data sample input pin for input capture ICU6
RX input pin for CAN1
External interrupt request input pin for INT9
P43
IN7
General purpose I/O ports
General purpose I/O port
INT9R
17
Analog input pin for A/D converter
Output pin for reload timer3
P42
16
Analog input pin for A/D converter
Event input pin for reload timer3
P54
13
Analog input pin for A/D converter
Serial clock I/O pin for UART2
P53
AN11
Analog input pin for A/D converter
Serial data output pin for UART2
P52
12
Analog input pin for A/D converter
SIN2
SOT2
11
Reset input pin
I
P50
9
Oscillation output pin
Oscillation input pin
General purpose I/O ports
AN2 to AN7
3 to 8
Function
General purpose I/O port
F
TX1
Data sample input pin for input capture ICU7
TX output pin for CAN1
P40, P41
F
General purpose I/O ports
(devices with S-suffix and MB90V340E-101/103)
X0A, X1A
B
X0A : Oscillation input pin for sub clock
X1A : Oscillation output pin for sub clock
(devices without S-suffix and MB90V340E-102/104)
19, 20
(Continued)
Document Number: 002-04493 Rev. *A
Page 14 of 84
MB90350E Series
Pin No.
Pin name
I/O
Circuit
type*
General purpose I/O ports. The register can be set to select whether to use a pull-up resistor.
This function is enabled in single-chip mode.
P00 to P07
24 to 31
AD00 to AD07
G
INT8 to INT15
33
AD08
General purpose I/O port. The register can be set to select whether to use a pull-up resistor.
This function is enabled in single-chip mode.
G
Event input pin for reload timer1
P11
General purpose I/O port. The register can be set to select whether to use a
pull-up resistor. This function is enabled in single-chip mode.
AD09
G
AD10
General purpose I/O port. The register can be set to select whether to use a pull-up resistor.
This function is enabled in single-chip mode.
N
SIN3
External interrupt request input pin for INT11
General purpose I/O port. The register can be set to select whether to use a pull-up resistor.
This function is enabled in single-chip mode.
P13
G
SOT3
AD12
Serial data output pin for UART3
G
SCK3
N
AD13
P16
38
Input/output pin for external bus address data bus bit 12.
This function is enabled when external bus is enabled.
Clock input/output pin for UART3
P15
37
Input/output pin for external bus address data bus bit 11.
This function is enabled when external bus is enabled.
General purpose I/O port. The register can be set to select whether to use a pull-up resistor.
This function is enabled in single-chip mode.
P14
36
Input/output pin for external bus address data bus bit 10. This function is enabled when external bus is enabled.
Serial data input pin for UART3
INT11R
AD11
Input/output pin for external bus address data bus bit 9. This function is
enabled when external bus is enabled.
Output pin for reload timer1
P12
35
Input/output pin for external bus address data bus bit 8.
This function is enabled when external bus is enabled.
TIN1
TOT1
34
Input/output pins of external address data bus lower 8 bits. This function is enabled when the
external bus is enabled.
External interrupt request input pins for INT8 to INT15
P10
32
Function
G
AD14
General purpose I/O port. The register can be set to select whether to use a pull-up resistor.
This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 13.
This function is enabled when external bus is enabled.
General purpose I/O port. The register can be set to select whether to use a pull-up resistor.
This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 14.
This function is enabled when external bus is enabled.
(Continued)
Document Number: 002-04493 Rev. *A
Page 15 of 84
MB90350E Series
Pin No.
Pin name
I/O
Circuit
type*
P17
39
G
AD15
A16 to A19
G
PPG9 (8)
PPGB (A)
PPGD (C)
PPGF (E)
51
G
A20
Output pin for A20 of the external address data bus. When the corresponding bit in the external
address output control register (HACR) is 0, the pin is
enabled as high address output pin A20.
IN0
Data sample input pin for input capture ICU0
P25
General purpose I/O port. The register can be set to select whether to use a pull-up resistor. In
external bus mode, the pin is enabled as a generalpurpose I/O port when the corresponding bit in the external address output control register
(HACR) is 1.
A21
G
Trigger input pin for A/D converter
P44
SDA0
General purpose I/O port
H
FRCK0
Serial data I/O pin for I2C 0
Input pin for the 16-bit Free-run Timer 0
P45
SCL0
Output pin for A21 of the external address data bus. When the corresponding bit in the external
address output control register (HACR) is 0, the pin is enabled as high address output pin A21.
Data sample input pin for input capture ICU1
ADTG
53
Output pins for A16 to A19 of the external address data bus.
When the corresponding bit in the external address output control register (HACR) is 0, the pins
are enabled as high address output pins A16 to A19.
General purpose I/O port. The register can be set to select whether to use a pull-up resistor. In
external bus mode, the pin is enabled as a generalpurpose I/O port when the corresponding bit in the external address output control register
(HACR) is 1.
IN1
52
Input/output pin for external bus address data bus bit 15.
This function is enabled when external bus is enabled.
Output pins for PPGs
P24
44
General purpose I/O port. The register can be set to select whether to use a pull-up resistor.
This function is enabled in single-chip mode.
General purpose I/O ports. The register can be set to select whether to use a pull-up resistor.
In external bus mode, the pins are enabled as a generalpurpose I/O port when the corresponding bit in the external address output control register
(HACR) is 1.
P20 to P23
40 to 43
Function
General purpose I/O port
H
FRCK1
Serial clock I/O pin for I2C 0
Input pin for the 16-bit Free-run Timer 1
(Continued)
Document Number: 002-04493 Rev. *A
Page 16 of 84
MB90350E Series
Pin No.
Pin name
I/O
Circuit
type*
General purpose I/O port. The register can be set to select whether to use a pull-up resistor.
This function is enabled in single-chip mode.
P30
54
55
56
ALE
G
Data sample input pin for input capture ICU4
P31
General purpose I/O port. The register can be set to select whether to use a pull-up resistor.
This function is enabled in single-chip mode.
RD
G
Data sample input pin for input capture ICU5
P32
General purpose I/O port. The register can be set to select whether to use a pull-up resistor.
This function is enabled either in single-chip mode or with the WR/WRL pin output disabled.
WR/WRL
57
G
Write strobe output pin for the data bus. This function is enabled when both the external bus
and the WR/WRL pin output are enabled. WRL is used to write-strobe 8 lower bits of the data
bus in 16-bit access. WR is used to write-strobe 8 bits of the data bus in 8-bit access.
External interrupt request input pin for INT10
G
General purpose I/O port. The register can be set to select whether to use a pull-up resistor.
This function is enabled either in single-chip mode, in
external bus 8-bit mode or with the WRH pin output disabled.
WRH
Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when the
external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH
output pin is enabled.
P34
General purpose I/O port. The register can be set to select whether to use a pull-up resistor.
This function is enabled either in single-chip mode or with the hold function disabled.
HRQ
G
OUT4
HAK
General purpose I/O port. The register can be set to select whether to use a pull-up resistor.
This function is enabled either in single-chip mode or with the hold function disabled.
G
OUT5
Hold acknowledge output pin. This function is enabled when both the
external bus and the hold function are enabled.
Wave form output pin for output compare OCU5
General purpose I/O port. The register can be set to select whether to use a pull-up resistor.
This function is enabled either in single-chip mode or with the external ready function disabled.
P36
RDY
Hold request input pin. This function is enabled when both the external bus and the hold function are enabled.
Wave form output pin for output compare OCU4
P35
60
Read strobe output pin for data bus. This function is enabled when external bus is enabled.
IN5
P33
59
Address latch enable output pin. This function is enabled when external bus is enabled.
IN4
INT10R
58
Function
G
OUT6
Ready input pin. This function is enabled when both the external bus and the external ready
function are enabled.
Wave form output pin for output compare OCU6
(Continued)
Document Number: 002-04493 Rev. *A
Page 17 of 84
MB90350E Series
(Continued)
Pin No.
Pin name
I/O
Circuit
type*
General purpose I/O port. The register can be set to select whether to use a pull-up resistor.
This function is enabled either in single-chip mode or with the CLK output disabled.
P37
61
CLK
G
OUT7
62, 63
P60, P61
AN0, AN1
Function
CLK output pin. This function is enabled when both the external bus and CLK output are enabled.
Wave form output pin for output compare OCU7
I
General purpose I/O ports
Analog input pins for A/D converter
64
AVCC
K
VCC power input pin for analog circuits
2
AVRH
L
Reference voltage input for the A/D converter. This power supply must be turned on or off
while a voltage higher than or equal to AVRH is applied to AVCC.
1
AVSS
K
VSS power input pin for analog circuits
22, 23
MD1, MD0
C
Input pins for specifying the operating mode
21
MD2
D
Input pin for specifying the operating mode
49
VCC
18, 48
VSS
50
C
K
Power (3.5 V to 5.5 V) input pin
Power (0 V) input pins
This is the power supply stabilization capacitor pin. It should be connected to a higher than or
equal to 0.1 F ceramic capacitor.
* : For the I/O circuit type, refer to “I/O Circuit Type”.
Document Number: 002-04493 Rev. *A
Page 18 of 84
MB90350E Series
6. I/O Circuit Type
Type
Circuit
Oscillation circuit
High-speed oscillation feedback
resistor = approx. 1 M
X1
A
Remarks
Xout
X0
Standby control signal
X1A
B
Oscillation circuit
Low-speed oscillation feedback
resistor = approx. 10 M
Xout
X0A
Standby control signal
■
MASK ROM device
CMOS hysteresis input pin
C
R
CMOS
hysteresis
inputs
■
Flash memory device
CMOS input pin
■
MASK ROM device
CMOS hysteresis input pin
R
D
CMOS
hysteresis
inputs
Pull-down resistor value: approx. 50 k
■
Flash memory device
CMOS input pin
Pull-down
resistor
No Pull-down
CMOS hysteresis input pin
Pull-up resistor value: approx. 50 k
E
Pull-up
resistor
R
CMOS
hysteresis
inputs
(Continued)
Document Number: 002-04493 Rev. *A
Page 19 of 84
MB90350E Series
Type
Circuit
Remarks
■
CMOS level output
(IOL = 4 mA, IOH 4 mA)
■
CMOS hysteresis inputs (With input
shutdown function when is standby)
■
Automotive input (With the standby-time input
shutdown function)
■
CMOS level output
(IOL = 4 mA, IOH 4 mA)
■
CMOS hysteresis inputs (With the standby-time
input shutdown function)
■
Automotive input (With the standby-time input
shutdown function)
■
TTL input (With the standby-time input shutdown
function)
■
Programmable pull-up resistor:
approx. 50 k
■
CMOS level output
(IOL = 3 mA, IOH 3 mA)
■
CMOS hysteresis inputs (With the standby-time
input shutdown function)
■
Automotive input (With the standby-time input
shutdown function)
P-ch
Pout
N-ch
Nout
F
R
CMOS
hysteresis inputs
Automotive input
Standby control for
input shutdown
Pull-up control
Pull-up
resistor
P-ch
P-ch
Pout
N-ch
Nout
G
R
CMOS
hysteresis inputs
Automotive input
TTL input
Standby control for
input shutdown
P-ch
Pout
N-ch
Nout
H
R
CMOS
hysteresis inputs
Automotive input
Standby control for
input shutdown
(Continued)
Document Number: 002-04493 Rev. *A
Page 20 of 84
MB90350E Series
Type
Circuit
Remarks
■
CMOS level output
(IOL = 4 mA, IOH = 4 mA)
■
CMOS hysteresis inputs (With the standby-time
input shutdown function)
■
Automotive input (With the standby-time input
shutdown function)
■
Analog input for A/D converter
P-ch
Pout
N-ch
Nout
I
R
CMOS
hysteresis inputs
Automotive input
Standby control for
input shutdown
Analog input
Protection circuit for power supply input
P-ch
K
N-ch
■
With the protection circuit of A/D
converter reference voltage power
input pin
■
Flash memory devices do not have a
protection circuit against VCC for pin
AVRH.
ANE
L
P-ch
N-ch
AVR
ANE
(Continued)
Document Number: 002-04493 Rev. *A
Page 21 of 84
MB90350E Series
(Continued)
Type
Circuit
Pull-up control
Pull-up
resistor
P-ch
P-ch
Remarks
■
CMOS level output
(IOL = 4 mA, IOH 4 mA)
■
CMOS inputs (With the standby-time
input shutdown function)
■
Automotive input (With the standby-time input
shutdown function)
■
TTL input (With the standby-time input shutdown
function)
■
Programmable pull-up resistor:
approx. 50 k
■
CMOS level output
(IOL = 4 mA, IOH 4 mA)
■
CMOS inputs (With the standby-time
input shutdown function)
■
Automotive input (With the standby-time input
shutdown function)
■
Analog input for A/D converter
Pout
N-ch
Nout
R
N
CMOS inputs
Automotive input
TTL input
Standby control for
input shutdown
P-ch
Pout
N-ch
Nout
R
O
CMOS inputs
Automotive input
Standby control for
input shutdown
Analog input
7. Handling Devices
1.
Preventing latch-up
CMOS IC may suffer latch-up under the following conditions :
■A
voltage higher than VCC or lower than VSS is applied to an input or output pin.
■A
voltage higher than the rated voltage is applied between VCC and VSS pins.
■The
AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply
voltage (VCC) .
2.
Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore
they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 k.
Unused I/O pins should be set to the output state and can be left open, or the input state with the above described connection.
Document Number: 002-04493 Rev. *A
Page 22 of 84
MB90350E Series
3.
Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90350E Series
X0
Open
4.
X1
Precautions for when not using a sub clock signal
X0A and X1A are oscillation pins for sub clock. If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on
the X0A pin, and leave the X1A pin open.
5.
Notes on during operation of PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode
is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Cypress
will not guarantee results of operations if such failure occurs.
6.
■
■
Treatment of Power Supply Pins (VCC/VSS)
If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected inside
of the device to prevent malfunction such as latch-up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard
for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally.
Connect VCC and VSS pins to the device from the current supply source at a possibly low impedance.
As a measure against power supply noise, it is recommended to connect a capacitor of about 0.1 F as a bypass capacitor between
VCC and VSS pins in the vicinity of VCC and VSS pins of the device.
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90350E
Series
Vcc
Vss
Vss
7.
Vcc
Pull-up/down resistors
The MB90350E series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors). Use external
components where needed.
8.
Crystal oscillator circuit
Noise around the X0/X1, or X0A/X1A pins may cause this device to operate abnormally. In the interest of stable operation it is strongly
recommended that printed circuit artwork places ground bypass capacitors as close as possible to the X0/X1, X0A/X1A and crystal
oscillator (or ceramic oscillator) and that oscillator lines do not cross the lines of other circuits.
Document Number: 002-04493 Rev. *A
Page 23 of 84
MB90350E Series
Please ask each crystal maker to evaluate the oscillational characteristics of the crystal and this device.
9.
Turning-on sequence of power supply to A/D converter and analog inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN14) after turning-on the digital power
supply (VCC) .Turn-off the digital power after turning off the A/D converter power
supply and analog inputs. In this case, make sure that the power supply voltage does not exceed the rated voltage of the A/D converter
(turning on/of the analog and digital power supplies simultaneously is acceptable).
10. Connection of unused pins of A/D converter if A/D converter is not used
Connect unused pins of A/D converter to AVCC VCC, AVSS AVRH VSS.
11. Notes on energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 s or more (0.2 V to 2.7 V) .
12. Stabilization of power supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage operating range.
Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should be controlled so that VCC ripple
variations (peak- to-peak values) at commercial frequencies (50 MHz/
60 MHz) fall below 10 of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
Document Number: 002-04493 Rev. *A
Page 24 of 84
MB90350E Series
13. Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed
circuit board so as to avoid noise.
Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of receiving wrong data due
to the noise.
14. Port 0 to port 3 output during power-on (External-bus mode)
As shown below, when power is turned on in external-bus mode, there is a possibility that output signal of
Port 0 to Port 3 might be unstable regardless of reset inputs.
1/2 VCC
VCC
Port 0 to Port 3
Port 0 to Port 3 outputs Port 0 to Port 3 outputs = Hi-Z
might be unstable.
15. Setting using CAN function
To use CAN function, please set “1” to DIRECT bit of CAN direct mode register (CDMR).
16. Flash security function
The security byte is located in the area of the Flash memory. If protection code 01H is written in the security byte, the Flash memory
is in the protected state by security.
Therefore please do not write 01H in this address if you do not use the security function.
Please refer to following table for the address of the security byte.
Product name
MB90F352E(S)
MB90F352TE(S)
MB90F357E(S)
MB90F357TE(S)
Flash memory size
Address for security bit
Embedded 1 Mbit Flash memory
FE0001H
17. Operation with TA 105C or more
If used exceeding TA 105C, please contact Cypress sales representatives for reliability limitations.
18. Low voltage/CPU operation reset circuit
The low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when a voltage drops below
a given voltage level. When a low voltage condition is detected, an internal reset signal is generated.
The CPU operation detection reset circuit is a 20-bit counter that uses oscillation as a count clock and generates an internal reset
signal if not cleared within a given time after startup.
(1) Low voltage detection reset circuit
Detection voltage
4.0 V 0.3 V
When a low voltage condition is detected, the low voltage detection flag (LVRC : LVRF) is set to “1” and an internal reset signal is
output.
Because the low voltage detection reset circuit continues to operate even in stop mode, detection of a low voltage condition generates
an internal reset and releases stop mode.
Document Number: 002-04493 Rev. *A
Page 25 of 84
MB90350E Series
During an internal RAM write cycle, low voltage reset is generated after the completion of writing. During the output of this internal
reset, the reset output from the low voltage detection reset circuit is suppressed.
(2) CPU operation detection reset circuit
The CPU operation detection reset circuit is a counter that prevents program runaway. The counter starts automatically after a
power-on reset, and must be continually and regularly cleared within a given time. If the given time interval elapses and the counter
has not been cleared, a cause such as infinite program looping is assumed and an internal reset signal is generated. The internal
reset generated from the CPU operation detection circuit has a width of 5 machine cycles.
Interval time
220/F
C
(approx. 262 ms*)
* : This value assumes the interval time at an oscillation clock frequency of 4 MHz.
During recovery from standby mode, the detection period is the maximum interval plus 20 s.
This circuit does not operate in modes where CPU operation is stopped.
The CPU operation detection reset circuit counter is cleared under any of the following conditions.
■“0”
writing to CL bit of LVRC register
■Internal
■Main
reset
oscillation clock stop
■Transit
to sleep mode
■Transit
to timebase timer mode and watch mode
19. Internal CR oscillation circuit
Parameter
Oscillation frequency
Oscillation stabilization wait time
Symbol
Value
Unit
Min
Typ
Max
fRC
50
100
200
kHz
tstab
100
s
Document Number: 002-04493 Rev. *A
Page 26 of 84
MB90350E Series
8. Block Diagrams
■
MB90V340E-101/102
X0
X0A*
RST
X1
X1A*
Clock
controller
F2MC-16LX
CPU
Free-run
timer 0
RAM
30 Kbytes
AN23 to AN0
AVRH
AVRL
IN7 to IN0
Output
compare
8 channels
OUT7 to OUT0
Free-run
timer 1
LIN-UART
5 channels
CAN
controller
3 channels
AVCC
AVSS
Input
capture
8 channels
Prescaler
5 channels
8/10-bit
A/D
converter
24 channels
F2MC-16LX Bus
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
FRCK0
16-bit
reload timer
4 channels
FRCK1
RX2 to RX0
TX2 to TX0
TIN3 to TIN0
TOT3 to TOT0
AD15 to AD00
A21 to A16
ADTG
ALE
DA00,DA01
PPGF to PPG0
SDA0,SDA1
SCL0,SCL1
10-bit
D/A
converter
2 channels
RD
External
bus
interface
8/16-bit
PPG
16/8 channels
I2C interface
2 channels
DMAC
WR/WRL
WRH
HRQ
HAK
RDY
CLK
DTP/
External
interrupt
Clock
monitor
INT7 to INT0
INT15 to INT8
(INT11R to INT9R)
CKOT
* : MB90V340E-102 only
Document Number: 002-04493 Rev. *A
Page 27 of 84
MB90350E Series
■
MB90V340E-103/104
X0
X0A*
RST
X1
X1A*
Clock
controller/Monitor
F2MC-16LX
CPU
Free-run
timer 0
Input
capture
8 channels
Output
compare
8 channels
CR oscillation
circuit
RAM
30 Kbytes
Prescaler
5 channels
LIN-UART
5 channels
AVCC
AVSS
AN23 to AN0
AVRH
AVRL
ADTG
8/10-bit
A/D
converter
24 channels
DA01, DA00
10-bit
D/A
converter
2 channels
PPGF to PPG0
SDA1, SDA0
SCL1, SCL0
F2MC-16LX Bus
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
Free-run
timer 1
DMA
IN7 to IN0
OUT7 to OUT0
FRCK1
CAN
controller
3 channels
RX2 to RX0
TX2 to TX0
16-bit
reload
timer
4 channels
TIN3 to TIN0
TOT3 to TOT0
External
bus
interface
8/16-bit
PPG
16/8 channels
I2C interface
2 channels
FRCK0
DTP/External
interrupt
Clock
monitor
AD15 to AD00
A23 to A16
ALE
RD
WRL
WRH
HRQ
HAK
RDY
CLK
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
CKOT
* : MB90V340E-104 only
Document Number: 002-04493 Rev. *A
Page 28 of 84
MB90350E Series
■
MB90351E (S) , MB90351TE (S) , MB90F351E (S) , MB90F351TE (S) , MB90352E (S) , MB90352TE (S) , MB90F352E (S)
MB90F352TE (S)
X0
X0A *1
RST
X1
X1A*1
Clock
controller
F2MC-16LX
CPU
Low voltage/
CPU operation
detection
reset*2
Free-run
timer 0
Input
capture
6 channels
RAM
4 Kbytes
ROM/Flash
128 Kbytes/
64 Kbytes
Output
compare
4 channels
Prescaler
2 channels
LIN-UART
2 channels
AVCC
AVSS
AN14 to AN0
AVRH
8/10-bit
A/D
converter
15 channels
F2MC-16LX Bus
SOT3, SOT2
SCK3, SCK2
SIN3, SIN2
Free-run
timer 1
CAN
controller
1 channel
16-bit
reload timer
2 channels
FRCK0
IN7 to IN4,
IN1, IN0
OUT7 to OUT4
FRCK1
RX1
TX1
TIN3, TIN1
TOT3, TOT1
AD15 to AD00
A21 to A16
ADTG
ALE
RD
PPGF to PPG8
PPG6, PPG4
SDA0
SCL0
8/16-bit
PPG
10/6 channels
External
bus
interface
WRH
HRQ
HAK
RDY
CLK
I2C interface
1 channel
DMAC
WR/WRL
DTP/
External
interrupt
INT15 to INT8
(INT11R to INT9
*1 : Only for devices without “S”-suffix
*2 : Only for devices with “T”-suffix
Document Number: 002-04493 Rev. *A
Page 29 of 84
MB90350E Series
■
MB90356E (S) , MB90356TE (S) , MB90F356E (S) , MB90F356TE (S) , MB90357E (S) , MB90357TE (S) , MB90F357E (S) ,
MB90F357TE (S)
X0
X0A*1
RST
X1
X1A*1
Clock
controller/Monitor
F2MC-16LX
CPU
CR
oscillation
circuit
Free-run
timer 0
Input
capture
6 channels
Output
compare
4 channels
Low voltage/
CPU operation
detector reset*2
RAM
4 Kbytes
Free-run
timer 1
Prescaler
2 channels
SOT3, SOT2
SCK3, SCK2
SIN3, SIN2
LIN-UART
2 channels
F2MC-16LX Bus
ROM/Flash
128 Kbytes/
64 Kbytes
CAN
controller
1 channel
16-bit
reload timer
4 channels
AVCC
AVSS
AN14 to AN0
AVRH
SDA0
SCL0
IN7 to IN4,
IN1, IN0
OUT7 to OUT4
FRCK1
RX1
TX1
TIN3, TIN1
TOT3, TOT1
AD15 to AD00
8/10-bit
A/D
converter
15 channels
ADTG
PPGF to PPG8
PPG6, PPG4
FRCK0
8/16-bit
PPG
10/6 channels
I2C interface
1 channel
A21 to A16
ALE
RD
External
bus
interface
WR/WRL
WRH
HRQ
HAK
RDY
CLK
External
interrupt
INT15 to INT8
(INT11R to INT9R)
DMAC
*1 : Only for devices without “S”-suffix
*2 : Only for devices with “T”-suffix
Document Number: 002-04493 Rev. *A
Page 30 of 84
MB90350E Series
9. Memory Map
MB90352E (S)
MB90352TE (S)
MB90F352E (S)
MB90F352TE (S)
MB90357E (S)
MB90357TE (S)
MB90F357E (S)
MB90F357TE (S)
MB90V340E-101
MB90V340E-102
MB90V340E-103
MB90V340E-104
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
F80000H
00FFFFH
ROM (FF bank)
ROM (FE bank)
FF0000H
FEFFFFH
ROM (FD bank)
FE0000H
FDFFFFH
ROM (FC bank)
ROM (FA bank)
ROM (FF bank)
FFFFFFH
ROM (FF bank)
FF0000H
ROM (FE bank)
FDFFFFH
External access
area
External access
area
ROM (FB bank)
C00100H
C00100H
ROM (F9 bank)
ROM (F8 bank)
00FFFFH
External access area
008000H
007FFFH
ROM
008000H (image of FF bank)
007FFFH
007900H
0078FFH
FFFFFFH
MB90351E (S)
MB90351TE (S)
MB90F351E (S)
MB90F351TE (S)
MB90356E (S)
MB90356TE (S)
MB90F356E (S)
MB90F356TE (S)
ROM
(image of FF bank)
Peripheral
00FFFFH
ROM
008000H (image of FF bank)
007FFFH
Peripheral
007900H
007900H
001100H
0010FFH
001100H
0010FFH
Peripheral
RAM 30 Kbytes
000100H
0000EFH
000000H
000100H
External access area
Peripheral
0000EFH
000000H
RAM 4 Kbytes
RAM 4 Kbytes
000100H
External access area
Peripheral
External access area
0000EFH
000000H
Peripheral
: No access
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective.
Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer
declaration.
For example, an attempt to access 00C000H practically accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF7FFFH is visible
only in bank FF.
Document Number: 002-04493 Rev. *A
Page 31 of 84
MB90350E Series
10. I/O Map
Address
Register
Abbreviation
Access
Resource name
Initial value
000000H
Port 0 Data Register
PDR0
R/W
Port 0
XXXXXXXXB
000001H
Port 1 Data Register
PDR1
R/W
Port 1
XXXXXXXXB
000002H
Port 2 Data Register
PDR2
R/W
Port 2
XXXXXXXXB
000003H
Port 3 Data Register
PDR3
R/W
Port 3
XXXXXXXXB
000004H
Port 4 Data Register
PDR4
R/W
Port 4
XXXXXXXXB
000005H
Port 5 Data Register
PDR5
R/W
Port 5
XXXXXXXXB
000006H
Port 6 Data Register
PDR6
R/W
Port 6
XXXXXXXXB
000007H to
00000AH
Reserved
00000BH
Port 5 Analog Input Enable Register
ADER5
R/W
Port 5, A/D
11111111B
00000CH
Port 6 Analog Input Enable Register
ADER6
R/W
Port 6, A/D
11111111B
00000DH
Reserved
00000EH
Input Level Select Register 0
ILSR0
R/W
Ports
00000000B
00000FH
Input Level Select Register 1
ILSR1
R/W
Ports
00000000B
000010H
Port 0 Direction Register
DDR0
R/W
Port 0
00000000B
000011H
Port 1 Direction Register
DDR1
R/W
Port 1
00000000B
000012H
Port 2 Direction Register
DDR2
R/W
Port 2
XX000000B
000013H
Port 3 Direction Register
DDR3
R/W
Port 3
00000000B
000014H
Port 4 Direction Register
DDR4
R/W
Port 4
XX000000B
000015H
Port 5 Direction Register
DDR5
R/W
Port 5
X0000000B
000016H
Port 6 Direction Register
DDR6
R/W
Port 6
00000000B
W
UART2, UART3
X00XXXXXB
000017H to
000019H
00001AH
Reserved
SIN input Level Setting Register
00001BH
DDRA
Reserved
00001CH
Port 0 Pull-up Control Register
PUCR0
R/W
Port 0
00000000B
00001DH
Port 1 Pull-up Control Register
PUCR1
R/W
Port 1
00000000B
00001EH
Port 2 Pull-up Control Register
PUCR2
R/W
Port 2
00000000B
00001FH
Port 3 Pull-up Control Register
PUCR3
R/W
Port 3
00000000B
000020H to
000037H
Reserved
(Continued)
Document Number: 002-04493 Rev. *A
Page 32 of 84
MB90350E Series
Address
Register
000038H
PPG 4 Operation Mode Control Register
Abbreviation
Access
PPGC4
W, R/W
000039H
PPG 5 Operation Mode Control Register
PPGC5
W, R/W
00003AH
PPG 4/5 Count Clock Select Register
PPG45
R/W
00003BH
Address Detect Control Register 1
PACSR1
R/W
00003CH
PPG 6 Operation Mode Control Register
PPGC6
W, R/W
00003DH
PPG 7 Operation Mode Control Register
PPGC7
W, R/W
00003EH
PPG 6/7 Count Clock Select Register
PPG67
R/W
000040H
PPG 8 Operation Mode Control Register
PPGC8
000041H
PPG 9 Operation Mode Control Register
PPGC9
W, R/W
000042H
PPG 8/9 Count Clock Select Register
PPG89
R/W
00003FH
Resource name
16-bit Programmable Pulse
Generator 4/5
Initial value
0X000XX1B
0X000001B
000000X0B
Address Match
Detection 1
16-bit Programmable Pulse
Generator 6/7
00000000B
0X000XX1B
0X000001B
000000X0B
Reserved
000043H
W, R/W
16-bit Programmable Pulse
Generator 8/9
0X000XX1B
0X000001B
000000X0B
Reserved
000044H
PPG A Operation Mode Control Register
000045H
PPG B Operation Mode Control Register
PPGCB
W, R/W
000046H
PPG A/B Count Clock Select Register
PPGAB
R/W
000048H
PPG C Operation Mode Control Register
PPGCC
000049H
PPG D Operation Mode Control Register
PPGCD
W,R/W
00004AH
PPG C/D Count Clock Select Register
PPGCD
R/W
000047H
PPGCA
W, R/W
16-bit Programmable Pulse
Generator A/B
0X000XX1B
0X000001B
000000X0B
Reserved
00004BH
W,R/W
16-bit Programmable Pulse
Generator C/D
0X000XX1B
0X000001B
000000X0B
Reserved
00004CH
PPG E Operation Mode Control Register
00004DH
PPG F Operation Mode Control Register
PPGCF
W,R/W
00004EH
PPG E/F Count Clock Select Register
PPGEF
R/W
00004FH
PPGCE
W,R/W
16-bit Programmable Pulse
Generator E/F
0X000XX1B
0X000001B
000000X0B
Reserved
000050H
Input Capture Control Status
Register 0/1
ICS01
R/W
000051H
Input Capture Edge Register 0/1
ICE01
R/W, R
000052H,
000053H
Input Capture 0/1
00000000B
XXX0X0XXB
Reserved
000054H
Input Capture Control Status
Register 4/5
ICS45
R/W
000055H
Input Capture Edge Register 4/5
ICE45
R
000056H
Input Capture Control Status
Register 6/7
ICS67
R/W
000057H
Input Capture Edge Register 6/7
ICE67
R/W, R
Input Capture 4/5
00000000B
XXXXXXXXB
Input Capture 6/7
00000000B
XXX000XXB
(Continued)
Document Number: 002-04493 Rev. *A
Page 33 of 84
MB90350E Series
Address
Register
Abbreviation
000058H
to
00005BH
Access
Resource name
Initial value
Reserved
Output Compare Control Status
Register 4
OCS4
00005DH
Output Compare Control Status
Register 5
OCS5
R/W
00005EH
Output Compare Control Status
Register 6
OCS6
R/W
00005FH
Output Compare Control Status
Register 7
OCS7
R/W
000060H
Timer Control Status Register 0
TMCSR0
R/W
000061H
Timer Control Status Register 0
TMCSR0
R/W
000062H
Timer Control Status Register 1
TMCSR1
R/W
000063H
Timer Control Status Register 1
TMCSR1
R/W
000064H
Timer Control Status Register 2
TMCSR2
R/W
000065H
Timer Control Status Register 2
TMCSR2
R/W
000066H
Timer Control Status Register 3
TMCSR3
R/W
000067H
Timer Control Status Register 3
TMCSR3
R/W
000068H
A/D Control Status Register 0
ADCS0
R/W
000XXXX0B
0000000XB
00005CH
R/W
0000XX00B
Output Compare 4/5
0XX00000B
0000XX00B
Output Compare 6/7
0XX00000B
16-bit Reload Timer 0
16-bit Reload Timer 1
16-bit Reload Timer 2
16-bit Reload Timer 3
00000000B
XXXX0000B
00000000B
XXXX0000B
00000000B
XXXX0000B
00000000B
XXXX0000B
000069H
A/D Control Status Register 1
ADCS1
R/W
00006AH
A/D Data Register 0
ADCR0
R
00006BH
A/D Data Register 1
ADCR1
R
00006CH
ADC Setting Register 0
ADSR0
R/W
00000000B
00006DH
ADC Setting Register 1
ADSR1
R/W
00000000B
00006EH
Low Voltage/CPU Operation Detection Reset
Control Register
LVRC
R/W, W
Low Voltage/CPU
Operation Detection Reset
00111000B
00006FH
ROM Mirror Function Select Register
ROMM
W
ROM Mirror
XXXXXXX1B
000070H
to
00007FH
000080H
to
00008FH
A/D Converter
00000000B
XXXXXX00B
Reserved
Reserved for CAN controller 1. Refer to “CAN Controllers”
000090H
to
00009AH
Reserved
(Continued)
Document Number: 002-04493 Rev. *A
Page 34 of 84
MB90350E Series
Address
Register
Abbreviation
Access
DCSR
R/W
Resource name
Initial value
00009BH
DMA Descriptor Channel Specification Register
00009CH
DMA Status Register L Register
DSRL
R/W
00009DH
DMA Status Register H Register
DSRH
R/W
00009EH
Address Detect Control Register 0
PACSR0
R/W
Address Match
Detection 0
00000000B
00009FH
Delayed Interrupt/Release Register
DIRR
R/W
Delayed Interrupt
XXXXXXX0B
0000A0H
Low-power Consumption Mode
Control Register
LPMCR
W,R/W
Low Power
Consumption
Control Circuit
00011000B
0000A1H
Clock Selection Register
CKSCR
R,R/W
Low Power
Consumption
Control Circuit
11111100B
DMA
00000000B
0000A2H,
0000A3H
00000000B
DMA
00000000B
00000000B
Reserved
0000A4H
DMA Stop Status Register
DSSR
R/W
0000A5H
Automatic Ready Function Selection
Register
ARSR
W
0000A6H
External Address Output Control Register
HACR
W
0000A7H
Bus Control Signal Selection Register
ECSR
W
0000A8H
Watchdog Control Register
WDTC
R,W
Watchdog Timer
XXXXX111B
0000A9H
Timebase Timer Control Register
TBTC
W,R/W
Timebase timer
1XX00100B
0000AAH
Watch Timer Control Register
WTC
R,R/W
Watch Timer
1X001000B
0000ABH
External Memory
Access
0011XX00B
00000000B
0000000XB
Reserved
0000ACH
DMA Enable Register L Register
DERL
R/W
0000ADH
DMA Enable Register H Register
DERH
R/W
0000AEH
Flash Control Status Register
(Flash Devices only. Otherwise
reserved)
FMCS
R,R/W
0000AFH
DMA
Flash memory
00000000B
00000000B
000X0000B
Reserved
0000B0H
Interrupt Control Register 00
ICR00
W,R/W
00000111B
0000B1H
Interrupt Control Register 01
ICR01
W,R/W
00000111B
0000B2H
Interrupt Control Register 02
ICR02
W,R/W
00000111B
0000B3H
Interrupt Control Register 03
ICR03
W,R/W
0000B4H
Interrupt Control Register 04
ICR04
W,R/W
0000B5H
Interrupt Control Register 05
ICR05
W,R/W
00000111B
0000B6H
Interrupt Control Register 06
ICR06
W,R/W
00000111B
0000B7H
Interrupt Control Register 07
ICR07
W,R/W
00000111B
0000B8H
Interrupt Control Register 08
ICR08
W,R/W
00000111B
00000111B
Interrupt Control
00000111B
(Continued)
Document Number: 002-04493 Rev. *A
Page 35 of 84
MB90350E Series
Address
Register
Abbreviation
Access
0000B9H
Interrupt Control Register 09
ICR09
W,R/W
00000111B
0000BAH
Interrupt Control Register 10
ICR10
W,R/W
00000111B
0000BBH
Interrupt Control Register 11
ICR11
W,R/W
00000111B
0000BCH
Interrupt Control Register 12
ICR12
W,R/W
0000BDH
Interrupt Control Register 13
ICR13
W,R/W
00000111B
0000BEH
Interrupt Control Register 14
ICR14
W,R/W
00000111B
0000BFH
Interrupt Control Register 15
ICR15
W,R/W
00000111B
0000C0H
to 0000C9H
Resource name
Interrupt Control
Initial value
00000111B
Reserved
0000CAH
External Interrupt Enable Register 1
ENIR1
R/W
00000000B
0000CBH
External Interrupt Source Register 1
EIRR1
R/W
XXXXXXXXB
0000CCH
External Interrupt Level Register 1
ELVR1
R/W
0000CDH
External Interrupt Level Register 1
ELVR1
R/W
00000000B
0000CEH
External Interrupt Source Select
Register
EISSR
R/W
00000000B
0000CFH
PLL/Sub clock Control register
PSCCR
W
0000D0H
DMA Buffer Address Pointer L
Register
BAPL
R/W
XXXXXXXXB
0000D1H
DMA Buffer Address Pointer M
Register
BAPM
R/W
XXXXXXXXB
0000D2H
DMA Buffer Address Pointer H
Register
BAPH
R/W
XXXXXXXXB
0000D3H
DMA Control Register
DMACS
R/W
0000D4H
I/O Register Address Pointer L
Register
IOAL
R/W
XXXXXXXXB
0000D5H
I/O Register Address Pointer H
Register
IOAH
R/W
XXXXXXXXB
0000D6H
Data Counter L Register
DCTL
R/W
XXXXXXXXB
0000D7H
Data Counter H Register
DCTH
R/W
XXXXXXXXB
0000D8H
Serial Mode Register 2
SMR2
W,R/W
00000000B
0000D9H
Serial Control Register 2
SCR2
W,R/W
00000000B
0000DAH
Reception/Transmission Data
Register 2
RDR2/TDR2
R/W
00000000B
0000DBH
Serial Status Register 2
SSR2
R,R/W
000000XXB
External Interrupt 1
PLL
DMA
UART2
00000000B
XXXX0000B
XXXXXXXXB
00001000B
0000DCH
Extended Communication Control Register 2
ECCR2
R,W,
R/W
0000DDH
Extended Status/Control Register 2
ESCR2
R/W
00000100B
0000DEH
Baud Rate Generator Register 20
BGR20
R/W
00000000B
(Continued)
Document Number: 002-04493 Rev. *A
Page 36 of 84
MB90350E Series
Address
0000DFH
Register
Baud Rate Generator Register 21
Abbreviation
Access
Resource name
Initial value
BGR21
R/W
UART2
00000000B
0000E0H
to 0000EFH
Reserved
0000F0H
to 0000FFH
External area
007900H
to
007907H
Reserved
007908H
Reload Register L4
007909H
Reload Register H4
00790AH
00790BH
00790CH
PRLL4
R/W
PRLH4
R/W
Reload Register L5
PRLL5
R/W
Reload Register H5
PRLH5
R/W
Reload Register L6
PRLL6
R/W
XXXXXXXXB
16-bit Programmable
Pulse
Generator 4/5
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bit Programmable
Pulse
Generator 6/7
00790DH
Reload Register H6
PRLH6
R/W
00790EH
Reload Register L7
PRLL7
R/W
00790FH
Reload Register H7
PRLH7
R/W
XXXXXXXXB
007910H
Reload Register L8
PRLL8
R/W
XXXXXXXXB
007911H
Reload Register H8
PRLH8
R/W
007912H
Reload Register L9
PRLL9
R/W
007913H
Reload Register H9
PRLH9
R/W
007914H
Reload Register LA
PRLLA
R/W
16-bit Programmable
Pulse
Generator 8/9
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bit Programmable
Pulse
Generator A/B
007915H
Reload Register HA
PRLHA
R/W
007916H
Reload Register LB
PRLLB
R/W
007917H
Reload Register HB
PRLHB
R/W
XXXXXXXXB
007918H
Reload Register LC
PRLLC
R/W
XXXXXXXXB
007919H
Reload Register HC
PRLHC
R/W
00791AH
Reload Register LD
PRLLD
R/W
00791BH
Reload Register HD
PRLHD
R/W
00791CH
Reload Register LE
PRLLE
R/W
16-bit Programmable
Pulse
Generator C/D
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bit Programmable
Pulse
Generator E/F
00791DH
Reload Register HE
PRLHE
R/W
00791EH
Reload Register LF
PRLLF
R/W
00791FH
Reload Register HF
PRLHF
R/W
XXXXXXXXB
007920H
Input Capture Register 0
IPCP0
R
XXXXXXXXB
007921H
Input Capture Register 0
IPCP0
R
007922H
Input Capture Register 1
IPCP1
R
007923H
Input Capture Register 1
IPCP1
R
Input Capture 0/1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
Document Number: 002-04493 Rev. *A
Page 37 of 84
MB90350E Series
Address
Register
007924H
to
007927H
Abbreviation
Access
Resource name
Initial value
Reserved
007928H
Input Capture Register 4
IPCP4
R
007929H
Input Capture Register 4
IPCP4
R
00792AH
Input Capture Register 5
IPCP5
R
XXXXXXXXB
Input Capture 4/5
XXXXXXXXB
XXXXXXXXB
00792BH
Input Capture Register 5
IPCP5
R
XXXXXXXXB
00792CH
Input Capture Register 6
IPCP6
R
XXXXXXXXB
00792DH
Input Capture Register 6
IPCP6
R
00792EH
Input Capture Register 7
IPCP7
R
00792FH
Input Capture Register 7
IPCP7
R
XXXXXXXXB
XXXXXXXXB
007930H
to
007937H
Input Capture 6/7
XXXXXXXXB
XXXXXXXXB
Reserved
007938H
Output Compare Register 4
OCCP4
R/W
007939H
Output Compare Register 4
OCCP4
R/W
00793AH
Output Compare Register 5
OCCP5
R/W
00793BH
Output Compare Register 5
OCCP5
R/W
XXXXXXXXB
00793CH
Output Compare Register 6
OCCP6
R/W
XXXXXXXXB
00793DH
Output Compare Register 6
OCCP6
R/W
00793EH
Output Compare Register 7
OCCP7
R/W
00793FH
Output Compare Register 7
OCCP7
R/W
XXXXXXXXB
007940H
Timer Data Register 0
TCDT0
R/W
00000000B
007941H
Timer Data Register 0
TCDT0
R/W
007942H
Timer Control Status Register 0
TCCSL0
R/W
007943H
Timer Control Status Register 0
TCCSH0
R/W
0XXXXXXXB
007944H
Timer Data Register 1
TCDT1
R/W
00000000B
007945H
Timer Data Register 1
TCDT1
R/W
007946H
Timer Control Status Register 1
TCCSL1
R/W
007947H
Timer Control Status Register 1
TCCSH1
R/W
Timer Register 0/Reload Register 0
TMR0/TMRL
R0
R/W
Timer Register 1/Reload Register 1
TMR1/TMRL
R1
R/W
Timer Register 2/Reload Register 2
TMR2/TMRL
R2
R/W
Timer Register 3/Reload Register 3
TMR3/TMRL
R3
R/W
007948H
007949H
00794AH
00794BH
00794CH
00794DH
00794EH
00794FH
R/W
R/W
R/W
R/W
Output Compare 4/5
Output Compare 6/7
Free-run Timer 0
Free-run Timer 1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
00000000B
00000000B
00000000B
0XXXXXXXB
16-bit Reload
Timer 0
XXXXXXXXB
16-bit Reload
Timer 1
XXXXXXXXB
16-bit Reload
Timer 2
XXXXXXXXB
16-bit Reload
Timer 3
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
Document Number: 002-04493 Rev. *A
Page 38 of 84
MB90350E Series
Address
Register
Abbreviation
Access
Resource name
Initial value
007950H
Serial Mode Register 3
SMR3
W, R/W
00000000B
007951H
Serial Control Register 3
SCR3
W, R/W
00000000B
007952H
Reception/Transmission Data
Register 3
RDR3/TDR3
R/W
00000000B
007953H
Serial Status Register 3
SSR3
R,R/W
007954H
Extended Communication Control
Register 3
ECCR3
R,W,
R/W
007955H
Extended Status Control Register 3
ESCR3
R/W
00000100B
007956H
Baud Rate Generator Register 30
BGR30
R/W
00000000B
007957H
Baud Rate Generator Register 31
BGR31
R/W
00000000B
007958H,
007959H
007960H
00001000B
000000XXB
Reserved
Clock supervisor Control Register
007961H
to
00796DH
00796EH
UART3
CSVCR
R, R/W
Clock Supervisor
00011100B
R/W
CAN Clock Sync
XXXXXXX0B
Reserved
CAN Direct Mode Register
00796FH
CDMR
Reserved
007970H
I2C Bus Status Register 0
IBSR0
R
00000000B
007971H
I2C Bus Control Register 0
IBCR0
W,R/W
00000000B
007972H
007973H
007974H
007975H
I2C 10-bit Slave Address Register 0
I2C 10-bit Slave Address Mask
Register 0
2
ITBAL0
R/W
00000000B
ITBAH0
R/W
00000000B
ITMKL0
R/W
ITMKH0
R/W
00111111B
I2C Interface 0
11111111B
007976H
I C 7-bit Slave Address Register 0
ISBA0
R/W
00000000B
007977H
I2C 7-bit Slave Address Mask Register 0
ISMK0
R/W
01111111B
007978H
I2 C
IDAR0
R/W
00000000B
data register 0
007979H,
00797AH
00797BH
Reserved
I2C Clock Control Register 0
00797CH
to 0079A1H
ICCR0
R/W
00011111B
Reserved
0079A2H
Flash Write Control Register 0
FWR0
R/W
0079A3H
Flash Write Control Register 1
FWR1
R/W
0079A4H
Sector Change Setting Register 0
SSR0
R/W
0079A5H
to
0079C1H
0079C2H
I2C Interface 0
Dual Operation
Flash
00000000B
00000000B
00XXXXX0B
Reserved
Clock modulator Control Register
CMCR
R, R/W
Clock Modulator
0001X000B
(Continued)
Document Number: 002-04493 Rev. *A
Page 39 of 84
MB90350E Series
(Continued)
Address
Register
Abbreviation
0079C3H to
0079DFH
Access
Resource name
Initial value
Reserved
0079E0H
Detect Address Setting Register 0
PADR0
R/W
XXXXXXXXB
0079E1H
Detect Address Setting Register 0
PADR0
R/W
XXXXXXXXB
0079E2H
Detect Address Setting Register 0
PADR0
R/W
XXXXXXXXB
0079E3H
Detect Address Setting Register 1
PADR1
R/W
0079E4H
Detect Address Setting Register 1
PADR1
R/W
0079E5H
Detect Address Setting Register 1
PADR1
R/W
XXXXXXXXB
0079E6H
Detect Address Setting Register 2
PADR2
R/W
XXXXXXXXB
0079E7H
Detect Address Setting Register 2
PADR2
R/W
XXXXXXXXB
0079E8H
Detect Address Setting Register 2
PADR2
R/W
XXXXXXXXB
0079E9H
to
0079EFH
Address Match
Detection 0
XXXXXXXXB
XXXXXXXXB
Reserved
0079F0H
Detect Address Setting Register 3
PADR3
R/W
XXXXXXXXB
0079F1H
Detect Address Setting Register 3
PADR3
R/W
XXXXXXXXB
0079F2H
Detect Address Setting Register 3
PADR3
R/W
XXXXXXXXB
0079F3H
Detect Address Setting Register 4
PADR4
R/W
0079F4H
Detect Address Setting Register 4
PADR4
R/W
0079F5H
Detect Address Setting Register 4
PADR4
R/W
XXXXXXXXB
0079F6H
Detect Address Setting Register 5
PADR5
R/W
XXXXXXXXB
0079F7H
Detect Address Setting Register 5
PADR5
R/W
XXXXXXXXB
0079F8H
Detect Address Setting Register 5
PADR5
R/W
XXXXXXXXB
Address Match
Detection 1
0079F9H
to
007BFFH
Reserved
007C00H to
007DFFH
Reserved for CAN controller 1. Refer to “CAN Controllers”
007E00H
to 007FFFH
Reserved
XXXXXXXXB
XXXXXXXXB
Notes : Initial value of “X” represents unknown value.
Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
addresses results reading unknown value.
11. CAN Controllers
■
Compliant with CAN standard Version2.0 Part A and Part B
- Supports tr12ansmission/reception in standard frame and extended frame formats
■
Supports transmitting of data frames by receiving remote frames
■
16 transmitting/receiving message buffers
- 29-bit ID and 8-byte data
- Multi-level message buffer configuration
■
Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask
- Two acceptance mask registers in either standard frame format or extended frame formats
■
Bit rate programmable from 10 kbps to 2 Mbps (when input clock is at 16 MHz)
Document Number: 002-04493 Rev. *A
Page 40 of 84
MB90350E Series
List of Control Registers
Address
CAN1
000080H
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
Register
Abbreviation
Access
Initial Value
Message buffer enable register
BVALR
R/W
00000000B
00000000B
Transmit request register
TREQR
R/W
00000000B
00000000B
Transmit cancel register
TCANR
W
00000000B
00000000B
Transmission complete register
TCR
R/W
00000000B
00000000B
Receive complete register
RCR
R/W
00000000B
00000000B
Remote request receiving register
RRTRR
R/W
00000000B
00000000B
Receive overrun register
ROVRR
R/W
00000000B
00000000B
Reception interrupt
enable register
RIER
R/W
00000000B
00000000B
(Continued)
Document Number: 002-04493 Rev. *A
Page 41 of 84
MB90350E Series
(Continued)
Address
CAN1
007D00H
007D01H
007D02H
007D03H
007D04H
007D05H
007D06H
007D07H
007D08H
007D09H
007D0AH
007D0BH
007D0CH
007D0DH
007D0EH
007D0FH
Register
Abbreviation
Access
Initial Value
Control status register
CSR
R/W, W
R/W, R
0XXXX0X1B
00XXX000B
Last event indicator register
LEIR
R/W
000X0000B
XXXXXXXXB
Receive/transmit error counter
RTEC
R
00000000B
00000000B
Bit timing register
BTR
R/W
11111111B
X1111111B
IDE register
IDER
R/W
XXXXXXXXB
XXXXXXXXB
Transmit RTR register
TRTRR
R/W
00000000B
00000000B
Remote frame receive waiting
register
RFWTR
R/W
XXXXXXXXB
XXXXXXXXB
Transmit interrupt
enable register
TIER
R/W
00000000B
00000000B
007D10H
007D11H
007D12H
Acceptance mask
select register
AMSR
R/W
XXXXXXXXB
XXXXXXXXB
007D13H
007D14H
007D15H
007D16H
Acceptance mask register 0
AMR0
R/W
007D18H
007D1AH
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007D17H
007D19H
XXXXXXXXB
XXXXXXXXB
Acceptance mask register 1
007D1BH
Document Number: 002-04493 Rev. *A
AMR1
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Page 42 of 84
MB90350E Series
List of Message Buffers (ID Registers)
Address
CAN1
007C00H
to
007C1FH
Register
Abbreviation
Access
Initial Value
General-purpose RAM
R/W
XXXXXXXXB
to
XXXXXXXXB
007C20H
007C21H
007C22H
ID register 0
IDR0
R/W
XXXXXXXXB
XXXXXXXXB
007C23H
007C24H
007C25H
007C26H
ID register 1
IDR1
R/W
007C28H
007C2AH
ID register 2
IDR2
R/W
007C2BH
007C2EH
ID register 3
IDR3
R/W
007C30H
007C32H
ID register 4
IDR4
R/W
007C34H
007C36H
ID register 5
IDR5
R/W
007C38H
007C3AH
ID register 6
IDR6
R/W
007C3CH
007C3EH
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C3BH
007C3DH
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C37H
007C39H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C33H
007C35H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C2FH
007C31H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C2CH
007C2DH
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C27H
007C29H
XXXXXXXXB
XXXXXXXXB
ID register 7
007C3FH
IDR7
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
Document Number: 002-04493 Rev. *A
Page 43 of 84
MB90350E Series
(Continued)
Address
CAN1
Register
Abbreviation
Access
007C40H
007C41H
007C42H
ID register 8
IDR8
R/W
007C44H
007C46H
ID register 9
IDR9
R/W
007C48H
007C4AH
ID register 10
IDR10
R/W
007C4CH
007C4EH
ID register 11
IDR11
R/W
007C50H
007C52H
ID register 12
IDR12
R/W
007C54H
007C56H
ID register 13
IDR13
R/W
007C58H
007C5AH
ID register 14
IDR14
R/W
007C5CH
007C5EH
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C5BH
007C5DH
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C57H
007C59H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C53H
007C55H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C4FH
007C51H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C4BH
007C4DH
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C47H
007C49H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
007C43H
007C45H
Initial Value
ID register 15
007C5FH
Document Number: 002-04493 Rev. *A
IDR15
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Page 44 of 84
MB90350E Series
List of Message Buffers (DLC Registers and Data Registers)
Address
CAN1
007C60H
007C61H
007C62H
007C63H
007C64H
007C65H
007C66H
007C67H
007C68H
007C69H
007C6AH
007C6BH
007C6CH
007C6DH
007C6EH
007C6FH
007C70H
007C71H
007C72H
007C73H
007C74H
007C75H
007C76H
007C77H
007C78H
007C79H
007C7AH
007C7BH
007C7CH
007C7DH
007C7EH
007C7FH
Register
Abbreviation
Access
Initial Value
DLC register 0
DLCR0
R/W
XXXXXXXXB
DLC register 1
DLCR1
R/W
XXXXXXXXB
DLC register 2
DLCR2
R/W
XXXXXXXXB
DLC register 3
DLCR3
R/W
XXXXXXXXB
DLC register 4
DLCR4
R/W
XXXXXXXXB
DLC register 5
DLCR5
R/W
XXXXXXXXB
DLC register 6
DLCR6
R/W
XXXXXXXXB
DLC register 7
DLCR7
R/W
XXXXXXXXB
DLC register 8
DLCR8
R/W
XXXXXXXXB
DLC register 9
DLCR9
R/W
XXXXXXXXB
DLC register 10
DLCR10
R/W
XXXXXXXXB
DLC register 11
DLCR11
R/W
XXXXXXXXB
DLC register 12
DLCR12
R/W
XXXXXXXXB
DLC register 13
DLCR13
R/W
XXXXXXXXB
DLC register 14
DLCR14
R/W
XXXXXXXXB
DLC register 15
DLCR15
R/W
XXXXXXXXB
(Continued)
Document Number: 002-04493 Rev. *A
Page 45 of 84
MB90350E Series
Address
Register
Abbreviation
Access
Initial Value
007C80H
to
007C87H
Data register 0
(8 bytes)
DTR0
R/W
XXXXXXXXB
to
XXXXXXXXB
007C88H
to
007C8FH
Data register 1
(8 bytes)
DTR1
R/W
XXXXXXXXB
to
XXXXXXXXB
007C90H
to
007C97H
Data register 2
(8 bytes)
DTR2
R/W
XXXXXXXXB
to
XXXXXXXXB
007C98H
to
007C9FH
Data register 3
(8 bytes)
DTR3
R/W
XXXXXXXXB
to
XXXXXXXXB
007CA0H
to
007CA7H
Data register 4
(8 bytes)
DTR4
R/W
XXXXXXXXB
to
XXXXXXXXB
007CA8H
to
007CAFH
Data register 5
(8 bytes)
DTR5
R/W
XXXXXXXXB
to
XXXXXXXXB
007CB0H
to
007CB7H
Data register 6
(8 bytes)
DTR6
R/W
XXXXXXXXB
to
XXXXXXXXB
007CB8H
to
007CBFH
Data register 7
(8 bytes)
DTR7
R/W
XXXXXXXXB
to
XXXXXXXXB
007CC0H
to
007CC7H
Data register 8
(8 bytes)
DTR8
R/W
XXXXXXXXB
to
XXXXXXXXB
007CC8H
to
007CCFH
Data register 9
(8 bytes)
DTR9
R/W
XXXXXXXXB
to
XXXXXXXXB
007CD0H
to
007CD7H
Data register 10
(8 bytes)
DTR10
R/W
XXXXXXXXB
to
XXXXXXXXB
007CD8H
to
007CDFH
Data register 11
(8 bytes)
DTR11
R/W
XXXXXXXXB
to
XXXXXXXXB
007CE0H
to
007CE7H
Data register 12
(8 bytes)
DTR12
R/W
XXXXXXXXB
to
XXXXXXXXB
007CE8H
to
007CEFH
Data register 13
(8 bytes)
DTR13
R/W
XXXXXXXXB
to
XXXXXXXXB
CAN1
(Continued)
Document Number: 002-04493 Rev. *A
Page 46 of 84
MB90350E Series
(Continued)
Address
Register
Abbreviation
Access
Initial Value
007CF0H
to
007CF7H
Data register 14
(8 bytes)
DTR14
R/W
XXXXXXXXB
to
XXXXXXXXB
007CF8H
to
007CFFH
Data register 15
(8 bytes)
DTR15
R/W
XXXXXXXXB
to
XXXXXXXXB
CAN1
Document Number: 002-04493 Rev. *A
Page 47 of 84
MB90350E Series
12. Interrupt Factors, Interrupt Vectors, Interrupt Control Register
Interrupt cause
EI2OS
corresponding
DMA ch
number
Interrupt vector
Number
Address
#08
FFFFDCH
#09
FFFFD8H
#10
FFFFD4H
#11
FFFFD0H
#12
FFFFCCH
#13
FFFFC8H
#14
FFFFC4H
#15
FFFFC0H
#16
FFFFBCH
Reset
N
INT9 instruction
N
Exception
N
Reserved
N
Reserved
N
CAN 1 RX / Input Capture 6
Y1
CAN 1 TX/NS / Input Capture 7
Y1
I2 C
N
Reserved
N
16-bit Reload Timer 0
Y1
0
#17
FFFFB8H
16-bit Reload Timer 1
Y1
1
#18
FFFFB4H
16-bit Reload Timer 2
Y1
2
#19
FFFFB0H
16-bit Reload Timer 3
Y1
#20
FFFFACH
PPG 4/5
N
#21
FFFFA8H
PPG 6/7
N
#22
FFFFA4H
PPG 8/9/C/D
N
#23
FFFFA0H
PPG A/B/E/F
N
#24
FFFF9CH
Timebase Timer
N
#25
FFFF98H
External Interrupt 8 to 11
Y1
3
#26
FFFF94H
Watch Timer
N
#27
FFFF90H
External Interrupt 12 to 15
Y1
4
#28
FFFF8CH
A/D Converter
Y1
5
#29
FFFF88H
Free-run Timer 0 /
free-run Timer 1
N
#30
FFFF84H
Input Capture 4/5
Y1
6
#31
FFFF80H
Output Compare 4/5
Y1
7
#32
FFFF7CH
Input Capture 0/1
Y1
8
#33
FFFF78H
Output Compare 6/7
Y1
9
#34
FFFF74H
Reserved
N
10
#35
FFFF70H
Reserved
N
11
#36
FFFF6CH
UART 3 RX
Y2
12
#37
FFFF68H
UART 3 TX
Y1
13
#38
FFFF64H
Interrupt control
register
Number
Address
ICR00
0000B0H
ICR01
0000B1H
ICR02
0000B2H
ICR03
0000B3H
ICR04
0000B4H
ICR05
0000B5H
ICR06
0000B6H
ICR07
0000B7H
ICR08
0000B8H
ICR09
0000B9H
ICR10
0000BAH
ICR11
0000BBH
ICR12
0000BCH
ICR13
0000BDH
(Continued)
Document Number: 002-04493 Rev. *A
Page 48 of 84
MB90350E Series
(Continued)
EI2OS
corresponding
DMA ch
number
UART 2 RX
Y2
UART 2 TX
Y1
Flash Memory
N
Delayed Interrupt
N
Interrupt cause
Interrupt control
register
Interrupt vector
Number
Address
14
#39
FFFF60H
15
#40
FFFF5CH
#41
FFFF58H
#42
FFFF54H
Number
Address
ICR14
0000BEH
ICR15
0000BFH
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N
Notes :
: Unusable
The peripheral resources sharing the ICR register have the same interrupt level.
When the peripheral resources sharing the ICR register use extended intelligent I/O service, only one
can use EI2OS at a time.
When either of the two peripheral resources sharing the ICR register specifies EI2OS, the other one
cannot use interrupts.
13. Electrical Characteristics
13.1 Absolute Maximum Ratings
Parameter
Power supply voltage*1
Input voltage*
1
Output voltage*
1
Maximum Clamp Current
Total Maximum Clamp Current
“L” level maximum output current
Symbol
Remarks
VSS 6.0
V
VSS 0.3
VSS 6.0
V
VCC AVCC*2
AVRH
VSS 0.3
VSS 6.0
V
AVCCAVRH*2
VI
VSS 0.3
VSS 6.0
V
*3
VO
VSS 0.3
VSS 6.0
V
*3
ICLAMP
4.0
4.0
mA
*5
40
mA
*5
15
mA
*4
|ICLAMP|
IOL
IOL
IOLAV
IOH
“H” level average output current
IOHAV
“H” level maximum overall output current
IOH
IOHAV
Power consumption
PD
Operating temperature
TA
Storage temperature
Unit
VSS 0.3
IOLAV
“H” level average overall output current
Max
VCC
“L” level average output current
“L” level average overall output current
Min
AVCC
“L” level maximum overall output current
“H” level maximum output current
Rating
TSTG
4
mA
*4
100
mA
*4
50
mA
*4
15
mA
*4
4
mA
*4
100
mA
*4
50
mA
*4
454
mW
40
105
C
40
125
C
55
150
C
*6
(Continued)
Document Number: 002-04493 Rev. *A
Page 49 of 84
MB90350E Series
(Continued)
*1: This parameter is based on VSS AVSS 0 V
*2: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does
not exceed AVCC when the power is switched on.
*3: VI and VO should not exceed VCC 0.3 V. VI should not exceed the specified ratings. However if the maximum current to/from an
input is limited by some means with external components, the ICLAMP rating supersedes the
VI rating.
*4: Applicable to pins:
P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45, P50 to P56, P60 to P67
*5: Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45,
P50 to P56 (for evaluation device : P50 to P55) , P60 to P67
Use within recommended operating conditions.
Use at DC voltage (current)
The B signal should always be applied a connecting limit resistance between the B signal and the
microcontroller.
The value of the limiting resistance should be set so that when the B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
Note that if a B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
Note that if the B input is applied during power-on, the power supply is provided from the pins and the resulting
power supply voltage may not be sufficient to operate the power-on reset.
Care must be taken not to leave the B input pin open.
Recommended circuit sample:
• Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
B input (0 V to 16 V)
N-ch
R
*6 : If used exceeding TA 105C, be sure to contact Cypress for reliability limitations.
WARNING:
Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-04493 Rev. *A
Page 50 of 84
MB90350E Series
13.2 Recommended Operating Conditions
Parameter
Power supply voltage
Symbol
VCC,
AVCC
(VSS AVSS 0 V)
Value
Unit
Remarks
Min
Typ
Max
4.0
5.0
5.5
V
Under normal operation
3.5
5.0
5.5
V
Under normal operation, when not using the A/D converter and not Flash programming.
4.5
5.0
5.5
V
When External bus is used.
3.0
5.5
V
Maintains RAM data in stop mode
Smoothing capacitor
CS
0.1
1.0
F
Operating temperature
TA
40
Use a ceramic capacitor or comparable
capacitor of the AC characteristics. Bypass capacitor at
the VCC pin should be greater than this capacitor.
125
C
*
* : If used exceeding TA 105C, be sure to contact Cypress for reliability limitations.
C Pin Connection Diagram
C
CS
WARNING:
The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
Document Number: 002-04493 Rev. *A
Page 51 of 84
MB90350E Series
13.3 DC Characteristics
Parameter
“H” level
input
voltage
(At VCC
5 V 10)
“L” level
input
voltage
(At VCC
5 V 10)
Symbol
(TA 40C to 125C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Pin
Condition
Value
Min
Typ
Max
Unit
Remarks
VIHS
0.8 VCC
VCC 0.3
V
Pin inputs if CMOS
hysteresis input levels are selected (except P12, P15, P44,
P45, P50)
VIHA
0.8 VCC
VCC 0.3
V
Pin inputs if
Automotive input
levels are selected
VIHT
2.0
VCC 0.3
V
Pin inputs if TTL input levels
are selected
VIHS
0.7 VCC
VCC 0.3
V
P12, P15, P50 inputs if CMOS
input levels are selected
VIHI
0.7 VCC
VCC 0.3
V
P44, P45 inputs if CMOS hysteresis input levels are selected
VIHR
0.8 VCC
VCC 0.3
V
RST input pin (CMOS hysteresis)
VIHM
VCC 0.3
VCC 0.3
V
MD input pin
VILS
VSS 0.3
0.2 VCC
V
Pin inputs if CMOS
hysteresis input levels are selected (except P12, P15, P44,
P45, P50)
VILA
VSS 0.3
0.5 VCC
V
Pin inputs if
Automotive input
levels are selected
VILT
VSS 0.3
0.8
V
Pin inputs if TTL
input levels are selected
VILS
VSS 0.3
0.3 VCC
V
P12, P15, P50 inputs if CMOS
input levels are selected
VILI
VSS 0.3
0.3 VCC
V
P44, P45 inputs if CMOS hysteresis input levels are selected
VILR
VSS 0.3
0.2 VCC
V
RST input pin (CMOS hysteresis)
VILM
VSS 0.3
VSS 0.3
V
MD input pin
Output “H”
voltage
VOH
Normal outputs
VCC 4.5 V,
IOH 4.0 mA
VCC 0.5
V
Output “H”
voltage
VOHI
I2C current
outputs
VCC 4.5 V,
IOH 3.0 mA
VCC 0.5
V
(Continued)
Document Number: 002-04493 Rev. *A
Page 52 of 84
MB90350E Series
(TA 40C to 125C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Parameter
Output “L”
voltage
Symbol
VOL
Pin
Normal
outputs
2
I C current
outputs
Condition
Value
Unit
Min
Typ
Max
VCC 4.5 V,
IOL 4.0 mA
0.4
V
VCC 4.5 V,
IOL 3.0 mA
0.4
V
VCC 5.5 V,
VSS < VI < VCC
1
1
µA
Remarks
Output “L”
voltage
VOLI
Input leak
current
IIL
Pull-up
resistance
RUP
P00 to P07,
P10 to P17,
P20 to P25,
P30 to P37,
RST
25
50
100
k
Pull-down
resistance
RDOWN
MD2
25
50
100
k
VCC 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
48
60
mA
VCC 5.0 V,
Internal frequency : 24 MHz,
At writing Flash memory.
53
65
mA
Flash memory
devices
VCC 5.0 V,
Internal frequency : 24 MHz,
At erasing Flash memory.
58
70
mA
Flash memory
devices
VCC 5.0 V,
Internal frequency : 24 MHz,
At Sleep mode.
25
35
mA
0.3
0.8
mA
Devices
without
“T”-suffix
0.4
1.0
mA
Devices
with “T”-suffix
4
7
mA
ICC
Power supply
current
ICCS
VCC
ICTS
ICTSPLL
6
VCC 5.0 V,
Internal frequency : 2 MHz,
At Main Timer mode
VCC 5.0 V,
Internal frequency : 24 MHz,
At PLL Timer mode,
external frequency 4 MHz
Except Flash
memory devices
(Continued)
Document Number: 002-04493 Rev. *A
Page 53 of 84
MB90350E Series
(TA 40C to 125C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Parameter
Symbol
Pin
Condition
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
supervisor,
At sub clock operation
TA = 25C
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock
supervisor,
At sub clock operation
TA = 25C
Power supply
current
ICCL
VCC
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At sub clock operation
TA = 25C
Value
Min
Typ
70
100
100
Max
140
200
200
Unit
Remarks
A
MB90351E
MB90F351E
MB90352E
MB90F352E
MB90356E
MB90F356E
MB90357E
MB90F357E
µA
MB90356E
MB90F356E
MB90357E
MB90F357E
µA
MB90356ES
MB90F356ES
MB90357ES
MB90F357ES
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
supervisor,
At sub clock operation
TA = 25C
120
240
µA
MB90351TE
MB90F351TE
MB90352TE
MB90F352TE
MB90356TE
MB90F356TE
MB90357TE
MB90F357TE
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock
supervisor,
At sub clock operation
TA = 25C
150
300
µA
MB90356TE
MB90F356TE
MB90357TE
MB90F357TE
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At sub clock operation
TA = 25C
150
300
µA
MB90356TES
MB90F356TES
MB90357TES
MB90F357TES
(Continued)
Document Number: 002-04493 Rev. *A
Page 54 of 84
MB90350E Series
(TA 40C to 125C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Parameter
Symbol
Pin
Condition
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
supervisor,
At sub sleep
TA = 25C
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock
supervisor,
At sub sleep
TA = 25C
Power supply
current
ICCLS
VCC
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At sub sleep
TA = 25C
Value
Min
Typ
20
60
60
Max
50
200
200
Unit
Remarks
A
MB90351E
MB90F351E
MB90352E
MB90F352E
MB90356E
MB90F356E
MB90357E
MB90F357E
A
MB90356E
MB90F356E
MB90357E
MB90F357E
A
MB90356ES
MB90F356ES
MB90357ES
MB90F357ES
VCC = 5.0 V,
Internal frequency: 8 kHz,
At sub sleep
TA = 25C
70
150
A
MB90351TE
MB90F351TE
MB90352TE
MB90F352TE
MB90356TE
MB90F356TE
MB90357TE
MB90F357TE
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock
supervisor,
At sub sleep
TA = 25C
110
300
A
MB90356TE
MB90F356TE
MB90357TE
MB90F357TE
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At sub sleep
TA = 25C
110
300
A
MB90356TES
MB90F356TES
MB90357TES
MB90F357TES
(Continued)
Document Number: 002-04493 Rev. *A
Page 55 of 84
MB90350E Series
(Continued)
Parameter
(TA 40C to 125C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Symbol
Pin
VCC
CIN
Document Number: 002-04493 Rev. *A
Unit
Remarks
10
35
A
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock supervisor,
At watch mode
TA = 25C
25
150
A
MB90356E
MB90F356E
MB90357E
MB90F357E
A
MB90356ES
MB90F356ES
MB90357ES
MB90F357ES
A
MB90351TE
MB90F351TE
MB90352TE
MB90F352TE
MB90356TE
MB90F356TE
MB90357TE
MB90F357TE
A
MB90356TE
MB90F356TE
MB90357TE
MB90F357TE
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
supervisor,
At watch mode
TA = 25C
VCC 5.0 V,
At stop mode,
TA 25C
Other than
C, AVCC, AVSS,
AVRH, VCC, VSS
Max
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At watch mode
TA = 25C
Input capacity
Typ
MB90351E
MB90F351E
MB90352E
MB90F352E
MB90356E
MB90F356E
MB90357E
MB90F357E
VCC = 5.0 V,
Internal frequency: 8 kHz,
During operating clock
supervisor,
At watch mode
TA = 25C
ICCH
Value
Min
VCC = 5.0 V,
Internal frequency: 8 kHz,
During stopping clock
supervisor,
At watch mode
TA = 25C
VCC = 5.0 V,
Internal CR oscillation/
4 division,
At watch mode
TA = 25C
ICCT
Power supply
current
Condition
25
60
80
150
140
250
80
250
A
MB90356TES
MB90F356TES
MB90357TES
MB90F357TES
7
25
A
Devices without
“T”-suffix
60
130
A
Devices with
“T”-suffix
5
15
pF
Page 56 of 84
MB90350E Series
13.4 AC Characteristics
13.4.1 Clock Timing
Parameter
(TA 40C to 125C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Symbol
Pin
Value
Max
3
16
MHz
1/2 (at PLL stop)
When using an oscillation circuit
4
16
MHz
1 multiplied PLL
When using an oscillation circuit
4
12
MHz
2 multiplied PLL
When using an oscillation circuit
4
8
MHz
3 multiplied PLL
When using an oscillation circuit
4
6
MHz
4 multiplied PLL
When using an oscillation circuit
4
MHz
6 multiplied PLL
When using an oscillation circuit
3
24
MHz
1/2 (at PLL stop),
When using an external clock
4
24
MHz
1 multiplied PLL
When using an external clock
4
12
MHz
2 multiplied PLL
When using an external clock
4
8
MHz
3 multiplied PLL
When using an external clock
4
6
MHz
4 multiplied PLL
When using an external clock
4
MHz
6 multiplied PLL
When using an external clock
—
32.768
100
kHz
When using sub clock
333
ns
When using an oscillation circuit
333
ns
When using an external clock
s
fC
X0
fCL
Clock cycle time
Input clock pulse width
Input clock rise and fall time
X0A, X1A
Remarks
Typ
X0, X1
Clock frequency
Unit
Min
X0, X1
62.5
X0
41.67
tCYLL
X0A, X1A
10
30.5
—
PWH, PWL
X0
10
PWHL, PWLL
X0A
5
15.2
s
Duty ratio should be about
30 to 70.
tCR, tCF
X0
5
ns
When using an external clock
tCYL
ns
(Continued)
Document Number: 002-04493 Rev. *A
Page 57 of 84
MB90350E Series
(Continued)
(TA 40C to 125C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Parameter
Symbol
Pin
Internal operating clock frequency
(machine clock)
fCP
Internal operating clock cycle time
(machine clock)
Value
Unit
Remarks
Min
Typ
Max
1.5
24
MHz
When using main clock
fCPL
8.192
50
kHz
When using sub clock
tCP
41.67
666
ns
When using main clock
tCPL
20
122.1
s
When using sub clock
*: The limitation is in the range of the clock frequency when PLL is used. Use within the range in graph of “· PLL guaranteed
operation range External clock frequency and internal operation clock frequency“.
Clock Timing
tCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCF
tCR
tCYLL
0.8 VCC
X0A
0.2 VCC
PWHL
PWLL
tCF
Document Number: 002-04493 Rev. *A
tCR
Page 58 of 84
MB90350E Series
PLL guaranteed operation range
Power supply voltage VCC (V)
Guaranteed operation range
5.5
Guaranteed A/D converter
operation range
4.0
3.5
Guaranteed PLL operation range
1.5
4
24
Main clock fCP (MHz)
Guaranteed operation range of MB90350E series
Guaranteed A/D converter operation range
×6
Internal clock fCP (MHz)
24
×4
×3
×2
×1
16
× 1/2
(PLL off)
12
8
4.0
1.5
3 4
12
8
24
16
External clock fC (MHz) *
* : When using crystal oscillator or ceramic oscillator, the maximum clock frequency is 16 MHz.
External clock frequency and internal operation clock frequency
13.4.2 Reset Standby Input
Parameter
Reset input
time
Symbol
tRSTL
(TA 40C to 125C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Pin
RST
Document Number: 002-04493 Rev. *A
Value
Unit
Remarks
Min
Max
500
ns
Under normal operation
Oscillation time of oscillator* 100 s
s
In Stop mode, Sub Clock mode,
Sub Sleep mode and Watch
mode
100
s
In Main timer mode and PLL
timer mode
Page 59 of 84
MB90350E Series
* : Oscillation time of oscillator is the time that the amplitude reaches 90. In the crystal oscillator, the oscillation
time is between several ms to tens of ms. In ceramic oscillators, the oscillation time is between hundreds
of s to several ms. With an external clock, the oscillation time is 0 ms.
Under normal operation:
tRSTL
RST
0.2 VCC
0.2 VCC
In Stop mode, Sub Clock mode, Sub Sleep mode and, Watch mode:
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation
clock
100 μs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
13.4.3 Power On Reset
Parameter
Power on rise time
Power off time
(TA 40C to 125C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Symbol
Pin
Condition
tR
VCC
tOFF
VCC
Value
Unit
Min
Max
0.05
30
ms
1
ms
Remarks
Waiting time until power-on
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Document Number: 002-04493 Rev. *A
Page 60 of 84
MB90350E Series
Note : If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you start up smoothly by
restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while
not using the PLL clock. However, if voltage drops are within
1 V/s, you can operate while using the PLL clock.
VCC
We recommend the slope for
a rise of 50 mV/ms maximum.
3V
Holds RAM data
VSS
13.4.4 Clock Output Timing
Parameter
(TA 40C to 105C, VCC 5.0 V 10, VSS 0.0 V, fCP 24 MHz)
Symbol
Pin
Condition
Cycle time
tCYC
CLK
CLK CLK
tCHCL
CLK
Value
Min
62.5
41.67
20
13
Max
Unit
Remarks
ns
fCP 16 MHz
ns
fCP 24 MHz
ns
fCP 16 MHz
ns
fCP 24 MHz
tCYC
tCHCL
CLK
2.4 V
2.4 V
0.8 V
Document Number: 002-04493 Rev. *A
Page 61 of 84
MB90350E Series
13.4.5 Bus Timing (Read)
Parameter
(TA = –40C to +105C, VCC = 5.0 V 10 , VSS = 0.0 V, fCP 24 MHz)
Symbol
Pin
Condition
Value
Min
Max
Unit
ALE pulse width
tLHLL
ALE
tCP/2 10
ns
Valid address ALE time
tAVLL
ALE, A21 to A16, AD15 to
AD00
tCP/2 20
ns
ALE Address valid time
tLLAX
ALE, AD15 to AD00
tCP/2 15
ns
Valid address RD time
tAVRL
A21 to A16,
AD15 to AD00, RD
tCP 15
ns
Valid address Valid data input
tAVDV
A21 to A16,
AD15 to AD00
5 tCP/2 60
ns
(n*+3/2) tCP 20
ns
(n*+3/2) tCP 50
ns
RD pulse width
tRLRH
RD
RD Valid data input
tRLDV
RD, AD15 to AD00
RD Data hold time
tRHDX
RD, AD15 to AD00
RD ALE time
tRHLH
RD, ALE
tCP/2 15
RD Address valid time
tRHAX
RD, A21 to A16
tCP/2 10
Valid address CLK time
tAVCH
A21 to A16,
AD15 to AD00,
CLK
tCP/2 16
RD CLK time
tRLCH
RD, CLK
tCP/2 15
ALE RD time
tLLRL
ALE, RD
tCP/2 15
0
ns
ns
ns
ns
ns
ns
* : Number of ready cycles
Document Number: 002-04493 Rev. *A
Page 62 of 84
MB90350E Series
For 1 cycle of auto-ready
tRLCH
tAVCH
2.4 V
CLK
2.4 V
tLLAX
tAVLL
ALE
2.4 V
tRHLH
2.4 V
2.4 V
0.8 V
tLHLL
tAVRL
tRLRH
2.4 V
RD
0.8 V
tLLRL
tRHAX
A21 to A16
2.4 V
2.4 V
0.8 V
0.8 V
tRLDV
tRHDX
tAVDV
AD15 to AD00
Document Number: 002-04493 Rev. *A
2.4 V
0.8 V
Address
2.4 V
VIH
0.8 V
VIL
Read data
VIH
VIL
Page 63 of 84
MB90350E Series
13.4.6 Bus Timing (Write)
Parameter
(TA = –40C to +105C, VCC = 5.0 V 10 , VSS = 0.0 V, fCP 24 MHz)
Value
Symbol
Pin
Condition
Valid address WR time
tAVWL
A21 to A16, AD15
to AD00, WR
WR pulse width
tWLWH
Valid data output WR time
tDVWH
WR Data hold time
tWHDX
AD15 to AD00, WR
WR Address valid time
tWHAX
A21 to A16, WR
tCP/2 10
WR ALE time
tWHLH
WR, ALE
tCP/2 15
WR CLK time
tWLCH
WR, CLK
tCP/2 15
Min
Max
tCP15
WR
(n*+3/2)tCP 20
AD15 to AD00, WR
(n*+3/2)tCP 20
15
Unit
ns
ns
ns
ns
ns
ns
ns
* : Number of ready cycles
For 1 cycle of auto-ready
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
2.4 V
WR (WRL, WRH)
0.8 V
tWHAX
A21 to A16
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
AD15 to AD00
Document Number: 002-04493 Rev. *A
2.4 V
0.8 V
Address
2.4 V
0.8 V
Write data
tWHDX
2.4 V
0.8 V
Page 64 of 84
MB90350E Series
13.4.7 Ready Input Timing
Parameter
(TA = –40C to +105C, VCC = 5.0 V 10 , VSS = 0.0 V, fCP 24 MHz)
Symbol
Pin
RDY set-up time
tRYHS
RDY
RDY hold time
tRYHH
RDY
Condition
Value
Min
45
Units
Max
32
0
Remarks
ns
fCP 16 MHz
ns
fCP 24 MHz
ns
Note : If the RDY set-up time is insufficient, use the auto-ready function.
2.4 V
CLK
ALE
RD/WR
RDY
(When WAIT is not used.)
RDY
(When WAIT is used.)
Document Number: 002-04493 Rev. *A
tRYHS
tRYHH
VIH
VIH
VIL
Page 65 of 84
MB90350E Series
13.4.8 Hold Timing
Parameter
(TA = –40C to +105C, VCC = 5.0 V 10 , VSS = 0.0 V, fCP 24 MHz)
Symbol
Pin
Condition
Pin floating HAK time
tXHAL
HAK
HAK time Pin valid time
tHAHV
HAK
Value
Units
Min
Max
30
tCP
ns
tCP
2 tCP
ns
Note : There is more than 1 machine cycle from when HRQ pin reads in until the HAK is changed.
2.4 V
HAK
0.8 V
tHAHV
tXHAL
Each pin
Document Number: 002-04493 Rev. *A
2.4 V
0.8 V
Hi-Z
2.4 V
0.8 V
Page 66 of 84
MB90350E Series
13.4.9 LIN-UART2/3
■
Bit setting: ESCR:SCES = 0, ECCR:SCDE = 0
Parameter
(TA 40C to 125C, VCC 5.0 V 10, fCP 24 MHz, VSS 0 V)
Symbol
Pin
tSCYC
SCK2, SCK3
SCK SOT delay time
tSLOVI
SCK2, SCK3
SOT2, SOT3
Valid SIN SCK
tIVSHI
SCK2, SCK3
SIN2, SIN3
SCK Valid SIN hold time
tSHIXI
Serial clock “L” pulse width
Condition
Value
Unit
Min
Max
5 tCP
ns
50
50
ns
tCP + 80
ns
SCK2, SCK3
SIN2, SIN3
0
ns
tSHSL
SCK2, SCK3
3 tCP - tR
Serial clock “H” pulse width
tSLSH
SCK2, SCK3
tCP + 10
SCK SOT delay time
tSLOVE
SCK2, SCK3
SOT2, SOT3
2 tCP + 60
ns
Valid SIN SCK
tIVSHE
SCK2, SCK3
SIN2, SIN3
30
ns
SCK Valid SIN hold time
tSHIXE
SCK2, SCK3
SIN2, SIN3
tCP + 30
ns
SCK fall time
tF
SCK2, SCK3
10
ns
SCK rise time
tR
SCK2, SCK3
10
ns
Serial clock cycle time
Internal shift clock
mode output pins are
CL 80 pF 1 TTL.
External shift clock
mode output pins are
CL 80 pF 1 TTL.
ns
ns
Notes : AC characteristic in CLK synchronized mode.
CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.
Internal Shift Clock Mode
tSCYC
SCK2, SCK3
2.4 V
0.8 V
0.8 V
tSLOVI
SOT2, SOT3
2.4 V
0.8 V
tIVSHI
SIN2, SIN3
Document Number: 002-04493 Rev. *A
tSHIXI
VIH
VIH
VIL
VIL
Page 67 of 84
MB90350E Series
External Shift Clock Mode
tSLSH
tSHSL
VIH
VIH
SCK2, SCK3
VIL
VIL
tF
tSLOVE
tR
2.4 V
SOT2, SOT3
0.8 V
tIVSHE
SIN2, SIN3
■
Bit setting: ESCR:SCES = 1, ECCR:SCDE = 0
Parameter
VIH
VIH
VIL
VIL
(TA 40C to 125C, VCC 5.0 V 10, fCP 24 MHz, VSS 0 V)
Symbol
Pin
Serial clock cycle time
tSCYC
SCK2, SCK3
SCK SOT delay time
tSHOVI
SCK2, SCK3
SOT2, SOT3
Valid SIN SCK
tIVSLI
SCK2, SCK3
SIN2, SIN3
SCK Valid SIN hold time
tSLIXI
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK SOT delay time
tSHIXE
Condition
Value
Unit
Min
Max
5 tCP
ns
50
50
ns
tCP + 80
ns
SCK2, SCK3
SIN2, SIN3
0
ns
tSHSL
SCK2, SCK3
3 tCP - tR
ns
tSLSH
SCK2, SCK3
tCP + 10
ns
tSHOVE
SCK2, SCK3
SOT2, SOT3
2 tCP + 60
ns
30
ns
Internal shift clock
mode output pins are
CL 80 pF 1 TTL.
External shift clock
mode output pins are
CL 80 pF 1 TTL.
Valid SIN SCK
tIVSLE
SCK2, SCK3
SIN2, SIN3
SCK Valid SIN hold time
tSLIXE
SCK2, SCK3
SIN2, SIN3
tCP + 30
ns
SCK fall time
tF
SCK2, SCK3
10
ns
SCK rise time
tR
SCK2, SCK3
10
ns
Notes : CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.
Document Number: 002-04493 Rev. *A
Page 68 of 84
MB90350E Series
Internal Shift Clock Mode
tSCYC
2.4 V
SCK2, SCK3
0.8 V
tSHOVI
2.4 V
SOT2, SOT3
0.8 V
tIVSLI
SIN2, SIN3
tSLIXI
VIH
VIH
VIL
VIL
External Shift Clock Mode
tSHSL
VIH
VIH
SCK2, SCK3
tSLSH
VIL
tR
tSHOVE
VIL
tF
2.4 V
SOT2, SOT3
0.8 V
tIVSLE
SIN2, SIN3
■
Bit setting: ESCR:SCES = 0, ECCR:SCDE = 1
Parameter
tSLIXE
VIH
VIH
VIL
VIL
(TA 40C to 125C, VCC 5.0 V 10, fCP 24 MHz, VSS 0 V)
Symbol
Pin
Serial clock cycle time
tSCYC
SCK SOT delay time
Condition
Value
Unit
Min
Max
SCK2, SCK3
5 tCP
ns
tSHOVI
SCK2, SCK3
SOT2, SOT3
50
50
ns
Valid SIN SCK
tIVSLI
SCK2, SCK3
SIN2, SIN3
tCP 80
ns
SCK Valid SIN hold time
tSLIXI
SCK2, SCK3
SIN2, SIN3
0
ns
SOT SCK delay time
tSOVLI
SCK2, SCK3
SOT2, SOT3
3 tCP 70
ns
Internal clock operation output
pins are
CL 80 pF 1 TTL.
Notes : CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.
Document Number: 002-04493 Rev. *A
Page 69 of 84
MB90350E Series
tSCYC
2.4 V
SCK2, SCK3
0.8 V
0.8 V
tSHOVI
tSOVLI
SOT2, SOT3
2.4 V
2.4 V
0.8 V
0.8 V
tSLIXI
tIVSLI
VIH
VIL
SIN2, SIN3
■
VIH
VIL
Bit setting: ESCR:SCES = 1, ECCR:SCDE = 1
Parameter
(TA 40C to 125C, VCC 5.0 V 10, fCP 24 MHz, VSS 0 V)
Symbol
Pin
Serial clock cycle time
tSCYC
SCK SOT delay time
Value
Condition
Unit
Min
Max
SCK2, SCK3
5 tCP
ns
tSLOVI
SCK2, SCK3
SOT2, SOT3
50
50
ns
Valid SIN SCK
tIVSHI
SCK2, SCK3
SIN2, SIN3
tCP 80
ns
SCK Valid SIN hold time
tSHIXI
SCK2, SCK3
SIN2, SIN3
0
ns
SOT SCK delay time
tSOVHI
SCK2, SCK3
SOT2, SOT3
3 tCP 70
ns
Internal clock operation output pins are
CL 80 pF 1 TTL.
Notes : CL is load capacity value of pins when testing.
tCP is internal operating clock cycle time (machine clock) . Refer to “Clock Timing”.
tSCYC
2.4 V
2.4 V
SCK2, SCK3
0.8 V
tSLOVI
tSOVHI
SOT2, SOT3
2.4 V
2.4 V
0.8 V
0.8 V
tIVSHI
SIN2, SIN3
Document Number: 002-04493 Rev. *A
tSHIXI
VIH
VIH
VIL
VIL
Page 70 of 84
MB90350E Series
13.4.10 Trigger Input Timing
Parameter
Input pulse width
(TA 40C to 125C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Symbol
Pin
Condition
tTRGH
tTRGL
INT8 to INT15,
INT9R to INT11R, ADTG
Input pulse width
(TA 40C to 125C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Pin
Condition
tTIWH
TIN1, TIN3,IN0, IN1,
IN4 to IN7
tTIWL
Value
Min
Max
4 tCP
Unit
ns
VIH
VIH
VIL
VIL
tTIWH
tTIWL
(TA 40C to 125C, VCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Symbol
Pin
Condition
tTO
TOT1, TOT3, PPG4, PPG6,
PPG8 to PPGF
Document Number: 002-04493 Rev. *A
ns
tTRGL
Symbol
13.4.12 Timer Related Resource Output Timing
CLK TOUT change time
5 tCP
Unit
VIL
tTRGH
TIN1, TIN3,
IN0, IN1,
IN4 to IN7
Parameter
Max
VIL
13.4.11 Timer Related Resource Input Timing
Parameter
Min
VIH
VIH
INT8 to INT15,
INT9R to INT11R,
ADTG
Value
Value
Min
Max
30
Unit
ns
Page 71 of 84
MB90350E Series
2.4 V
CLK
2.4 V
TOT1, TOT3,
PPG4, PPG6
PPG8 to PPGF
0.8 V
tTO
13.4.13 I2C Timing
(TA 40C to 125C, VCC AVCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Parameter
Symbol
Condition
Standard-mode
Fast-mode*4
Unit
Min
Max
Min
Max
fSCL
0
100
0
400
kHz
tHDSTA
4.0
0.6
s
“L” width of the SCL clock
tLOW
4.7
tHIGH
4.0
0.6
s
“H” width of the SCL clock
4.7
0.6
s
0
3.45*2
0
0.9*3
s
SCL clock frequency
Hold time for (repeated) START condition
SDA SCL
1.3
s
Set-up time for a repeated START condition
SCL SDA
tSUSTA
Data hold time
SCL SDA
tHDDAT
Data set-up time
SDA SCL
tSUDAT
250*5
100*5
ns
Set-up time for STOP condition
SCL SDA
tSUSTO
4.0
0.6
s
tBUS
4.7
1.3
s
Bus free time between STOP condition and START
condition
R 1.7 k,
C 50 pF*1
*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT has to meet at least that the device does not exceed the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C -bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT250 ns must be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
*5 : Refer to “ Note of SDA, SCL set-up time”.
Document Number: 002-04493 Rev. *A
Page 72 of 84
MB90350E Series
• Note of SDA, SCL set-up time
SDA
Input data set-up time
SCL
6 tCP
Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on the load capacitance
or pull-up resistor.
Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be satisfied.
• Timing definition
SDA
tBUS
tLOW
tHDSTA
tSUDAT
SCL
tHDSTA
Document Number: 002-04493 Rev. *A
tHIGH
tHDDAT
fSCL
tSUSTA
tSUSTO
Page 73 of 84
MB90350E Series
13.5 A/D Converter
Parameter
(TA 40C to 125C, 3.0 V AVRH, VCC AVCC 5.0 V 10, fCP 24 MHz, VSS AVSS 0 V)
Symbol
Pin
Value
Unit
Min
Typ
Max
3.0
2.5
1.9
LSB
Zero reading
voltage
VOT
AN0 to AN14
AVSS
1.5LSB
AVSS
0.5LSB
AVSS
2.5LSB
V
Full scale reading
voltage
VFST
AN0 to AN14
AVRH
3.5LSB
AVRH
1.5LSB
AVRH
0.5LSB
V
Compare time
1.0
16500
s
Sampling time
s
Analog port input
current
IAIN
AN0 to AN14
0.3
0.3
A
Analog input
voltage range
VAIN
AN0 to AN14
AVSS
AVRH
V
Reference
voltage range
AVRH
AVSS 2.7
AVCC
V
Power supply
current
IA
AVCC
3.5
7.5
mA
IAH
AVCC
5
A
IR
AVRH
600
900
A
IRH
AVRH
5
A
AN0 to AN14
4
LSB
Resolution
Total error
Nonlinearity error
Differential
nonlinearity error
Reference
voltage supply current
Offset between
channels
2.0
0.5
1.2
10
Remarks
bit
LSB
LSB
4.5 V AVCC 5.5 V
4.0 V AVCC < 4.5 V
4.5 V AVCC 5.5 V
4.0 V AVCC < 4.5 V
*
*
* : If A/D converter is not operating, a current when CPU is stopped is applicable (VCC AVCC AVRH 5.0 V) .
Notes on A/D Converter Section
■
About the external impedance of the analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage
charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationship between the external
impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external
impedance so that the sampling time is longer than the minimum value. Also if the sampling time cannot be sufficient, connect a
capacitor of about 0.1 F to the analog input pin.
Document Number: 002-04493 Rev. *A
Page 74 of 84
MB90350E Series
· Analog input equivalence circuit
R
Analog input
Comparator
C
ON at sampling
MB90F351E(S),MB90F351TE(S),MB90F352E(S),MB90F352TE(S),
MB90F356E(S),MB90F356TE(S),MB90F357E(S),MB90F357TE(S)
R
4.5 V ≤ AVCC ≤ 5.5 V 2.0 kΩ (Max)
4.0 V ≤ AVCC ≤ 4.5 V 8.2 kΩ (Max)
C
16.0 pF (Max)
16.0 pF (Max)
MB90351E(S),MB90351TE(S),MB90352E(S),MB90352TE(S),
MB90356E(S),MB90356TE(S),MB90357E(S),MB90357TE(S),
MB90V340E-101/102/103/104
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC ≤ 4.5 V
Note : The value is reference value.
■
R
2.0 kΩ (Max)
8.2 kΩ (Max)
C
14.4 pF (Max)
14.4 pF (Max)
Flash memory device
· Relation between External impedance and minimum sampling time
(MB90F351E(S),MB90F351TE(S),MB90F352E(S),MB90F352TE(S),
MB90F356E(S),MB90F356TE(S),MB90F357E(S),MB90F357TE(S))
[External impedance = 0 kΩ to 100 kΩ]
100
[External impedance = 0 kΩ to 20 kΩ]
4.5 V ≤ AVCC ≤ 5.5 V
18
External impedance [kΩ]
External impedance [kΩ]
90
80
70
60
4.0 V ≤ AVCC ≤ 4.5 V
50
40
30
20
10
0
4.5 V ≤ AVCC ≤ 5.5 V
20
0
5
10
15
20
25
30
Minimum sampling time [μs]
Document Number: 002-04493 Rev. *A
35
16
14
12
4.0 V ≤ AVCC ≤ 4.5 V
10
8
6
4
2
0
0
1
2
3
4
5
6
7
8
Minimum sampling time [μs]
Page 75 of 84
MB90350E Series
■
MASK ROM device
· Relation between External impedance and minimum sampling time
( MB90351E(S),MB90351TE(S),MB90352E(S),MB90352TE(S),MB90356E(S),
MB90356TE(S),MB90357E(S),MB90357TE(S),MB90V340E-101/102/103/104)
[External impedance = 0 kΩ to 100 kΩ]
4.5 V ≤ AVCC ≤ 5.5 V
20
90
External impedance [kΩ]
External impedance [kΩ]
100
[External impedance = 0 kΩ to 20kΩ]
80
70
60
4.0 V ≤ AVCC ≤ 4.5 V
50
40
30
20
10
00
5
10
15
20
25
30
35
18
16
14
12
4.0 V ≤ AVCC ≤ 4.5 V
10
8
6
4
2
00
Minimum sampling time [μs]
■
4.5 V ≤ AVCC ≤ 5.5 V
1
2
3
4
5
6
7
8
Minimum sampling time [μs]
About the error
Values of relative errors grow larger, as |AVRH AVSS| becomes smaller.
Document Number: 002-04493 Rev. *A
Page 76 of 84
MB90350E Series
13.6 Definition of A/D Converter Terms
Resolution
Non linearity
error
: Analog variation that is recognized by an A/D converter.
:
Deviation between a line across zero-transition line ( “00 0000 0000” “00 0000 0001” ) and
full-scale transition line ( “11 1111 1110” “11 1111 1111” ) and actual conversion characteristics.
Differential
linearity error
Total error
:
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
: Difference between an actual value and a theoretical value. A total error includes zero
transition error, full-scale transition error, and linear error.
Total error
3FFH
3FEH
Actual conversion
characteristics
1.5 LSB
Digital output
3FDH
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
(Actual measurement value)
003H
Actual conversion
characteristics
Ideal characteristics
002H
001H
0.5 LSB
AVSS
AVRH
Analog input
Total error of digital output “N”
1 LSB (Ideal value)
VNT {1 LSB (N 1)
1 LSB
AVRH AVSS
[V]
1024
0.5 LSB}
[LSB]
N : A/D converter digital output value
VOT (Ideal value) AVSS 0.5 LSB [V]
VFST (Ideal value) AVRH 1.5 LSB [V]
VNT : A voltage at which digital output transits from (N 1) H to NH.
(Continued)
Document Number: 002-04493 Rev. *A
Page 77 of 84
MB90350E Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FFH
Digital output
3FDH
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
(N + 1)H
VFST (actual
measurement
value)
Digital output
3FEH
VNT (actual
measurement value)
004H
Actual conversion
characteristics
003H
Actual conversion
characteristics
NH
V (N + 1) T
(actual measurement
value)
VNT
(actual measurement value)
(N − 1)H
002H
Ideal characteristics
Actual conversion
characteristics
(N − 2)H
001H
VOT (actual measurement value)
AVSS
AVRH
AVSS
AVRH
Analog input
Analog input
VNT {1 LSB (N 1)
1 LSB
Non linearity error of digital output N
Differential linearity error of digital output N
V (N+1) T VNT
1 LSB
VFST VOT
1022
1 LSB
VOT}
[LSB]
1 LSB [LSB]
[V]
N : A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H”.
VFST : Voltage at which digital output transits from “3FEH” to “3FFH”.
13.7 Flash Memory Program/Erase Characteristics
■
Dual Operation Flash Memory
Parameter
Conditions
Value
Unit
Remarks
Min
Typ
Max
Sector erase time
(4 Kbytes sector)
0.2
0.5
s
Excludes programming prior to
erasure
Sector erase time
(16 Kbytes sector)
0.5
7.5
s
Excludes programming prior to
erasure
4.6
s
Excludes programming prior to
erasure
64
3600
s
Except for the overhead time of
the system level
10000
cycle
Chip erase time
TA 25C
VCC 5.0 V
Word (16-bit width)
programming time
Program/Erase cycle
Document Number: 002-04493 Rev. *A
Page 78 of 84
MB90350E Series
Parameter
Flash memory Data
Retention Time
Conditions
Average
TA 85C
Value
Min
Typ
Max
20
Unit
year
Remarks
*
* : Corresponding value comes from the technology reliability evaluation result.
(Using Arrhenius equation to translate high temperature measurements test result into normalized value at 85C)
14. Ordering Information
Part number
Package
Remarks
64-pin plastic LQFP
FPT-64P-M23
12.0 mm , 0.65 mm pitch
Flash memory products
(64 Kbytes)
64-pin plastic LQFP
FPT-64P-M23
12.0 mm , 0.65 mm pitch
Dual operation
Flash memory products
(128 Kbytes)
64-pin plastic LQFP
FPT-64P-M23
12.0 mm , 0.65 mm pitch
MASK ROM products
(64 Kbytes)
64-pin plastic LQFP
FPT-64P-M23
12.0 mm , 0.65 mm pitch
MASK ROM products
(128 Kbytes)
MB90F351EPMC
MB90F351ESPMC
MB90F351TEPMC
MB90F351TESPMC
MB90F356EPMC
MB90F356ESPMC
MB90F356TEPMC
MB90F356TESPMC
MB90F352EPMC
MB90F352ESPMC
MB90F352TEPMC
MB90F352TESPMC
MB90F357EPMC
MB90F357ESPMC
MB90F357TEPMC
MB90F357TESPMC
MB90351EPMC
MB90351ESPMC
MB90351TEPMC
MB90351TESPMC
MB90356EPMC
MB90356ESPMC
MB90356TEPMC
MB90356TESPMC
MB90352EPMC
MB90352ESPMC
MB90352TEPMC
MB90352TESPMC
MB90357EPMC
MB90357ESPMC
MB90357TEPMC
MB90357TESPMC
(Continued)
Document Number: 002-04493 Rev. *A
Page 79 of 84
MB90350E Series
(Continued)
Part number
Package
Remarks
64-pin plastic LQFP
FPT-64P-M24
10.0 mm , 0.50 mm pitch
Flash memory products
(64 Kbytes)
64-pin plastic LQFP
FPT-64P-M24
10.0 mm , 0.50 mm pitch
Dual operation
Flash memory products
(128 Kbytes)
64-pin plastic LQFP
FPT-64P-M24
10.0 mm , 0.50 mm pitch
MASK ROM products
(64 Kbytes)
64-pin plastic LQFP
FPT-64P-M24
10.0 mm , 0.50 mm pitch
MASK ROM products
(128 Kbytes)
299-pin ceramic PGA
PGA-299C-A01
Device for evaluation
MB90F351EPMC1
MB90F351ESPMC1
MB90F351TEPMC1
MB90F351TESPMC1
MB90F356EPMC1
MB90F356ESPMC1
MB90F356TEPMC1
MB90F356TESPMC1
MB90F352EPMC1
MB90F352ESPMC1
MB90F352TEPMC1
MB90F352TESPMC1
MB90F357EPMC1
MB90F357ESPMC1
MB90F357TEPMC1
MB90F357TESPMC1
MB90351EPMC1
MB90351ESPMC1
MB90351TEPMC1
MB90351TESPMC1
MB90356EPMC1
MB90356ESPMC1
MB90356TEPMC1
MB90356TESPMC1
MB90352EPMC1
MB90352ESPMC1
MB90352TEPMC1
MB90352TESPMC1
MB90357EPMC1
MB90357ESPMC1
MB90357TEPMC1
MB90357TESPMC1
MB90V340E-101CR
MB90V340E-102CR
MB90V340E-103CR
MB90V340E-104CR
Document Number: 002-04493 Rev. *A
Page 80 of 84
MB90350E Series
14.1 Package Dimensions
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12.0 × 12.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LFQFP64-12×12-0.65
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
*12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.0057±.0022)
33
32
49
0.10(.004)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0.25(.010)
INDEX
0~8˚
17
64
1
"A"
16
0.65(.026)
0.32±0.05
(.013±.002)
0.13(.005)
©2003-2008
FUJITSU
LIMITED F64034S-c-1-2
C
2003 FUJITSU
LIMITEDMICROELECTRONICS
F64034S-c-1-1
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values
(Continued)
Document Number: 002-04493 Rev. *A
Page 81 of 84
MB90350E Series
(Continued)
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.0 × 10.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.32 g
Code
(Reference)
P-LFQFP64-10×10-0.50
(FPT-64P-M24)
64-pin plastic LQFP
(FPT-64P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
* 10.00±0.10(.394±.004)SQ
48
0.145±0.055
(.006±.002)
33
49
32
Details of "A" part
0.08(.003)
+0.20
1.50 –0.10
+.008
.059 –.004
INDEX
64
0˚~8˚
17
(Mounting height)
0.10±0.10
(.004±.004)
(Stand off)
"A"
LEAD No.
1
16
0.50(.020)
0.20±0.05
(.008±.002)
0.08(.003)
M
©2005-2008
FUJITSU MICROELECTRONICS LIMITED F64036S-c-1-2
C
2005 FUJITSU LIMITED F64036S-c-1-1
Document Number: 002-04493 Rev. *A
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Page 82 of 84
MB90350E Series
15. Major Changes
Page
Section
Change Results
The following names are changed.
UART LIN-UART
16-bit I/O timer 16-bit free-run timer
26
Handling Devices
Added the section ”13. Serial Communication”.
51
Electrical Characteristics
Absolute Maximum Ratings
Changed the maximum value of power consumption.
63
Electrical Characteristics
AC Characteristics
Changed the "(4) Clock Output Timing".
Changed the Minimum value of cycle time.
(41.76 41.67)
69 to 73
Changed the notation of “(9) LIN-UART”.
78
A/D Converter
Changed the notation of “Zero reading voltage” and “full scale reading voltage”.
85
Ordering Information
Changed the part number;
MB90V340E-101 MB90V340E-101CR
MB90V340E-102 MB90V340E-102CR
MB90V340E-103 MB90V340E-103CR
MB90V340E-104 MB90V340E-104CR
NOTE: Please see “Document History” about later revised information.
Document History
Document Title: MB90350E Series F2MC-16LX 16-bit Microcontrollers
Document Number: 002-04493
Revision
ECN
**
*A
5193077
Orig. of
Change
Submission
Date
AKIH
10/12/2006
Migrated to Cypress and assigned document number 002-04993.
No change to document contents or format.
AKIH
04/07/2016
Updated to Cypress template
Document Number: 002-04493 Rev. *A
Description of Change
Page 83 of 84
MB90350E Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
cypress.com/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/support
cypress.com/touch
USB Controllers
Wireless/RF
cypress.com/psoc
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2006-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then
Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code
form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to
end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the
Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation,
or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be
reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from
any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages,
and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-04493 Rev. *A
Revised April 7, 2016
Page 84 of 84
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