MB90594GPF-G-127-BNDE1

The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix “CY”. How to Check the Ordering Part Number 1. Go to www.cypress.com/pcn. 2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrupt markets by creating new product categories in record time. To learn more, go to www.cypress.com. F2MC-16LX MB90590G Series CMOS 16-bit Proprietary Microcontroller The MB90590G series with two FULL-CAN interfaces and FLASH ROM is especially designed for automotive and industrial applications. Its main features are two on board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach. The instruction set of F2MC-16LX CPU core inherits an AT architecture of the F2MC* family with additional instruction sets for highlevel languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data. The MB90590/590G series has peripheral resources of 8/10-bit A/D converters, UART (SCI), extended I/O serial interface, 8/16-bit PPG timer, I/O timer (input capture (ICU), output compare (OCU)), stepping motor controller, and sound generator. Features ■ ■ ■ Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from divided-by2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz). Minimum instruction execution time : 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock, VCC of 5.0 V) Instruction set to optimize controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator Instruction set designed for high level language (C language) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions ■ Program patch function (for two address pointers) ■ Enhanced execution speed : 4-byte instruction queue ■ Enhanced interrupt function : 8 levels, 34 factors ■ Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS) : Up to 10 channels ■ Embedded ROM size and types Mask ROM : 256 Kbytes/384 Kbytes Flash ROM : 256 Kbytes/384 Kbytes Embedded RAM size : 6 Kbytes/8 Kbytes ■ ■ Flash ROM Supports automatic programming, Embedded Algorithm Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Erase can be performed on each block Block protection with external programming voltage Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) Cypress Semiconductor Corporation Document Number: 002-07698 Rev. *B • CPU intermittent operation mode Watch mode Hardware stand-by mode ■ Process 0.5m CMOS technology ■ I/O port General-purpose I/O ports : 78 ports ■ Timer Watchdog timer : 1 channel 8/16-bit PPG timer : 8/16-bit  6 channels 16-bit re-load timer : 2 channels ■ 16-bit I/O timer 16-bit free-run timer : 1 channel Input capture : 6 channels Output compare : 6 channels ■ Extended I/O serial interface : 1 channel ■ UART (3 channels) With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used. ■ Stepping motor controller (4 channels) ■ External interrupt circuit (8 channels) A module for starting an extended intelligent I/O service (EI2OS) and generating an external interrupt which is triggered by an external input. ■ Delayed interrupt generation module Generates an interrupt request for switching tasks. ■ 8/10-bit A/D converter (8 channels) 8/10-bit resolution can be selectively used. Starting by an external trigger input. ■ FULL-CAN interfaces : 2 Conforming to Version 2.0 Part A and Part B Flexible message buffering (mailbox and FIFO buffering can be mixed) ■ Sound generator ■ 18-bit Time-base counter ■ Watch timer : 1 channel ■ External bus interface : Maximum address space 16 Mbytes 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 6, 2018 MB90590G Series Contents Product Lineup ................................................................. 3 Pin Assignment ................................................................ 5 Pin Description ................................................................. 6 I/O Circuit Type ............................................................... 10 Handling Devices ............................................................ 12 Block Diagram ............................................................... 16 Memory Space ................................................................ 17 I/O Map ............................................................................. 18 CAN Controllers .............................................................. 27 Interrupt Map .................................................................. 33 Electrical Characteristics ............................................... 35 Absolute Maximum Ratings ....................................... 35 Recommended Conditions ........................................ 36 DC Characteristics .................................................... 38 Document Number: 002-07698 Rev. *B AC Characteristics ..................................................... 40 A/D Converter ............................................................ 47 A/D Converter Glossary ............................................ 48 Notes on Using A/D Converter .................................. 49 Flash Memory ............................................................ 50 Example Characteristics ................................................ 51 Ordering Information ...................................................... 52 Package Dimension ........................................................ 53 Major Changes ................................................................ 54 Sales, Solutions, and Legal Information ...................... 55 Page 2 of 55 MB90590G Series 1. Product Lineup Features MB90591G/594G MB90F591G/F594G MB90V590G Mask ROM product Flash ROM product Evaluation product ROM size 384/256 Kbytes 384/256 Kbytes Boot block Hard-wired reset vector None RAM size 8/6 Kbytes 8/6 Kbytes 8 Kbytes Classification  Emulator-specific power supply *1 None CPU functions The number of instructions : 340 Instruction bit length : 8 bits, 16 bits Instruction length : 1 byte to 7 bytes Data bit length : 1 bit, 8 bits, 16 bits Minimum execution time : 62.5 ns (at machine clock frequency of 16 MHz) Interrupt processing time : 1.5 s (at machine clock frequency of 16 MHz, minimum value) UART (3 channels) Clock synchronized transmission (500 Kbps / 1 Mbps / 2 Mbps) Clock asynchronized transmission (4808/5208/9615/10417/19230/38460/62500 /500000 bps at machine clock frequency of 16 MHz) Transmission can be performed by bi-directional serial transmission or by master/slave connection. 8/10-bit A/D converter Conversion precision : 8/10-bit can be selectively used. Number of inputs : 8 One-shot conversion mode (converts selected channel once only) Scan conversion mode (converts two or more successive channels and can program up to 8 channels) Continuous conversion mode (converts selected channel continuously) Stop conversion mode (converts selected channel and stop operation repeatedly) 8/16-bit PPG timers (6 channels) Number of channels : 6 (8/16-bit  6 channels) PPG operation of 8-bit or 16-bit A pulse wave of given intervals and given duty ratios can be output. Pulse interval : fsys, fsys/21, fsys/22, fsys/23, fsys/24, 128s (at oscillation of 4 MHz, fsys  system clock frequency of 16 MHz, fosc = oscillation clock frequency) 16-bit Reload timer Number of channels : 2 Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function 16-bit I/O timer 16-bit Output compares Number of channels : 6 (8/16-bit  6 channels) Pin input factor : A match signal of compare register Input captures Number of channels : 6 Rewriting a register value upon a pin input (rising, falling, or both edges) (Continued) Document Number: 002-07698 Rev. *B Page 3 of 55 MB90590G Series (Continued) Features MB90591G/594G MB90F591G/F594G MB90V590G CAN Interface Number of channels : 2 Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID’s Supports multiple messages Flexible configuration of acceptance filtering : Full bit compare / Full bit mask / Two partial bit masks Supports up to 1Mbps CAN bit timing setting : MB90(F)59xG : TSEG2RSJW Stepping motor controller (4 channels) Four high current outputs for each channel Synchronized two 8-bit PWM’s for each channel External interrupt circuit Number of inputs : 8 Started by a rising edge, a falling edge, an “H” level input, or an “L” level input. Sound generator 8-bit PWM signal is mixed with tone frequency from 8-bit reload counter PWM frequency : 62.5K, 31.2K, 15.6K, 7.8KHz (at System clock = 16MHz) Tone frequency : PWM frequency / 2 / (reload value + 1) Extended I/O serial interface Clock synchronized transmission (31.25K/62.5K/125K/500K/1Mbps at machine clock frequency of 16 MHz) LSB first/MSB first Watch timer Directly operates with the system clock Read/Write accessible Second/Minute/Hour registers Watchdog timer Reset generation interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) Flash Memory Supports automatic programming, Embedded Algorithm and Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Boot block configuration Erase can be performed on each block Block protection with external programming voltage Flash Writer from Minato Electronics Inc. Low-power consumption (standSleep/stop/CPU intermittent operation/watch timer/hardware stand-by by) mode Process Power supply voltage for operation*2 Package CMOS 5 V10 % (MB90V590G, MB90F594G, MB90594G) 5 V5 % (MB90F591G, MB90591G) QFP-100 PGA-256 *1 : It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used. Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details. *2 : Varies with conditions such as the operating frequency. (See section “Electrical Characteristics.”) Document Number: 002-07698 Rev. *B Page 4 of 55 MB90590G Series 2. Pin Assignment X1 X0 Vss 81 Vcc 84 82 P00/IN0 85 83 P01/IN1 86 87 88 P05/IN5 P04/IN4 P03/IN3 P02/IN2 P06/OUT0 91 89 P07/OUT1 92 90 P11/OUT3 P10/OUT2 93 P12/OUT4 94 95 P14/RX1 P15/TX1 P16/SGO P13/OUT5 96 97 98 99 100 P17/SGA (Top view) 65 P81/PWM1M2 P37/SIN1 17 64 P80/PWM1P2 P40/SCK1 18 63 DVSS P41/SOT1 P42/SOT2 19 62 P77/PWM2M1 20 61 P76/PWM2P1 P43/SCK2 21 60 P75/PWM1M1 P44/SIN2 22 59 P74/PWM1P1 Vcc 23 58 DVCC P45/SCIN3 24 57 P73/PWM2M0 P46/SCK3 25 56 P72/PWM2P0 P47/SOT3 26 55 P71/PWM1M0 C 27 54 P70/PWM1P0 P50/PPG0 28 53 DVSS P51/PPG1 29 52 HST P52/PPG2 30 51 MD2 50 P82/PWM2P2 16 MD1 66 49 15 MD0 P83/PWM2M2 P35/SCK0 P36/SIN0 48 67 P56/TIN 14 P57/TOT/WOT DVCC P34/SOT0 47 68 P67/AN7 13 46 P84/PWM1P3 P33 45 69 P66/AN6 12 44 P85/PWM1M3 P32 43 11 70 P65/AN5 P86/PWM2P3 Vss P64/AN4 71 42 10 Vss P87/PWM2M3 P31 41 DVSS 72 P63/AN3 73 9 40 8 P30 39 P27/INT7 P62/AN2 P91/RX0 P90/TX0 P61/AN1 74 38 75 7 P60/AN0 6 P26/INT6 37 RST P92/INT0 36 76 AVss 5 AVRL P24/INT4 P25/INT5 35 77 AVRH 4 34 P93/INT1 P23 AVcc 78 33 3 P55/PPG5/ADTG P94/INT2 P22 32 P95/INT3 79 31 80 2 P54/PPG4 1 P21 P53/PPG3 P20 (PQH100) Document Number: 002-07698 Rev. *B Page 5 of 55 MB90590G Series 3. Pin Description No. Pin name 82 X0 83 X1 77 52 85 to 90 Circuit type A Oscillator pin RST B Reset input HST C Hardware standby input P00 to P05 IN0 to IN5 D P06, P07, P10 to P13 91 to 96 D P14 RX1 D P15 98 TX1 SGO D 1 to 4 5 to 8 SGA P20 to P23 P24 to P27 INT4 to INT7 Outputs for the Output Compares. To enable the signal outputs, the corresponding bits of the Port Direction registers should be set to “1”. General purpose I/O RX input for CAN Interface 1 TX output for CAN Interface 1. To enable the signal output, the corresponding bit of the Port Direction register should be set to “1”. General purpose I/O D P17 100 Inputs for the Input Captures General purpose I/O P16 99 General purpose I/O General purpose I/O OUT0 to OUT5 97 Function SGO output for the Sound Generator. To enable the signal output, the corresponding bit of the Port Direction register should be set to “1”. General purpose I/O D SGA output for the Sound Generator. To enable the signal output, the corresponding bit of the Port Direction register should be set to “1”. D General purpose I/O D General purpose I/O External interrupt input for INT4 to INT7 9, 10 P30, P31 D General purpose I/O 12, 13 P32, P33 D General purpose I/O P34 14 SOT0 General purpose I/O D P35 15 SCK0 SOT output for UART 0. To enable the signal output, the corresponding bit of the Port Direction register should be set to “1”. General purpose I/O D SCK input/output for UART 0. To enable the signal output, the corresponding bit of the Port Direction register should be set to “1”. (Continued) Document Number: 002-07698 Rev. *B Page 6 of 55 MB90590G Series No. 16 17 18 19 20 21 22 24 25 26 Pin name Circuit type P36 SIN0 P37 SIN1 P40 SCK1 P41 SOT1 P42 SOT2 P43 SCK2 P44 SIN2 P45 SIN3 P46 SCK3 P47 SOT3 D D D D D D D D D D P50 to P55 28 to 33 38 to 41 43 to 46 47 PPG0 to PPG5, ADTG P60 to P63 AN0 to AN3 P64 to P67 AN4 to AN7 P56 TIN TOT/WOT General purpose I/O SIN input for UART 0 General purpose I/O SIN input for UART 1 General purpose I/O SCK input/output for UART 1 General purpose I/O SOT output for UART 1 General purpose I/O SOT output for UART 2 General purpose I/O SCK input/output for UART 2 General purpose I/O SIN input for UART 2 General purpose I/O SIN input for the Serial I/O General purpose I/O SCK input/output for the Serial I/O General purpose I/O SOT output for the Serial I/O General purpose I/O D E E D P57 48 Function Outputs for the Programmable Pulse Generators. Pin number 33 is also shared with ADTG input for the external trigger of the A/D Converter. General purpose I/O Inputs for the A/D Converter General purpose I/O Inputs for the A/D Converter General purpose I/O TIN input for the 16-bit Reload Timers General purpose I/O D TOT output for the 16-bit Reload Timers and WOT output for the Watch Timer. Only one of three output enable flags in these peripheral blocks can be set at a time. Otherwise the output signal has no meaning. (Continued) Document Number: 002-07698 Rev. *B Page 7 of 55 MB90590G Series No. Pin name Circuit type P70 to P73 54 to 57 PWM1P0, PWM1M0, PWM2P0, PWM2M0 General purpose I/O F P74 to P77 59 to 62 PWM1P1, PWM1M1, PWM2P1, PWM2M1 PWM1P2, PWM1M2, PWM2P2, PWM2M2 F 74 75 76 78 79 80 PWM1P3, PWM1M3, PWM2P3, PWM2M3 P90 TX0 P91 RX0 P92 INT0 P93 INT1 P94 INT2 P95 INT3 Output for Stepping Motor Controller channel 1. General purpose I/O F P84 to P87 69 to 72 Output for Stepping Motor Controller channel 0. General purpose I/O P80 to P83 64 to 67 Function Output for Stepping Motor Controller channel 2. General purpose I/O F D D D D D D Output for Stepping Motor Controller channel 3. General purpose I/O TX output for CAN Interface 0 General purpose I/O RX input for CAN Interface 0 General purpose I/O External interrupt input for INT0 General purpose I/O External interrupt input for INT1 General purpose I/O External interrupt input for INT2 General purpose I/O External interrupt input for INT3 58, 68 DVCC  Dedicated power supply pins for the high current output buffers (Pin No. 54 to 72) 53, 63, 73 DVSS  Dedicated ground pins for the high current output buffers (Pin No. 54 to 72) 34 AVCC Power supply Power supply for analog circuit pin When turning this power supply on or off, always be sure to first apply electric potential equal to or greater than AVCC to VCC. 37 AVSS Power supply Ground level for analog circuit (Continued) Document Number: 002-07698 Rev. *B Page 8 of 55 MB90590G Series (Continued) No. Pin name Circuit type Function 35 AVRH Power supply Reference voltage input pin for analog circuit When turning this power supply on or off, always be sure to first apply electric potential equal to or greater than AVRH to AVCC. 36 AVRL Power supply Reference voltage input pin for analog circuit 49, 50 MD0, MD1 C Operating mode selection input pins Connect directly to VCC or VSS. 51 MD2 G Operating mode selection input pin Connect directly to VCC or VSS. 27 C  This is the power supply stabilization capacitor pin. It should be connected externally to an 0.1 F ceramic capacitor. 23, 84 VCC Power supply Power supply (5.0 V) input pin for digital circuit 11,42,81 VSS Power supply Power supply (GND) input pin for digital circuit Document Number: 002-07698 Rev. *B Page 9 of 55 MB90590G Series 4. I/O Circuit Type Circuit Type Circuit Remarks ■ Oscillation feedback resistor : 1 M approx. X1 Clock Input A X0 HARD,SOFT STANDBY CONTROL ■ Hysteresis input with pull-up resistor : 50 k approx. B R (pull-up) R HYS ■ Hysteresis input C R HYS ■ CMOS output VCC ■ Hysteresis input P-ch N-ch D R HYS (Continued) Document Number: 002-07698 Rev. *B Page 10 of 55 MB90590G Series (Continued) Circuit Type Circuit Remarks ■ CMOS output Vcc ■ Hysteresis input ■ Analog input P-ch N-ch E P-ch Analog input N-ch HYS R ■ CMOS high current output ■ Hysteresis input P-ch High current N-ch F HYS R ■ Hysteresis input with pull-down resistor : 50 k approx. R G Document Number: 002-07698 Rev. *B HYS ■ Flash version does not have pull-down resistor. R (pull-down) Page 11 of 55 MB90590G Series 5. Handling Devices (1) Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions : ■ A voltage higher than Vcc or lower than Vss is applied to an input or output pin. ■ A voltage higher than the rated voltage is applied between Vcc and Vss. The AVcc power supply is applied before the Vcc voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. (2) Treatment of unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefor they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 k. Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. (3) Using external clock To use external clock, drive X0 pin only and leave X1 pin unconnected. Below is a diagram of how to use external clock. Using external clock ■ MB90590G Series X0 X1 Document Number: 002-07698 Rev. *B Page 12 of 55 MB90590G Series (4)Power supply pins (Vcc/Vss) In products with multiple VCC or VSS pins, pins with the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to an external power and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pin near the device. Vcc Vss Vcc Vss Vss Vcc MB90590G Series Vcc Vss Vss Vcc (5) Pull-up/down resistors The MB90590G Series does not support internal pull-up/down resistors. Use external components where needed. (6) Crystal Oscillator Circuit Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via the shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure that lines of oscillation circuits do not cross the lines of other circuits. A printed circuit board artwork surrounding the X0 and X1 pins with a ground area for stabilizing the operation is highly recommended. (7) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRHor AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). (8) Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS. Document Number: 002-07698 Rev. *B Page 13 of 55 MB90590G Series (9) N.C. Pin The N.C. (internally connected) pin must be opened for use. (10) Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 s or more (0.2 V to 2.7 V). (11) Indeterminate outputs from ports 0 and 1 (without MB90F591G/591G, MB90F594G) During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the outputs from ports 0 and 1 become following state. ■ If RST pin is “H”, the outputs become indeterminate. ■ If RST pin is “L”, the outputs become high-impedance. Pay attention to the port output timing shown as follow. Oscillation setting time* RST pin is “H” Power-on reset* Vcc (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal Period of indeterminated *1 : Power-on reset time : "Period of clock frequency"  217 (Clock frequency of 16 MHz : 8.19 ms) *2 : Oscillation setting time : "Period of clock frequency"  218 (Clock frequency of 16 MHz : 16.38ms) Oscillation setting time RST pin is “L” Power-on reset Vcc (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal High-impedance *1 : Power-on reset time : "Period of clock frequency"  217 (Clock frequency of 16 MHz : 8.19 ms) *2 : Oscillation setting time : "Period of clock frequency"  218 (Clock frequency of 16 MHz : 16.38ms) Document Number: 002-07698 Rev. *B Page 14 of 55 MB90590G Series (12) Initialization The device contains internal registers which are initialized only by a power-on reset. To initialize these registers, please turn on the power again. (13) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”), the value of the corresponding bank register (DTB, ADB, USB, SSB) is set in “00 H”. If the values of the corresponding bank registers (DTB,ADB,USB,SSB) are set to other than “00 H”, the remainder by the execution result of the instruction is not stored in the register of the instruction operand. (14) Using REALOS The use of EI2OS is not possible with the REALOS real time operating system. (15) Caution on Operations during PLL Clock Mode If the PLL clock mode is selected in the microcontroller, it may attempt to continue the operation using the free-running frequency of the automatic oscillating circuit in the PLL circuitry even if the oscillator is out of place or the clock input is stopped. Performance of this operation, however, cannot be guaranteed. Document Number: 002-07698 Rev. *B Page 15 of 55 MB90590G Series 6. Block Diagram X0,X1 RST HST Clock Controller F2MC-16LX CPU 16-bit Free-run Timer RAM 6/8 K ROM/Flash 256 K/384 K 16-bit Input Capture 6ch IN0 to IN5 16-bit Output Compare 6ch OUT0 to OUT5 8/16-bit PPG 6ch PPG0 to PPG5 Prescaler  3 SOT0 to SOT2 SCK0 to SCK2 SIN0 to SIN2 UART 3ch CAN 2ch Prescaler AVCC AVSS AN0 to AN7 AVRH AVRL ADTG TIN TOT/WOT Serial I/O PWM1M0 to PWM1M3 10-bit ADC 8ch 16-bit Reload Timer 2ch F2MC-16 Bus SOT3 SCK3 SIN3 RX0, RX1 TX0, TX1 SMC 4ch DVSS External Interrupt Circuit 8ch Generator Document Number: 002-07698 Rev. *B PWM2P0 to PWM2P3 DVCC Sound Watch Timer PWM1P0 to PWM1P3 PWM2M0 to PWM2M3 INT0 to INT7 SGO SGA Page 16 of 55 MB90590G Series 7. Memory Space The memory space of the MB90590/590G Series is shown below Memory space map MB90V590G FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H 00FFFFH 004000H 0028FFH 002100H 0020FFH 001FFFH 001900H 0018FFH ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FA bank) ROM (F9 bank) 00FFFFH 004000H ROM (Image of FF bank) Peripheral 000100H 001FFFH 001900H 0018FFH Peripheral 00FFFFH 004000H 001FFFH 001900H 0018FFH RAM 6K 000100H Peripheral FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H 0028FFH 002100H 0020FFH RAM 2K RAM 6K 0000BFH 000000H ROM (FF bank) ROM (FB bank) ROM (Image of FF bank) MB90591G/ F591G MB90594G/F594G 0000BFH 000000H ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (Image of FF bank) RAM 2K Peripheral RAM 6K 000100H Peripheral 0000BFH 000000H Peripheral Note: : The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same address, enabling reference of the table on the ROM without stating “far”. For example, if an attempt has been made to access 00C000H , the contents of the ROM at FFC000H are accessed. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 004000H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH. Document Number: 002-07698 Rev. *B Page 17 of 55 MB90590G Series 8. I/O Map Address Register Abbreviation Access Peripheral Initial value 00H Port 0 Data Register PDR0 R/W Port 0 XXXXXXXXB 01H Port 1 Data Register PDR1 R/W Port 1 XXXXXXXXB 02H Port 2 Data Register PDR2 R/W Port 2 XXXXXXXXB 03H Port 3 Data Register PDR3 R/W Port 3 XXXXXXXXB 04H Port 4 Data Register PDR4 R/W Port 4 XXXXXXXXB 05H Port 5 Data Register PDR5 R/W Port 5 XXXXXXXXB 06H Port 6 Data Register PDR6 R/W Port 6 XXXXXXXXB 07H Port 7 Data Register PDR7 R/W Port 7 XXXXXXXXB 08H Port 8 Data Register PDR8 R/W Port 8 XXXXXXXXB 09H Port 9 Data Register PDR9 R/W Port 9 _ _ XXXXXXB 0AH to 0FH Reserved 10H Port 0 Direction Register DDR0 R/W Port 0 0 0 0 0 0 0 0 0B 11H Port 1 Direction Register DDR1 R/W Port 1 0 0 0 0 0 0 0 0B 12H Port 2 Direction Register DDR2 R/W Port 2 0 0 0 0 0 0 0 0B 13H Port 3 Direction Register DDR3 R/W Port 3 0 0 0 0 0 0 0 0B 14H Port 4 Direction Register DDR4 R/W Port 4 0 0 0 0 0 0 0 0B 15H Port 5 Direction Register DDR5 R/W Port 5 0 0 0 0 0 0 0 0B 16H Port 6 Direction Register DDR6 R/W Port 6 0 0 0 0 0 0 0 0B 17H Port 7 Direction Register DDR7 R/W Port 7 0 0 0 0 0 0 0 0B 18H Port 8 Direction Register DDR8 R/W Port 8 0 0 0 0 0 0 0 0B 19H Port 9 Direction Register DDR9 R/W Port 9 _ _ 0 0 0 0 0 0B R/W Port 6, A/D 1 1 1 1 1 1 1 1B 1AH 1BH Reserved Analog Input Enable Register ADER 1CH to 1FH Reserved 20H Serial Mode Control Register 0 UMC0 R/W 0 0 0 0 0 1 0 0B 21H Serial Status Register 0 USR0 R/W 0 0 0 1 0 0 0 0B 22H Serial Input/Output Data Register 0 UIDR0/UODR0 R/W 23H Rate and Data Register 0 URD0 R/W 0 0 0 0 0 0 0XB 24H Serial Mode Control Register 1 UMC1 R/W 0 0 0 0 0 1 0 0B 25H Serial Status Register 1 USR1 R/W 26H Serial Input/Output Data Register 1 UIDR1/UODR1 R/W 27H Rate and Data Register 1 URD1 R/W UART0 UART1 XXXXXXXXB 0 0 0 1 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0XB (Continued) Document Number: 002-07698 Rev. *B Page 18 of 55 MB90590G Series Address Register Abbreviation Access 28H Serial Mode Control Register 2 UMC2 R/W 29H Serial Status Register 2 USR2 R/W Peripheral Initial value 0 0 0 0 0 1 0 0B 0 0 0 1 0 0 0 0B UART2 2AH Serial Input/Output Data Register 2 UIDR2/UODR2 R/W 2BH Rate and Data Register 2 URD2 R/W 0 0 0 0 0 0 0XB 2CH Serial Mode Control Register (low-order) SMCS R/W _ _ _ _0 0 0 0B 2DH Serial Mode Control Register (high-order) SMCS R/W 2EH Serial Data Register SDR R/W XXXXXXXXB 2FH Edge Selector Register SES R/W _ _ _ _ _ _ _0B 30H External Interrupt Enable Register ENIR R/W 0 0 0 0 0 0 0 0B 31H External Interrupt Request Register EIRR R/W 32H External Interrupt Level Register ELVR R/W 33H External Interrupt Level Register ELVR R/W 0 0 0 0 0 0 0 0B 34H A/D Control Status Register 0 ADCS0 R/W 0 0 0 0 0 0 0 0B 35H A/D Control Status Register 1 ADCS1 R/W 36H A/D Data Register 0 ADCR0 R 37H A/D Data Register 1 ADCR1 R/W 38H PPG0 Operation Mode Control Register PPGC0 R/W 39H PPG1 Operation Mode Control Register PPGC1 R/W 3AH PPG0,1 Output Pin Control Register PPG01 R/W 3BH Serial I/O External Interrupt A/D Converter XXXXXXXXB 0 0 0 0 0 0 1 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 1 0 XXB 0 _ 0 0 0 _ _ 1B 16-bit Programmable Pulse Generator 0/1 0 _ 0 0 0 0 0 1B 16-bit Programmable Pulse Generator 2/3 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B Reserved 3CH PPG2 Operation Mode Control Register PPGC2 R/W 3DH PPG3 Operation Mode Control Register PPGC3 R/W 3EH PPG2,3 Output Pin Control Register PPG23 R/W 3FH 0 _ 0 0 0 _ _1B 0 0 0 0 0 0 0 0B Reserved 40H PPG4 Operation Mode Control Register PPGC4 R/W 41H PPG5 Operation Mode Control Register PPGC5 R/W 42H PPG4,5 Output Pin Control Register PPG45 R/W 43H 0 _ 0 0 0 _ _ 1B 16-bit Programmable Pulse Generator 4/5 0 _ 0 0 0 0 0 1B 16-bit Programmable Pulse Generator 6/7 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B Reserved 44H PPG6 Operation Mode Control Register PPGC6 R/W 45H PPG7 Operation Mode Control Register PPGC7 R/W 46H PPG6,7 Output Pin Control Register PPG67 R/W 47H 0 _ 0 0 0 _ _ 1B 0 0 0 0 0 0 0 0B Reserved (Continued) Document Number: 002-07698 Rev. *B Page 19 of 55 MB90590G Series Address Register Abbreviation Access 48H PPG8 Operation Mode Control Register PPGC8 R/W 49H PPG9 Operation Mode Control Register PPGC9 R/W 4AH PPG8,9 Output Pin Control Register PPG89 R/W 4BH 16-bit Programmable Pulse Generator 8/9 Initial value 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B Reserved 4CH PPGA Operation Mode Control Register PPGCA R/W 4DH PPGB Operation Mode Control Register PPGCB R/W 4EH PPGA,B Output Pin Control Register PPGAB R/W 4FH 50H Peripheral 16-bit Programmable Pulse Generator A/B 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B Reserved Timer Control Status Register 0 (low-order) TMCSR0 R/W 0 0 0 0 0 0 0 0B 16-bit Reload Timer 0 51H Timer Control Status Register 0 (high-order) TMCSR0 R/W 52H Timer Control Status Register 1 (low-order) TMCSR1 R/W _ _ _ _ 0 0 0 0B 0 0 0 0 0 0 0 0B 16-bit Reload Timer 1 53H Timer Control Status Register 1 (high-order) TMCSR1 R/W 54H Input Capture Control Status Register 0/1 ICS01 R/W Input Capture 0/1 0 0 0 0 0 0 0 0B 55H Input Capture Control Status Register 2/3 ICS23 R/W Input Capture 2/3 0 0 0 0 0 0 0 0B 56H Input Capture Control Status Register 4/5 ICS45 R/W Input Capture 4/5 0 0 0 0 0 0 0 0B 58H Output Compare Control Status Register 0 OCS0 R/W 59H Output Compare Control Status Register 1 OCS1 R/W 5AH Output Compare Control Status Register 2 OCS2 R/W 57H _ _ _ _ 0 0 0 0B Reserved 5BH Output Compare Control Status Register 3 OCS3 R/W 5CH Output Compare Control Status Register 4 OCS4 R/W 5DH Output Compare Control Status Register 5 OCS5 R/W 5EH Sound Control Register (low-order) SGCR R/W 5FH Sound Control Register (high-order) SGCR R/W Output Compare 0/1 Output Compare 2/3 Output Compare 4/5 Sound Generator 0 0 0 0 _ _ 0 0B _ _ _0 0 0 0 0B 0 0 0 0 _ _ 0 0B _ _ _ 0 0 0 0 0B 0 0 0 0 _ _ 0 0B _ _ _ 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 _ _ _ _ _ _ 0B (Continued) Document Number: 002-07698 Rev. *B Page 20 of 55 MB90590G Series Address Register Abbreviation Access 60H Watch Timer Control Register (low-order) WTCR R/W 61H Watch Timer Control Register (high-order) WTCR R/W 62H PWM Control Register 0 PWC0 R/W 0 0 0 _ _ 0 0 0B 0 0 0 0 0 0 0 0B Stepping Motor Controller 0 0 0 0 0 0 _ _ 0B Stepping Motor Controller 1 0 0 0 0 0 _ _ 0B Stepping Motor Controller 2 0 0 0 0 0 _ _ 0B Stepping Motor Controller 3 0 0 0 0 0 _ _ 0B Reserved PWM Control Register 1 PWC1 65H 66H Initial value Watch Timer 63H 64H Peripheral R/W Reserved PWM Control Register 2 PWC2 67H R/W Reserved PWM Control Register 3 PWC3 6DH Serial I/O Prescaler Register CDCR R/W Prescaler (Serial I/O) 0 XXX 1 1 1 1B 6EH Timer Control Status Register TCCS R/W 16-bit Free-run Timer 0 0 0 0 0 0 0 0B 6FH ROM Mirror Function Select Register ROMM W ROM Mirror XXXXXXX1B 68H 69H to 6CH R/W Reserved 70H to 8FH Reserved for CAN Interface 0/1. Refer to section about CAN Controller 90H to 9DH Reserved 9EH Program Address Detection Control Status Register PACSR R/W Address Match Detection Function 0 0 0 0 0 0 0 0B 9FH Delayed Interrupt/Release Register DIRR R/W Delayed Interrupt _ _ _ _ _ _ _ 0B A0H Low Power Mode Control Register LPMCR R/W Low Power Controller 0 0 0 1 1 0 0 0B A1H Clock Selection Register CKSCR R/W Low Power Controller 1 1 1 1 1 1 0 0B A8H Watchdog Timer Control Register WDTC R/W Watchdog Timer XXXXX 1 1 1B A9H Time Base Timer Control Register TBTC R/W Time Base Timer 1 - - 0 0 1 0 0B Flash Memory 0 0 0 X 0 0 0 0B A2H to A7H Reserved AAH to ADH AEH Reserved Flash Memory Control Status Register (Flash product only. Otherwise reserved) AFH FMCS R/W Reserved (Continued) Document Number: 002-07698 Rev. *B Page 21 of 55 MB90590G Series Address Register Abbreviation Access Peripheral B0H Interrupt Control Register 00 ICR00 R/W 0 0 0 0 0 1 1 1B B1H Interrupt Control Register 01 ICR01 R/W 0 0 0 0 0 1 1 1B B2H Interrupt Control Register 02 ICR02 R/W 0 0 0 0 0 1 1 1B B3H Interrupt Control Register 03 ICR03 R/W 0 0 0 0 0 1 1 1B B4H Interrupt Control Register 04 ICR04 R/W 0 0 0 0 0 1 1 1B B5H Interrupt Control Register 05 ICR05 R/W 0 0 0 0 0 1 1 1B B6H Interrupt Control Register 06 ICR06 R/W 0 0 0 0 0 1 1 1B B7H Interrupt Control Register 07 ICR07 R/W B8H Interrupt Control Register 08 ICR08 R/W B9H Interrupt Control Register 09 ICR09 R/W 0 0 0 0 0 1 1 1B BAH Interrupt Control Register 10 ICR10 R/W 0 0 0 0 0 1 1 1B Interrupt controller Initial value 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B BBH Interrupt Control Register 11 ICR11 R/W 0 0 0 0 0 1 1 1B BCH Interrupt Control Register 12 ICR12 R/W 0 0 0 0 0 1 1 1B BDH Interrupt Control Register 13 ICR13 R/W 0 0 0 0 0 1 1 1B BEH Interrupt Control Register 14 ICR14 R/W 0 0 0 0 0 1 1 1B BFH Interrupt Control Register 15 ICR15 R/W 0 0 0 0 0 1 1 1B C0H to FFH Reserved 1900H Reload L Register PRLL0 R/W 1901H Reload H Register PRLH0 R/W XXXXXXXXB 16-bit Programmable Pulse Generator 0/1 XXXXXXXXB 1902H Reload L Register PRLL1 R/W 1903H Reload H Register PRLH1 R/W XXXXXXXXB 1904H Reload L Register PRLL2 R/W XXXXXXXXB 1905H Reload H Register PRLH2 R/W 16-bit Programmable Pulse Generator 2/3 XXXXXXXXB XXXXXXXXB 1906H Reload L Register PRLL3 R/W 1907H Reload H Register PRLH3 R/W XXXXXXXXB 1908H Reload L Register PRLL4 R/W XXXXXXXXB 1909H Reload H Register PRLH4 R/W 16-bit Programmable Pulse Generator 4/5 XXXXXXXXB XXXXXXXXB 190AH Reload L Register PRLL5 R/W 190BH Reload H Register PRLH5 R/W XXXXXXXXB 190CH Reload L Register PRLL6 R/W XXXXXXXXB 190DH Reload H Register PRLH6 R/W 190EH Reload L Register PRLL7 R/W 190FH Reload H Register PRLH7 R/W 16-bit Programmable Pulse Generator 6/7 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) Document Number: 002-07698 Rev. *B Page 22 of 55 MB90590G Series Address Register Abbreviation Access Peripheral Initial value 1910H Reload L Register PRLL8 R/W 1911H Reload H Register PRLH8 R/W 1912H Reload L Register PRLL9 R/W 1913H Reload H Register PRLH9 R/W XXXXXXXXB XXXXXXXXB 1914H Reload L Register PRLLA R/W 1915H Reload H Register PRLHA R/W 1916H Reload L Register PRLLB R/W 1917H Reload H Register PRLHB R/W 1918H to 191FH XXXXXXXXB 16-bit Programmable Pulse Generator 8/9 16-bit Programmable Pulse Generator A/B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Reserved 1920H Input Capture Register 0 (low-order) IPCP0 R 1921H Input Capture Register 0 (high-order) IPCP0 R 1922H Input Capture Register 1 (low-order) IPCP1 R XXXXXXXXB 1923H Input Capture Register 1 (high-order) IPCP1 R XXXXXXXXB 1924H Input Capture Register 2 (low-order) IPCP2 R XXXXXXXXB 1925H Input Capture Register 2 (high-order) IPCP2 R 1926H Input Capture Register 3 (low-order) IPCP3 R XXXXXXXXB 1927H Input Capture Register 3 (high-order) IPCP3 R XXXXXXXXB 1928H Input Capture Register 4 (low-order) IPCP4 R XXXXXXXXB 1929H Input Capture Register 4 (high-order) IPCP4 R 192AH Input Capture Register 5 (low-order) IPCP5 R XXXXXXXXB 192BH Input Capture Register 5 (high-order) IPCP5 R XXXXXXXXB 192CH to 192FH XXXXXXXXB XXXXXXXXB Input Capture 0/1 XXXXXXXXB Input Capture 2/3 XXXXXXXXB Input Capture 4/5 Reserved (Continued) Document Number: 002-07698 Rev. *B Page 23 of 55 MB90590G Series Address Register Abbreviation Access 1930H Output Compare Register 0 (low-order) OCCP0 R/W 1931H Output Compare Register 0 (high-order) OCCP0 R/W 1932H Output Compare Register 1 (low-order) OCCP1 R/W 1933H Output Compare Register 1 (high-order) OCCP1 R/W XXXXXXXXB 1934H Output Compare Register 2 (low-order) OCCP2 R/W XXXXXXXXB 1935H Output Compare Register 2 (high-order) OCCP2 R/W 1936H Output Compare Register 3 (low-order) OCCP3 R/W 1937H Output Compare Register 3 (high-order) OCCP3 R/W XXXXXXXXB 1938H Output Compare Register 4 (low-order) OCCP4 R/W XXXXXXXXB 1939H Output Compare Register 4 (high-order) OCCP4 R/W 193AH Output Compare Register 5 (low-order) OCCP5 R/W 193BH Output Compare Register 5 (high-order) OCCP5 R/W 193CH to 193FH TMR0/TMRLR0 1941H Timer 0/Reload Register 0 (high-order) TMR0/TMRLR0 R/W 1942H Timer 1/Reload Register 1 (low-order) TMR1/TMRLR1 R/W Timer 1/Reload Register 1 (high-order) TMR1/TMRLR1 R/W 1944H Timer Data Register (low-order) TCDT R/W 1945H Timer Data Register (high-order) TCDT R/W 1946H Frequency Data Register SGFR R/W 1947H Amplitude Data Register SGAR R/W 1948H Decrement Grade Register SGDR R/W 1949H Tone Count Register SGTR R/W 1943H Initial value XXXXXXXXB Output Compare 0/1 Output Compare 2/3 Output Compare 4/5 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Reserved Timer 0/Reload Register 0 (low-order) 1940H Peripheral R/W XXXXXXXXB 16-bit Reload Timer 0 XXXXXXXXB XXXXXXXXB 16-bit Reload Timer 1 XXXXXXXXB 16-bit Free-run Timer 00000000B 00000000B XXXXXXXXB Sound Generator XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) Document Number: 002-07698 Rev. *B Page 24 of 55 MB90590G Series Address Register Abbreviation Access Peripheral Initial value 194AH Sub-second Data Register (low-order) WTBR R/W 194BH Sub-second Data Register (middle-order) WTBR R/W 194CH Sub-second Data Register (high-order) WTBR R/W _ _ _ XXXXXB 194DH Second Data Register WTSR R/W __000000B 194EH Minute Data Register WTMR R/W 194FH Hour Data Register WTHR R/W 1950H PWM1 Compare Register 0 PWC10 R/W 1951H PWM2 Compare Register 0 PWC20 R/W 1952H PWM1 Select Register 0 PWS10 R/W 1953H PWM2 Select Register 0 PWS20 R/W _0000000B 1954H PWM1 Compare Register 1 PWC11 R/W XXXXXXXXB 1955H PWM2 Compare Register 1 PWC21 R/W 1956H PWM1 Select Register 1 PWS11 R/W 1957H PWM2 Select Register 1 PWS21 R/W _0000000B 1958H PWM1 Compare Register 2 PWC12 R/W XXXXXXXXB XXXXXXXXB Watch Timer Watch Timer XXXXXXXXB __000000B ___00000B XXXXXXXXB Stepping Motor Controller 0 Stepping Motor Controller 1 XXXXXXXXB __000000B XXXXXXXXB __000000B 1959H PWM2 Compare Register 2 PWC22 R/W 195AH PWM1 Select Register 2 PWS12 R/W 195BH PWM2 Select Register 2 PWS22 R/W _0000000B 195CH PWM1 Compare Register 3 PWC13 R/W XXXXXXXXB 195DH PWM2 Compare Register 3 PWC23 R/W 195EH PWM1 Select Register 3 PWS13 R/W 195FH PWM2 Select Register 3 PWS23 R/W 1960H to 19FFH Reserved Stepping Motor Controller 2 Stepping Motor Controller 3 1A00H to 1AFFH CAN Interface 0. Refer to section about CAN Controller 1B00H to 1BFFH CAN Interface 1. Refer to section about CAN Controller 1C00H to 1CFFH CAN Interface 0. Refer to section about CAN Controller 1D00H to 1DFFH CAN Interface 1. Refer to section about CAN Controller 1E00H to 1EFFH Reserved XXXXXXXXB __000000B XXXXXXXXB __000000B _0 0 0 0 0 0 0 B (Continued) Document Number: 002-07698 Rev. *B Page 25 of 55 MB90590G Series (Continued) Address Register Abbreviation Access 1FF0H Program Address Detection Register 0 (low-order) PADR0 R/W XXXXXXXX B 1FF1H Program Address Detection Register 0 (middle-order) PADR0 R/W XXXXXXXX B 1FF2H Program Address Detection Register 0 (high-order) PADR0 R/W 1FF3H Program Address Detection Register 1 (low-order) PADR1 R/W 1FF4H Program Address Detection Register 1 (middle-order) PADR1 R/W XXXXXXXX B 1FF5H Program Address Detection Register 1 (high-order) PADR1 R/W XXXXXXXX B 1FF6H to 1FFFH Peripheral Address Match Detection Function Initial value XXXXXXXX B XXXXXXXX B Reserved Note: : Initial value of “” represents unused bit; “X” represents unknown value. Addresses in the rage 0000H to 00FFH, which are not listed in the table, are reserved for the primary functions of the MCU. A read access to these reserved addresses results in reading “X”, and any write access should not be performed. Document Number: 002-07698 Rev. *B Page 26 of 55 MB90590G Series 9. CAN Controllers The CAN controller has the following features : Conforms to CAN Specification Version 2.0 Part A and B ■ Supports transmission/reception in standard frame and extended frame formats ■ Supports transmission of data frames by receiving remote frames ■ 16 transmitting/receiving message buffers ❐ 29-bit ID and 8-byte data ❐ Multi-level message buffer configuration ■ Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as 1D acceptance mask ❐ Two acceptance mask registers in either standard frame format or extended frame formats ■ Bit rate programmable from 10 Kbit/s to 2 Mbit/s (when input clock is at 16 MHz) List of Control Registers Address CAN0 CAN1 000070H 000080H 000071H 000081H 000072H 000082H 000073H 000083H 000074H 000084H 000075H 000085H 000076H 000086H 000077H 000087H 000078H 000088H 000079H 000089H 00007AH 00008AH 00007BH 00008BH 00007CH 00008CH 00007DH 00008DH 00007EH 00008EH 00007FH 00008FH Register Abbreviation Access Initial Value Message buffer valid register BVALR R/W 00000000 00000000B Transmit request register TREQR R/W 00000000 00000000B Transmit cancel register TCANR W 00000000 00000000B Transmit complete register TCR R/W 00000000 00000000B Receive complete register RCR R/W 00000000 00000000B Remote request receiving register RRTRR R/W 00000000 00000000B Receive overrun register ROVRR R/W 00000000 00000000B RIER R/W 00000000 00000000B Receive interrupt enable register (Continued) Document Number: 002-07698 Rev. *B Page 27 of 55 MB90590G Series (Continued) List of Control Registers Address CAN0 CAN1 001C00H 001D00H 001C01H 001D01H 001C02H 001D02H 001C03H 001D03H 001C04H 001D04H 001C05H 001D05H 001C06H 001D06H 001C07H 001D07H 001C08H 001D08H 001C09H 001D09H 001C0AH 001D0AH 001C0BH 001D0BH 001C0CH 001D0CH 001C0DH 001D0DH 001C0EH 001D0EH 001C0FH 001D0FH 001C10H 001D10H 001C11H 001D11H 001C12H 001D12H 001C13H 001D13H 001C14H 001D14H 001C15H 001D15H 001C16H 001D16H 001C17H 001D17H 001C18H 001D18H 001C19H 001D19H 001C1AH 001D1AH 001C1BH 001D1BH Register Abbreviation Access Initial Value Control status register CSR R/W, R 00---000 0----0-1B Last event indicator register LEIR R/W -------- 000-0000B Receive/transmit error counter RTEC R 00000000 00000000B Bit timing register BTR R/W -1111111 11111111B IDE register IDER R/W XXXXXXXX XXXXXXXXB Transmit RTR register TRTRR R/W 00000000 00000000B Remote frame receive waiting register RFWTR R/W XXXXXXXX XXXXXXXXB TIER R/W 00000000 00000000B Transmit interrupt enable register XXXXXXXX XXXXXXXXB Acceptance mask select register AMSR R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB Acceptance mask register 0 AMR0 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB Acceptance mask register 1 Document Number: 002-07698 Rev. *B AMR1 R/W XXXXX--- XXXXXXXXB Page 28 of 55 MB90590G Series List of Message Buffers (ID Registers) Address Register CAN0 CAN1 001A20H 001B20H 001A21H 001B21H 001A22H 001B22H 001A23H 001B23H 001A24H 001B24H 001A25H 001B25H 001A26H 001B26H 001A27H 001B27H 001A28H 001B28H 001A29H 001B29H 001A2AH 001B2AH 001A2BH 001B2BH 001A2CH 001B2CH 001A2DH 001B2DH 001A2EH 001B2EH 001A2FH 001B2FH 001A30H 001B30H 001A31H 001B31H 001A32H 001B32H 001A33H 001B33H 001A34H 001B34H 001A35H 001B35H 001A36H 001B36H 001A37H 001B37H 001A38H 001B38H 001A39H 001B39H 001A3AH 001B3AH 001A3BH 001B3BH 001A3CH 001B3CH 001A3DH 001B3DH 001A3EH 001B3EH 001A3FH 001B3FH Abbreviation Access Initial Value XXXXXXXX XXXXXXXXB ID register 0 IDR0 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 1 IDR1 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 2 IDR2 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 3 IDR3 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 4 IDR4 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 5 IDR5 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 6 IDR6 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 7 IDR7 R/W XXXXX--- XXXXXXXXB (Continued) Document Number: 002-07698 Rev. *B Page 29 of 55 MB90590G Series (Continued) Address CAN0 CAN1 001A40H 001B40H 001A41H 001B41H 001A42H 001B42H 001A43FH 001B43H 001A44H 001B44H 001A45H 001B45H 001A46H 001B46H 001A47H 001B47H 001A48H 001B48H 001A49H 001B49H 001A4AH 001B4AH 001A4BH 001B4BH 001A4CH 001B4CH 001A4DH 001B4DH 001A4EH 001B4EH 001A4FH 001B4FH 001A50H 001B50H 001A51H 001B51H 001A52H 001B52H 001A53H 001B53H 001A54H 001B54H 001A55H 001B55H 001A56H 001B56H 001A57H 001B57H 001A58H 001B58H 001A59H 001B59H 001A5AH 001B5AH 001A5BH 001B5BH 001A5CH 001B5CH 001A5DH 001B5DH 001A5EH 001B5EH 001A5FH 001B5FH Register Abbreviation Access IDR8 R/W Initial Value XXXXXXXX XXXXXXXXB ID register 8 XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 9 IDR9 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 10 IDR10 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 11 IDR11 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 12 IDR12 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 13 IDR13 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 14 IDR14 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 15 Document Number: 002-07698 Rev. *B IDR15 R/W XXXXX--- XXXXXXXXB Page 30 of 55 MB90590G Series List of Message Buffers (DLC Registers and Data Registers) Address Register CAN0 CAN1 001A60H 001B60H 001A61H 001B61H 001A62H 001B62H 001A63H 001B63H 001A64H 001B64H 001A65H 001B65H 001A66H 001B66H 001A67H 001B67H 001A68H 001B68H 001A69H 001B69H 001A6AH 001B6AH 001A6BH 001B6BH 001A6CH 001B6CH 001A6DH 001B6DH 001A6EH 001B6EH 001A6FH 001B6FH 001A70H 001B70H 001A71H 001B71H 001A72H 001B72H 001A73H 001B73H 001A74H 001B74H 001A75H 001B75H 001A76H 001B76H 001A77H 001B77H 001A78H 001B78H 001A79H 001B79H 001A7AH 001B7AH 001A7BH 001B7BH 001A7CH 001B7CH 001A7DH 001B7DH 001A7EH 001B7EH 001A7FH 001B7FH 001A80H to 001A87H 001B80H to 001B87H Abbreviation Access Initial Value DLC register 0 DLCR0 R/W ----XXXXB DLC register 1 DLCR1 R/W ----XXXXB DLC register 2 DLCR2 R/W ----XXXXB DLC register 3 DLCR3 R/W ----XXXXB DLC register 4 DLCR4 R/W ----XXXXB DLC register 5 DLCR5 R/W ----XXXXB DLC register 6 DLCR6 R/W ----XXXXB DLC register 7 DLCR7 R/W ----XXXXB DLC register 8 DLCR8 R/W ----XXXX DLC register 9 DLCR9 R/W ----XXXXB DLC register 10 DLCR10 R/W ----XXXXB DLC register 11 DLCR11 R/W ----XXXXB DLC register 12 DLCR12 R/W ----XXXXB DLC register 13 DLCR13 R/W ----XXXXB DLC register 14 DLCR14 R/W ----XXXXB DLC register 15 DLCR15 R/W ----XXXXB DTR0 R/W XXXXXXXXB to XXXXXXXXB Data register 0 (8 bytes) (Continued) Document Number: 002-07698 Rev. *B Page 31 of 55 MB90590G Series (Continued) Address Abbreviation Access Initial Value Data register 1 (8 bytes) DTR1 R/W XXXXXXXXB to XXXXXXXXB 001B90H to 001B97H Data register 2 (8 bytes) DTR2 R/W XXXXXXXXB to XXXXXXXXB 001A98H to 001A9FH 001B98H to 001B9FH Data register 3 (8 bytes) DTR3 R/W XXXXXXXXB to XXXXXXXXB 001AA0H to 001AA7H 001BA0H to 001BA7H Data register 4 (8 bytes) DTR4 R/W XXXXXXXXB to XXXXXXXXB 001AA8H to 001AAFH 001BA8H to 001BAFH Data register 5 (8 bytes) DTR5 R/W XXXXXXXXB to XXXXXXXXB 001AB0H to 001AB7H 001BB0H to 001BB7H Data register 6 (8 bytes) DTR6 R/W XXXXXXXXB to XXXXXXXXB 001AB8H to 001ABFH 001BB8H to 001BBFH Data register 7 (8 bytes) DTR7 R/W XXXXXXXXB to XXXXXXXXB 001AC0H to 001AC7H 001BC0H to 001BC7H Data register 8 (8 bytes) DTR8 R/W XXXXXXXXB to XXXXXXXXB 001AC8H to 001ACFH 001BC8H to 001BCFH Data register 9 (8 bytes) DTR9 R/W XXXXXXXXB to XXXXXXXXB 001AD0H to 001AD7H 001BD0H to 001BD7H Data register 10 (8 bytes) DTR10 R/W XXXXXXXXB to XXXXXXXXB 001AD8H to 001ADFH 001BD8H to 001BDFH Data register 11 (8 bytes) DTR11 R/W XXXXXXXXB to XXXXXXXXB 001AE0H to 001AE7H 001BE0H to 001BE7H Data register 12 (8 bytes) DTR12 R/W XXXXXXXXB to XXXXXXXXB 001AE8H to 001AEFH 001BE8H to 001BEFH Data register 13 (8 bytes) DTR13 R/W XXXXXXXXB to XXXXXXXXB 001AF0H to 001AF7H 001BF0H to 001BF7H Data register 14 (8 bytes) DTR14 R/W XXXXXXXXB to XXXXXXXXB 001AF8H to 001AFFH 001BF8H to 001BFFH Data register 15 (8 bytes) DTR15 R/W XXXXXXXXB to XXXXXXXXB CAN0 CAN1 001A88H to 001A8FH 001B88H to 001B8FH 001A90H to 001A97H Register Document Number: 002-07698 Rev. *B Page 32 of 55 MB90590G Series 10. Interrupt Map Interrupt vector EI2OS clear Number Address Reset N/A # 08 FFFFDCH INT9 instruction N/A # 09 FFFFD8H Exception N/A # 10 FFFFD4H Time Base Timer N/A # 11 FFFFD0H *1 # 12 FFFFCCH CAN 0 RX N/A # 13 FFFFC8H CAN 0 TX/NS N/A # 14 FFFFC4H CAN 1 RX N/A # 15 FFFFC0H CAN 1 TX/NS N/A # 16 FFFFBCH 8/16 bit PPG 0/1 N/A # 17 FFFFB8H 8/16 bit PPG 2/3 N/A # 18 FFFFB4H 8/16 bit PPG 4/5 N/A # 19 FFFFB0H 8/16 bit PPG 6/7 N/A # 20 FFFFACH 8/16 bit PPG 8/9 N/A # 21 FFFFA8H 8/16 bit PPG A/B N/A # 22 FFFFA4H 16-bit Reload Timer 0 *1 # 23 FFFFA0H 16-bit Reload Timer 1 *1 # 24 FFFF9CH Input Capture 0/1 *1 # 25 FFFF98H Output compare 0/1 *1 # 26 FFFF94H Input Capture 2/3 *1 # 27 FFFF90H Output Compare 2/3 *1 # 28 FFFF8CH Interrupt cause External Interrupt (INT0 to INT7) Input Capture 4/5 *1 # 29 FFFF88H Output Compare 4/5 *1 # 30 FFFF84H 8/10 bit A/D Converter *1 # 31 FFFF80H N/A # 32 FFFF7CH 16-bit Free-run Timer/Watch Timer Serial I/O *1 # 33 FFFF78H N/A # 34 FFFF74H UART 0 RX *2 # 35 FFFF70H UART 0 TX *1 # 36 FFFF6CH Sound Generator UART 1 RX *2 # 37 FFFF68H UART 1 TX *1 # 38 FFFF64H UART 2 RX *2 # 39 FFFF60H UART 2 TX *1 # 40 FFFF5CH Flash Memory N/A # 41 FFFF58H Delayed interrupt N/A # 42 FFFF54H Interrupt control register Number Address       ICR00 0000B0H ICR01 0000B1H ICR02 0000B2H ICR03 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH *1 : The interrupt request flag is cleared by the EI2OS interrupt clear signal. *2 : The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available. N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal. Document Number: 002-07698 Rev. *B Page 33 of 55 MB90590G Series Notes: ■ For a peripheral module with two interrupt for a single interrupt number, both interrupt request flags are cleared by the EI2OS interrupt clear signal. ■ At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by a hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the first event. So it is recommended not to use the EI2OS for this interrupt number. ■ If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor which should be unique for each interrupt source. For this reason, when one interrupt source uses the EI2OS, the other interrupt should be disabled. Document Number: 002-07698 Rev. *B Page 34 of 55 MB90590G Series 11. Electrical Characteristics 11.1 Absolute Maximum Ratings (VSS = AVSS = 0.0 V) Parameter Symbol VCC Power supply voltage Rating Min Max VSS  0.3 AVCC VSS  0.3 AVRH, AVRL VSS  0.3  0.3  0.3 V  0.3 2.0 Unit Remarks VSS + 6.0 V VSS + 6.0 V VCC  AVCC *1 VSS + 6.0 V AVCC  AVRH/L, AVRH  AVRL *1 VCC  DVCC DVCC VSS VSS + 6.0 V Input voltage VI VSS VSS + 6.0 V Output voltage VO SS VSS + 6.0 V *2 + 2.0 mA *6 Max clamp current ICLAMP *2  | ICLAMP | — 20 mA “L” level Max output current IOL1 — 15 mA Normal output “L” level avg. output current IOLAV1 — 4 mA Normal output, average value *4 “L” level Max output current IOL2 — 40 mA High current output *3 “L” level avg. output current IOLAV2 — 30 mA High current output, average value *4 “L” level Max overall output current “L” level Max overall output current “L” level avg. overall output current “L” level avg. overall output current IOL1 — Total Max clamp current IOL2 IOLAV1 — IOLAV2 *6 *3 100 mA Total normal output 330 mA Total high current output 50 mA Total normal output, average value *5 250 mA Total high current output, average value *5 “H” level Max output current IOH1 — –15 mA Normal output *3 “H” level avg. output current IOHAV1 — –4 mA Normal output, average value *4 “H” level Max output current IOH2 — –40 mA High current output *3 “H” level avg. output current IOHAV2 — –30 mA High current output, average value *4 “H” level Max overall output current “H” level Max overall output current “H” level avg. overall output current “H” level avg. overall output current IOH1 — –100 mA Total normal output IOH2 — –330 mA Total high current output IOHAV1 — –50 mA Total normal output, average value *5 IOHAV2 — –250 mA *5 — 500 mW Total high current output, average value MB90F594G, MB90F591G — 400 mW MB90594G, MB90591G Power consumption PD Operating temperature TA –40 +85 C TSTG –55 +150 C Storage temperature *1 : AVCC, AVRH, AVRL and DVCC shall not exceed VCC. AVRH and AVRL shall not exceed AVCC. Also, AVRL shall not exceed AVRH. *2 : VI and VO should not exceed VCC + 0.3V. VI should not exceed the specified ratings. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *3 : The maximum output current is a peak value for a corresponding pin. *4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin. *5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins. *6 : ■ Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 toP95 ■ Use within recommended operating conditions. ■ Use at DC voltage (current) ■ The B signal should always be applied with a limiting resistance placed between the B signal and the microcontroller. ■ The value of the limiting resistance should be set so that when the B signal is applied the input current to the microcontroller pins does not exceed rated values, either instantaneously or for prolonged periods. ■ Note that when the microcontroller drive current is low, such as in the power saving modes, the B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. Document Number: 002-07698 Rev. *B Page 35 of 55 MB90590G Series ■ Note that if a B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. ■ Note that if the B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. ■ Care must be taken not to leave the B input pin open. ■ Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept B signal input. ■ Sample recommended circuits • Input/Output equivalent circuits Protective diode VCC B input Limiting resistance P-ch (0 V to 16 V) N-ch R Note: : Average output current = operating current  operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 11.2 Recommended Conditions (VSS = AVSS = 0.0 V) Parameter Power supply voltage Value Symbol VCC AVCC Min Typ Max 4.5 5.0 5.5 Unit Remarks V Under normal operation 3.0 — 5.5 V Maintains RAM data in stop mode 4.75 5.0 5.25 V Under normal operation 3.0 — 5.25 V Maintains RAM data in stop mode * Smooth capacitor CS 0.022 0.1 1.0 F Operating temperature TA –40 — +85 C MB90V590G MB90F594G MB90594G MB90F591G MB90591G * : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-07698 Rev. *B Page 36 of 55 MB90590G Series • C Pin Connection Diagram C CS Document Number: 002-07698 Rev. *B Page 37 of 55 MB90590G Series 11.3 DC Characteristics Parameter Input H voltage Input L voltage Output H voltage Output L voltage (MB90V590G, MB90F594G, MB90594G : VCC  5.0 V10 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) (MB90F591G, MB90591G : VCC  5.0 V5 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Symbol Pin name Condition Unit Remarks Min Typ Max VIHS CMOS hysteresis input — 0.8 VCC — VCC +0.3 V VIHM MD input — VCC – 0.3 — VCC +0.3 V VILS CMOS hysteresis input — VSS – 0.3 — 0.5VCC V VILM MD input — VSS – 0.3 — VSS + 0.3 V VILR RST, HST — VSS – 0.3 — 0.2VCC V VOH1 Normal output VCC = 4.5 V, IOH1 = –4.0 mA VCC – 0.5 — — V VOH2 High current output VCC = 4.5 V, IOH2 = –30.0 mA VCC – 0.5 — — V VOL1 Normal output VCC = 4.5 V, IOL1 = 4.0 mA — — 0.4 V VOL2 High current output VCC = 4.5 V, IOL2 = 30.0 mA — — 0.5 V VCC = 5.5 V, VSS < VI < VCC –5 — 5 A VCC = 5.5 V, AVSS  VI  –1 — 1 A — 37 60 mA MB90594G — 50 80 mA MB90F594G — 50 80 mA MB90F591G — 45 60 mA MB90591G — 13 20 mA MB90594G — 15 23 mA MB90F594G — 15 23 mA MB90F591G Input leak current IIL Analog input leak current IIAL — AN0 to AN7 VCC = 5.0 V10%, Internal frequency : 16 MHz, At normal operation. ICC VCC = 5.0 V10%, Internal frequency : 16 MHz, At Sleep mode. ICCS Power supply current * AVCC VCC ICTS ICCH VCC = 5.0 V10%, Internal frequency : 2 MHz, At Timer mode VCC = 5.0 V10%, At Stop mode, TA = 25C — 15 23 mA MB90591G — 0.3 0.6 mA MB90594G — 0.35 0.6 mA MB90F594G — 0.35 0.6 mA MB90F591G — 0.35 0.6 mA MB90591G — 5 20 A MB90594G — 5 20 A MB90F594G — 5 20 A MB90F591G — 5 20 A MB90591G * : The power supply current testing conditions are when using the external clock. (Continued) Document Number: 002-07698 Rev. *B Page 38 of 55 MB90590G Series Parameter Input capacity Symbol CIN (MB90F591G, MB90591G : VCC  5.0 V5 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Pin name Condition Unit Remarks Min Typ Max Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS, DVCC, DVSS, P70 to P87 — — 5 15 pF P70 to P87 — — 15 30 pF Pull-up resistance RUP RST — 25 50 100 k Pull-down resistance RDOWN MD2 — 25 50 100 k Document Number: 002-07698 Rev. *B Page 39 of 55 MB90590G Series 11.4 AC Characteristics 11.4.1 Clock Timing (MB90V590G, MB90F594G, MB90594G : VCC  5.0 V10 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) (MB90F591G, MB90591G : VCC  5.0 V5 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Pin Parameter Symbol Unit Remarks name Min Typ Max Oscillation frequency Input clock rise and fall time 3 — 16 MHz tCYL X0, X1 62.5 — 333 ns X0 10 — — ns Duty ratio is about 30 to 70%. tCR, tCF X0 — — 5 ns When using external clock fCP — 1.5 — 16 MHz tCP — 62.5 — 666 ns tCYCFL — — 2 tCP — ns Machine clock frequency Machine clock cycle time Flash read cycle time X0, X1 PWH, PWL Oscillation cycle time Input clock pulse width fC • Clock Timing When Flash is accessed by CPU tCYL 0.8 VCC X0 0.2 VCC PWH PWL tCF tCR Example of Oscillation circuit X0 X1 R C1 Document Number: 002-07698 Rev. *B C2 Page 40 of 55 MB90590G Series • Guaranteed operation range Guaranteed operation range (MB90F591G, MB90591G) Guaranteed operation range (MB90V590G, MB90F594G, MB90594G) 5.5 5.25 4.75 4.5 Guaranteed PLL operation range (MB90F591G, MB90591G) Power supply voltage VCC (V) Guaranteed PLL operation range (MB90V590G, MB90F594G, MB90594G) 3.0 1.5 8 Machine clock 16 fCP (MHz) • Oscillation clock frequency and machine clock frequency 4 16 3 2 1 12 Machine clock fCP (MHz) 9 8 1/2 (PLL off) 4 3 4 8 16 Oscillation frequency fC (MHz) Document Number: 002-07698 Rev. *B Page 41 of 55 MB90590G Series 11.4.2 Reset and Hardware Standby Input Timing (MB90V590G, MB90F594G, MB90594G : VCC  5.0 V10 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) (MB90F591G, MB90591G : VCC  5.0 V5 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Parameter Symbol Pin name Unit Remarks Min Max 16 tCP*1 — ns Under normal operation Reset input time tRSTL RST Oscillation time of oscillator*2  16 tCP*1 — ms In stop mode Hardware standby input time tHSTL HST 16 tCP*1 — ns Under normal operation *1 : “tcp” represents one cycle time of the machine clock. No reset can fully initialize the Flash Memory if it is performing the automatic algorithm. *2 : Oscillation time of oscillator is time that the amplitude reached the 90%. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In ceramic oscillator, the oscillation time is between hundreds of s to several ms. In the external clock, the oscillation time is 0 ms. Under Normal Operation tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC In Stop Mode tRSTL RST 0.2VCC 0.2VCC 90 of amplitude X0 Internal operation clock 16 tCP Oscillation time of oscillator Oscillation setting time Instruction execution Internal reset Document Number: 002-07698 Rev. *B Page 42 of 55 MB90590G Series 11.4.3 Power On Reset (MB90V590G, MB90F594G, MB90594G : VCC  5.0 V10 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) (MB90F591G, MB90591G : VCC  5.0 V5 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Parameter Symbol Pin name Condition Unit Remarks Min Max Power on rise time Power off time tR VCC tOFF VCC — 0.05 30 ms 50 — ms Due to repetitive operation Notes: ■ VCC must be kept lower than 0.2 V before power-on. ■ The above values are used for creating a power-on reset. ■ Some registers in the device are initialized only upon a power-on reset. To initialize these register, turn on the power supply using the above values. tR 2.7 V VCC 0.2 V 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer per second, however, you can use the PLL clock. VCC 3V RAM data being held It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower. VSS Document Number: 002-07698 Rev. *B Page 43 of 55 MB90590G Series 11.4.4 UART0/1/2, Serial I/O Timing (MB90V590G, MB90F594G, MB90594G : VCC  5.0 V10 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) (MB90F591G, MB90591G : VCC  5.0 V5 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Parameter Symbol Pin name Condition Unit Remarks Min Max Serial clock cycle time tSCYC SCK0 to SCK3 8 tCP* — ns SCK   SOT delay time tSLOV SCK0 to SCK3, SOT0 to SOT3 –80 80 ns Valid SIN  SCK  tIVSH SCK0 to SCK3, SIN0 to SIN3 100 — ns SCK   Valid SIN hold time tSHIX SCK0 to SCK3, SIN0 to SIN3 60 — ns Serial clock "H" pulse width tSHSL SCK0 to SCK3 4 tCP — ns Serial clock "L" pulse width tSLSH SCK0 to SCK3 4 tCP — ns SCK   SOT delay time tSLOV SCK0 to SCK3, SOT0 to SOT3 — 150 ns Valid SIN  SCK  tIVSH SCK0 to SCK3, SIN0 to SIN3 60 — ns SCK   Valid SIN hold time tSHIX SCK0 to SCK3, SIN0 to SIN3 60 — ns Internal clock operation output pins are CL = 80 pF + 1 TTL. External clock operation output pins are CL = 80 pF + 1 TTL. * : tCP is the machine cycle (Unit : ns) Notes: ■ AC characteristic in CLK synchronized mode. ■ CL is load capacity value of pins when testing. • Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH SIN Document Number: 002-07698 Rev. *B 0.8 VCC 0.5 VCC tSHIX 0.8 VCC 0.5 VCC Page 44 of 55 MB90590G Series • External Shift Clock Mode tSLSH tSHSL 0.8 VCC SCK 0.8 VCC 0.5 VCC 0.5 VCC tSLOV 2.4 V SOT 0.8 V tIVSH tSHIX 0.8 VCC 0.5 VCC 0.8 VCC SIN 0.5 VCC 11.4.5 Timer Input Timing (MB90V590G, MB90F594G, MB90594G : VCC  5.0 V10 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) (MB90F591G, MB90591G : VCC  5.0 V5 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Parameter Symbol Pin name Condition Unit Remarks Min Max Input pulse width tTIWH TIN0 tTIWL IN0 to IN5 — 4 tCP — ns Under normal operation 1 — s In stop mode • Timer Input Timing 0.8 VCC 0.8 VCC 0.5 VCC 0.5 VCC tTIWH tTIWL 11.4.6 Trigger Input Timing (MB90V590G, MB90F594G, MB90594G : VCC  5.0 V10 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) (MB90F591G, MB90591G : VCC  5.0 V5 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Parameter Symbol Pin name Condition Unit Remarks Min Max Input pulse width tTRGH tTRGL INT0 to INT7, ADTG Document Number: 002-07698 Rev. *B — 5 tCP — ns Page 45 of 55 MB90590G Series • Trigger Input Timing 0.8 VCC 0.8 VCC 0.5 VCC 0.5 VCC tTRGH tTRGL 11.4.7 Slew Rate High Current Outputs (MB90F591G, MB90591G, MB90594G and MB90F594G only) (MB90F594G, MB90594G : VCC  5.0 V10 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) (MB90F591G, MB90591G : VCC  5.0 V5 %, VSS  AVSS  0.0 V, TA  40 C to 85 C) Value Parameter Symbol Pin name Condition Unit Remarks Min Max Output Rise/Fall time tR2 tF2 Port P70 to P77, Port P80 to P87 — 15 40 ns • Slew Rate Output Timing VH VH VL VL tR2 Document Number: 002-07698 Rev. *B VH  VOL2  0.1  (VOH2  VOL2) VL  VOL2  0.9  (VOH2  VOL2) tF2 Page 46 of 55 MB90590G Series 11.5 A/D Converter (MB90V590G, MB90F594G, MB90594G : VCC  AVCC  5.0 V10 %, VSS  AVSS  0.0 V, 3.0 V  AVR+  AVR-, TA  40 C to 85 C) (MB90F591G, MB90591G : VCC  AVCC  5.0 V5 %, VSS  AVSS  0.0 V, 3.0 V  AVR+  AVR-, TA  40 C to 85 C) Parameter Symbol Pin name Resolution — Conversion error Value Unit Remarks Min Typ Max — — — 10 bit — — — — 5.0 LSB Nonlinearity error — — — — 2.5 LSB Differential linearity error — — — — 1.9 LSB Zero transition voltage VOT AN0 to AN7 AVRL – 3.5 LSB AVRL + 0.5 LSB AVRL + 4.5 LSB V Full scale transition voltage VFST AN0 to AN7 AVRH – 6.5 LSB AVRH – 1.5 LSB AVRH + 1.5 LSB V Compare time — — 352tCP — — ns Internal frequency : 16 MHz Sampling time — — 64tCP — — ns Internal frequency : 16 MHz Analog port input current IAIN AN0 to AN7 -1 — +1 A Analog input voltage range VAIN AN0 to AN7 AVRL — AVRH V — AVRH AVRL + 2.7 — AVCC V — AVRL 0 — AVRH – 2.7 V IA AVCC — 5 — mA IAH AVCC — — 5 A * — 400 600 A MB90V590G MB90F594G MB90F591G — 140 600 A MB90594G MB90591G * Reference voltage range Power supply current Reference voltage current Offset between input channels IR AVRH IRH AVRH — — 5 A — AN0 to AN7 — — 4 LSB * : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) when the CPU is stopped. Document Number: 002-07698 Rev. *B Page 47 of 55 MB90590G Series 11.6 A/D Converter Glossary Resolution : Analog changes that are identifiable with the A/D converter Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000”  “00 0000 0001”) with the full-scale transition point (“11 1111 1110” “11 1111 1111”) from actual conversion characteristics Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zerotransition error/full-scale transition error and linearity error. Total error 3FF 3FE 0.5 LSB Actual conversion value Digital output 3FD {1 LSB  (N – 1) + 0.5 LSB} 004 VNT (measured value) 003 Actual conversion characteristics 002 Theoretical characteristics 001 0.5 LSB AVRL 1 LSB = (Theoretical value) AVRH – AVRL 1024 VOT (Theoretical value) = AVRL + 0.5 LSB[V] Analog input [V] AVRH Total error for digital output N = VNT – {1 LSB  (N – 1) + 0.5 LSB} 1 LSB [LSB] VNT : Voltage at a transition of digital output from (N – 1) to N VFST (Theoretical value) = AVRH – 1.5 LSB[V] (Continued) Document Number: 002-07698 Rev. *B Page 48 of 55 MB90590G Series (Continued) Linearity error Differential linearity error Theoretical characteristics 3FF Actual conversion value {1 LSB  (N – 1)+ VOT} 3FE N+1 Actual conversion value VFST (measured value) VNT (measured value) 004 Actual conversion characteristics 003 Digital output Digital output 3FD N V(N + 1)T (measured value) N–1 VNT (measured value) 002 Theoretical characteristics 001 Actual conversion value N–2 VOT (measured value) AVRL Analog input AVRH AVRL Analog input AVRH Linearity error of VNT – {1 LSB  (N – 1) + VOT} [LSB] digital output N = 1 LSB Differential linearity error = of digital N 1 LSB = VFST – VOT 1022 V(N + 1)T – VNT 1 LSB – 1 LSB [LSB] [V] VOT : Voltage at transition of digital output from “000H” to “001H” VFST : Voltage at transition of digital output from “3FEH” to “3FFH” 11.7 Notes on Using A/D Converter Select the output impedance value for the external circuit of analog input according to the following conditions, : ■ Output impedance values of the external circuit of 15 k or lower are recommended. When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 s @machine clock of 16 MHz). ■ • Equipment of analog input circuit model Analog input Comparator 3.2 kMax 30 pF Max Note : Listed values must be considered as standards. Document Number: 002-07698 Rev. *B Page 49 of 55 MB90590G Series Error The smaller the | AVRH  AVRL |, the greater the error would become relatively. ■ 11.8 Flash Memory ■ Erase and Programming Performance Parameter Condition Sector erase time Chip erase time TA   25 C VCC  5.0 V Word (16-bit) programming time Erase/Program cycle — Document Number: 002-07698 Rev. *B Value Unit Remarks Min Typ Max — 1 15 s Excludes 00H programming prior erasure — 7 — s MB90F594G — 12 — s MB90F591G — 16 3,600 ns Excludes system-level overhead 10,000 — — cycle Excludes 00H programming prior erasure Page 50 of 55 MB90590G Series 12. Example Characteristics ■ “H” Level Output Voltage VOH1 – IOH1 4.5 4.5 4 4 3.5 3.5 3 2.5 3 2.5 2 2 1.5 1.5 1 1 0.5 0.5 0 0 0.0 -2.0 -4.0 -6.0 -8.0 -10.0 0 IOH1 [mA] “L” Level Output Voltage VOL1 [V] 0.8 VOL1 – IOL1 (Vcc = 4.5 V, TA = +25˚C) -30 -40 0.8 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 2.0 4.0 6.0 8.0 0.0 10.0 10.0 20.0 30.0 40.0 IOL2 [mA] IOL1 [mA] ■ -20 VOL2 – IOL2 (Vcc = 4.5 V, TA = +25˚C) 0.7 0 0.0 -10 IOH2 [mA] VOL2 [V] ■ (Vcc = 4.5 V, TA = +25˚C) 5 VOH2 [V] VOH1 [V] VOH2 – IOH2 (Vcc = 4.5 V, TA = +25˚C) 5 “H” Level Input Voltage/“L Level Input Voltage (Hysteresis Input) VIN – VCC (TA = +25˚C) 5 VIH 4 VIN [V] VIL 3 2 1 0 3 4 5 6 Vcc [V] Document Number: 002-07698 Rev. *B Page 51 of 55 MB90590G Series (Continued) ■ Power Supply Voltage ICC – VCC ICCS – VCC (TA = +25˚C) (TA = +25˚C) 60 25 fcp = 16 MHz fcp = 16 MHz 40 30 fcp = 8 MHz ICCS [mA] ICC [mA] 50 20 15 fcp = 8 MHz 10 20 fcp = 4 MHz fcp = 4 MHz 5 10 0 fcp = 2 MHz fcp = 2 MHz 2.0 3.0 4.0 5.0 6.0 0 7.0 2.0 3.0 4.0 VCC [V] ICTS – VCC 800 5.0 6.0 7.0 VCC [V] ICCH – VCC (TA =˚C) 20 fcp = 18 700 (TA =˚C) 16 600 14 500 12 fcp = 400 10 300 8 6 200 4 100 2 0 2.0 3.0 4.0 5.0 6.0 0 7.0 VCC [V] 2.0 3.0 4.0 5.0 6.0 7.0 VCC [V] 13. Ordering Information Part number Package MB90594GPF MB90F594GPF MB90F591GPF MB90591GPF 100-pin Plastic QFP (PQH100) MB90V590GCR 256-pin Ceramic PGA Remarks   Document Number: 002-07698 Rev. *B For evaluation Page 52 of 55 MB90590G Series 14. Package Dimension Package Type Package Code QFP 100 PQH100 D D1 4 5 7 80 51 51 81 50 80 50 81 31 100 E1 E 5 7 6 3 4 31 100 1 30 e 3 0.40 C A-B D 30 2 5 7 1 0.20 C A-B D b 0.13 C A-B D BOTTOM VIEW 8 TOP VIEW 2 θ 9 A A' SEATING PLANE L2 c 10 b 0.10 C SECTION A-A' DETAIL A SIDE VIEW SYMBOL DIMENSIONS MIN. NOM. MAX. A1 0.05 0.45 b 0.27 c 0.11 A 3.35 0.32 D 23.90 BSC D1 20.00 BSC e 0.65 BSC E 17.90 BSC E1 θ L 0.37 0.23 14.00 BSC 0° 0.73 8° 0.88 L1 1.95 REF L2 0.25 BSC 1.03 PACKAGE OUTLINE, 100 LEAD QFP 20.00X14.00X3.35 MM PQH100 REV** Document Number: 002-07698 Rev. *B 002-15156 ** Page 53 of 55 MB90590G Series 15. Major Changes Spansion Publication Number: DS07-13704-6E Section Change Results  Deleted the part numbers. MB90591, MB90F591A, MB90594, MB90F594A, MB90V590A  Changed the series name. MB90590/590G series MB90590G series  Changed the following name. I/O Timer 16-bit Free-run Timer  Peripheral Resource name is changed. Clock Timer Watch Timer  one of Standby mode name is changed. Clock mode Watch mode BLOCK DIAGRAM Changed the number of channels of 16-bit output compare. 4 ch 6 ch INTERRUPT MAP Changed the abbreviation of Extended Intelligent I/O Service. ELECTRICAL CHARACTERISTICS 5. A/D Converter Changed the items of “Zero transition voltage” and “Full scale transition voltage”. mV V I2OS EI2OS NOTE: Please see “Document History” about later revised information. Document History Document Title: F2MC-16LX MB90590G Series CMOS 16-bit Proprietary Microcontroller Document Number: 002-07698 Orig. of Change Submission Date AKIH 10/01/2008 Migrated to Cypress and assigned document number 002-07698. No change to document contents or format. 5537127 AKIH 11/30/2016 Updated to Cypress template 6059031 TORS 02/06/2018 Adapted new Cypress logo Updated following package code FPT-100P-M06 → PQH100 Revision ECN **  *A *B Document Number: 002-07698 Rev. *B Description of Change Page 54 of 55 MB90590G Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC®Solutions Products Arm® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2008-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach, such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-07698 Rev. *B Revised February 6, 2018 Page 55 of 55